xref: /illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_dfclib.h (revision 8f23e9fa)

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at
 * http://www.opensource.org/licenses/cddl1.txt.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2004-2011 Emulex. All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _EMLXS_DFCLIB_H
#define	_EMLXS_DFCLIB_H

#ifdef	__cplusplus
extern "C" {
#endif

#define	MAX_DFC_EVENTS			16
#define	MAX_EMLXS_BRDS			128
#define	MAX_CFG_PARAM 			64
#define	MAX_NODES 				4096

#ifndef MAX_VPORTS
#define	MAX_VPORTS			256
#endif  /* MAX_VPORTS */

#ifdef EMLXS_SPARC
#define	EMLXS_BIG_ENDIAN
#endif	/* EMLXS_SPARC */

#ifdef EMLXS_I386
#define	EMLXS_LITTLE_ENDIAN
#endif	/* EMLXS_I386 */


typedef struct brdinfo
{
	uint32_t a_mem_hi;	/* memory identifier for adapter access */
	uint32_t a_mem_low;	/* memory identifier for adapter access */
	uint32_t a_flash_hi;	/* memory identifier for adapter access */
	uint32_t a_flash_low;	/* memory identifier for adapter access */
	uint32_t a_ctlreg_hi;	/* memory identifier for adapter access */
	uint32_t a_ctlreg_low;	/* memory identifier for adapter access */
	uint32_t a_intrlvl;	/* interrupt level for adapter */
	uint32_t a_pci;		/* PCI identifier (device / vendor id) */
	uint32_t a_busid;	/* identifier of PCI bus adapter is on */
	uint32_t a_devid;	/* identifier of PCI device number */
	uint8_t  a_rsvd1;	/* reserved for future use */
	uint8_t  a_rsvd2;	/* reserved for future use */
	uint8_t  a_siglvl;	/* signal handler used by library */
	uint8_t  a_ddi;		/* identifier device driver instance number */
	uint32_t a_onmask;	/* mask of ONDI primatives supported */
	uint32_t a_offmask;	/* mask of OFFDI primatives supported */
	uint8_t  a_drvrid[16];	/* driver version */
	uint8_t  a_fwname[32];	/* firmware version */
} brdinfo_t;


typedef struct dfc_brdinfo
{
	uint32_t a_mem_hi;	/* memory identifier for adapter access */
	uint32_t a_mem_low;	/* memory identifier for adapter access */
	uint32_t a_flash_hi;	/* memory identifier for adapter access */
	uint32_t a_flash_low;	/* memory identifier for adapter access */
	uint32_t a_ctlreg_hi;	/* memory identifier for adapter access */
	uint32_t a_ctlreg_low;	/* memory identifier for adapter access */
	uint32_t a_intrlvl;	/* interrupt level for adapter */
	uint32_t a_pci;		/* PCI identifier (device / vendor id) */
	uint32_t a_busid;	/* identifier of PCI bus adapter is on */
	uint32_t a_devid;	/* identifier of PCI device number */
	uint8_t  a_pciFunc;	/* identifier of PCI function number */
	uint8_t  a_siglvl;	/* signal handler used by library */
	uint16_t a_ddi;		/* identifier device driver instance number */
	uint32_t a_onmask;	/* mask of ONDI primatives supported */
	uint32_t a_offmask;	/* mask of OFFDI primatives supported */
	uint8_t  a_drvrid[16];	/* driver version */
	uint8_t  a_fwname[32];	/* firmware version */
	uint8_t  a_wwpn[8];	/* worldwide portname */
} dfc_brdinfo_t;


#define	PADDR_LO(addr)	((uint32_t)(((uint64_t)(addr)) & 0xffffffff))
#define	PADDR_HI(addr)	((uint32_t)(((uint64_t)(addr)) >> 32))
#define	PADDR(high, low)	((uint64_t)((((uint64_t)(high)) << 32) \
					| (((uint64_t)(low)) & 0xffffffff)))

typedef struct ulp_bde
{
	uint32_t	bdeAddress;

#ifdef EMLXS_BIG_ENDIAN
	uint32_t	bdeReserved:4;
	uint32_t	bdeAddrHigh:4;
	uint32_t	bdeSize:24;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	bdeSize:24;
	uint32_t	bdeAddrHigh:4;
	uint32_t	bdeReserved:4;
#endif
} ulp_bde_t;

typedef struct ulp_bde64
{
	union
	{
		uint32_t	w;
		struct
		{
#ifdef EMLXS_BIG_ENDIAN
			uint32_t	bdeFlags:8;
			uint32_t	bdeSize:24;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
			uint32_t	bdeSize:24;
			uint32_t	bdeFlags:8;
#endif

#define	BUFF_USE_RSVD		0x01 /* bdeFlags */
#define	BUFF_USE_INTRPT		0x02 /* Not Implemented with LP6000 */
#define	BUFF_USE_CMND		0x04 /* Optional, 1=cmd/rsp 0=data buffer */
#define	BUFF_USE_RCV		0x08 /* ""  "",  1=rcv buffer, 0=xmit buffer */
#define	BUFF_TYPE_32BIT		0x10 /* ""  "",  1=32 bit addr 0=64 bit addr */
#define	BUFF_TYPE_SPECIAL	0x20 /* Not Implemented with LP6000  */
#define	BUFF_TYPE_BDL		0x40 /* Optional,  may be set in BDL */
#define	BUFF_TYPE_INVALID	0x80 /* ""  "" */
		} f;
	} tus;

	uint32_t	addrLow;
	uint32_t	addrHigh;
} ulp_bde64_t;


/* ==== Mailbox Commands ==== */
#define	MBX_SHUTDOWN		0x00
#define	MBX_LOAD_SM		0x01
#define	MBX_READ_NV		0x02
#define	MBX_WRITE_NV		0x03
#define	MBX_RUN_BIU_DIAG	0x04
#define	MBX_INIT_LINK		0x05
#define	MBX_DOWN_LINK		0x06
#define	MBX_CONFIG_LINK		0x07
#define	MBX_PART_SLIM		0x08
#define	MBX_CONFIG_RING		0x09
#define	MBX_RESET_RING		0x0A
#define	MBX_READ_CONFIG		0x0B
#define	MBX_READ_RCONFIG	0x0C
#define	MBX_READ_SPARM		0x0D
#define	MBX_READ_STATUS		0x0E
#define	MBX_READ_RPI		0x0F
#define	MBX_READ_XRI		0x10
#define	MBX_READ_REV		0x11
#define	MBX_READ_LNK_STAT	0x12
#define	MBX_REG_LOGIN		0x13
#define	MBX_UNREG_LOGIN		0x14
#define	MBX_READ_LA		0x15
#define	MBX_CLEAR_LA		0x16
#define	MBX_DUMP_MEMORY		0x17
#define	MBX_DUMP_CONTEXT	0x18
#define	MBX_RUN_DIAGS		0x19
#define	MBX_RESTART		0x1A
#define	MBX_UPDATE_CFG		0x1B
#define	MBX_DOWN_LOAD		0x1C
#define	MBX_DEL_LD_ENTRY	0x1D
#define	MBX_RUN_PROGRAM		0x1E
#define	MBX_SET_MASK		0x20
#define	MBX_SET_SLIM		0x21
#define	MBX_UNREG_D_ID		0x23
#define	MBX_KILL_BOARD		0x24
#define	MBX_CONFIG_FARP		0x25
#define	MBX_WRITE_VPARMS	0x32
#define	MBX_LOAD_AREA		0x81
#define	MBX_RUN_BIU_DIAG64	0x84
#define	MBX_CONFIG_PORT		0x88
#define	MBX_READ_SPARM64	0x8D
#define	MBX_READ_RPI64		0x8F
#define	MBX_CONFIG_MSI		0x90
#define	MBX_REG_LOGIN64		0x93
#define	MBX_READ_LA64		0x95
#define	MBX_FLASH_WR_ULA	0x98
#define	MBX_SET_DEBUG		0x99
#define	MBX_SLI_CONFIG		0x9B
#define	MBX_LOAD_EXP_ROM	0x9C
#define	MBX_REQUEST_FEATURES	0x9D
#define	MBX_RESUME_RPI		0x9E
#define	MBX_REG_VFI		0x9F
#define	MBX_REG_FCFI		0xA0
#define	MBX_UNREG_VFI		0xA1
#define	MBX_UNREG_FCFI		0xA2
#define	MBX_INIT_VFI		0xA3
#define	MBX_INIT_VPI		0xA4
#define	MBX_ACCESS_VDATA	0xA5
#define	MBX_MAX_CMDS		0xA6
#define	MBX_SLI2_CMD_MASK	0x80


typedef struct read_sparm_var
{
	uint32_t	rsvd1;
	uint32_t	rsvd2;
	union
	{
		ulp_bde_t	sp;
		ulp_bde64_t	sp64;
	} un;
} read_sparm_var_t;


typedef struct read_rev_var
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	cv:1;
	uint32_t	rr:1;
	uint32_t	rsvd1:29;
	uint32_t	rv:1;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	rv:1;
	uint32_t	rsvd1:29;
	uint32_t	rr:1;
	uint32_t	cv:1;
#endif
	uint32_t	biuRev;
	uint32_t	smRev;
	union
	{
		uint32_t	smFwRev;
		struct
		{
#ifdef EMLXS_BIG_ENDIAN
			uint8_t		ProgType;
			uint8_t		ProgId;
			uint16_t	ProgVer:4;
			uint16_t	ProgRev:4;
			uint16_t	ProgFixLvl:2;
			uint16_t	ProgDistType:2;
			uint16_t	DistCnt:4;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
			uint16_t	DistCnt:4;
			uint16_t	ProgDistType:2;
			uint16_t	ProgFixLvl:2;
			uint16_t	ProgRev:4;
			uint16_t	ProgVer:4;
			uint8_t		ProgId;
			uint8_t		ProgType;
#endif
		} b;
	} un;
	uint32_t	endecRev;

#ifdef EMLXS_BIG_ENDIAN
	uint8_t		feaLevelHigh;
	uint8_t		feaLevelLow;
	uint8_t		fcphHigh;
	uint8_t		fcphLow;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		fcphLow;
	uint8_t		fcphHigh;
	uint8_t		feaLevelLow;
	uint8_t		feaLevelHigh;
#endif
	uint32_t	postKernRev;
	uint32_t	opFwRev;
	uint8_t		opFwName[16];
	uint32_t	sli1FwRev;
	uint8_t		sli1FwName[16];
	uint32_t	sli2FwRev;
	uint8_t		sli2FwName[16];
} read_rev_var_t;


typedef struct dump_var
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	rsvd:25;
	uint32_t	ra:1;
	uint32_t	co:1;
	uint32_t	cv:1;
	uint32_t	type:4;

	uint32_t	entry_index:16;
	uint32_t	region_id:16;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	type:4;
	uint32_t	cv:1;
	uint32_t	co:1;
	uint32_t	ra:1;
	uint32_t	rsvd:25;

	uint32_t	region_id:16;
	uint32_t	entry_index:16;
#endif
	uint32_t	base_adr;
	uint32_t	word_cnt;
	uint32_t	resp_offset;
} dump_var_t;


typedef struct dump4_var
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	link:8;
	uint32_t	rsvd:20;
	uint32_t	type:4;

	uint32_t	entry_index:16;
	uint32_t	region_id:16;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	type:4;
	uint32_t	rsvd:20;
	uint32_t	link:8;

	uint32_t	region_id:16;
	uint32_t	entry_index:16;
#endif
	uint32_t	available_cnt;
	uint32_t	addrLow;
	uint32_t	addrHigh;
	uint32_t	rsp_cnt;
} dump4_var_t;


typedef struct update_cfg
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	rsvd2:16;
	uint32_t	proc_type:8;
	uint32_t	rsvd1:1;
	uint32_t	Abit:1;
	uint32_t	DIbit:1;
	uint32_t	Vbit:1;
	uint32_t	req_type:4;
#define	INIT_REGION	1
#define	UPDATE_DATA	2
#define	CLEAN_UP_CFG	3
	uint32_t	entry_len:16;
	uint32_t	region_id:16;
#endif

#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	req_type:4;
#define	INIT_REGION	1
#define	UPDATE_DATA	2
#define	CLEAN_UP_CFG	3
	uint32_t	Vbit:1;
	uint32_t	DIbit:1;
	uint32_t	Abit:1;
	uint32_t	rsvd1:1;
	uint32_t	proc_type:8;
	uint32_t	rsvd2:16;

	uint32_t	region_id:16;
	uint32_t	entry_len:16;
#endif

	uint32_t	rsp_info;
	uint32_t	byte_len;
	uint32_t	cfg_data;
} update_cfg_var_t;



typedef struct
{
	union {
		struct {
#ifdef EMLXS_BIG_ENDIAN
			uint8_t domain;
			uint8_t port_number;
			uint8_t subsystem;
			uint8_t opcode;
#else
			uint8_t opcode;
			uint8_t subsystem;
			uint8_t port_number;
			uint8_t domain;
#endif
			uint32_t timeout;
			uint32_t request_length;
			uint32_t rsvd0;
		}req;

		struct {
#ifdef EMLXS_BIG_ENDIAN
			/* dw 0 */
			uint8_t domain;
			uint8_t rsvd0;
			uint8_t subsystem;
			uint8_t opcode;

			/* dw 1 */
			uint16_t rsvd1;
			uint8_t additional_status;
			uint8_t status;
#else
			/* dw 0 */
			uint8_t opcode;
			uint8_t subsystem;
			uint8_t rsvd0;
			uint8_t domain;

			/* dw 1 */
			uint8_t status;
			uint8_t additional_status;
			uint16_t rsvd1;
#endif

			uint32_t rsp_length;
			uint32_t actual_rsp_length;
		}rsp;
		uint32_t dw[4];
	}u0;
} common_hdr_t;

typedef struct get_oem_attrs
{
	common_hdr_t hdr;
	union {
		struct {
			uint32_t rsvd0;
		}req;

		struct {
			uint8_t emulex_serial_number[12];
			uint8_t oem_serial_number[24];
			uint32_t oem_personality_mgmt_word;
#ifdef EMLXS_BIG_ENDIAN
			uint8_t rsvd[3];
			uint8_t oem_current_personality;
#else
			uint8_t oem_current_personality;
			uint8_t rsvd[3];
#endif

		}rsp;
	}params;

} get_oem_attrs_t;


typedef struct read_write_flashrom {
	common_hdr_t hdr;
	uint32_t	flash_op_code;
	uint32_t	flash_op_type;
	uint32_t	data_buffer_size;
	uint32_t	data_offset;
	uint8_t		data_buffer[4];
} read_write_flashrom_t;


typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	special:8;		/* word 1 */
	uint32_t	reserved2:16;		/* word 1 */
	uint32_t	sge_cnt:5;		/* word 1 */
	uint32_t	reserved1:2;		/* word 1 */
	uint32_t	embedded:1;		/* word 1 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	embedded:1;		/* word 1 */
	uint32_t	reserved1:2;		/* word 1 */
	uint32_t	sge_cnt:5;		/* word 1 */
	uint32_t	reserved2:16;		/* word 1 */
	uint32_t	special:8;		/* word 1 */
#endif
	uint32_t	payload_length;		/* word 2 */
	uint32_t	tag_low;		/* word 3 */
	uint32_t	tag_hi;			/* word 4 */
	uint32_t	reserved3;		/* word 5 */

} be_req_header_t;

typedef struct
{
	be_req_header_t	be;

	union
	{
		get_oem_attrs_t		varOemAttrs;
		read_write_flashrom_t	varFlashRom;
	} un;

} sli_config_var_t;


typedef struct read_cfg_var
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	cr:1;
	uint32_t	ci:1;
	uint32_t	cr_delay:6;
	uint32_t	cr_count:8;
	uint32_t	InitBBC: