1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_DFCLIB_H 28 #define _EMLXS_DFCLIB_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define MAX_DFC_EVENTS 16 35 #define MAX_EMLXS_BRDS 128 36 #define MAX_CFG_PARAM 64 37 #define MAX_NODES 4096 38 39 #ifndef MAX_VPORTS 40 #define MAX_VPORTS 256 41 #endif /* MAX_VPORTS */ 42 43 #ifdef EMLXS_SPARC 44 #define EMLXS_BIG_ENDIAN 45 #endif /* EMLXS_SPARC */ 46 47 #ifdef EMLXS_I386 48 #define EMLXS_LITTLE_ENDIAN 49 #endif /* EMLXS_I386 */ 50 51 52 typedef struct brdinfo 53 { 54 uint32_t a_mem_hi; /* memory identifier for adapter access */ 55 uint32_t a_mem_low; /* memory identifier for adapter access */ 56 uint32_t a_flash_hi; /* memory identifier for adapter access */ 57 uint32_t a_flash_low; /* memory identifier for adapter access */ 58 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 59 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 60 uint32_t a_intrlvl; /* interrupt level for adapter */ 61 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 62 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 63 uint32_t a_devid; /* identifier of PCI device number */ 64 uint8_t a_rsvd1; /* reserved for future use */ 65 uint8_t a_rsvd2; /* reserved for future use */ 66 uint8_t a_siglvl; /* signal handler used by library */ 67 uint8_t a_ddi; /* identifier device driver instance number */ 68 uint32_t a_onmask; /* mask of ONDI primatives supported */ 69 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 70 uint8_t a_drvrid[16]; /* driver version */ 71 uint8_t a_fwname[32]; /* firmware version */ 72 } brdinfo_t; 73 74 75 typedef struct dfc_brdinfo 76 { 77 uint32_t a_mem_hi; /* memory identifier for adapter access */ 78 uint32_t a_mem_low; /* memory identifier for adapter access */ 79 uint32_t a_flash_hi; /* memory identifier for adapter access */ 80 uint32_t a_flash_low; /* memory identifier for adapter access */ 81 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 82 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 83 uint32_t a_intrlvl; /* interrupt level for adapter */ 84 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 85 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 86 uint32_t a_devid; /* identifier of PCI device number */ 87 uint8_t a_pciFunc; /* identifier of PCI function number */ 88 uint8_t a_siglvl; /* signal handler used by library */ 89 uint16_t a_ddi; /* identifier device driver instance number */ 90 uint32_t a_onmask; /* mask of ONDI primatives supported */ 91 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 92 uint8_t a_drvrid[16]; /* driver version */ 93 uint8_t a_fwname[32]; /* firmware version */ 94 uint8_t a_wwpn[8]; /* worldwide portname */ 95 } dfc_brdinfo_t; 96 97 98 #define PADDR_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xffffffff)) 99 #define PADDR_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 100 #define PADDR(high, low) ((uint64_t)((((uint64_t)(high)) << 32) \ 101 | (((uint64_t)(low)) & 0xffffffff))) 102 103 typedef struct ulp_bde 104 { 105 uint32_t bdeAddress; 106 107 #ifdef EMLXS_BIG_ENDIAN 108 uint32_t bdeReserved:4; 109 uint32_t bdeAddrHigh:4; 110 uint32_t bdeSize:24; 111 #endif 112 #ifdef EMLXS_LITTLE_ENDIAN 113 uint32_t bdeSize:24; 114 uint32_t bdeAddrHigh:4; 115 uint32_t bdeReserved:4; 116 #endif 117 } ulp_bde_t; 118 119 typedef struct ulp_bde64 120 { 121 union 122 { 123 uint32_t w; 124 struct 125 { 126 #ifdef EMLXS_BIG_ENDIAN 127 uint32_t bdeFlags:8; 128 uint32_t bdeSize:24; 129 #endif 130 #ifdef EMLXS_LITTLE_ENDIAN 131 uint32_t bdeSize:24; 132 uint32_t bdeFlags:8; 133 #endif 134 135 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 136 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 137 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 138 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit buffer */ 139 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit addr */ 140 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 141 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 142 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 143 } f; 144 } tus; 145 146 uint32_t addrLow; 147 uint32_t addrHigh; 148 } ulp_bde64_t; 149 150 151 /* ==== Mailbox Commands ==== */ 152 #define MBX_SHUTDOWN 0x00 153 #define MBX_LOAD_SM 0x01 154 #define MBX_READ_NV 0x02 155 #define MBX_WRITE_NV 0x03 156 #define MBX_RUN_BIU_DIAG 0x04 157 #define MBX_INIT_LINK 0x05 158 #define MBX_DOWN_LINK 0x06 159 #define MBX_CONFIG_LINK 0x07 160 #define MBX_PART_SLIM 0x08 161 #define MBX_CONFIG_RING 0x09 162 #define MBX_RESET_RING 0x0A 163 #define MBX_READ_CONFIG 0x0B 164 #define MBX_READ_RCONFIG 0x0C 165 #define MBX_READ_SPARM 0x0D 166 #define MBX_READ_STATUS 0x0E 167 #define MBX_READ_RPI 0x0F 168 #define MBX_READ_XRI 0x10 169 #define MBX_READ_REV 0x11 170 #define MBX_READ_LNK_STAT 0x12 171 #define MBX_REG_LOGIN 0x13 172 #define MBX_UNREG_LOGIN 0x14 173 #define MBX_READ_LA 0x15 174 #define MBX_CLEAR_LA 0x16 175 #define MBX_DUMP_MEMORY 0x17 176 #define MBX_DUMP_CONTEXT 0x18 177 #define MBX_RUN_DIAGS 0x19 178 #define MBX_RESTART 0x1A 179 #define MBX_UPDATE_CFG 0x1B 180 #define MBX_DOWN_LOAD 0x1C 181 #define MBX_DEL_LD_ENTRY 0x1D 182 #define MBX_RUN_PROGRAM 0x1E 183 #define MBX_SET_MASK 0x20 184 #define MBX_SET_SLIM 0x21 185 #define MBX_UNREG_D_ID 0x23 186 #define MBX_KILL_BOARD 0x24 187 #define MBX_CONFIG_FARP 0x25 188 #define MBX_WRITE_VPARMS 0x32 189 #define MBX_LOAD_AREA 0x81 190 #define MBX_RUN_BIU_DIAG64 0x84 191 #define MBX_CONFIG_PORT 0x88 192 #define MBX_READ_SPARM64 0x8D 193 #define MBX_READ_RPI64 0x8F 194 #define MBX_CONFIG_MSI 0x90 195 #define MBX_REG_LOGIN64 0x93 196 #define MBX_READ_LA64 0x95 197 #define MBX_FLASH_WR_ULA 0x98 198 #define MBX_SET_DEBUG 0x99 199 #define MBX_LOAD_EXP_ROM 0x9C 200 #define MBX_REQUEST_FEATURES 0x9D 201 #define MBX_RESUME_RPI 0x9E 202 #define MBX_REG_VFI 0x9F 203 #define MBX_REG_FCFI 0xA0 204 #define MBX_UNREG_VFI 0xA1 205 #define MBX_UNREG_FCFI 0xA2 206 #define MBX_INIT_VFI 0xA3 207 #define MBX_INIT_VPI 0xA4 208 #define MBX_ACCESS_VDATA 0xA5 209 #define MBX_MAX_CMDS 0xA6 210 #define MBX_SLI2_CMD_MASK 0x80 211 212 213 typedef struct read_sparm_var 214 { 215 uint32_t rsvd1; 216 uint32_t rsvd2; 217 union 218 { 219 ulp_bde_t sp; 220 ulp_bde64_t sp64; 221 } un; 222 } read_sparm_var_t; 223 224 225 typedef struct read_rev_var 226 { 227 #ifdef EMLXS_BIG_ENDIAN 228 uint32_t cv:1; 229 uint32_t rr:1; 230 uint32_t rsvd1:29; 231 uint32_t rv:1; 232 #endif 233 #ifdef EMLXS_LITTLE_ENDIAN 234 uint32_t rv:1; 235 uint32_t rsvd1:29; 236 uint32_t rr:1; 237 uint32_t cv:1; 238 #endif 239 uint32_t biuRev; 240 uint32_t smRev; 241 union 242 { 243 uint32_t smFwRev; 244 struct 245 { 246 #ifdef EMLXS_BIG_ENDIAN 247 uint8_t ProgType; 248 uint8_t ProgId; 249 uint16_t ProgVer:4; 250 uint16_t ProgRev:4; 251 uint16_t ProgFixLvl:2; 252 uint16_t ProgDistType:2; 253 uint16_t DistCnt:4; 254 #endif 255 #ifdef EMLXS_LITTLE_ENDIAN 256 uint16_t DistCnt:4; 257 uint16_t ProgDistType:2; 258 uint16_t ProgFixLvl:2; 259 uint16_t ProgRev:4; 260 uint16_t ProgVer:4; 261 uint8_t ProgId; 262 uint8_t ProgType; 263 #endif 264 } b; 265 } un; 266 uint32_t endecRev; 267 268 #ifdef EMLXS_BIG_ENDIAN 269 uint8_t feaLevelHigh; 270 uint8_t feaLevelLow; 271 uint8_t fcphHigh; 272 uint8_t fcphLow; 273 #endif 274 #ifdef EMLXS_LITTLE_ENDIAN 275 uint8_t fcphLow; 276 uint8_t fcphHigh; 277 uint8_t feaLevelLow; 278 uint8_t feaLevelHigh; 279 #endif 280 uint32_t postKernRev; 281 uint32_t opFwRev; 282 uint8_t opFwName[16]; 283 uint32_t sli1FwRev; 284 uint8_t sli1FwName[16]; 285 uint32_t sli2FwRev; 286 uint8_t sli2FwName[16]; 287 } read_rev_var_t; 288 289 290 typedef struct dump_var 291 { 292 #ifdef EMLXS_BIG_ENDIAN 293 uint32_t rsvd:25; 294 uint32_t ra:1; 295 uint32_t co:1; 296 uint32_t cv:1; 297 uint32_t type:4; 298 299 uint32_t entry_index:16; 300 uint32_t region_id:16; 301 #endif 302 #ifdef EMLXS_LITTLE_ENDIAN 303 uint32_t type:4; 304 uint32_t cv:1; 305 uint32_t co:1; 306 uint32_t ra:1; 307 uint32_t rsvd:25; 308 309 uint32_t region_id:16; 310 uint32_t entry_index:16; 311 #endif 312 uint32_t base_adr; 313 uint32_t word_cnt; 314 uint32_t resp_offset; 315 } dump_var_t; 316 317 318 typedef struct dump4_var 319 { 320 #ifdef EMLXS_BIG_ENDIAN 321 uint32_t link:8; 322 uint32_t rsvd:20; 323 uint32_t type:4; 324 325 uint32_t entry_index:16; 326 uint32_t region_id:16; 327 #endif 328 #ifdef EMLXS_LITTLE_ENDIAN 329 uint32_t type:4; 330 uint32_t rsvd:20; 331 uint32_t link:8; 332 333 uint32_t region_id:16; 334 uint32_t entry_index:16; 335 #endif 336 uint32_t available_cnt; 337 uint32_t addrLow; 338 uint32_t addrHigh; 339 uint32_t rsp_cnt; 340 } dump4_var_t; 341 342 343 typedef struct update_cfg 344 { 345 #ifdef EMLXS_BIG_ENDIAN 346 uint32_t rsvd2:16; 347 uint32_t proc_type:8; 348 uint32_t rsvd1:1; 349 uint32_t Abit:1; 350 uint32_t DIbit:1; 351 uint32_t Vbit:1; 352 uint32_t req_type:4; 353 #define INIT_REGION 1 354 #define UPDATE_DATA 2 355 #define CLEAN_UP_CFG 3 356 uint32_t entry_len:16; 357 uint32_t region_id:16; 358 #endif 359 360 #ifdef EMLXS_LITTLE_ENDIAN 361 uint32_t req_type:4; 362 #define INIT_REGION 1 363 #define UPDATE_DATA 2 364 #define CLEAN_UP_CFG 3 365 uint32_t Vbit:1; 366 uint32_t DIbit:1; 367 uint32_t Abit:1; 368 uint32_t rsvd1:1; 369 uint32_t proc_type:8; 370 uint32_t rsvd2:16; 371 372 uint32_t region_id:16; 373 uint32_t entry_len:16; 374 #endif 375 376 uint32_t rsp_info; 377 uint32_t byte_len; 378 uint32_t cfg_data; 379 } update_cfg_var_t; 380 381 382 typedef struct read_cfg_var 383 { 384 #ifdef EMLXS_BIG_ENDIAN 385 uint32_t cr:1; 386 uint32_t ci:1; 387 uint32_t cr_delay:6; 388 uint32_t cr_count:8; 389 uint32_t InitBBC:8; 390 uint32_t MaxBBC:8; 391 #endif 392 #ifdef EMLXS_LITTLE_ENDIAN 393 uint32_t MaxBBC:8; 394 uint32_t InitBBC:8; 395 uint32_t cr_count:8; 396 uint32_t cr_delay:6; 397 uint32_t ci:1; 398 uint32_t cr:1; 399 #endif 400 #ifdef EMLXS_BIG_ENDIAN 401 uint32_t topology:8; 402 uint32_t myDid:24; 403 #endif 404 #ifdef EMLXS_LITTLE_ENDIAN 405 uint32_t myDid:24; 406 uint32_t topology:8; 407 #endif 408 /* Defines for topology (defined previously) */ 409 #ifdef EMLXS_BIG_ENDIAN 410 uint32_t AR:1; 411 uint32_t IR:1; 412 uint32_t rsvd1:29; 413 uint32_t ack0:1; 414 #endif 415 #ifdef EMLXS_LITTLE_ENDIAN 416 uint32_t ack0:1; 417 uint32_t rsvd1:29; 418 uint32_t IR:1; 419 uint32_t AR:1; 420 #endif 421 uint32_t edtov; 422 uint32_t arbtov; 423 uint32_t ratov; 424 uint32_t rttov; 425 uint32_t altov; 426 uint32_t lmt; 427 428 #define LMT_1GB_CAPABLE 0x0004 429 #define LMT_2GB_CAPABLE 0x0008 430 #define LMT_4GB_CAPABLE 0x0040 431 #define LMT_8GB_CAPABLE 0x0080 432 #define LMT_10GB_CAPABLE 0x0100 433 434 uint32_t rsvd2; 435 uint32_t rsvd3; 436 uint32_t max_xri; 437 uint32_t max_iocb; 438 uint32_t max_rpi; 439 uint32_t avail_xri; 440 uint32_t avail_iocb; 441 uint32_t avail_rpi; 442 uint32_t default_rpi; 443 } read_cfg_var_t; 444 445 446 typedef struct read_log_var 447 { 448 #ifdef EMLXS_BIG_ENDIAN 449 uint32_t type:8; 450 uint32_t byte_count:8; 451 uint32_t write:1; 452 uint32_t resv:3; 453 uint32_t offset:12; 454 #endif 455 #ifdef EMLXS_LITTLE_ENDIAN 456 uint32_t offset:12; 457 uint32_t resv:3; 458 uint32_t write:1; 459 uint32_t byte_count:8; 460 uint32_t type:8; 461 #endif 462 463 uint32_t data; 464 } read_log_var_t; 465 466 467 typedef struct log_status_var 468 { 469 470 #ifdef EMLXS_BIG_ENDIAN 471 uint16_t split_log_next; 472 uint16_t log_next; 473 474 uint32_t size; 475 476 uint32_t format:8; 477 uint32_t resv2:22; 478 uint32_t log_level:1; 479 uint32_t split_log:1; 480 #endif 481 #ifdef EMLXS_LITTLE_ENDIAN 482 uint16_t log_next; 483 uint16_t split_log_next; 484 485 uint32_t size; 486 487 uint32_t split_log:1; 488 uint32_t log_level:1; 489 uint32_t resv2:22; 490 uint32_t format:8; 491 #endif 492 493 uint32_t offset; 494 } log_status_var_t; 495 496 497 typedef struct read_evt_log_var 498 { 499 #ifdef EMLXS_BIG_ENDIAN 500 uint32_t read_log:1; 501 uint32_t clear_log:1; 502 uint32_t mbox_rsp:1; 503 uint32_t resv:28; 504 #endif 505 #ifdef EMLXS_LITTLE_ENDIAN 506 uint32_t resv:28; 507 uint32_t mbox_rsp:1; 508 uint32_t clear_log:1; 509 uint32_t read_log:1; 510 #endif 511 512 uint32_t offset; 513 514 union 515 { 516 ulp_bde_t sp; 517 ulp_bde64_t sp64; 518 } un; 519 } read_evt_log_var_t; 520 521 522 typedef struct dfc_mailbox 523 { 524 #ifdef EMLXS_BIG_ENDIAN 525 uint16_t mbxStatus; 526 uint8_t mbxCommand; 527 uint8_t mbxReserved:6; 528 uint8_t mbxHc:1; 529 uint8_t mbxOwner:1; /* Low order bit first word */ 530 #endif 531 #ifdef EMLXS_LITTLE_ENDIAN 532 uint8_t mbxOwner:1; /* Low order bit first word */ 533 uint8_t mbxHc:1; 534 uint8_t mbxReserved:6; 535 uint8_t mbxCommand; 536 uint16_t mbxStatus; 537 #endif 538 539 union 540 { 541 uint32_t varWords[31]; 542 read_sparm_var_t varRdSparm; 543 read_rev_var_t varRdRev; 544 read_cfg_var_t varRdCfg; 545 dump_var_t varDmp; 546 read_log_var_t varRdLog; 547 log_status_var_t varLogStat; 548 read_evt_log_var_t varRdEvtLog; 549 550 } un; 551 } dfc_mailbox_t; 552 553 554 typedef struct dfc_mailbox4 555 { 556 #ifdef EMLXS_BIG_ENDIAN 557 uint16_t mbxStatus; 558 uint8_t mbxCommand; 559 uint8_t mbxReserved:6; 560 uint8_t mbxHc:1; 561 uint8_t mbxOwner:1; /* Low order bit first word */ 562 #endif 563 #ifdef EMLXS_LITTLE_ENDIAN 564 uint8_t mbxOwner:1; /* Low order bit first word */ 565 uint8_t mbxHc:1; 566 uint8_t mbxReserved:6; 567 uint8_t mbxCommand; 568 uint16_t mbxStatus; 569 #endif 570 571 union 572 { 573 uint32_t varWords[63]; 574 dump4_var_t varDmp; 575 update_cfg_var_t varUpdateCfg; 576 } un; 577 } dfc_mailbox4_t; 578 579 580 /* Config Region 23 Records */ 581 582 typedef struct tlv_fcoe { 583 uint8_t type; 584 uint8_t length; 585 uint8_t version; 586 #define TLV_FCOE_VER 1 587 588 uint8_t fip_flags; 589 #define TLV_FCOE_FIP 0x40 590 #define TLV_FCOE_VLAN 0x01 591 592 uint8_t FCMap[3]; 593 uint8_t reserved; 594 #ifdef EMLXS_BIG_ENDIAN 595 uint32_t rsvd:20; 596 uint32_t VLanId:12; 597 #endif 598 #ifdef EMLXS_LITTLE_ENDIAN 599 uint32_t VLanId:12; 600 uint32_t rsvd:20; 601 #endif 602 } tlv_fcoe_t; 603 604 605 typedef struct tlv_fcfconnectentry { 606 #ifdef EMLXS_BIG_ENDIAN 607 uint32_t rsvd1:4; 608 uint32_t VLanId:12; 609 uint32_t rsvd2:7; 610 uint32_t AddrMode:1; 611 uint32_t AddrModePreferred:1; 612 uint32_t AddrModeValid:1; 613 uint32_t VLanValid:1; 614 uint32_t SwitchNameValid:1; 615 uint32_t FabricNameValid:1; 616 uint32_t Primary:1; 617 uint32_t Boot:1; 618 uint32_t Valid:1; 619 #endif 620 #ifdef EMLXS_LITTLE_ENDIAN 621 uint32_t Valid:1; 622 uint32_t Boot:1; 623 uint32_t Primary:1; 624 uint32_t FabricNameValid:1; 625 uint32_t SwitchNameValid:1; 626 uint32_t VLanValid:1; 627 uint32_t AddrModeValid:1; 628 uint32_t AddrModePreferred:1; 629 uint32_t AddrMode:1; 630 uint32_t rsvd2:7; 631 uint32_t VLanId:12; 632 uint32_t rsvd1:4; 633 #endif 634 uint8_t FabricName[8]; 635 uint8_t SwitchName[8]; 636 } tlv_fcfconnectentry_t; 637 638 639 #define MAX_FCFCONNECTLIST_ENTRIES 16 640 typedef struct tlv_fcfconnectlist { 641 uint8_t type; 642 uint8_t length; 643 uint16_t rsvd; 644 tlv_fcfconnectentry_t entry[MAX_FCFCONNECTLIST_ENTRIES]; 645 } tlv_fcfconnectlist_t; 646 647 648 typedef struct dfc_ioinfo 649 { 650 uint32_t a_mboxCmd; /* mailbox commands issued */ 651 uint32_t a_mboxCmpl; /* mailbox commands completed */ 652 uint32_t a_mboxErr; /* mailbox commands completed, error status */ 653 uint32_t a_iocbCmd; /* iocb command ring issued */ 654 uint32_t a_iocbRsp; /* iocb rsp ring received */ 655 uint32_t a_adapterIntr; /* adapter interrupt events */ 656 uint32_t a_fcpCmd; /* FCP commands issued */ 657 uint32_t a_fcpCmpl; /* FCP command completions received */ 658 uint32_t a_fcpErr; /* FCP command completions errors */ 659 uint32_t a_seqXmit; /* IP xmit sequences sent */ 660 uint32_t a_seqRcv; /* IP sequences received */ 661 uint32_t a_bcastXmit; /* cnt of successful xmit bcast cmds issued */ 662 uint32_t a_bcastRcv; /* cnt of receive bcast cmds received */ 663 uint32_t a_elsXmit; /* cnt of successful ELS req cmds issued */ 664 uint32_t a_elsRcv; /* cnt of ELS request commands received */ 665 uint32_t a_RSCNRcv; /* cnt of RSCN commands received */ 666 uint32_t a_seqXmitErr; /* cnt of unsuccessful xmit bcast cmds issued */ 667 uint32_t a_elsXmitErr; /* cnt of unsuccessful ELS req cmds issued */ 668 uint32_t a_elsBufPost; /* cnt of ELS buffers posted to adapter */ 669 uint32_t a_ipBufPost; /* cnt of IP buffers posted to adapter */ 670 uint32_t a_cnt1; /* generic counter */ 671 uint32_t a_cnt2; /* generic counter */ 672 uint32_t a_cnt3; /* generic counter */ 673 uint32_t a_cnt4; /* generic counter */ 674 675 } dfc_ioinfo_t; 676 677 678 typedef struct dfc_linkinfo 679 { 680 uint32_t a_linkEventTag; 681 uint32_t a_linkUp; 682 uint32_t a_linkDown; 683 uint32_t a_linkMulti; 684 uint32_t a_DID; 685 uint8_t a_topology; 686 uint8_t a_linkState; 687 uint8_t a_alpa; 688 uint8_t a_alpaCnt; 689 uint8_t a_alpaMap[128]; 690 uint8_t a_wwpName[8]; 691 uint8_t a_wwnName[8]; 692 } dfc_linkinfo_t; 693 694 /* values for a_topology */ 695 #define LNK_LOOP 0x1 696 #define LNK_PUBLIC_LOOP 0x2 697 #define LNK_FABRIC 0x3 698 #define LNK_PT2PT 0x4 699 #define LNK_MENLO_MAINTENANCE 0x5 700 701 /* values for a_linkState */ 702 #define LNK_DOWN 0x1 703 #define LNK_UP 0x2 704 #define LNK_FLOGI 0x3 705 #define LNK_DISCOVERY 0x4 706 #define LNK_REDISCOVERY 0x5 707 #define LNK_READY 0x6 708 #define LNK_DOWN_PERSIST 0x7 709 710 711 typedef struct dfc_traceinfo 712 { 713 uint8_t a_event; 714 uint8_t a_cmd; 715 uint16_t a_status; 716 uint32_t a_information; 717 } dfc_traceinfo_t; 718 719 720 typedef struct dfc_cfgparam 721 { 722 char a_string[32]; 723 uint32_t a_low; 724 uint32_t a_hi; 725 uint32_t a_default; 726 uint32_t a_current; 727 uint16_t a_flag; 728 #define CFG_EXPORT 0x1 /* Export this parameter to end user */ 729 #define CFG_IGNORE 0x2 /* Ignore this parameter */ 730 #define CFG_APPLICABLE 0x4 /* Applicable to this HBA */ 731 #define CFG_COMMON 0x8 /* Common to all HBAs */ 732 733 uint16_t a_changestate; 734 #define CFG_REBOOT 0x0 /* Changes effective after system */ 735 /* reboot */ 736 #define CFG_DYMANIC 0x1 /* Changes effective immediately */ 737 #define CFG_RESTART 0x2 /* Changes effective after adapter */ 738 /* restart */ 739 #define CFG_LINKRESET 0x3 /* Changes effective after link reset */ 740 741 char a_help[80]; 742 } dfc_cfgparam_t; 743 744 745 746 typedef struct dfc_nodeinfo 747 { 748 uint16_t a_flag; 749 uint16_t a_state; 750 uint32_t a_did; 751 uint8_t a_wwpn[8]; 752 uint8_t a_wwnn[8]; 753 uint32_t a_targetid; 754 } dfc_nodeinfo_t; 755 756 /* Defines for a_state */ 757 #define NODE_UNUSED 0 /* unused NL_PORT entry */ 758 #define NODE_LIMBO 0x1 /* entry needs to hang around for wwpn / sid */ 759 #define NODE_LOGOUT 0x2 /* NL_PORT is not logged in - entry is cached */ 760 #define NODE_PLOGI 0x3 /* PLOGI was sent to NL_PORT */ 761 #define NODE_LOGIN 0x4 /* NL_PORT is logged in / login REG_LOGINed */ 762 #define NODE_PRLI 0x5 /* PRLI was sent to NL_PORT */ 763 #define NODE_ALLOC 0x6 /* NL_PORT is ready to initiate adapter I/O */ 764 #define NODE_SEED 0x7 /* seed scsi id bind in table */ 765 766 /* Defines for a_flag */ 767 #define NODE_RPI_XRI 0x1 /* creating xri for entry */ 768 #define NODE_REQ_SND 0x2 /* sent ELS request for this entry */ 769 #define NODE_ADDR_AUTH 0x4 /* Authenticating addr for this entry */ 770 #define NODE_RM_ENTRY 0x8 /* Remove this entry */ 771 #define NODE_FARP_SND 0x10 /* sent FARP request for this entry */ 772 #define NODE_FABRIC 0x20 /* this entry represents the Fabric */ 773 #define NODE_FCP_TARGET 0x40 /* this entry is an FCP target */ 774 #define NODE_IP_NODE 0x80 /* this entry is an IP node */ 775 #define NODE_DISC_START 0x100 /* start discovery on this entry */ 776 #define NODE_SEED_WWPN 0x200 /* Entry scsi id is seeded for WWPN */ 777 #define NODE_SEED_WWNN 0x400 /* Entry scsi id is seeded for WWNN */ 778 #define NODE_SEED_DID 0x800 /* Entry scsi id is seeded for DID */ 779 #define NODE_SEED_MASK 0xe00 /* mask for seeded flags */ 780 #define NODE_AUTOMAP 0x1000 /* This entry was automap'ed */ 781 #define NODE_NS_REMOVED 0x2000 /* This entry removed from NameServer */ 782 783 784 typedef struct dfc_vpd 785 { 786 uint32_t version; 787 #define DFC_VPD_VERSION 1 788 789 char ModelDescription[256]; /* VPD field V1 */ 790 char Model[80]; /* VPD field V2 */ 791 char ProgramType[256]; /* VPD field V3 */ 792 char PortNum[20]; /* VPD field V4 */ 793 } dfc_vpd_t; 794 795 typedef struct dfc_destid 796 { 797 uint32_t idType; /* 0 - wwpn, 1 - d_id */ 798 uint32_t d_id; 799 uint8_t wwpn[8]; 800 } dfc_destid_t; 801 802 803 typedef struct dfc_loopback 804 { 805 uint32_t bufSize; 806 uint8_t *XmitBuffer; 807 uint8_t *RcvBuffer; 808 } dfc_loopback_t; 809 810 811 typedef struct dfc_drvinfo 812 { 813 uint8_t drvInfoVer; /* Version of this structure */ 814 #define DFC_DRVINFO_VERSION2 0x02 815 #define DFC_DRVINFO_VERSION3 0x03 /* NPIV */ 816 #define DFC_DRVINFO_VERSION4 0x04 /* DHCHAP */ 817 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION3 818 819 #ifdef DHCHAP_SUPPORT 820 #undef DFC_DRVINFO_VERSION 821 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION4 822 #endif /* DHCHAP_SUPPORT */ 823 824 uint8_t drvType; 825 #define DFC_DRVINFO_SOLARIS 0x11 /* Solaris */ 826 #define DFC_DRVINFO_LEADVILLE 0x14 /* Solaris Leadville ULP */ 827 #define DFC_DRVINFO_COMSTAR 0x16 /* Solaris Comstar ULP */ 828 829 uint16_t reserved; 830 uint8_t rmLevel; /* Remote Management (HBAnyware) */ 831 /* Support Level */ 832 #define DFC_DRVINFO_RMLEVEL 0x02 /* HBAnyware v2.3 */ 833 834 uint8_t mpLevel; /* MultiPulse support Level */ 835 uint8_t hbaapiLevel; /* HBAAPI support level */ 836 #define DFC_DRVINFO_HBAAPI 0x01 /* HBAAPI v1.0 */ 837 838 uint8_t reserved1; 839 char drvVer[16]; /* Driver Version string */ 840 char drvName[8]; /* Driver Name */ 841 char ftrDrvVer[16]; /* Filter/IOCtl Driver Version string */ 842 char ftrDrvName[8]; /* Filter/IOCtl Driver Name */ 843 char ipDrvVer[16]; /* IP Driver/component Version string */ 844 char ipDrvName[8]; /* IP Driver/component Name */ 845 uint32_t d_id; 846 uint8_t wwpn[8]; 847 uint8_t wwnn[8]; 848 uint8_t hostname[32]; /* IP node hostname from uname -n */ 849 850 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION3) 851 uint32_t NPIVsupport; 852 #define DFC_DRVINFO_NPIV_DRV 0x00000001 853 #define DFC_DRVINFO_NPIV_MODS 0x00000002 854 #define DFC_DRVINFO_NPIV_PARMS 0x00000004 855 #define DFC_DRVINFO_NPIV_FW 0x00000008 856 857 #endif /* >= DFC_DRVINFO_VERSION3 */ 858 859 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION4) 860 uint32_t sliMode; 861 uint64_t featureList; 862 #define DFC_DRVINFO_FEATURE_DIAG 0x00000001 863 #define DFC_DRVINFO_FEATURE_MAPPING 0x00000002 864 #define DFC_DRVINFO_FEATURE_DHCHAP 0x00000004 865 #define DFC_DRVINFO_FEATURE_IKE 0x00000008 866 #define DFC_DRVINFO_FEATURE_NPIV 0x00000010 867 #define DFC_DRVINFO_FEATURE_RESET_WWN 0x00000020 868 #define DFC_DRVINFO_FEATURE_VOLATILE_WWN 0x00000040 869 #define DFC_DRVINFO_FEATURE_E2E_AUTH 0x00000080 870 #define DFC_DRVINFO_FEATURE_SAN_DIAG 0x00000100 871 #define DFC_DRVINFO_FEATURE_FCOE 0x00000200 872 #define DFC_DRVINFO_FEATURE_PERSISTLINK 0x00000400 873 #define DFC_DRVINFO_FEATURE_TARGET_MODE 0x00000800 874 875 #endif /* >= DFC_DRVINFO_VERSION4 */ 876 } dfc_drvinfo_t; 877 878 879 880 typedef struct dfc_regevent 881 { 882 uint32_t ppid; 883 uint32_t cpid; 884 885 uint32_t event; 886 uint32_t type; 887 uint32_t outsz; 888 void *ctx; 889 void (*func) (); 890 891 uint32_t cindex; /* Set only by child */ 892 uint32_t state; /* Set only by child */ 893 894 /* state */ 895 #define CHILD_UNKNOWN 0 896 #define CHILD_UNBORN 1 897 #define CHILD_ALIVE 2 898 #define CHILD_REGISTERED 3 899 #define CHILD_ASLEEP 4 900 #define CHILD_AWAKE 5 901 #define CHILD_DIED 6 902 903 uint32_t pindex; /* Set only by parent */ 904 uint32_t flags; /* Set only by parent */ 905 906 /* flags */ 907 #define EVENT_REGISTERED 0x01 908 #define EVENT_SERVICE_ACTIVE 0x02 909 910 #ifdef SAN_DIAG_SUPPORT 911 HBA_WWN portname; 912 #endif /* SAN_DIAG_SUPPORT */ 913 } dfc_regevent_t; 914 915 916 /* Defines for RegisterForEvent mask */ 917 #define FC_REG_LINK_EVENT 0x01 /* Register for link up/down */ 918 /* events */ 919 #define FC_REG_RSCN_EVENT 0x02 /* Register for RSCN events */ 920 #define FC_REG_CT_EVENT 0x04 /* Register for CT request */ 921 /* events */ 922 #define FC_REG_MULTIPULSE_EVENT 0x08 /* Register for MultiPulse */ 923 /* events */ 924 #define FC_REG_DUMP_EVENT 0x10 /* Register for Diagnostic */ 925 /* Dump events */ 926 #define FC_REG_TEMP_EVENT 0x20 /* Register for Temperature */ 927 /* events */ 928 #define FC_REG_VPORTRSCN_EVENT 0x40 /* Register for VPort RSCN */ 929 /* events */ 930 #ifdef SAN_DIAG_SUPPORT 931 #define FC_REG_SD_ELS_EVENT 0x1000 /* Register for SANDiag ELS */ 932 /* events */ 933 #define FC_REG_SD_FABRIC_EVENT 0x2000 /* Register for SANDiag */ 934 /* Fabric events */ 935 #define FC_REG_SD_SCSI_EVENT 0x4000 /* Register for SANDiag SCSI */ 936 /* events */ 937 #define FC_REG_SD_BOARD_EVENT 0x8000 /* Register for SANDiag Board */ 938 /* events */ 939 #endif /* SAN_DIAG_SUPPORT */ 940 #define FC_REG_FCOE_EVENT 0x80000000 /* (Unofficial) Register for */ 941 /* FCOE events */ 942 943 #define MAX_RSCN_PAYLOAD 1024 944 #define MAX_CT_PAYLOAD (1024*320) 945 946 /* Temperature event types */ 947 #define DFC_TEMP_CRITICAL 1 948 #define DFC_TEMP_WARNING 2 949 #define DFC_TEMP_SAFE 3 950 951 /* bits in a_onmask */ 952 #define ONDI_MBOX 0x1 /* allows non-destructive mailbox */ 953 /* commands */ 954 #define ONDI_IOINFO 0x2 /* supports retrieval of I/O info */ 955 #define ONDI_LNKINFO 0x4 /* supports retrieval of link info */ 956 #define ONDI_NODEINFO 0x8 /* supports retrieval of node info */ 957 #define ONDI_TRACEINFO 0x10 /* supports retrieval of trace info */ 958 #define ONDI_SETTRACE 0x20 /* supports configuration of trace */ 959 /* info */ 960 #define ONDI_SLI1 0x40 /* hardware supports SLI-1 interface */ 961 #define ONDI_SLI2 0x80 /* hardware supports SLI-2 interface */ 962 #define ONDI_BIG_ENDIAN 0x100 /* DDI interface is BIG Endian */ 963 #define ONDI_LTL_ENDIAN 0x200 /* DDI interface is LITTLE Endian */ 964 #define ONDI_RMEM 0x400 /* allows reading of adapter shared */ 965 /* memory */ 966 #define ONDI_RFLASH 0x800 /* allows reading of adapter flash */ 967 #define ONDI_RPCI 0x1000 /* allows reading of adapter pci */ 968 /* registers */ 969 #define ONDI_RCTLREG 0x2000 /* allows reading of adapter cntrol */ 970 /* registers */ 971 #define ONDI_CFGPARAM 0x4000 /* supports get/set configuration */ 972 /* parameters */ 973 #define ONDI_CT 0x8000 /* supports passthru CT interface */ 974 #define ONDI_HBAAPI 0x10000 /* supports HBA API interface */ 975 #define ONDI_SBUS 0x20000 /* supports SBUS adapter interface */ 976 977 /* bits in a_offmask */ 978 #define OFFDI_MBOX 0x1 /* allows all mailbox commands */ 979 #define OFFDI_RMEM 0x2 /* allows reading of adapter shared */ 980 /* memory */ 981 #define OFFDI_WMEM 0x4 /* allows writing of adapter shared */ 982 /* memory */ 983 #define OFFDI_RFLASH 0x8 /* allows reading of adapter flash */ 984 #define OFFDI_WFLASH 0x10 /* allows writing of adapter flash */ 985 #define OFFDI_RPCI 0x20 /* allows reading of adapter pci */ 986 /* registers */ 987 #define OFFDI_WPCI 0x40 /* allows writing of adapter pci */ 988 /* registers */ 989 #define OFFDI_RCTLREG 0x80 /* allows reading of adapter cntrol */ 990 /* registers */ 991 #define OFFDI_WCTLREG 0x100 /* allows writing of adapter cntrol */ 992 /* registers */ 993 #define OFFDI_OFFLINE 0x80000000 /* if set, adapter is in offline */ 994 /* state */ 995 996 997 #define DDI_SHOW 0x0 998 #define DDI_ONDI 0x1 999 #define DDI_OFFDI 0x2 1000 #define DDI_WARMDI 0x3 1001 #define DDI_DIAGDI 0x4 1002 1003 /* mbxStatus */ 1004 #define DFC_MBX_SUCCESS 0x00 1005 #define DFC_MBXERR_NUM_RINGS 0x01 1006 #define DFC_MBXERR_NUM_IOCBS 0x02 1007 #define DFC_MBXERR_IOCBS_EXCEEDED 0x03 1008 #define DFC_MBXERR_BAD_RING_NUMBER 0x04 1009 #define DFC_MBXERR_MASK_ENTRIES_RANGE 0x05 1010 #define DFC_MBXERR_MASKS_EXCEEDED 0x06 1011 #define DFC_MBXERR_BAD_PROFILE 0x07 1012 #define DFC_MBXERR_BAD_DEF_CLASS 0x08 1013 #define DFC_MBXERR_BAD_MAX_RESPONDER 0x09 1014 #define DFC_MBXERR_BAD_MAX_ORIGINATOR 0x0A 1015 #define DFC_MBXERR_RPI_REGISTERED 0x0B 1016 #define DFC_MBXERR_RPI_FULL 0x0C 1017 #define DFC_MBXERR_NO_RESOURCES 0x0D 1018 #define DFC_MBXERR_BAD_RCV_LENGTH 0x0E 1019 #define DFC_MBXERR_DMA_ERROR 0x0F 1020 #define DFC_MBXERR_ERROR 0x10 1021 1022 #define DFC_MBXERR_OVERTEMP_ERROR 0xFA 1023 #define DFC_MBXERR_HARDWARE_ERROR 0xFB 1024 #define DFC_MBXERR_DRVR_ERROR 0xFC 1025 #define DFC_MBXERR_BUSY 0xFD 1026 #define DFC_MBXERR_TIMEOUT 0xFE 1027 #define DFC_MBX_NOT_FINISHED 0xFF 1028 1029 1030 1031 /* Error codes for library calls */ 1032 #define DFC_ERR_GENERAL_ERROR 0x1 1033 1034 #define DFC_ERR_MBOX_ERROR 0x2 1035 #define DFC_ERR_LINK_DOWN 0x2 1036 #define DFC_ERR_INCORRECT_VER 0x2 1037 #define DFC_ERR_INVALID_ID 0x2 1038 #define DFC_ERR_TIMEOUT 0x2 1039 #define DFC_ERR_NOT_SUPPORTED 0x2 1040 #define DFC_ERR_NPIV_ACTIVE 0x2 1041 1042 #define DFC_ERR_NO_RPI 0x3 1043 #define DFC_ERR_BUFFER_OVERFLOW 0x3 1044 #define DFC_ERR_INVALID_LOOPBACK_TYPE 0x3 1045 #define DFC_ERR_OVERTEMP 0x3 1046 1047 #define DFC_ERR_LOOPBACK_BUSY 0x4 1048 #define DFC_ERR_INVALID_RESET_TYPE 0x4 1049 #define DFC_ERR_MENLO_LINKDOWN 0x4 1050 1051 #define DFC_ERR_SEQ_TIMEOUT 0x5 1052 1053 #define DFC_ERR_NO_XMIT 0x6 1054 #define DFC_ERR_INVALID_NUMBER 0x6 1055 1056 #define DFC_ERR_RESET_RECV 0x7 1057 1058 1059 1060 1061 /* type definitions for GetBindList function */ 1062 typedef enum dfc_bindtype 1063 { 1064 BIND_NONE, 1065 BIND_WWNN, 1066 BIND_WWPN, 1067 BIND_DID, 1068 BIND_ALPA 1069 } dfc_bindtype_t; 1070 1071 1072 typedef struct dfc_bind_entry 1073 { 1074 dfc_bindtype_t bind_type; 1075 uint32_t scsi_id; 1076 uint32_t did; 1077 uint8_t wwnn[8]; 1078 uint8_t wwpn[8]; 1079 uint32_t flags; 1080 1081 /* Bind Entry flags */ 1082 #define DFC_BIND_AUTOMAP 0x1 /* Node is automapped */ 1083 #define DFC_BIND_BINDLIST 0x2 /* entry in bind list not mapped */ 1084 #define DFC_BIND_MAPPED 0x4 /* Node is mapped to a scsiid */ 1085 #define DFC_BIND_UNMAPPED 0x8 /* Node is unmapped */ 1086 #define DFC_BIND_NODEVTMO 0x10 /* NODEVTMO flag of the node */ 1087 #define DFC_BIND_NOSCSIID 0x20 /* No scsi id is assigned yet */ 1088 #define DFC_BIND_RPTLUNST 0x40 /* Node is in report lun cmpl st */ 1089 } dfc_bind_entry_t; 1090 1091 typedef struct dfc_bind_list 1092 { 1093 uint32_t NumberOfEntries; 1094 dfc_bind_entry_t entry[1]; /* Variable length array */ 1095 } dfc_bind_list_t; 1096 1097 1098 1099 /* Defines for error codes -OLD- */ 1100 #define FC_ERROR_BUFFER_OVERFLOW 0xff 1101 #define FC_ERROR_RESPONSE_TIMEOUT 0xfe 1102 #define FC_ERROR_LINK_UNAVAILABLE 0xfd 1103 #define FC_ERROR_INSUFFICIENT_RESOURCES 0xfc 1104 #define FC_ERROR_EXISTING_REGISTRATION 0xfb 1105 #define FC_ERROR_INVALID_TAG 0xfa 1106 #define FC_ERROR_INVALID_WWN 0xf9 1107 #define FC_ERROR_CREATEVENT_FAILED 0xf8 1108 1109 1110 1111 typedef union dfc_ct_rev 1112 { 1113 /* Structure is in Big Endian format */ 1114 struct 1115 { 1116 uint32_t Revision:8; 1117 uint32_t InId:24; 1118 } bits; 1119 uint32_t word; 1120 } dfc_ct_rev_t; 1121 1122 typedef union dfc_ct_resp 1123 { 1124 /* Structure is in Big Endian format */ 1125 struct 1126 { 1127 uint32_t CmdRsp:16; 1128 uint32_t Size:16; 1129 } bits; 1130 uint32_t word; 1131 } dfc_ct_resp_t; 1132 1133 typedef struct dfc_ct_request 1134 { 1135 /* Structure is in Big Endian format */ 1136 dfc_ct_rev_t RevisionId; 1137 uint8_t FsType; 1138 uint8_t FsSubType; 1139 uint8_t Options; 1140 uint8_t Rsrvd1; 1141 dfc_ct_resp_t CommandResponse; 1142 uint8_t Rsrvd2; 1143 uint8_t ReasonCode; 1144 uint8_t Explanation; 1145 uint8_t VendorUnique; 1146 } dfc_ct_request_t; 1147 1148 #define SLI_CT_REVISION 1 1149 1150 #define FC_FSTYPE_ALL 0xffff /* match on all fsTypes */ 1151 1152 /* Emulex Vendor-Unique CT Request Command Codes */ 1153 #define CT_OP_GSAT 0x0101 /* Get Server Attributes */ 1154 #define CT_OP_GHAT 0x0102 /* Get HBA Attributes */ 1155 #define CT_OP_GPAT 0x0103 /* Get Port Attributes */ 1156 #define CT_OP_GDAT 0x0104 /* Get Driver Attributes */ 1157 #define CT_OP_GPST 0x0105 /* Get Port Statistics */ 1158 /* 0x0106 is reserved */ 1159 #define CT_OP_GDP 0x0107 /* Get Driver Parameters */ 1160 #define CT_OP_GDPG 0x0108 /* Get Driver Parameters Global */ 1161 #define CT_OP_GEPS 0x0109 /* Get Extended Port Statistics */ 1162 #define CT_OP_GLAT 0x010A /* Get Lun Attributes */ 1163 1164 #define CT_OP_SSAT 0x0111 /* Set Server Attributes */ 1165 #define CT_OP_SHAT 0x0112 /* Set HBA Attributes */ 1166 #define CT_OP_SPAT 0x0113 /* Set Port Attributes */ 1167 #define CT_OP_SDAT 0x0114 /* Set Driver Attributes */ 1168 /* 0x0115 is reserved */ 1169 /* 0x0116 is reserved */ 1170 #define CT_OP_SDP 0x0117 /* Set Driver Parameter */ 1171 #define CT_OP_SBBS 0x0118 /* Set Boot Bios State */ 1172 1173 #define CT_OP_RPST 0x0121 /* Reset Port Statistics */ 1174 #define CT_OP_VFW 0x0122 /* Verify Firmware */ 1175 #define CT_OP_DFW 0x0123 /* Download Firmware */ 1176 #define CT_OP_RES 0x0124 /* Reset HBA */ 1177 #define CT_OP_RHD 0x0125 /* Run HBA Diagnostic */ 1178 #define CT_OP_UFW 0x0126 /* Upgrade Firmware */ 1179 #define CT_OP_RDP 0x0127 /* Reset Driver Parameters */ 1180 #define CT_OP_GHDR 0x0128 /* Get HBA Diagnotic Results */ 1181 #define CT_OP_CHD 0x0129 /* Cancel HBA Diagnostic */ 1182 1183 /* 0x0131 is reserved */ 1184 /* 0x0132 is reserved */ 1185 #define CT_OP_SSR 0x0133 /* Send Software Resource */ 1186 1187 #define CT_OP_RSAT 0x0141 /* Read SA Table */ 1188 #define CT_OP_WSAT 0x0142 /* Write SA Table */ 1189 #define CT_OP_RSAH 0x0143 /* Read SA Table Header */ 1190 #define CT_OP_WSAH 0x0144 /* Write SA Table Header */ 1191 #define CT_OP_RACT 0x0145 /* Read Access Control Table */ 1192 #define CT_OP_WACT 0x0146 /* Write Access Control Table */ 1193 #define CT_OP_RKT 0x0147 /* Read Key Table Table */ 1194 #define CT_OP_WKT 0x0148 /* Write Key Table Table */ 1195 #define CT_OP_SSC 0x0149 /* Cause SA Table re-read;sync */ 1196 1197 #define CT_OP_QHBA 0x0151 /* Query HBA */ 1198 #define CT_OP_GST 0x0152 /* Get Status */ 1199 1200 #define CT_OP_GFTM 0x0161 /* Get FCP Target Mapping */ 1201 #define CT_OP_SRL 0x0162 /* SCSI Report Luns */ 1202 #define CT_OP_SI 0x0163 /* SCSI Inquiry */ 1203 #define CT_OP_SRC 0x0164 /* SCSI Read Capacity */ 1204 1205 #define CT_OP_GPB 0x0171 /* Get FCP Persistent Binding */ 1206 #define CT_OP_SPB 0x0172 /* Set FCP Persistent Binding */ 1207 #define CT_OP_RPB 0x0173 /* Remove FCP Persistent Binding */ 1208 #define CT_OP_RAPB 0x0174 /* Remove All FCP Persistent Bindings */ 1209 #define CT_OP_GBC 0x0175 /* Get Binding Capability */ 1210 #define CT_OP_GBS 0x0176 /* Get Binding Support */ 1211 #define CT_OP_SBS 0x0177 /* Set Binding Support */ 1212 #define CT_OP_GANI 0x0178 /* Get All Nodes Info */ 1213 #define CT_OP_GRV 0x0179 /* Get Range Value for Bus#, Target#, Lun# */ 1214 #define CT_OP_GAPBS 0x017A /* Get AutoPB service state */ 1215 /* (AutoPilotManager) */ 1216 #define CT_OP_APBC 0x017B /* Configure AutoPB service */ 1217 /* (AutoPilotManager) */ 1218 1219 #define CT_OP_GDT 0x0180 /* Get Driver Type */ 1220 #define CT_OP_GDLMI 0x0181 /* Get Drive Letter Mapping */ 1221 /* Information [GDLM] */ 1222 #define CT_OP_GANA 0x0182 /* Get All Node Addresses */ 1223 #define CT_OP_GDLV 0x0183 /* Get Driver Library Version */ 1224 #define CT_OP_GWUP 0x0184 /* Get Adapter Wakeup Parameters */ 1225 #define CT_OP_GLM 0x0185 /* Get Adapter Loopmap */ 1226 #define CT_OP_GABS 0x0186 /* Get Adapter Beacon State */ 1227 #define CT_OP_SABS 0x0187 /* Set Adapter Beacon State */ 1228 #define CT_OP_RPR 0x0188 /* Read Adapter PCI Registers */ 1229 1230 /* NPIV return codes */ 1231 #define DFC_NPIV_SUCCESS 0 1232 #define DFC_NPIV_GENERAL_ERROR 1 1233 #define DFC_NPIV_NOT_SUPPORTED 2 1234 #define DFC_NPIV_NO_RESOURCES 3 1235 #define DFC_NPIV_INVALID_HANDLE 3 1236 #define DFC_NPIV_ILLEGAL_WWPN 4 1237 #define DFC_NPIV_TOO_MANY_VPORTS 4 1238 #define DFC_NPIV_ILLEGAL_WWN 5 1239 #define DFC_NPIV_BUSY 5 1240 #define DFC_NPIV_INVALID_WWN 6 1241 #define DFC_NPIV_LINK_DOWN 7 1242 #define DFC_NPIV_MORE_DATA 7 1243 #define DFC_NPIV_FABRIC_NOT_SUPPORTED 8 1244 #define DFC_NPIV_FABRIC_OUT_OF_RESOURCE 9 1245 #define DFC_NPIV_INVALID_ACCESS_KEY 10 1246 #define DFC_NPIV_INVALID_HANDLE_AT_CREATE 11 1247 #define DFC_NPIV_UNSUPPORTED_OPTION 12 1248 1249 typedef struct dfc_vport_QoS 1250 { 1251 uint32_t resv; 1252 } dfc_vport_QoS_t; 1253 1254 1255 /* VPORT type */ 1256 #define VPORT_TYPE_PHYSICAL 0 1257 #define VPORT_TYPE_VIRTUAL 1 1258 1259 /* VPORT States */ 1260 #define VPORT_STATE_UNKNOWN 0 1261 #define VPORT_STATE_LINKDOWN 1 1262 #define VPORT_STATE_INIT 2 1263 #define VPORT_STATE_NO_FABRIC_SUPPORT 3 1264 #define VPORT_STATE_NO_FABRIC_RESOURCE 4 1265 #define VPORT_STATE_FABRIC_LOGOUT 5 1266 #define VPORT_STATE_FABRIC_REJECT_WWN 6 1267 #define VPORT_STATE_FABRIC_LOGIN_FAIL 7 1268 #define VPORT_STATE_ACTIVE 8 1269 #define VPORT_STATE_AUTH_FAILED 9 1270 1271 /* VPORT Options */ 1272 #define VPORT_OPT_AUTORETRY 0x00000001 1273 #define VPORT_OPT_AUTOWWN 0x00000002 1274 #define VPORT_OPT_ACTIVATE 0x00000004 1275 1276 #define VPORT_OPT_SAVE_CREATE_ONLY 0x00000000 1277 #define VPORT_OPT_SAVE_CREATE_UPDATE 0x00000010 1278 #define VPORT_OPT_SAVE_UPDATE_ONLY 0x00000018 1279 #define VPORT_OPT_SAVE_MASK 0x00000018 1280 1281 #define VPORT_OPT_RESTRICT 0x00000020 1282 #define VPORT_OPT_UNRESTRICT 0x00000040 1283 #define VPORT_OPT_RESTRICT_MASK 0x00000060 1284 1285 #define VPORT_OPT_FAILOVER 0x00000080 1286 1287 /* Check list bit-mapped value */ 1288 #define CL_NPIV_PARM_ENABLE 0x00000001 1289 #define CL_SLI3_ENABLE 0x00000002 1290 #define CL_HBA_SUPPORT_NPIV 0x00000004 1291 #define CL_HBA_HAS_RESOURCES 0x00000008 1292 #define CL_HBA_LINKUP 0x00000010 1293 #define CL_P2P_TOPOLOGY 0x00000020 1294 #define CL_FABRIC_SUPPORTS_NPIV 0x00000040 1295 #define CL_FABRIC_HAS_RESOURCES 0x00000080 1296 #define CL_NPIV_READY 0x000000FF 1297 1298 1299 1300 1301 #define DFC_VPORT_ATTR_VERSION 2 1302 typedef struct dfc_vport_attrs 1303 { 1304 uint8_t version; /* 2 = version of this structure, */ 1305 /* for compatibility check */ 1306 uint8_t reserved1[3]; 1307 1308 uint8_t wwpn[8]; /* virtual port WWPN */ 1309 uint8_t wwnn[8]; /* virtual port WWNN */ 1310 char name[256]; /* name to be register with the */ 1311 /* fabric */ 1312 1313 uint32_t options; 1314 1315 uint32_t portFcId; /* D-ID; set when the N-port is */ 1316 /* created successfully */ 1317 1318 uint8_t state; /* VPORT state */ 1319 uint8_t restrictLogin; 1320 uint8_t flags; 1321 uint8_t reserved2; 1322 uint64_t buf; /* Used for VPI */ 1323 1324 uint8_t fabric_wwn[8]; /* Fabric WWN (WWNN) */ 1325 uint32_t checklist; 1326 uint8_t accessKey[32]; 1327 } dfc_vport_attrs_t; 1328 1329 1330 typedef struct dfc_vport_entry 1331 { 1332 uint8_t wwpn[8]; /* wwpn of the virtual port */ 1333 uint8_t wwnn[8]; /* wwnn of the virtual port */ 1334 uint32_t PortFcId; /* FC port ID assigned to this */ 1335 /* virtual port */ 1336 } dfc_vport_entry_t; 1337 1338 1339 typedef struct dfc_vport_entry_list 1340 { 1341 uint32_t NumberOfEntries; 1342 dfc_vport_entry_t entry[MAX_VPORTS]; 1343 } dfc_vport_entry_list_t; 1344 1345 1346 typedef struct dfc_vport_nodeinfo_entry 1347 { 1348 uint32_t bind_type; 1349 #define VPORT_NODE_BINDDID 0x0000 1350 #define VPORT_NODE_BINDWWNN 0x0001 1351 #define VPORT_NODE_BINDWWPN 0x0002 1352 #define VPORT_NODE_AUTOMAP 0x0004 1353 #define VPORT_NODE_UNMASK_ALL_LUN 0x0008 1354 #define VPORT_NODE_DISABLE_LUN_AUTOMAP 0x0010 1355 #define VPORT_NODE_ALPA 0x0020 1356 1357 HBA_SCSIID scsiId; 1358 HBA_FCPID fcpId; 1359 1360 uint32_t nodeState; 1361 #define VPORT_NODESTATE_EXIST 0x0001 1362 #define VPORT_NODESTATE_READY 0x0002 1363 #define VPORT_NODESTATE_LINKDOWN 0x0004 1364 #define VPORT_NODESTATE_UNMAPPED 0x0008 1365 #define VPORT_NODESTATE_BOUND 0x0010 1366 1367 uint32_t reserved; 1368 } dfc_vport_nodeinfo_entry_t; 1369 1370 typedef struct dfc_vport_get_nodeinfo 1371 { 1372 uint32_t NumberOfEntries; /* number of nodes */ 1373 dfc_vport_nodeinfo_entry_t entry[MAX_NODES]; /* start of array */ 1374 } dfc_vport_get_nodeinfo_t; 1375 1376 1377 typedef struct dfc_vport_resource 1378 { 1379 uint32_t vpi_max; 1380 uint32_t vpi_inuse; 1381 uint32_t rpi_max; 1382 uint32_t rpi_inuse; 1383 } dfc_vport_resource_t; 1384 1385 1386 typedef struct dfc_vlinkinfo 1387 { 1388 uint32_t api_versions; 1389 1390 uint8_t linktype; 1391 uint8_t state; 1392 uint8_t fail_reason; 1393 uint8_t prev_fail_reason; 1394 #define VPORT_FAIL_UNKNOWN 0 1395 #define VPORT_FAIL_LINKDOWN 1 1396 #define VPORT_FAIL_FAB_UNSUPPORTED 2 1397 #define VPORT_FAIL_FAB_NORESOURCES 3 1398 #define VPORT_FAIL_FAB_LOGOUT 4 1399 #define VPORT_FAIL_HBA_NORESOURCES 5 1400 1401 uint8_t wwnn[8]; 1402 uint8_t wwpn[8]; 1403 1404 void *vlink; 1405 1406 uint32_t vpi_max; 1407 uint32_t vpi_inuse; 1408 uint32_t rpi_max; 1409 uint32_t rpi_inuse; 1410 } dfc_vlinkinfo_t; 1411 1412 1413 #ifdef DHCHAP_SUPPORT 1414 1415 /* DHCHAP return code */ 1416 #define DFC_AUTH_STATUS_NOT_CONFIGURED 0x8001 1417 #define DFC_AUTH_STATUS_AUTH_FAILED_NO_SA_FOUND 0x8002 1418 #define DFC_AUTH_STATUS_AUTH_INIT_OK_AUTH_FAILED 0x8003 1419 #define DFC_AUTH_STATUS_COMPARE_FAILED 0x8004 1420 #define DFC_AUTH_STATUS_WWN_NOT_FOUND 0x8005 1421 #define DFC_AUTH_STATUS_PASSWORD_INVALID 0x8006 1422 #define DFC_AUTH_STATUS_INVALID_ENTITY 0x8007 1423 #define DFC_AUTH_STATUS_ENTITY_NOT_ACTIVE 0x8008 1424 #define DFC_AUTH_STATUS_INVALID_OPERATION 0x8009 1425 #define DFC_AUTH_STATUS_OUT_OF_RESOURCES 0x800a 1426 #define DFC_AUTH_STATUS_AUTHENTICATION_GOINGON 0x800b 1427 #define DFC_AUTH_STATUS_INVALID_BOARD_NO 0x800c 1428 #define DFC_AUTH_STATUS_IO_ERROR 0x800d 1429 #define DFC_AUTH_STATUS_CREATE_STORKEY_ERROR 0x800e 1430 #define DFC_AUTH_STATUS_CREATE_PARMKEY_ERROR 0x800f 1431 #define DFC_AUTH_STATUS_CREATE_AUTHKEY_ERROR 0x8010 1432 #define DFC_AUTH_STATUS_LOCAL_REMOTE_PASSWORD_SAME 0x8011 1433 #define DFC_AUTH_STATUS_CREATE_BORDKEY_ERROR 0x8020 1434 #define DFC_AUTH_STATUS_DRVTYPE_NOT_SUPPORTED 0x8030 1435 #define DFC_AUTH_STATUS_AUTHENTICATION_NOT_SUPPORTED 0x8031 1436 #define DFC_AUTH_STATUS_GENERAL_ERROR 0x8032 1437 #define DFC_AUTH_STATUS_CONFIG_NOT_FOUND 0x8034 1438 #define DFC_AUTH_STATUS_NOT_PRIVILEGE_USER 0x8040 1439 1440 1441 typedef struct dfc_fcsp_config 1442 { 1443 HBA_WWN lwwpn; 1444 HBA_WWN rwwpn; 1445 1446 uint16_t auth_tov; /* seconds */ 1447 #define DFC_AUTH_TOV_MIN 20 1448 #define DFC_AUTH_TOV_MAX 1000 1449 #define DFC_AUTH_TOV_DEFAULT 45 1450 1451 uint8_t auth_mode; 1452 #define DFC_AUTH_MODE_DISABLED 1 1453 #define DFC_AUTH_MODE_ACTIVE 2 1454 #define DFC_AUTH_MODE_PASSIVE 3 1455 #define DFC_AUTH_MODE_DEFAULT DFC_AUTH_MODE_DISABLED 1456 1457 uint8_t auth_bidir:1; 1458 #define DFC_AUTH_BIDIR_DISABLED 0 1459 #define DFC_AUTH_BIDIR_ENABLED 1 1460 #define DFC_AUTH_BIDIR_DEFAULT DFC_AUTH_BIDIR_DISABLED 1461 uint8_t reserved:7; 1462 1463 uint8_t type_priority[4]; 1464 #define DFC_AUTH_TYPE_DHCHAP 1 /* Only one currently supported */ 1465 #define DFC_AUTH_TYPE_FCAP 2 1466 #define DFC_AUTH_TYPE_FCPAP 3 1467 #define DFC_AUTH_TYPE_KERBEROS 4 1468 #define DFC_AUTH_TYPE_MAX 4 1469 #define DFC_AUTH_TYPE_DEFAULT0 DFC_AUTH_TYPE_DHCHAP 1470 #define DFC_AUTH_TYPE_DEFAULT1 0 1471 #define DFC_AUTH_TYPE_DEFAULT2 0 1472 #define DFC_AUTH_TYPE_DEFAULT3 0 1473 1474 uint8_t hash_priority[4]; 1475 #define DFC_AUTH_HASH_MD5 1 1476 #define DFC_AUTH_HASH_SHA1 2 1477 #define DFC_AUTH_HASH_MAX 2 1478 #define DFC_AUTH_HASH_DEFAULT0 DFC_AUTH_HASH_MD5 1479 #define DFC_AUTH_HASH_DEFAULT1 DFC_AUTH_HASH_SHA1 1480 #define DFC_AUTH_HASH_DEFAULT2 0 1481 #define DFC_AUTH_HASH_DEFAULT3 0 1482 1483 uint8_t group_priority[8]; 1484 #define DFC_AUTH_GROUP_NULL 1 1485 #define DFC_AUTH_GROUP_1024 2 1486 #define DFC_AUTH_GROUP_1280 3 1487 #define DFC_AUTH_GROUP_1536 4 1488 #define DFC_AUTH_GROUP_2048 5 1489 #define DFC_AUTH_GROUP_MAX 5 1490 1491 #define DFC_AUTH_GROUP_DEFAULT0 DFC_AUTH_GROUP_NULL 1492 #define DFC_AUTH_GROUP_DEFAULT1 DFC_AUTH_GROUP_1024 1493 #define DFC_AUTH_GROUP_DEFAULT2 DFC_AUTH_GROUP_1280 1494 #define DFC_AUTH_GROUP_DEFAULT3 DFC_AUTH_GROUP_1536 1495 #define DFC_AUTH_GROUP_DEFAULT4 DFC_AUTH_GROUP_2048 1496 #define DFC_AUTH_GROUP_DEFAULT5 0 1497 #define DFC_AUTH_GROUP_DEFAULT6 0 1498 #define DFC_AUTH_GROUP_DEFAULT7 0 1499 1500 uint32_t reauth_tov; /* minutes */ 1501 #define DFC_REAUTH_TOV_MIN 0 1502 #define DFC_REAUTH_TOV_MAX 7200 1503 #define DFC_REAUTH_TOV_DEFAULT 1440 1504 } dfc_fcsp_config_t; 1505 1506 1507 typedef struct dfc_password 1508 { 1509 uint16_t length; 1510 #define DFC_PASSWORD_LENGTH_MIN 8 1511 #define DFC_PASSWORD_LENGTH_MAX 128 1512 1513 uint16_t type; 1514 #define DFC_PASSWORD_TYPE_ASCII 1 1515 #define DFC_PASSWORD_TYPE_BINARY 2 1516 #define DFC_PASSWORD_TYPE_IGNORE 3 1517 1518 uint8_t password[DFC_PASSWORD_LENGTH_MAX]; 1519 } dfc_password_t; 1520 1521 typedef struct dfc_auth_password 1522 { 1523 HBA_WWN lwwpn; 1524 HBA_WWN rwwpn; 1525 1526 dfc_password_t lpw; 1527 dfc_password_t rpw; 1528 1529 dfc_password_t lpw_new; 1530 dfc_password_t rpw_new; 1531 } dfc_auth_password_t; 1532 1533 1534 typedef struct dfc_auth_cfglist 1535 { 1536 uint32_t cnt; 1537 HBA_WWN rwwpn[1]; 1538 } dfc_auth_cfglist_t; 1539 1540 1541 typedef struct dfc_auth_status 1542 { 1543 HBA_WWN lwwpn; 1544 HBA_WWN rwwpn; 1545 1546 uint8_t auth_state; 1547 #define DFC_AUTH_STATE_OFF 1 1548 #define DFC_AUTH_STATE_INP 2 1549 #define DFC_AUTH_STATE_ON 3 1550 #define DFC_AUTH_STATE_FAILED 4 1551 1552 uint8_t auth_failReason; 1553 #define DFC_AUTH_FAIL_GENERIC 1 1554 #define DFC_AUTH_FAIL_ELS_TMO 2 1555 #define DFC_AUTH_FAIL_XACT_TMO 3 1556 #define DFC_AUTH_FAIL_LS_RJT 4 1557 #define DFC_AUTH_FAIL_BSY_LS_RJT 5 1558 #define DFC_AUTH_FAIL_REJECTED 6 1559 1560 uint8_t type_priority; 1561 uint8_t group_priority; 1562 1563 uint8_t hash_priority; 1564 uint8_t localAuth :1; 1565 uint8_t remoteAuth :1; 1566 uint8_t pad :6; 1567 uint16_t reserved0; 1568 1569 uint32_t time_from_last_auth; /* seconds */ 1570 uint32_t time_until_next_auth; /* seconds */ 1571 1572 uint32_t reserved1; 1573 uint32_t reserved2; 1574 } dfc_auth_status_t; 1575 1576 #endif /* DHCHAP_SUPPORT */ 1577 1578 /* 1579 * Start of FCP specific structures 1580 */ 1581 1582 #ifndef MAX_FCP_SNS 1583 typedef struct emlxs_fcp_rsp 1584 { 1585 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 1586 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 1587 1588 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 1589 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 1590 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 1591 #define RSP_LEN_VALID 0x01 /* bit 0 */ 1592 #define SNS_LEN_VALID 0x02 /* bit 1 */ 1593 #define RESID_OVER 0x04 /* bit 2 */ 1594 #define RESID_UNDER 0x08 /* bit 3 */ 1595 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 1596 #define SCSI_STAT_GOOD 0x00 1597 #define SCSI_STAT_CHECK_COND 0x02 1598 #define SCSI_STAT_COND_MET 0x04 1599 #define SCSI_STAT_BUSY 0x08 1600 #define SCSI_STAT_INTERMED 0x10 1601 #define SCSI_STAT_INTERMED_CM 0x14 1602 #define SCSI_STAT_RES_CNFLCT 0x18 1603 #define SCSI_STAT_CMD_TERM 0x22 1604 #define SCSI_STAT_QUE_FULL 0x28 1605 #define SCSI_STAT_ACA_ACTIVE 0x30 1606 #define SCSI_STAT_TASK_ABORT 0x40 1607 1608 uint32_t rspResId; /* Residual xfer if RESID_xxxx set in */ 1609 /* fcpStatus2 */ 1610 /* Received in Big Endian format */ 1611 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 1612 /* received in Big Endian format */ 1613 uint32_t rspRspLen; /* Length of FCP response data in */ 1614 /* fcpRspInfo */ 1615 /* Received In Big Endian format */ 1616 1617 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 1618 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 1619 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 1620 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 1621 1622 #define RSP_NO_FAILURE 0x00 1623 #define RSP_DATA_BURST_ERR 0x01 1624 #define RSP_CMD_FIELD_ERR 0x02 1625 #define RSP_RO_MISMATCH_ERR 0x03 1626 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 1627 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 1628 1629 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 1630 1631 /* 1632 * Define maximum size of SCSI Sense buffer. 1633 * Seagate never issues more than 18 bytes of Sense data. 1634 */ 1635 #define MAX_FCP_SNS 128 1636 uint8_t rspSnsInfo[MAX_FCP_SNS]; 1637 } emlxs_fcp_rsp; 1638 typedef emlxs_fcp_rsp FCP_RSP; 1639 #endif /* MAX_FCP_SNS */ 1640 1641 1642 #ifndef FC_LUN_SHIFT 1643 typedef struct emlxs_fcp_cmd 1644 { 1645 uint32_t fcpLunMsl; /* most significant word (32 bits) */ 1646 uint32_t fcpLunLsl; /* least significant word (32 bits) */ 1647 1648 /* 1649 * # of bits to shift lun id to end up in right payload word, 1650 * little endian = 8, big = 16. 1651 */ 1652 #ifdef EMLXS_LITTLE_ENDIAN 1653 #define FC_LUN_SHIFT 8 1654 #define FC_ADDR_MODE_SHIFT 0 1655 #endif 1656 #ifdef EMLXS_BIG_ENDIAN 1657 #define FC_LUN_SHIFT 16 1658 #define FC_ADDR_MODE_SHIFT 24 1659 #endif 1660 1661 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 1662 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 1663 #define SIMPLE_Q 0x00 1664 #define HEAD_OF_Q 0x01 1665 #define ORDERED_Q 0x02 1666 #define ACA_Q 0x04 1667 #define UNTAGGED 0x05 1668 1669 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 1670 /* codes */ 1671 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 1672 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 1673 #define LUN_RESET 0x10 /* bit 4 */ 1674 #define TARGET_RESET 0x20 /* bit 5 */ 1675 #define CLEAR_ACA 0x40 /* bit 6 */ 1676 #define TERMINATE_TASK 0x80 /* bit 7 */ 1677 1678 uint8_t fcpCntl3; 1679 #define WRITE_DATA 0x01 /* Bit 0 */ 1680 #define READ_DATA 0x02 /* Bit 1 */ 1681 1682 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 1683 uint32_t fcpDl; /* Total transfer length */ 1684 } emlxs_fcp_cmd_t; 1685 typedef emlxs_fcp_cmd_t FCP_CMND; 1686 #endif /* FC_LUN_SHIFT */ 1687 1688 1689 /* 1690 * Used by libdfc (SendScsiCmd, SendFcpCmd, DFC_SendScsiCmdV2, DFC_SendFcpCmdV2 1691 * and emlxs_dfc_send_scsi_fcp functions 1692 */ 1693 typedef struct dfc_send_scsi_fcp_cmd_info 1694 { 1695 HBA_WWN src_wwn; 1696 HBA_WWN dst_wwn; 1697 uint32_t cnt1; 1698 uint32_t cnt2; 1699 uint32_t ver; 1700 } dfc_send_scsi_fcp_cmd_info_t; 1701 1702 #define SCSI_RSP_CNT(x) x.cnt1 1703 #define SCSI_SNS_CNT(x) x.cnt2 1704 #define FC_DATA_CNT(x) x.cnt1 1705 #define FC_RSP_CNT(x) x.cnt2 1706 #define DFC_SEND_SCSI_FCP_V1 1 1707 #define DFC_SEND_SCSI_FCP_V2 2 1708 1709 typedef struct DFC_FCoEParam 1710 { 1711 uint8_t version; 1712 #define DFC_FCoE_PARAM_VERSION 1 1713 1714 uint8_t Reserved[3]; 1715 uint8_t FCMap[3]; 1716 uint8_t VLanValid; 1717 #define VLAN_ID_INVALID 0x0 1718 #define VLAN_ID_VALID 0x1 1719 1720 uint16_t VLanId; 1721 } DFC_FCoEParam_t; 1722 1723 typedef struct DFC_FCoEFCFConnectEntry 1724 { 1725 uint32_t flags; 1726 #define FCFCNCT_RSVD 0x00000001 1727 #define FCFCNCT_BOOT 0x00000002 1728 #define FCFCNCT_PRIMARY 0x00000004 1729 #define FCFCNCT_FBNM_VALID 0x00000008 1730 #define FCFCNCT_SWNM_VALID 0x00000010 1731 #define FCFCNCT_VLAN_VALID 0x00000020 1732 #define FCFCNCT_MASK 0xFFFFFF00 1733 1734 uint16_t vlan_id; 1735 uint8_t fabric_name[8]; 1736 uint8_t switch_name[8]; 1737 uint8_t reserved[2]; 1738 } DFC_FCoEFCFConnectEntry_t; 1739 1740 typedef struct DFC_FCoEFCFConnectList 1741 { 1742 uint8_t version; 1743 #define DFC_FCoE_FCFCONNECTLIST_VERSION 1 1744 1745 uint8_t reserved; 1746 uint8_t numberOfEntries; 1747 uint8_t maxNumOfEntries; 1748 DFC_FCoEFCFConnectEntry_t entries[1]; 1749 } DFC_FCoEFCFConnectList_t; 1750 1751 typedef struct DFC_FCoEFCFInfo 1752 { 1753 uint8_t FabricName[8]; 1754 uint8_t SwitchName[8]; 1755 uint8_t Mac[6]; 1756 uint16_t State; 1757 #define FCF_AVAILABLE_STATE 0x1 1758 1759 uint8_t VLanBitMap[512]; 1760 uint8_t FC_Map[3]; 1761 uint8_t reserved1; 1762 uint32_t LKA_Period; 1763 uint32_t reserved2; 1764 uint32_t Priority; 1765 } DFC_FCoEFCFInfo_t; 1766 1767 typedef struct DFC_FCoEFCFList 1768 { 1769 uint8_t version; 1770 #define DFC_FCoE_FCFLIST_VERSION 1 1771 1772 uint8_t reserved[3]; 1773 uint16_t numberOfEntries; 1774 uint16_t nActiveFCFs; 1775 DFC_FCoEFCFInfo_t entries[1]; 1776 } DFC_FCoEFCFList_t; 1777 1778 #ifdef __cplusplus 1779 } 1780 #endif 1781 1782 #endif /* _EMLXS_DFCLIB_H */ 1783