1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_DFCLIB_H 29 #define _EMLXS_DFCLIB_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define MAX_DFC_EVENTS 16 36 #define MAX_EMLXS_BRDS 128 37 #define MAX_CFG_PARAM 64 38 #define MAX_NODES 4096 39 40 41 #ifndef MAX_VPORTS 42 #ifdef NPIV_SUPPORT 43 #define MAX_VPORTS 256 44 #else 45 #define MAX_VPORTS 1 46 #endif /* NPIV_SUPPORT */ 47 #endif /* MAX_VPORTS */ 48 49 #ifdef EMLXS_SPARC 50 #define EMLXS_BIG_ENDIAN 51 #endif /* EMLXS_SPARC */ 52 53 #ifdef EMLXS_I386 54 #define EMLXS_LITTLE_ENDIAN 55 #endif /* EMLXS_I386 */ 56 57 58 typedef struct brdinfo 59 { 60 uint32_t a_mem_hi; /* memory identifier for adapter access */ 61 uint32_t a_mem_low; /* memory identifier for adapter access */ 62 uint32_t a_flash_hi; /* memory identifier for adapter access */ 63 uint32_t a_flash_low; /* memory identifier for adapter access */ 64 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 65 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 66 uint32_t a_intrlvl; /* interrupt level for adapter */ 67 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 68 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 69 uint32_t a_devid; /* identifier of PCI device number */ 70 uint8_t a_rsvd1; /* reserved for future use */ 71 uint8_t a_rsvd2; /* reserved for future use */ 72 uint8_t a_siglvl; /* signal handler used by library */ 73 uint8_t a_ddi; /* identifier device driver instance number */ 74 uint32_t a_onmask; /* mask of ONDI primatives supported */ 75 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 76 uint8_t a_drvrid[16]; /* driver version */ 77 uint8_t a_fwname[32]; /* firmware version */ 78 } brdinfo_t; 79 80 81 typedef struct dfc_brdinfo 82 { 83 uint32_t a_mem_hi; /* memory identifier for adapter access */ 84 uint32_t a_mem_low; /* memory identifier for adapter access */ 85 uint32_t a_flash_hi; /* memory identifier for adapter access */ 86 uint32_t a_flash_low; /* memory identifier for adapter access */ 87 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 88 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 89 uint32_t a_intrlvl; /* interrupt level for adapter */ 90 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 91 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 92 uint32_t a_devid; /* identifier of PCI device number */ 93 uint8_t a_rsvd; /* reserved for word alignment */ 94 uint8_t a_siglvl; /* signal handler used by library */ 95 uint16_t a_ddi; /* identifier device driver instance number */ 96 uint32_t a_onmask; /* mask of ONDI primatives supported */ 97 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 98 uint8_t a_drvrid[16]; /* driver version */ 99 uint8_t a_fwname[32]; /* firmware version */ 100 uint8_t a_wwpn[8]; /* worldwide portname */ 101 } dfc_brdinfo_t; 102 103 104 #define putPaddrLow(addr) ((uint32_t)(((uint64_t)(addr)) & 0xffffffff)) 105 #define putPaddrHigh(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 106 #define getPaddr(high, low) ((uint64_t)((((uint64_t)(high)) << 32) \ 107 | (((uint64_t)(low)) & 0xffffffff))) 108 109 typedef struct ulp_bde 110 { 111 uint32_t bdeAddress; 112 113 #ifdef EMLXS_BIG_ENDIAN 114 uint32_t bdeReserved:4; 115 uint32_t bdeAddrHigh:4; 116 uint32_t bdeSize:24; 117 #endif 118 #ifdef EMLXS_LITTLE_ENDIAN 119 uint32_t bdeSize:24; 120 uint32_t bdeAddrHigh:4; 121 uint32_t bdeReserved:4; 122 #endif 123 } ulp_bde_t; 124 125 typedef struct ulp_bde64 126 { 127 union 128 { 129 uint32_t w; 130 struct 131 { 132 #ifdef EMLXS_BIG_ENDIAN 133 uint32_t bdeFlags:8; 134 uint32_t bdeSize:24; 135 #endif 136 #ifdef EMLXS_LITTLE_ENDIAN 137 uint32_t bdeSize:24; 138 uint32_t bdeFlags:8; 139 #endif 140 141 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 142 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 143 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 144 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit buffer */ 145 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit addr */ 146 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 147 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 148 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 149 } f; 150 } tus; 151 152 uint32_t addrLow; 153 uint32_t addrHigh; 154 } ulp_bde64_t; 155 156 typedef struct read_sparm_var 157 { 158 uint32_t rsvd1; 159 uint32_t rsvd2; 160 union 161 { 162 ulp_bde_t sp; 163 ulp_bde64_t sp64; 164 } un; 165 } read_sparm_var_t; 166 167 typedef struct read_rev_var 168 { 169 #ifdef EMLXS_BIG_ENDIAN 170 uint32_t cv:1; 171 uint32_t rr:1; 172 uint32_t rsvd1:29; 173 uint32_t rv:1; 174 #endif 175 #ifdef EMLXS_LITTLE_ENDIAN 176 uint32_t rv:1; 177 uint32_t rsvd1:29; 178 uint32_t rr:1; 179 uint32_t cv:1; 180 #endif 181 uint32_t biuRev; 182 uint32_t smRev; 183 union 184 { 185 uint32_t smFwRev; 186 struct 187 { 188 #ifdef EMLXS_BIG_ENDIAN 189 uint8_t ProgType; 190 uint8_t ProgId; 191 uint16_t ProgVer:4; 192 uint16_t ProgRev:4; 193 uint16_t ProgFixLvl:2; 194 uint16_t ProgDistType:2; 195 uint16_t DistCnt:4; 196 #endif 197 #ifdef EMLXS_LITTLE_ENDIAN 198 uint16_t DistCnt:4; 199 uint16_t ProgDistType:2; 200 uint16_t ProgFixLvl:2; 201 uint16_t ProgRev:4; 202 uint16_t ProgVer:4; 203 uint8_t ProgId; 204 uint8_t ProgType; 205 #endif 206 } b; 207 } un; 208 uint32_t endecRev; 209 210 #ifdef EMLXS_BIG_ENDIAN 211 uint8_t feaLevelHigh; 212 uint8_t feaLevelLow; 213 uint8_t fcphHigh; 214 uint8_t fcphLow; 215 #endif 216 #ifdef EMLXS_LITTLE_ENDIAN 217 uint8_t fcphLow; 218 uint8_t fcphHigh; 219 uint8_t feaLevelLow; 220 uint8_t feaLevelHigh; 221 #endif 222 uint32_t postKernRev; 223 uint32_t opFwRev; 224 uint8_t opFwName[16]; 225 uint32_t sli1FwRev; 226 uint8_t sli1FwName[16]; 227 uint32_t sli2FwRev; 228 uint8_t sli2FwName[16]; 229 } read_rev_var_t; 230 231 232 typedef struct dump_var 233 { 234 #ifdef EMLXS_BIG_ENDIAN 235 uint32_t rsvd:25; 236 uint32_t ra:1; 237 uint32_t co:1; 238 uint32_t cv:1; 239 uint32_t type:4; 240 241 uint32_t entry_index:16; 242 uint32_t region_id:16; 243 #endif 244 #ifdef EMLXS_LITTLE_ENDIAN 245 uint32_t type:4; 246 uint32_t cv:1; 247 uint32_t co:1; 248 uint32_t ra:1; 249 uint32_t rsvd:25; 250 251 uint32_t region_id:16; 252 uint32_t entry_index:16; 253 #endif 254 uint32_t base_adr; 255 uint32_t word_cnt; 256 uint32_t resp_offset; 257 } dump_var_t; 258 259 260 typedef struct read_cfg_var 261 { 262 #ifdef EMLXS_BIG_ENDIAN 263 uint32_t cr:1; 264 uint32_t ci:1; 265 uint32_t cr_delay:6; 266 uint32_t cr_count:8; 267 uint32_t InitBBC:8; 268 uint32_t MaxBBC:8; 269 #endif 270 #ifdef EMLXS_LITTLE_ENDIAN 271 uint32_t MaxBBC:8; 272 uint32_t InitBBC:8; 273 uint32_t cr_count:8; 274 uint32_t cr_delay:6; 275 uint32_t ci:1; 276 uint32_t cr:1; 277 #endif 278 #ifdef EMLXS_BIG_ENDIAN 279 uint32_t topology:8; 280 uint32_t myDid:24; 281 #endif 282 #ifdef EMLXS_LITTLE_ENDIAN 283 uint32_t myDid:24; 284 uint32_t topology:8; 285 #endif 286 /* Defines for topology (defined previously) */ 287 #ifdef EMLXS_BIG_ENDIAN 288 uint32_t AR:1; 289 uint32_t IR:1; 290 uint32_t rsvd1:29; 291 uint32_t ack0:1; 292 #endif 293 #ifdef EMLXS_LITTLE_ENDIAN 294 uint32_t ack0:1; 295 uint32_t rsvd1:29; 296 uint32_t IR:1; 297 uint32_t AR:1; 298 #endif 299 uint32_t edtov; 300 uint32_t arbtov; 301 uint32_t ratov; 302 uint32_t rttov; 303 uint32_t altov; 304 uint32_t lmt; 305 306 #define LMT_1GB_CAPABLE 0x0004 307 #define LMT_2GB_CAPABLE 0x0008 308 #define LMT_4GB_CAPABLE 0x0040 309 #define LMT_8GB_CAPABLE 0x0080 310 #define LMT_10GB_CAPABLE 0x0100 311 312 uint32_t rsvd2; 313 uint32_t rsvd3; 314 uint32_t max_xri; 315 uint32_t max_iocb; 316 uint32_t max_rpi; 317 uint32_t avail_xri; 318 uint32_t avail_iocb; 319 uint32_t avail_rpi; 320 uint32_t default_rpi; 321 } read_cfg_var_t; 322 323 324 typedef struct read_log_var 325 { 326 #ifdef EMLXS_BIG_ENDIAN 327 uint32_t type:8; 328 uint32_t byte_count:8; 329 uint32_t write:1; 330 uint32_t resv:3; 331 uint32_t offset:12; 332 #endif 333 #ifdef EMLXS_LITTLE_ENDIAN 334 uint32_t offset:12; 335 uint32_t resv:3; 336 uint32_t write:1; 337 uint32_t byte_count:8; 338 uint32_t type:8; 339 #endif 340 341 uint32_t data; 342 } read_log_var_t; 343 344 345 typedef struct log_status_var 346 { 347 348 #ifdef EMLXS_BIG_ENDIAN 349 uint16_t split_log_next; 350 uint16_t log_next; 351 352 uint32_t size; 353 354 uint32_t format:8; 355 uint32_t resv2:22; 356 uint32_t log_level:1; 357 uint32_t split_log:1; 358 #endif 359 #ifdef EMLXS_LITTLE_ENDIAN 360 uint16_t log_next; 361 uint16_t split_log_next; 362 363 uint32_t size; 364 365 uint32_t split_log:1; 366 uint32_t log_level:1; 367 uint32_t resv2:22; 368 uint32_t format:8; 369 #endif 370 371 uint32_t offset; 372 } log_status_var_t; 373 374 375 typedef struct read_evt_log_var 376 { 377 #ifdef EMLXS_BIG_ENDIAN 378 uint32_t read_log:1; 379 uint32_t clear_log:1; 380 uint32_t mbox_rsp:1; 381 uint32_t resv:28; 382 #endif 383 #ifdef EMLXS_LITTLE_ENDIAN 384 uint32_t resv:28; 385 uint32_t mbox_rsp:1; 386 uint32_t clear_log:1; 387 uint32_t read_log:1; 388 #endif 389 390 uint32_t offset; 391 392 union 393 { 394 ulp_bde_t sp; 395 ulp_bde64_t sp64; 396 } un; 397 } read_evt_log_var_t; 398 399 400 typedef struct dfc_mailbox 401 { 402 #ifdef EMLXS_BIG_ENDIAN 403 uint16_t mbxStatus; 404 uint8_t mbxCommand; 405 uint8_t mbxReserved:6; 406 uint8_t mbxHc:1; 407 uint8_t mbxOwner:1; /* Low order bit first word */ 408 #endif 409 #ifdef EMLXS_LITTLE_ENDIAN 410 uint8_t mbxOwner:1; /* Low order bit first word */ 411 uint8_t mbxHc:1; 412 uint8_t mbxReserved:6; 413 uint8_t mbxCommand; 414 uint16_t mbxStatus; 415 #endif 416 417 union 418 { 419 uint32_t varWords[31]; 420 read_sparm_var_t varRdSparm; 421 read_rev_var_t varRdRev; 422 read_cfg_var_t varRdCfg; 423 dump_var_t varDmp; 424 read_log_var_t varRdLog; 425 log_status_var_t varLogStat; 426 read_evt_log_var_t varRdEvtLog; 427 428 } un; 429 } dfc_mailbox_t; 430 431 432 typedef struct dfc_ioinfo 433 { 434 uint32_t a_mboxCmd; /* mailbox commands issued */ 435 uint32_t a_mboxCmpl; /* mailbox commands completed */ 436 uint32_t a_mboxErr; /* mailbox commands completed, error status */ 437 uint32_t a_iocbCmd; /* iocb command ring issued */ 438 uint32_t a_iocbRsp; /* iocb rsp ring received */ 439 uint32_t a_adapterIntr; /* adapter interrupt events */ 440 uint32_t a_fcpCmd; /* FCP commands issued */ 441 uint32_t a_fcpCmpl; /* FCP command completions received */ 442 uint32_t a_fcpErr; /* FCP command completions errors */ 443 uint32_t a_seqXmit; /* IP xmit sequences sent */ 444 uint32_t a_seqRcv; /* IP sequences received */ 445 uint32_t a_bcastXmit; /* cnt of successful xmit bcast cmds issued */ 446 uint32_t a_bcastRcv; /* cnt of receive bcast cmds received */ 447 uint32_t a_elsXmit; /* cnt of successful ELS req cmds issued */ 448 uint32_t a_elsRcv; /* cnt of ELS request commands received */ 449 uint32_t a_RSCNRcv; /* cnt of RSCN commands received */ 450 uint32_t a_seqXmitErr; /* cnt of unsuccessful xmit bcast cmds issued */ 451 uint32_t a_elsXmitErr; /* cnt of unsuccessful ELS req cmds issued */ 452 uint32_t a_elsBufPost; /* cnt of ELS buffers posted to adapter */ 453 uint32_t a_ipBufPost; /* cnt of IP buffers posted to adapter */ 454 uint32_t a_cnt1; /* generic counter */ 455 uint32_t a_cnt2; /* generic counter */ 456 uint32_t a_cnt3; /* generic counter */ 457 uint32_t a_cnt4; /* generic counter */ 458 459 } dfc_ioinfo_t; 460 461 462 typedef struct dfc_linkinfo 463 { 464 uint32_t a_linkEventTag; 465 uint32_t a_linkUp; 466 uint32_t a_linkDown; 467 uint32_t a_linkMulti; 468 uint32_t a_DID; 469 uint8_t a_topology; 470 uint8_t a_linkState; 471 uint8_t a_alpa; 472 uint8_t a_alpaCnt; 473 uint8_t a_alpaMap[128]; 474 uint8_t a_wwpName[8]; 475 uint8_t a_wwnName[8]; 476 } dfc_linkinfo_t; 477 478 /* values for a_topology */ 479 #define LNK_LOOP 0x1 480 #define LNK_PUBLIC_LOOP 0x2 481 #define LNK_FABRIC 0x3 482 #define LNK_PT2PT 0x4 483 #define LNK_MENLO_MAINTENANCE 0x5 484 485 /* values for a_linkState */ 486 #define LNK_DOWN 0x1 487 #define LNK_UP 0x2 488 #define LNK_FLOGI 0x3 489 #define LNK_DISCOVERY 0x4 490 #define LNK_REDISCOVERY 0x5 491 #define LNK_READY 0x6 492 493 494 typedef struct dfc_traceinfo 495 { 496 uint8_t a_event; 497 uint8_t a_cmd; 498 uint16_t a_status; 499 uint32_t a_information; 500 } dfc_traceinfo_t; 501 502 503 typedef struct dfc_cfgparam 504 { 505 char a_string[32]; 506 uint32_t a_low; 507 uint32_t a_hi; 508 uint32_t a_default; 509 uint32_t a_current; 510 uint16_t a_flag; 511 #define CFG_EXPORT 0x1 /* Export this parameter to end user */ 512 #define CFG_IGNORE 0x2 /* Ignore this parameter */ 513 514 uint16_t a_changestate; 515 #define CFG_REBOOT 0x0 /* Changes effective after system */ 516 /* reboot */ 517 #define CFG_DYMANIC 0x1 /* Changes effective immediately */ 518 #define CFG_RESTART 0x2 /* Changes effective after adapter */ 519 /* restart */ 520 #define CFG_LINKRESET 0x3 /* Changes effective after link reset */ 521 522 char a_help[80]; 523 } dfc_cfgparam_t; 524 525 526 527 typedef struct dfc_nodeinfo 528 { 529 uint16_t a_flag; 530 uint16_t a_state; 531 uint32_t a_did; 532 uint8_t a_wwpn[8]; 533 uint8_t a_wwnn[8]; 534 uint32_t a_targetid; 535 } dfc_nodeinfo_t; 536 537 /* Defines for a_state */ 538 #define NODE_UNUSED 0 /* unused NL_PORT entry */ 539 #define NODE_LIMBO 0x1 /* entry needs to hang around for wwpn / sid */ 540 #define NODE_LOGOUT 0x2 /* NL_PORT is not logged in - entry is cached */ 541 #define NODE_PLOGI 0x3 /* PLOGI was sent to NL_PORT */ 542 #define NODE_LOGIN 0x4 /* NL_PORT is logged in / login REG_LOGINed */ 543 #define NODE_PRLI 0x5 /* PRLI was sent to NL_PORT */ 544 #define NODE_ALLOC 0x6 /* NL_PORT is ready to initiate adapter I/O */ 545 #define NODE_SEED 0x7 /* seed scsi id bind in table */ 546 547 /* Defines for a_flag */ 548 #define NODE_RPI_XRI 0x1 /* creating xri for entry */ 549 #define NODE_REQ_SND 0x2 /* sent ELS request for this entry */ 550 #define NODE_ADDR_AUTH 0x4 /* Authenticating addr for this entry */ 551 #define NODE_RM_ENTRY 0x8 /* Remove this entry */ 552 #define NODE_FARP_SND 0x10 /* sent FARP request for this entry */ 553 #define NODE_FABRIC 0x20 /* this entry represents the Fabric */ 554 #define NODE_FCP_TARGET 0x40 /* this entry is an FCP target */ 555 #define NODE_IP_NODE 0x80 /* this entry is an IP node */ 556 #define NODE_DISC_START 0x100 /* start discovery on this entry */ 557 #define NODE_SEED_WWPN 0x200 /* Entry scsi id is seeded for WWPN */ 558 #define NODE_SEED_WWNN 0x400 /* Entry scsi id is seeded for WWNN */ 559 #define NODE_SEED_DID 0x800 /* Entry scsi id is seeded for DID */ 560 #define NODE_SEED_MASK 0xe00 /* mask for seeded flags */ 561 #define NODE_AUTOMAP 0x1000 /* This entry was automap'ed */ 562 #define NODE_NS_REMOVED 0x2000 /* This entry removed from NameServer */ 563 564 565 typedef struct dfc_vpd 566 { 567 uint32_t version; 568 #define DFC_VPD_VERSION 1 569 570 char ModelDescription[256]; /* VPD field V1 */ 571 char Model[80]; /* VPD field V2 */ 572 char ProgramType[256]; /* VPD field V3 */ 573 char PortNum[20]; /* VPD field V4 */ 574 } dfc_vpd_t; 575 576 typedef struct dfc_destid 577 { 578 uint32_t idType; /* 0 - wwpn, 1 - d_id */ 579 uint32_t d_id; 580 uint8_t wwpn[8]; 581 } dfc_destid_t; 582 583 584 typedef struct dfc_loopback 585 { 586 uint32_t bufSize; 587 uint8_t *XmitBuffer; 588 uint8_t *RcvBuffer; 589 } dfc_loopback_t; 590 591 592 typedef struct dfc_drvinfo 593 { 594 uint8_t drvInfoVer; /* Version of this structure */ 595 #define DFC_DRVINFO_VERSION2 0x02 596 #define DFC_DRVINFO_VERSION3 0x03 /* NPIV */ 597 #define DFC_DRVINFO_VERSION4 0x04 /* DHCHAP */ 598 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION2 599 600 #ifdef NPIV_SUPPORT 601 #undef DFC_DRVINFO_VERSION 602 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION3 603 #endif /* NPIV_SUPPORT */ 604 605 #ifdef DHCHAP_SUPPORT 606 #undef DFC_DRVINFO_VERSION 607 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION4 608 #endif /* DHCHAP_SUPPORT */ 609 610 uint8_t drvType; 611 #define DFC_DRVINFO_SOLARIS 0x11 /* Solaris */ 612 #define DFC_DRVINFO_LEADVILLE 0x14 /* Solaris Leadville ULP */ 613 #define DFC_DRVINFO_COMSTAR 0x16 /* Solaris Comstar ULP */ 614 615 uint16_t reserved; 616 uint8_t rmLevel; /* Remote Management (HBAnyware) */ 617 /* Support Level */ 618 #define DFC_DRVINFO_RMLEVEL 0x02 /* HBAnyware v2.3 */ 619 620 uint8_t mpLevel; /* MultiPulse support Level */ 621 uint8_t hbaapiLevel; /* HBAAPI support level */ 622 #define DFC_DRVINFO_HBAAPI 0x01 /* HBAAPI v1.0 */ 623 624 uint8_t reserved1; 625 char drvVer[16]; /* Driver Version string */ 626 char drvName[8]; /* Driver Name */ 627 char ftrDrvVer[16]; /* Filter/IOCtl Driver Version string */ 628 char ftrDrvName[8]; /* Filter/IOCtl Driver Name */ 629 char ipDrvVer[16]; /* IP Driver/component Version string */ 630 char ipDrvName[8]; /* IP Driver/component Name */ 631 uint32_t d_id; 632 uint8_t wwpn[8]; 633 uint8_t wwnn[8]; 634 uint8_t hostname[32]; /* IP node hostname from uname -n */ 635 636 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION3) 637 uint32_t NPIVsupport; 638 #define DFC_DRVINFO_NPIV_DRV 0x00000001 639 #define DFC_DRVINFO_NPIV_MODS 0x00000002 640 #define DFC_DRVINFO_NPIV_PARMS 0x00000004 641 #define DFC_DRVINFO_NPIV_FW 0x00000008 642 643 #endif /* >= DFC_DRVINFO_VERSION3 */ 644 645 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION4) 646 uint32_t sliMode; 647 uint64_t featureList; 648 #define DFC_DRVINFO_FEATURE_DIAG 0x00000001 649 #define DFC_DRVINFO_FEATURE_MAPPING 0x00000002 650 #define DFC_DRVINFO_FEATURE_DHCHAP 0x00000004 651 #define DFC_DRVINFO_FEATURE_IKE 0x00000008 652 #define DFC_DRVINFO_FEATURE_NPIV 0x00000010 653 #define DFC_DRVINFO_FEATURE_RESET_WWN 0x00000020 654 #define DFC_DRVINFO_FEATURE_VOLATILE_WWN 0x00000040 655 #define DFC_DRVINFO_FEATURE_E2E_AUTH 0x00000080 656 #define DFC_DRVINFO_FEATURE_TARGET_MODE 0x00000100 657 658 #endif /* >= DFC_DRVINFO_VERSION4 */ 659 } dfc_drvinfo_t; 660 661 662 663 typedef struct dfc_regevent 664 { 665 uint32_t ppid; 666 uint32_t cpid; 667 668 uint32_t event; 669 uint32_t type; 670 uint32_t outsz; 671 void *ctx; 672 void (*func) (); 673 674 uint32_t cindex; /* Set only by child */ 675 uint32_t state; /* Set only by child */ 676 677 /* state */ 678 #define CHILD_UNKNOWN 0 679 #define CHILD_UNBORN 1 680 #define CHILD_ALIVE 2 681 #define CHILD_REGISTERED 3 682 #define CHILD_ASLEEP 4 683 #define CHILD_AWAKE 5 684 #define CHILD_DIED 6 685 686 uint32_t pindex; /* Set only by parent */ 687 uint32_t flags; /* Set only by parent */ 688 689 /* flags */ 690 #define EVENT_REGISTERED 0x01 691 #define EVENT_SERVICE_ACTIVE 0x02 692 693 #ifdef SAN_DIAG_SUPPORT 694 HBA_WWN portname; 695 #endif /* SAN_DIAG_SUPPORT */ 696 } dfc_regevent_t; 697 698 699 /* Defines for RegisterForEvent mask */ 700 #define FC_REG_LINK_EVENT 0x01 /* Register for link up/down */ 701 /* events */ 702 #define FC_REG_RSCN_EVENT 0x02 /* Register for RSCN events */ 703 #define FC_REG_CT_EVENT 0x04 /* Register for CT request */ 704 /* events */ 705 #define FC_REG_MULTIPULSE_EVENT 0x08 /* Register for MultiPulse */ 706 /* events */ 707 #define FC_REG_DUMP_EVENT 0x10 /* Register for Diagnostic */ 708 /* Dump events */ 709 #define FC_REG_TEMP_EVENT 0x20 /* Register for Temperature */ 710 /* events */ 711 #define FC_REG_VPORTRSCN_EVENT 0x40 /* Register for VPort RSCN */ 712 /* events */ 713 #ifdef SAN_DIAG_SUPPORT 714 #define FC_REG_SD_ELS_EVENT 0x1000 /* Register for SANDiag ELS */ 715 /* events */ 716 #define FC_REG_SD_FABRIC_EVENT 0x2000 /* Register for SANDiag */ 717 /* Fabric events */ 718 #define FC_REG_SD_SCSI_EVENT 0x4000 /* Register for SANDiag SCSI */ 719 /* events */ 720 #define FC_REG_SD_BOARD_EVENT 0x8000 /* Register for SANDiag Board */ 721 /* events */ 722 #endif /* SAN_DIAG_SUPPORT */ 723 #define FC_REG_FCOE_EVENT 0x80000000 /* (Unofficial) Register for */ 724 /* FCOE events */ 725 726 #define MAX_RSCN_PAYLOAD 1024 727 #define MAX_CT_PAYLOAD (1024*320) 728 729 /* Temperature event types */ 730 #define DFC_TEMP_CRITICAL 1 731 #define DFC_TEMP_WARNING 2 732 #define DFC_TEMP_SAFE 3 733 734 /* bits in a_onmask */ 735 #define ONDI_MBOX 0x1 /* allows non-destructive mailbox */ 736 /* commands */ 737 #define ONDI_IOINFO 0x2 /* supports retrieval of I/O info */ 738 #define ONDI_LNKINFO 0x4 /* supports retrieval of link info */ 739 #define ONDI_NODEINFO 0x8 /* supports retrieval of node info */ 740 #define ONDI_TRACEINFO 0x10 /* supports retrieval of trace info */ 741 #define ONDI_SETTRACE 0x20 /* supports configuration of trace */ 742 /* info */ 743 #define ONDI_SLI1 0x40 /* hardware supports SLI-1 interface */ 744 #define ONDI_SLI2 0x80 /* hardware supports SLI-2 interface */ 745 #define ONDI_BIG_ENDIAN 0x100 /* DDI interface is BIG Endian */ 746 #define ONDI_LTL_ENDIAN 0x200 /* DDI interface is LITTLE Endian */ 747 #define ONDI_RMEM 0x400 /* allows reading of adapter shared */ 748 /* memory */ 749 #define ONDI_RFLASH 0x800 /* allows reading of adapter flash */ 750 #define ONDI_RPCI 0x1000 /* allows reading of adapter pci */ 751 /* registers */ 752 #define ONDI_RCTLREG 0x2000 /* allows reading of adapter cntrol */ 753 /* registers */ 754 #define ONDI_CFGPARAM 0x4000 /* supports get/set configuration */ 755 /* parameters */ 756 #define ONDI_CT 0x8000 /* supports passthru CT interface */ 757 #define ONDI_HBAAPI 0x10000 /* supports HBA API interface */ 758 #define ONDI_SBUS 0x20000 /* supports SBUS adapter interface */ 759 760 /* bits in a_offmask */ 761 #define OFFDI_MBOX 0x1 /* allows all mailbox commands */ 762 #define OFFDI_RMEM 0x2 /* allows reading of adapter shared */ 763 /* memory */ 764 #define OFFDI_WMEM 0x4 /* allows writing of adapter shared */ 765 /* memory */ 766 #define OFFDI_RFLASH 0x8 /* allows reading of adapter flash */ 767 #define OFFDI_WFLASH 0x10 /* allows writing of adapter flash */ 768 #define OFFDI_RPCI 0x20 /* allows reading of adapter pci */ 769 /* registers */ 770 #define OFFDI_WPCI 0x40 /* allows writing of adapter pci */ 771 /* registers */ 772 #define OFFDI_RCTLREG 0x80 /* allows reading of adapter cntrol */ 773 /* registers */ 774 #define OFFDI_WCTLREG 0x100 /* allows writing of adapter cntrol */ 775 /* registers */ 776 #define OFFDI_OFFLINE 0x80000000 /* if set, adapter is in offline */ 777 /* state */ 778 779 780 #define DDI_SHOW 0x0 781 #define DDI_ONDI 0x1 782 #define DDI_OFFDI 0x2 783 #define DDI_WARMDI 0x3 784 #define DDI_DIAGDI 0x4 785 786 /* mbxStatus */ 787 #define DFC_MBX_SUCCESS 0x00 788 #define DFC_MBXERR_NUM_RINGS 0x01 789 #define DFC_MBXERR_NUM_IOCBS 0x02 790 #define DFC_MBXERR_IOCBS_EXCEEDED 0x03 791 #define DFC_MBXERR_BAD_RING_NUMBER 0x04 792 #define DFC_MBXERR_MASK_ENTRIES_RANGE 0x05 793 #define DFC_MBXERR_MASKS_EXCEEDED 0x06 794 #define DFC_MBXERR_BAD_PROFILE 0x07 795 #define DFC_MBXERR_BAD_DEF_CLASS 0x08 796 #define DFC_MBXERR_BAD_MAX_RESPONDER 0x09 797 #define DFC_MBXERR_BAD_MAX_ORIGINATOR 0x0A 798 #define DFC_MBXERR_RPI_REGISTERED 0x0B 799 #define DFC_MBXERR_RPI_FULL 0x0C 800 #define DFC_MBXERR_NO_RESOURCES 0x0D 801 #define DFC_MBXERR_BAD_RCV_LENGTH 0x0E 802 #define DFC_MBXERR_DMA_ERROR 0x0F 803 #define DFC_MBXERR_ERROR 0x10 804 805 #define DFC_MBXERR_OVERTEMP_ERROR 0xFA 806 #define DFC_MBXERR_HARDWARE_ERROR 0xFB 807 #define DFC_MBXERR_DRVR_ERROR 0xFC 808 #define DFC_MBXERR_BUSY 0xFD 809 #define DFC_MBXERR_TIMEOUT 0xFE 810 #define DFC_MBX_NOT_FINISHED 0xFF 811 812 813 814 /* Error codes for library calls */ 815 #define DFC_ERR_GENERAL_ERROR 0x1 816 817 #define DFC_ERR_MBOX_ERROR 0x2 818 #define DFC_ERR_LINK_DOWN 0x2 819 #define DFC_ERR_INCORRECT_VER 0x2 820 #define DFC_ERR_INVALID_ID 0x2 821 #define DFC_ERR_TIMEOUT 0x2 822 #define DFC_ERR_NOT_SUPPORTED 0x2 823 #define DFC_ERR_NPIV_ACTIVE 0x2 824 825 #define DFC_ERR_NO_RPI 0x3 826 #define DFC_ERR_BUFFER_OVERFLOW 0x3 827 #define DFC_ERR_INVALID_LOOPBACK_TYPE 0x3 828 #define DFC_ERR_OVERTEMP 0x3 829 830 #define DFC_ERR_LOOPBACK_BUSY 0x4 831 #define DFC_ERR_INVALID_RESET_TYPE 0x4 832 #define DFC_ERR_MENLO_LINKDOWN 0x4 833 834 #define DFC_ERR_SEQ_TIMEOUT 0x5 835 836 #define DFC_ERR_NO_XMIT 0x6 837 #define DFC_ERR_INVALID_NUMBER 0x6 838 839 #define DFC_ERR_RESET_RECV 0x7 840 841 842 843 844 /* type definitions for GetBindList function */ 845 typedef enum dfc_bindtype 846 { 847 BIND_NONE, 848 BIND_WWNN, 849 BIND_WWPN, 850 BIND_DID, 851 BIND_ALPA 852 } dfc_bindtype_t; 853 854 855 typedef struct dfc_bind_entry 856 { 857 dfc_bindtype_t bind_type; 858 uint32_t scsi_id; 859 uint32_t did; 860 uint8_t wwnn[8]; 861 uint8_t wwpn[8]; 862 uint32_t flags; 863 864 /* Bind Entry flags */ 865 #define DFC_BIND_AUTOMAP 0x1 /* Node is automapped */ 866 #define DFC_BIND_BINDLIST 0x2 /* entry in bind list not mapped */ 867 #define DFC_BIND_MAPPED 0x4 /* Node is mapped to a scsiid */ 868 #define DFC_BIND_UNMAPPED 0x8 /* Node is unmapped */ 869 #define DFC_BIND_NODEVTMO 0x10 /* NODEVTMO flag of the node */ 870 #define DFC_BIND_NOSCSIID 0x20 /* No scsi id is assigned yet */ 871 #define DFC_BIND_RPTLUNST 0x40 /* Node is in report lun cmpl st */ 872 } dfc_bind_entry_t; 873 874 typedef struct dfc_bind_list 875 { 876 uint32_t NumberOfEntries; 877 dfc_bind_entry_t entry[1]; /* Variable length array */ 878 } dfc_bind_list_t; 879 880 881 882 /* Defines for error codes -OLD- */ 883 #define FC_ERROR_BUFFER_OVERFLOW 0xff 884 #define FC_ERROR_RESPONSE_TIMEOUT 0xfe 885 #define FC_ERROR_LINK_UNAVAILABLE 0xfd 886 #define FC_ERROR_INSUFFICIENT_RESOURCES 0xfc 887 #define FC_ERROR_EXISTING_REGISTRATION 0xfb 888 #define FC_ERROR_INVALID_TAG 0xfa 889 #define FC_ERROR_INVALID_WWN 0xf9 890 #define FC_ERROR_CREATEVENT_FAILED 0xf8 891 892 893 894 typedef union dfc_ct_rev 895 { 896 /* Structure is in Big Endian format */ 897 struct 898 { 899 uint32_t Revision:8; 900 uint32_t InId:24; 901 } bits; 902 uint32_t word; 903 } dfc_ct_rev_t; 904 905 typedef union dfc_ct_resp 906 { 907 /* Structure is in Big Endian format */ 908 struct 909 { 910 uint32_t CmdRsp:16; 911 uint32_t Size:16; 912 } bits; 913 uint32_t word; 914 } dfc_ct_resp_t; 915 916 typedef struct dfc_ct_request 917 { 918 /* Structure is in Big Endian format */ 919 dfc_ct_rev_t RevisionId; 920 uint8_t FsType; 921 uint8_t FsSubType; 922 uint8_t Options; 923 uint8_t Rsrvd1; 924 dfc_ct_resp_t CommandResponse; 925 uint8_t Rsrvd2; 926 uint8_t ReasonCode; 927 uint8_t Explanation; 928 uint8_t VendorUnique; 929 } dfc_ct_request_t; 930 931 #define SLI_CT_REVISION 1 932 933 #define FC_FSTYPE_ALL 0xffff /* match on all fsTypes */ 934 935 /* Emulex Vendor-Unique CT Request Command Codes */ 936 #define CT_OP_GSAT 0x0101 /* Get Server Attributes */ 937 #define CT_OP_GHAT 0x0102 /* Get HBA Attributes */ 938 #define CT_OP_GPAT 0x0103 /* Get Port Attributes */ 939 #define CT_OP_GDAT 0x0104 /* Get Driver Attributes */ 940 #define CT_OP_GPST 0x0105 /* Get Port Statistics */ 941 /* 0x0106 is reserved */ 942 #define CT_OP_GDP 0x0107 /* Get Driver Parameters */ 943 #define CT_OP_GDPG 0x0108 /* Get Driver Parameters Global */ 944 #define CT_OP_GEPS 0x0109 /* Get Extended Port Statistics */ 945 #define CT_OP_GLAT 0x010A /* Get Lun Attributes */ 946 947 #define CT_OP_SSAT 0x0111 /* Set Server Attributes */ 948 #define CT_OP_SHAT 0x0112 /* Set HBA Attributes */ 949 #define CT_OP_SPAT 0x0113 /* Set Port Attributes */ 950 #define CT_OP_SDAT 0x0114 /* Set Driver Attributes */ 951 /* 0x0115 is reserved */ 952 /* 0x0116 is reserved */ 953 #define CT_OP_SDP 0x0117 /* Set Driver Parameter */ 954 #define CT_OP_SBBS 0x0118 /* Set Boot Bios State */ 955 956 #define CT_OP_RPST 0x0121 /* Reset Port Statistics */ 957 #define CT_OP_VFW 0x0122 /* Verify Firmware */ 958 #define CT_OP_DFW 0x0123 /* Download Firmware */ 959 #define CT_OP_RES 0x0124 /* Reset HBA */ 960 #define CT_OP_RHD 0x0125 /* Run HBA Diagnostic */ 961 #define CT_OP_UFW 0x0126 /* Upgrade Firmware */ 962 #define CT_OP_RDP 0x0127 /* Reset Driver Parameters */ 963 #define CT_OP_GHDR 0x0128 /* Get HBA Diagnotic Results */ 964 #define CT_OP_CHD 0x0129 /* Cancel HBA Diagnostic */ 965 966 /* 0x0131 is reserved */ 967 /* 0x0132 is reserved */ 968 #define CT_OP_SSR 0x0133 /* Send Software Resource */ 969 970 #define CT_OP_RSAT 0x0141 /* Read SA Table */ 971 #define CT_OP_WSAT 0x0142 /* Write SA Table */ 972 #define CT_OP_RSAH 0x0143 /* Read SA Table Header */ 973 #define CT_OP_WSAH 0x0144 /* Write SA Table Header */ 974 #define CT_OP_RACT 0x0145 /* Read Access Control Table */ 975 #define CT_OP_WACT 0x0146 /* Write Access Control Table */ 976 #define CT_OP_RKT 0x0147 /* Read Key Table Table */ 977 #define CT_OP_WKT 0x0148 /* Write Key Table Table */ 978 #define CT_OP_SSC 0x0149 /* Cause SA Table re-read;sync */ 979 980 #define CT_OP_QHBA 0x0151 /* Query HBA */ 981 #define CT_OP_GST 0x0152 /* Get Status */ 982 983 #define CT_OP_GFTM 0x0161 /* Get FCP Target Mapping */ 984 #define CT_OP_SRL 0x0162 /* SCSI Report Luns */ 985 #define CT_OP_SI 0x0163 /* SCSI Inquiry */ 986 #define CT_OP_SRC 0x0164 /* SCSI Read Capacity */ 987 988 #define CT_OP_GPB 0x0171 /* Get FCP Persistent Binding */ 989 #define CT_OP_SPB 0x0172 /* Set FCP Persistent Binding */ 990 #define CT_OP_RPB 0x0173 /* Remove FCP Persistent Binding */ 991 #define CT_OP_RAPB 0x0174 /* Remove All FCP Persistent Bindings */ 992 #define CT_OP_GBC 0x0175 /* Get Binding Capability */ 993 #define CT_OP_GBS 0x0176 /* Get Binding Support */ 994 #define CT_OP_SBS 0x0177 /* Set Binding Support */ 995 #define CT_OP_GANI 0x0178 /* Get All Nodes Info */ 996 #define CT_OP_GRV 0x0179 /* Get Range Value for Bus#, Target#, Lun# */ 997 #define CT_OP_GAPBS 0x017A /* Get AutoPB service state */ 998 /* (AutoPilotManager) */ 999 #define CT_OP_APBC 0x017B /* Configure AutoPB service */ 1000 /* (AutoPilotManager) */ 1001 1002 #define CT_OP_GDT 0x0180 /* Get Driver Type */ 1003 #define CT_OP_GDLMI 0x0181 /* Get Drive Letter Mapping */ 1004 /* Information [GDLM] */ 1005 #define CT_OP_GANA 0x0182 /* Get All Node Addresses */ 1006 #define CT_OP_GDLV 0x0183 /* Get Driver Library Version */ 1007 #define CT_OP_GWUP 0x0184 /* Get Adapter Wakeup Parameters */ 1008 #define CT_OP_GLM 0x0185 /* Get Adapter Loopmap */ 1009 #define CT_OP_GABS 0x0186 /* Get Adapter Beacon State */ 1010 #define CT_OP_SABS 0x0187 /* Set Adapter Beacon State */ 1011 #define CT_OP_RPR 0x0188 /* Read Adapter PCI Registers */ 1012 1013 1014 #ifdef NPIV_SUPPORT 1015 1016 /* NPIV return codes */ 1017 #define DFC_NPIV_SUCCESS 0 1018 #define DFC_NPIV_GENERAL_ERROR 1 1019 #define DFC_NPIV_NOT_SUPPORTED 2 1020 #define DFC_NPIV_NO_RESOURCES 3 1021 #define DFC_NPIV_INVALID_HANDLE 3 1022 #define DFC_NPIV_ILLEGAL_WWPN 4 1023 #define DFC_NPIV_TOO_MANY_VPORTS 4 1024 #define DFC_NPIV_ILLEGAL_WWN 5 1025 #define DFC_NPIV_BUSY 5 1026 #define DFC_NPIV_INVALID_WWN 6 1027 #define DFC_NPIV_LINK_DOWN 7 1028 #define DFC_NPIV_MORE_DATA 7 1029 #define DFC_NPIV_FABRIC_NOT_SUPPORTED 8 1030 #define DFC_NPIV_FABRIC_OUT_OF_RESOURCE 9 1031 #define DFC_NPIV_INVALID_ACCESS_KEY 10 1032 #define DFC_NPIV_INVALID_HANDLE_AT_CREATE 11 1033 #define DFC_NPIV_UNSUPPORTED_OPTION 12 1034 1035 typedef struct dfc_vport_QoS 1036 { 1037 uint32_t resv; 1038 } dfc_vport_QoS_t; 1039 1040 1041 /* VPORT type */ 1042 #define VPORT_TYPE_PHYSICAL 0 1043 #define VPORT_TYPE_VIRTUAL 1 1044 1045 /* VPORT States */ 1046 #define VPORT_STATE_UNKNOWN 0 1047 #define VPORT_STATE_LINKDOWN 1 1048 #define VPORT_STATE_INIT 2 1049 #define VPORT_STATE_NO_FABRIC_SUPPORT 3 1050 #define VPORT_STATE_NO_FABRIC_RESOURCE 4 1051 #define VPORT_STATE_FABRIC_LOGOUT 5 1052 #define VPORT_STATE_FABRIC_REJECT_WWN 6 1053 #define VPORT_STATE_FABRIC_LOGIN_FAIL 7 1054 #define VPORT_STATE_ACTIVE 8 1055 #define VPORT_STATE_AUTH_FAILED 9 1056 1057 /* VPORT Options */ 1058 #define VPORT_OPT_AUTORETRY 0x00000001 1059 #define VPORT_OPT_AUTOWWN 0x00000002 1060 #define VPORT_OPT_ACTIVATE 0x00000004 1061 1062 #define VPORT_OPT_SAVE_CREATE_ONLY 0x00000000 1063 #define VPORT_OPT_SAVE_CREATE_UPDATE 0x00000010 1064 #define VPORT_OPT_SAVE_UPDATE_ONLY 0x00000018 1065 #define VPORT_OPT_SAVE_MASK 0x00000018 1066 1067 #define VPORT_OPT_RESTRICT 0x00000020 1068 #define VPORT_OPT_UNRESTRICT 0x00000040 1069 #define VPORT_OPT_RESTRICT_MASK 0x00000060 1070 1071 #define VPORT_OPT_FAILOVER 0x00000080 1072 1073 /* Check list bit-mapped value */ 1074 #define CL_NPIV_PARM_ENABLE 0x00000001 1075 #define CL_SLI3_ENABLE 0x00000002 1076 #define CL_HBA_SUPPORT_NPIV 0x00000004 1077 #define CL_HBA_HAS_RESOURCES 0x00000008 1078 #define CL_HBA_LINKUP 0x00000010 1079 #define CL_P2P_TOPOLOGY 0x00000020 1080 #define CL_FABRIC_SUPPORTS_NPIV 0x00000040 1081 #define CL_FABRIC_HAS_RESOURCES 0x00000080 1082 #define CL_NPIV_READY 0x000000FF 1083 1084 1085 1086 1087 #define DFC_VPORT_ATTR_VERSION 2 1088 typedef struct dfc_vport_attrs 1089 { 1090 uint8_t version; /* 2 = version of this structure, */ 1091 /* for compatibility check */ 1092 uint8_t reserved1[3]; 1093 1094 uint8_t wwpn[8]; /* virtual port WWPN */ 1095 uint8_t wwnn[8]; /* virtual port WWNN */ 1096 char name[256]; /* name to be register with the */ 1097 /* fabric */ 1098 1099 uint32_t options; 1100 1101 uint32_t portFcId; /* D-ID; set when the N-port is */ 1102 /* created successfully */ 1103 1104 uint8_t state; /* VPORT state */ 1105 uint8_t restrictLogin; 1106 uint8_t reserved2[2]; 1107 uint64_t buf; /* Used for VPI */ 1108 1109 uint8_t fabric_wwn[8]; /* Fabric WWN (WWNN) */ 1110 uint32_t checklist; 1111 uint8_t accessKey[32]; 1112 } dfc_vport_attrs_t; 1113 1114 1115 typedef struct dfc_vport_entry 1116 { 1117 uint8_t wwpn[8]; /* wwpn of the virtual port */ 1118 uint8_t wwnn[8]; /* wwnn of the virtual port */ 1119 uint32_t PortFcId; /* FC port ID assigned to this */ 1120 /* virtual port */ 1121 } dfc_vport_entry_t; 1122 1123 1124 typedef struct dfc_vport_entry_list 1125 { 1126 uint32_t NumberOfEntries; 1127 dfc_vport_entry_t entry[MAX_VPORTS]; 1128 } dfc_vport_entry_list_t; 1129 1130 1131 typedef struct dfc_vport_nodeinfo_entry 1132 { 1133 uint32_t bind_type; 1134 #define VPORT_NODE_BINDDID 0x0000 1135 #define VPORT_NODE_BINDWWNN 0x0001 1136 #define VPORT_NODE_BINDWWPN 0x0002 1137 #define VPORT_NODE_AUTOMAP 0x0004 1138 #define VPORT_NODE_UNMASK_ALL_LUN 0x0008 1139 #define VPORT_NODE_DISABLE_LUN_AUTOMAP 0x0010 1140 #define VPORT_NODE_ALPA 0x0020 1141 1142 HBA_SCSIID scsiId; 1143 HBA_FCPID fcpId; 1144 1145 uint32_t nodeState; 1146 #define VPORT_NODESTATE_EXIST 0x0001 1147 #define VPORT_NODESTATE_READY 0x0002 1148 #define VPORT_NODESTATE_LINKDOWN 0x0004 1149 #define VPORT_NODESTATE_UNMAPPED 0x0008 1150 #define VPORT_NODESTATE_BOUND 0x0010 1151 1152 uint32_t reserved; 1153 } dfc_vport_nodeinfo_entry_t; 1154 1155 typedef struct dfc_vport_get_nodeinfo 1156 { 1157 uint32_t NumberOfEntries; /* number of nodes */ 1158 dfc_vport_nodeinfo_entry_t entry[MAX_NODES]; /* start of array */ 1159 } dfc_vport_get_nodeinfo_t; 1160 1161 1162 typedef struct dfc_vport_resource 1163 { 1164 uint32_t vpi_max; 1165 uint32_t vpi_inuse; 1166 uint32_t rpi_max; 1167 uint32_t rpi_inuse; 1168 } dfc_vport_resource_t; 1169 1170 1171 typedef struct dfc_vlinkinfo 1172 { 1173 uint32_t api_versions; 1174 1175 uint8_t linktype; 1176 uint8_t state; 1177 uint8_t fail_reason; 1178 uint8_t prev_fail_reason; 1179 #define VPORT_FAIL_UNKNOWN 0 1180 #define VPORT_FAIL_LINKDOWN 1 1181 #define VPORT_FAIL_FAB_UNSUPPORTED 2 1182 #define VPORT_FAIL_FAB_NORESOURCES 3 1183 #define VPORT_FAIL_FAB_LOGOUT 4 1184 #define VPORT_FAIL_HBA_NORESOURCES 5 1185 1186 uint8_t wwnn[8]; 1187 uint8_t wwpn[8]; 1188 1189 void *vlink; 1190 1191 uint32_t vpi_max; 1192 uint32_t vpi_inuse; 1193 uint32_t rpi_max; 1194 uint32_t rpi_inuse; 1195 } dfc_vlinkinfo_t; 1196 1197 #endif /* NPIV_SUPPORT */ 1198 1199 1200 #ifdef DHCHAP_SUPPORT 1201 1202 /* DHCHAP return code */ 1203 #define DFC_AUTH_STATUS_NOT_CONFIGURED 0x8001 1204 #define DFC_AUTH_STATUS_AUTH_FAILED_NO_SA_FOUND 0x8002 1205 #define DFC_AUTH_STATUS_AUTH_INIT_OK_AUTH_FAILED 0x8003 1206 #define DFC_AUTH_STATUS_COMPARE_FAILED 0x8004 1207 #define DFC_AUTH_STATUS_WWN_NOT_FOUND 0x8005 1208 #define DFC_AUTH_STATUS_PASSWORD_INVALID 0x8006 1209 #define DFC_AUTH_STATUS_INVALID_ENTITY 0x8007 1210 #define DFC_AUTH_STATUS_ENTITY_NOT_ACTIVE 0x8008 1211 #define DFC_AUTH_STATUS_INVALID_OPERATION 0x8009 1212 #define DFC_AUTH_STATUS_OUT_OF_RESOURCES 0x800a 1213 #define DFC_AUTH_STATUS_AUTHENTICATION_GOINGON 0x800b 1214 #define DFC_AUTH_STATUS_INVALID_BOARD_NO 0x800c 1215 #define DFC_AUTH_STATUS_IO_ERROR 0x800d 1216 #define DFC_AUTH_STATUS_CREATE_STORKEY_ERROR 0x800e 1217 #define DFC_AUTH_STATUS_CREATE_PARMKEY_ERROR 0x800f 1218 #define DFC_AUTH_STATUS_CREATE_AUTHKEY_ERROR 0x8010 1219 #define DFC_AUTH_STATUS_LOCAL_REMOTE_PASSWORD_SAME 0x8011 1220 #define DFC_AUTH_STATUS_CREATE_BORDKEY_ERROR 0x8020 1221 #define DFC_AUTH_STATUS_DRVTYPE_NOT_SUPPORTED 0x8030 1222 #define DFC_AUTH_STATUS_AUTHENTICATION_NOT_SUPPORTED 0x8031 1223 #define DFC_AUTH_STATUS_GENERAL_ERROR 0x8032 1224 #define DFC_AUTH_STATUS_CONFIG_NOT_FOUND 0x8034 1225 #define DFC_AUTH_STATUS_NOT_PRIVILEGE_USER 0x8040 1226 1227 1228 typedef struct dfc_fcsp_config 1229 { 1230 HBA_WWN lwwpn; 1231 HBA_WWN rwwpn; 1232 1233 uint16_t auth_tov; /* seconds */ 1234 #define DFC_AUTH_TOV_MIN 20 1235 #define DFC_AUTH_TOV_MAX 1000 1236 #define DFC_AUTH_TOV_DEFAULT 45 1237 1238 uint8_t auth_mode; 1239 #define DFC_AUTH_MODE_DISABLED 1 1240 #define DFC_AUTH_MODE_ACTIVE 2 1241 #define DFC_AUTH_MODE_PASSIVE 3 1242 #define DFC_AUTH_MODE_DEFAULT DFC_AUTH_MODE_DISABLED 1243 1244 uint8_t auth_bidir:1; 1245 #define DFC_AUTH_BIDIR_DISABLED 0 1246 #define DFC_AUTH_BIDIR_ENABLED 1 1247 #define DFC_AUTH_BIDIR_DEFAULT DFC_AUTH_BIDIR_DISABLED 1248 uint8_t reserved:7; 1249 1250 uint8_t type_priority[4]; 1251 #define DFC_AUTH_TYPE_DHCHAP 1 /* Only one currently supported */ 1252 #define DFC_AUTH_TYPE_FCAP 2 1253 #define DFC_AUTH_TYPE_FCPAP 3 1254 #define DFC_AUTH_TYPE_KERBEROS 4 1255 #define DFC_AUTH_TYPE_MAX 4 1256 #define DFC_AUTH_TYPE_DEFAULT0 DFC_AUTH_TYPE_DHCHAP 1257 #define DFC_AUTH_TYPE_DEFAULT1 0 1258 #define DFC_AUTH_TYPE_DEFAULT2 0 1259 #define DFC_AUTH_TYPE_DEFAULT3 0 1260 1261 uint8_t hash_priority[4]; 1262 #define DFC_AUTH_HASH_MD5 1 1263 #define DFC_AUTH_HASH_SHA1 2 1264 #define DFC_AUTH_HASH_MAX 2 1265 #define DFC_AUTH_HASH_DEFAULT0 DFC_AUTH_HASH_MD5 1266 #define DFC_AUTH_HASH_DEFAULT1 DFC_AUTH_HASH_SHA1 1267 #define DFC_AUTH_HASH_DEFAULT2 0 1268 #define DFC_AUTH_HASH_DEFAULT3 0 1269 1270 uint8_t group_priority[8]; 1271 #define DFC_AUTH_GROUP_NULL 1 1272 #define DFC_AUTH_GROUP_1024 2 1273 #define DFC_AUTH_GROUP_1280 3 1274 #define DFC_AUTH_GROUP_1536 4 1275 #define DFC_AUTH_GROUP_2048 5 1276 #define DFC_AUTH_GROUP_MAX 5 1277 1278 #define DFC_AUTH_GROUP_DEFAULT0 DFC_AUTH_GROUP_NULL 1279 #define DFC_AUTH_GROUP_DEFAULT1 DFC_AUTH_GROUP_1024 1280 #define DFC_AUTH_GROUP_DEFAULT2 DFC_AUTH_GROUP_1280 1281 #define DFC_AUTH_GROUP_DEFAULT3 DFC_AUTH_GROUP_1536 1282 #define DFC_AUTH_GROUP_DEFAULT4 DFC_AUTH_GROUP_2048 1283 #define DFC_AUTH_GROUP_DEFAULT5 0 1284 #define DFC_AUTH_GROUP_DEFAULT6 0 1285 #define DFC_AUTH_GROUP_DEFAULT7 0 1286 1287 uint32_t reauth_tov; /* minutes */ 1288 #define DFC_REAUTH_TOV_MIN 0 1289 #define DFC_REAUTH_TOV_MAX 7200 1290 #define DFC_REAUTH_TOV_DEFAULT 1440 1291 } dfc_fcsp_config_t; 1292 1293 1294 typedef struct dfc_password 1295 { 1296 uint16_t length; 1297 #define DFC_PASSWORD_LENGTH_MIN 8 1298 #define DFC_PASSWORD_LENGTH_MAX 128 1299 1300 uint16_t type; 1301 #define DFC_PASSWORD_TYPE_ASCII 1 1302 #define DFC_PASSWORD_TYPE_BINARY 2 1303 #define DFC_PASSWORD_TYPE_IGNORE 3 1304 1305 uint8_t password[DFC_PASSWORD_LENGTH_MAX]; 1306 } dfc_password_t; 1307 1308 typedef struct dfc_auth_password 1309 { 1310 HBA_WWN lwwpn; 1311 HBA_WWN rwwpn; 1312 1313 dfc_password_t lpw; 1314 dfc_password_t rpw; 1315 1316 dfc_password_t lpw_new; 1317 dfc_password_t rpw_new; 1318 } dfc_auth_password_t; 1319 1320 1321 typedef struct dfc_auth_cfglist 1322 { 1323 uint32_t cnt; 1324 HBA_WWN rwwpn[1]; 1325 } dfc_auth_cfglist_t; 1326 1327 1328 typedef struct dfc_auth_status 1329 { 1330 HBA_WWN lwwpn; 1331 HBA_WWN rwwpn; 1332 1333 uint8_t auth_state; 1334 #define DFC_AUTH_STATE_OFF 1 1335 #define DFC_AUTH_STATE_INP 2 1336 #define DFC_AUTH_STATE_ON 3 1337 #define DFC_AUTH_STATE_FAILED 4 1338 1339 uint8_t auth_failReason; 1340 #define DFC_AUTH_FAIL_GENERIC 1 1341 #define DFC_AUTH_FAIL_ELS_TMO 2 1342 #define DFC_AUTH_FAIL_XACT_TMO 3 1343 #define DFC_AUTH_FAIL_LS_RJT 4 1344 #define DFC_AUTH_FAIL_BSY_LS_RJT 5 1345 #define DFC_AUTH_FAIL_REJECTED 6 1346 1347 uint8_t type_priority; 1348 uint8_t group_priority; 1349 1350 uint8_t hash_priority; 1351 uint8_t localAuth :1; 1352 uint8_t remoteAuth :1; 1353 uint8_t pad :6; 1354 uint16_t reserved0; 1355 1356 uint32_t time_from_last_auth; /* seconds */ 1357 uint32_t time_until_next_auth; /* seconds */ 1358 1359 uint32_t reserved1; 1360 uint32_t reserved2; 1361 } dfc_auth_status_t; 1362 1363 #endif /* DHCHAP_SUPPORT */ 1364 1365 /* 1366 * Start of FCP specific structures 1367 */ 1368 1369 #ifndef MAX_FCP_SNS 1370 typedef struct emlxs_fcp_rsp 1371 { 1372 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 1373 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 1374 1375 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 1376 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 1377 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 1378 #define RSP_LEN_VALID 0x01 /* bit 0 */ 1379 #define SNS_LEN_VALID 0x02 /* bit 1 */ 1380 #define RESID_OVER 0x04 /* bit 2 */ 1381 #define RESID_UNDER 0x08 /* bit 3 */ 1382 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 1383 #define SCSI_STAT_GOOD 0x00 1384 #define SCSI_STAT_CHECK_COND 0x02 1385 #define SCSI_STAT_COND_MET 0x04 1386 #define SCSI_STAT_BUSY 0x08 1387 #define SCSI_STAT_INTERMED 0x10 1388 #define SCSI_STAT_INTERMED_CM 0x14 1389 #define SCSI_STAT_RES_CNFLCT 0x18 1390 #define SCSI_STAT_CMD_TERM 0x22 1391 #define SCSI_STAT_QUE_FULL 0x28 1392 #define SCSI_STAT_ACA_ACTIVE 0x30 1393 #define SCSI_STAT_TASK_ABORT 0x40 1394 1395 uint32_t rspResId; /* Residual xfer if RESID_xxxx set in */ 1396 /* fcpStatus2 */ 1397 /* Received in Big Endian format */ 1398 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 1399 /* received in Big Endian format */ 1400 uint32_t rspRspLen; /* Length of FCP response data in */ 1401 /* fcpRspInfo */ 1402 /* Received In Big Endian format */ 1403 1404 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 1405 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 1406 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 1407 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 1408 1409 #define RSP_NO_FAILURE 0x00 1410 #define RSP_DATA_BURST_ERR 0x01 1411 #define RSP_CMD_FIELD_ERR 0x02 1412 #define RSP_RO_MISMATCH_ERR 0x03 1413 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 1414 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 1415 1416 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 1417 1418 /* 1419 * Define maximum size of SCSI Sense buffer. 1420 * Seagate never issues more than 18 bytes of Sense data. 1421 */ 1422 #define MAX_FCP_SNS 128 1423 uint8_t rspSnsInfo[MAX_FCP_SNS]; 1424 } emlxs_fcp_rsp; 1425 typedef emlxs_fcp_rsp FCP_RSP; 1426 #endif /* MAX_FCP_SNS */ 1427 1428 1429 #ifndef FC_LUN_SHIFT 1430 typedef struct emlxs_fcp_cmd 1431 { 1432 uint32_t fcpLunMsl; /* most significant word (32 bits) */ 1433 uint32_t fcpLunLsl; /* least significant word (32 bits) */ 1434 1435 /* 1436 * # of bits to shift lun id to end up in right payload word, 1437 * little endian = 8, big = 16. 1438 */ 1439 #ifdef EMLXS_LITTLE_ENDIAN 1440 #define FC_LUN_SHIFT 8 1441 #define FC_ADDR_MODE_SHIFT 0 1442 #endif 1443 #ifdef EMLXS_BIG_ENDIAN 1444 #define FC_LUN_SHIFT 16 1445 #define FC_ADDR_MODE_SHIFT 24 1446 #endif 1447 1448 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 1449 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 1450 #define SIMPLE_Q 0x00 1451 #define HEAD_OF_Q 0x01 1452 #define ORDERED_Q 0x02 1453 #define ACA_Q 0x04 1454 #define UNTAGGED 0x05 1455 1456 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 1457 /* codes */ 1458 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 1459 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 1460 #define LUN_RESET 0x10 /* bit 4 */ 1461 #define TARGET_RESET 0x20 /* bit 5 */ 1462 #define CLEAR_ACA 0x40 /* bit 6 */ 1463 #define TERMINATE_TASK 0x80 /* bit 7 */ 1464 1465 uint8_t fcpCntl3; 1466 #define WRITE_DATA 0x01 /* Bit 0 */ 1467 #define READ_DATA 0x02 /* Bit 1 */ 1468 1469 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 1470 uint32_t fcpDl; /* Total transfer length */ 1471 } emlxs_fcp_cmd_t; 1472 typedef emlxs_fcp_cmd_t FCP_CMND; 1473 #endif /* FC_LUN_SHIFT */ 1474 1475 1476 /* 1477 * Used by libdfc (SendScsiCmd, SendFcpCmd, DFC_SendScsiCmdV2, DFC_SendFcpCmdV2 1478 * and emlxs_dfc_send_scsi_fcp functions 1479 */ 1480 typedef struct dfc_send_scsi_fcp_cmd_info 1481 { 1482 HBA_WWN src_wwn; 1483 HBA_WWN dst_wwn; 1484 uint32_t cnt1; 1485 uint32_t cnt2; 1486 uint32_t ver; 1487 } dfc_send_scsi_fcp_cmd_info_t; 1488 1489 #define SCSI_RSP_CNT(x) x.cnt1 1490 #define SCSI_SNS_CNT(x) x.cnt2 1491 #define FC_DATA_CNT(x) x.cnt1 1492 #define FC_RSP_CNT(x) x.cnt2 1493 #define DFC_SEND_SCSI_FCP_V1 1 1494 #define DFC_SEND_SCSI_FCP_V2 2 1495 1496 #ifdef __cplusplus 1497 } 1498 #endif 1499 1500 #endif /* _EMLXS_DFCLIB_H */ 1501