1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_DFC_H 28 #define _EMLXS_DFC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/fibre-channel/fcio.h> 35 #include <emlxs_fcio.h> 36 37 #define DFC_REV 1 38 39 #ifdef DHCHAP_SUPPORT 40 #undef DFC_REV 41 #define DFC_REV 2 /* DHCHAP_SUPPORT */ 42 #endif /* DHCHAP_SUPPORT */ 43 44 #undef DFC_REV 45 #define DFC_REV 3 /* NPIV_SUPPORT */ 46 47 48 typedef struct dfc 49 { 50 uint32_t cmd; 51 uint32_t flag; 52 53 void *buf1; 54 uint32_t buf1_size; 55 uint32_t data1; 56 57 void *buf2; 58 uint32_t buf2_size; 59 uint32_t data2; 60 61 void *buf3; 62 uint32_t buf3_size; 63 uint32_t data3; 64 65 void *buf4; 66 uint32_t buf4_size; 67 uint32_t data4; 68 } dfc_t; 69 70 71 /* 72 * 32 bit varient of dfc_t to be used only in the driver and NOT applications 73 */ 74 typedef struct dfc32 75 { 76 uint32_t cmd; 77 uint32_t flag; 78 79 uint32_t buf1; 80 uint32_t buf1_size; 81 uint32_t data1; 82 83 uint32_t buf2; 84 uint32_t buf2_size; 85 uint32_t data2; 86 87 uint32_t buf3; 88 uint32_t buf3_size; 89 uint32_t data3; 90 91 uint32_t buf4; 92 uint32_t buf4_size; 93 uint32_t data4; 94 95 } dfc32_t; 96 97 98 #ifdef SAN_DIAG_SUPPORT 99 typedef struct sd_bucket_info 100 { 101 uint16_t type; 102 uint16_t search_type; 103 uint32_t base; 104 uint32_t step; 105 uint16_t state; 106 uint64_t values[SD_IO_LATENCY_MAX_BUCKETS]; 107 } sd_bucket_info_t; 108 #endif 109 110 /* Valid dfc.dfc_cmd codes (DFC_REV=1) */ 111 #define EMLXS_GET_HBAINFO 1 112 #define EMLXS_GET_IOINFO 2 113 #define EMLXS_GET_LINKINFO 3 114 #define EMLXS_GET_NODEINFO 4 115 #define EMLXS_GET_EVENTINFO 5 116 #define EMLXS_GET_REV 6 117 #define EMLXS_GET_DUMPREGION 7 118 #define EMLXS_GET_HBASTATS 8 119 #define EMLXS_GET_DRVSTATS 9 120 121 /* FCIO_SUPPORT */ 122 #define EMLXS_FCIO_CMD 10 123 124 #define EMLXS_GET_CFG 15 125 #define EMLXS_SET_CFG 16 126 #define EMLXS_GET_EVENT 17 127 #define EMLXS_SET_EVENT 18 128 129 #define EMLXS_SEND_MBOX 20 130 #define EMLXS_SEND_ELS 21 131 #define EMLXS_SEND_CT 22 132 #define EMLXS_SEND_CT_RSP 23 133 #define EMLXS_SEND_MENLO 24 134 #define EMLXS_SEND_SCSI 25 135 136 #define EMLXS_SET_DIAG 30 137 #define EMLXS_LOOPBACK_MODE 31 138 #define EMLXS_LOOPBACK_TEST 32 139 140 #define EMLXS_READ_PCI 40 141 #define EMLXS_WRITE_PCI 41 142 #define EMLXS_WRITE_FLASH 42 143 #define EMLXS_READ_FLASH 43 144 #define EMLXS_READ_MEM 44 145 #define EMLXS_WRITE_MEM 45 146 #define EMLXS_WRITE_CTLREG 46 147 #define EMLXS_READ_CTLREG 47 148 149 150 /* NPIV_SUPPORT */ 151 #define EMLXS_CREATE_VPORT 50 152 #define EMLXS_DESTROY_VPORT 51 153 #define EMLXS_GET_VPORTINFO 52 154 #define EMLXS_NPIV_RESOURCE 53 155 #define EMLXS_NPIV_TEST 54 156 157 /* DHCHAP_SUPPORT */ 158 #define EMLXS_INIT_AUTH 60 159 #define EMLXS_GET_AUTH_CFG 61 160 #define EMLXS_SET_AUTH_CFG 62 161 #define EMLXS_GET_AUTH_PASSWORD 63 162 #define EMLXS_SET_AUTH_PASSWORD 64 163 #define EMLXS_GET_AUTH_STATUS 65 164 #define EMLXS_GET_AUTH_CFG_TABLE 66 165 #define EMLXS_GET_AUTH_KEY_TABLE 67 166 167 /* SFCT_SUPPORT */ 168 #define EMLXS_GET_FCTSTAT 70 169 170 #define EMLXS_GET_PERSIST_LINKDOWN 71 171 #define EMLXS_SET_PERSIST_LINKDOWN 72 172 173 /* FCOE_SUPPORT */ 174 #define EMLXS_GET_FCOE_FCFLIST 80 175 #define EMLXS_SEND_MBOX4 81 176 #define EMLXS_RD_BE_FCF 82 177 #define EMLXS_SET_BE_DCBX 83 178 #define EMLXS_GET_BE_DCBX 84 179 #define EMLXS_GET_QOS 85 180 181 /* SAN DIAG SUPPORT */ 182 #define EMLXS_SD_SET_BUCKET 100 183 #define EMLXS_SD_START_DATA_COLLECTION 101 184 #define EMLXS_SD_STOP_DATA_COLLECTION 102 185 #define EMLXS_SD_RESET_DATA_COLLECTION 103 186 #define EMLXS_SD_GET_DATA 104 187 #define EMLXS_SD_DESTROY_BUCKET 105 188 #define EMLXS_SD_GET_BUCKET 106 189 #define EMLXS_SD_SET_EVENT 107 190 #define EMLXS_SD_GET_EVENT 108 191 192 /* EMLXS_SET_AUTH_CFG - flags */ 193 #define EMLXS_AUTH_CFG_ADD 0 194 #define EMLXS_AUTH_CFG_DELETE 1 195 196 /* ERROR Codes */ 197 #define DFC_ERRNO_START 0x200 198 199 #define DFC_SUCCESS 0 200 #define DFC_SYS_ERROR (DFC_ERRNO_START + 1) /* General system err */ 201 #define DFC_DRV_ERROR (DFC_ERRNO_START + 2) /* General driver err */ 202 #define DFC_HBA_ERROR (DFC_ERRNO_START + 3) /* General HBA err */ 203 #define DFC_IO_ERROR (DFC_ERRNO_START + 4) /* General IO err */ 204 205 #define DFC_ARG_INVALID (DFC_ERRNO_START + 5) /* Invalid Argument */ 206 #define DFC_ARG_MISALIGNED (DFC_ERRNO_START + 6) /* Misaligned Argument */ 207 #define DFC_ARG_NULL (DFC_ERRNO_START + 7) /* NULL Argument */ 208 #define DFC_ARG_TOOSMALL (DFC_ERRNO_START + 8) /* Argument too small */ 209 #define DFC_ARG_TOOBIG (DFC_ERRNO_START + 9) /* Argument too big */ 210 211 #define DFC_COPYIN_ERROR (DFC_ERRNO_START + 10) /* DDI copyin err */ 212 #define DFC_COPYOUT_ERROR (DFC_ERRNO_START + 11) /* DDI copyout err */ 213 214 #define DFC_TIMEOUT (DFC_ERRNO_START + 12) /* Resource timeout */ 215 #define DFC_SYSRES_ERROR (DFC_ERRNO_START + 13) /* Out of sys resource */ 216 #define DFC_DRVRES_ERROR (DFC_ERRNO_START + 14) /* Out of drv resource */ 217 #define DFC_HBARES_ERROR (DFC_ERRNO_START + 15) /* Out of HBA resource */ 218 219 #define DFC_OFFLINE_ERROR (DFC_ERRNO_START + 16) /* Driver offline */ 220 #define DFC_ONLINE_ERROR (DFC_ERRNO_START + 17) /* Driver offline */ 221 222 /* NPIV_SUPPORT */ 223 #define DFC_NPIV_DISABLED (DFC_ERRNO_START + 18) /* NPIV disabled */ 224 #define DFC_NPIV_UNSUPPORTED (DFC_ERRNO_START + 19) /* NPIV not supported */ 225 #define DFC_NPIV_ACTIVE (DFC_ERRNO_START + 20) /* NPIV active */ 226 227 /* FCOE_SUPPORT */ 228 #define DFC_FCOE_NOTSUPPORTED (DFC_ERRNO_START + 21) /* FCoE not supported */ 229 230 /* DHCHAP_SUPPORT */ 231 #define DFC_AUTH_NOT_CONFIGURED (DFC_ERRNO_START + 30) 232 #define DFC_AUTH_FAILED_NO_SA_FOUND (DFC_ERRNO_START + 31) 233 #define DFC_AUTH_INIT_OK_AUTH_FAILED (DFC_ERRNO_START + 32) 234 #define DFC_AUTH_COMPARE_FAILED (DFC_ERRNO_START + 33) 235 #define DFC_AUTH_WWN_NOT_FOUND (DFC_ERRNO_START + 34) 236 #define DFC_AUTH_PASSWORD_INVALID (DFC_ERRNO_START + 35) 237 #define DFC_AUTH_INVALID_ENTITY (DFC_ERRNO_START + 36) 238 #define DFC_AUTH_ENTITY_NOT_ACTIVE (DFC_ERRNO_START + 37) 239 #define DFC_AUTH_INVALID_OPERATION (DFC_ERRNO_START + 38) 240 #define DFC_AUTH_AUTHENTICATION_GOINGON (DFC_ERRNO_START + 39) 241 #define DFC_AUTH_CREATE_STORKEY_ERROR (DFC_ERRNO_START + 40) 242 #define DFC_AUTH_CREATE_PARMKEY_ERROR (DFC_ERRNO_START + 41) 243 #define DFC_AUTH_CREATE_AUTHKEY_ERROR (DFC_ERRNO_START + 42) 244 #define DFC_AUTH_CREATE_BORDKEY_ERROR (DFC_ERRNO_START + 43) 245 #define DFC_AUTH_AUTHENTICATION_NOT_SUPPORTED (DFC_ERRNO_START + 44) 246 #define DFC_AUTH_AUTHENTICATION_DISABLED (DFC_ERRNO_START + 45) 247 #define DFC_AUTH_CONFIG_NOT_FOUND (DFC_ERRNO_START + 47) 248 #define DFC_AUTH_LOCAL_REMOTE_PWD_EQUAL (DFC_ERRNO_START + 48) 249 250 /* MENLO_SUPPORT */ 251 #define DFC_INVALID_ADAPTER (DFC_ERRNO_START + 50) 252 #define DFC_RSP_BUF_OVERRUN (DFC_ERRNO_START + 51) 253 #define DFC_LINKDOWN_ERROR (DFC_ERRNO_START + 52) 254 255 /* SAN_DIAG_SUPPORT */ 256 #define DFC_SD_STAT_START (DFC_ERRNO_START + 60) 257 258 #define DFC_SD_OK (DFC_ERRNO_START + 60) 259 #define DFC_SD_ERROR_GENERIC (DFC_ERRNO_START + 61) 260 #define DFC_SD_ERROR_INVALID_ARG (DFC_ERRNO_START + 62) 261 #define DFC_SD_ERROR_INVALID_BOARD_ID (DFC_ERRNO_START + 63) 262 #define DFC_SD_ERROR_INVALID_PORT (DFC_ERRNO_START + 64) 263 #define DFC_SD_ERROR_NOT_SUPPORTED (DFC_ERRNO_START + 65) 264 #define DFC_SD_ERROR_CATEGORY_NOT_SUPPORTED (DFC_ERRNO_START + 66) 265 #define DFC_SD_ERROR_SUBCAT_NOT_SUPPORTED (DFC_ERRNO_START + 67) 266 #define DFC_SD_ERROR_MORE_DATA_AVAIL (DFC_ERRNO_START + 68) 267 #define DFC_SD_ERROR_EVENT_ALREADY_REG (DFC_ERRNO_START + 69) 268 #define DFC_SD_ERROR_NO_ACTIVE_REG (DFC_ERRNO_START + 70) 269 #define DFC_SD_ERROR_ARG_MISSING (DFC_ERRNO_START + 71) 270 #define DFC_SD_ERROR_NO_MEM (DFC_ERRNO_START + 72) 271 #define DFC_SD_ERROR_BUCKET_NOT_SET (DFC_ERRNO_START + 73) 272 #define DFC_SD_ERROR_REG_HANDLE (DFC_ERRNO_START + 74) 273 #define DFC_SD_ERROR_INVALID_SEARCH_TYPE (DFC_ERRNO_START + 75) 274 #define DFC_SD_ERROR_FUNCTION_NOT_SUPPORTED (DFC_ERRNO_START + 76) 275 #define DFC_SD_ERROR_OUT_OF_HANDLES (DFC_ERRNO_START + 77) 276 #define DFC_SD_ERROR_LIB_NOT_INIT (DFC_ERRNO_START + 78) 277 #define DFC_SD_ERROR_DATA_COLLECTION_ACTIVE (DFC_ERRNO_START + 79) 278 #define DFC_SD_ERROR_DATA_COLLECTION_NOT_ACTIVE (DFC_ERRNO_START + 80) 279 280 281 #define DFC_ERRNO_END (DFC_ERRNO_START + 128) 282 283 typedef struct dfc_hbainfo 284 { 285 char vpd_serial_num[32]; 286 char vpd_part_num[32]; 287 char vpd_port_num[20]; 288 char vpd_eng_change[32]; 289 char vpd_manufacturer[80]; 290 char vpd_model[80]; 291 char vpd_model_desc[256]; 292 char vpd_prog_types[256]; 293 char vpd_id[80]; 294 295 uint32_t flags; 296 #define HBA_FLAG_SBUS 0x00000001 297 #define HBA_FLAG_OFFLINE 0x00000002 298 #define HBA_FLAG_NPIV 0x00000004 /* Supports NPIV */ 299 #define HBA_FLAG_DHCHAP 0x00000008 /* Supports DHCHAP */ 300 #define HBA_FLAG_DYN_WWN 0x00000010 /* Supports Dynamic WWN */ 301 #define HBA_FLAG_E2E_AUTH 0x00000020 /* Supports E2E Auth */ 302 #define HBA_FLAG_TARGET_MODE 0x00000040 /* Supports Target Mode */ 303 #define HBA_FLAG_TARGET_MODE_ENA 0x00000080 /* Target Mode is enabled */ 304 #define HBA_FLAG_SAN_DIAG 0x00000100 /* Supports SAN Diags */ 305 #define HBA_FLAG_FCOE 0x00000200 /* Supports FCoE */ 306 #define HBA_FLAG_PERSISTLINK 0x00000400 /* Supports Persist Link */ 307 /* Up/Down */ 308 309 uint32_t device_id; 310 uint32_t vendor_id; 311 uint32_t ports; 312 uint32_t port_index; 313 314 uint32_t vpi_max; 315 uint32_t vpi_high; 316 317 char wwnn[8]; 318 char snn[256]; 319 320 char wwpn[8]; 321 char spn[256]; 322 323 char fw_version[256]; 324 char fcode_version[256]; 325 char boot_version[256]; 326 327 uint32_t biuRev; 328 uint32_t smRev; 329 uint32_t smFwRev; 330 uint32_t endecRev; 331 uint32_t rBit; 332 uint32_t fcphHigh; 333 uint32_t fcphLow; 334 uint32_t feaLevelHigh; 335 uint32_t feaLevelLow; 336 337 uint32_t kern_rev; 338 char kern_name[32]; 339 uint32_t stub_rev; 340 char stub_name[32]; 341 uint32_t sli1_rev; 342 char sli1_name[32]; 343 uint32_t sli2_rev; 344 char sli2_name[32]; 345 uint32_t sli3_rev; 346 char sli3_name[32]; 347 uint32_t sli4_rev; 348 char sli4_name[32]; 349 uint32_t sli_mode; 350 351 uint32_t drv_instance; 352 char drv_label[64]; 353 char drv_module[64]; 354 char drv_name[32]; 355 char drv_version[64]; 356 char drv_revision[64]; 357 358 char hostname[32]; 359 char os_devname[256]; 360 361 uint32_t port_id; 362 uint32_t port_type; 363 uint32_t port_state; 364 uint32_t topology; 365 uint32_t hard_alpa; 366 uint8_t alpa_count; 367 uint8_t alpa_map[128]; 368 369 uint32_t supported_cos; 370 uint32_t supported_types[8]; 371 uint32_t active_types[8]; 372 373 uint32_t supported_speeds; 374 uint32_t port_speed; 375 uint32_t max_frame_size; 376 377 uint8_t fabric_wwpn[8]; 378 uint8_t fabric_wwnn[8]; 379 uint32_t node_count; 380 381 uint8_t pci_function_number; 382 uint8_t pci_device_number; 383 uint8_t pci_bus_number; 384 } dfc_hbainfo_t; 385 386 387 388 typedef struct fc_class 389 { 390 #ifdef EMLXS_BIG_ENDIAN 391 uint8_t classValid:1; /* FC Word 0, bit 31 */ 392 uint8_t intermix:1; /* FC Word 0, bit 30 */ 393 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 394 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 395 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 396 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 397 #endif 398 #ifdef EMLXS_LITTLE_ENDIAN 399 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 400 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 401 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 402 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 403 uint8_t intermix:1; /* FC Word 0, bit 30 */ 404 uint8_t classValid:1; /* FC Word 0, bit 31 */ 405 #endif 406 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 407 #ifdef EMLXS_BIG_ENDIAN 408 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 409 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 410 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 411 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 412 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 413 #endif 414 #ifdef EMLXS_LITTLE_ENDIAN 415 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 416 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 417 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 418 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 419 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 420 #endif 421 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 422 #ifdef EMLXS_BIG_ENDIAN 423 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 424 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 425 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 426 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 427 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 428 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 429 #endif 430 #ifdef EMLXS_LITTLE_ENDIAN 431 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 432 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 433 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 434 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 435 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 436 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 437 #endif 438 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 439 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 440 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 441 442 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 443 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 444 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 445 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 446 447 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 448 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 449 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 450 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 451 } fc_class_t; 452 453 typedef struct fc_csp 454 { 455 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 456 uint8_t fcphLow; /* FC Word 0, byte 1 */ 457 uint8_t bbCreditMsb; /* FC Word 0, byte 2 */ 458 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 459 460 #ifdef EMLXS_BIG_ENDIAN 461 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 462 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 463 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 464 uint16_t fPort:1; /* FC Word 1, bit 28 */ 465 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 466 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 467 uint16_t multicast:1; /* FC Word 1, bit 25 */ 468 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 469 470 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 471 uint16_t simplex:1; /* FC Word 1, bit 22 */ 472 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 473 uint16_t dhd:1; /* FC Word 1, bit 18 */ 474 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 475 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 476 #endif 477 #ifdef EMLXS_LITTLE_ENDIAN 478 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 479 uint16_t multicast:1; /* FC Word 1, bit 25 */ 480 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 481 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 482 uint16_t fPort:1; /* FC Word 1, bit 28 */ 483 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 484 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 485 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 486 487 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 488 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 489 uint16_t dhd:1; /* FC Word 1, bit 18 */ 490 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 491 uint16_t simplex:1; /* FC Word 1, bit 22 */ 492 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 493 #endif 494 495 uint8_t bbRcvSizeMsb; /* FC Word 1, byte 2 */ 496 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 497 498 union 499 { 500 struct 501 { 502 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 503 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 504 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 505 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 506 } nPort; 507 508 uint32_t r_a_tov; /* RATOV (Big Endian) */ 509 } w2; 510 511 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 512 } fc_csp_t; 513 514 515 typedef struct fc_sparm 516 { 517 fc_csp_t csp; 518 519 uint8_t wwpn[8]; 520 uint8_t wwnn[8]; 521 522 fc_class_t cls1; 523 fc_class_t cls2; 524 fc_class_t cls3; 525 fc_class_t cls4; 526 527 uint8_t vendorVersion[16]; 528 } fc_sparm_t; 529 530 531 typedef struct dfc_node 532 { 533 uint32_t port_id; 534 uint32_t rpi; 535 uint32_t xri; 536 uint32_t flags; 537 538 #define PORT_FLAG_FCP_TARGET 0x00000001 539 #define PORT_FLAG_FCP_INI 0x00000002 540 #define PORT_FLAG_FCP2 0x00000004 541 #define PORT_FLAG_IP 0x00000008 542 #define PORT_FLAG_VPORT 0x00000010 543 544 fc_sparm_t sparm; 545 546 } dfc_node_t; 547 548 549 typedef struct dfc_hbastats 550 { 551 uint32_t tx_frame_cnt; 552 uint32_t rx_frame_cnt; 553 uint32_t tx_kbyte_cnt; 554 uint32_t rx_kbyte_cnt; 555 uint32_t tx_seq_cnt; 556 uint32_t rx_seq_cnt; 557 uint32_t orig_exch_cnt; 558 uint32_t resp_exch_cnt; 559 uint32_t pbsy_cnt; 560 uint32_t fbsy_cnt; 561 uint32_t link_failure_cnt; 562 uint32_t loss_sync_cnt; 563 uint32_t loss_signal_cnt; 564 uint32_t seq_error_cnt; 565 uint32_t inval_tx_word_cnt; 566 uint32_t crc_error_cnt; 567 uint32_t seq_timeout_cnt; 568 uint32_t elastic_overrun_cnt; 569 uint32_t arb_timeout_cnt; 570 uint32_t rx_buf_credit; 571 uint32_t rx_buf_cnt; 572 uint32_t tx_buf_credit; 573 uint32_t tx_buf_cnt; 574 uint32_t EOFa_cnt; 575 uint32_t EOFdti_cnt; 576 uint32_t EOFni_cnt; 577 uint32_t SOFf_cnt; 578 uint32_t link_event_tag; 579 uint32_t last_reset_time; 580 uint32_t topology; 581 uint32_t port_type; 582 uint32_t link_speed; 583 } dfc_hbastats_t; 584 585 586 typedef struct dfc_drvstats 587 { 588 uint32_t LinkUp; 589 uint32_t LinkDown; 590 uint32_t LinkEvent; 591 uint32_t LinkMultiEvent; 592 593 uint32_t MboxIssued; 594 uint32_t MboxCompleted; /* = MboxError + MbxGood */ 595 uint32_t MboxGood; 596 uint32_t MboxError; 597 uint32_t MboxBusy; 598 uint32_t MboxInvalid; 599 600 uint32_t IocbIssued[4]; 601 uint32_t IocbReceived[4]; 602 uint32_t IocbTxPut[4]; 603 uint32_t IocbTxGet[4]; 604 uint32_t IocbRingFull[4]; 605 606 uint32_t IntrEvent[8]; 607 #define RESV_INTR 7 608 #define ERATT_INTR 6 609 #define MBATT_INTR 5 610 #define LKATT_INTR 4 611 #define R3ATT_INTR 3 612 #define R2ATT_INTR 2 613 #define R1ATT_INTR 1 614 #define R0ATT_INTR 0 615 616 uint32_t FcpIssued; 617 uint32_t FcpCompleted; /* FcpGood + FcpError */ 618 uint32_t FcpGood; 619 uint32_t FcpError; 620 621 uint32_t FcpEvent; /* FcpStray + FcpComplete */ 622 uint32_t FcpStray; 623 624 uint32_t ElsEvent; /* ElsStray + ElsComplete (cmd + rsp) */ 625 uint32_t ElsStray; 626 627 uint32_t ElsCmdIssued; 628 uint32_t ElsCmdCompleted; /* ElsCmdGood + ElsCmdError */ 629 uint32_t ElsCmdGood; 630 uint32_t ElsCmdError; 631 632 uint32_t ElsRspIssued; 633 uint32_t ElsRspCompleted; 634 635 uint32_t ElsRcvEvent; /* ElsRcvError + ElsRcvDrop + ElsCmdRcv */ 636 uint32_t ElsRcvError; 637 uint32_t ElsRcvDropped; 638 uint32_t ElsCmdReceived; /* ElsRscnRcv + ElsPlogiRcv + ... */ 639 uint32_t ElsRscnReceived; 640 uint32_t ElsPlogiReceived; 641 uint32_t ElsPrliReceived; 642 uint32_t ElsPrloReceived; 643 uint32_t ElsLogoReceived; 644 uint32_t ElsAdiscReceived; 645 uint32_t ElsGenReceived; 646 647 uint32_t CtEvent; /* CtStray + CtCmdComplete + CtRspComplete */ 648 uint32_t CtStray; 649 650 uint32_t CtCmdIssued; 651 uint32_t CtCmdCompleted; /* CtCmdGood + CtCmdError */ 652 uint32_t CtCmdGood; 653 uint32_t CtCmdError; 654 655 uint32_t CtRspIssued; 656 uint32_t CtRspCompleted; 657 658 uint32_t CtRcvEvent; /* CtRcvError + CtRcvDropp + CtCmdRcv */ 659 uint32_t CtRcvError; 660 uint32_t CtRcvDropped; 661 uint32_t CtCmdReceived; 662 663 uint32_t IpEvent; /* IpStray + IpSeqComplete + IpBcastComplete */ 664 uint32_t IpStray; 665 666 uint32_t IpSeqIssued; 667 uint32_t IpSeqCompleted; /* IpSeqGood + IpSeqError */ 668 uint32_t IpSeqGood; 669 uint32_t IpSeqError; 670 671 uint32_t IpBcastIssued; 672 uint32_t IpBcastCompleted; /* IpBcastGood + IpBcastError */ 673 uint32_t IpBcastGood; 674 uint32_t IpBcastError; 675 676 uint32_t IpRcvEvent; /* IpDrop + IpSeqRcv + IpBcastRcv */ 677 uint32_t IpDropped; 678 uint32_t IpSeqReceived; 679 uint32_t IpBcastReceived; 680 681 uint32_t IpUbPosted; 682 uint32_t ElsUbPosted; 683 uint32_t CtUbPosted; 684 685 #if (DFC_REV >= 2) 686 uint32_t IocbThrottled; 687 uint32_t ElsAuthReceived; 688 #endif 689 } dfc_drvstats_t; 690 691 #ifdef SFCT_SUPPORT 692 /* 693 * FctP2IOXcnt will count IOs by their fcpDL. Counters 694 * are for buckets of various power of 2 sizes. 695 * Bucket 0 < 512 > 0 696 * Bucket 1 >= 512 < 1024 697 * Bucket 2 >= 1024 < 2048 698 * Bucket 3 >= 2048 < 4096 699 * Bucket 4 >= 4096 < 8192 700 * Bucket 5 >= 8192 < 16K 701 * Bucket 6 >= 16K < 32K 702 * Bucket 7 >= 32K < 64K 703 * Bucket 8 >= 64K < 128K 704 * Bucket 9 >= 128K < 256K 705 * Bucket 10 >= 256K < 512K 706 * Bucket 11 >= 512K < 1MB 707 * Bucket 12 >= 1MB < 2MB 708 * Bucket 13 >= 2MB < 4MB 709 * Bucket 14 >= 4MB < 8MB 710 * Bucket 15 >= 8MB 711 */ 712 #define DFC_TGTPORT_STAT_VERSION 1 713 #define MAX_TGTPORT_IOCNT 16 714 typedef struct dfc_tgtport_stat 715 { 716 uint8_t Version; 717 uint8_t Reserved[7]; 718 719 /* IO counters */ 720 uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */ 721 uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */ 722 uint64_t FctIOCmdCnt; /* Other, ie TUR */ 723 uint64_t FctCmdReceived; /* total I/O */ 724 uint64_t FctReadBytes; /* total read bytes */ 725 uint64_t FctWriteBytes; /* total write bytes */ 726 727 /* IOCB handling counters */ 728 uint64_t FctEvent; /* FctStray + FctCmpl */ 729 uint64_t FctCompleted; /* FctCmpl (Good+Err) */ 730 uint64_t FctCmplGood; 731 732 uint32_t FctCmplError; 733 uint32_t FctStray; 734 735 /* Fct event counters */ 736 uint32_t FctRcvDropped; 737 uint32_t FctOverQDepth; 738 uint32_t FctOutstandingIO; 739 uint32_t FctFailedPortRegister; 740 uint32_t FctPortRegister; 741 uint32_t FctPortDeregister; 742 743 uint32_t FctAbortSent; 744 uint32_t FctNoBuffer; 745 uint32_t FctScsiStatusErr; 746 uint32_t FctScsiQfullErr; 747 uint32_t FctScsiResidOver; 748 uint32_t FctScsiResidUnder; 749 uint32_t FctScsiSenseErr; 750 751 /* Additional info */ 752 uint32_t FctLinkState; 753 } dfc_tgtport_stat_t; 754 #endif /* SFCT_SUPPORT */ 755 756 /* DFC_REV >= 3 */ 757 typedef struct dfc_vportinfo 758 { 759 uint32_t flags; 760 #define VPORT_CONFIG 0x00000001 761 #define VPORT_ENABLED 0x00000002 762 #define VPORT_BOUND 0x00000004 763 #define VPORT_IP 0x00000008 764 #define VPORT_RESTRICTED 0x00000010 /* login restricted */ 765 766 uint32_t vpi; 767 uint32_t port_id; 768 uint8_t wwpn[8]; 769 uint8_t wwnn[8]; 770 771 char snn[256]; 772 char spn[256]; 773 774 uint32_t ulp_statec; 775 } dfc_vportinfo_t; 776 777 #ifdef __cplusplus 778 } 779 #endif 780 781 #endif /* _EMLXS_DFC_H */ 782