1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_DFC_H 29 #define _EMLXS_DFC_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/fibre-channel/fcio.h> 36 #include <emlxs_fcio.h> 37 38 39 #ifndef DFC_SUPPORT 40 #define DFC_REV 0 41 #else 42 #define DFC_REV 1 43 44 #ifdef DHCHAP_SUPPORT 45 #undef DFC_REV 46 #define DFC_REV 2 47 #endif /* DHCHAP_SUPPORT */ 48 49 #ifdef NPIV_SUPPORT 50 #undef DFC_REV 51 #define DFC_REV 3 52 #endif /* NPIV_SUPPORT */ 53 54 #endif /* DFC_SUPPORT */ 55 56 57 58 typedef struct dfc { 59 uint32_t cmd; 60 uint32_t flag; 61 62 void *buf1; 63 uint32_t buf1_size; 64 uint32_t data1; 65 66 void *buf2; 67 uint32_t buf2_size; 68 uint32_t data2; 69 70 void *buf3; 71 uint32_t buf3_size; 72 uint32_t data3; 73 74 void *buf4; 75 uint32_t buf4_size; 76 uint32_t data4; 77 78 } dfc_t; 79 80 81 82 /* 83 * 32 bit varient of dfc_t to be used only in the driver and NOT applications 84 */ 85 typedef struct dfc32 { 86 uint32_t cmd; 87 uint32_t flag; 88 89 uint32_t buf1; 90 uint32_t buf1_size; 91 uint32_t data1; 92 93 uint32_t buf2; 94 uint32_t buf2_size; 95 uint32_t data2; 96 97 uint32_t buf3; 98 uint32_t buf3_size; 99 uint32_t data3; 100 101 uint32_t buf4; 102 uint32_t buf4_size; 103 uint32_t data4; 104 105 } dfc32_t; 106 107 108 /* Valid dfc.dfc_cmd codes (DFC_REV=1) */ 109 #define EMLXS_GET_HBAINFO 1 110 #define EMLXS_GET_IOINFO 2 111 #define EMLXS_GET_LINKINFO 3 112 #define EMLXS_GET_NODEINFO 4 113 #define EMLXS_GET_EVENTINFO 5 114 #define EMLXS_GET_REV 6 115 #define EMLXS_GET_DUMPREGION 7 116 #define EMLXS_GET_HBASTATS 8 117 #define EMLXS_GET_DRVSTATS 9 118 119 /* FCIO_SUPPORT */ 120 #define EMLXS_FCIO_CMD 10 121 122 #define EMLXS_GET_CFG 15 123 #define EMLXS_SET_CFG 16 124 #define EMLXS_GET_EVENT 17 125 #define EMLXS_SET_EVENT 18 126 127 #define EMLXS_SEND_MBOX 20 128 #define EMLXS_SEND_ELS 21 129 #define EMLXS_SEND_CT 22 130 #define EMLXS_SEND_CT_RSP 23 131 #define EMLXS_SEND_MENLO 24 132 #define EMLXS_SEND_SCSI 25 133 134 #define EMLXS_SET_DIAG 30 135 #define EMLXS_LOOPBACK_MODE 31 136 #define EMLXS_LOOPBACK_TEST 32 137 138 #define EMLXS_READ_PCI 40 139 #define EMLXS_WRITE_PCI 41 140 #define EMLXS_WRITE_FLASH 42 141 #define EMLXS_READ_FLASH 43 142 #define EMLXS_READ_MEM 44 143 #define EMLXS_WRITE_MEM 45 144 #define EMLXS_WRITE_CTLREG 46 145 #define EMLXS_READ_CTLREG 47 146 147 148 /* NPIV_SUPPORT */ 149 #define EMLXS_CREATE_VPORT 50 150 #define EMLXS_DESTROY_VPORT 51 151 #define EMLXS_GET_VPORTINFO 52 152 #define EMLXS_NPIV_RESOURCE 53 153 #define EMLXS_NPIV_TEST 54 154 155 /* DHCHAP_SUPPORT */ 156 #define EMLXS_INIT_AUTH 60 157 #define EMLXS_GET_AUTH_CFG 61 158 #define EMLXS_SET_AUTH_CFG 62 159 #define EMLXS_GET_AUTH_PASSWORD 63 160 #define EMLXS_SET_AUTH_PASSWORD 64 161 #define EMLXS_GET_AUTH_STATUS 65 162 #define EMLXS_GET_AUTH_CFG_TABLE 66 163 #define EMLXS_GET_AUTH_KEY_TABLE 67 164 165 /* SFCT_SUPPORT */ 166 #define EMLXS_GET_FCTSTAT 70 167 168 /* EMLXS_SET_AUTH_CFG - flags */ 169 #define EMLXS_AUTH_CFG_ADD 0 170 #define EMLXS_AUTH_CFG_DELETE 1 171 172 /* ERROR Codes */ 173 #define DFC_ERRNO_START 0x200 174 175 #define DFC_SUCCESS 0 176 #define DFC_SYS_ERROR (DFC_ERRNO_START + 1) /* General system err */ 177 #define DFC_DRV_ERROR (DFC_ERRNO_START + 2) /* General driver err */ 178 #define DFC_HBA_ERROR (DFC_ERRNO_START + 3) /* General HBA error */ 179 #define DFC_IO_ERROR (DFC_ERRNO_START + 4) /* General IO error */ 180 181 #define DFC_ARG_INVALID (DFC_ERRNO_START + 5) /* Argument value */ 182 /* invalid */ 183 #define DFC_ARG_MISALIGNED (DFC_ERRNO_START + 6) /* Argument value */ 184 /* misaligned */ 185 #define DFC_ARG_NULL (DFC_ERRNO_START + 7) /* Argument value */ 186 /* NULL */ 187 #define DFC_ARG_TOOSMALL (DFC_ERRNO_START + 8) /* Argument value too */ 188 /* small */ 189 #define DFC_ARG_TOOBIG (DFC_ERRNO_START + 9) /* Argument value too */ 190 /* big */ 191 192 #define DFC_COPYIN_ERROR (DFC_ERRNO_START + 10) /* DDI copyin error */ 193 #define DFC_COPYOUT_ERROR (DFC_ERRNO_START + 11) /* DDI copyout error */ 194 195 #define DFC_TIMEOUT (DFC_ERRNO_START + 12) /* Resource timeout */ 196 /* occurred */ 197 #define DFC_SYSRES_ERROR (DFC_ERRNO_START + 13) /* Out of system */ 198 /* resources */ 199 #define DFC_DRVRES_ERROR (DFC_ERRNO_START + 14) /* Out of driver */ 200 /* resources */ 201 #define DFC_HBARES_ERROR (DFC_ERRNO_START + 15) /* Out HBA resources */ 202 203 #define DFC_OFFLINE_ERROR (DFC_ERRNO_START + 16) /* Driver offline */ 204 #define DFC_ONLINE_ERROR (DFC_ERRNO_START + 17) /* Driver offline */ 205 206 /* NPIV_SUPPORT */ 207 #define DFC_NPIV_DISABLED (DFC_ERRNO_START + 18) /* NPIV is disabled */ 208 #define DFC_NPIV_UNSUPPORTED (DFC_ERRNO_START + 19) /* NPIV not supported */ 209 #define DFC_NPIV_ACTIVE (DFC_ERRNO_START + 20) /* NPIV is active */ 210 211 /* DHCHAP_SUPPORT */ 212 #define DFC_AUTH_NOT_CONFIGURED (DFC_ERRNO_START + 30) 213 #define DFC_AUTH_FAILED_NO_SA_FOUND (DFC_ERRNO_START + 31) 214 #define DFC_AUTH_INIT_OK_AUTH_FAILED (DFC_ERRNO_START + 32) 215 #define DFC_AUTH_COMPARE_FAILED (DFC_ERRNO_START + 33) 216 #define DFC_AUTH_WWN_NOT_FOUND (DFC_ERRNO_START + 34) 217 #define DFC_AUTH_PASSWORD_INVALID (DFC_ERRNO_START + 35) 218 #define DFC_AUTH_INVALID_ENTITY (DFC_ERRNO_START + 36) 219 #define DFC_AUTH_ENTITY_NOT_ACTIVE (DFC_ERRNO_START + 37) 220 #define DFC_AUTH_INVALID_OPERATION (DFC_ERRNO_START + 38) 221 #define DFC_AUTH_AUTHENTICATION_GOINGON (DFC_ERRNO_START + 39) 222 #define DFC_AUTH_CREATE_STORKEY_ERROR (DFC_ERRNO_START + 40) 223 #define DFC_AUTH_CREATE_PARMKEY_ERROR (DFC_ERRNO_START + 41) 224 #define DFC_AUTH_CREATE_AUTHKEY_ERROR (DFC_ERRNO_START + 42) 225 #define DFC_AUTH_CREATE_BORDKEY_ERROR (DFC_ERRNO_START + 43) 226 #define DFC_AUTH_AUTHENTICATION_NOT_SUPPORTED (DFC_ERRNO_START + 44) 227 #define DFC_AUTH_AUTHENTICATION_DISABLED (DFC_ERRNO_START + 45) 228 #define DFC_AUTH_CONFIG_NOT_FOUND (DFC_ERRNO_START + 47) 229 230 /* MENLO_SUPPORT */ 231 #define DFC_INVALID_ADAPTER (DFC_ERRNO_START + 50) 232 #define DFC_RSP_BUF_OVERRUN (DFC_ERRNO_START + 51) 233 #define DFC_LINKDOWN_ERROR (DFC_ERRNO_START + 52) 234 235 236 #define DFC_ERRNO_END (DFC_ERRNO_START + 128) 237 238 typedef struct dfc_hbainfo { 239 char vpd_serial_num[32]; 240 char vpd_part_num[32]; 241 char vpd_port_num[20]; 242 char vpd_eng_change[32]; 243 char vpd_manufacturer[80]; 244 char vpd_model[80]; 245 char vpd_model_desc[256]; 246 char vpd_prog_types[256]; 247 char vpd_id[80]; 248 249 uint32_t flags; 250 #define HBA_FLAG_SBUS 0x00000001 251 #define HBA_FLAG_OFFLINE 0x00000002 252 #define HBA_FLAG_NPIV 0x00000004 /* Supports NPIV */ 253 #define HBA_FLAG_DHCHAP 0x00000008 /* Supports DHCHAP */ 254 #define HBA_FLAG_DYN_WWN 0x00000010 /* Supports Dynamic WWN */ 255 #define HBA_FLAG_E2E_AUTH 0x00000010 /* Supports End to End Auth */ 256 257 uint32_t device_id; 258 uint32_t vendor_id; 259 uint32_t ports; 260 uint32_t port_index; 261 262 uint32_t vpi_max; 263 uint32_t vpi_high; 264 265 char wwnn[8]; 266 char snn[256]; 267 268 char wwpn[8]; 269 char spn[256]; 270 271 char fw_version[256]; 272 char fcode_version[256]; 273 char boot_version[256]; 274 275 uint32_t biuRev; 276 uint32_t smRev; 277 uint32_t smFwRev; 278 uint32_t endecRev; 279 uint32_t rBit; 280 uint32_t fcphHigh; 281 uint32_t fcphLow; 282 uint32_t feaLevelHigh; 283 uint32_t feaLevelLow; 284 285 uint32_t kern_rev; 286 char kern_name[32]; 287 uint32_t stub_rev; 288 char stub_name[32]; 289 uint32_t sli1_rev; 290 char sli1_name[32]; 291 uint32_t sli2_rev; 292 char sli2_name[32]; 293 uint32_t sli3_rev; 294 char sli3_name[32]; 295 uint32_t sli4_rev; 296 char sli4_name[32]; 297 uint32_t sli_mode; 298 299 uint32_t drv_instance; 300 char drv_label[64]; 301 char drv_module[64]; 302 char drv_name[32]; 303 char drv_version[64]; 304 char drv_revision[64]; 305 306 char hostname[32]; 307 char os_devname[256]; 308 309 uint32_t port_id; 310 uint32_t port_type; 311 uint32_t port_state; 312 uint32_t topology; 313 uint32_t hard_alpa; 314 uint8_t alpa_count; 315 uint8_t alpa_map[128]; 316 317 uint32_t supported_cos; 318 uint32_t supported_types[8]; 319 uint32_t active_types[8]; 320 321 uint32_t supported_speeds; 322 uint32_t port_speed; 323 uint32_t max_frame_size; 324 325 uint8_t fabric_wwpn[8]; 326 uint8_t fabric_wwnn[8]; 327 uint32_t node_count; 328 329 } dfc_hbainfo_t; 330 331 332 333 typedef struct fc_class { 334 #ifdef EMLXS_BIG_ENDIAN 335 uint8_t classValid:1; /* FC Word 0, bit 31 */ 336 uint8_t intermix:1; /* FC Word 0, bit 30 */ 337 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 338 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 339 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 340 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 341 #endif 342 #ifdef EMLXS_LITTLE_ENDIAN 343 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 344 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 345 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 346 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 347 uint8_t intermix:1; /* FC Word 0, bit 30 */ 348 uint8_t classValid:1; /* FC Word 0, bit 31 */ 349 350 #endif 351 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 352 #ifdef EMLXS_BIG_ENDIAN 353 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 354 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 355 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 356 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 357 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 358 #endif 359 #ifdef EMLXS_LITTLE_ENDIAN 360 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 361 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 362 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 363 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 364 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 365 #endif 366 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 367 #ifdef EMLXS_BIG_ENDIAN 368 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 369 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 370 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 371 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 372 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 373 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 374 #endif 375 #ifdef EMLXS_LITTLE_ENDIAN 376 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 377 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 378 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 379 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 380 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 381 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 382 #endif 383 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 384 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 385 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 386 387 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 388 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 389 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 390 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 391 392 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 393 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 394 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 395 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 396 397 } fc_class_t; 398 399 typedef struct fc_csp { 400 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 401 uint8_t fcphLow; /* FC Word 0, byte 1 */ 402 uint8_t bbCreditMsb; /* FC Word 0, byte 2 */ 403 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 404 405 #ifdef EMLXS_BIG_ENDIAN 406 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 407 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 408 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 409 uint16_t fPort:1; /* FC Word 1, bit 28 */ 410 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 411 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 412 uint16_t multicast:1; /* FC Word 1, bit 25 */ 413 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 414 415 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 416 uint16_t simplex:1; /* FC Word 1, bit 22 */ 417 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 418 uint16_t dhd:1; /* FC Word 1, bit 18 */ 419 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 420 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 421 #endif 422 #ifdef EMLXS_LITTLE_ENDIAN 423 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 424 uint16_t multicast:1; /* FC Word 1, bit 25 */ 425 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 426 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 427 uint16_t fPort:1; /* FC Word 1, bit 28 */ 428 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 429 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 430 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 431 432 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 433 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 434 uint16_t dhd:1; /* FC Word 1, bit 18 */ 435 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 436 uint16_t simplex:1; /* FC Word 1, bit 22 */ 437 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 438 #endif 439 440 uint8_t bbRcvSizeMsb; /* FC Word 1, byte 2 */ 441 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 442 443 union { 444 struct { 445 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 446 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 447 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 448 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 449 } nPort; 450 451 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 452 } w2; 453 454 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 455 456 } fc_csp_t; 457 458 459 typedef struct fc_sparm { 460 fc_csp_t csp; 461 462 uint8_t wwpn[8]; 463 uint8_t wwnn[8]; 464 465 fc_class_t cls1; 466 fc_class_t cls2; 467 fc_class_t cls3; 468 fc_class_t cls4; 469 470 uint8_t vendorVersion[16]; 471 472 } fc_sparm_t; 473 474 475 typedef struct dfc_node { 476 uint32_t port_id; 477 uint32_t rpi; 478 uint32_t xri; 479 uint32_t flags; 480 #define PORT_FLAG_FCP_TARGET 0x00000001 481 #define PORT_FLAG_FCP_INI 0x00000002 482 #define PORT_FLAG_FCP2 0x00000004 483 #define PORT_FLAG_IP 0x00000008 484 485 fc_sparm_t sparm; 486 487 } dfc_node_t; 488 489 490 typedef struct dfc_hbastats { 491 uint32_t tx_frame_cnt; 492 uint32_t rx_frame_cnt; 493 uint32_t tx_kbyte_cnt; 494 uint32_t rx_kbyte_cnt; 495 uint32_t tx_seq_cnt; 496 uint32_t rx_seq_cnt; 497 uint32_t orig_exch_cnt; 498 uint32_t resp_exch_cnt; 499 uint32_t pbsy_cnt; 500 uint32_t fbsy_cnt; 501 uint32_t link_failure_cnt; 502 uint32_t loss_sync_cnt; 503 uint32_t loss_signal_cnt; 504 uint32_t seq_error_cnt; 505 uint32_t inval_tx_word_cnt; 506 uint32_t crc_error_cnt; 507 uint32_t seq_timeout_cnt; 508 uint32_t elastic_overrun_cnt; 509 uint32_t arb_timeout_cnt; 510 uint32_t rx_buf_credit; 511 uint32_t rx_buf_cnt; 512 uint32_t tx_buf_credit; 513 uint32_t tx_buf_cnt; 514 uint32_t EOFa_cnt; 515 uint32_t EOFdti_cnt; 516 uint32_t EOFni_cnt; 517 uint32_t SOFf_cnt; 518 uint32_t link_event_tag; 519 uint32_t last_reset_time; 520 uint32_t topology; 521 uint32_t port_type; 522 uint32_t link_speed; 523 524 } dfc_hbastats_t; 525 526 527 typedef struct dfc_drvstats { 528 uint32_t LinkUp; 529 uint32_t LinkDown; 530 uint32_t LinkEvent; 531 uint32_t LinkMultiEvent; 532 533 uint32_t MboxIssued; 534 uint32_t MboxCompleted; /* MboxCompleted = MboxError + MbxGood */ 535 uint32_t MboxGood; 536 uint32_t MboxError; 537 uint32_t MboxBusy; 538 uint32_t MboxInvalid; 539 540 uint32_t IocbIssued[4]; 541 uint32_t IocbReceived[4]; 542 uint32_t IocbTxPut[4]; 543 uint32_t IocbTxGet[4]; 544 uint32_t IocbRingFull[4]; 545 546 uint32_t IntrEvent[8]; 547 #define RESV_INTR 7 548 #define ERATT_INTR 6 549 #define MBATT_INTR 5 550 #define LKATT_INTR 4 551 #define R3ATT_INTR 3 552 #define R2ATT_INTR 2 553 #define R1ATT_INTR 1 554 #define R0ATT_INTR 0 555 556 uint32_t FcpIssued; 557 uint32_t FcpCompleted; /* = FcpGood + FcpError */ 558 uint32_t FcpGood; 559 uint32_t FcpError; 560 561 uint32_t FcpEvent; /* = FcpStray + FcpCompleted */ 562 uint32_t FcpStray; 563 564 uint32_t ElsEvent; /* = ElsStray + ElsCmdCompleted + */ 565 /* ElsRspCompleted */ 566 uint32_t ElsStray; 567 568 uint32_t ElsCmdIssued; 569 uint32_t ElsCmdCompleted; /* = ElsCmdGood + ElsCmdError */ 570 uint32_t ElsCmdGood; 571 uint32_t ElsCmdError; 572 573 uint32_t ElsRspIssued; 574 uint32_t ElsRspCompleted; 575 576 uint32_t ElsRcvEvent; /* = ElsRcvError + ElsRcvDropped + */ 577 /* ElsCmdReceived */ 578 uint32_t ElsRcvError; 579 uint32_t ElsRcvDropped; 580 uint32_t ElsCmdReceived; /* = ElsRscnReceived + */ 581 /* ElsPlogiReceived + ... */ 582 uint32_t ElsRscnReceived; 583 uint32_t ElsPlogiReceived; 584 uint32_t ElsPrliReceived; 585 uint32_t ElsPrloReceived; 586 uint32_t ElsLogoReceived; 587 uint32_t ElsAdiscReceived; 588 uint32_t ElsGenReceived; 589 590 uint32_t CtEvent; /* = CtStray + CtCmdCompleted + */ 591 /* CtRspCompleted */ 592 uint32_t CtStray; 593 594 uint32_t CtCmdIssued; 595 uint32_t CtCmdCompleted; /* = CtCmdGood + CtCmdError */ 596 uint32_t CtCmdGood; 597 uint32_t CtCmdError; 598 599 uint32_t CtRspIssued; 600 uint32_t CtRspCompleted; 601 602 uint32_t CtRcvEvent; /* = CtRcvError + CtRcvDropped + */ 603 /* CtCmdReceived */ 604 uint32_t CtRcvError; 605 uint32_t CtRcvDropped; 606 uint32_t CtCmdReceived; 607 608 uint32_t IpEvent; /* = IpStray + IpSeqCompleted + */ 609 /* IpBcastCompleted */ 610 uint32_t IpStray; 611 612 uint32_t IpSeqIssued; 613 uint32_t IpSeqCompleted; /* = IpSeqGood + IpSeqError */ 614 uint32_t IpSeqGood; 615 uint32_t IpSeqError; 616 617 uint32_t IpBcastIssued; 618 uint32_t IpBcastCompleted; /* = IpBcastGood + IpBcastError */ 619 uint32_t IpBcastGood; 620 uint32_t IpBcastError; 621 622 uint32_t IpRcvEvent; /* = IpDropped + IpSeqReceived + */ 623 /* IpBcastReceived */ 624 uint32_t IpDropped; 625 uint32_t IpSeqReceived; 626 uint32_t IpBcastReceived; 627 628 uint32_t IpUbPosted; 629 uint32_t ElsUbPosted; 630 uint32_t CtUbPosted; 631 632 #if (DFC_REV >= 2) 633 uint32_t IocbThrottled; 634 uint32_t ElsAuthReceived; 635 #endif 636 637 } dfc_drvstats_t; 638 639 #ifdef SFCT_SUPPORT 640 /* 641 * FctP2IOXcnt will count IOs by their fcpDL. Counters 642 * are for buckets of various power of 2 sizes. 643 * Bucket 0 < 512 > 0 644 * Bucket 1 >= 512 < 1024 645 * Bucket 2 >= 1024 < 2048 646 * Bucket 3 >= 2048 < 4096 647 * Bucket 4 >= 4096 < 8192 648 * Bucket 5 >= 8192 < 16K 649 * Bucket 6 >= 16K < 32K 650 * Bucket 7 >= 32K < 64K 651 * Bucket 8 >= 64K < 128K 652 * Bucket 9 >= 128K < 256K 653 * Bucket 10 >= 256K < 512K 654 * Bucket 11 >= 512K < 1MB 655 * Bucket 12 >= 1MB < 2MB 656 * Bucket 13 >= 2MB < 4MB 657 * Bucket 14 >= 4MB < 8MB 658 * Bucket 15 >= 8MB 659 */ 660 #define MAX_TGTPORT_IOCNT 16 661 typedef struct dfc_tgtport_stat { 662 /* IO counters */ 663 uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */ 664 uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */ 665 uint64_t FctIOCmdCnt; /* Other, ie TUR */ 666 uint64_t FctCmdReceived; /* total IOs */ 667 uint64_t FctReadBytes; /* total bytes Read */ 668 uint64_t FctWriteBytes; /* total bytes Written */ 669 670 /* IOCB handling counters */ 671 uint64_t FctEvent; /* = FctStray + FctCompleted */ 672 uint64_t FctCompleted; /* = FctCmplGood + FctCmplError */ 673 uint64_t FctCmplGood; 674 675 uint32_t FctCmplError; 676 uint32_t FctStray; 677 678 /* Fct event counters */ 679 uint32_t FctRcvDropped; 680 uint32_t FctOverQDepth; 681 uint32_t FctOutstandingIO; 682 uint32_t FctFailedPortRegister; 683 uint32_t FctPortRegister; 684 uint32_t FctPortDeregister; 685 686 uint32_t FctAbortSent; 687 uint32_t FctNoBuffer; 688 uint32_t FctScsiStatusErr; 689 uint32_t FctScsiQfullErr; 690 uint32_t FctScsiResidOver; 691 uint32_t FctScsiResidUnder; 692 uint32_t FctScsiSenseErr; 693 694 /* Additional info */ 695 uint32_t FctLinkState; 696 697 } dfc_tgtport_stat_t; 698 #endif /* SFCT_SUPPORT */ 699 700 /* DFC_REV >= 3 */ 701 typedef struct dfc_vportinfo { 702 uint32_t flags; 703 #define VPORT_CONFIG 0x00000001 704 #define VPORT_ENABLED 0x00000002 705 #define VPORT_BOUND 0x00000004 706 #define VPORT_IP 0x00000008 707 #define VPORT_RESTRICTED 0x00000010 /* login restricted */ 708 709 uint32_t vpi; 710 uint32_t port_id; 711 uint8_t wwpn[8]; 712 uint8_t wwnn[8]; 713 714 char snn[256]; 715 char spn[256]; 716 717 uint32_t ulp_statec; 718 719 } dfc_vportinfo_t; 720 721 #ifdef __cplusplus 722 } 723 #endif 724 725 #endif /* _EMLXS_DFC_H */ 726