17c478bdstevel@tonic-gate/*
27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
57c478bdstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
67c478bdstevel@tonic-gate * (the "License").  You may not use this file except in compliance
77c478bdstevel@tonic-gate * with the License.
87c478bdstevel@tonic-gate *
97c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
107c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
117c478bdstevel@tonic-gate * See the License for the specific language governing permissions
127c478bdstevel@tonic-gate * and limitations under the License.
137c478bdstevel@tonic-gate *
147c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
157c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
167c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
177c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
187c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
197c478bdstevel@tonic-gate *
207c478bdstevel@tonic-gate * CDDL HEADER END
217c478bdstevel@tonic-gate */
227c478bdstevel@tonic-gate/*
237c478bdstevel@tonic-gate * Copyright 1992-2002 Sun Microsystems, Inc.  All rights reserved.
247c478bdstevel@tonic-gate * Use is subject to license terms.
257c478bdstevel@tonic-gate */
267c478bdstevel@tonic-gate
277c478bdstevel@tonic-gate#ifndef	_SYS_ECPPREG_H
287c478bdstevel@tonic-gate#define	_SYS_ECPPREG_H
297c478bdstevel@tonic-gate
307c478bdstevel@tonic-gate#pragma ident	"%Z%%M%	%I%	%E% SMI"
317c478bdstevel@tonic-gate
327c478bdstevel@tonic-gate#ifdef	__cplusplus
337c478bdstevel@tonic-gateextern "C" {
347c478bdstevel@tonic-gate#endif
357c478bdstevel@tonic-gate
367c478bdstevel@tonic-gate/*
377c478bdstevel@tonic-gate * Register definitions for the National Semiconductor PC87332VLJ
387c478bdstevel@tonic-gate * SuperI/O chip.
397c478bdstevel@tonic-gate */
407c478bdstevel@tonic-gate
417c478bdstevel@tonic-gate/*
427c478bdstevel@tonic-gate * configuration registers
437c478bdstevel@tonic-gate */
447c478bdstevel@tonic-gatestruct config_reg {
457c478bdstevel@tonic-gate	uint8_t index;
467c478bdstevel@tonic-gate	uint8_t data;
477c478bdstevel@tonic-gate};
487c478bdstevel@tonic-gate
497c478bdstevel@tonic-gate/* index values for the configuration registers */
507c478bdstevel@tonic-gate#define	FER	0x0	/* Function Enable Register */
517c478bdstevel@tonic-gate#define	FAR	0x1	/* Function Address Register */
527c478bdstevel@tonic-gate#define	PTR	0x2	/* Power and Test Register */
537c478bdstevel@tonic-gate#define	FCR	0x3	/* Function Control Register */
547c478bdstevel@tonic-gate#define	PCR	0x4	/* Printer Control Register */
557c478bdstevel@tonic-gate#define	KRR	0x5	/* Keyboard and RTC control Register */
567c478bdstevel@tonic-gate#define	PMC	0x6	/* Power Management Control register */
577c478bdstevel@tonic-gate#define	TUP	0x7	/* Tape, UART, and Parallel port register */
587c478bdstevel@tonic-gate#define	SID	0x8	/* Super I/O Identification register */
597c478bdstevel@tonic-gate
607c478bdstevel@tonic-gate#define	SIO_LITE	0x40
617c478bdstevel@tonic-gate#define	SIO_LITE_B	0x90
627c478bdstevel@tonic-gate#define	SIO_REVA	0x1a
637c478bdstevel@tonic-gate#define	SIO_REVB	0x1b
647c478bdstevel@tonic-gate
657c478bdstevel@tonic-gate/* bit definitions for the FCR register */
667c478bdstevel@tonic-gate#define	PC87332_FCR_MSD_SEL		0x01
677c478bdstevel@tonic-gate#define	PC87332_FCR_RESERVED		0x02
687c478bdstevel@tonic-gate#define	PC87332_FCR_PPM_EN		0x04
697c478bdstevel@tonic-gate#define	PC87332_FCR_PPM_FLOAT_CTL	0x08
707c478bdstevel@tonic-gate#define	PC87332_FCR_LDX			0x10
717c478bdstevel@tonic-gate#define	PC87332_FCR_ZWS_EN		0x20
727c478bdstevel@tonic-gate#define	PC87332_FCR_ZWS_SEL		0x40
737c478bdstevel@tonic-gate#define	PC87332_FCR_IOCHRDY_SEL		0x80
747c478bdstevel@tonic-gate
757c478bdstevel@tonic-gate/* bit definitions for the PCR register */
767c478bdstevel@tonic-gate#define	PC87332_PCR_EPP_EN		0x01
777c478bdstevel@tonic-gate#define	PC87332_PCR_EPP_VER		0x02
787c478bdstevel@tonic-gate#define	PC87332_PCR_ECP_EN		0x04
797c478bdstevel@tonic-gate#define	PC87332_PCR_ECP_CLK_FZ		0x08
807c478bdstevel@tonic-gate#define	PC87332_PCR_INTR_LEVL		0x10
817c478bdstevel@tonic-gate#define	PC87332_PCR_INTR_POL		0x20
827c478bdstevel@tonic-gate#define	PC87332_PCR_INTR_DRAIN		0x40
837c478bdstevel@tonic-gate#define	PC87332_PCR_RESERVED		0x80
847c478bdstevel@tonic-gate
857c478bdstevel@tonic-gate/* bit definitions for the PMC register */
867c478bdstevel@tonic-gate#define	PC87332_PMC_IDE_TRISTATE	0x01
877c478bdstevel@tonic-gate#define	PC87332_PMC_FDC_TRISTATE	0x02
887c478bdstevel@tonic-gate#define	PC87332_PMC_UART_TRISTATE	0x04
897c478bdstevel@tonic-gate#define	PC87332_PMC_ECP_DMA_CONFIG	0x08
907c478bdstevel@tonic-gate#define	PC87332_PMC_FDC_PD		0x10
917c478bdstevel@tonic-gate#define	PC87332_PMC_SLB			0x20
927c478bdstevel@tonic-gate#define	PC87332_PMC_PP_TRISTATE		0x40
937c478bdstevel@tonic-gate#define	PC87332_PMC_RESERVED		0x80
947c478bdstevel@tonic-gate
957c478bdstevel@tonic-gate/*
967c478bdstevel@tonic-gate * National 97317 superio registers
977c478bdstevel@tonic-gate */
987c478bdstevel@tonic-gate#define	PC97317_CONFIG_DEV_NO		0x07
997c478bdstevel@tonic-gate#define	PC97317_CONFIG_ACTIVATE		0x30
1007c478bdstevel@tonic-gate#define	PC97317_CONFIG_IO_RANGE		0x31
1017c478bdstevel@tonic-gate#define	PC97317_CONFIG_BASE_ADDR_MSB	0x60
1027c478bdstevel@tonic-gate#define	PC97317_CONFIG_BASE_ADDR_LSB	0x61
1037c478bdstevel@tonic-gate#define	PC97317_CONFIG_INTR_SEL		0x70
1047c478bdstevel@tonic-gate#define	PC97317_CONFIG_INTR_TYPE	0x71
1057c478bdstevel@tonic-gate#define	PC97317_CONFIG_DMA0_CHAN	0x74
1067c478bdstevel@tonic-gate#define	PC97317_CONFIG_DMA1_CHAN	0x75
1077c478bdstevel@tonic-gate#define	PC97317_CONFIG_PP_CONFIG	0xF0
1087c478bdstevel@tonic-gate
1097c478bdstevel@tonic-gate/*
1107c478bdstevel@tonic-gate * Plug N Play configuration superio registers
1117c478bdstevel@tonic-gate * used in PC97317 & M1553
1127c478bdstevel@tonic-gate */
1137c478bdstevel@tonic-gate#define	PnP_CONFIG_DEV_NO		0x07
1147c478bdstevel@tonic-gate#define	PnP_CONFIG_ACTIVATE		0x30
1157c478bdstevel@tonic-gate#define	PnP_CONFIG_IO_RANGE		0x31
1167c478bdstevel@tonic-gate#define	PnP_CONFIG_BASE_ADDR_MSB	0x60
1177c478bdstevel@tonic-gate#define	PnP_CONFIG_BASE_ADDR_LSB	0x61
1187c478bdstevel@tonic-gate#define	PnP_CONFIG_INTR_SEL		0x70
1197c478bdstevel@tonic-gate#define	PnP_CONFIG_INTR_TYPE		0x71
1207c478bdstevel@tonic-gate#define	PnP_CONFIG_DMA0_CHAN		0x74
1217c478bdstevel@tonic-gate#define	PnP_CONFIG_DMA1_CHAN		0x75
1227c478bdstevel@tonic-gate#define	PnP_CONFIG_PP_CONFIG0		0xF0
1237c478bdstevel@tonic-gate#define	PnP_CONFIG_PP_CONFIG1		0xF1
1247c478bdstevel@tonic-gate
1257c478bdstevel@tonic-gate
1267c478bdstevel@tonic-gate/*
1277c478bdstevel@tonic-gate * parallel port interface registers - same for all 1284 modes.
1287c478bdstevel@tonic-gate */
1297c478bdstevel@tonic-gatestruct info_reg {
1307c478bdstevel@tonic-gate	union {
1317c478bdstevel@tonic-gate		uint8_t	datar;
1327c478bdstevel@tonic-gate		uint8_t	afifo;
1337c478bdstevel@tonic-gate	} ir;
1347c478bdstevel@tonic-gate	uint8_t dsr;
1357c478bdstevel@tonic-gate	uint8_t dcr;
1367c478bdstevel@tonic-gate	uint8_t epp_addr;
1377c478bdstevel@tonic-gate	uint8_t epp_data;
1387c478bdstevel@tonic-gate	uint8_t epp_data32[3];
1397c478bdstevel@tonic-gate};
1407c478bdstevel@tonic-gate
1417c478bdstevel@tonic-gate/*
1427c478bdstevel@tonic-gate * additional ECP mode registers.
1437c478bdstevel@tonic-gate */
1447c478bdstevel@tonic-gatestruct fifo_reg {
1457c478bdstevel@tonic-gate	union {
1467c478bdstevel@tonic-gate		uint8_t cfifo;
1477c478bdstevel@tonic-gate		uint8_t dfifo;
1487c478bdstevel@tonic-gate		uint8_t tfifo;
1497c478bdstevel@tonic-gate		uint8_t config_a;
1507c478bdstevel@tonic-gate	} fr;
1517c478bdstevel@tonic-gate	uint8_t config_b;
1527c478bdstevel@tonic-gate	uint8_t ecr;
1537c478bdstevel@tonic-gate};
1547c478bdstevel@tonic-gate
1557c478bdstevel@tonic-gate/*
1567c478bdstevel@tonic-gate * Values for the ECR field
1577c478bdstevel@tonic-gate *
1587c478bdstevel@tonic-gate * The ECR has 3 read-only bits - bits 0,1,2.  Bits 3,4,5,6,7 are read/write.
1597c478bdstevel@tonic-gate * While writing to this register (ECPPIOC_SETREGS), bits 0,1,2 must be 0.
1607c478bdstevel@tonic-gate * If not, ECPPIOC_SETREGS will return EINVAL.
1617c478bdstevel@tonic-gate */
1627c478bdstevel@tonic-gate
1637c478bdstevel@tonic-gate#define	ECPP_FIFO_EMPTY		0x01	/* 1 when FIFO empty */
1647c478bdstevel@tonic-gate#define	ECPP_FIFO_FULL		0x02	/* 1 when FIFO full  */
1657c478bdstevel@tonic-gate#define	ECPP_INTR_SRV		0x04
1667c478bdstevel@tonic-gate
1677c478bdstevel@tonic-gate/*
1687c478bdstevel@tonic-gate * When bit is 0, bit will be set to 1
1697c478bdstevel@tonic-gate * and interrupt will be generated if
1707c478bdstevel@tonic-gate * any of the three events occur:
1717c478bdstevel@tonic-gate * (a) TC is reached while DMA enabled
1727c478bdstevel@tonic-gate * (b) If DMA disabled & DCR5 = 0, 8 or more bytes free in FIFO,
1737c478bdstevel@tonic-gate * (c) IF DMA disable & DCR5 = 1, 8 or more bytes to be read in FIFO.
1747c478bdstevel@tonic-gate *
1757c478bdstevel@tonic-gate * When this bit is 1, DMA & (a), (b), (c)
1767c478bdstevel@tonic-gate * interrupts are disabled.
1777c478bdstevel@tonic-gate */
1787c478bdstevel@tonic-gate
1797c478bdstevel@tonic-gate#define	ECPP_DMA_ENABLE		0x08  /* DMA enable =1 */
1807c478bdstevel@tonic-gate#define	ECPP_INTR_MASK		0x10  /* intr-enable nErr mask=1 */
1817c478bdstevel@tonic-gate#define	ECR_mode_000		0x00  /* PIO CENTRONICS */
1827c478bdstevel@tonic-gate#define	ECR_mode_001		0x20  /* PIO NIBBLE */
1837c478bdstevel@tonic-gate#define	ECR_mode_010		0x40  /* DMA CENTRONICS */
1847c478bdstevel@tonic-gate#define	ECR_mode_011		0x60  /* DMA ECP */
1857c478bdstevel@tonic-gate#define	ECR_mode_100		0x80  /* PIO EPP */
1867c478bdstevel@tonic-gate#define	ECR_mode_110		0xc0  /* TDMA (TFIFO) */
1877c478bdstevel@tonic-gate#define	ECR_mode_111		0xe0  /* Config Mode */
1887c478bdstevel@tonic-gate
1897c478bdstevel@tonic-gate/*
1907c478bdstevel@tonic-gate * 97317 second level configuration registers
1917c478bdstevel@tonic-gate */
1927c478bdstevel@tonic-gatestruct config2_reg {
1937c478bdstevel@tonic-gate	uint8_t		eir;	/* Extended Index Register */
1947c478bdstevel@tonic-gate	uint8_t		edr;	/* Extended Data Register */
1957c478bdstevel@tonic-gate};
1967c478bdstevel@tonic-gate
1977c478bdstevel@tonic-gate/*
1987c478bdstevel@tonic-gate * Second level offset
1997c478bdstevel@tonic-gate */
2007c478bdstevel@tonic-gate#define	PC97317_CONFIG2_CONTROL0	0x00
2017c478bdstevel@tonic-gate#define	PC97317_CONFIG2_CONTROL2	0x02
2027c478bdstevel@tonic-gate#define	PC97317_CONFIG2_CONTROL4	0x04
2037c478bdstevel@tonic-gate#define	PC97317_CONFIG2_PPCONFG0	0x05
2047c478bdstevel@tonic-gate
2057c478bdstevel@tonic-gate/* Cheerio Ebus DMAC */
2067c478bdstevel@tonic-gate
2077c478bdstevel@tonic-gatestruct cheerio_dma_reg {
2087c478bdstevel@tonic-gate	uint32_t csr;	/* Data Control Status Register */
2097c478bdstevel@tonic-gate	uint32_t acr;	/* DMA Address Count Registers */
2107c478bdstevel@tonic-gate	uint32_t bcr;	/* DMA Byte Count Register */
2117c478bdstevel@tonic-gate};
2127c478bdstevel@tonic-gate
2137c478bdstevel@tonic-gate/*
2147c478bdstevel@tonic-gate * DMA Control and Status Register(DCSR) definitions.  See Cheerio spec
2157c478bdstevel@tonic-gate * for more details
2167c478bdstevel@tonic-gate */
2177c478bdstevel@tonic-gate#define	DCSR_INT_PEND 	0x00000001	/* 1= pport or dma interrupts */
2187c478bdstevel@tonic-gate#define	DCSR_ERR_PEND 	0x00000002	/* 1= host bus error detected */
2197c478bdstevel@tonic-gate#define	DCSR_INT_EN 	0x00000010	/* 1= enable sidewinder/ebus intr */
2207c478bdstevel@tonic-gate#define	DCSR_RESET  	0x00000080	/* 1= resets the DCSR */
2217c478bdstevel@tonic-gate#define	DCSR_WRITE  	0x00000100  	/* DMA direction; 1 = memory */
2227c478bdstevel@tonic-gate#define	DCSR_EN_DMA  	0x00000200  	/* 1= enable DMA */
2237c478bdstevel@tonic-gate#define	DCSR_CYC_PEND	0x00000400	/* 1 = DMA pending */
2247c478bdstevel@tonic-gate#define	DCSR_EN_CNT 	0x00002000	/* 1= enables byte counter */
2257c478bdstevel@tonic-gate#define	DCSR_TC		0x00004000  	/* 1= Terminal Count occurred */
2267c478bdstevel@tonic-gate#define	DCSR_CSR_DRAIN 	0x00000000 	/* 1= disable draining */
2277c478bdstevel@tonic-gate#define	DCSR_BURST_0    0x00040000 	/* Burst Size bit 0 */
2287c478bdstevel@tonic-gate#define	DCSR_BURST_1    0x00080000 	/* Burst Size bit 1 */
2297c478bdstevel@tonic-gate#define	DCSR_DIAG	0x00000000 	/* 1= diag enable */
2307c478bdstevel@tonic-gate#define	DCSR_TCI_DIS 	0x00800000	/* 1= TC won't cause interrupt */
2317c478bdstevel@tonic-gate
2327c478bdstevel@tonic-gate
2337c478bdstevel@tonic-gate/* Southbridge support */
2347c478bdstevel@tonic-gatestruct isaspace {
2357c478bdstevel@tonic-gate	uchar_t	isa_reg[0x500];	/* 0x500 regs from isa config space */
2367c478bdstevel@tonic-gate};
2377c478bdstevel@tonic-gate
2387c478bdstevel@tonic-gate
2397c478bdstevel@tonic-gate#ifdef	__cplusplus
2407c478bdstevel@tonic-gate}
2417c478bdstevel@tonic-gate#endif
2427c478bdstevel@tonic-gate
2437c478bdstevel@tonic-gate#endif	/* _SYS_ECPPREG_H */
244