17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5102cb92eSjohnny  * Common Development and Distribution License (the "License").
6102cb92eSjohnny  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22a120541cSScott M. Carter  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
237c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate #ifndef	_SYS_DDI_INTR_IMPL_H
267c478bd9Sstevel@tonic-gate #define	_SYS_DDI_INTR_IMPL_H
287c478bd9Sstevel@tonic-gate /*
297c478bd9Sstevel@tonic-gate  * Sun DDI interrupt implementation specific definitions
307c478bd9Sstevel@tonic-gate  */
325febcb4aSScott Carter, SD IOSW #include <sys/list.h>
335febcb4aSScott Carter, SD IOSW #include <sys/ksynch.h>
345febcb4aSScott Carter, SD IOSW 
357c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
367c478bd9Sstevel@tonic-gate extern "C" {
377c478bd9Sstevel@tonic-gate #endif
397c478bd9Sstevel@tonic-gate #ifdef _KERNEL
417c478bd9Sstevel@tonic-gate /*
427c478bd9Sstevel@tonic-gate  * Typedef for interrupt ops
437c478bd9Sstevel@tonic-gate  */
447c478bd9Sstevel@tonic-gate typedef enum {
457c478bd9Sstevel@tonic-gate 	DDI_INTROP_SUPPORTED_TYPES = 1,	/* 1 get supported interrupts types */
467c478bd9Sstevel@tonic-gate 	DDI_INTROP_NINTRS,		/* 2 get num of interrupts supported */
477c478bd9Sstevel@tonic-gate 	DDI_INTROP_ALLOC,		/* 3 allocate interrupt handle */
487c478bd9Sstevel@tonic-gate 	DDI_INTROP_GETPRI,		/* 4 get priority */
497c478bd9Sstevel@tonic-gate 	DDI_INTROP_SETPRI,		/* 5 set priority */
507c478bd9Sstevel@tonic-gate 	DDI_INTROP_ADDISR,		/* 6 add interrupt handler */
517c478bd9Sstevel@tonic-gate 	DDI_INTROP_DUPVEC,		/* 7 duplicate interrupt handler */
527c478bd9Sstevel@tonic-gate 	DDI_INTROP_ENABLE,		/* 8 enable interrupt */
537c478bd9Sstevel@tonic-gate 	DDI_INTROP_BLOCKENABLE,		/* 9 block enable interrupts */
547c478bd9Sstevel@tonic-gate 	DDI_INTROP_BLOCKDISABLE,	/* 10 block disable interrupts */
557c478bd9Sstevel@tonic-gate 	DDI_INTROP_DISABLE,		/* 11 disable interrupt */
567c478bd9Sstevel@tonic-gate 	DDI_INTROP_REMISR,		/* 12 remove interrupt handler */
577c478bd9Sstevel@tonic-gate 	DDI_INTROP_FREE,		/* 13 free interrupt handle */
587c478bd9Sstevel@tonic-gate 	DDI_INTROP_GETCAP,		/* 14 get capacity */
597c478bd9Sstevel@tonic-gate 	DDI_INTROP_SETCAP,		/* 15 set capacity */
607c478bd9Sstevel@tonic-gate 	DDI_INTROP_SETMASK,		/* 16 set mask */
617c478bd9Sstevel@tonic-gate 	DDI_INTROP_CLRMASK,		/* 17 clear mask */
627c478bd9Sstevel@tonic-gate 	DDI_INTROP_GETPENDING,		/* 18 get pending interrupt */
635febcb4aSScott Carter, SD IOSW 	DDI_INTROP_NAVAIL,		/* 19 get num of available interrupts */
6409b1eac2SEvan Yan 	DDI_INTROP_GETPOOL,		/* 20 get resource management pool */
6509b1eac2SEvan Yan 	DDI_INTROP_GETTARGET,		/* 21 get target for a given intr(s) */
6609b1eac2SEvan Yan 	DDI_INTROP_SETTARGET		/* 22 set target for a given intr(s) */
677c478bd9Sstevel@tonic-gate } ddi_intr_op_t;
697c478bd9Sstevel@tonic-gate /* Version number used in the handles */
707c478bd9Sstevel@tonic-gate #define	DDI_INTR_VERSION_1	1
717c478bd9Sstevel@tonic-gate #define	DDI_INTR_VERSION	DDI_INTR_VERSION_1
737c478bd9Sstevel@tonic-gate /*
747c478bd9Sstevel@tonic-gate  * One such data structure is allocated per ddi_intr_handle_t
757c478bd9Sstevel@tonic-gate  * This is the incore copy of the regular interrupt info.
767c478bd9Sstevel@tonic-gate  */
777c478bd9Sstevel@tonic-gate typedef struct ddi_intr_handle_impl {
787c478bd9Sstevel@tonic-gate 	dev_info_t		*ih_dip;	/* dip associated with handle */
797c478bd9Sstevel@tonic-gate 	uint16_t		ih_type;	/* interrupt type being used */
807c478bd9Sstevel@tonic-gate 	ushort_t		ih_inum;	/* interrupt number */
81a195726fSgovinda 	uint32_t		ih_vector;	/* vector number */
827c478bd9Sstevel@tonic-gate 	uint16_t		ih_ver;		/* Version */
837c478bd9Sstevel@tonic-gate 	uint_t			ih_state;	/* interrupt handle state */
847c478bd9Sstevel@tonic-gate 	uint_t			ih_cap;		/* interrupt capabilities */
857c478bd9Sstevel@tonic-gate 	uint_t			ih_pri;		/* priority - bus dependent */
867c478bd9Sstevel@tonic-gate 	krwlock_t		ih_rwlock;	/* read/write lock per handle */
887c478bd9Sstevel@tonic-gate 	uint_t			(*ih_cb_func)(caddr_t, caddr_t);
897c478bd9Sstevel@tonic-gate 	void			*ih_cb_arg1;
907c478bd9Sstevel@tonic-gate 	void			*ih_cb_arg2;
9220036fe5Segillett 	/*
9320036fe5Segillett 	 * The following 3 members are used to support MSI-X specific features
9420036fe5Segillett 	 */
9520036fe5Segillett 	uint_t			ih_flags;	/* Misc flags */
9620036fe5Segillett 	uint_t			ih_dup_cnt;	/* # of dupped msi-x vectors */
9720036fe5Segillett 	struct ddi_intr_handle_impl	*ih_main;
9820036fe5Segillett 						/* pntr to the main vector */
997c478bd9Sstevel@tonic-gate 	/*
1007c478bd9Sstevel@tonic-gate 	 * The next set of members are for 'scratch' purpose only.
1017c478bd9Sstevel@tonic-gate 	 * The DDI interrupt framework uses them internally and their
1027c478bd9Sstevel@tonic-gate 	 * interpretation is left to the framework. For now,
1037c478bd9Sstevel@tonic-gate 	 *	scratch1	- used to send NINTRs information
1047c478bd9Sstevel@tonic-gate 	 *			  to various nexus drivers.
1057c478bd9Sstevel@tonic-gate 	 *	scratch2	- used to send 'behavior' flag
1067c478bd9Sstevel@tonic-gate 	 *			  information to the nexus drivers
107102cb92eSjohnny 	 *			  from ddi_intr_alloc().  It is also
108102cb92eSjohnny 	 *			  used to send 'h_array' to the nexus drivers
109102cb92eSjohnny 	 *			  for ddi_intr_block_enable/disable() on x86.
1107a364d25Sschwartz 	 *	private		- On X86 it usually carries a pointer to
1117a364d25Sschwartz 	 *			  ihdl_plat_t.  Not used on SPARC platforms.
1127c478bd9Sstevel@tonic-gate 	 */
1137c478bd9Sstevel@tonic-gate 	void			*ih_private;	/* Platform specific data */
1147c478bd9Sstevel@tonic-gate 	uint_t			ih_scratch1;	/* Scratch1: #interrupts */
115102cb92eSjohnny 	void			*ih_scratch2;	/* Scratch2: flag/h_array */
11609b1eac2SEvan Yan 
11709b1eac2SEvan Yan 	/*
11809b1eac2SEvan Yan 	 * The ih_target field may not reflect the actual target that is
11909b1eac2SEvan Yan 	 * currently being used for the given interrupt. This field is just a
12009b1eac2SEvan Yan 	 * snapshot taken either during ddi_intr_add_handler() or
121657f87deSgongtian zhao - Sun Microsystems - Beijing China 	 * get/set_intr_affinity() calls.
12209b1eac2SEvan Yan 	 */
123657f87deSgongtian zhao - Sun Microsystems - Beijing China 	processorid_t 		ih_target;	/* Target ID */
1247c478bd9Sstevel@tonic-gate } ddi_intr_handle_impl_t;
1267c478bd9Sstevel@tonic-gate /* values for ih_state (strictly for interrupt handle) */
1277c478bd9Sstevel@tonic-gate #define	DDI_IHDL_STATE_ALLOC	0x01	/* Allocated. ddi_intr_alloc() called */
1287c478bd9Sstevel@tonic-gate #define	DDI_IHDL_STATE_ADDED	0x02	/* Added interrupt handler */
1297c478bd9Sstevel@tonic-gate 					/* ddi_intr_add_handler() called */
1307c478bd9Sstevel@tonic-gate #define	DDI_IHDL_STATE_ENABLE	0x04	/* Enabled. ddi_intr_enable() called */
1327c478bd9Sstevel@tonic-gate #define	DDI_INTR_IS_MSI_OR_MSIX(type) \
1337c478bd9Sstevel@tonic-gate 	((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX)
1352326332eSanish #define	DDI_INTR_BEHAVIOR_FLAG_VALID(f) \
1362326332eSanish 	    (((f) == DDI_INTR_ALLOC_NORMAL) || ((f) == DDI_INTR_ALLOC_STRICT))
138d626b9f5Sanish #define	DDI_INTR_TYPE_FLAG_VALID(t) \
139d626b9f5Sanish 	    (((t) == DDI_INTR_TYPE_FIXED) || \
140d626b9f5Sanish 	    ((t) == DDI_INTR_TYPE_MSI) || \
141d626b9f5Sanish 	    ((t) == DDI_INTR_TYPE_MSIX))
14320036fe5Segillett /* values for ih_flags */
14420036fe5Segillett #define	DDI_INTR_MSIX_DUP	0x01	/* MSI-X vector which has been dupped */
146ef643aefSegillett /* Maximum number of MSI resources to allocate */
147ef643aefSegillett #define	DDI_MAX_MSI_ALLOC	2
149ef643aefSegillett /* Default number of MSI-X resources to allocate */
150ef643aefSegillett #define	DDI_DEFAULT_MSIX_ALLOC	2
15263ea9ad2SEvan Yan #define	DDI_MSIX_ALLOC_DIVIDER	32
15363ea9ad2SEvan Yan #define	DDI_MIN_MSIX_ALLOC	8
15463ea9ad2SEvan Yan #define	DDI_MAX_MSIX_ALLOC	2048
156e23a7e34Slq struct av_softinfo;
1587c478bd9Sstevel@tonic-gate /*
1597c478bd9Sstevel@tonic-gate  * One such data structure is allocated per ddi_soft_intr_handle
1607c478bd9Sstevel@tonic-gate  * This is the incore copy of the softint info.
1617c478bd9Sstevel@tonic-gate  */
1627c478bd9Sstevel@tonic-gate typedef struct ddi_softint_hdl_impl {
1637c478bd9Sstevel@tonic-gate 	dev_info_t	*ih_dip;		/* dip associated with handle */
1647c478bd9Sstevel@tonic-gate 	uint_t		ih_pri;			/* priority - bus dependent */
1657c478bd9Sstevel@tonic-gate 	krwlock_t	ih_rwlock;		/* read/write lock per handle */
166e23a7e34Slq 	struct av_softinfo *ih_pending;		/* whether softint is pending */
1687c478bd9Sstevel@tonic-gate 	uint_t		(*ih_cb_func)(caddr_t, caddr_t);
1697c478bd9Sstevel@tonic-gate 						/* cb function for soft ints */
1707c478bd9Sstevel@tonic-gate 	void		*ih_cb_arg1;		/* arg1 of callback function */
1717c478bd9Sstevel@tonic-gate 	void		*ih_cb_arg2;		/* arg2 passed to "trigger" */
1737c478bd9Sstevel@tonic-gate 	/*
1747c478bd9Sstevel@tonic-gate 	 * The next member is for 'scratch' purpose only.
1757c478bd9Sstevel@tonic-gate 	 * The DDI interrupt framework uses it internally and its
1767c478bd9Sstevel@tonic-gate 	 * interpretation is left to the framework.
1777c478bd9Sstevel@tonic-gate 	 *	private		- used by the DDI framework to pass back
1787c478bd9Sstevel@tonic-gate 	 *			  and forth 'softid' information on SPARC
1797c478bd9Sstevel@tonic-gate 	 *			  side only. Not used on X86 platform.
1807c478bd9Sstevel@tonic-gate 	 */
1817c478bd9Sstevel@tonic-gate 	void		*ih_private;		/* Platform specific data */
1827c478bd9Sstevel@tonic-gate } ddi_softint_hdl_impl_t;
1847c478bd9Sstevel@tonic-gate /* Softint internal implementation defines */
1857c478bd9Sstevel@tonic-gate #define	DDI_SOFT_INTR_PRI_M	4
1867c478bd9Sstevel@tonic-gate #define	DDI_SOFT_INTR_PRI_H	6
1887c478bd9Sstevel@tonic-gate /*
1897c478bd9Sstevel@tonic-gate  * One such data structure is allocated for MSI-X enabled
1907c478bd9Sstevel@tonic-gate  * device. If no MSI-X is enabled then it is NULL
1917c478bd9Sstevel@tonic-gate  */
1927c478bd9Sstevel@tonic-gate typedef struct ddi_intr_msix {
1937c478bd9Sstevel@tonic-gate 	/* MSI-X Table related information */
1947c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	msix_tbl_hdl;		/* MSI-X table handle */
1959c75c6bfSgovinda 	uint32_t		*msix_tbl_addr;		/* MSI-X table addr */
1969c75c6bfSgovinda 	uint32_t		msix_tbl_offset;	/* MSI-X table offset */
1987c478bd9Sstevel@tonic-gate 	/* MSI-X PBA Table related information */
1997c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	msix_pba_hdl;		/* MSI-X PBA handle */
2009c75c6bfSgovinda 	uint32_t		*msix_pba_addr;		/* MSI-X PBA addr */
2019c75c6bfSgovinda 	uint32_t		msix_pba_offset;	/* MSI-X PBA offset */
2037c478bd9Sstevel@tonic-gate 	ddi_device_acc_attr_t	msix_dev_attr;		/* MSI-X device attr */
2047c478bd9Sstevel@tonic-gate } ddi_intr_msix_t;
2065febcb4aSScott Carter, SD IOSW /*
2075febcb4aSScott Carter, SD IOSW  * Interrupt Resource Management (IRM).
2085febcb4aSScott Carter, SD IOSW  */
2095febcb4aSScott Carter, SD IOSW 
2105febcb4aSScott Carter, SD IOSW #define	DDI_IRM_POLICY_LARGE	1
2115febcb4aSScott Carter, SD IOSW #define	DDI_IRM_POLICY_EVEN	2
2125febcb4aSScott Carter, SD IOSW 
2135febcb4aSScott Carter, SD IOSW #define	DDI_IRM_POLICY_VALID(p)	(((p) == DDI_IRM_POLICY_LARGE) || \
2145febcb4aSScott Carter, SD IOSW 				((p) == DDI_IRM_POLICY_EVEN))
2155febcb4aSScott Carter, SD IOSW 
2165febcb4aSScott Carter, SD IOSW #define	DDI_IRM_FLAG_ACTIVE	0x1		/* Pool is active */
2175febcb4aSScott Carter, SD IOSW #define	DDI_IRM_FLAG_QUEUED	0x2		/* Pool is queued */
2185febcb4aSScott Carter, SD IOSW #define	DDI_IRM_FLAG_WAITERS	0x4		/* Pool has waiters */
2195febcb4aSScott Carter, SD IOSW #define	DDI_IRM_FLAG_EXIT	0x8		/* Balance thread must exit */
2205febcb4aSScott Carter, SD IOSW #define	DDI_IRM_FLAG_NEW	0x10		/* Request is new */
2215febcb4aSScott Carter, SD IOSW #define	DDI_IRM_FLAG_CALLBACK	0x20		/* Request has callback */
2225febcb4aSScott Carter, SD IOSW 
2235febcb4aSScott Carter, SD IOSW /*
2245febcb4aSScott Carter, SD IOSW  * One such data structure for each supply of interrupt vectors.
2255febcb4aSScott Carter, SD IOSW  * Contains information about the size and policies defining the
2265febcb4aSScott Carter, SD IOSW  * supply, and a list of associated device-specific requests.
2275febcb4aSScott Carter, SD IOSW  */
2285febcb4aSScott Carter, SD IOSW typedef struct ddi_irm_pool {
2295febcb4aSScott Carter, SD IOSW 	int		ipool_flags;		/* Status flags of the pool */
2305febcb4aSScott Carter, SD IOSW 	int		ipool_types;		/* Types of interrupts */
2315febcb4aSScott Carter, SD IOSW 	int		ipool_policy;		/* Rebalancing policy */
2325febcb4aSScott Carter, SD IOSW 	uint_t		ipool_totsz;		/* Total size of the pool */
2335febcb4aSScott Carter, SD IOSW 	uint_t		ipool_defsz;		/* Default allocation size */
2345febcb4aSScott Carter, SD IOSW 	uint_t		ipool_minno;		/* Minimum number consumed */
2355febcb4aSScott Carter, SD IOSW 	uint_t		ipool_reqno;		/* Total number requested */
2365febcb4aSScott Carter, SD IOSW 	uint_t		ipool_resno;		/* Total number reserved */
2375febcb4aSScott Carter, SD IOSW 	kmutex_t	ipool_lock;		/* Protects all pool usage */
2385febcb4aSScott Carter, SD IOSW 	kmutex_t	ipool_navail_lock;	/* Protects 'navail' of reqs */
2395febcb4aSScott Carter, SD IOSW 	kcondvar_t	ipool_cv;		/* Condition variable */
2405febcb4aSScott Carter, SD IOSW 	kthread_t	*ipool_thread;		/* Balancing thread */
2415febcb4aSScott Carter, SD IOSW 	dev_info_t	*ipool_owner;		/* Device that created pool */
2425febcb4aSScott Carter, SD IOSW 	list_t		ipool_req_list;		/* All requests in pool */
2435febcb4aSScott Carter, SD IOSW 	list_t		ipool_scratch_list;	/* Requests being reduced */
2445febcb4aSScott Carter, SD IOSW 	list_node_t	ipool_link;		/* Links in global pool list */
2455febcb4aSScott Carter, SD IOSW } ddi_irm_pool_t;
2465febcb4aSScott Carter, SD IOSW 
2475febcb4aSScott Carter, SD IOSW /*
2485febcb4aSScott Carter, SD IOSW  * One such data structure for each dip's devinfo_intr_t.
2495febcb4aSScott Carter, SD IOSW  * Contains information about vectors requested from IRM.
2505febcb4aSScott Carter, SD IOSW  */
2515febcb4aSScott Carter, SD IOSW typedef struct ddi_irm_req {
2525febcb4aSScott Carter, SD IOSW 	int		ireq_flags;		/* Flags for request */
2535febcb4aSScott Carter, SD IOSW 	int		ireq_type;		/* Type requested */
2545febcb4aSScott Carter, SD IOSW 	uint_t		ireq_nreq;		/* Number requested */
2555febcb4aSScott Carter, SD IOSW 	uint_t		ireq_navail;		/* Number available */
2565febcb4aSScott Carter, SD IOSW 	uint_t		ireq_scratch;		/* Scratch value */
2575febcb4aSScott Carter, SD IOSW 	dev_info_t	*ireq_dip;		/* Requesting device */
2585febcb4aSScott Carter, SD IOSW 	ddi_irm_pool_t	*ireq_pool_p;		/* Supplying pool */
2595febcb4aSScott Carter, SD IOSW 	list_node_t	ireq_link;		/* Request list link */
2605febcb4aSScott Carter, SD IOSW 	list_node_t	ireq_scratch_link;	/* Scratch list link */
2615febcb4aSScott Carter, SD IOSW } ddi_irm_req_t;
2625febcb4aSScott Carter, SD IOSW 
2635febcb4aSScott Carter, SD IOSW /*
2645febcb4aSScott Carter, SD IOSW  * This structure is used to pass parameters to ndi_create_irm(),
2655febcb4aSScott Carter, SD IOSW  * and describes the operating parameters of an IRM pool.
2665febcb4aSScott Carter, SD IOSW  */
2675febcb4aSScott Carter, SD IOSW typedef struct ddi_irm_params {
2685febcb4aSScott Carter, SD IOSW 	int	iparams_types;		/* Types of interrupts in pool */
2695febcb4aSScott Carter, SD IOSW 	uint_t	iparams_total;		/* Total size of the pool */
2705febcb4aSScott Carter, SD IOSW } ddi_irm_params_t;
2727c478bd9Sstevel@tonic-gate /*
2737c478bd9Sstevel@tonic-gate  * One such data structure is allocated for each dip.
2747c478bd9Sstevel@tonic-gate  * It has interrupt related information that can be
2757c478bd9Sstevel@tonic-gate  * stored/retrieved for convenience.
2767c478bd9Sstevel@tonic-gate  */
2777c478bd9Sstevel@tonic-gate typedef struct devinfo_intr {
2787c478bd9Sstevel@tonic-gate 	/* These three fields show what the device is capable of */
2797c478bd9Sstevel@tonic-gate 	uint_t		devi_intr_sup_types;	/* Intrs supported by device */
2817c478bd9Sstevel@tonic-gate 	ddi_intr_msix_t	*devi_msix_p;		/* MSI-X info, if supported */
2837c478bd9Sstevel@tonic-gate 	/* Next three fields show current status for the device */
2847c478bd9Sstevel@tonic-gate 	uint_t		devi_intr_curr_type;	/* Interrupt type being used */
2857c478bd9Sstevel@tonic-gate 	uint_t		devi_intr_sup_nintrs;	/* #intr supported */
2867c478bd9Sstevel@tonic-gate 	uint_t		devi_intr_curr_nintrs;	/* #intr currently being used */
2872145b8d4SGuoli Shu 	/*
2882145b8d4SGuoli Shu 	 * #intr currently being enabled
2892145b8d4SGuoli Shu 	 * (for MSI block enable, the valuse is either 1 or 0.)
2902145b8d4SGuoli Shu 	 */
2912145b8d4SGuoli Shu 	uint_t		devi_intr_curr_nenables;
2935febcb4aSScott Carter, SD IOSW 	ddi_intr_handle_t *devi_intr_handle_p;	/* Hdl for legacy intr APIs */
295d12abe7cSanish #if defined(__i386) || defined(__amd64)
296d12abe7cSanish 	/* Save the PCI config space handle */
297d12abe7cSanish 	ddi_acc_handle_t devi_cfg_handle;
298d12abe7cSanish 	int		 devi_cap_ptr;		/* MSI or MSI-X cap pointer */
299d12abe7cSanish #endif
3005febcb4aSScott Carter, SD IOSW 
3015febcb4aSScott Carter, SD IOSW 	ddi_irm_req_t	*devi_irm_req_p;	/* IRM request information */
3027c478bd9Sstevel@tonic-gate } devinfo_intr_t;
3047c478bd9Sstevel@tonic-gate #define	NEXUS_HAS_INTR_OP(dip)	\
3057c478bd9Sstevel@tonic-gate 	((DEVI(dip)->devi_ops->devo_bus_ops) && \
3067c478bd9Sstevel@tonic-gate 	(DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \
3077c478bd9Sstevel@tonic-gate 	(DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op))
3097c478bd9Sstevel@tonic-gate int	i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op,
3107c478bd9Sstevel@tonic-gate 	    ddi_intr_handle_impl_t *hdlp, void *result);
3127c478bd9Sstevel@tonic-gate int	i_ddi_add_softint(ddi_softint_hdl_impl_t *);
3137c478bd9Sstevel@tonic-gate void	i_ddi_remove_softint(ddi_softint_hdl_impl_t *);
314b08160e2Sgovinda int	i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *);
3157c478bd9Sstevel@tonic-gate int	i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t);
3177c478bd9Sstevel@tonic-gate void	i_ddi_intr_devi_init(dev_info_t *dip);
3187c478bd9Sstevel@tonic-gate void	i_ddi_intr_devi_fini(dev_info_t *dip);
3207c478bd9Sstevel@tonic-gate uint_t	i_ddi_intr_get_supported_types(dev_info_t *dip);
3217c478bd9Sstevel@tonic-gate void	i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type);
3227c478bd9Sstevel@tonic-gate uint_t	i_ddi_intr_get_current_type(dev_info_t *dip);
3237c478bd9Sstevel@tonic-gate void	i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type);
3247c478bd9Sstevel@tonic-gate uint_t	i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type);
3257c478bd9Sstevel@tonic-gate void	i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs);
3267c478bd9Sstevel@tonic-gate uint_t	i_ddi_intr_get_current_nintrs(dev_info_t *dip);
3277c478bd9Sstevel@tonic-gate void	i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs);
3282145b8d4SGuoli Shu uint_t	i_ddi_intr_get_current_nenables(dev_info_t *dip);
3292145b8d4SGuoli Shu void	i_ddi_intr_set_current_nenables(dev_info_t *dip, int nintrs);
3305febcb4aSScott Carter, SD IOSW uint_t	i_ddi_intr_get_current_navail(dev_info_t *dip, int intr_type);
331a120541cSScott M. Carter uint_t	i_ddi_intr_get_limit(dev_info_t *dip, int intr_type,
332a120541cSScott M. Carter 	    ddi_irm_pool_t *pool_p);
3335febcb4aSScott Carter, SD IOSW 
3345febcb4aSScott Carter, SD IOSW ddi_irm_pool_t	*i_ddi_intr_get_pool(dev_info_t *dip, int intr_type);
3355febcb4aSScott Carter, SD IOSW 
3365febcb4aSScott Carter, SD IOSW void	irm_init(void);
3375febcb4aSScott Carter, SD IOSW int	i_ddi_irm_insert(dev_info_t *dip, int intr_type, int count);
3385febcb4aSScott Carter, SD IOSW int	i_ddi_irm_modify(dev_info_t *dip, int nreq);
3395febcb4aSScott Carter, SD IOSW int	i_ddi_irm_remove(dev_info_t *dip);
3405febcb4aSScott Carter, SD IOSW void	i_ddi_irm_set_cb(dev_info_t *dip, boolean_t cb_flag);
341a120541cSScott M. Carter int	i_ddi_irm_supported(dev_info_t *dip, int type);
3435febcb4aSScott Carter, SD IOSW ddi_intr_handle_t i_ddi_get_intr_handle(dev_info_t *dip, int inum);
3445febcb4aSScott Carter, SD IOSW void	i_ddi_set_intr_handle(dev_info_t *dip, int inum, ddi_intr_handle_t hdl);
3467c478bd9Sstevel@tonic-gate ddi_intr_msix_t	*i_ddi_get_msix(dev_info_t *dip);
3477c478bd9Sstevel@tonic-gate void	i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p);
349d12abe7cSanish #if defined(__i386) || defined(__amd64)
350d12abe7cSanish ddi_acc_handle_t	i_ddi_get_pci_config_handle(dev_info_t *dip);
351d12abe7cSanish void	i_ddi_set_pci_config_handle(dev_info_t *dip, ddi_acc_handle_t handle);
352d12abe7cSanish int	i_ddi_get_msi_msix_cap_ptr(dev_info_t *dip);
353d12abe7cSanish void	i_ddi_set_msi_msix_cap_ptr(dev_info_t *dip, int cap_ptr);
354d12abe7cSanish #endif
3567c478bd9Sstevel@tonic-gate int32_t i_ddi_get_intr_weight(dev_info_t *);
3577c478bd9Sstevel@tonic-gate int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t);
3597a364d25Sschwartz void	i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *);
3607a364d25Sschwartz void	i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *);
362*7ff178cdSJimmy Vetayases extern	int irm_enable; /* global flag for IRM */
363*7ff178cdSJimmy Vetayases 
3647c478bd9Sstevel@tonic-gate #define	DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \
3657c478bd9Sstevel@tonic-gate 	hdlp->ih_cb_func = func; \
3667c478bd9Sstevel@tonic-gate 	hdlp->ih_cb_arg1 = arg1; \
3677c478bd9Sstevel@tonic-gate 	hdlp->ih_cb_arg2 = arg2;
36920036fe5Segillett #ifdef DEBUG
37020036fe5Segillett #define	I_DDI_VERIFY_MSIX_HANDLE(hdlp)					\
37120036fe5Segillett 	if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && 			\
37220036fe5Segillett 	    (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) {			\
37320036fe5Segillett 		ASSERT(hdlp->ih_dip == hdlp->ih_main->ih_dip);		\
37420036fe5Segillett 		ASSERT(hdlp->ih_type == hdlp->ih_main->ih_type);	\
37520036fe5Segillett 		ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector);	\
37620036fe5Segillett 		ASSERT(hdlp->ih_ver == hdlp->ih_main->ih_ver);		\
37720036fe5Segillett 		ASSERT(hdlp->ih_cap == hdlp->ih_main->ih_cap);		\
37820036fe5Segillett 		ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri);		\
37920036fe5Segillett 	}
38020036fe5Segillett #else
38120036fe5Segillett #define	I_DDI_VERIFY_MSIX_HANDLE(hdlp)
38220036fe5Segillett #endif
3847c478bd9Sstevel@tonic-gate #else	/* _KERNEL */
3867c478bd9Sstevel@tonic-gate typedef struct devinfo_intr devinfo_intr_t;
3887c478bd9Sstevel@tonic-gate #endif	/* _KERNEL */
3907c478bd9Sstevel@tonic-gate /*
3917c478bd9Sstevel@tonic-gate  * Used only by old DDI interrupt interfaces.
3927c478bd9Sstevel@tonic-gate  */
3947c478bd9Sstevel@tonic-gate /*
3957c478bd9Sstevel@tonic-gate  * This structure represents one interrupt possible from the given
3967c478bd9Sstevel@tonic-gate  * device. It is used in an array for devices with multiple interrupts.
3977c478bd9Sstevel@tonic-gate  */
3987c478bd9Sstevel@tonic-gate struct intrspec {
3997c478bd9Sstevel@tonic-gate 	uint_t intrspec_pri;		/* interrupt priority */
4007c478bd9Sstevel@tonic-gate 	uint_t intrspec_vec;		/* vector # (0 if none) */
4017c478bd9Sstevel@tonic-gate 	uint_t (*intrspec_func)();	/* function to call for interrupt, */
4027c478bd9Sstevel@tonic-gate 					/* If (uint_t (*)()) 0, none. */
4037c478bd9Sstevel@tonic-gate 					/* If (uint_t (*)()) 1, then */
4047c478bd9Sstevel@tonic-gate };
4067c478bd9Sstevel@tonic-gate #ifdef _KERNEL
408a54f81fbSanish /*
409a54f81fbSanish  * Figure out how many FIXED nintrs are supported
410a54f81fbSanish  */
411a54f81fbSanish int	i_ddi_get_intx_nintrs(dev_info_t *dip);
4137c478bd9Sstevel@tonic-gate /*
4147c478bd9Sstevel@tonic-gate  * NOTE:
4157c478bd9Sstevel@tonic-gate  *	The following 4 busops entry points are obsoleted with version
4167c478bd9Sstevel@tonic-gate  *	9 or greater. Use i_ddi_intr_op interface in place of these
4177c478bd9Sstevel@tonic-gate  *	obsolete interfaces.
4187c478bd9Sstevel@tonic-gate  *
4197c478bd9Sstevel@tonic-gate  *	Remove these busops entry points and all related data structures
4207c478bd9Sstevel@tonic-gate  *	in future minor/major solaris release.
4217c478bd9Sstevel@tonic-gate  */
4227c478bd9Sstevel@tonic-gate typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t;
424657f87deSgongtian zhao - Sun Microsystems - Beijing China /*
425657f87deSgongtian zhao - Sun Microsystems - Beijing China  * Interrupt get/set affinity functions
426657f87deSgongtian zhao - Sun Microsystems - Beijing China  */
427657f87deSgongtian zhao - Sun Microsystems - Beijing China int	get_intr_affinity(ddi_intr_handle_t h, processorid_t *tgt_p);
428657f87deSgongtian zhao - Sun Microsystems - Beijing China int	set_intr_affinity(ddi_intr_handle_t h, processorid_t tgt);
429657f87deSgongtian zhao - Sun Microsystems - Beijing China 
430d84bdf75Segillett /* The following are obsolete interfaces */
4317c478bd9Sstevel@tonic-gate ddi_intrspec_t	i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip,
4327c478bd9Sstevel@tonic-gate 	    uint_t inumber);
4347c478bd9Sstevel@tonic-gate int	i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip,
4357c478bd9Sstevel@tonic-gate 	    ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep,
4367c478bd9Sstevel@tonic-gate 	    ddi_idevice_cookie_t *idevice_cookiep,
4377c478bd9Sstevel@tonic-gate 	    uint_t (*int_handler)(caddr_t int_handler_arg),
4387c478bd9Sstevel@tonic-gate 	    caddr_t int_handler_arg, int kind);
4407c478bd9Sstevel@tonic-gate void	i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip,
4417c478bd9Sstevel@tonic-gate 	    ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie);
4437c478bd9Sstevel@tonic-gate int	i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip,
4447c478bd9Sstevel@tonic-gate 	    ddi_intr_ctlop_t op, void *arg, void *val);
4467c478bd9Sstevel@tonic-gate #endif	/* _KERNEL */
4487c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
4497c478bd9Sstevel@tonic-gate }
4507c478bd9Sstevel@tonic-gate #endif
4527c478bd9Sstevel@tonic-gate #endif	/* _SYS_DDI_INTR_IMPL_H */