17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5102cb92eSjohnny * Common Development and Distribution License (the "License"). 6102cb92eSjohnny * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22102cb92eSjohnny * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_DDI_INTR_IMPL_H 277c478bd9Sstevel@tonic-gate #define _SYS_DDI_INTR_IMPL_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate /* 327c478bd9Sstevel@tonic-gate * Sun DDI interrupt implementation specific definitions 337c478bd9Sstevel@tonic-gate */ 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate #ifdef __cplusplus 367c478bd9Sstevel@tonic-gate extern "C" { 377c478bd9Sstevel@tonic-gate #endif 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate #ifdef _KERNEL 407c478bd9Sstevel@tonic-gate 417c478bd9Sstevel@tonic-gate /* 427c478bd9Sstevel@tonic-gate * Typedef for interrupt ops 437c478bd9Sstevel@tonic-gate */ 447c478bd9Sstevel@tonic-gate typedef enum { 457c478bd9Sstevel@tonic-gate DDI_INTROP_SUPPORTED_TYPES = 1, /* 1 get supported interrupts types */ 467c478bd9Sstevel@tonic-gate DDI_INTROP_NINTRS, /* 2 get num of interrupts supported */ 477c478bd9Sstevel@tonic-gate DDI_INTROP_ALLOC, /* 3 allocate interrupt handle */ 487c478bd9Sstevel@tonic-gate DDI_INTROP_GETPRI, /* 4 get priority */ 497c478bd9Sstevel@tonic-gate DDI_INTROP_SETPRI, /* 5 set priority */ 507c478bd9Sstevel@tonic-gate DDI_INTROP_ADDISR, /* 6 add interrupt handler */ 517c478bd9Sstevel@tonic-gate DDI_INTROP_DUPVEC, /* 7 duplicate interrupt handler */ 527c478bd9Sstevel@tonic-gate DDI_INTROP_ENABLE, /* 8 enable interrupt */ 537c478bd9Sstevel@tonic-gate DDI_INTROP_BLOCKENABLE, /* 9 block enable interrupts */ 547c478bd9Sstevel@tonic-gate DDI_INTROP_BLOCKDISABLE, /* 10 block disable interrupts */ 557c478bd9Sstevel@tonic-gate DDI_INTROP_DISABLE, /* 11 disable interrupt */ 567c478bd9Sstevel@tonic-gate DDI_INTROP_REMISR, /* 12 remove interrupt handler */ 577c478bd9Sstevel@tonic-gate DDI_INTROP_FREE, /* 13 free interrupt handle */ 587c478bd9Sstevel@tonic-gate DDI_INTROP_GETCAP, /* 14 get capacity */ 597c478bd9Sstevel@tonic-gate DDI_INTROP_SETCAP, /* 15 set capacity */ 607c478bd9Sstevel@tonic-gate DDI_INTROP_SETMASK, /* 16 set mask */ 617c478bd9Sstevel@tonic-gate DDI_INTROP_CLRMASK, /* 17 clear mask */ 627c478bd9Sstevel@tonic-gate DDI_INTROP_GETPENDING, /* 18 get pending interrupt */ 637c478bd9Sstevel@tonic-gate DDI_INTROP_NAVAIL /* 19 get num of available interrupts */ 647c478bd9Sstevel@tonic-gate } ddi_intr_op_t; 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate /* Version number used in the handles */ 677c478bd9Sstevel@tonic-gate #define DDI_INTR_VERSION_1 1 687c478bd9Sstevel@tonic-gate #define DDI_INTR_VERSION DDI_INTR_VERSION_1 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate /* 717c478bd9Sstevel@tonic-gate * One such data structure is allocated per ddi_intr_handle_t 727c478bd9Sstevel@tonic-gate * This is the incore copy of the regular interrupt info. 737c478bd9Sstevel@tonic-gate */ 747c478bd9Sstevel@tonic-gate typedef struct ddi_intr_handle_impl { 757c478bd9Sstevel@tonic-gate dev_info_t *ih_dip; /* dip associated with handle */ 767c478bd9Sstevel@tonic-gate uint16_t ih_type; /* interrupt type being used */ 777c478bd9Sstevel@tonic-gate ushort_t ih_inum; /* interrupt number */ 78a195726fSgovinda uint32_t ih_vector; /* vector number */ 797c478bd9Sstevel@tonic-gate uint16_t ih_ver; /* Version */ 807c478bd9Sstevel@tonic-gate uint_t ih_state; /* interrupt handle state */ 817c478bd9Sstevel@tonic-gate uint_t ih_cap; /* interrupt capabilities */ 827c478bd9Sstevel@tonic-gate uint_t ih_pri; /* priority - bus dependent */ 837c478bd9Sstevel@tonic-gate krwlock_t ih_rwlock; /* read/write lock per handle */ 847c478bd9Sstevel@tonic-gate 857c478bd9Sstevel@tonic-gate uint_t (*ih_cb_func)(caddr_t, caddr_t); 867c478bd9Sstevel@tonic-gate void *ih_cb_arg1; 877c478bd9Sstevel@tonic-gate void *ih_cb_arg2; 887c478bd9Sstevel@tonic-gate 8920036fe5Segillett /* 9020036fe5Segillett * The following 3 members are used to support MSI-X specific features 9120036fe5Segillett */ 9220036fe5Segillett uint_t ih_flags; /* Misc flags */ 9320036fe5Segillett uint_t ih_dup_cnt; /* # of dupped msi-x vectors */ 9420036fe5Segillett struct ddi_intr_handle_impl *ih_main; 9520036fe5Segillett /* pntr to the main vector */ 967c478bd9Sstevel@tonic-gate /* 977c478bd9Sstevel@tonic-gate * The next set of members are for 'scratch' purpose only. 987c478bd9Sstevel@tonic-gate * The DDI interrupt framework uses them internally and their 997c478bd9Sstevel@tonic-gate * interpretation is left to the framework. For now, 1007c478bd9Sstevel@tonic-gate * scratch1 - used to send NINTRs information 1017c478bd9Sstevel@tonic-gate * to various nexus drivers. 1027c478bd9Sstevel@tonic-gate * scratch2 - used to send 'behavior' flag 1037c478bd9Sstevel@tonic-gate * information to the nexus drivers 104102cb92eSjohnny * from ddi_intr_alloc(). It is also 105102cb92eSjohnny * used to send 'h_array' to the nexus drivers 106102cb92eSjohnny * for ddi_intr_block_enable/disable() on x86. 1077a364d25Sschwartz * private - On X86 it usually carries a pointer to 1087a364d25Sschwartz * ihdl_plat_t. Not used on SPARC platforms. 1097c478bd9Sstevel@tonic-gate */ 1107c478bd9Sstevel@tonic-gate void *ih_private; /* Platform specific data */ 1117c478bd9Sstevel@tonic-gate uint_t ih_scratch1; /* Scratch1: #interrupts */ 112102cb92eSjohnny void *ih_scratch2; /* Scratch2: flag/h_array */ 1137c478bd9Sstevel@tonic-gate } ddi_intr_handle_impl_t; 1147c478bd9Sstevel@tonic-gate 1157c478bd9Sstevel@tonic-gate /* values for ih_state (strictly for interrupt handle) */ 1167c478bd9Sstevel@tonic-gate #define DDI_IHDL_STATE_ALLOC 0x01 /* Allocated. ddi_intr_alloc() called */ 1177c478bd9Sstevel@tonic-gate #define DDI_IHDL_STATE_ADDED 0x02 /* Added interrupt handler */ 1187c478bd9Sstevel@tonic-gate /* ddi_intr_add_handler() called */ 1197c478bd9Sstevel@tonic-gate #define DDI_IHDL_STATE_ENABLE 0x04 /* Enabled. ddi_intr_enable() called */ 1207c478bd9Sstevel@tonic-gate 1217c478bd9Sstevel@tonic-gate #define DDI_INTR_IS_MSI_OR_MSIX(type) \ 1227c478bd9Sstevel@tonic-gate ((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX) 1237c478bd9Sstevel@tonic-gate 124a195726fSgovinda #define DDI_INTR_SUP_TYPES DDI_INTR_TYPE_FIXED|DDI_INTR_TYPE_MSI|\ 125a195726fSgovinda DDI_INTR_TYPE_MSIX 126a195726fSgovinda 12720036fe5Segillett /* values for ih_flags */ 12820036fe5Segillett #define DDI_INTR_MSIX_DUP 0x01 /* MSI-X vector which has been dupped */ 12920036fe5Segillett 130e23a7e34Slq struct av_softinfo; 131e23a7e34Slq 1327c478bd9Sstevel@tonic-gate /* 1337c478bd9Sstevel@tonic-gate * One such data structure is allocated per ddi_soft_intr_handle 1347c478bd9Sstevel@tonic-gate * This is the incore copy of the softint info. 1357c478bd9Sstevel@tonic-gate */ 1367c478bd9Sstevel@tonic-gate typedef struct ddi_softint_hdl_impl { 1377c478bd9Sstevel@tonic-gate dev_info_t *ih_dip; /* dip associated with handle */ 1387c478bd9Sstevel@tonic-gate uint_t ih_pri; /* priority - bus dependent */ 1397c478bd9Sstevel@tonic-gate krwlock_t ih_rwlock; /* read/write lock per handle */ 140e23a7e34Slq struct av_softinfo *ih_pending; /* whether softint is pending */ 1417c478bd9Sstevel@tonic-gate 1427c478bd9Sstevel@tonic-gate uint_t (*ih_cb_func)(caddr_t, caddr_t); 1437c478bd9Sstevel@tonic-gate /* cb function for soft ints */ 1447c478bd9Sstevel@tonic-gate void *ih_cb_arg1; /* arg1 of callback function */ 1457c478bd9Sstevel@tonic-gate void *ih_cb_arg2; /* arg2 passed to "trigger" */ 1467c478bd9Sstevel@tonic-gate 1477c478bd9Sstevel@tonic-gate /* 1487c478bd9Sstevel@tonic-gate * The next member is for 'scratch' purpose only. 1497c478bd9Sstevel@tonic-gate * The DDI interrupt framework uses it internally and its 1507c478bd9Sstevel@tonic-gate * interpretation is left to the framework. 1517c478bd9Sstevel@tonic-gate * private - used by the DDI framework to pass back 1527c478bd9Sstevel@tonic-gate * and forth 'softid' information on SPARC 1537c478bd9Sstevel@tonic-gate * side only. Not used on X86 platform. 1547c478bd9Sstevel@tonic-gate */ 1557c478bd9Sstevel@tonic-gate void *ih_private; /* Platform specific data */ 1567c478bd9Sstevel@tonic-gate } ddi_softint_hdl_impl_t; 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate /* Softint internal implementation defines */ 1597c478bd9Sstevel@tonic-gate #define DDI_SOFT_INTR_PRI_M 4 1607c478bd9Sstevel@tonic-gate #define DDI_SOFT_INTR_PRI_H 6 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate /* 1637c478bd9Sstevel@tonic-gate * One such data structure is allocated for MSI-X enabled 1647c478bd9Sstevel@tonic-gate * device. If no MSI-X is enabled then it is NULL 1657c478bd9Sstevel@tonic-gate */ 1667c478bd9Sstevel@tonic-gate typedef struct ddi_intr_msix { 1677c478bd9Sstevel@tonic-gate /* MSI-X Table related information */ 1687c478bd9Sstevel@tonic-gate ddi_acc_handle_t msix_tbl_hdl; /* MSI-X table handle */ 1699c75c6bfSgovinda uint32_t *msix_tbl_addr; /* MSI-X table addr */ 1709c75c6bfSgovinda uint32_t msix_tbl_offset; /* MSI-X table offset */ 1717c478bd9Sstevel@tonic-gate 1727c478bd9Sstevel@tonic-gate /* MSI-X PBA Table related information */ 1737c478bd9Sstevel@tonic-gate ddi_acc_handle_t msix_pba_hdl; /* MSI-X PBA handle */ 1749c75c6bfSgovinda uint32_t *msix_pba_addr; /* MSI-X PBA addr */ 1759c75c6bfSgovinda uint32_t msix_pba_offset; /* MSI-X PBA offset */ 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate ddi_device_acc_attr_t msix_dev_attr; /* MSI-X device attr */ 1787c478bd9Sstevel@tonic-gate } ddi_intr_msix_t; 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate 1817c478bd9Sstevel@tonic-gate /* 1827c478bd9Sstevel@tonic-gate * One such data structure is allocated for each dip. 1837c478bd9Sstevel@tonic-gate * It has interrupt related information that can be 1847c478bd9Sstevel@tonic-gate * stored/retrieved for convenience. 1857c478bd9Sstevel@tonic-gate */ 1867c478bd9Sstevel@tonic-gate typedef struct devinfo_intr { 1877c478bd9Sstevel@tonic-gate /* These three fields show what the device is capable of */ 1887c478bd9Sstevel@tonic-gate uint_t devi_intr_sup_types; /* Intrs supported by device */ 1897c478bd9Sstevel@tonic-gate 1907c478bd9Sstevel@tonic-gate ddi_intr_msix_t *devi_msix_p; /* MSI-X info, if supported */ 1917c478bd9Sstevel@tonic-gate 1927c478bd9Sstevel@tonic-gate /* Next three fields show current status for the device */ 1937c478bd9Sstevel@tonic-gate uint_t devi_intr_curr_type; /* Interrupt type being used */ 1947c478bd9Sstevel@tonic-gate uint_t devi_intr_sup_nintrs; /* #intr supported */ 1957c478bd9Sstevel@tonic-gate uint_t devi_intr_curr_nintrs; /* #intr currently being used */ 1967c478bd9Sstevel@tonic-gate 1977c478bd9Sstevel@tonic-gate ddi_intr_handle_t **devi_intr_handle_p; /* Hdl for legacy intr APIs */ 198*d12abe7cSanish 199*d12abe7cSanish #if defined(__i386) || defined(__amd64) 200*d12abe7cSanish /* Save the PCI config space handle */ 201*d12abe7cSanish ddi_acc_handle_t devi_cfg_handle; 202*d12abe7cSanish int devi_cap_ptr; /* MSI or MSI-X cap pointer */ 203*d12abe7cSanish #endif 2047c478bd9Sstevel@tonic-gate } devinfo_intr_t; 2057c478bd9Sstevel@tonic-gate 2067c478bd9Sstevel@tonic-gate #define NEXUS_HAS_INTR_OP(dip) \ 2077c478bd9Sstevel@tonic-gate ((DEVI(dip)->devi_ops->devo_bus_ops) && \ 2087c478bd9Sstevel@tonic-gate (DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \ 2097c478bd9Sstevel@tonic-gate (DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op)) 2107c478bd9Sstevel@tonic-gate 2117c478bd9Sstevel@tonic-gate int i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op, 2127c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result); 2137c478bd9Sstevel@tonic-gate 2147c478bd9Sstevel@tonic-gate int i_ddi_add_softint(ddi_softint_hdl_impl_t *); 2157c478bd9Sstevel@tonic-gate void i_ddi_remove_softint(ddi_softint_hdl_impl_t *); 216b08160e2Sgovinda int i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *); 2177c478bd9Sstevel@tonic-gate int i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t); 2187c478bd9Sstevel@tonic-gate 2197c478bd9Sstevel@tonic-gate void i_ddi_intr_devi_init(dev_info_t *dip); 2207c478bd9Sstevel@tonic-gate void i_ddi_intr_devi_fini(dev_info_t *dip); 2217c478bd9Sstevel@tonic-gate 2227c478bd9Sstevel@tonic-gate uint_t i_ddi_intr_get_supported_types(dev_info_t *dip); 2237c478bd9Sstevel@tonic-gate void i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type); 2247c478bd9Sstevel@tonic-gate uint_t i_ddi_intr_get_current_type(dev_info_t *dip); 2257c478bd9Sstevel@tonic-gate void i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type); 2267c478bd9Sstevel@tonic-gate uint_t i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type); 2277c478bd9Sstevel@tonic-gate void i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs); 2287c478bd9Sstevel@tonic-gate uint_t i_ddi_intr_get_current_nintrs(dev_info_t *dip); 2297c478bd9Sstevel@tonic-gate void i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs); 2307c478bd9Sstevel@tonic-gate 231a195726fSgovinda ddi_intr_handle_t *i_ddi_get_intr_handle(dev_info_t *dip, int inum); 2327c478bd9Sstevel@tonic-gate void i_ddi_set_intr_handle(dev_info_t *dip, int inum, 2337c478bd9Sstevel@tonic-gate ddi_intr_handle_t *hdlp); 2347c478bd9Sstevel@tonic-gate 2357c478bd9Sstevel@tonic-gate ddi_intr_msix_t *i_ddi_get_msix(dev_info_t *dip); 2367c478bd9Sstevel@tonic-gate void i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p); 2377c478bd9Sstevel@tonic-gate 238*d12abe7cSanish #if defined(__i386) || defined(__amd64) 239*d12abe7cSanish ddi_acc_handle_t i_ddi_get_pci_config_handle(dev_info_t *dip); 240*d12abe7cSanish void i_ddi_set_pci_config_handle(dev_info_t *dip, ddi_acc_handle_t handle); 241*d12abe7cSanish int i_ddi_get_msi_msix_cap_ptr(dev_info_t *dip); 242*d12abe7cSanish void i_ddi_set_msi_msix_cap_ptr(dev_info_t *dip, int cap_ptr); 243*d12abe7cSanish #endif 244*d12abe7cSanish 2457c478bd9Sstevel@tonic-gate int32_t i_ddi_get_intr_weight(dev_info_t *); 2467c478bd9Sstevel@tonic-gate int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t); 2477c478bd9Sstevel@tonic-gate 2487a364d25Sschwartz void i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *); 2497a364d25Sschwartz void i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *); 2507a364d25Sschwartz 2517c478bd9Sstevel@tonic-gate #define DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \ 2527c478bd9Sstevel@tonic-gate hdlp->ih_cb_func = func; \ 2537c478bd9Sstevel@tonic-gate hdlp->ih_cb_arg1 = arg1; \ 2547c478bd9Sstevel@tonic-gate hdlp->ih_cb_arg2 = arg2; 2557c478bd9Sstevel@tonic-gate 25620036fe5Segillett #ifdef DEBUG 25720036fe5Segillett #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) \ 25820036fe5Segillett if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && \ 25920036fe5Segillett (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) { \ 26020036fe5Segillett ASSERT(hdlp->ih_dip == hdlp->ih_main->ih_dip); \ 26120036fe5Segillett ASSERT(hdlp->ih_type == hdlp->ih_main->ih_type); \ 26220036fe5Segillett ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector); \ 26320036fe5Segillett ASSERT(hdlp->ih_ver == hdlp->ih_main->ih_ver); \ 26420036fe5Segillett ASSERT(hdlp->ih_cap == hdlp->ih_main->ih_cap); \ 26520036fe5Segillett ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri); \ 26620036fe5Segillett } 26720036fe5Segillett #else 26820036fe5Segillett #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) 26920036fe5Segillett #endif 27020036fe5Segillett 2717c478bd9Sstevel@tonic-gate #else /* _KERNEL */ 2727c478bd9Sstevel@tonic-gate 2737c478bd9Sstevel@tonic-gate typedef struct devinfo_intr devinfo_intr_t; 2747c478bd9Sstevel@tonic-gate 2757c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 2767c478bd9Sstevel@tonic-gate 2777c478bd9Sstevel@tonic-gate /* 2787c478bd9Sstevel@tonic-gate * Used only by old DDI interrupt interfaces. 2797c478bd9Sstevel@tonic-gate */ 2807c478bd9Sstevel@tonic-gate 2817c478bd9Sstevel@tonic-gate /* 2827c478bd9Sstevel@tonic-gate * This structure represents one interrupt possible from the given 2837c478bd9Sstevel@tonic-gate * device. It is used in an array for devices with multiple interrupts. 2847c478bd9Sstevel@tonic-gate */ 2857c478bd9Sstevel@tonic-gate struct intrspec { 2867c478bd9Sstevel@tonic-gate uint_t intrspec_pri; /* interrupt priority */ 2877c478bd9Sstevel@tonic-gate uint_t intrspec_vec; /* vector # (0 if none) */ 2887c478bd9Sstevel@tonic-gate uint_t (*intrspec_func)(); /* function to call for interrupt, */ 2897c478bd9Sstevel@tonic-gate /* If (uint_t (*)()) 0, none. */ 2907c478bd9Sstevel@tonic-gate /* If (uint_t (*)()) 1, then */ 2917c478bd9Sstevel@tonic-gate }; 2927c478bd9Sstevel@tonic-gate 2937c478bd9Sstevel@tonic-gate #ifdef _KERNEL 2947c478bd9Sstevel@tonic-gate 2957c478bd9Sstevel@tonic-gate /* 2967c478bd9Sstevel@tonic-gate * NOTE: 2977c478bd9Sstevel@tonic-gate * The following 4 busops entry points are obsoleted with version 2987c478bd9Sstevel@tonic-gate * 9 or greater. Use i_ddi_intr_op interface in place of these 2997c478bd9Sstevel@tonic-gate * obsolete interfaces. 3007c478bd9Sstevel@tonic-gate * 3017c478bd9Sstevel@tonic-gate * Remove these busops entry points and all related data structures 3027c478bd9Sstevel@tonic-gate * in future minor/major solaris release. 3037c478bd9Sstevel@tonic-gate */ 3047c478bd9Sstevel@tonic-gate typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t; 3057c478bd9Sstevel@tonic-gate 3067c478bd9Sstevel@tonic-gate /* The following are the obsolete interfaces */ 3077c478bd9Sstevel@tonic-gate ddi_intrspec_t i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip, 3087c478bd9Sstevel@tonic-gate uint_t inumber); 3097c478bd9Sstevel@tonic-gate 3107c478bd9Sstevel@tonic-gate int i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip, 3117c478bd9Sstevel@tonic-gate ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep, 3127c478bd9Sstevel@tonic-gate ddi_idevice_cookie_t *idevice_cookiep, 3137c478bd9Sstevel@tonic-gate uint_t (*int_handler)(caddr_t int_handler_arg), 3147c478bd9Sstevel@tonic-gate caddr_t int_handler_arg, int kind); 3157c478bd9Sstevel@tonic-gate 3167c478bd9Sstevel@tonic-gate void i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip, 3177c478bd9Sstevel@tonic-gate ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie); 3187c478bd9Sstevel@tonic-gate 3197c478bd9Sstevel@tonic-gate int i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip, 3207c478bd9Sstevel@tonic-gate ddi_intr_ctlop_t op, void *arg, void *val); 3217c478bd9Sstevel@tonic-gate 3227c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 3237c478bd9Sstevel@tonic-gate 3247c478bd9Sstevel@tonic-gate #ifdef __cplusplus 3257c478bd9Sstevel@tonic-gate } 3267c478bd9Sstevel@tonic-gate #endif 3277c478bd9Sstevel@tonic-gate 3287c478bd9Sstevel@tonic-gate #endif /* _SYS_DDI_INTR_IMPL_H */ 329