xref: /illumos-gate/usr/src/uts/common/sys/cpu_pm.h (revision 113b131b)
10e751525SEric Saxe /*
20e751525SEric Saxe  * CDDL HEADER START
30e751525SEric Saxe  *
40e751525SEric Saxe  * The contents of this file are subject to the terms of the
50e751525SEric Saxe  * Common Development and Distribution License (the "License").
60e751525SEric Saxe  * You may not use this file except in compliance with the License.
70e751525SEric Saxe  *
80e751525SEric Saxe  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90e751525SEric Saxe  * or http://www.opensolaris.org/os/licensing.
100e751525SEric Saxe  * See the License for the specific language governing permissions
110e751525SEric Saxe  * and limitations under the License.
120e751525SEric Saxe  *
130e751525SEric Saxe  * When distributing Covered Code, include this CDDL HEADER in each
140e751525SEric Saxe  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150e751525SEric Saxe  * If applicable, add the following below this CDDL HEADER, with the
160e751525SEric Saxe  * fields enclosed by brackets "[]" replaced with your own identifying
170e751525SEric Saxe  * information: Portions Copyright [yyyy] [name of copyright owner]
180e751525SEric Saxe  *
190e751525SEric Saxe  * CDDL HEADER END
200e751525SEric Saxe  */
210e751525SEric Saxe /*
220e751525SEric Saxe  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
230e751525SEric Saxe  * Use is subject to license terms.
240e751525SEric Saxe  */
250e751525SEric Saxe 
260e751525SEric Saxe #ifndef	_CPU_PM_H
270e751525SEric Saxe #define	_CPU_PM_H
280e751525SEric Saxe 
290e751525SEric Saxe #ifdef	__cplusplus
300e751525SEric Saxe extern "C" {
310e751525SEric Saxe #endif
320e751525SEric Saxe 
330e751525SEric Saxe #if (defined(_KERNEL) || defined(_KMEMUSER))
340e751525SEric Saxe #include <sys/cpuvar.h>
350e751525SEric Saxe #include <sys/processor.h>
360e751525SEric Saxe #include <sys/types.h>
370e751525SEric Saxe #include <sys/kstat.h>
380e751525SEric Saxe #include <sys/cmt.h>
390e751525SEric Saxe 
400e751525SEric Saxe /*
410e751525SEric Saxe  * CPU Power Manager Policies
420e751525SEric Saxe  */
430e751525SEric Saxe typedef enum cpupm_policy {
440e751525SEric Saxe 	CPUPM_POLICY_ELASTIC,
450e751525SEric Saxe 	CPUPM_POLICY_DISABLED,
460e751525SEric Saxe 	CPUPM_NUM_POLICIES
470e751525SEric Saxe } cpupm_policy_t;
480e751525SEric Saxe 
490e751525SEric Saxe /*
500e751525SEric Saxe  * Power Managable CPU Domain Types
510e751525SEric Saxe  */
520e751525SEric Saxe typedef enum cpupm_dtype {
530e751525SEric Saxe 	CPUPM_DTYPE_ACTIVE,	/* Active Power Domain */
540e751525SEric Saxe 	CPUPM_DTYPE_IDLE	/* Idle Power Domain */
550e751525SEric Saxe } cpupm_dtype_t;
560e751525SEric Saxe 
570e751525SEric Saxe /*
580e751525SEric Saxe  * CPUPM state names for policy implementation.
590e751525SEric Saxe  * The last element is used to size the enumeration.
600e751525SEric Saxe  */
610e751525SEric Saxe typedef enum cpupm_state_name {
620e751525SEric Saxe 	CPUPM_STATE_LOW_POWER,
630e751525SEric Saxe 	CPUPM_STATE_MAX_PERF,
640e751525SEric Saxe 	CPUPM_STATE_NAMES
650e751525SEric Saxe } cpupm_state_name_t;
660e751525SEric Saxe 
67*113b131bSEric Saxe /*
68*113b131bSEric Saxe  * Possible states for the domain's transience governor
69*113b131bSEric Saxe  */
70*113b131bSEric Saxe typedef enum cpupm_gov_state_t {
71*113b131bSEric Saxe 	CPUPM_GOV_DISENGAGED,
72*113b131bSEric Saxe 	CPUPM_GOV_TRANS_IDLE,	/* Transient idleness, lowerings disabled */
73*113b131bSEric Saxe 	CPUPM_GOV_TRANS_WORK	/* Transient work, raises disabled */
74*113b131bSEric Saxe } cpupm_gov_state_t;
75*113b131bSEric Saxe 
760e751525SEric Saxe /*
770e751525SEric Saxe  * Utilization events delivered by the dispatcher.
780e751525SEric Saxe  */
790e751525SEric Saxe typedef enum cpupm_util_event {
800e751525SEric Saxe 	CPUPM_DOM_BUSY_FROM_IDLE,
810e751525SEric Saxe 	CPUPM_DOM_IDLE_FROM_BUSY,
820e751525SEric Saxe 	CPUPM_DOM_REMAIN_BUSY
830e751525SEric Saxe } cpupm_util_event_t;
840e751525SEric Saxe 
850e751525SEric Saxe typedef uintptr_t	cpupm_handle_t;	/* Platform handle */
860e751525SEric Saxe 
870e751525SEric Saxe /*
880e751525SEric Saxe  * CPU Power Domain State
890e751525SEric Saxe  */
900e751525SEric Saxe typedef struct cpupm_state {
910e751525SEric Saxe 	uint32_t	cps_speed;
920e751525SEric Saxe 	cpupm_handle_t	cps_handle;
930e751525SEric Saxe } cpupm_state_t;
940e751525SEric Saxe 
950e751525SEric Saxe /*
960e751525SEric Saxe  * CPU Power Domain
970e751525SEric Saxe  */
980e751525SEric Saxe typedef struct cpupm_domain {
990e751525SEric Saxe 	id_t			cpd_id;		/* Domain ID */
1000e751525SEric Saxe 	cpupm_dtype_t		cpd_type;	/* Active or Idle */
1010e751525SEric Saxe 	cpupm_state_t		*cpd_states;	/* Available Power States */
1020e751525SEric Saxe 	cpupm_state_t		*cpd_state;	/* Current State */
1030e751525SEric Saxe 	uint_t			cpd_nstates;	/* Number of States */
1040e751525SEric Saxe 	cpupm_state_t		*cpd_named_states[CPUPM_STATE_NAMES];
1050e751525SEric Saxe 	hrtime_t		cpd_last_raise;	/* Last raise request time */
1060e751525SEric Saxe 	hrtime_t		cpd_last_lower;	/* last lower request time */
1070e751525SEric Saxe 	int			cpd_ti;		/* transient idle history */
108*113b131bSEric Saxe 	int			cpd_tw;		/* transient work history */
109*113b131bSEric Saxe 	cpupm_gov_state_t	cpd_governor;   /* transience governor */
1100e751525SEric Saxe 	struct cpupm_domain	*cpd_next;
1110e751525SEric Saxe } cpupm_domain_t;
1120e751525SEric Saxe 
1130e751525SEric Saxe #define	CPUPM_NO_DOMAIN ((id_t)-1)
1140e751525SEric Saxe 
1150e751525SEric Saxe /*
1160e751525SEric Saxe  * CPU power manager domain management interfaces
1170e751525SEric Saxe  */
1180e751525SEric Saxe cpupm_domain_t		*cpupm_domain_init(struct cpu *, cpupm_dtype_t);
1190e751525SEric Saxe id_t			cpupm_domain_id(struct cpu *, cpupm_dtype_t);
1200e751525SEric Saxe int			cpupm_change_state(struct cpu *, cpupm_domain_t *,
1210e751525SEric Saxe     cpupm_state_t *);
1220e751525SEric Saxe extern void		cpupm_redefine_max_activepwr_state(struct cpu *, int);
1230e751525SEric Saxe 
1240e751525SEric Saxe /*
1250e751525SEric Saxe  * CPU power manager policy engine interfaces
1260e751525SEric Saxe  */
1270e751525SEric Saxe int			cpupm_set_policy(cpupm_policy_t);
1280e751525SEric Saxe cpupm_policy_t		cpupm_get_policy(void);
1290e751525SEric Saxe void			cpupm_utilization_event(struct cpu *, hrtime_t,
1300e751525SEric Saxe 			    cpupm_domain_t *, cpupm_util_event_t);
1310e751525SEric Saxe 
1320e751525SEric Saxe /*
1330e751525SEric Saxe  * CPU power platform driver interfaces
1340e751525SEric Saxe  */
1350e751525SEric Saxe id_t	cpupm_plat_domain_id(struct cpu *, cpupm_dtype_t);
1360e751525SEric Saxe uint_t	cpupm_plat_state_enumerate(struct cpu *, cpupm_dtype_t,
1370e751525SEric Saxe     cpupm_state_t *);
1380e751525SEric Saxe int	cpupm_plat_change_state(struct cpu *, cpupm_state_t *);
1390e751525SEric Saxe 
1400e751525SEric Saxe 
1410e751525SEric Saxe #endif	/* !_KERNEL && !_KMEMUSER */
1420e751525SEric Saxe 
1430e751525SEric Saxe #ifdef	__cplusplus
1440e751525SEric Saxe }
1450e751525SEric Saxe #endif
1460e751525SEric Saxe 
1470e751525SEric Saxe #endif /* _CPU_PM_H */
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