1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*7c478bd9Sstevel@tonic-gate * All rights reserved. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate /* 31*7c478bd9Sstevel@tonic-gate * hci1394_ioctl.h 32*7c478bd9Sstevel@tonic-gate * Test ioctl's to support test/debug of the 1394 HW. hci1394_ioctl_enum_t is 33*7c478bd9Sstevel@tonic-gate * passed in cmd and a pointer to the appropriate structure (i.e. 34*7c478bd9Sstevel@tonic-gate * hci1394_ioctl_wrreg_t) is passed in arg. 35*7c478bd9Sstevel@tonic-gate */ 36*7c478bd9Sstevel@tonic-gate 37*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 38*7c478bd9Sstevel@tonic-gate extern "C" { 39*7c478bd9Sstevel@tonic-gate #endif 40*7c478bd9Sstevel@tonic-gate 41*7c478bd9Sstevel@tonic-gate 42*7c478bd9Sstevel@tonic-gate /* 43*7c478bd9Sstevel@tonic-gate * write_reg - write OpenHCI register 44*7c478bd9Sstevel@tonic-gate * read_reg - read OpenHCI register 45*7c478bd9Sstevel@tonic-gate * write_vreg - write OpenHCI Vendor Specific register 46*7c478bd9Sstevel@tonic-gate * read_vreg - read OpenHCI Vendor Specific register 47*7c478bd9Sstevel@tonic-gate * reset_bus - reset the 1394 bus 48*7c478bd9Sstevel@tonic-gate * selfid_cnt - return the number of times we saw the selfid complete 49*7c478bd9Sstevel@tonic-gate * interrupt signifying a bus reset has completed. This does not 50*7c478bd9Sstevel@tonic-gate * have to match the bus generation and probably won't. 51*7c478bd9Sstevel@tonic-gate * busgen_cnt - return the current bus generation 52*7c478bd9Sstevel@tonic-gate * read_selfid - read selfid buffer 53*7c478bd9Sstevel@tonic-gate * write_phy - write PHY register 54*7c478bd9Sstevel@tonic-gate * read_phy - read PHY register 55*7c478bd9Sstevel@tonic-gate * hba_info - HBA vendor information 56*7c478bd9Sstevel@tonic-gate */ 57*7c478bd9Sstevel@tonic-gate #define HCI11394_IOCTL ('f' << 8) 58*7c478bd9Sstevel@tonic-gate typedef enum { 59*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_WRITE_REG = HCI11394_IOCTL | 0x00, 60*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_READ_REG = HCI11394_IOCTL | 0x01, 61*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_WRITE_VREG = HCI11394_IOCTL | 0x02, 62*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_READ_VREG = HCI11394_IOCTL | 0x03, 63*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_RESET_BUS = HCI11394_IOCTL | 0x04, 64*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_SELFID_CNT = HCI11394_IOCTL | 0x05, 65*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_BUSGEN_CNT = HCI11394_IOCTL | 0x06, 66*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_READ_SELFID = HCI11394_IOCTL | 0x07, 67*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_WRITE_PHY = HCI11394_IOCTL | 0x08, 68*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_READ_PHY = HCI11394_IOCTL | 0x09, 69*7c478bd9Sstevel@tonic-gate HCI1394_IOCTL_HBA_INFO = HCI11394_IOCTL | 0x0A 70*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_enum_t; 71*7c478bd9Sstevel@tonic-gate 72*7c478bd9Sstevel@tonic-gate 73*7c478bd9Sstevel@tonic-gate /* 74*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_WRITE_REG 75*7c478bd9Sstevel@tonic-gate * Write OHCI register. addr is an offset into the OpenHCI register map. 76*7c478bd9Sstevel@tonic-gate * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 77*7c478bd9Sstevel@tonic-gate * aligned (i.e. 0, 4, 8, C, 10). data is the 32-bit word to write into the 78*7c478bd9Sstevel@tonic-gate * OpenHCI register. 79*7c478bd9Sstevel@tonic-gate * 80*7c478bd9Sstevel@tonic-gate * NOTE: Writing OpenHCI registers can cause the hardware and/or SW to 81*7c478bd9Sstevel@tonic-gate * misbehave. Extreme care should be used when using this call. 82*7c478bd9Sstevel@tonic-gate */ 83*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_wrreg_s { 84*7c478bd9Sstevel@tonic-gate uint_t addr; 85*7c478bd9Sstevel@tonic-gate uint32_t data; 86*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_wrreg_t; 87*7c478bd9Sstevel@tonic-gate 88*7c478bd9Sstevel@tonic-gate 89*7c478bd9Sstevel@tonic-gate /* 90*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_READ_REG 91*7c478bd9Sstevel@tonic-gate * Read OHCI register. addr is an offset into the OpenHCI register map. 92*7c478bd9Sstevel@tonic-gate * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 93*7c478bd9Sstevel@tonic-gate * aligned (i.e. 0, 4, 8, C, 10). When the ioctl returns successfully, data 94*7c478bd9Sstevel@tonic-gate * will contain the 32-bit word read from the OHCI register. 95*7c478bd9Sstevel@tonic-gate */ 96*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_rdreg_s { 97*7c478bd9Sstevel@tonic-gate uint_t addr; 98*7c478bd9Sstevel@tonic-gate uint32_t data; 99*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_rdreg_t; 100*7c478bd9Sstevel@tonic-gate 101*7c478bd9Sstevel@tonic-gate 102*7c478bd9Sstevel@tonic-gate /* 103*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_WRITE_VREG 104*7c478bd9Sstevel@tonic-gate * Write Vendor Specific OHCI register. addr is an offset into the Vendor 105*7c478bd9Sstevel@tonic-gate * Specific OpenHCI register map. (i.e. addr = 0 would write to the first 106*7c478bd9Sstevel@tonic-gate * Vendor Specific register. addr must be 32-bit aligned (i.e. 0, 4, 8, C, 107*7c478bd9Sstevel@tonic-gate * 10). data is the 32-bit word to write into the Vendor Specific OpenHCI 108*7c478bd9Sstevel@tonic-gate * register. regset defines which vendor specific register set to write to. 109*7c478bd9Sstevel@tonic-gate * There will usually be one vendor specific register set so this will 110*7c478bd9Sstevel@tonic-gate * usually be set to 0. 111*7c478bd9Sstevel@tonic-gate * 112*7c478bd9Sstevel@tonic-gate * NOTE: Writing Vendor Specific OpenHCI registers can cause the hardware 113*7c478bd9Sstevel@tonic-gate * and/or SW to misbehave. Extreme care should be used when using this 114*7c478bd9Sstevel@tonic-gate * call. 115*7c478bd9Sstevel@tonic-gate */ 116*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_wrvreg_s { 117*7c478bd9Sstevel@tonic-gate uint_t regset; 118*7c478bd9Sstevel@tonic-gate uint_t addr; 119*7c478bd9Sstevel@tonic-gate uint32_t data; 120*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_wrvreg_t; 121*7c478bd9Sstevel@tonic-gate 122*7c478bd9Sstevel@tonic-gate 123*7c478bd9Sstevel@tonic-gate /* 124*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_READ_VREG 125*7c478bd9Sstevel@tonic-gate * Read Vendor specific OHCI register. addr is an offset into the Vendor 126*7c478bd9Sstevel@tonic-gate * Specific OpenHCI register space. (i.e. addr = 0 is the first Vendor 127*7c478bd9Sstevel@tonic-gate * Specific register). addr must be 32-bit aligned (i.e. 0, 4, 8, C, 10). 128*7c478bd9Sstevel@tonic-gate * When the ioctl returns successfully, data will contain the 32-bit word 129*7c478bd9Sstevel@tonic-gate * read from the Vendor Specific OHCI register. regset defines which vendor 130*7c478bd9Sstevel@tonic-gate * specific register set to read from. There will usually be one vendor 131*7c478bd9Sstevel@tonic-gate * specific register set so this will usually be set to 0. 132*7c478bd9Sstevel@tonic-gate */ 133*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_rdvreg_s { 134*7c478bd9Sstevel@tonic-gate uint_t regset; 135*7c478bd9Sstevel@tonic-gate uint_t addr; 136*7c478bd9Sstevel@tonic-gate uint32_t data; 137*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_rdvreg_t; 138*7c478bd9Sstevel@tonic-gate 139*7c478bd9Sstevel@tonic-gate 140*7c478bd9Sstevel@tonic-gate /* HCI1394_IOCTL_RESET_BUS has no parameters */ 141*7c478bd9Sstevel@tonic-gate 142*7c478bd9Sstevel@tonic-gate 143*7c478bd9Sstevel@tonic-gate /* 144*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_SELFID_CNT 145*7c478bd9Sstevel@tonic-gate * When the ioctl returns successfully, count will contain the number of 146*7c478bd9Sstevel@tonic-gate * times the nexus driver has seen and responded to a selfid_complete 147*7c478bd9Sstevel@tonic-gate * interrupt. This interrupt signifies that the bus reset has completed 148*7c478bd9Sstevel@tonic-gate * and the hardware based bus enumeration has completed. This number will 149*7c478bd9Sstevel@tonic-gate * most likely not be the same as the bus generation. Everytime this 150*7c478bd9Sstevel@tonic-gate * increments, the bus generation count should increment by at least one. 151*7c478bd9Sstevel@tonic-gate * 152*7c478bd9Sstevel@tonic-gate * NOTE: The current implementation of the nexus driver uses a uint_t for 153*7c478bd9Sstevel@tonic-gate * selfid_cnt. 154*7c478bd9Sstevel@tonic-gate */ 155*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_selfid_cnt_s { 156*7c478bd9Sstevel@tonic-gate uint_t count; 157*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_selfid_cnt_t; 158*7c478bd9Sstevel@tonic-gate 159*7c478bd9Sstevel@tonic-gate 160*7c478bd9Sstevel@tonic-gate /* 161*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_BUSGEN_CNT 162*7c478bd9Sstevel@tonic-gate * When the ioctl returns successfully, count will contain the current 1394 163*7c478bd9Sstevel@tonic-gate * bus generation count. 164*7c478bd9Sstevel@tonic-gate * 165*7c478bd9Sstevel@tonic-gate * NOTE: The current implementation of the nexus driver uses the OpenHCI 166*7c478bd9Sstevel@tonic-gate * generation count which is an 8 bit value. Therefore, this count will 167*7c478bd9Sstevel@tonic-gate * wrap over at 0xFF. 168*7c478bd9Sstevel@tonic-gate */ 169*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_busgen_cnt_s { 170*7c478bd9Sstevel@tonic-gate uint_t count; 171*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_busgen_cnt_t; 172*7c478bd9Sstevel@tonic-gate 173*7c478bd9Sstevel@tonic-gate 174*7c478bd9Sstevel@tonic-gate /* 175*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_READ_SELFID 176*7c478bd9Sstevel@tonic-gate * Copies the contents of the selfid buffer into a buffer pointed to by buf. 177*7c478bd9Sstevel@tonic-gate * Count is the number of 32-bit words to copy into buf. The maximum size 178*7c478bd9Sstevel@tonic-gate * of the selfid buffer is 1024 32-bit words. The very first word is the 179*7c478bd9Sstevel@tonic-gate * OpenHCI selfid header. 180*7c478bd9Sstevel@tonic-gate */ 181*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_read_selfid_s { 182*7c478bd9Sstevel@tonic-gate uint32_t *buf; 183*7c478bd9Sstevel@tonic-gate uint_t count; 184*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_read_selfid_t; 185*7c478bd9Sstevel@tonic-gate 186*7c478bd9Sstevel@tonic-gate 187*7c478bd9Sstevel@tonic-gate /* 188*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_WRPHY 189*7c478bd9Sstevel@tonic-gate * Write PHY register. addr is an offset into the phy register space. 190*7c478bd9Sstevel@tonic-gate * (i.e. addr = 0 is the first phy register). addr is byte aligned 191*7c478bd9Sstevel@tonic-gate * (i.e. 0, 1, 2, 3, 4). data should contain the 8-bit value to write to the 192*7c478bd9Sstevel@tonic-gate * PHY register. The data should be stored as follows <0x000000dd> where dd 193*7c478bd9Sstevel@tonic-gate * is the byte written. 194*7c478bd9Sstevel@tonic-gate * 195*7c478bd9Sstevel@tonic-gate * NOTE: Phy register 0 cannot be read or written. 196*7c478bd9Sstevel@tonic-gate * 197*7c478bd9Sstevel@tonic-gate * NOTE: Writing PHY registers can cause the hardware and/or SW to misbehave. 198*7c478bd9Sstevel@tonic-gate * Extreme care should be used when using this call. 199*7c478bd9Sstevel@tonic-gate */ 200*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_wrphy_s { 201*7c478bd9Sstevel@tonic-gate uint_t addr; 202*7c478bd9Sstevel@tonic-gate uint_t data; 203*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_wrphy_t; 204*7c478bd9Sstevel@tonic-gate 205*7c478bd9Sstevel@tonic-gate 206*7c478bd9Sstevel@tonic-gate /* 207*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_RDPHY 208*7c478bd9Sstevel@tonic-gate * Read PHY register. addr is an offset into the phy register space. 209*7c478bd9Sstevel@tonic-gate * (i.e. addr = 0 is the first phy register). addr is byte aligned 210*7c478bd9Sstevel@tonic-gate * (i.e. 0, 1, 2, 3, 4). When the ioctl returns successfully, data will 211*7c478bd9Sstevel@tonic-gate * contain the 8-bit data read from the PHY register. The data will be stored 212*7c478bd9Sstevel@tonic-gate * as follows <0x000000dd> where dd is the byte read. 213*7c478bd9Sstevel@tonic-gate * 214*7c478bd9Sstevel@tonic-gate * NOTE: Phy register 0 cannot be read or written. 215*7c478bd9Sstevel@tonic-gate */ 216*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_rdphy_s { 217*7c478bd9Sstevel@tonic-gate uint_t addr; 218*7c478bd9Sstevel@tonic-gate uint_t data; 219*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_rdphy_t; 220*7c478bd9Sstevel@tonic-gate 221*7c478bd9Sstevel@tonic-gate 222*7c478bd9Sstevel@tonic-gate /* 223*7c478bd9Sstevel@tonic-gate * HCI1394_IOCTL_HBA_INFO 224*7c478bd9Sstevel@tonic-gate * HBA Vendor Information 225*7c478bd9Sstevel@tonic-gate * 226*7c478bd9Sstevel@tonic-gate * Vendor Specific Info 227*7c478bd9Sstevel@tonic-gate * pci_vendor_id - VendorID from PCI config space (0x0-0x1) 228*7c478bd9Sstevel@tonic-gate * pci_device_id - DeviceID from PCI config space (0x2-0x3) 229*7c478bd9Sstevel@tonic-gate * pci_revision_id - RevisionID from PCI config space (0x8) 230*7c478bd9Sstevel@tonic-gate * ohci_version - 1394 OpenHCI Version Register (0x0) 231*7c478bd9Sstevel@tonic-gate * ohci_vendor_id - 1394 OpenHCI Vendor ID Register (0x40) 232*7c478bd9Sstevel@tonic-gate * ohci_vregset_cnt - Number of vendor specific register maps that have been 233*7c478bd9Sstevel@tonic-gate * mapped by the driver. The driver will only map in 234*7c478bd9Sstevel@tonic-gate * vendor specific registers for adapters it knows about. 235*7c478bd9Sstevel@tonic-gate */ 236*7c478bd9Sstevel@tonic-gate typedef struct hci1394_ioctl_hbainfo_s { 237*7c478bd9Sstevel@tonic-gate uint_t pci_vendor_id; 238*7c478bd9Sstevel@tonic-gate uint_t pci_device_id; 239*7c478bd9Sstevel@tonic-gate uint_t pci_revision_id; 240*7c478bd9Sstevel@tonic-gate uint32_t ohci_version; 241*7c478bd9Sstevel@tonic-gate uint32_t ohci_vendor_id; 242*7c478bd9Sstevel@tonic-gate uint_t ohci_vregset_cnt; 243*7c478bd9Sstevel@tonic-gate } hci1394_ioctl_hbainfo_t; 244*7c478bd9Sstevel@tonic-gate 245*7c478bd9Sstevel@tonic-gate 246*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 247*7c478bd9Sstevel@tonic-gate } 248*7c478bd9Sstevel@tonic-gate #endif 249*7c478bd9Sstevel@tonic-gate 250*7c478bd9Sstevel@tonic-gate #endif /* _SYS_1394_ADAPTERS_HCI1394_IOCTL_H */ 251