1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*7c478bd9Sstevel@tonic-gate * All rights reserved. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate /* 31*7c478bd9Sstevel@tonic-gate * hci1394_descriptors.h 32*7c478bd9Sstevel@tonic-gate * 1394 Open HCI command descriptors. 33*7c478bd9Sstevel@tonic-gate * These are DMA commands chained together to form packets. 34*7c478bd9Sstevel@tonic-gate */ 35*7c478bd9Sstevel@tonic-gate 36*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 37*7c478bd9Sstevel@tonic-gate extern "C" { 38*7c478bd9Sstevel@tonic-gate #endif 39*7c478bd9Sstevel@tonic-gate 40*7c478bd9Sstevel@tonic-gate #include <sys/note.h> 41*7c478bd9Sstevel@tonic-gate 42*7c478bd9Sstevel@tonic-gate /* 43*7c478bd9Sstevel@tonic-gate * There are 2 different 1394 Open HCI entities defined in this file. 44*7c478bd9Sstevel@tonic-gate * The HCI DMA descriptors (aka context descriptors or descriptor 45*7c478bd9Sstevel@tonic-gate * commands), and the packet formats. 46*7c478bd9Sstevel@tonic-gate * 47*7c478bd9Sstevel@tonic-gate * Packet formats are used within descriptors for transmit and 48*7c478bd9Sstevel@tonic-gate * are available in buffers for receive. EACH PACKET TYPE 49*7c478bd9Sstevel@tonic-gate * (such as read_quadlet_request) may have a different format 50*7c478bd9Sstevel@tonic-gate * depending on whether it is to be transmitted or whether it 51*7c478bd9Sstevel@tonic-gate * is being received. 52*7c478bd9Sstevel@tonic-gate * 53*7c478bd9Sstevel@tonic-gate * In general, fields within a packet remain in the same location 54*7c478bd9Sstevel@tonic-gate * within a quadlet either way. However, the location of the 55*7c478bd9Sstevel@tonic-gate * quadlets themselves may be different. 56*7c478bd9Sstevel@tonic-gate * 57*7c478bd9Sstevel@tonic-gate * In an attempt to clarify what is used for what, Macros used 58*7c478bd9Sstevel@tonic-gate * for setting up packets within a descriptor (an "Immediate" command) 59*7c478bd9Sstevel@tonic-gate * shall have "DESC" in their name. Macros used for reading packets 60*7c478bd9Sstevel@tonic-gate * from an input buffer shall have "PKT" in their name. 61*7c478bd9Sstevel@tonic-gate * 62*7c478bd9Sstevel@tonic-gate * For more information, see OpenHCI 1.00 chapters 7 (Asynch Transmit), 63*7c478bd9Sstevel@tonic-gate * 8 (Asynch Receive), 9 (Isoch Transmit) and 10 (Isoch Receive). 64*7c478bd9Sstevel@tonic-gate * Each chapter shows the DMA descriptors at the beginning, and 65*7c478bd9Sstevel@tonic-gate * the packet formats at the end. 66*7c478bd9Sstevel@tonic-gate * Also see chapter 11 (Self ID). 67*7c478bd9Sstevel@tonic-gate */ 68*7c478bd9Sstevel@tonic-gate 69*7c478bd9Sstevel@tonic-gate 70*7c478bd9Sstevel@tonic-gate /* 71*7c478bd9Sstevel@tonic-gate * hci1394_desc is the basic format used for the following descriptor commands: 72*7c478bd9Sstevel@tonic-gate * OUTPUT_MORE, OUTPUT_LAST, INPUT_MORE and INPUT_LAST 73*7c478bd9Sstevel@tonic-gate */ 74*7c478bd9Sstevel@tonic-gate typedef struct hci1394_desc_s { 75*7c478bd9Sstevel@tonic-gate uint32_t hdr; 76*7c478bd9Sstevel@tonic-gate uint32_t data_addr; 77*7c478bd9Sstevel@tonic-gate uint32_t branch; /* branch or skip address (& Z) */ 78*7c478bd9Sstevel@tonic-gate uint32_t status; /* status and/or (timestamp or rescount) */ 79*7c478bd9Sstevel@tonic-gate } hci1394_desc_t; 80*7c478bd9Sstevel@tonic-gate 81*7c478bd9Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_desc_s)) 82*7c478bd9Sstevel@tonic-gate 83*7c478bd9Sstevel@tonic-gate /* 84*7c478bd9Sstevel@tonic-gate * hci1394_desc_imm is the basic format used for the "immediate" descriptor 85*7c478bd9Sstevel@tonic-gate * commands: OUTPUT_MORE_IMMEDIATE and OUTPUT_LAST_IMMEDIATE. 86*7c478bd9Sstevel@tonic-gate */ 87*7c478bd9Sstevel@tonic-gate typedef struct hci1394_desc_imm_s { 88*7c478bd9Sstevel@tonic-gate uint32_t hdr; 89*7c478bd9Sstevel@tonic-gate uint32_t data_addr; 90*7c478bd9Sstevel@tonic-gate uint32_t branch; 91*7c478bd9Sstevel@tonic-gate uint32_t status; 92*7c478bd9Sstevel@tonic-gate uint32_t q1; 93*7c478bd9Sstevel@tonic-gate uint32_t q2; 94*7c478bd9Sstevel@tonic-gate uint32_t q3; 95*7c478bd9Sstevel@tonic-gate uint32_t q4; 96*7c478bd9Sstevel@tonic-gate } hci1394_desc_imm_t; 97*7c478bd9Sstevel@tonic-gate 98*7c478bd9Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_desc_imm_s)) 99*7c478bd9Sstevel@tonic-gate 100*7c478bd9Sstevel@tonic-gate /* 101*7c478bd9Sstevel@tonic-gate * hci1394_desc_hdr contains the immediate packet header quadlets 102*7c478bd9Sstevel@tonic-gate * for OUTPUT_MORE_IMMEDIATE and OUTPUT_LAST_IMMEDIATE. A packet header 103*7c478bd9Sstevel@tonic-gate * has up to 4 quadlets of data which are specific to the individual operation 104*7c478bd9Sstevel@tonic-gate * and operation type (i.e. this data would be different between a quadlet read 105*7c478bd9Sstevel@tonic-gate * and quadlet write). 106*7c478bd9Sstevel@tonic-gate */ 107*7c478bd9Sstevel@tonic-gate typedef struct hci1394_desc_hdr_s { 108*7c478bd9Sstevel@tonic-gate uint32_t q1; 109*7c478bd9Sstevel@tonic-gate uint32_t q2; 110*7c478bd9Sstevel@tonic-gate uint32_t q3; 111*7c478bd9Sstevel@tonic-gate uint32_t q4; 112*7c478bd9Sstevel@tonic-gate } hci1394_desc_hdr_t; 113*7c478bd9Sstevel@tonic-gate 114*7c478bd9Sstevel@tonic-gate 115*7c478bd9Sstevel@tonic-gate /* typedefs for each descriptor command */ 116*7c478bd9Sstevel@tonic-gate typedef hci1394_desc_imm_t hci1394_output_more_imm_t; 117*7c478bd9Sstevel@tonic-gate typedef hci1394_desc_t hci1394_output_more_t; 118*7c478bd9Sstevel@tonic-gate typedef hci1394_desc_imm_t hci1394_output_last_imm_t; 119*7c478bd9Sstevel@tonic-gate typedef hci1394_desc_t hci1394_output_last_t; 120*7c478bd9Sstevel@tonic-gate typedef hci1394_desc_t hci1394_input_more_t; 121*7c478bd9Sstevel@tonic-gate typedef hci1394_desc_t hci1394_input_last_t; 122*7c478bd9Sstevel@tonic-gate 123*7c478bd9Sstevel@tonic-gate /* 124*7c478bd9Sstevel@tonic-gate * maximum number of 16-byte components comprising a descriptor block. 125*7c478bd9Sstevel@tonic-gate * Note that "immediate" descriptors take up 32-bytes and therefore are 126*7c478bd9Sstevel@tonic-gate * 2 Z counts. Refer to OHCI 1.00 sections 3.1.2, 7.1.5.1, 8.3.1, 9.2.1, 127*7c478bd9Sstevel@tonic-gate * and table 10-2 for context specific info about Z. 128*7c478bd9Sstevel@tonic-gate */ 129*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_MAX_Z 8 130*7c478bd9Sstevel@tonic-gate 131*7c478bd9Sstevel@tonic-gate 132*7c478bd9Sstevel@tonic-gate /* 133*7c478bd9Sstevel@tonic-gate * There are two sets of defines below. The first set includes 134*7c478bd9Sstevel@tonic-gate * definitions for the descriptor header. Namely hdr, branch, and stat. 135*7c478bd9Sstevel@tonic-gate * The second set includes definitions for the different packet header 136*7c478bd9Sstevel@tonic-gate * formats that have to be placed in the immediate q1-q4 fields 137*7c478bd9Sstevel@tonic-gate * of a descriptor. 138*7c478bd9Sstevel@tonic-gate */ 139*7c478bd9Sstevel@tonic-gate 140*7c478bd9Sstevel@tonic-gate 141*7c478bd9Sstevel@tonic-gate /* General descriptor HDR quadlet defs */ 142*7c478bd9Sstevel@tonic-gate #define DESC_HDR_STAT_ENBL 0x08000000 /* AR, IT & IR only */ 143*7c478bd9Sstevel@tonic-gate #define DESC_HDR_STAT_DSABL 0x00000000 /* AR, IT & IR only */ 144*7c478bd9Sstevel@tonic-gate #define DESC_HDR_PING_ENBL 0x00800000 /* AT only */ 145*7c478bd9Sstevel@tonic-gate #define DESC_HDR_REQCOUNT_MASK 0x0000FFFF /* IR only */ 146*7c478bd9Sstevel@tonic-gate #define DESC_HDR_REQCOUNT_SHIFT 0 147*7c478bd9Sstevel@tonic-gate #define DESC_HDR_STVAL_MASK 0x0000FFFF /* IT STORE only */ 148*7c478bd9Sstevel@tonic-gate #define DESC_HDR_STVAL_SHIFT 0 149*7c478bd9Sstevel@tonic-gate #define DESC_GET_HDR_REQCOUNT(DESCP) \ 150*7c478bd9Sstevel@tonic-gate (((DESCP)->hdr & DESC_HDR_REQCOUNT_MASK) >> DESC_HDR_REQCOUNT_SHIFT) 151*7c478bd9Sstevel@tonic-gate 152*7c478bd9Sstevel@tonic-gate /* CMD_TYPE values */ 153*7c478bd9Sstevel@tonic-gate #define DESC_TY_OUTPUT_MORE 0x00000000 /* AT & IT */ 154*7c478bd9Sstevel@tonic-gate #define DESC_TY_OUTPUT_LAST 0x10000000 /* AT & IT */ 155*7c478bd9Sstevel@tonic-gate #define DESC_TY_INPUT_MORE 0x20000000 /* AR & IR */ 156*7c478bd9Sstevel@tonic-gate #define DESC_TY_INPUT_LAST 0x30000000 /* IR only */ 157*7c478bd9Sstevel@tonic-gate #define DESC_TY_STORE 0x80000000 /* IT only */ 158*7c478bd9Sstevel@tonic-gate 159*7c478bd9Sstevel@tonic-gate /* CMD_KEY values */ 160*7c478bd9Sstevel@tonic-gate #define DESC_KEY_REF 0x00000000 /* reference ptr to data */ 161*7c478bd9Sstevel@tonic-gate #define DESC_KEY_IMMED 0x02000000 /* immediate data */ 162*7c478bd9Sstevel@tonic-gate #define DESC_KEY_STORE 0x06000000 /* store data */ 163*7c478bd9Sstevel@tonic-gate 164*7c478bd9Sstevel@tonic-gate /* CMD_BR and CMD_INT values - two bits */ 165*7c478bd9Sstevel@tonic-gate #define DESC_INTR_DSABL 0x00000000 166*7c478bd9Sstevel@tonic-gate #define DESC_INTR_ENBL 0x00300000 167*7c478bd9Sstevel@tonic-gate #define DESC_BR_DSABL 0x00000000 168*7c478bd9Sstevel@tonic-gate #define DESC_BR_ENBL 0x000C0000 169*7c478bd9Sstevel@tonic-gate #define DESC_W_DSABL 0x00000000 170*7c478bd9Sstevel@tonic-gate #define DESC_W_ENBL 0x00030000 171*7c478bd9Sstevel@tonic-gate 172*7c478bd9Sstevel@tonic-gate /* 173*7c478bd9Sstevel@tonic-gate * Shortcuts for AT Descriptor types. We will always interrupt upon command 174*7c478bd9Sstevel@tonic-gate * completion for AT OL, OLI, and IM. 175*7c478bd9Sstevel@tonic-gate */ 176*7c478bd9Sstevel@tonic-gate #define DESC_AT_OM DESC_TY_OUTPUT_MORE 177*7c478bd9Sstevel@tonic-gate #define DESC_AT_OMI (DESC_TY_OUTPUT_MORE | DESC_KEY_IMMED) 178*7c478bd9Sstevel@tonic-gate #define DESC_AT_OL (DESC_TY_OUTPUT_LAST | DESC_INTR_ENBL | DESC_BR_ENBL) 179*7c478bd9Sstevel@tonic-gate #define DESC_AT_OLI (DESC_AT_OL | DESC_KEY_IMMED) 180*7c478bd9Sstevel@tonic-gate #define DESC_AR_IM (DESC_TY_INPUT_MORE | DESC_HDR_STAT_ENBL | \ 181*7c478bd9Sstevel@tonic-gate DESC_INTR_ENBL | DESC_BR_ENBL) 182*7c478bd9Sstevel@tonic-gate 183*7c478bd9Sstevel@tonic-gate /* 184*7c478bd9Sstevel@tonic-gate * descriptor BRANCH field defs 185*7c478bd9Sstevel@tonic-gate * Branch addresses are 16-byte aligned. the low order 4-bits are 186*7c478bd9Sstevel@tonic-gate * used for the Z value. 187*7c478bd9Sstevel@tonic-gate */ 188*7c478bd9Sstevel@tonic-gate #define DESC_BRANCH_MASK 0xFFFFFFF0 189*7c478bd9Sstevel@tonic-gate #define DESC_Z_MASK 0x0000000F 190*7c478bd9Sstevel@tonic-gate 191*7c478bd9Sstevel@tonic-gate #define HCI1394_SET_BRANCH(DESCP, ADDR, Z) ((DESCP)->branch = 0 | \ 192*7c478bd9Sstevel@tonic-gate ((ADDR) & DESC_BRANCH_MASK) | ((Z) & DESC_Z_MASK)) 193*7c478bd9Sstevel@tonic-gate 194*7c478bd9Sstevel@tonic-gate #define HCI1394_GET_BRANCH_ADDR(DESCP) ((DESCP)->branch & ~DESC_Z_MASK) 195*7c478bd9Sstevel@tonic-gate #define HCI1394_GET_BRANCH_Z(DESCP) ((DESCP)->branch & DESC_Z_MASK) 196*7c478bd9Sstevel@tonic-gate 197*7c478bd9Sstevel@tonic-gate /* 198*7c478bd9Sstevel@tonic-gate * descriptor STATUS field defs. comprised of xfer status and either 199*7c478bd9Sstevel@tonic-gate * a timestamp or a residual count (rescount) 200*7c478bd9Sstevel@tonic-gate */ 201*7c478bd9Sstevel@tonic-gate #define DESC_ST_XFER_STAT_MASK 0xFFFF0000 202*7c478bd9Sstevel@tonic-gate #define DESC_ST_XFER_STAT_SHIFT 16 203*7c478bd9Sstevel@tonic-gate #define DESC_ST_RESCOUNT_MASK 0x0000FFFF /* AR, IR only */ 204*7c478bd9Sstevel@tonic-gate #define DESC_ST_RESCOUNT_SHIFT 0 205*7c478bd9Sstevel@tonic-gate #define DESC_ST_TIMESTAMP_MASK 0x0000FFFF /* AT, IT only */ 206*7c478bd9Sstevel@tonic-gate #define DESC_ST_TIMESTAMP_SHIFT 0 207*7c478bd9Sstevel@tonic-gate 208*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_RESCOUNT_GET(data) ((data) & DESC_ST_RESCOUNT_MASK) 209*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_TIMESTAMP_GET(data) ((data) & DESC_ST_TIMESTAMP_MASK) 210*7c478bd9Sstevel@tonic-gate 211*7c478bd9Sstevel@tonic-gate /* 212*7c478bd9Sstevel@tonic-gate * XFER status fields are the same as the context control fields. 213*7c478bd9Sstevel@tonic-gate * but in the high 16 bits 214*7c478bd9Sstevel@tonic-gate */ 215*7c478bd9Sstevel@tonic-gate #define DESC_XFER_RUN_MASK (OHCI_CC_RUN_MASK << DESC_ST_XFER_STAT_SHIFT) 216*7c478bd9Sstevel@tonic-gate #define DESC_XFER_WAKE_MASK (OHCI_CC_WAKE_MASK << DESC_ST_XFER_STAT_SHIFT) 217*7c478bd9Sstevel@tonic-gate #define DESC_XFER_DEAD_MASK (OHCI_CC_DEAD_MASK << DESC_ST_XFER_STAT_SHIFT) 218*7c478bd9Sstevel@tonic-gate #define DESC_XFER_ACTIVE_MASK (OHCI_CC_ACTIVE_MASK << DESC_ST_XFER_STAT_SHIFT) 219*7c478bd9Sstevel@tonic-gate 220*7c478bd9Sstevel@tonic-gate #define DESC_AT_SPD_MASK 0x7 221*7c478bd9Sstevel@tonic-gate #define DESC_AT_SPD_SHIFT 16 222*7c478bd9Sstevel@tonic-gate #define DESC_AR_SPD_MASK 0x00E00000 223*7c478bd9Sstevel@tonic-gate #define DESC_AR_SPD_SHIFT 21 224*7c478bd9Sstevel@tonic-gate #define DESC_AR_EVT_MASK 0x001F0000 225*7c478bd9Sstevel@tonic-gate #define DESC_AR_EVT_SHIFT 16 226*7c478bd9Sstevel@tonic-gate 227*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_EVT_GET(data) \ 228*7c478bd9Sstevel@tonic-gate (((data) & DESC_AR_EVT_MASK) >> DESC_AR_EVT_SHIFT) 229*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_AR_SPD_GET(data) \ 230*7c478bd9Sstevel@tonic-gate (((data) & DESC_AR_SPD_MASK) >> DESC_AR_SPD_SHIFT) 231*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_AT_SPD_SET(data) \ 232*7c478bd9Sstevel@tonic-gate (((data) & DESC_AT_SPD_MASK) << DESC_AT_SPD_SHIFT) 233*7c478bd9Sstevel@tonic-gate 234*7c478bd9Sstevel@tonic-gate 235*7c478bd9Sstevel@tonic-gate /* 236*7c478bd9Sstevel@tonic-gate * XferStatus events are as follows 237*7c478bd9Sstevel@tonic-gate */ 238*7c478bd9Sstevel@tonic-gate #define DESC_EVT_NO_STATUS 0x00 /* AT, AR, IT, IR */ 239*7c478bd9Sstevel@tonic-gate #define DESC_EVT_LONG_PKT 0x02 /* IR */ 240*7c478bd9Sstevel@tonic-gate #define DESC_EVT_MISSING_ACK 0x03 /* AT */ 241*7c478bd9Sstevel@tonic-gate #define DESC_EVT_UNDERRUN 0x04 /* AT, IT */ 242*7c478bd9Sstevel@tonic-gate #define DESC_EVT_OVERRUN 0x05 /* IR */ 243*7c478bd9Sstevel@tonic-gate #define DESC_EVT_DESC_READ 0x06 /* AT, AR, IT, IR */ 244*7c478bd9Sstevel@tonic-gate #define DESC_EVT_DATA_READ 0x07 /* AT, IT */ 245*7c478bd9Sstevel@tonic-gate #define DESC_EVT_DATA_WRITE 0x08 /* AR, IR */ 246*7c478bd9Sstevel@tonic-gate #define DESC_EVT_BUS_RESET 0x09 /* AR */ 247*7c478bd9Sstevel@tonic-gate #define DESC_EVT_TIMEOUT 0x0A /* AT */ 248*7c478bd9Sstevel@tonic-gate #define DESC_EVT_TCODE_ERR 0x0B /* AT, IT */ 249*7c478bd9Sstevel@tonic-gate 250*7c478bd9Sstevel@tonic-gate #define DESC_ACK_COMPLETE 0x11 /* AT, AR, IT, IR */ 251*7c478bd9Sstevel@tonic-gate #define DESC_ACK_PENDING 0x12 /* AT, AR */ 252*7c478bd9Sstevel@tonic-gate #define DESC_ACK_BUSY_X 0x14 /* AT */ 253*7c478bd9Sstevel@tonic-gate #define DESC_ACK_BUSY_A 0x15 /* AT */ 254*7c478bd9Sstevel@tonic-gate #define DESC_ACK_BUSY_B 0x16 /* AT */ 255*7c478bd9Sstevel@tonic-gate #define DESC_ACK_TARDY 0x1B /* AT */ 256*7c478bd9Sstevel@tonic-gate #define DESC_ACK_DATA_ERR 0x1D /* AT IR */ 257*7c478bd9Sstevel@tonic-gate #define DESC_ACK_TYPE_ERR 0x1E /* AT, AR */ 258*7c478bd9Sstevel@tonic-gate 259*7c478bd9Sstevel@tonic-gate /* 260*7c478bd9Sstevel@tonic-gate * Response packet response codes 261*7c478bd9Sstevel@tonic-gate */ 262*7c478bd9Sstevel@tonic-gate #define DESC_RESP_COMPLETE 0x0 263*7c478bd9Sstevel@tonic-gate #define DESC_RESP_CONFLICT_ERR 0x4 264*7c478bd9Sstevel@tonic-gate #define DESC_RESP_DATA_ERR 0x5 265*7c478bd9Sstevel@tonic-gate #define DESC_RESP_TYPE_ERR 0x6 266*7c478bd9Sstevel@tonic-gate #define DESC_RESP_ADDR_ERR 0x7 267*7c478bd9Sstevel@tonic-gate 268*7c478bd9Sstevel@tonic-gate 269*7c478bd9Sstevel@tonic-gate /* 270*7c478bd9Sstevel@tonic-gate * Context dependent MACROs used to set up the command headers and 271*7c478bd9Sstevel@tonic-gate * Caller provides only the necessary variables. 272*7c478bd9Sstevel@tonic-gate */ 273*7c478bd9Sstevel@tonic-gate 274*7c478bd9Sstevel@tonic-gate /* 275*7c478bd9Sstevel@tonic-gate * Isochronous Transmit Descriptors 276*7c478bd9Sstevel@tonic-gate */ 277*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IT_OMORE(DESCP, REQCOUNT) ((DESCP)->hdr = 0 | \ 278*7c478bd9Sstevel@tonic-gate (DESC_TY_OUTPUT_MORE | DESC_KEY_REF | DESC_BR_DSABL | \ 279*7c478bd9Sstevel@tonic-gate ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT))) 280*7c478bd9Sstevel@tonic-gate 281*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IT_OMORE_IMM(DESCP) ((DESCP)->hdr = 0 | \ 282*7c478bd9Sstevel@tonic-gate (DESC_TY_OUTPUT_MORE | DESC_KEY_IMMED | DESC_BR_DSABL | \ 283*7c478bd9Sstevel@tonic-gate (8 << DESC_HDR_REQCOUNT_SHIFT))) 284*7c478bd9Sstevel@tonic-gate 285*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IT_OLAST(DESCP, STAT, INTR, REQCOUNT) ((DESCP)->hdr = 0 |\ 286*7c478bd9Sstevel@tonic-gate (DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_REF | (INTR) | \ 287*7c478bd9Sstevel@tonic-gate DESC_BR_ENBL | ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT))) 288*7c478bd9Sstevel@tonic-gate 289*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IT_OLAST_IMM(DESCP, STAT, INTR) ((DESCP)->hdr = 0 | \ 290*7c478bd9Sstevel@tonic-gate (DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_IMMED | (INTR) | \ 291*7c478bd9Sstevel@tonic-gate DESC_BR_ENBL | (8 << DESC_HDR_REQCOUNT_SHIFT))) 292*7c478bd9Sstevel@tonic-gate 293*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IT_STORE(DESCP, VAL) ((DESCP)->hdr = 0 | \ 294*7c478bd9Sstevel@tonic-gate (DESC_TY_STORE | DESC_KEY_STORE | ((VAL) << DESC_HDR_STVAL_SHIFT))) 295*7c478bd9Sstevel@tonic-gate 296*7c478bd9Sstevel@tonic-gate /* 297*7c478bd9Sstevel@tonic-gate * Isochronous Receive Descriptors 298*7c478bd9Sstevel@tonic-gate * PPB is Packet-Per-Buffer mode, BF is Buffer-Fill mode 299*7c478bd9Sstevel@tonic-gate */ 300*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IR_PPB_IMORE(DESCP, WAIT, REQCOUNT) (DESCP)->hdr = 0 | \ 301*7c478bd9Sstevel@tonic-gate (DESC_TY_INPUT_MORE | DESC_HDR_STAT_DSABL | DESC_KEY_REF | \ 302*7c478bd9Sstevel@tonic-gate DESC_INTR_DSABL | DESC_BR_DSABL | (WAIT) | \ 303*7c478bd9Sstevel@tonic-gate ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 304*7c478bd9Sstevel@tonic-gate (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 305*7c478bd9Sstevel@tonic-gate DESC_ST_RESCOUNT_MASK); 306*7c478bd9Sstevel@tonic-gate 307*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IR_PPB_ILAST(DESCP, STAT, INTR, WAIT, REQCOUNT) \ 308*7c478bd9Sstevel@tonic-gate (DESCP)->hdr = 0 | (DESC_TY_INPUT_LAST | (STAT) | DESC_KEY_REF | \ 309*7c478bd9Sstevel@tonic-gate (INTR) | DESC_BR_ENBL | (WAIT) | \ 310*7c478bd9Sstevel@tonic-gate ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 311*7c478bd9Sstevel@tonic-gate (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 312*7c478bd9Sstevel@tonic-gate DESC_ST_RESCOUNT_MASK); 313*7c478bd9Sstevel@tonic-gate 314*7c478bd9Sstevel@tonic-gate #define HCI1394_INIT_IR_BF_IMORE(DESCP, INT, WAIT, REQCOUNT) \ 315*7c478bd9Sstevel@tonic-gate (DESCP)->hdr = 0 | (DESC_TY_INPUT_MORE | DESC_HDR_STAT_ENBL | \ 316*7c478bd9Sstevel@tonic-gate DESC_KEY_REF | (INT) | DESC_BR_ENBL | (WAIT) | \ 317*7c478bd9Sstevel@tonic-gate ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 318*7c478bd9Sstevel@tonic-gate (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 319*7c478bd9Sstevel@tonic-gate DESC_ST_RESCOUNT_MASK); 320*7c478bd9Sstevel@tonic-gate 321*7c478bd9Sstevel@tonic-gate /* 322*7c478bd9Sstevel@tonic-gate * Packet Formats 323*7c478bd9Sstevel@tonic-gate * 324*7c478bd9Sstevel@tonic-gate * HCI packet formats typically comprise 2-4 quadlets for transmit 325*7c478bd9Sstevel@tonic-gate * and 3-5 quadlets for receive. Although particular quadlets 326*7c478bd9Sstevel@tonic-gate * may be in different parts of the 1394 header, the fields within 327*7c478bd9Sstevel@tonic-gate * the quadlets remain in a consistent location. 328*7c478bd9Sstevel@tonic-gate */ 329*7c478bd9Sstevel@tonic-gate typedef struct hci1394_basic_packet { 330*7c478bd9Sstevel@tonic-gate uint32_t q1; /* (HCI format) packet header w/tcode */ 331*7c478bd9Sstevel@tonic-gate uint32_t q2; 332*7c478bd9Sstevel@tonic-gate uint32_t q3; 333*7c478bd9Sstevel@tonic-gate uint32_t q4; 334*7c478bd9Sstevel@tonic-gate uint32_t q5; /* xferstatus/rescount for AR/IR */ 335*7c478bd9Sstevel@tonic-gate } hci1394_basic_pkt_t; 336*7c478bd9Sstevel@tonic-gate 337*7c478bd9Sstevel@tonic-gate 338*7c478bd9Sstevel@tonic-gate /* defs for the # of bytes are used in building the immediate descriptors */ 339*7c478bd9Sstevel@tonic-gate /* These are used to set REQCOUNT in the HDR etc... */ 340*7c478bd9Sstevel@tonic-gate #define DESC_FIVE_QUADS 20 341*7c478bd9Sstevel@tonic-gate #define DESC_FOUR_QUADS 16 342*7c478bd9Sstevel@tonic-gate #define DESC_THREE_QUADS 12 343*7c478bd9Sstevel@tonic-gate #define DESC_TWO_QUADS 8 344*7c478bd9Sstevel@tonic-gate #define DESC_ONE_QUAD 4 345*7c478bd9Sstevel@tonic-gate #define DESC_ONE_OCTLET 8 346*7c478bd9Sstevel@tonic-gate #define DESC_TWO_OCTLETS 16 347*7c478bd9Sstevel@tonic-gate 348*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_READQUAD DESC_THREE_QUADS 349*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_WRITEQUAD DESC_FOUR_QUADS 350*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_READBLOCK DESC_FOUR_QUADS 351*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_WRITEBLOCK DESC_FOUR_QUADS 352*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_LOCK DESC_FOUR_QUADS 353*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_PHY DESC_THREE_QUADS 354*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_WRITE_RESP DESC_THREE_QUADS 355*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_READQUAD_RESP DESC_FOUR_QUADS 356*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_READBLOCK_RESP DESC_FOUR_QUADS 357*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_LOCK_RESP DESC_FOUR_QUADS 358*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_STREAM DESC_TWO_QUADS 359*7c478bd9Sstevel@tonic-gate #define DESC_PKT_HDRLEN_AT_ISOCH DESC_PKT_HDRLEN_AT_STREAM 360*7c478bd9Sstevel@tonic-gate 361*7c478bd9Sstevel@tonic-gate /* q1 shortcuts for ASYNC processing */ 362*7c478bd9Sstevel@tonic-gate #define DESC_AT_SRCBUSID 0x00800000 363*7c478bd9Sstevel@tonic-gate #define DESC_ATREQ_Q1_PHY 0x000000E0 364*7c478bd9Sstevel@tonic-gate #define DESC_ATREQ_Q1_QWR 0x00000100 365*7c478bd9Sstevel@tonic-gate #define DESC_ATREQ_Q1_BWR 0x00000110 366*7c478bd9Sstevel@tonic-gate #define DESC_ATREQ_Q1_QRD 0x00000140 367*7c478bd9Sstevel@tonic-gate #define DESC_ATREQ_Q1_BRD 0x00000150 368*7c478bd9Sstevel@tonic-gate #define DESC_ATREQ_Q1_LCK 0x00000190 369*7c478bd9Sstevel@tonic-gate #define DESC_ATRESP_Q1_WR 0x00000120 370*7c478bd9Sstevel@tonic-gate #define DESC_ATRESP_Q1_QRD 0x00000160 371*7c478bd9Sstevel@tonic-gate #define DESC_ATRESP_Q1_BRD 0x00000170 372*7c478bd9Sstevel@tonic-gate #define DESC_ATRESP_Q1_LCK 0x000001B0 373*7c478bd9Sstevel@tonic-gate 374*7c478bd9Sstevel@tonic-gate /* q1 - definitions for the asynch packet first quadlet */ 375*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SRCBUSID_SHIFT 23 376*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SRCBUSID_MASK 0x00800000 377*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SPD_SHIFT 16 /* asynch and isoch */ 378*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SPD_MASK 0x00070000 379*7c478bd9Sstevel@tonic-gate #define DESC_PKT_TLABEL_SHIFT 10 /* asynch and isoch */ 380*7c478bd9Sstevel@tonic-gate #define DESC_PKT_TLABEL_MASK 0x0000FC00 381*7c478bd9Sstevel@tonic-gate #define DESC_PKT_RT_SHIFT 8 382*7c478bd9Sstevel@tonic-gate #define DESC_PKT_RT_MASK 0x00000300 383*7c478bd9Sstevel@tonic-gate #define DESC_PKT_TCODE_SHIFT 4 /* asynch and isoch */ 384*7c478bd9Sstevel@tonic-gate #define DESC_PKT_TCODE_MASK 0x000000F0 385*7c478bd9Sstevel@tonic-gate #define DESC_RT_RETRYX 0x1 386*7c478bd9Sstevel@tonic-gate 387*7c478bd9Sstevel@tonic-gate /* q1 - definitions for the isoch first quadlet (see q1 async above for spd) */ 388*7c478bd9Sstevel@tonic-gate #define DESC_PKT_TAG_SHIFT 14 389*7c478bd9Sstevel@tonic-gate #define DESC_PKT_TAG_MASK 0x0000C000 390*7c478bd9Sstevel@tonic-gate #define DESC_PKT_CHAN_SHIFT 8 391*7c478bd9Sstevel@tonic-gate #define DESC_PKT_CHAN_MASK 0x00003F00 392*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SY_SHIFT 0 393*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SY_MASK 0x0000000F 394*7c478bd9Sstevel@tonic-gate 395*7c478bd9Sstevel@tonic-gate /* q2 - definitions for the asynch second quadlet */ 396*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DESTID_SHIFT 16 /* 1st quadlet for AR */ 397*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DESTID_MASK 0xFFFF0000 398*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SRCID_SHIFT 16 /* asynch recv only */ 399*7c478bd9Sstevel@tonic-gate #define DESC_PKT_SRCID_MASK 0xFFFF0000 400*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DESTOFFHI_SHIFT 0 401*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DESTOFFHI_MASK 0x0000FFFF 402*7c478bd9Sstevel@tonic-gate 403*7c478bd9Sstevel@tonic-gate #define DESC_PKT_BUSID_SHIFT 22 /* in srcid or destid */ 404*7c478bd9Sstevel@tonic-gate #define DESC_PKT_BUSID_MASK 0xFFC00000 /* in srcid or destid */ 405*7c478bd9Sstevel@tonic-gate #define DESC_PKT_NODENUM_SHIFT 16 /* in srcid or destid */ 406*7c478bd9Sstevel@tonic-gate #define DESC_PKT_NODENUM_MASK 0x003F0000 /* in srcid or destid */ 407*7c478bd9Sstevel@tonic-gate #define DESC_PKT_RC_SHIFT 12 /* AT/AR read respnse */ 408*7c478bd9Sstevel@tonic-gate #define DESC_PKT_RC_MASK 0x0000F000 /* AT/AR read respnse */ 409*7c478bd9Sstevel@tonic-gate 410*7c478bd9Sstevel@tonic-gate /* q3 - definitions for the asynch third quadlet */ 411*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DESTOFFLO_SHIFT 0 412*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DESTOFFLO_MASK 0xFFFFFFFF 413*7c478bd9Sstevel@tonic-gate #define DESC_PKT_PHYGEN_SHIFT 16 414*7c478bd9Sstevel@tonic-gate #define DESC_PKT_PHYGEN_MASK 0x00FF0000 415*7c478bd9Sstevel@tonic-gate 416*7c478bd9Sstevel@tonic-gate /* q4 - definitions for the fourth quadlet */ 417*7c478bd9Sstevel@tonic-gate #define DESC_PKT_QDATA_SHIFT 0 /* at_wr_quad, at_rd_resp_quad */ 418*7c478bd9Sstevel@tonic-gate #define DESC_PKT_QDATA_MASK 0xFFFFFFFF 419*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DATALEN_SHIFT 16 /* at_rd_blk, at_wr_blk, isoch (q2), */ 420*7c478bd9Sstevel@tonic-gate #define DESC_PKT_DATALEN_MASK 0xFFFF0000 /* at_rd_resp_blk, at_lock_resp, */ 421*7c478bd9Sstevel@tonic-gate /* ar_rd_blk, ar_wr_blk, ar_lock, */ 422*7c478bd9Sstevel@tonic-gate /* ar_rd_resp, ar_lock_resp */ 423*7c478bd9Sstevel@tonic-gate #define DESC_PKT_EXTTCODE_MASK 0x0000FFFF 424*7c478bd9Sstevel@tonic-gate 425*7c478bd9Sstevel@tonic-gate /* 426*7c478bd9Sstevel@tonic-gate * MACROS for getting and setting HCI packet fields 427*7c478bd9Sstevel@tonic-gate */ 428*7c478bd9Sstevel@tonic-gate 429*7c478bd9Sstevel@tonic-gate /* ASYNCHRONOUS */ 430*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_TCODE_GET(data) \ 431*7c478bd9Sstevel@tonic-gate (((data) & DESC_PKT_TCODE_MASK) >> DESC_PKT_TCODE_SHIFT) 432*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_TLABEL_GET(data) \ 433*7c478bd9Sstevel@tonic-gate (((data) & DESC_PKT_TLABEL_MASK) >> DESC_PKT_TLABEL_SHIFT) 434*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_RCODE_GET(data) \ 435*7c478bd9Sstevel@tonic-gate (((data) & DESC_PKT_RC_MASK) >> DESC_PKT_RC_SHIFT) 436*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_DESTID_GET(data) \ 437*7c478bd9Sstevel@tonic-gate (((data) & DESC_PKT_DESTID_MASK) >> DESC_PKT_DESTID_SHIFT) 438*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_SRCID_GET(data) \ 439*7c478bd9Sstevel@tonic-gate (((data) & DESC_PKT_SRCID_MASK) >> DESC_PKT_SRCID_SHIFT) 440*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_DATALEN_GET(data) \ 441*7c478bd9Sstevel@tonic-gate (((data) & DESC_PKT_DATALEN_MASK) >> DESC_PKT_DATALEN_SHIFT) 442*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_EXTTCODE_GET(data) \ 443*7c478bd9Sstevel@tonic-gate ((data) & DESC_PKT_EXTTCODE_MASK) 444*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_PHYGEN_GET(data) \ 445*7c478bd9Sstevel@tonic-gate (((data) & DESC_PKT_PHYGEN_MASK) >> DESC_PKT_PHYGEN_SHIFT) 446*7c478bd9Sstevel@tonic-gate 447*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_TLABEL_SET(data) \ 448*7c478bd9Sstevel@tonic-gate (((data) << DESC_PKT_TLABEL_SHIFT) & DESC_PKT_TLABEL_MASK) 449*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_RCODE_SET(data) \ 450*7c478bd9Sstevel@tonic-gate (((data) << DESC_PKT_RC_SHIFT) & DESC_PKT_RC_MASK) 451*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_DESTID_SET(data) \ 452*7c478bd9Sstevel@tonic-gate (((data) << DESC_PKT_DESTID_SHIFT) & DESC_PKT_DESTID_MASK) 453*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_DATALEN_SET(data) \ 454*7c478bd9Sstevel@tonic-gate (((data) << DESC_PKT_DATALEN_SHIFT) & DESC_PKT_DATALEN_MASK) 455*7c478bd9Sstevel@tonic-gate #define HCI1394_DESC_EXTTCODE_SET(data) \ 456*7c478bd9Sstevel@tonic-gate ((data) & DESC_PKT_EXTTCODE_MASK) 457*7c478bd9Sstevel@tonic-gate 458*7c478bd9Sstevel@tonic-gate 459*7c478bd9Sstevel@tonic-gate /* ISOCHRONOUS */ 460*7c478bd9Sstevel@tonic-gate /* 461*7c478bd9Sstevel@tonic-gate * note: the GET macros for isoch take the actual quadlet as an arg because 462*7c478bd9Sstevel@tonic-gate * the location of the IR header quadlet varies depending on the mode. 463*7c478bd9Sstevel@tonic-gate * SETs are expected to be done only for isochronous transmit. 464*7c478bd9Sstevel@tonic-gate */ 465*7c478bd9Sstevel@tonic-gate #define HCI1394_GETTAG(Q) (((Q) & DESC_TAG_MASK) >> DESC_TAG_SHIFT) 466*7c478bd9Sstevel@tonic-gate 467*7c478bd9Sstevel@tonic-gate #define HCI1394_SETTAG(PKT, VAL) ((PKT)->q1 = (((PKT)->q1) & \ 468*7c478bd9Sstevel@tonic-gate ~DESC_PKT_TAG_MASK) | (((VAL) << DESC_PKT_TAG_SHIFT) & \ 469*7c478bd9Sstevel@tonic-gate DESC_PKT_TAG_MASK)) 470*7c478bd9Sstevel@tonic-gate 471*7c478bd9Sstevel@tonic-gate #define HCI1394_GETCHAN(Q) (((Q) & PKT_CHAN_MASK) >> \ 472*7c478bd9Sstevel@tonic-gate DESC_PKT_CHAN_SHIFT) 473*7c478bd9Sstevel@tonic-gate 474*7c478bd9Sstevel@tonic-gate #define HCI1394_SETCHAN(PKT, VAL) ((PKT)->q1 = ((PKT)->q1) & \ 475*7c478bd9Sstevel@tonic-gate ~DESC_PKT_CHAN_MASK) | (((VAL) << DESC_PKT_CHAN_SHIFT) & \ 476*7c478bd9Sstevel@tonic-gate DESC_PKT_CHAN_MASK)) 477*7c478bd9Sstevel@tonic-gate 478*7c478bd9Sstevel@tonic-gate #define HCI1394_GETSY(Q) (((Q) & DESC_PKT_SY_MASK) >> \ 479*7c478bd9Sstevel@tonic-gate DESC_PKT_SY_SHIFT) 480*7c478bd9Sstevel@tonic-gate 481*7c478bd9Sstevel@tonic-gate #define HCI1394_SETSY(PKT, VAL) ((PKT)->q1 = ((PKT)->q1) & \ 482*7c478bd9Sstevel@tonic-gate ~DESC_PKT_SY_MASK) | (((VAL) << DESC_PKT_SY_SHIFT) & DESC_PKT_SY_MASK)) 483*7c478bd9Sstevel@tonic-gate 484*7c478bd9Sstevel@tonic-gate #define HCI1394_GET_ILEN(Q) (((Q) & DESC_DATALEN_MASK) >> \ 485*7c478bd9Sstevel@tonic-gate DESC_DATALEN_SHIFT) 486*7c478bd9Sstevel@tonic-gate 487*7c478bd9Sstevel@tonic-gate #define HCI1394_SET_ILEN(PKT, VAL) ((PKT)->q2 = (((PKT)->q1) & \ 488*7c478bd9Sstevel@tonic-gate ~DESC_PKT_DATALEN_MASK) | (((VAL) << DESC_PKT_DATALEN_SHIFT) & \ 489*7c478bd9Sstevel@tonic-gate DESC_PKT_DATALEN_MASK)) 490*7c478bd9Sstevel@tonic-gate 491*7c478bd9Sstevel@tonic-gate #define HCI1394_IT_SET_HDR_Q1(PKT, SPD, TAG, CH, TC, SY) ((PKT)->q1 = 0 | \ 492*7c478bd9Sstevel@tonic-gate (((SPD) << DESC_PKT_SPD_SHIFT) & DESC_PKT_SPD_MASK) | \ 493*7c478bd9Sstevel@tonic-gate (((TAG) << DESC_PKT_TAG_SHIFT) & DESC_PKT_TAG_MASK) | \ 494*7c478bd9Sstevel@tonic-gate (((CH) << DESC_PKT_CH_SHIFT) & DESC_PKT_CH_MASK) | \ 495*7c478bd9Sstevel@tonic-gate (((TC) << DESC_PKT_TCODE_SHIFT) & DESC_PKT_TCODE_MASK) | \ 496*7c478bd9Sstevel@tonic-gate (((SY) << DESC_PKT_SY_SHIFT) & DESC_PKT_SY_MASK)) 497*7c478bd9Sstevel@tonic-gate 498*7c478bd9Sstevel@tonic-gate /* 499*7c478bd9Sstevel@tonic-gate * OpenHCI Packet format sizes (header only) 500*7c478bd9Sstevel@tonic-gate */ 501*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_WRITEQUAD_REQ DESC_FIVE_QUADS 502*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_WRITEBLOCK_REQ DESC_FIVE_QUADS /* add data_len */ 503*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_WRITE_RESP DESC_FOUR_QUADS 504*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_READQUAD_REQ DESC_FOUR_QUADS 505*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_READBLOCK_REQ DESC_FIVE_QUADS 506*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_READQUAD_RESP DESC_FIVE_QUADS 507*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_READ_BLOCK_RESP DESC_FIVE_QUADS /* add data_len */ 508*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_PHY DESC_FOUR_QUADS 509*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_LOCK_REQ DESC_FIVE_QUADS /* add data_len */ 510*7c478bd9Sstevel@tonic-gate #define DESC_SZ_AR_LOCK_RESP DESC_FIVE_QUADS /* add data_len */ 511*7c478bd9Sstevel@tonic-gate 512*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 513*7c478bd9Sstevel@tonic-gate } 514*7c478bd9Sstevel@tonic-gate #endif 515*7c478bd9Sstevel@tonic-gate 516*7c478bd9Sstevel@tonic-gate #endif /* _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H */ 517