xref: /illumos-gate/usr/src/uts/common/os/sunpci.c (revision cb7ea99db394f3bd5f4a6c6bf58c8c52df3508f0)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
54ab75253Smrj  * Common Development and Distribution License (the "License").
64ab75253Smrj  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
214ab75253Smrj 
227c478bd9Sstevel@tonic-gate /*
23*cb7ea99dSJimmy Vetayases  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
247c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
257c478bd9Sstevel@tonic-gate  */
267c478bd9Sstevel@tonic-gate 
277c478bd9Sstevel@tonic-gate #include <sys/types.h>
287c478bd9Sstevel@tonic-gate #include <sys/sunndi.h>
2900d0963fSdilpreet #include <sys/sysmacros.h>
307c478bd9Sstevel@tonic-gate #include <sys/pci.h>
319164eb65Stimh #include <sys/pcie.h>
327c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h>
337c478bd9Sstevel@tonic-gate #include <sys/epm.h>
347c478bd9Sstevel@tonic-gate 
357c478bd9Sstevel@tonic-gate int
367c478bd9Sstevel@tonic-gate pci_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle)
377c478bd9Sstevel@tonic-gate {
387c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
397c478bd9Sstevel@tonic-gate 	ddi_device_acc_attr_t attr;
407c478bd9Sstevel@tonic-gate 
417c478bd9Sstevel@tonic-gate 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
427c478bd9Sstevel@tonic-gate 	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
437c478bd9Sstevel@tonic-gate 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
447c478bd9Sstevel@tonic-gate 
457c478bd9Sstevel@tonic-gate 	/* Check for fault management capabilities */
4600d0963fSdilpreet 	if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) {
4700d0963fSdilpreet 		attr.devacc_attr_version = DDI_DEVICE_ATTR_V1;
487c478bd9Sstevel@tonic-gate 		attr.devacc_attr_access = DDI_FLAGERR_ACC;
4900d0963fSdilpreet 	}
507c478bd9Sstevel@tonic-gate 
517c478bd9Sstevel@tonic-gate 	return (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, handle));
527c478bd9Sstevel@tonic-gate }
537c478bd9Sstevel@tonic-gate 
547c478bd9Sstevel@tonic-gate void
557c478bd9Sstevel@tonic-gate pci_config_teardown(ddi_acc_handle_t *handle)
567c478bd9Sstevel@tonic-gate {
577c478bd9Sstevel@tonic-gate 	ddi_regs_map_free(handle);
587c478bd9Sstevel@tonic-gate }
597c478bd9Sstevel@tonic-gate 
607c478bd9Sstevel@tonic-gate uint8_t
617c478bd9Sstevel@tonic-gate pci_config_get8(ddi_acc_handle_t handle, off_t offset)
627c478bd9Sstevel@tonic-gate {
637c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
647c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
657c478bd9Sstevel@tonic-gate 
667c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
677c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
687c478bd9Sstevel@tonic-gate 	return (ddi_get8(handle, (uint8_t *)cfgaddr));
697c478bd9Sstevel@tonic-gate }
707c478bd9Sstevel@tonic-gate 
717c478bd9Sstevel@tonic-gate uint16_t
727c478bd9Sstevel@tonic-gate pci_config_get16(ddi_acc_handle_t handle, off_t offset)
737c478bd9Sstevel@tonic-gate {
747c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
757c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
767c478bd9Sstevel@tonic-gate 
777c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
787c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
797c478bd9Sstevel@tonic-gate 	return (ddi_get16(handle, (uint16_t *)cfgaddr));
807c478bd9Sstevel@tonic-gate }
817c478bd9Sstevel@tonic-gate 
827c478bd9Sstevel@tonic-gate uint32_t
837c478bd9Sstevel@tonic-gate pci_config_get32(ddi_acc_handle_t handle, off_t offset)
847c478bd9Sstevel@tonic-gate {
857c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
867c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
877c478bd9Sstevel@tonic-gate 
887c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
897c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
907c478bd9Sstevel@tonic-gate 	return (ddi_get32(handle, (uint32_t *)cfgaddr));
917c478bd9Sstevel@tonic-gate }
927c478bd9Sstevel@tonic-gate 
937c478bd9Sstevel@tonic-gate uint64_t
947c478bd9Sstevel@tonic-gate pci_config_get64(ddi_acc_handle_t handle, off_t offset)
957c478bd9Sstevel@tonic-gate {
967c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
977c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
987c478bd9Sstevel@tonic-gate 
997c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1007c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1017c478bd9Sstevel@tonic-gate 	return (ddi_get64(handle, (uint64_t *)cfgaddr));
1027c478bd9Sstevel@tonic-gate }
1037c478bd9Sstevel@tonic-gate 
1047c478bd9Sstevel@tonic-gate void
1057c478bd9Sstevel@tonic-gate pci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value)
1067c478bd9Sstevel@tonic-gate {
1077c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
1087c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
1097c478bd9Sstevel@tonic-gate 
1107c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1117c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1127c478bd9Sstevel@tonic-gate 	ddi_put8(handle, (uint8_t *)cfgaddr, value);
1137c478bd9Sstevel@tonic-gate }
1147c478bd9Sstevel@tonic-gate 
1157c478bd9Sstevel@tonic-gate void
1167c478bd9Sstevel@tonic-gate pci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value)
1177c478bd9Sstevel@tonic-gate {
1187c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
1197c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
1207c478bd9Sstevel@tonic-gate 
1217c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1227c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1237c478bd9Sstevel@tonic-gate 	ddi_put16(handle, (uint16_t *)cfgaddr, value);
1247c478bd9Sstevel@tonic-gate }
1257c478bd9Sstevel@tonic-gate 
1267c478bd9Sstevel@tonic-gate void
1277c478bd9Sstevel@tonic-gate pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value)
1287c478bd9Sstevel@tonic-gate {
1297c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
1307c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
1317c478bd9Sstevel@tonic-gate 
1327c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1337c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1347c478bd9Sstevel@tonic-gate 	ddi_put32(handle, (uint32_t *)cfgaddr, value);
1357c478bd9Sstevel@tonic-gate }
1367c478bd9Sstevel@tonic-gate 
1377c478bd9Sstevel@tonic-gate void
1387c478bd9Sstevel@tonic-gate pci_config_put64(ddi_acc_handle_t handle, off_t offset, uint64_t value)
1394ab75253Smrj {
1404ab75253Smrj 	caddr_t	cfgaddr;
1414ab75253Smrj 	ddi_acc_hdl_t *hp;
1424ab75253Smrj 
1434ab75253Smrj 	hp = impl_acc_hdl_get(handle);
1444ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
1454ab75253Smrj 	ddi_put64(handle, (uint64_t *)cfgaddr, value);
1464ab75253Smrj }
1474ab75253Smrj 
1484ab75253Smrj /*
1494ab75253Smrj  * We need to separate the old interfaces from the new ones and leave them
1504ab75253Smrj  * in here for a while. Previous versions of the OS defined the new interfaces
1514ab75253Smrj  * to the old interfaces. This way we can fix things up so that we can
1524ab75253Smrj  * eventually remove these interfaces.
1534ab75253Smrj  * e.g. A 3rd party module/driver using pci_config_get8 and built against S10
1544ab75253Smrj  * or earlier will actually have a reference to pci_config_getb in the binary.
1554ab75253Smrj  */
1564ab75253Smrj #ifdef _ILP32
1574ab75253Smrj uint8_t
1584ab75253Smrj pci_config_getb(ddi_acc_handle_t handle, off_t offset)
1594ab75253Smrj {
1604ab75253Smrj 	caddr_t	cfgaddr;
1614ab75253Smrj 	ddi_acc_hdl_t *hp;
1624ab75253Smrj 
1634ab75253Smrj 	hp = impl_acc_hdl_get(handle);
1644ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
1654ab75253Smrj 	return (ddi_get8(handle, (uint8_t *)cfgaddr));
1664ab75253Smrj }
1674ab75253Smrj 
1684ab75253Smrj uint16_t
1694ab75253Smrj pci_config_getw(ddi_acc_handle_t handle, off_t offset)
1704ab75253Smrj {
1714ab75253Smrj 	caddr_t	cfgaddr;
1724ab75253Smrj 	ddi_acc_hdl_t *hp;
1734ab75253Smrj 
1744ab75253Smrj 	hp = impl_acc_hdl_get(handle);
1754ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
1764ab75253Smrj 	return (ddi_get16(handle, (uint16_t *)cfgaddr));
1774ab75253Smrj }
1784ab75253Smrj 
1794ab75253Smrj uint32_t
1804ab75253Smrj pci_config_getl(ddi_acc_handle_t handle, off_t offset)
1814ab75253Smrj {
1824ab75253Smrj 	caddr_t	cfgaddr;
1834ab75253Smrj 	ddi_acc_hdl_t *hp;
1844ab75253Smrj 
1854ab75253Smrj 	hp = impl_acc_hdl_get(handle);
1864ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
1874ab75253Smrj 	return (ddi_get32(handle, (uint32_t *)cfgaddr));
1884ab75253Smrj }
1894ab75253Smrj 
1904ab75253Smrj uint64_t
1914ab75253Smrj pci_config_getll(ddi_acc_handle_t handle, off_t offset)
1924ab75253Smrj {
1934ab75253Smrj 	caddr_t	cfgaddr;
1944ab75253Smrj 	ddi_acc_hdl_t *hp;
1954ab75253Smrj 
1964ab75253Smrj 	hp = impl_acc_hdl_get(handle);
1974ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
1984ab75253Smrj 	return (ddi_get64(handle, (uint64_t *)cfgaddr));
1994ab75253Smrj }
2004ab75253Smrj 
2014ab75253Smrj void
2024ab75253Smrj pci_config_putb(ddi_acc_handle_t handle, off_t offset, uint8_t value)
2034ab75253Smrj {
2044ab75253Smrj 	caddr_t	cfgaddr;
2054ab75253Smrj 	ddi_acc_hdl_t *hp;
2064ab75253Smrj 
2074ab75253Smrj 	hp = impl_acc_hdl_get(handle);
2084ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
2094ab75253Smrj 	ddi_put8(handle, (uint8_t *)cfgaddr, value);
2104ab75253Smrj }
2114ab75253Smrj 
2124ab75253Smrj void
2134ab75253Smrj pci_config_putw(ddi_acc_handle_t handle, off_t offset, uint16_t value)
2144ab75253Smrj {
2154ab75253Smrj 	caddr_t	cfgaddr;
2164ab75253Smrj 	ddi_acc_hdl_t *hp;
2174ab75253Smrj 
2184ab75253Smrj 	hp = impl_acc_hdl_get(handle);
2194ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
2204ab75253Smrj 	ddi_put16(handle, (uint16_t *)cfgaddr, value);
2214ab75253Smrj }
2224ab75253Smrj 
2234ab75253Smrj void
2244ab75253Smrj pci_config_putl(ddi_acc_handle_t handle, off_t offset, uint32_t value)
2254ab75253Smrj {
2264ab75253Smrj 	caddr_t	cfgaddr;
2274ab75253Smrj 	ddi_acc_hdl_t *hp;
2284ab75253Smrj 
2294ab75253Smrj 	hp = impl_acc_hdl_get(handle);
2304ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
2314ab75253Smrj 	ddi_put32(handle, (uint32_t *)cfgaddr, value);
2324ab75253Smrj }
2334ab75253Smrj 
2347c478bd9Sstevel@tonic-gate void
2357c478bd9Sstevel@tonic-gate pci_config_putll(ddi_acc_handle_t handle, off_t offset, uint64_t value)
2367c478bd9Sstevel@tonic-gate {
2377c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
2387c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
2397c478bd9Sstevel@tonic-gate 
2407c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
2417c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
2427c478bd9Sstevel@tonic-gate 	ddi_put64(handle, (uint64_t *)cfgaddr, value);
2437c478bd9Sstevel@tonic-gate }
2444ab75253Smrj #endif /* _ILP32 */
2457c478bd9Sstevel@tonic-gate 
2467c478bd9Sstevel@tonic-gate /*ARGSUSED*/
2477c478bd9Sstevel@tonic-gate int
2487c478bd9Sstevel@tonic-gate pci_report_pmcap(dev_info_t *dip, int cap, void *arg)
2497c478bd9Sstevel@tonic-gate {
2507c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
2517c478bd9Sstevel@tonic-gate }
2527c478bd9Sstevel@tonic-gate 
2537c478bd9Sstevel@tonic-gate /*
2547c478bd9Sstevel@tonic-gate  * Note about saving and restoring config space.
2557c478bd9Sstevel@tonic-gate  * PCI devices have only upto 256 bytes of config space while PCI Express
2567c478bd9Sstevel@tonic-gate  * devices can have upto 4k config space. In case of PCI Express device,
2577c478bd9Sstevel@tonic-gate  * we save all 4k config space and restore it even if it doesn't make use
2587c478bd9Sstevel@tonic-gate  * of all 4k. But some devices don't respond to reads to non-existent
2597c478bd9Sstevel@tonic-gate  * registers within the config space. To avoid any panics, we use ddi_peek
2607c478bd9Sstevel@tonic-gate  * to do the reads. A bit mask is used to indicate which words of the
2617c478bd9Sstevel@tonic-gate  * config space are accessible. While restoring the config space, only those
2627c478bd9Sstevel@tonic-gate  * readable words are restored. We do all this in 32 bit size words.
2637c478bd9Sstevel@tonic-gate  */
2647c478bd9Sstevel@tonic-gate #define	INDEX_SHIFT		3
2657c478bd9Sstevel@tonic-gate #define	BITMASK			0x7
2667c478bd9Sstevel@tonic-gate 
2677c478bd9Sstevel@tonic-gate static uint32_t pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2687c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp);
2697c478bd9Sstevel@tonic-gate static void pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2707c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t elements);
2717c478bd9Sstevel@tonic-gate static uint32_t pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2727c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t nwords);
2737c478bd9Sstevel@tonic-gate static uint32_t pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2747c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t notused);
2757c478bd9Sstevel@tonic-gate static uint32_t pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2767c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t notused);
2777c478bd9Sstevel@tonic-gate static uint32_t pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2787c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t notused);
279*cb7ea99dSJimmy Vetayases static uint32_t pci_ht_addrmap_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
280*cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused);
281*cb7ea99dSJimmy Vetayases static uint32_t pci_ht_funcext_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
282*cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused);
2837c478bd9Sstevel@tonic-gate static void pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2847c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t nwords);
2857c478bd9Sstevel@tonic-gate static uint32_t cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2867c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace);
2877c478bd9Sstevel@tonic-gate static void pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2887c478bd9Sstevel@tonic-gate     uint16_t pmcap_offset);
2897c478bd9Sstevel@tonic-gate 
2907c478bd9Sstevel@tonic-gate /*
2917c478bd9Sstevel@tonic-gate  * Table below specifies the number of registers to be saved for each PCI
2927c478bd9Sstevel@tonic-gate  * capability. pci_generic_save saves the number of words specified in the
2937c478bd9Sstevel@tonic-gate  * table. Any special considerations will be taken care by the capability
2947c478bd9Sstevel@tonic-gate  * specific save function e.g. use pci_msi_save to save registers associated
2957c478bd9Sstevel@tonic-gate  * with MSI capability. PCI_UNKNOWN_SIZE indicates that number of registers
2967c478bd9Sstevel@tonic-gate  * to be saved is variable and will be determined by the specific save function.
2977c478bd9Sstevel@tonic-gate  * Currently we save/restore all the registers associated with the capability
2987c478bd9Sstevel@tonic-gate  * including read only registers. Regsiters are saved and restored in 32 bit
2997c478bd9Sstevel@tonic-gate  * size words.
3007c478bd9Sstevel@tonic-gate  */
3017c478bd9Sstevel@tonic-gate static pci_cap_entry_t pci_cap_table[] = {
302*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_PM, 0, 0, PCI_PMCAP_NDWORDS, pci_generic_save},
303*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_AGP, 0, 0, PCI_AGP_NDWORDS, pci_generic_save},
304*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_SLOT_ID, 0, 0, PCI_SLOTID_NDWORDS, pci_generic_save},
305*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_MSI_X, 0, 0, PCI_MSIX_NDWORDS, pci_generic_save},
306*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_MSI, 0, 0, PCI_CAP_SZUNKNOWN, pci_msi_save},
307*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_PCIX, 0, 0, PCI_CAP_SZUNKNOWN, pci_pcix_save},
308*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_PCI_E, 0, 0, PCI_CAP_SZUNKNOWN, pci_pcie_save},
309*cb7ea99dSJimmy Vetayases 
310*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_SLPRI_TYPE, PCI_HTCAP_TYPE_SLHOST_MASK,
311*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_SLPRI_NDWORDS, pci_generic_save},
312*cb7ea99dSJimmy Vetayases 
313*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_HOSTSEC_TYPE, PCI_HTCAP_TYPE_SLHOST_MASK,
314*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_HOSTSEC_NDWORDS, pci_generic_save},
315*cb7ea99dSJimmy Vetayases 
316*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_INTCONF_TYPE, PCI_HTCAP_TYPE_MASK,
317*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_INTCONF_NDWORDS, pci_generic_save},
318*cb7ea99dSJimmy Vetayases 
319*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_REVID_TYPE, PCI_HTCAP_TYPE_MASK,
320*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_REVID_NDWORDS, pci_generic_save},
321*cb7ea99dSJimmy Vetayases 
322*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_UNITID_CLUMP_TYPE, PCI_HTCAP_TYPE_MASK,
323*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_UNITID_CLUMP_NDWORDS, pci_generic_save},
324*cb7ea99dSJimmy Vetayases 
325*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_ECFG_TYPE, PCI_HTCAP_TYPE_MASK,
326*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_ECFG_NDWORDS, pci_generic_save},
327*cb7ea99dSJimmy Vetayases 
328*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_ADDRMAP_TYPE, PCI_HTCAP_TYPE_MASK,
329*cb7ea99dSJimmy Vetayases 		PCI_CAP_SZUNKNOWN, pci_ht_addrmap_save},
330*cb7ea99dSJimmy Vetayases 
331*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_MSIMAP_TYPE, PCI_HTCAP_TYPE_MASK,
332*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_MSIMAP_NDWORDS, pci_generic_save},
333*cb7ea99dSJimmy Vetayases 
334*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_DIRROUTE_TYPE, PCI_HTCAP_TYPE_MASK,
335*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_DIRROUTE_NDWORDS, pci_generic_save},
336*cb7ea99dSJimmy Vetayases 
337*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_VCSET_TYPE, PCI_HTCAP_TYPE_MASK,
338*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_VCSET_NDWORDS, pci_generic_save},
339*cb7ea99dSJimmy Vetayases 
340*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_RETRYMODE_TYPE, PCI_HTCAP_TYPE_MASK,
341*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_RETRYMODE_NDWORDS, pci_generic_save},
342*cb7ea99dSJimmy Vetayases 
343*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_GEN3_TYPE, PCI_HTCAP_TYPE_MASK,
344*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_GEN3_NDWORDS, pci_generic_save},
345*cb7ea99dSJimmy Vetayases 
346*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_FUNCEXT_TYPE, PCI_HTCAP_TYPE_MASK,
347*cb7ea99dSJimmy Vetayases 		PCI_CAP_SZUNKNOWN, pci_ht_funcext_save},
348*cb7ea99dSJimmy Vetayases 
349*cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_PM_TYPE, PCI_HTCAP_TYPE_MASK,
350*cb7ea99dSJimmy Vetayases 		PCI_HTCAP_PM_NDWORDS, pci_generic_save},
351*cb7ea99dSJimmy Vetayases 
3527c478bd9Sstevel@tonic-gate 	/*
3537c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_cPCI_CRC, 0, NULL},
3547c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_VPD, 0, NULL},
3557c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_cPCI_HS, 0, NULL},
3567c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_PCI_HOTPLUG, 0, NULL},
3577c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_AGP_8X, 0, NULL},
3587c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_SECURE_DEV, 0, NULL},
3597c478bd9Sstevel@tonic-gate 	 */
3607c478bd9Sstevel@tonic-gate 	{PCI_CAP_NEXT_PTR_NULL, 0, NULL}
3617c478bd9Sstevel@tonic-gate };
3627c478bd9Sstevel@tonic-gate 
363*cb7ea99dSJimmy Vetayases 
3647c478bd9Sstevel@tonic-gate /*
3657c478bd9Sstevel@tonic-gate  * Save the configuration registers for cdip as a property
3667c478bd9Sstevel@tonic-gate  * so that it persists after detach/uninitchild.
3677c478bd9Sstevel@tonic-gate  */
3687c478bd9Sstevel@tonic-gate int
3697c478bd9Sstevel@tonic-gate pci_save_config_regs(dev_info_t *dip)
3707c478bd9Sstevel@tonic-gate {
3717c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t confhdl;
3727c478bd9Sstevel@tonic-gate 	pci_config_header_state_t *chsp;
3737c478bd9Sstevel@tonic-gate 	pci_cap_save_desc_t *pci_cap_descp;
3747c478bd9Sstevel@tonic-gate 	int ret;
3757c478bd9Sstevel@tonic-gate 	uint32_t i, ncaps, nwords;
3767c478bd9Sstevel@tonic-gate 	uint32_t *regbuf, *p;
3777c478bd9Sstevel@tonic-gate 	uint8_t *maskbuf;
3787c478bd9Sstevel@tonic-gate 	size_t maskbufsz, regbufsz, capbufsz;
379c4e64f25Sgs #ifdef __sparc
3807c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
381c4e64f25Sgs #else
382c4e64f25Sgs 	ddi_device_acc_attr_t attr;
383c4e64f25Sgs 	caddr_t cfgaddr;
384c4e64f25Sgs #endif
3857c478bd9Sstevel@tonic-gate 	off_t offset = 0;
3867c478bd9Sstevel@tonic-gate 	uint8_t cap_ptr, cap_id;
3877c478bd9Sstevel@tonic-gate 	int pcie = 0;
388c602bc24Syf 	uint16_t status;
389c602bc24Syf 
3902df1fe9cSrandyf 	PMD(PMD_SX, ("pci_save_config_regs %s:%d\n", ddi_driver_name(dip),
3912df1fe9cSrandyf 	    ddi_get_instance(dip)))
3927c478bd9Sstevel@tonic-gate 
393c4e64f25Sgs #ifdef __sparc
3947c478bd9Sstevel@tonic-gate 	if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) {
3957c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't get config handle",
3962df1fe9cSrandyf 		    ddi_driver_name(dip), ddi_get_instance(dip));
3977c478bd9Sstevel@tonic-gate 
3987c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
3997c478bd9Sstevel@tonic-gate 	}
400c4e64f25Sgs #else
401c4e64f25Sgs 	/* Set up cautious config access handle */
402c4e64f25Sgs 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V1;
403c4e64f25Sgs 	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
404c4e64f25Sgs 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
405c4e64f25Sgs 	attr.devacc_attr_access = DDI_CAUTIOUS_ACC;
406c4e64f25Sgs 	if (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, &confhdl)
407c4e64f25Sgs 	    != DDI_SUCCESS) {
408c4e64f25Sgs 		cmn_err(CE_WARN, "%s%d can't setup cautious config handle",
409c4e64f25Sgs 		    ddi_driver_name(dip), ddi_get_instance(dip));
410c4e64f25Sgs 
411c4e64f25Sgs 		return (DDI_FAILURE);
412c4e64f25Sgs 	}
413c4e64f25Sgs #endif
414c602bc24Syf 
415c602bc24Syf 	/*
416c602bc24Syf 	 * Determine if it implements capabilities
417c602bc24Syf 	 */
418c602bc24Syf 	status = pci_config_get16(confhdl, PCI_CONF_STAT);
419c602bc24Syf 	if (!(status & 0x10)) {
420c602bc24Syf 		goto no_cap;
421c602bc24Syf 	}
4227c478bd9Sstevel@tonic-gate 	/*
4237c478bd9Sstevel@tonic-gate 	 * Determine if it is a pci express device. If it is, save entire
4247c478bd9Sstevel@tonic-gate 	 * 4k config space treating it as a array of 32 bit integers.
4257c478bd9Sstevel@tonic-gate 	 * If it is not, do it in a usual PCI way.
4267c478bd9Sstevel@tonic-gate 	 */
4277c478bd9Sstevel@tonic-gate 	cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR);
4287c478bd9Sstevel@tonic-gate 	/*
4297c478bd9Sstevel@tonic-gate 	 * Walk the capabilities searching for pci express capability
4307c478bd9Sstevel@tonic-gate 	 */
4317c478bd9Sstevel@tonic-gate 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
4327c478bd9Sstevel@tonic-gate 		cap_id = pci_config_get8(confhdl,
4337c478bd9Sstevel@tonic-gate 		    cap_ptr + PCI_CAP_ID);
4347c478bd9Sstevel@tonic-gate 		if (cap_id == PCI_CAP_ID_PCI_E) {
4357c478bd9Sstevel@tonic-gate 			pcie = 1;
4367c478bd9Sstevel@tonic-gate 			break;
4377c478bd9Sstevel@tonic-gate 		}
4387c478bd9Sstevel@tonic-gate 		cap_ptr = pci_config_get8(confhdl,
4397c478bd9Sstevel@tonic-gate 		    cap_ptr + PCI_CAP_NEXT_PTR);
4407c478bd9Sstevel@tonic-gate 	}
441c602bc24Syf no_cap:
4427c478bd9Sstevel@tonic-gate 	if (pcie) {
4437c478bd9Sstevel@tonic-gate 		/* PCI express device. Can have data in all 4k space */
4447c478bd9Sstevel@tonic-gate 		regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE,
4452df1fe9cSrandyf 		    KM_SLEEP);
4467c478bd9Sstevel@tonic-gate 		p = regbuf;
4477c478bd9Sstevel@tonic-gate 		/*
4487c478bd9Sstevel@tonic-gate 		 * Allocate space for mask.
4497c478bd9Sstevel@tonic-gate 		 * mask size is 128 bytes (4096 / 4 / 8 )
4507c478bd9Sstevel@tonic-gate 		 */
4517c478bd9Sstevel@tonic-gate 		maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >>
4527c478bd9Sstevel@tonic-gate 		    INDEX_SHIFT);
4537c478bd9Sstevel@tonic-gate 		maskbuf = (uint8_t *)kmem_zalloc(maskbufsz, KM_SLEEP);
454c4e64f25Sgs #ifdef __sparc
4557c478bd9Sstevel@tonic-gate 		hp = impl_acc_hdl_get(confhdl);
456c4e64f25Sgs #endif
4577c478bd9Sstevel@tonic-gate 		for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) {
458c4e64f25Sgs #ifdef __sparc
459c4e64f25Sgs 			ret = ddi_peek32(dip, (int32_t *)(hp->ah_addr + offset),
460c4e64f25Sgs 			    (int32_t *)p);
461abee7076Sgs 			if (ret == DDI_SUCCESS) {
462c4e64f25Sgs #else
463c4e64f25Sgs 			/*
464c4e64f25Sgs 			 * ddi_peek doesn't work on x86, so we use cautious pci
465c4e64f25Sgs 			 * config access instead.
466c4e64f25Sgs 			 */
467c4e64f25Sgs 			*p = pci_config_get32(confhdl, offset);
468c4e64f25Sgs 			if (*p != -1) {
469c4e64f25Sgs #endif
4707c478bd9Sstevel@tonic-gate 				/* it is readable register. set the bit */
4717c478bd9Sstevel@tonic-gate 				maskbuf[i >> INDEX_SHIFT] |=
4727c478bd9Sstevel@tonic-gate 				    (uint8_t)(1 << (i & BITMASK));
4737c478bd9Sstevel@tonic-gate 			}
4747c478bd9Sstevel@tonic-gate 			p++;
4757c478bd9Sstevel@tonic-gate 			offset += sizeof (uint32_t);
4767c478bd9Sstevel@tonic-gate 		}
4777c478bd9Sstevel@tonic-gate 
4787c478bd9Sstevel@tonic-gate 		if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
4797c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_MASK, (uchar_t *)maskbuf,
4807c478bd9Sstevel@tonic-gate 		    maskbufsz)) != DDI_PROP_SUCCESS) {
4817c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "couldn't create %s property while"
4827c478bd9Sstevel@tonic-gate 			    "saving config space for %s@%d\n",
4837c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_MASK, ddi_driver_name(dip),
4847c478bd9Sstevel@tonic-gate 			    ddi_get_instance(dip));
4857c478bd9Sstevel@tonic-gate 		} else if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE,
4867c478bd9Sstevel@tonic-gate 		    dip, SAVED_CONFIG_REGS, (uchar_t *)regbuf,
4877c478bd9Sstevel@tonic-gate 		    (size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) {
4887c478bd9Sstevel@tonic-gate 			(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
4897c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_MASK);
4907c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s%d can't update prop %s",
4917c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
4927c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS);
4937c478bd9Sstevel@tonic-gate 		}
4947c478bd9Sstevel@tonic-gate 
4957c478bd9Sstevel@tonic-gate 		kmem_free(maskbuf, (size_t)maskbufsz);
4967c478bd9Sstevel@tonic-gate 		kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE);
4977c478bd9Sstevel@tonic-gate 	} else {
4987c478bd9Sstevel@tonic-gate 		regbuf = (uint32_t *)kmem_zalloc((size_t)PCI_CONF_HDR_SIZE,
4992df1fe9cSrandyf 		    KM_SLEEP);
5007c478bd9Sstevel@tonic-gate 		chsp = (pci_config_header_state_t *)regbuf;
5017c478bd9Sstevel@tonic-gate 
5027c478bd9Sstevel@tonic-gate 		chsp->chs_command = pci_config_get16(confhdl, PCI_CONF_COMM);
5037c478bd9Sstevel@tonic-gate 		chsp->chs_header_type =	pci_config_get8(confhdl,
5042df1fe9cSrandyf 		    PCI_CONF_HEADER);
5057c478bd9Sstevel@tonic-gate 		if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) ==
5067c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE)
5077c478bd9Sstevel@tonic-gate 			chsp->chs_bridge_control =
5087c478bd9Sstevel@tonic-gate 			    pci_config_get16(confhdl, PCI_BCNF_BCNTRL);
5097c478bd9Sstevel@tonic-gate 		chsp->chs_cache_line_size = pci_config_get8(confhdl,
5107c478bd9Sstevel@tonic-gate 		    PCI_CONF_CACHE_LINESZ);
5117c478bd9Sstevel@tonic-gate 		chsp->chs_latency_timer = pci_config_get8(confhdl,
5127c478bd9Sstevel@tonic-gate 		    PCI_CONF_LATENCY_TIMER);
5137c478bd9Sstevel@tonic-gate 		if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) ==
5147c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE) {
5157c478bd9Sstevel@tonic-gate 			chsp->chs_sec_latency_timer =
5167c478bd9Sstevel@tonic-gate 			    pci_config_get8(confhdl, PCI_BCNF_LATENCY_TIMER);
5177c478bd9Sstevel@tonic-gate 		}
5187c478bd9Sstevel@tonic-gate 
5197c478bd9Sstevel@tonic-gate 		chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);
5207c478bd9Sstevel@tonic-gate 		chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
5217c478bd9Sstevel@tonic-gate 		chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);
5227c478bd9Sstevel@tonic-gate 		chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);
5237c478bd9Sstevel@tonic-gate 		chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4);
5247c478bd9Sstevel@tonic-gate 		chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);
5257c478bd9Sstevel@tonic-gate 
5267c478bd9Sstevel@tonic-gate 		/*
5277c478bd9Sstevel@tonic-gate 		 * Allocate maximum space required for capability descriptions.
5287c478bd9Sstevel@tonic-gate 		 * The maximum number of capabilties saved is the number of
5297c478bd9Sstevel@tonic-gate 		 * capabilities listed in the pci_cap_table.
5307c478bd9Sstevel@tonic-gate 		 */
5317c478bd9Sstevel@tonic-gate 		ncaps = (sizeof (pci_cap_table) / sizeof (pci_cap_entry_t));
5327c478bd9Sstevel@tonic-gate 		capbufsz = ncaps * sizeof (pci_cap_save_desc_t);
5337c478bd9Sstevel@tonic-gate 		pci_cap_descp = (pci_cap_save_desc_t *)kmem_zalloc(
5347c478bd9Sstevel@tonic-gate 		    capbufsz, KM_SLEEP);
5357c478bd9Sstevel@tonic-gate 		p = (uint32_t *)((caddr_t)regbuf +
5367c478bd9Sstevel@tonic-gate 		    sizeof (pci_config_header_state_t));
5377c478bd9Sstevel@tonic-gate 		nwords = pci_save_caps(confhdl, p, pci_cap_descp, &ncaps);
5387c478bd9Sstevel@tonic-gate 		regbufsz = sizeof (pci_config_header_state_t) +
5397c478bd9Sstevel@tonic-gate 		    nwords * sizeof (uint32_t);
5407c478bd9Sstevel@tonic-gate 
5417c478bd9Sstevel@tonic-gate 		if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
5427c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS, (uchar_t *)regbuf, regbufsz)) !=
5437c478bd9Sstevel@tonic-gate 		    DDI_PROP_SUCCESS) {
5447c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s%d can't update prop %s",
5457c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
5467c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS);
5477c478bd9Sstevel@tonic-gate 		} else if (ncaps) {
5487c478bd9Sstevel@tonic-gate 			ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
5497c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_CAPINFO, (uchar_t *)pci_cap_descp,
5507c478bd9Sstevel@tonic-gate 			    ncaps * sizeof (pci_cap_save_desc_t));
5517c478bd9Sstevel@tonic-gate 			if (ret != DDI_PROP_SUCCESS)
5527c478bd9Sstevel@tonic-gate 				(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
5537c478bd9Sstevel@tonic-gate 				    SAVED_CONFIG_REGS);
5547c478bd9Sstevel@tonic-gate 		}
5557c478bd9Sstevel@tonic-gate 		kmem_free(regbuf, (size_t)PCI_CONF_HDR_SIZE);
5567c478bd9Sstevel@tonic-gate 		kmem_free(pci_cap_descp, capbufsz);
5577c478bd9Sstevel@tonic-gate 	}
5587c478bd9Sstevel@tonic-gate 	pci_config_teardown(&confhdl);
5597c478bd9Sstevel@tonic-gate 
5607c478bd9Sstevel@tonic-gate 	if (ret != DDI_PROP_SUCCESS)
5617c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
5627c478bd9Sstevel@tonic-gate 
5637c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
5647c478bd9Sstevel@tonic-gate }
5657c478bd9Sstevel@tonic-gate 
5667c478bd9Sstevel@tonic-gate /*
5677c478bd9Sstevel@tonic-gate  * Saves registers associated with PCI capabilities.
5687c478bd9Sstevel@tonic-gate  * Returns number of 32 bit words saved.
5697c478bd9Sstevel@tonic-gate  * Number of capabilities saved is returned in ncapsp.
5707c478bd9Sstevel@tonic-gate  */
5717c478bd9Sstevel@tonic-gate static uint32_t
5727c478bd9Sstevel@tonic-gate pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
5737c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp)
5747c478bd9Sstevel@tonic-gate {
5757c478bd9Sstevel@tonic-gate 	return (cap_walk_and_save(confhdl, regbuf, cap_descp, ncapsp, 0));
5767c478bd9Sstevel@tonic-gate }
5777c478bd9Sstevel@tonic-gate 
5787c478bd9Sstevel@tonic-gate static uint32_t
5797c478bd9Sstevel@tonic-gate cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf,
5807c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace)
5817c478bd9Sstevel@tonic-gate {
5827c478bd9Sstevel@tonic-gate 	pci_cap_entry_t *pci_cap_entp;
583c602bc24Syf 	uint16_t cap_id, offset, status;
5847c478bd9Sstevel@tonic-gate 	uint32_t words_saved = 0, nwords = 0;
5857c478bd9Sstevel@tonic-gate 	uint16_t cap_ptr = PCI_CAP_NEXT_PTR_NULL;
586*cb7ea99dSJimmy Vetayases 	uint16_t cap_reg;
5877c478bd9Sstevel@tonic-gate 
5887c478bd9Sstevel@tonic-gate 	*ncapsp = 0;
589c602bc24Syf 
590c602bc24Syf 	/*
591c602bc24Syf 	 * Determine if it implements capabilities
592c602bc24Syf 	 */
593c602bc24Syf 	status = pci_config_get16(confhdl, PCI_CONF_STAT);
594c602bc24Syf 	if (!(status & 0x10)) {
595c602bc24Syf 		return (words_saved);
596c602bc24Syf 	}
597c602bc24Syf 
5987c478bd9Sstevel@tonic-gate 	if (!xspace)
5997c478bd9Sstevel@tonic-gate 		cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR);
6007c478bd9Sstevel@tonic-gate 	/*
6017c478bd9Sstevel@tonic-gate 	 * Walk the capabilities
6027c478bd9Sstevel@tonic-gate 	 */
6037c478bd9Sstevel@tonic-gate 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
6047c478bd9Sstevel@tonic-gate 		cap_id = CAP_ID(confhdl, cap_ptr, xspace);
605*cb7ea99dSJimmy Vetayases 
6067c478bd9Sstevel@tonic-gate 		/* Search for this cap id in our table */
607*cb7ea99dSJimmy Vetayases 		if (!xspace) {
6087c478bd9Sstevel@tonic-gate 			pci_cap_entp = pci_cap_table;
609*cb7ea99dSJimmy Vetayases 			cap_reg = pci_config_get16(confhdl,
610*cb7ea99dSJimmy Vetayases 			    cap_ptr + PCI_CAP_ID_REGS_OFF);
611*cb7ea99dSJimmy Vetayases 		}
612*cb7ea99dSJimmy Vetayases 
613*cb7ea99dSJimmy Vetayases 		while (pci_cap_entp->cap_id != PCI_CAP_NEXT_PTR_NULL) {
614*cb7ea99dSJimmy Vetayases 			if (pci_cap_entp->cap_id == cap_id &&
615*cb7ea99dSJimmy Vetayases 			    (cap_reg & pci_cap_entp->cap_mask) ==
616*cb7ea99dSJimmy Vetayases 			    pci_cap_entp->cap_reg)
617*cb7ea99dSJimmy Vetayases 				break;
618*cb7ea99dSJimmy Vetayases 
6197c478bd9Sstevel@tonic-gate 			pci_cap_entp++;
620*cb7ea99dSJimmy Vetayases 		}
6217c478bd9Sstevel@tonic-gate 
6227c478bd9Sstevel@tonic-gate 		offset = cap_ptr;
6237c478bd9Sstevel@tonic-gate 		cap_ptr = NEXT_CAP(confhdl, cap_ptr, xspace);
6247c478bd9Sstevel@tonic-gate 		/*
6257c478bd9Sstevel@tonic-gate 		 * If this cap id is not found in the table, there is nothing
6267c478bd9Sstevel@tonic-gate 		 * to save.
6277c478bd9Sstevel@tonic-gate 		 */
6287c478bd9Sstevel@tonic-gate 		if (pci_cap_entp->cap_id == PCI_CAP_NEXT_PTR_NULL)
6297c478bd9Sstevel@tonic-gate 			continue;
6307c478bd9Sstevel@tonic-gate 		if (pci_cap_entp->cap_save_func) {
6317c478bd9Sstevel@tonic-gate 			if ((nwords = pci_cap_entp->cap_save_func(confhdl,
6327c478bd9Sstevel@tonic-gate 			    offset, regbuf, pci_cap_entp->cap_ndwords))) {
6337c478bd9Sstevel@tonic-gate 				cap_descp->cap_nregs = nwords;
6347c478bd9Sstevel@tonic-gate 				cap_descp->cap_offset = offset;
6357c478bd9Sstevel@tonic-gate 				cap_descp->cap_id = cap_id;
6367c478bd9Sstevel@tonic-gate 				regbuf += nwords;
6377c478bd9Sstevel@tonic-gate 				cap_descp++;
6387c478bd9Sstevel@tonic-gate 				words_saved += nwords;
6397c478bd9Sstevel@tonic-gate 				(*ncapsp)++;
6407c478bd9Sstevel@tonic-gate 			}
6417c478bd9Sstevel@tonic-gate 		}
6427c478bd9Sstevel@tonic-gate 
6437c478bd9Sstevel@tonic-gate 	}
6447c478bd9Sstevel@tonic-gate 	return (words_saved);
6457c478bd9Sstevel@tonic-gate }
6467c478bd9Sstevel@tonic-gate 
6477c478bd9Sstevel@tonic-gate static void
6487c478bd9Sstevel@tonic-gate pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
6497c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t nwords)
6507c478bd9Sstevel@tonic-gate {
6517c478bd9Sstevel@tonic-gate 	int i;
6527c478bd9Sstevel@tonic-gate 
6537c478bd9Sstevel@tonic-gate 	for (i = 0; i < nwords; i++) {
6547c478bd9Sstevel@tonic-gate 		*regbuf = pci_config_get32(confhdl, cap_ptr);
6557c478bd9Sstevel@tonic-gate 		regbuf++;
6567c478bd9Sstevel@tonic-gate 		cap_ptr += 4;
6577c478bd9Sstevel@tonic-gate 	}
6587c478bd9Sstevel@tonic-gate }
6597c478bd9Sstevel@tonic-gate 
6607c478bd9Sstevel@tonic-gate static uint32_t
6617c478bd9Sstevel@tonic-gate pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
6627c478bd9Sstevel@tonic-gate     uint32_t nwords)
6637c478bd9Sstevel@tonic-gate {
6647c478bd9Sstevel@tonic-gate 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
6657c478bd9Sstevel@tonic-gate 	return (nwords);
6667c478bd9Sstevel@tonic-gate }
6677c478bd9Sstevel@tonic-gate 
6687c478bd9Sstevel@tonic-gate /*ARGSUSED*/
6697c478bd9Sstevel@tonic-gate static uint32_t
6707c478bd9Sstevel@tonic-gate pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
6717c478bd9Sstevel@tonic-gate     uint32_t notused)
6727c478bd9Sstevel@tonic-gate {
6737c478bd9Sstevel@tonic-gate 	uint32_t nwords = PCI_MSI_MIN_WORDS;
6747c478bd9Sstevel@tonic-gate 	uint16_t msi_ctrl;
6757c478bd9Sstevel@tonic-gate 
6767c478bd9Sstevel@tonic-gate 	/* Figure out how many registers to be saved */
6777c478bd9Sstevel@tonic-gate 	msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL);
6787c478bd9Sstevel@tonic-gate 	/* If 64 bit address capable add one word */
6797c478bd9Sstevel@tonic-gate 	if (msi_ctrl & PCI_MSI_64BIT_MASK)
6807c478bd9Sstevel@tonic-gate 		nwords++;
6817c478bd9Sstevel@tonic-gate 	/* If per vector masking capable, add two more words */
6827c478bd9Sstevel@tonic-gate 	if (msi_ctrl & PCI_MSI_PVM_MASK)
6837c478bd9Sstevel@tonic-gate 		nwords += 2;
6847c478bd9Sstevel@tonic-gate 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
6857c478bd9Sstevel@tonic-gate 
6867c478bd9Sstevel@tonic-gate 	return (nwords);
6877c478bd9Sstevel@tonic-gate }
6887c478bd9Sstevel@tonic-gate 
6897c478bd9Sstevel@tonic-gate /*ARGSUSED*/
6907c478bd9Sstevel@tonic-gate static uint32_t
6917c478bd9Sstevel@tonic-gate pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
6927c478bd9Sstevel@tonic-gate     uint32_t notused)
6937c478bd9Sstevel@tonic-gate {
6947c478bd9Sstevel@tonic-gate 	uint32_t nwords = PCI_PCIX_MIN_WORDS;
6957c478bd9Sstevel@tonic-gate 	uint16_t pcix_command;
6967c478bd9Sstevel@tonic-gate 
6977c478bd9Sstevel@tonic-gate 	/* Figure out how many registers to be saved */
6987c478bd9Sstevel@tonic-gate 	pcix_command = pci_config_get16(confhdl, cap_ptr + PCI_PCIX_COMMAND);
6997c478bd9Sstevel@tonic-gate 	/* If it is version 1 or version 2, add 4 words */
7007c478bd9Sstevel@tonic-gate 	if (((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_1) ||
7017c478bd9Sstevel@tonic-gate 	    ((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2))
7027c478bd9Sstevel@tonic-gate 		nwords += 4;
7037c478bd9Sstevel@tonic-gate 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
7047c478bd9Sstevel@tonic-gate 
7057c478bd9Sstevel@tonic-gate 	return (nwords);
7067c478bd9Sstevel@tonic-gate }
7077c478bd9Sstevel@tonic-gate 
7087c478bd9Sstevel@tonic-gate /*ARGSUSED*/
7097c478bd9Sstevel@tonic-gate static uint32_t
7107c478bd9Sstevel@tonic-gate pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
7117c478bd9Sstevel@tonic-gate     uint32_t notused)
7127c478bd9Sstevel@tonic-gate {
7137c478bd9Sstevel@tonic-gate 	return (0);
7147c478bd9Sstevel@tonic-gate }
7157c478bd9Sstevel@tonic-gate 
716*cb7ea99dSJimmy Vetayases /*ARGSUSED*/
717*cb7ea99dSJimmy Vetayases static uint32_t
718*cb7ea99dSJimmy Vetayases pci_ht_addrmap_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
719*cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused)
720*cb7ea99dSJimmy Vetayases {
721*cb7ea99dSJimmy Vetayases 	uint32_t nwords = 0;
722*cb7ea99dSJimmy Vetayases 	uint16_t reg;
723*cb7ea99dSJimmy Vetayases 
724*cb7ea99dSJimmy Vetayases 	reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
725*cb7ea99dSJimmy Vetayases 
726*cb7ea99dSJimmy Vetayases 	switch ((reg & PCI_HTCAP_ADDRMAP_MAPTYPE_MASK) >>
727*cb7ea99dSJimmy Vetayases 	    PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT) {
728*cb7ea99dSJimmy Vetayases 	case PCI_HTCAP_ADDRMAP_40BIT_ID:
729*cb7ea99dSJimmy Vetayases 		/* HT3.1 spec, ch 7.7, 40-bit dma */
730*cb7ea99dSJimmy Vetayases 		nwords = 3 + ((reg & PCI_HTCAP_ADDRMAP_NUMMAP_MASK) * 2);
731*cb7ea99dSJimmy Vetayases 		break;
732*cb7ea99dSJimmy Vetayases 	case PCI_HTCAP_ADDRMAP_64BIT_ID:
733*cb7ea99dSJimmy Vetayases 		/* HT3.1 spec, ch 7.8, 64-bit dma */
734*cb7ea99dSJimmy Vetayases 		nwords = 4;
735*cb7ea99dSJimmy Vetayases 		break;
736*cb7ea99dSJimmy Vetayases 	default:
737*cb7ea99dSJimmy Vetayases 		nwords = 0;
738*cb7ea99dSJimmy Vetayases 	}
739*cb7ea99dSJimmy Vetayases 
740*cb7ea99dSJimmy Vetayases 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
741*cb7ea99dSJimmy Vetayases 	return (nwords);
742*cb7ea99dSJimmy Vetayases }
743*cb7ea99dSJimmy Vetayases 
744*cb7ea99dSJimmy Vetayases /*ARGSUSED*/
745*cb7ea99dSJimmy Vetayases static uint32_t
746*cb7ea99dSJimmy Vetayases pci_ht_funcext_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
747*cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused)
748*cb7ea99dSJimmy Vetayases {
749*cb7ea99dSJimmy Vetayases 	uint32_t nwords;
750*cb7ea99dSJimmy Vetayases 	uint16_t reg;
751*cb7ea99dSJimmy Vetayases 
752*cb7ea99dSJimmy Vetayases 	reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
753*cb7ea99dSJimmy Vetayases 
754*cb7ea99dSJimmy Vetayases 	/* HT3.1 spec, ch 7.17 */
755*cb7ea99dSJimmy Vetayases 	nwords = 1 + (reg & PCI_HTCAP_FUNCEXT_LEN_MASK);
756*cb7ea99dSJimmy Vetayases 
757*cb7ea99dSJimmy Vetayases 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
758*cb7ea99dSJimmy Vetayases 	return (nwords);
759*cb7ea99dSJimmy Vetayases }
760*cb7ea99dSJimmy Vetayases 
7617c478bd9Sstevel@tonic-gate static void
7627c478bd9Sstevel@tonic-gate pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf,
7637c478bd9Sstevel@tonic-gate     uint16_t pmcap_offset)
7647c478bd9Sstevel@tonic-gate {
7657c478bd9Sstevel@tonic-gate 	uint16_t pmcsr;
7667c478bd9Sstevel@tonic-gate 	uint16_t pmcsr_offset = pmcap_offset + PCI_PMCSR;
7677c478bd9Sstevel@tonic-gate 	uint32_t *saved_pmcsrp = (uint32_t *)((caddr_t)regbuf + PCI_PMCSR);
7687c478bd9Sstevel@tonic-gate 
7697c478bd9Sstevel@tonic-gate 	/*
7707c478bd9Sstevel@tonic-gate 	 * Copy the power state bits from the PMCSR to our saved copy.
7717c478bd9Sstevel@tonic-gate 	 * This is to make sure that we don't change the D state when
7727c478bd9Sstevel@tonic-gate 	 * we restore config space of the device.
7737c478bd9Sstevel@tonic-gate 	 */
7747c478bd9Sstevel@tonic-gate 	pmcsr = pci_config_get16(confhdl, pmcsr_offset);
7757c478bd9Sstevel@tonic-gate 	(*saved_pmcsrp) &= ~PCI_PMCSR_STATE_MASK;
7767c478bd9Sstevel@tonic-gate 	(*saved_pmcsrp) |= (pmcsr & PCI_PMCSR_STATE_MASK);
7777c478bd9Sstevel@tonic-gate }
7787c478bd9Sstevel@tonic-gate 
7797c478bd9Sstevel@tonic-gate static void
7807c478bd9Sstevel@tonic-gate pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
7817c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t elements)
7827c478bd9Sstevel@tonic-gate {
7837c478bd9Sstevel@tonic-gate 	int i, j;
7847c478bd9Sstevel@tonic-gate 	uint16_t offset;
7857c478bd9Sstevel@tonic-gate 
7867c478bd9Sstevel@tonic-gate 	for (i = 0; i < (elements / sizeof (pci_cap_save_desc_t)); i++) {
7877c478bd9Sstevel@tonic-gate 		offset = cap_descp->cap_offset;
7887c478bd9Sstevel@tonic-gate 		if (cap_descp->cap_id == PCI_CAP_ID_PM)
7897c478bd9Sstevel@tonic-gate 			pci_pmcap_check(confhdl, regbuf, offset);
7907c478bd9Sstevel@tonic-gate 		for (j = 0; j < cap_descp->cap_nregs; j++) {
7917c478bd9Sstevel@tonic-gate 			pci_config_put32(confhdl, offset, *regbuf);
7927c478bd9Sstevel@tonic-gate 			regbuf++;
7937c478bd9Sstevel@tonic-gate 			offset += 4;
7947c478bd9Sstevel@tonic-gate 		}
7957c478bd9Sstevel@tonic-gate 		cap_descp++;
7967c478bd9Sstevel@tonic-gate 	}
7977c478bd9Sstevel@tonic-gate }
7987c478bd9Sstevel@tonic-gate 
7997c478bd9Sstevel@tonic-gate /*
8007c478bd9Sstevel@tonic-gate  * Restore config_regs from a single devinfo node.
8017c478bd9Sstevel@tonic-gate  */
8027c478bd9Sstevel@tonic-gate int
8037c478bd9Sstevel@tonic-gate pci_restore_config_regs(dev_info_t *dip)
8047c478bd9Sstevel@tonic-gate {
8057c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t confhdl;
8067c478bd9Sstevel@tonic-gate 	pci_config_header_state_t *chs_p;
8077c478bd9Sstevel@tonic-gate 	pci_cap_save_desc_t *cap_descp;
8087c478bd9Sstevel@tonic-gate 	uint32_t elements, i;
8097c478bd9Sstevel@tonic-gate 	uint8_t *maskbuf;
8107c478bd9Sstevel@tonic-gate 	uint32_t *regbuf, *p;
8117c478bd9Sstevel@tonic-gate 	off_t offset = 0;
8127c478bd9Sstevel@tonic-gate 
8137c478bd9Sstevel@tonic-gate 	if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) {
8147c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't get config handle",
8157c478bd9Sstevel@tonic-gate 		    ddi_driver_name(dip), ddi_get_instance(dip));
8167c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
8177c478bd9Sstevel@tonic-gate 	}
8187c478bd9Sstevel@tonic-gate 
8197c478bd9Sstevel@tonic-gate 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8207c478bd9Sstevel@tonic-gate 	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS_MASK,
8217c478bd9Sstevel@tonic-gate 	    (uchar_t **)&maskbuf, &elements) == DDI_PROP_SUCCESS) {
8227c478bd9Sstevel@tonic-gate 
8237c478bd9Sstevel@tonic-gate 		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8247c478bd9Sstevel@tonic-gate 		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS,
8257c478bd9Sstevel@tonic-gate 		    (uchar_t **)&regbuf, &elements) != DDI_PROP_SUCCESS) {
8267c478bd9Sstevel@tonic-gate 			goto restoreconfig_err;
8277c478bd9Sstevel@tonic-gate 		}
8287c478bd9Sstevel@tonic-gate 		ASSERT(elements == PCIE_CONF_HDR_SIZE);
8297c478bd9Sstevel@tonic-gate 		/* pcie device and has 4k config space saved */
8307c478bd9Sstevel@tonic-gate 		p = regbuf;
8317c478bd9Sstevel@tonic-gate 		for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) {
8327c478bd9Sstevel@tonic-gate 			/* If the word is readable then restore it */
8337c478bd9Sstevel@tonic-gate 			if (maskbuf[i >> INDEX_SHIFT] &
8347c478bd9Sstevel@tonic-gate 			    (uint8_t)(1 << (i & BITMASK)))
8357c478bd9Sstevel@tonic-gate 				pci_config_put32(confhdl, offset, *p);
8367c478bd9Sstevel@tonic-gate 			p++;
8377c478bd9Sstevel@tonic-gate 			offset += sizeof (uint32_t);
8387c478bd9Sstevel@tonic-gate 		}
8397c478bd9Sstevel@tonic-gate 		ddi_prop_free(regbuf);
8407c478bd9Sstevel@tonic-gate 		ddi_prop_free(maskbuf);
8417c478bd9Sstevel@tonic-gate 		if (ndi_prop_remove(DDI_DEV_T_NONE, dip,
8427c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_MASK) != DDI_PROP_SUCCESS) {
8437c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s%d can't remove prop %s",
8447c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
8457c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_MASK);
8467c478bd9Sstevel@tonic-gate 		}
8477c478bd9Sstevel@tonic-gate 	} else {
8487c478bd9Sstevel@tonic-gate 		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8497c478bd9Sstevel@tonic-gate 		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS,
8507c478bd9Sstevel@tonic-gate 		    (uchar_t **)&regbuf, &elements) != DDI_PROP_SUCCESS) {
8517c478bd9Sstevel@tonic-gate 
8527c478bd9Sstevel@tonic-gate 			pci_config_teardown(&confhdl);
853abee7076Sgs 			return (DDI_SUCCESS);
8547c478bd9Sstevel@tonic-gate 		}
8557c478bd9Sstevel@tonic-gate 
8567c478bd9Sstevel@tonic-gate 		chs_p = (pci_config_header_state_t *)regbuf;
8577c478bd9Sstevel@tonic-gate 		pci_config_put16(confhdl, PCI_CONF_COMM,
8587c478bd9Sstevel@tonic-gate 		    chs_p->chs_command);
8597c478bd9Sstevel@tonic-gate 		if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) ==
8607c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE) {
8617c478bd9Sstevel@tonic-gate 			pci_config_put16(confhdl, PCI_BCNF_BCNTRL,
8627c478bd9Sstevel@tonic-gate 			    chs_p->chs_bridge_control);
8637c478bd9Sstevel@tonic-gate 		}
8647c478bd9Sstevel@tonic-gate 		pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ,
8657c478bd9Sstevel@tonic-gate 		    chs_p->chs_cache_line_size);
8667c478bd9Sstevel@tonic-gate 		pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER,
8677c478bd9Sstevel@tonic-gate 		    chs_p->chs_latency_timer);
8687c478bd9Sstevel@tonic-gate 		if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) ==
8697c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE)
8707c478bd9Sstevel@tonic-gate 			pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER,
8717c478bd9Sstevel@tonic-gate 			    chs_p->chs_sec_latency_timer);
8727c478bd9Sstevel@tonic-gate 
8737c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0);
8747c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
8757c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2);
8767c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3);
8777c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4);
8787c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5);
8797c478bd9Sstevel@tonic-gate 
8807c478bd9Sstevel@tonic-gate 		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8817c478bd9Sstevel@tonic-gate 		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
8827c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_CAPINFO,
8837c478bd9Sstevel@tonic-gate 		    (uchar_t **)&cap_descp, &elements) == DDI_PROP_SUCCESS) {
8847c478bd9Sstevel@tonic-gate 			/*
8857c478bd9Sstevel@tonic-gate 			 * PCI capability related regsiters are saved.
8867c478bd9Sstevel@tonic-gate 			 * Restore them based on the description.
8877c478bd9Sstevel@tonic-gate 			 */
8887c478bd9Sstevel@tonic-gate 			p = (uint32_t *)((caddr_t)regbuf +
8897c478bd9Sstevel@tonic-gate 			    sizeof (pci_config_header_state_t));
8907c478bd9Sstevel@tonic-gate 			pci_restore_caps(confhdl, p, cap_descp, elements);
8917c478bd9Sstevel@tonic-gate 			ddi_prop_free(cap_descp);
8927c478bd9Sstevel@tonic-gate 		}
8937c478bd9Sstevel@tonic-gate 
8947c478bd9Sstevel@tonic-gate 		ddi_prop_free(regbuf);
8957c478bd9Sstevel@tonic-gate 	}
8967c478bd9Sstevel@tonic-gate 
8977c478bd9Sstevel@tonic-gate 	/*
8987c478bd9Sstevel@tonic-gate 	 * Make sure registers are flushed
8997c478bd9Sstevel@tonic-gate 	 */
9007c478bd9Sstevel@tonic-gate 	(void) pci_config_get32(confhdl, PCI_CONF_BASE5);
9017c478bd9Sstevel@tonic-gate 
9027c478bd9Sstevel@tonic-gate 
9037c478bd9Sstevel@tonic-gate 	if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS) !=
9047c478bd9Sstevel@tonic-gate 	    DDI_PROP_SUCCESS) {
9057c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't remove prop %s",
9067c478bd9Sstevel@tonic-gate 		    ddi_driver_name(dip), ddi_get_instance(dip),
9077c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS);
9087c478bd9Sstevel@tonic-gate 	}
9097c478bd9Sstevel@tonic-gate 
9107c478bd9Sstevel@tonic-gate 	pci_config_teardown(&confhdl);
9117c478bd9Sstevel@tonic-gate 
9127c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
9137c478bd9Sstevel@tonic-gate 
9147c478bd9Sstevel@tonic-gate restoreconfig_err:
9157c478bd9Sstevel@tonic-gate 	ddi_prop_free(maskbuf);
9167c478bd9Sstevel@tonic-gate 	if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS_MASK) !=
9177c478bd9Sstevel@tonic-gate 	    DDI_PROP_SUCCESS) {
9187c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't remove prop %s",
9197c478bd9Sstevel@tonic-gate 		    ddi_driver_name(dip), ddi_get_instance(dip),
9207c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_MASK);
9217c478bd9Sstevel@tonic-gate 	}
9227c478bd9Sstevel@tonic-gate 	pci_config_teardown(&confhdl);
9237c478bd9Sstevel@tonic-gate 	return (DDI_FAILURE);
9247c478bd9Sstevel@tonic-gate }
9252df1fe9cSrandyf 
9262df1fe9cSrandyf /*ARGSUSED*/
9272df1fe9cSrandyf static int
9282df1fe9cSrandyf pci_lookup_pmcap(dev_info_t *dip, ddi_acc_handle_t conf_hdl,
9292df1fe9cSrandyf 	uint16_t *pmcap_offsetp)
9302df1fe9cSrandyf {
9312df1fe9cSrandyf 	uint8_t cap_ptr;
9322df1fe9cSrandyf 	uint8_t cap_id;
9332df1fe9cSrandyf 	uint8_t header_type;
9342df1fe9cSrandyf 	uint16_t status;
9352df1fe9cSrandyf 
9362df1fe9cSrandyf 	header_type = pci_config_get8(conf_hdl, PCI_CONF_HEADER);
9372df1fe9cSrandyf 	header_type &= PCI_HEADER_TYPE_M;
9382df1fe9cSrandyf 
9392df1fe9cSrandyf 	/* we don't deal with bridges, etc here */
9402df1fe9cSrandyf 	if (header_type != PCI_HEADER_ZERO) {
9412df1fe9cSrandyf 		return (DDI_FAILURE);
9422df1fe9cSrandyf 	}
9432df1fe9cSrandyf 
9442df1fe9cSrandyf 	status = pci_config_get16(conf_hdl, PCI_CONF_STAT);
9452df1fe9cSrandyf 	if ((status & PCI_STAT_CAP) == 0) {
9462df1fe9cSrandyf 		return (DDI_FAILURE);
9472df1fe9cSrandyf 	}
9482df1fe9cSrandyf 
9492df1fe9cSrandyf 	cap_ptr = pci_config_get8(conf_hdl, PCI_CONF_CAP_PTR);
9502df1fe9cSrandyf 
9512df1fe9cSrandyf 	/*
9522df1fe9cSrandyf 	 * Walk the capabilities searching for a PM entry.
9532df1fe9cSrandyf 	 */
9542df1fe9cSrandyf 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
9552df1fe9cSrandyf 		cap_id = pci_config_get8(conf_hdl, cap_ptr + PCI_CAP_ID);
9562df1fe9cSrandyf 		if (cap_id == PCI_CAP_ID_PM) {
9572df1fe9cSrandyf 			break;
9582df1fe9cSrandyf 		}
9592df1fe9cSrandyf 		cap_ptr = pci_config_get8(conf_hdl,
9602df1fe9cSrandyf 		    cap_ptr + PCI_CAP_NEXT_PTR);
9612df1fe9cSrandyf 	}
9622df1fe9cSrandyf 
9632df1fe9cSrandyf 	if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) {
9642df1fe9cSrandyf 		return (DDI_FAILURE);
9652df1fe9cSrandyf 	}
9662df1fe9cSrandyf 	*pmcap_offsetp = cap_ptr;
9672df1fe9cSrandyf 	return (DDI_SUCCESS);
9682df1fe9cSrandyf }
9692df1fe9cSrandyf 
9702df1fe9cSrandyf /*
9712df1fe9cSrandyf  * Do common pci-specific suspend actions:
9722df1fe9cSrandyf  *  - enable wakeup if appropriate for the device
9732df1fe9cSrandyf  *  - put device in lowest D-state that supports wakeup, or D3 if none
9742df1fe9cSrandyf  *  - turn off bus mastering in control register
9752df1fe9cSrandyf  * For lack of per-dip storage (parent private date is pretty busy)
9762df1fe9cSrandyf  * we use properties to store the necessary context
9772df1fe9cSrandyf  * To avoid grotting through pci config space on every suspend,
9782df1fe9cSrandyf  * we leave the prop in existence after resume, cause we know that
9792df1fe9cSrandyf  * the detach framework code will dispose of it for us.
9802df1fe9cSrandyf  */
9812df1fe9cSrandyf 
9822df1fe9cSrandyf typedef struct pci_pm_context {
9832df1fe9cSrandyf 	int		ppc_flags;
9842df1fe9cSrandyf 	uint16_t	ppc_cap_offset;	/* offset in config space to pm cap */
9852df1fe9cSrandyf 	uint16_t	ppc_pmcsr;	/* need this too */
9862df1fe9cSrandyf 	uint16_t	ppc_suspend_level;
9872df1fe9cSrandyf } pci_pm_context_t;
9882df1fe9cSrandyf 
9892df1fe9cSrandyf #define	SAVED_PM_CONTEXT	"pci-pm-context"
9902df1fe9cSrandyf 
9912df1fe9cSrandyf /* values for ppc_flags	*/
9922df1fe9cSrandyf #define	PPCF_NOPMCAP	1
9932df1fe9cSrandyf 
9942df1fe9cSrandyf /*
9952df1fe9cSrandyf  * Handle pci-specific suspend processing
9962df1fe9cSrandyf  *   PM CSR and PCI CMD are saved by pci_save_config_regs().
9972df1fe9cSrandyf  *   If device can wake up system via PME, enable it to do so
9982df1fe9cSrandyf  *   Set device power level to lowest that can generate PME, or D3 if none can
9992df1fe9cSrandyf  *   Turn off bus master enable in pci command register
10002df1fe9cSrandyf  */
10012df1fe9cSrandyf #if defined(__x86)
10022df1fe9cSrandyf extern int acpi_ddi_setwake(dev_info_t *dip, int level);
10032df1fe9cSrandyf #endif
10042df1fe9cSrandyf 
10052df1fe9cSrandyf int
10062df1fe9cSrandyf pci_post_suspend(dev_info_t *dip)
10072df1fe9cSrandyf {
10082df1fe9cSrandyf 	pci_pm_context_t *p;
10092df1fe9cSrandyf 	uint16_t	pmcap, pmcsr, pcicmd;
10102df1fe9cSrandyf 	uint_t length;
10112df1fe9cSrandyf 	int ret;
10122df1fe9cSrandyf 	int fromprop = 1;	/* source of memory *p */
10132df1fe9cSrandyf 	ddi_acc_handle_t hdl;
10142df1fe9cSrandyf 
10152df1fe9cSrandyf 	PMD(PMD_SX, ("pci_post_suspend %s:%d\n",
10162df1fe9cSrandyf 	    ddi_driver_name(dip), ddi_get_instance(dip)))
10172df1fe9cSrandyf 
10182df1fe9cSrandyf 	if (pci_save_config_regs(dip) != DDI_SUCCESS) {
10192df1fe9cSrandyf 		return (DDI_FAILURE);
10202df1fe9cSrandyf 	}
10212df1fe9cSrandyf 
10222df1fe9cSrandyf 	if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) {
10232df1fe9cSrandyf 		return (DDI_FAILURE);
10242df1fe9cSrandyf 	}
10252df1fe9cSrandyf 
10262df1fe9cSrandyf 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
10272df1fe9cSrandyf 	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
10282df1fe9cSrandyf 	    SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) {
10292df1fe9cSrandyf 		p = (pci_pm_context_t *)kmem_zalloc(sizeof (*p), KM_SLEEP);
10302df1fe9cSrandyf 		fromprop = 0;
10312df1fe9cSrandyf 		if (pci_lookup_pmcap(dip, hdl,
10322df1fe9cSrandyf 		    &p->ppc_cap_offset) != DDI_SUCCESS) {
10332df1fe9cSrandyf 			p->ppc_flags |= PPCF_NOPMCAP;
10342df1fe9cSrandyf 			ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
10352df1fe9cSrandyf 			    SAVED_PM_CONTEXT, (uchar_t *)p,
10362df1fe9cSrandyf 			    sizeof (pci_pm_context_t));
10372df1fe9cSrandyf 			if (ret != DDI_PROP_SUCCESS) {
10382df1fe9cSrandyf 				(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
10392df1fe9cSrandyf 				    SAVED_PM_CONTEXT);
10402df1fe9cSrandyf 				ret = DDI_FAILURE;
10412df1fe9cSrandyf 			} else {
10422df1fe9cSrandyf 				ret = DDI_SUCCESS;
10432df1fe9cSrandyf 			}
10442df1fe9cSrandyf 			kmem_free(p, sizeof (*p));
10452df1fe9cSrandyf 			pci_config_teardown(&hdl);
10462df1fe9cSrandyf 			return (DDI_SUCCESS);
10472df1fe9cSrandyf 		}
10482df1fe9cSrandyf 		/*
10492df1fe9cSrandyf 		 * Upon suspend, set the power level to the lowest that can
10502df1fe9cSrandyf 		 * wake the system.  If none can, then set to lowest.
10512df1fe9cSrandyf 		 * XXX later we will need to check policy to see if this
10522df1fe9cSrandyf 		 * XXX device has had wakeup disabled
10532df1fe9cSrandyf 		 */
10542df1fe9cSrandyf 		pmcap = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCAP);
10552df1fe9cSrandyf 		if ((pmcap & PCI_PMCAP_D3COLD_PME) != 0)
10562df1fe9cSrandyf 			p->ppc_suspend_level =
10572df1fe9cSrandyf 			    (PCI_PMCSR_PME_EN | PCI_PMCSR_D3HOT);
10582df1fe9cSrandyf 		else if ((pmcap & (PCI_PMCAP_D3HOT_PME | PCI_PMCAP_D2_PME)) !=
10592df1fe9cSrandyf 		    0)
10602df1fe9cSrandyf 			p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D2;
10612df1fe9cSrandyf 		else if ((pmcap & PCI_PMCAP_D1_PME) != 0)
10622df1fe9cSrandyf 			p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D1;
10632df1fe9cSrandyf 		else if ((pmcap & PCI_PMCAP_D0_PME) != 0)
10642df1fe9cSrandyf 			p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D0;
10652df1fe9cSrandyf 		else
10662df1fe9cSrandyf 			p->ppc_suspend_level = PCI_PMCSR_D3HOT;
10672df1fe9cSrandyf 
10682df1fe9cSrandyf 		/*
10692df1fe9cSrandyf 		 * we defer updating the property to catch the saved
10702df1fe9cSrandyf 		 * register values as well
10712df1fe9cSrandyf 		 */
10722df1fe9cSrandyf 	}
10732df1fe9cSrandyf 	/* If we set this in kmem_zalloc'd memory, we already returned above */
10742df1fe9cSrandyf 	if ((p->ppc_flags & PPCF_NOPMCAP) != 0) {
10752df1fe9cSrandyf 		ddi_prop_free(p);
10762df1fe9cSrandyf 		pci_config_teardown(&hdl);
10772df1fe9cSrandyf 		return (DDI_SUCCESS);
10782df1fe9cSrandyf 	}
10792df1fe9cSrandyf 
10802df1fe9cSrandyf 
10812df1fe9cSrandyf 	/*
10822df1fe9cSrandyf 	 * Turn off (Bus) Master Enable, since acpica will be turning off
10832df1fe9cSrandyf 	 * bus master aribitration
10842df1fe9cSrandyf 	 */
10852df1fe9cSrandyf 	pcicmd = pci_config_get16(hdl, PCI_CONF_COMM);
10862df1fe9cSrandyf 	pcicmd &= ~PCI_COMM_ME;
10872df1fe9cSrandyf 	pci_config_put16(hdl, PCI_CONF_COMM, pcicmd);
10882df1fe9cSrandyf 
10892df1fe9cSrandyf 	/*
10902df1fe9cSrandyf 	 * set pm csr
10912df1fe9cSrandyf 	 */
10922df1fe9cSrandyf 	pmcsr = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCSR);
10932df1fe9cSrandyf 	p->ppc_pmcsr = pmcsr;
10942df1fe9cSrandyf 	pmcsr &= (PCI_PMCSR_STATE_MASK);
10952df1fe9cSrandyf 	pmcsr |= (PCI_PMCSR_PME_STAT | p->ppc_suspend_level);
10962df1fe9cSrandyf 	pci_config_put16(hdl, p->ppc_cap_offset + PCI_PMCSR, pmcsr);
10972df1fe9cSrandyf 
10982df1fe9cSrandyf #if defined(__x86)
10992df1fe9cSrandyf 	/*
11002df1fe9cSrandyf 	 * Arrange for platform wakeup enabling
11012df1fe9cSrandyf 	 */
11022df1fe9cSrandyf 	if ((p->ppc_suspend_level & PCI_PMCSR_PME_EN) != 0) {
11032df1fe9cSrandyf 		int retval;
11042df1fe9cSrandyf 
11052df1fe9cSrandyf 		retval = acpi_ddi_setwake(dip, 3);	/* XXX 3 for now */
11062df1fe9cSrandyf 		if (retval) {
11072df1fe9cSrandyf 			PMD(PMD_SX, ("pci_post_suspend, setwake %s@%s rets "
11082df1fe9cSrandyf 			    "%x\n", PM_NAME(dip), PM_ADDR(dip), retval));
11092df1fe9cSrandyf 		}
11102df1fe9cSrandyf 	}
11112df1fe9cSrandyf #endif
11122df1fe9cSrandyf 
11132df1fe9cSrandyf 	/*
11142df1fe9cSrandyf 	 * Push out saved register values
11152df1fe9cSrandyf 	 */
11162df1fe9cSrandyf 	ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT,
11172df1fe9cSrandyf 	    (uchar_t *)p, sizeof (pci_pm_context_t));
11182df1fe9cSrandyf 	if (ret == DDI_PROP_SUCCESS) {
11192df1fe9cSrandyf 		if (fromprop)
11202df1fe9cSrandyf 			ddi_prop_free(p);
11212df1fe9cSrandyf 		else
11222df1fe9cSrandyf 			kmem_free(p, sizeof (*p));
11232df1fe9cSrandyf 		pci_config_teardown(&hdl);
11242df1fe9cSrandyf 		return (DDI_SUCCESS);
11252df1fe9cSrandyf 	}
11262df1fe9cSrandyf 	/* Failed; put things back the way we found them */
11272df1fe9cSrandyf 	(void) pci_restore_config_regs(dip);
11282df1fe9cSrandyf 	if (fromprop)
11292df1fe9cSrandyf 		ddi_prop_free(p);
11302df1fe9cSrandyf 	else
11312df1fe9cSrandyf 		kmem_free(p, sizeof (*p));
11322df1fe9cSrandyf 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT);
11332df1fe9cSrandyf 	pci_config_teardown(&hdl);
11342df1fe9cSrandyf 	return (DDI_FAILURE);
11352df1fe9cSrandyf }
11362df1fe9cSrandyf 
11372df1fe9cSrandyf /*
11382df1fe9cSrandyf  * The inverse of pci_post_suspend; handle pci-specific resume processing
11392df1fe9cSrandyf  *   First, turn device back on, then restore config space.
11402df1fe9cSrandyf  */
11412df1fe9cSrandyf 
11422df1fe9cSrandyf int
11432df1fe9cSrandyf pci_pre_resume(dev_info_t *dip)
11442df1fe9cSrandyf {
11452df1fe9cSrandyf 	ddi_acc_handle_t hdl;
11462df1fe9cSrandyf 	pci_pm_context_t *p;
11472df1fe9cSrandyf 	/* E_FUNC_SET_NOT_USED */
11482df1fe9cSrandyf 	uint16_t	pmcap, pmcsr;
11492df1fe9cSrandyf 	int flags;
11502df1fe9cSrandyf 	uint_t length;
11512df1fe9cSrandyf 	clock_t drv_usectohz(clock_t microsecs);
11522df1fe9cSrandyf #if defined(__x86)
11532df1fe9cSrandyf 	uint16_t	suspend_level;
11542df1fe9cSrandyf #endif
11552df1fe9cSrandyf 
11562df1fe9cSrandyf 	PMD(PMD_SX, ("pci_pre_resume %s:%d\n", ddi_driver_name(dip),
11572df1fe9cSrandyf 	    ddi_get_instance(dip)))
11582df1fe9cSrandyf 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
11592df1fe9cSrandyf 	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
11602df1fe9cSrandyf 	    SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) {
11612df1fe9cSrandyf 		return (DDI_FAILURE);
11622df1fe9cSrandyf 	}
11632df1fe9cSrandyf 	flags = p->ppc_flags;
11642df1fe9cSrandyf 	pmcap = p->ppc_cap_offset;
11652df1fe9cSrandyf 	pmcsr = p->ppc_pmcsr;
11662df1fe9cSrandyf #if defined(__x86)
11672df1fe9cSrandyf 	suspend_level = p->ppc_suspend_level;
11682df1fe9cSrandyf #endif
11692df1fe9cSrandyf 	ddi_prop_free(p);
1170abee7076Sgs 	if ((flags & PPCF_NOPMCAP) != 0)
1171abee7076Sgs 		goto done;
11722df1fe9cSrandyf #if defined(__x86)
11732df1fe9cSrandyf 	/*
11742df1fe9cSrandyf 	 * Turn platform wake enable back off
11752df1fe9cSrandyf 	 */
11762df1fe9cSrandyf 	if ((suspend_level & PCI_PMCSR_PME_EN) != 0) {
11772df1fe9cSrandyf 		int retval;
11782df1fe9cSrandyf 
11792df1fe9cSrandyf 		retval = acpi_ddi_setwake(dip, 0);	/* 0 for now */
11802df1fe9cSrandyf 		if (retval) {
11812df1fe9cSrandyf 			PMD(PMD_SX, ("pci_pre_resume, setwake %s@%s rets "
11822df1fe9cSrandyf 			    "%x\n", PM_NAME(dip), PM_ADDR(dip), retval));
11832df1fe9cSrandyf 		}
11842df1fe9cSrandyf 	}
11852df1fe9cSrandyf #endif
11862df1fe9cSrandyf 	if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) {
11872df1fe9cSrandyf 		return (DDI_FAILURE);
11882df1fe9cSrandyf 	}
11892df1fe9cSrandyf 	pci_config_put16(hdl, pmcap + PCI_PMCSR, pmcsr);
11902df1fe9cSrandyf 	delay(drv_usectohz(10000));	/* PCI PM spec D3->D0 (10ms) */
11912df1fe9cSrandyf 	pci_config_teardown(&hdl);
1192abee7076Sgs done:
11932df1fe9cSrandyf 	(void) pci_restore_config_regs(dip);	/* fudges D-state! */
11942df1fe9cSrandyf 	return (DDI_SUCCESS);
11952df1fe9cSrandyf }
1196