17c478bdstevel@tonic-gate/*
27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
54ab7525mrj * Common Development and Distribution License (the "License").
64ab7525mrj * You may not use this file except in compliance with the License.
77c478bdstevel@tonic-gate *
87c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bdstevel@tonic-gate * See the License for the specific language governing permissions
117c478bdstevel@tonic-gate * and limitations under the License.
127c478bdstevel@tonic-gate *
137c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bdstevel@tonic-gate *
197c478bdstevel@tonic-gate * CDDL HEADER END
207c478bdstevel@tonic-gate */
217c478bdstevel@tonic-gate/*
226f6c7d2Vincent Wang * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
237c478bdstevel@tonic-gate */
247c478bdstevel@tonic-gate
257c478bdstevel@tonic-gate#include <sys/types.h>
267c478bdstevel@tonic-gate#include <sys/sunndi.h>
2700d0963dilpreet#include <sys/sysmacros.h>
287c478bdstevel@tonic-gate#include <sys/pci.h>
299164eb6timh#include <sys/pcie.h>
307c478bdstevel@tonic-gate#include <sys/pci_impl.h>
317c478bdstevel@tonic-gate#include <sys/epm.h>
327c478bdstevel@tonic-gate
336f6c7d2Vincent Wangint	pci_enable_wakeup = 1;
346f6c7d2Vincent Wang
357c478bdstevel@tonic-gateint
367c478bdstevel@tonic-gatepci_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle)
377c478bdstevel@tonic-gate{
387c478bdstevel@tonic-gate	caddr_t	cfgaddr;
397c478bdstevel@tonic-gate	ddi_device_acc_attr_t attr;
407c478bdstevel@tonic-gate
417c478bdstevel@tonic-gate	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
427c478bdstevel@tonic-gate	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
437c478bdstevel@tonic-gate	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
447c478bdstevel@tonic-gate
457c478bdstevel@tonic-gate	/* Check for fault management capabilities */
4600d0963dilpreet	if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) {
4700d0963dilpreet		attr.devacc_attr_version = DDI_DEVICE_ATTR_V1;
487c478bdstevel@tonic-gate		attr.devacc_attr_access = DDI_FLAGERR_ACC;
4900d0963dilpreet	}
507c478bdstevel@tonic-gate
517c478bdstevel@tonic-gate	return (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, handle));
527c478bdstevel@tonic-gate}
537c478bdstevel@tonic-gate
547c478bdstevel@tonic-gatevoid
557c478bdstevel@tonic-gatepci_config_teardown(ddi_acc_handle_t *handle)
567c478bdstevel@tonic-gate{
577c478bdstevel@tonic-gate	ddi_regs_map_free(handle);
587c478bdstevel@tonic-gate}
597c478bdstevel@tonic-gate
607c478bdstevel@tonic-gateuint8_t
617c478bdstevel@tonic-gatepci_config_get8(ddi_acc_handle_t handle, off_t offset)
627c478bdstevel@tonic-gate{
637c478bdstevel@tonic-gate	caddr_t	cfgaddr;
647c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
657c478bdstevel@tonic-gate
667c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
677c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
687c478bdstevel@tonic-gate	return (ddi_get8(handle, (uint8_t *)cfgaddr));
697c478bdstevel@tonic-gate}
707c478bdstevel@tonic-gate
717c478bdstevel@tonic-gateuint16_t
727c478bdstevel@tonic-gatepci_config_get16(ddi_acc_handle_t handle, off_t offset)
737c478bdstevel@tonic-gate{
747c478bdstevel@tonic-gate	caddr_t	cfgaddr;
757c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
767c478bdstevel@tonic-gate
777c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
787c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
797c478bdstevel@tonic-gate	return (ddi_get16(handle, (uint16_t *)cfgaddr));
807c478bdstevel@tonic-gate}
817c478bdstevel@tonic-gate
827c478bdstevel@tonic-gateuint32_t
837c478bdstevel@tonic-gatepci_config_get32(ddi_acc_handle_t handle, off_t offset)
847c478bdstevel@tonic-gate{
857c478bdstevel@tonic-gate	caddr_t	cfgaddr;
867c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
877c478bdstevel@tonic-gate
887c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
897c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
907c478bdstevel@tonic-gate	return (ddi_get32(handle, (uint32_t *)cfgaddr));
917c478bdstevel@tonic-gate}
927c478bdstevel@tonic-gate
937c478bdstevel@tonic-gateuint64_t
947c478bdstevel@tonic-gatepci_config_get64(ddi_acc_handle_t handle, off_t offset)
957c478bdstevel@tonic-gate{
967c478bdstevel@tonic-gate	caddr_t	cfgaddr;
977c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
987c478bdstevel@tonic-gate
997c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
1007c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
1017c478bdstevel@tonic-gate	return (ddi_get64(handle, (uint64_t *)cfgaddr));
1027c478bdstevel@tonic-gate}
1037c478bdstevel@tonic-gate
1047c478bdstevel@tonic-gatevoid
1057c478bdstevel@tonic-gatepci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value)
1067c478bdstevel@tonic-gate{
1077c478bdstevel@tonic-gate	caddr_t	cfgaddr;
1087c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
1097c478bdstevel@tonic-gate
1107c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
1117c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
1127c478bdstevel@tonic-gate	ddi_put8(handle, (uint8_t *)cfgaddr, value);
1137c478bdstevel@tonic-gate}
1147c478bdstevel@tonic-gate
1157c478bdstevel@tonic-gatevoid
1167c478bdstevel@tonic-gatepci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value)
1177c478bdstevel@tonic-gate{
1187c478bdstevel@tonic-gate	caddr_t	cfgaddr;
1197c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
1207c478bdstevel@tonic-gate
1217c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
1227c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
1237c478bdstevel@tonic-gate	ddi_put16(handle, (uint16_t *)cfgaddr, value);
1247c478bdstevel@tonic-gate}
1257c478bdstevel@tonic-gate
1267c478bdstevel@tonic-gatevoid
1277c478bdstevel@tonic-gatepci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value)
1287c478bdstevel@tonic-gate{
1297c478bdstevel@tonic-gate	caddr_t	cfgaddr;
1307c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
1317c478bdstevel@tonic-gate
1327c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
1337c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
1347c478bdstevel@tonic-gate	ddi_put32(handle, (uint32_t *)cfgaddr, value);
1357c478bdstevel@tonic-gate}
1367c478bdstevel@tonic-gate
1377c478bdstevel@tonic-gatevoid
1387c478bdstevel@tonic-gatepci_config_put64(ddi_acc_handle_t handle, off_t offset, uint64_t value)
1394ab7525mrj{
1404ab7525mrj	caddr_t	cfgaddr;
1414ab7525mrj	ddi_acc_hdl_t *hp;
1424ab7525mrj
1434ab7525mrj	hp = impl_acc_hdl_get(handle);
1444ab7525mrj	cfgaddr = hp->ah_addr + offset;
1454ab7525mrj	ddi_put64(handle, (uint64_t *)cfgaddr, value);
1464ab7525mrj}
1474ab7525mrj
1484ab7525mrj/*
1494ab7525mrj * We need to separate the old interfaces from the new ones and leave them
1504ab7525mrj * in here for a while. Previous versions of the OS defined the new interfaces
1514ab7525mrj * to the old interfaces. This way we can fix things up so that we can
1524ab7525mrj * eventually remove these interfaces.
1534ab7525mrj * e.g. A 3rd party module/driver using pci_config_get8 and built against S10
1544ab7525mrj * or earlier will actually have a reference to pci_config_getb in the binary.
1554ab7525mrj */
1564ab7525mrj#ifdef _ILP32
1574ab7525mrjuint8_t
1584ab7525mrjpci_config_getb(ddi_acc_handle_t handle, off_t offset)
1594ab7525mrj{
1604ab7525mrj	caddr_t	cfgaddr;
1614ab7525mrj	ddi_acc_hdl_t *hp;
1624ab7525mrj
1634ab7525mrj	hp = impl_acc_hdl_get(handle);
1644ab7525mrj	cfgaddr = hp->ah_addr + offset;
1654ab7525mrj	return (ddi_get8(handle, (uint8_t *)cfgaddr));
1664ab7525mrj}
1674ab7525mrj
1684ab7525mrjuint16_t
1694ab7525mrjpci_config_getw(ddi_acc_handle_t handle, off_t offset)
1704ab7525mrj{
1714ab7525mrj	caddr_t	cfgaddr;
1724ab7525mrj	ddi_acc_hdl_t *hp;
1734ab7525mrj
1744ab7525mrj	hp = impl_acc_hdl_get(handle);
1754ab7525mrj	cfgaddr = hp->ah_addr + offset;
1764ab7525mrj	return (ddi_get16(handle, (uint16_t *)cfgaddr));
1774ab7525mrj}
1784ab7525mrj
1794ab7525mrjuint32_t
1804ab7525mrjpci_config_getl(ddi_acc_handle_t handle, off_t offset)
1814ab7525mrj{
1824ab7525mrj	caddr_t	cfgaddr;
1834ab7525mrj	ddi_acc_hdl_t *hp;
1844ab7525mrj
1854ab7525mrj	hp = impl_acc_hdl_get(handle);
1864ab7525mrj	cfgaddr = hp->ah_addr + offset;
1874ab7525mrj	return (ddi_get32(handle, (uint32_t *)cfgaddr));
1884ab7525mrj}
1894ab7525mrj
1904ab7525mrjuint64_t
1914ab7525mrjpci_config_getll(ddi_acc_handle_t handle, off_t offset)
1924ab7525mrj{
1934ab7525mrj	caddr_t	cfgaddr;
1944ab7525mrj	ddi_acc_hdl_t *hp;
1954ab7525mrj
1964ab7525mrj	hp = impl_acc_hdl_get(handle);
1974ab7525mrj	cfgaddr = hp->ah_addr + offset;
1984ab7525mrj	return (ddi_get64(handle, (uint64_t *)cfgaddr));
1994ab7525mrj}
2004ab7525mrj
2014ab7525mrjvoid
2024ab7525mrjpci_config_putb(ddi_acc_handle_t handle, off_t offset, uint8_t value)
2034ab7525mrj{
2044ab7525mrj	caddr_t	cfgaddr;
2054ab7525mrj	ddi_acc_hdl_t *hp;
2064ab7525mrj
2074ab7525mrj	hp = impl_acc_hdl_get(handle);
2084ab7525mrj	cfgaddr = hp->ah_addr + offset;
2094ab7525mrj	ddi_put8(handle, (uint8_t *)cfgaddr, value);
2104ab7525mrj}
2114ab7525mrj
2124ab7525mrjvoid
2134ab7525mrjpci_config_putw(ddi_acc_handle_t handle, off_t offset, uint16_t value)
2144ab7525mrj{
2154ab7525mrj	caddr_t	cfgaddr;
2164ab7525mrj	ddi_acc_hdl_t *hp;
2174ab7525mrj
2184ab7525mrj	hp = impl_acc_hdl_get(handle);
2194ab7525mrj	cfgaddr = hp->ah_addr + offset;
2204ab7525mrj	ddi_put16(handle, (uint16_t *)cfgaddr, value);
2214ab7525mrj}
2224ab7525mrj
2234ab7525mrjvoid
2244ab7525mrjpci_config_putl(ddi_acc_handle_t handle, off_t offset, uint32_t value)
2254ab7525mrj{
2264ab7525mrj	caddr_t	cfgaddr;
2274ab7525mrj	ddi_acc_hdl_t *hp;
2284ab7525mrj
2294ab7525mrj	hp = impl_acc_hdl_get(handle);
2304ab7525mrj	cfgaddr = hp->ah_addr + offset;
2314ab7525mrj	ddi_put32(handle, (uint32_t *)cfgaddr, value);
2324ab7525mrj}
2334ab7525mrj
2347c478bdstevel@tonic-gatevoid
2357c478bdstevel@tonic-gatepci_config_putll(ddi_acc_handle_t handle, off_t offset, uint64_t value)
2367c478bdstevel@tonic-gate{
2377c478bdstevel@tonic-gate	caddr_t	cfgaddr;
2387c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
2397c478bdstevel@tonic-gate
2407c478bdstevel@tonic-gate	hp = impl_acc_hdl_get(handle);
2417c478bdstevel@tonic-gate	cfgaddr = hp->ah_addr + offset;
2427c478bdstevel@tonic-gate	ddi_put64(handle, (uint64_t *)cfgaddr, value);
2437c478bdstevel@tonic-gate}
2444ab7525mrj#endif /* _ILP32 */
2457c478bdstevel@tonic-gate
2467c478bdstevel@tonic-gate/*ARGSUSED*/
2477c478bdstevel@tonic-gateint
2487c478bdstevel@tonic-gatepci_report_pmcap(dev_info_t *dip, int cap, void *arg)
2497c478bdstevel@tonic-gate{
2507c478bdstevel@tonic-gate	return (DDI_SUCCESS);
2517c478bdstevel@tonic-gate}
2527c478bdstevel@tonic-gate
2537c478bdstevel@tonic-gate/*
2547c478bdstevel@tonic-gate * Note about saving and restoring config space.
2557c478bdstevel@tonic-gate * PCI devices have only upto 256 bytes of config space while PCI Express
2567c478bdstevel@tonic-gate * devices can have upto 4k config space. In case of PCI Express device,
2577c478bdstevel@tonic-gate * we save all 4k config space and restore it even if it doesn't make use
2587c478bdstevel@tonic-gate * of all 4k. But some devices don't respond to reads to non-existent
2597c478bdstevel@tonic-gate * registers within the config space. To avoid any panics, we use ddi_peek
2607c478bdstevel@tonic-gate * to do the reads. A bit mask is used to indicate which words of the
2617c478bdstevel@tonic-gate * config space are accessible. While restoring the config space, only those
2627c478bdstevel@tonic-gate * readable words are restored. We do all this in 32 bit size words.
2637c478bdstevel@tonic-gate */
2647c478bdstevel@tonic-gate#define	INDEX_SHIFT		3
2657c478bdstevel@tonic-gate#define	BITMASK			0x7
2667c478bdstevel@tonic-gate
2677c478bdstevel@tonic-gatestatic uint32_t pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2687c478bdstevel@tonic-gate    pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp);
2697c478bdstevel@tonic-gatestatic void pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2707c478bdstevel@tonic-gate    pci_cap_save_desc_t *cap_descp, uint32_t elements);
2717c478bdstevel@tonic-gatestatic uint32_t pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2727c478bdstevel@tonic-gate    uint32_t *regbuf, uint32_t nwords);
2737c478bdstevel@tonic-gatestatic uint32_t pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2747c478bdstevel@tonic-gate    uint32_t *regbuf, uint32_t notused);
2757c478bdstevel@tonic-gatestatic uint32_t pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2767c478bdstevel@tonic-gate    uint32_t *regbuf, uint32_t notused);
2777c478bdstevel@tonic-gatestatic uint32_t pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2787c478bdstevel@tonic-gate    uint32_t *regbuf, uint32_t notused);
279cb7ea99Jimmy Vetayasesstatic uint32_t pci_ht_addrmap_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
280cb7ea99Jimmy Vetayases    uint32_t *regbuf, uint32_t notused);
281cb7ea99Jimmy Vetayasesstatic uint32_t pci_ht_funcext_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
282cb7ea99Jimmy Vetayases    uint32_t *regbuf, uint32_t notused);
2837c478bdstevel@tonic-gatestatic void pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
2847c478bdstevel@tonic-gate    uint32_t *regbuf, uint32_t nwords);
2857c478bdstevel@tonic-gatestatic uint32_t cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2867c478bdstevel@tonic-gate    pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace);
2877c478bdstevel@tonic-gatestatic void pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf,
2887c478bdstevel@tonic-gate    uint16_t pmcap_offset);
2897c478bdstevel@tonic-gate
2907c478bdstevel@tonic-gate/*
2917c478bdstevel@tonic-gate * Table below specifies the number of registers to be saved for each PCI
2927c478bdstevel@tonic-gate * capability. pci_generic_save saves the number of words specified in the
2937c478bdstevel@tonic-gate * table. Any special considerations will be taken care by the capability
2947c478bdstevel@tonic-gate * specific save function e.g. use pci_msi_save to save registers associated
2957c478bdstevel@tonic-gate * with MSI capability. PCI_UNKNOWN_SIZE indicates that number of registers
2967c478bdstevel@tonic-gate * to be saved is variable and will be determined by the specific save function.
2977c478bdstevel@tonic-gate * Currently we save/restore all the registers associated with the capability
2987c478bdstevel@tonic-gate * including read only registers. Regsiters are saved and restored in 32 bit
2997c478bdstevel@tonic-gate * size words.
3007c478bdstevel@tonic-gate */
3017c478bdstevel@tonic-gatestatic pci_cap_entry_t pci_cap_table[] = {
302cb7ea99Jimmy Vetayases	{PCI_CAP_ID_PM, 0, 0, PCI_PMCAP_NDWORDS, pci_generic_save},
303cb7ea99Jimmy Vetayases	{PCI_CAP_ID_AGP, 0, 0, PCI_AGP_NDWORDS, pci_generic_save},
304cb7ea99Jimmy Vetayases	{PCI_CAP_ID_SLOT_ID, 0, 0, PCI_SLOTID_NDWORDS, pci_generic_save},
305cb7ea99Jimmy Vetayases	{PCI_CAP_ID_MSI_X, 0, 0, PCI_MSIX_NDWORDS, pci_generic_save},
306cb7ea99Jimmy Vetayases	{PCI_CAP_ID_MSI, 0, 0, PCI_CAP_SZUNKNOWN, pci_msi_save},
307cb7ea99Jimmy Vetayases	{PCI_CAP_ID_PCIX, 0, 0, PCI_CAP_SZUNKNOWN, pci_pcix_save},
308cb7ea99Jimmy Vetayases	{PCI_CAP_ID_PCI_E, 0, 0, PCI_CAP_SZUNKNOWN, pci_pcie_save},
309cb7ea99Jimmy Vetayases
310cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_SLPRI_TYPE, PCI_HTCAP_TYPE_SLHOST_MASK,
311cb7ea99Jimmy Vetayases		PCI_HTCAP_SLPRI_NDWORDS, pci_generic_save},
312cb7ea99Jimmy Vetayases
313cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_HOSTSEC_TYPE, PCI_HTCAP_TYPE_SLHOST_MASK,
314cb7ea99Jimmy Vetayases		PCI_HTCAP_HOSTSEC_NDWORDS, pci_generic_save},
315cb7ea99Jimmy Vetayases
316cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_INTCONF_TYPE, PCI_HTCAP_TYPE_MASK,
317cb7ea99Jimmy Vetayases		PCI_HTCAP_INTCONF_NDWORDS, pci_generic_save},
318cb7ea99Jimmy Vetayases
319cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_REVID_TYPE, PCI_HTCAP_TYPE_MASK,
320cb7ea99Jimmy Vetayases		PCI_HTCAP_REVID_NDWORDS, pci_generic_save},
321cb7ea99Jimmy Vetayases
322cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_UNITID_CLUMP_TYPE, PCI_HTCAP_TYPE_MASK,
323cb7ea99Jimmy Vetayases		PCI_HTCAP_UNITID_CLUMP_NDWORDS, pci_generic_save},
324cb7ea99Jimmy Vetayases
325cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_ECFG_TYPE, PCI_HTCAP_TYPE_MASK,
326cb7ea99Jimmy Vetayases		PCI_HTCAP_ECFG_NDWORDS, pci_generic_save},
327cb7ea99Jimmy Vetayases
328cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_ADDRMAP_TYPE, PCI_HTCAP_TYPE_MASK,
329cb7ea99Jimmy Vetayases		PCI_CAP_SZUNKNOWN, pci_ht_addrmap_save},
330cb7ea99Jimmy Vetayases
331cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_MSIMAP_TYPE, PCI_HTCAP_TYPE_MASK,
332cb7ea99Jimmy Vetayases		PCI_HTCAP_MSIMAP_NDWORDS, pci_generic_save},
333cb7ea99Jimmy Vetayases
334cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_DIRROUTE_TYPE, PCI_HTCAP_TYPE_MASK,
335cb7ea99Jimmy Vetayases		PCI_HTCAP_DIRROUTE_NDWORDS, pci_generic_save},
336cb7ea99Jimmy Vetayases
337cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_VCSET_TYPE, PCI_HTCAP_TYPE_MASK,
338cb7ea99Jimmy Vetayases		PCI_HTCAP_VCSET_NDWORDS, pci_generic_save},
339cb7ea99Jimmy Vetayases
340cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_RETRYMODE_TYPE, PCI_HTCAP_TYPE_MASK,
341cb7ea99Jimmy Vetayases		PCI_HTCAP_RETRYMODE_NDWORDS, pci_generic_save},
342cb7ea99Jimmy Vetayases
343cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_GEN3_TYPE, PCI_HTCAP_TYPE_MASK,
344cb7ea99Jimmy Vetayases		PCI_HTCAP_GEN3_NDWORDS, pci_generic_save},
345cb7ea99Jimmy Vetayases
346cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_FUNCEXT_TYPE, PCI_HTCAP_TYPE_MASK,
347cb7ea99Jimmy Vetayases		PCI_CAP_SZUNKNOWN, pci_ht_funcext_save},
348cb7ea99Jimmy Vetayases
349cb7ea99Jimmy Vetayases	{PCI_CAP_ID_HT, PCI_HTCAP_PM_TYPE, PCI_HTCAP_TYPE_MASK,
350cb7ea99Jimmy Vetayases		PCI_HTCAP_PM_NDWORDS, pci_generic_save},
351cb7ea99Jimmy Vetayases
3527c478bdstevel@tonic-gate	/*
3537c478bdstevel@tonic-gate	 * {PCI_CAP_ID_cPCI_CRC, 0, NULL},
3547c478bdstevel@tonic-gate	 * {PCI_CAP_ID_VPD, 0, NULL},
3557c478bdstevel@tonic-gate	 * {PCI_CAP_ID_cPCI_HS, 0, NULL},
3567c478bdstevel@tonic-gate	 * {PCI_CAP_ID_PCI_HOTPLUG, 0, NULL},
3577c478bdstevel@tonic-gate	 * {PCI_CAP_ID_AGP_8X, 0, NULL},
3587c478bdstevel@tonic-gate	 * {PCI_CAP_ID_SECURE_DEV, 0, NULL},
3597c478bdstevel@tonic-gate	 */
3607e12cebToomas Soome	{PCI_CAP_NEXT_PTR_NULL, 0, 0}
3617c478bdstevel@tonic-gate};
3627c478bdstevel@tonic-gate
363cb7ea99Jimmy Vetayases
3647c478bdstevel@tonic-gate/*
3657c478bdstevel@tonic-gate * Save the configuration registers for cdip as a property
3667c478bdstevel@tonic-gate * so that it persists after detach/uninitchild.
3677c478bdstevel@tonic-gate */
3687c478bdstevel@tonic-gateint
3697c478bdstevel@tonic-gatepci_save_config_regs(dev_info_t *dip)
3707c478bdstevel@tonic-gate{
3717c478bdstevel@tonic-gate	ddi_acc_handle_t confhdl;
3727c478bdstevel@tonic-gate	pci_config_header_state_t *chsp;
3737c478bdstevel@tonic-gate	pci_cap_save_desc_t *pci_cap_descp;
3747c478bdstevel@tonic-gate	int ret;
3757c478bdstevel@tonic-gate	uint32_t i, ncaps, nwords;
3767c478bdstevel@tonic-gate	uint32_t *regbuf, *p;
3777c478bdstevel@tonic-gate	uint8_t *maskbuf;
3787c478bdstevel@tonic-gate	size_t maskbufsz, regbufsz, capbufsz;
379c4e64f2gs#ifdef __sparc
3807c478bdstevel@tonic-gate	ddi_acc_hdl_t *hp;
381c4e64f2gs#else
382c4e64f2gs	ddi_device_acc_attr_t attr;
383c4e64f2gs	caddr_t cfgaddr;
384c4e64f2gs#endif
3857c478bdstevel@tonic-gate	off_t offset = 0;
3867c478bdstevel@tonic-gate	uint8_t cap_ptr, cap_id;
3877c478bdstevel@tonic-gate	int pcie = 0;
388c602bc2yf	uint16_t status;
389c602bc2yf
3902df1fe9randyf	PMD(PMD_SX, ("pci_save_config_regs %s:%d\n", ddi_driver_name(dip),
3912df1fe9randyf	    ddi_get_instance(dip)))
3927c478bdstevel@tonic-gate
393c4e64f2gs#ifdef __sparc
3947c478bdstevel@tonic-gate	if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) {
3957c478bdstevel@tonic-gate		cmn_err(CE_WARN, "%s%d can't get config handle",
3962df1fe9randyf		    ddi_driver_name(dip), ddi_get_instance(dip));
3977c478bdstevel@tonic-gate
3987c478bdstevel@tonic-gate		return (DDI_FAILURE);
3997c478bdstevel@tonic-gate	}
400c4e64f2gs#else
401c4e64f2gs	/* Set up cautious config access handle */
402c4e64f2gs	attr.devacc_attr_version = DDI_DEVICE_ATTR_V1;
403c4e64f2gs	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
404c4e64f2gs	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
405c4e64f2gs	attr.devacc_attr_access = DDI_CAUTIOUS_ACC;
406c4e64f2gs	if (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, &confhdl)
407c4e64f2gs	    != DDI_SUCCESS) {
408c4e64f2gs		cmn_err(CE_WARN, "%s%d can't setup cautious config handle",
409c4e64f2gs		    ddi_driver_name(dip), ddi_get_instance(dip));
410c4e64f2gs
411c4e64f2gs		return (DDI_FAILURE);
412c4e64f2gs	}
413c4e64f2gs#endif
414c602bc2yf
415c602bc2yf	/*
416c602bc2yf	 * Determine if it implements capabilities
417c602bc2yf	 */
418c602bc2yf	status = pci_config_get16(confhdl, PCI_CONF_STAT);
419c602bc2yf	if (!(status & 0x10)) {
420c602bc2yf		goto no_cap;
421c602bc2yf	}
4227c478bdstevel@tonic-gate	/*
4237c478bdstevel@tonic-gate	 * Determine if it is a pci express device. If it is, save entire
4247c478bdstevel@tonic-gate	 * 4k config space treating it as a array of 32 bit integers.
4257c478bdstevel@tonic-gate	 * If it is not, do it in a usual PCI way.
4267c478bdstevel@tonic-gate	 */
4277c478bdstevel@tonic-gate	cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR);
4287c478bdstevel@tonic-gate	/*
4297c478bdstevel@tonic-gate	 * Walk the capabilities searching for pci express capability
4307c478bdstevel@tonic-gate	 */
4317c478bdstevel@tonic-gate	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
4327c478bdstevel@tonic-gate		cap_id = pci_config_get8(confhdl,
4337c478bdstevel@tonic-gate		    cap_ptr + PCI_CAP_ID);
4347c478bdstevel@tonic-gate		if (cap_id == PCI_CAP_ID_PCI_E) {
4357c478bdstevel@tonic-gate			pcie = 1;
4367c478bdstevel@tonic-gate			break;
4377c478bdstevel@tonic-gate		}
4387c478bdstevel@tonic-gate		cap_ptr = pci_config_get8(confhdl,
4397c478bdstevel@tonic-gate		    cap_ptr + PCI_CAP_NEXT_PTR);
4407c478bdstevel@tonic-gate	}
441c602bc2yfno_cap:
4427c478bdstevel@tonic-gate	if (pcie) {
4437c478bdstevel@tonic-gate		/* PCI express device. Can have data in all 4k space */
4447c478bdstevel@tonic-gate		regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE,
4452df1fe9randyf		    KM_SLEEP);
4467c478bdstevel@tonic-gate		p = regbuf;
4477c478bdstevel@tonic-gate		/*
4487c478bdstevel@tonic-gate		 * Allocate space for mask.
4497c478bdstevel@tonic-gate		 * mask size is 128 bytes (4096 / 4 / 8 )
4507c478bdstevel@tonic-gate		 */
4517c478bdstevel@tonic-gate		maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >>
4527c478bdstevel@tonic-gate		    INDEX_SHIFT);
4537c478bdstevel@tonic-gate		maskbuf = (uint8_t *)kmem_zalloc(maskbufsz, KM_SLEEP);
454c4e64f2gs#ifdef __sparc
4557c478bdstevel@tonic-gate		hp = impl_acc_hdl_get(confhdl);
456c4e64f2gs#endif
4577c478bdstevel@tonic-gate		for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) {
458c4e64f2gs#ifdef __sparc
459c4e64f2gs			ret = ddi_peek32(dip, (int32_t *)(hp->ah_addr + offset),
460c4e64f2gs			    (int32_t *)p);
461abee707gs			if (ret == DDI_SUCCESS) {
462c4e64f2gs#else
463c4e64f2gs			/*
464c4e64f2gs			 * ddi_peek doesn't work on x86, so we use cautious pci
465c4e64f2gs			 * config access instead.
466c4e64f2gs			 */
467c4e64f2gs			*p = pci_config_get32(confhdl, offset);
468c4e64f2gs			if (*p != -1) {
469c4e64f2gs#endif
4707c478bdstevel@tonic-gate				/* it is readable register. set the bit */
4717c478bdstevel@tonic-gate				maskbuf[i >> INDEX_SHIFT] |=
4727c478bdstevel@tonic-gate				    (uint8_t)(1 << (i & BITMASK));
4737c478bdstevel@tonic-gate			}
4747c478bdstevel@tonic-gate			p++;
4757c478bdstevel@tonic-gate			offset += sizeof (uint32_t);
4767c478bdstevel@tonic-gate		}
4777c478bdstevel@tonic-gate
4787c478bdstevel@tonic-gate		if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
4797c478bdstevel@tonic-gate		    SAVED_CONFIG_REGS_MASK, (uchar_t *)maskbuf,
4807c478bdstevel@tonic-gate		    maskbufsz)) != DDI_PROP_SUCCESS) {
4817c478bdstevel@tonic-gate			cmn_err(CE_WARN, "couldn't create %s property while"
4827c478bdstevel@tonic-gate			    "saving config space for %s@%d\n",
4837c478bdstevel@tonic-gate			    SAVED_CONFIG_REGS_MASK, ddi_driver_name(dip),
4847c478bdstevel@tonic-gate			    ddi_get_instance(dip));
4857c478bdstevel@tonic-gate		} else if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE,
4867c478bdstevel@tonic-gate		    dip, SAVED_CONFIG_REGS, (uchar_t *)regbuf,
4877c478bdstevel@tonic-gate		    (size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) {
4887c478bdstevel@tonic-gate			(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
4897c478bdstevel@tonic-gate			    SAVED_CONFIG_REGS_MASK);
4907c478bdstevel@tonic-gate			cmn_err(CE_WARN, "%s%d can't update prop %s",
4917c478bdstevel@tonic-gate			    ddi_driver_name(dip), ddi_get_instance(dip),
4927c478bdstevel@tonic-gate			    SAVED_CONFIG_REGS);
4937c478bdstevel@tonic-gate		}
4947c478bdstevel@tonic-gate
4957c478bdstevel@tonic-gate		kmem_free(maskbuf, (size_t)maskbufsz);
4967c478bdstevel@tonic-gate		kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE);
4977c478bdstevel@tonic-gate	} else {
4987c478bdstevel@tonic-gate		regbuf = (uint32_t *)kmem_zalloc((size_t)PCI_CONF_HDR_SIZE,
4992df1fe9randyf		    KM_SLEEP);
5007c478bdstevel@tonic-gate		chsp = (pci_config_header_state_t *)regbuf;
5017c478bdstevel@tonic-gate
5027c478bdstevel@tonic-gate		chsp->chs_command = pci_config_get16(confhdl, PCI_CONF_COMM);
5037c478bdstevel@tonic-gate		chsp->chs_header_type =	pci_config_get8(confhdl,
5042df1fe9randyf		    PCI_CONF_HEADER);
5057c478bdstevel@tonic-gate		if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) ==
5067c478bdstevel@tonic-gate		    PCI_HEADER_ONE)
5077c478bdstevel@tonic-gate			chsp->chs_bridge_control =
5087c478bdstevel@tonic-gate			    pci_config_get16(confhdl, PCI_BCNF_BCNTRL);
5097c478bdstevel@tonic-gate		chsp->chs_cache_line_size = pci_config_get8(confhdl,
5107c478bdstevel@tonic-gate		    PCI_CONF_CACHE_LINESZ);
5117c478bdstevel@tonic-gate		chsp->chs_latency_timer = pci_config_get8(confhdl,
5127c478bdstevel@tonic-gate		    PCI_CONF_LATENCY_TIMER);
5137c478bdstevel@tonic-gate		if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) ==
5147c478bdstevel@tonic-gate		    PCI_HEADER_ONE) {
5157c478bdstevel@tonic-gate			chsp->chs_sec_latency_timer =
5167c478bdstevel@tonic-gate			    pci_config_get8(confhdl, PCI_BCNF_LATENCY_TIMER);
5177c478bdstevel@tonic-gate		}
5187c478bdstevel@tonic-gate
5197c478bdstevel@tonic-gate		chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);
5207c478bdstevel@tonic-gate		chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
5217c478bdstevel@tonic-gate		chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);
5227c478bdstevel@tonic-gate		chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);
5237c478bdstevel@tonic-gate		chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4);
5247c478bdstevel@tonic-gate		chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);
5257c478bdstevel@tonic-gate
5267c478bdstevel@tonic-gate		/*
5277c478bdstevel@tonic-gate		 * Allocate maximum space required for capability descriptions.
5287c478bdstevel@tonic-gate		 * The maximum number of capabilties saved is the number of
5297c478bdstevel@tonic-gate		 * capabilities listed in the pci_cap_table.
5307c478bdstevel@tonic-gate		 */
5317c478bdstevel@tonic-gate		ncaps = (sizeof (pci_cap_table) / sizeof (pci_cap_entry_t));
5327c478bdstevel@tonic-gate		capbufsz = ncaps * sizeof (pci_cap_save_desc_t);
5337c478bdstevel@tonic-gate		pci_cap_descp = (pci_cap_save_desc_t *)kmem_zalloc(
5347c478bdstevel@tonic-gate		    capbufsz, KM_SLEEP);
5357c478bdstevel@tonic-gate		p = (uint32_t *)((caddr_t)regbuf +
5367c478bdstevel@tonic-gate		    sizeof (pci_config_header_state_t));
5377c478bdstevel@tonic-gate		nwords = pci_save_caps(confhdl, p, pci_cap_descp, &ncaps);
5387c478bdstevel@tonic-gate		regbufsz = sizeof (pci_config_header_state_t) +
5397c478bdstevel@tonic-gate		    nwords * sizeof (uint32_t);
5407c478bdstevel@tonic-gate
5417c478bdstevel@tonic-gate		if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
5427c478bdstevel@tonic-gate		    SAVED_CONFIG_REGS, (uchar_t *)regbuf, regbufsz)) !=
5437c478bdstevel@tonic-gate		    DDI_PROP_SUCCESS) {
5447c478bdstevel@tonic-gate			cmn_err(CE_WARN, "%s%d can't update prop %s",
5457c478bdstevel@tonic-gate			    ddi_driver_name(dip), ddi_get_instance(dip),
5467c478bdstevel@tonic-gate			    SAVED_CONFIG_REGS);
5477c478bdstevel@tonic-gate		} else if (ncaps) {
5487c478bdstevel@tonic-gate			ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
5497c478bdstevel@tonic-gate			    SAVED_CONFIG_REGS_CAPINFO, (uchar_t *)pci_cap_descp,
5507c478bdstevel@tonic-gate			    ncaps * sizeof (pci_cap_save_desc_t));
5517c478bdstevel@tonic-gate			if (ret != DDI_PROP_SUCCESS)
5527c478bdstevel@tonic-gate				(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
5537c478bdstevel@tonic-gate				    SAVED_CONFIG_REGS);
5547c478bdstevel@tonic-gate		}
5557c478bdstevel@tonic-gate		kmem_free(regbuf, (size_t)PCI_CONF_HDR_SIZE);
5567c478bdstevel@tonic-gate		kmem_free(pci_cap_descp, capbufsz);
5577c478bdstevel@tonic-gate	}
5587c478bdstevel@tonic-gate	pci_config_teardown(&confhdl);
5597c478bdstevel@tonic-gate
5607c478bdstevel@tonic-gate	if (ret != DDI_PROP_SUCCESS)
5617c478bdstevel@tonic-gate		return (DDI_FAILURE);
5627c478bdstevel@tonic-gate
5637c478bdstevel@tonic-gate	return (DDI_SUCCESS);
5647c478bdstevel@tonic-gate}
5657c478bdstevel@tonic-gate
5667c478bdstevel@tonic-gate/*
5677c478bdstevel@tonic-gate * Saves registers associated with PCI capabilities.
5687c478bdstevel@tonic-gate * Returns number of 32 bit words saved.
5697c478bdstevel@tonic-gate * Number of capabilities saved is returned in ncapsp.
5707c478bdstevel@tonic-gate */
5717c478bdstevel@tonic-gatestatic uint32_t
5727c478bdstevel@tonic-gatepci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
5737c478bdstevel@tonic-gate    pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp)
5747c478bdstevel@tonic-gate{
5757c478bdstevel@tonic-gate	return (cap_walk_and_save(confhdl, regbuf, cap_descp, ncapsp, 0));
5767c478bdstevel@tonic-gate}
5777c478bdstevel@tonic-gate
5787c478bdstevel@tonic-gatestatic uint32_t
5797c478bdstevel@tonic-gatecap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf,
5807c478bdstevel@tonic-gate    pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace)
5817c478bdstevel@tonic-gate{
5827c478bdstevel@tonic-gate	pci_cap_entry_t *pci_cap_entp;
583c602bc2yf	uint16_t cap_id, offset, status;
5847c478bdstevel@tonic-gate	uint32_t words_saved = 0, nwords = 0;
5857c478bdstevel@tonic-gate	uint16_t cap_ptr = PCI_CAP_NEXT_PTR_NULL;
586cb7ea99Jimmy Vetayases	uint16_t cap_reg;
5877c478bdstevel@tonic-gate
5887c478bdstevel@tonic-gate	*ncapsp = 0;
589c602bc2yf
590c602bc2yf	/*
591c602bc2yf	 * Determine if it implements capabilities
592c602bc2yf	 */
593c602bc2yf	status = pci_config_get16(confhdl, PCI_CONF_STAT);
594c602bc2yf	if (!(status & 0x10)) {
595c602bc2yf		return (words_saved);
596c602bc2yf	}
597c602bc2yf
5987c478bdstevel@tonic-gate	if (!xspace)
5997c478bdstevel@tonic-gate		cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR);
6007c478bdstevel@tonic-gate	/*
6017c478bdstevel@tonic-gate	 * Walk the capabilities
6027c478bdstevel@tonic-gate	 */
6037c478bdstevel@tonic-gate	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
6047c478bdstevel@tonic-gate		cap_id = CAP_ID(confhdl, cap_ptr, xspace);
605cb7ea99Jimmy Vetayases
6067c478bdstevel@tonic-gate		/* Search for this cap id in our table */
607cb7ea99Jimmy Vetayases		if (!xspace) {
6087c478bdstevel@tonic-gate			pci_cap_entp = pci_cap_table;
609cb7ea99Jimmy Vetayases			cap_reg = pci_config_get16(confhdl,
610cb7ea99Jimmy Vetayases			    cap_ptr + PCI_CAP_ID_REGS_OFF);
611cb7ea99Jimmy Vetayases		}
612cb7ea99Jimmy Vetayases
613cb7ea99Jimmy Vetayases		while (pci_cap_entp->cap_id != PCI_CAP_NEXT_PTR_NULL) {
614cb7ea99Jimmy Vetayases			if (pci_cap_entp->cap_id == cap_id &&
615cb7ea99Jimmy Vetayases			    (cap_reg & pci_cap_entp->cap_mask) ==
616cb7ea99Jimmy Vetayases			    pci_cap_entp->cap_reg)
617cb7ea99Jimmy Vetayases				break;
618cb7ea99Jimmy Vetayases
6197c478bdstevel@tonic-gate			pci_cap_entp++;
620cb7ea99Jimmy Vetayases		}
6217c478bdstevel@tonic-gate
6227c478bdstevel@tonic-gate		offset = cap_ptr;
6237c478bdstevel@tonic-gate		cap_ptr = NEXT_CAP(confhdl, cap_ptr, xspace);
6247c478bdstevel@tonic-gate		/*
6257c478bdstevel@tonic-gate		 * If this cap id is not found in the table, there is nothing
6267c478bdstevel@tonic-gate		 * to save.
6277c478bdstevel@tonic-gate		 */
6287c478bdstevel@tonic-gate		if (pci_cap_entp->cap_id == PCI_CAP_NEXT_PTR_NULL)
6297c478bdstevel@tonic-gate			continue;
6307c478bdstevel@tonic-gate		if (pci_cap_entp->cap_save_func) {
6317c478bdstevel@tonic-gate			if ((nwords = pci_cap_entp->cap_save_func(confhdl,
6327c478bdstevel@tonic-gate			    offset, regbuf, pci_cap_entp->cap_ndwords))) {
6337c478bdstevel@tonic-gate				cap_descp->cap_nregs = nwords;
6347c478bdstevel@tonic-gate				cap_descp->cap_offset = offset;
6357c478bdstevel@tonic-gate				cap_descp->cap_id = cap_id;
6367c478bdstevel@tonic-gate				regbuf += nwords;
6377c478bdstevel@tonic-gate				cap_descp++;
6387c478bdstevel@tonic-gate				words_saved += nwords;
6397c478bdstevel@tonic-gate				(*ncapsp)++;
6407c478bdstevel@tonic-gate			}
6417c478bdstevel@tonic-gate		}
6427c478bdstevel@tonic-gate
6437c478bdstevel@tonic-gate	}
6447c478bdstevel@tonic-gate	return (words_saved);
6457c478bdstevel@tonic-gate}
6467c478bdstevel@tonic-gate
6477c478bdstevel@tonic-gatestatic void
6487c478bdstevel@tonic-gatepci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
6497c478bdstevel@tonic-gate    uint32_t *regbuf, uint32_t nwords)
6507c478bdstevel@tonic-gate{
6517c478bdstevel@tonic-gate	int i;
6527c478bdstevel@tonic-gate
6537c478bdstevel@tonic-gate	for (i = 0; i < nwords; i++) {
6547c478bdstevel@tonic-gate		*regbuf = pci_config_get32(confhdl, cap_ptr);
6557c478bdstevel@tonic-gate		regbuf++;
6567c478bdstevel@tonic-gate		cap_ptr += 4;
6577c478bdstevel@tonic-gate	}
6587c478bdstevel@tonic-gate}
6597c478bdstevel@tonic-gate
6607c478bdstevel@tonic-gatestatic uint32_t
6617c478bdstevel@tonic-gatepci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
6627c478bdstevel@tonic-gate    uint32_t nwords)
6637c478bdstevel@tonic-gate{
6647c478bdstevel@tonic-gate	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
6657c478bdstevel@tonic-gate	return (nwords);
6667c478bdstevel@tonic-gate}
6677c478bdstevel@tonic-gate
6687c478bdstevel@tonic-gate/*ARGSUSED*/
6697c478bdstevel@tonic-gatestatic uint32_t
6707c478bdstevel@tonic-gatepci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
6717c478bdstevel@tonic-gate    uint32_t notused)
6727c478bdstevel@tonic-gate{
6737c478bdstevel@tonic-gate	uint32_t nwords = PCI_MSI_MIN_WORDS;
6747c478bdstevel@tonic-gate	uint16_t msi_ctrl;
6757c478bdstevel@tonic-gate
6767c478bdstevel@tonic-gate	/* Figure out how many registers to be saved */
6777c478bdstevel@tonic-gate	msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL);
6787c478bdstevel@tonic-gate	/* If 64 bit address capable add one word */
6797c478bdstevel@tonic-gate	if (msi_ctrl & PCI_MSI_64BIT_MASK)
6807c478bdstevel@tonic-gate		nwords++;
6817c478bdstevel@tonic-gate	/* If per vector masking capable, add two more words */
6827c478bdstevel@tonic-gate	if (msi_ctrl & PCI_MSI_PVM_MASK)
6837c478bdstevel@tonic-gate		nwords += 2;
6847c478bdstevel@tonic-gate	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
6857c478bdstevel@tonic-gate
6867c478bdstevel@tonic-gate	return (nwords);
6877c478bdstevel@tonic-gate}
6887c478bdstevel@tonic-gate
6897c478bdstevel@tonic-gate/*ARGSUSED*/
6907c478bdstevel@tonic-gatestatic uint32_t
6917c478bdstevel@tonic-gatepci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
6927c478bdstevel@tonic-gate    uint32_t notused)
6937c478bdstevel@tonic-gate{
6947c478bdstevel@tonic-gate	uint32_t nwords = PCI_PCIX_MIN_WORDS;
6957c478bdstevel@tonic-gate	uint16_t pcix_command;
6967c478bdstevel@tonic-gate
6977c478bdstevel@tonic-gate	/* Figure out how many registers to be saved */
6987c478bdstevel@tonic-gate	pcix_command = pci_config_get16(confhdl, cap_ptr + PCI_PCIX_COMMAND);
6997c478bdstevel@tonic-gate	/* If it is version 1 or version 2, add 4 words */
7007c478bdstevel@tonic-gate	if (((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_1) ||
7017c478bdstevel@tonic-gate	    ((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2))
7027c478bdstevel@tonic-gate		nwords += 4;
7037c478bdstevel@tonic-gate	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
7047c478bdstevel@tonic-gate
7057c478bdstevel@tonic-gate	return (nwords);
7067c478bdstevel@tonic-gate}
7077c478bdstevel@tonic-gate
7087c478bdstevel@tonic-gate/*ARGSUSED*/
7097c478bdstevel@tonic-gatestatic uint32_t
7107c478bdstevel@tonic-gatepci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
7117c478bdstevel@tonic-gate    uint32_t notused)
7127c478bdstevel@tonic-gate{
7137c478bdstevel@tonic-gate	return (0);
7147c478bdstevel@tonic-gate}
7157c478bdstevel@tonic-gate
716cb7ea99Jimmy Vetayases/*ARGSUSED*/
717cb7ea99Jimmy Vetayasesstatic uint32_t
718cb7ea99Jimmy Vetayasespci_ht_addrmap_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
719cb7ea99Jimmy Vetayases    uint32_t *regbuf, uint32_t notused)
720cb7ea99Jimmy Vetayases{
721cb7ea99Jimmy Vetayases	uint32_t nwords = 0;
722cb7ea99Jimmy Vetayases	uint16_t reg;
723cb7ea99Jimmy Vetayases
724cb7ea99Jimmy Vetayases	reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
725cb7ea99Jimmy Vetayases
726cb7ea99Jimmy Vetayases	switch ((reg & PCI_HTCAP_ADDRMAP_MAPTYPE_MASK) >>
727cb7ea99Jimmy Vetayases	    PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT) {
728cb7ea99Jimmy Vetayases	case PCI_HTCAP_ADDRMAP_40BIT_ID:
729cb7ea99Jimmy Vetayases		/* HT3.1 spec, ch 7.7, 40-bit dma */
730cb7ea99Jimmy Vetayases		nwords = 3 + ((reg & PCI_HTCAP_ADDRMAP_NUMMAP_MASK) * 2);
731cb7ea99Jimmy Vetayases		break;
732cb7ea99Jimmy Vetayases	case PCI_HTCAP_ADDRMAP_64BIT_ID:
733cb7ea99Jimmy Vetayases		/* HT3.1 spec, ch 7.8, 64-bit dma */
734cb7ea99Jimmy Vetayases		nwords = 4;
735cb7ea99Jimmy Vetayases		break;
736cb7ea99Jimmy Vetayases	default:
737cb7ea99Jimmy Vetayases		nwords = 0;
738cb7ea99Jimmy Vetayases	}
739cb7ea99Jimmy Vetayases
740cb7ea99Jimmy Vetayases	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
741cb7ea99Jimmy Vetayases	return (nwords);
742cb7ea99Jimmy Vetayases}
743cb7ea99Jimmy Vetayases
744cb7ea99Jimmy Vetayases/*ARGSUSED*/
745cb7ea99Jimmy Vetayasesstatic uint32_t
746cb7ea99Jimmy Vetayasespci_ht_funcext_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
747cb7ea99Jimmy Vetayases    uint32_t *regbuf, uint32_t notused)
748cb7ea99Jimmy Vetayases{
749cb7ea99Jimmy Vetayases	uint32_t nwords;
750cb7ea99Jimmy Vetayases	uint16_t reg;
751cb7ea99Jimmy Vetayases
752cb7ea99Jimmy Vetayases	reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
753cb7ea99Jimmy Vetayases
754cb7ea99Jimmy Vetayases	/* HT3.1 spec, ch 7.17 */
755cb7ea99Jimmy Vetayases	nwords = 1 + (reg & PCI_HTCAP_FUNCEXT_LEN_MASK);
756cb7ea99Jimmy Vetayases
757cb7ea99Jimmy Vetayases	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
758cb7ea99Jimmy Vetayases	return (nwords);
759cb7ea99Jimmy Vetayases}
760cb7ea99Jimmy Vetayases
7617c478bdstevel@tonic-gatestatic void
7627c478bdstevel@tonic-gatepci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf,
7637c478bdstevel@tonic-gate    uint16_t pmcap_offset)
7647c478bdstevel@tonic-gate{
7657c478bdstevel@tonic-gate	uint16_t pmcsr;
7667c478bdstevel@tonic-gate	uint16_t pmcsr_offset = pmcap_offset + PCI_PMCSR;
7677c478bdstevel@tonic-gate	uint32_t *saved_pmcsrp = (uint32_t *)((caddr_t)regbuf + PCI_PMCSR);
7687c478bdstevel@tonic-gate
7697c478bdstevel@tonic-gate	/*
7707c478bdstevel@tonic-gate	 * Copy the power state bits from the PMCSR to our saved copy.
7717c478bdstevel@tonic-gate	 * This is to make sure that we don't change the D state when
7727c478bdstevel@tonic-gate	 * we restore config space of the device.
7737c478bdstevel@tonic-gate	 */
7747c478bdstevel@tonic-gate	pmcsr = pci_config_get16(confhdl, pmcsr_offset);
7757c478bdstevel@tonic-gate	(*saved_pmcsrp) &= ~PCI_PMCSR_STATE_MASK;
7767c478bdstevel@tonic-gate	(*saved_pmcsrp) |= (pmcsr & PCI_PMCSR_STATE_MASK);
7777c478bdstevel@tonic-gate}
7787c478bdstevel@tonic-gate
7797c478bdstevel@tonic-gatestatic void
7807c478bdstevel@tonic-gatepci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
7817c478bdstevel@tonic-gate    pci_cap_save_desc_t *cap_descp, uint32_t elements)
7827c478bdstevel@tonic-gate{
7837c478bdstevel@tonic-gate	int i, j;
7847c478bdstevel@tonic-gate	uint16_t offset;
7857c478bdstevel@tonic-gate
7867c478bdstevel@tonic-gate	for (i = 0; i < (elements / sizeof (pci_cap_save_desc_t)); i++) {
7877c478bdstevel@tonic-gate		offset = cap_descp->cap_offset;
7887c478bdstevel@tonic-gate		if (cap_descp->cap_id == PCI_CAP_ID_PM)
7897c478bdstevel@tonic-gate			pci_pmcap_check(confhdl, regbuf, offset);
7907c478bdstevel@tonic-gate		for (j = 0; j < cap_descp->cap_nregs; j++) {
7917c478bdstevel@tonic-gate			pci_config_put32(confhdl, offset, *regbuf);
7927c478bdstevel@tonic-gate			regbuf++;
7937c478bdstevel@tonic-gate			offset += 4;
7947c478bdstevel@tonic-gate		}
7957c478bdstevel@tonic-gate		cap_descp++;
7967c478bdstevel@tonic-gate	}
7977c478bdstevel@tonic-gate}
7987c478bdstevel@tonic-gate
7997c478bdstevel@tonic-gate/*
8007c478bdstevel@tonic-gate * Restore config_regs from a single devinfo node.
8017c478bdstevel@tonic-gate */
8027c478bdstevel@tonic-gateint
8037c478bdstevel@tonic-gatepci_restore_config_regs(dev_info_t *dip)
8047c478bdstevel@tonic-gate{
8057c478bdstevel@tonic-gate	ddi_acc_handle_t confhdl;
8067c478bdstevel@tonic-gate	pci_config_header_state_t *chs_p;
8077c478bdstevel@tonic-gate	pci_cap_save_desc_t *cap_descp;
8087c478bdstevel@tonic-gate	uint32_t elements, i;
8097c478bdstevel@tonic-gate	uint8_t *maskbuf;
8107c478bdstevel@tonic-gate	uint32_t *regbuf, *p;
8117c478bdstevel@tonic-gate	off_t offset = 0;
8127c478bdstevel@tonic-gate
8137c478bdstevel@tonic-gate	if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) {
8147c478bdstevel@tonic-gate		cmn_err(CE_WARN, "%s%d can't get config handle",
8157c478bdstevel@tonic-gate		    ddi_driver_name(dip), ddi_get_instance(dip));
8167c478bdstevel@tonic-gate		return (DDI_FAILURE);
8177c478bdstevel@tonic-gate	}
8187c478bdstevel@tonic-gate
8197c478bdstevel@tonic-gate	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8207c478bdstevel@tonic-gate	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS_MASK,
8217c478bdstevel@tonic-gate	    (uchar_t **)&maskbuf, &elements) == DDI_PROP_SUCCESS) {
8227c478bdstevel@tonic-gate
8237c478bdstevel@tonic-gate		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8247c478bdstevel@tonic-gate		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS,
8257c478bdstevel@tonic-gate		    (uchar_t **)&regbuf, &elements) != DDI_PROP_SUCCESS) {
8267c478bdstevel@tonic-gate			goto restoreconfig_err;
8277c478bdstevel@tonic-gate		}
8287c478bdstevel@tonic-gate		ASSERT(elements == PCIE_CONF_HDR_SIZE);
8297c478bdstevel@tonic-gate		/* pcie device and has 4k config space saved */
8307c478bdstevel@tonic-gate		p = regbuf;
8317c478bdstevel@tonic-gate		for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) {
8327c478bdstevel@tonic-gate			/* If the word is readable then restore it */
8337c478bdstevel@tonic-gate			if (maskbuf[i >> INDEX_SHIFT] &
8347c478bdstevel@tonic-gate			    (uint8_t)(1 << (i & BITMASK)))
8357c478bdstevel@tonic-gate				pci_config_put32(confhdl, offset, *p);
8367c478bdstevel@tonic-gate			p++;
8377c478bdstevel@tonic-gate			offset += sizeof (uint32_t);
8387c478bdstevel@tonic-gate		}
8397c478bdstevel@tonic-gate		ddi_prop_free(regbuf);
8407c478bdstevel@tonic-gate		ddi_prop_free(maskbuf);
8417c478bdstevel@tonic-gate		if (ndi_prop_remove(DDI_DEV_T_NONE, dip,
8427c478bdstevel@tonic-gate		    SAVED_CONFIG_REGS_MASK) != DDI_PROP_SUCCESS) {
8437c478bdstevel@tonic-gate			cmn_err(CE_WARN, "%s%d can't remove prop %s",
8447c478bdstevel@tonic-gate			    ddi_driver_name(dip), ddi_get_instance(dip),
8457c478bdstevel@tonic-gate			    SAVED_CONFIG_REGS_MASK);
8467c478bdstevel@tonic-gate		}
8477c478bdstevel@tonic-gate	} else {
8487c478bdstevel@tonic-gate		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8497c478bdstevel@tonic-gate		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS,
8507c478bdstevel@tonic-gate		    (uchar_t **)&regbuf, &elements) != DDI_PROP_SUCCESS) {
8517c478bdstevel@tonic-gate
8527c478bdstevel@tonic-gate			pci_config_teardown(&confhdl);
853abee707gs			return (DDI_SUCCESS);
8547c478bdstevel@tonic-gate		}
8557c478bdstevel@tonic-gate
8567c478bdstevel@tonic-gate		chs_p = (pci_config_header_state_t *)regbuf;
8577c478bdstevel@tonic-gate		pci_config_put16(confhdl, PCI_CONF_COMM,
8587c478bdstevel@tonic-gate		    chs_p->chs_command);
8597c478bdstevel@tonic-gate		if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) ==
8607c478bdstevel@tonic-gate		    PCI_HEADER_ONE) {
8617c478bdstevel@tonic-gate			pci_config_put16(confhdl, PCI_BCNF_BCNTRL,
8627c478bdstevel@tonic-gate			    chs_p->chs_bridge_control);
8637c478bdstevel@tonic-gate		}
8647c478bdstevel@tonic-gate		pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ,
8657c478bdstevel@tonic-gate		    chs_p->chs_cache_line_size);
8667c478bdstevel@tonic-gate		pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER,
8677c478bdstevel@tonic-gate		    chs_p->chs_latency_timer);
8687c478bdstevel@tonic-gate		if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) ==
8697c478bdstevel@tonic-gate		    PCI_HEADER_ONE)
8707c478bdstevel@tonic-gate			pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER,
8717c478bdstevel@tonic-gate			    chs_p->chs_sec_latency_timer);
8727c478bdstevel@tonic-gate
8737c478bdstevel@tonic-gate		pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0);
8747c478bdstevel@tonic-gate		pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
8757c478bdstevel@tonic-gate		pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2);
8767c478bdstevel@tonic-gate		pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3);
8777c478bdstevel@tonic-gate		pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4);
8787c478bdstevel@tonic-gate		pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5);
8797c478bdstevel@tonic-gate
8807c478bdstevel@tonic-gate		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
8817c478bdstevel@tonic-gate		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
8827c478bdstevel@tonic-gate		    SAVED_CONFIG_REGS_CAPINFO,
8837c478bdstevel@tonic-gate		    (uchar_t **)&cap_descp, &elements) == DDI_PROP_SUCCESS) {
8847c478bdstevel@tonic-gate			/*
8857c478bdstevel@tonic-gate			 * PCI capability related regsiters are saved.
8867c478bdstevel@tonic-gate			 * Restore them based on the description.
8877c478bdstevel@tonic-gate			 */
8887c478bdstevel@tonic-gate			p = (uint32_t *)((caddr_t)regbuf +
8897c478bdstevel@tonic-gate			    sizeof (pci_config_header_state_t));
8907c478bdstevel@tonic-gate			pci_restore_caps(confhdl, p, cap_descp, elements);
8917c478bdstevel@tonic-gate			ddi_prop_free(cap_descp);
8927c478bdstevel@tonic-gate		}
8937c478bdstevel@tonic-gate
8947c478bdstevel@tonic-gate		ddi_prop_free(regbuf);
8957c478bdstevel@tonic-gate	}
8967c478bdstevel@tonic-gate
8977c478bdstevel@tonic-gate	/*
8987c478bdstevel@tonic-gate	 * Make sure registers are flushed
8997c478bdstevel@tonic-gate	 */
9007c478bdstevel@tonic-gate	(void) pci_config_get32(confhdl, PCI_CONF_BASE5);
9017c478bdstevel@tonic-gate
9027c478bdstevel@tonic-gate
9037c478bdstevel@tonic-gate	if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS) !=
9047c478bdstevel@tonic-gate	    DDI_PROP_SUCCESS) {
9057c478bdstevel@tonic-gate		cmn_err(CE_WARN, "%s%d can't remove prop %s",
9067c478bdstevel@tonic-gate		    ddi_driver_name(dip), ddi_get_instance(dip),
9077c478bdstevel@tonic-gate		    SAVED_CONFIG_REGS);
9087c478bdstevel@tonic-gate	}
9097c478bdstevel@tonic-gate
9107c478bdstevel@tonic-gate	pci_config_teardown(&confhdl);
9117c478bdstevel@tonic-gate
9127c478bdstevel@tonic-gate	return (DDI_SUCCESS);
9137c478bdstevel@tonic-gate
9147c478bdstevel@tonic-gaterestoreconfig_err:
9157c478bdstevel@tonic-gate	ddi_prop_free(maskbuf);
9167c478bdstevel@tonic-gate	if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS_MASK) !=
9177c478bdstevel@tonic-gate	    DDI_PROP_SUCCESS) {
9187c478bdstevel@tonic-gate		cmn_err(CE_WARN, "%s%d can't remove prop %s",
9197c478bdstevel@tonic-gate		    ddi_driver_name(dip), ddi_get_instance(dip),
9207c478bdstevel@tonic-gate		    SAVED_CONFIG_REGS_MASK);
9217c478bdstevel@tonic-gate	}
9227c478bdstevel@tonic-gate	pci_config_teardown(&confhdl);
9237c478bdstevel@tonic-gate	return (DDI_FAILURE);
9247c478bdstevel@tonic-gate}
9252df1fe9randyf
9262df1fe9randyf/*ARGSUSED*/
9272df1fe9randyfstatic int
9282df1fe9randyfpci_lookup_pmcap(dev_info_t *dip, ddi_acc_handle_t conf_hdl,
9292df1fe9randyf	uint16_t *pmcap_offsetp)
9302df1fe9randyf{
9312df1fe9randyf	uint8_t cap_ptr;
9322df1fe9randyf	uint8_t cap_id;
9332df1fe9randyf	uint8_t header_type;
9342df1fe9randyf	uint16_t status;
9352df1fe9randyf
9362df1fe9randyf	header_type = pci_config_get8(conf_hdl, PCI_CONF_HEADER);
9372df1fe9randyf	header_type &= PCI_HEADER_TYPE_M;
9382df1fe9randyf
9392df1fe9randyf	/* we don't deal with bridges, etc here */
9402df1fe9randyf	if (header_type != PCI_HEADER_ZERO) {
9412df1fe9randyf		return (DDI_FAILURE);
9422df1fe9randyf	}
9432df1fe9randyf
9442df1fe9randyf	status = pci_config_get16(conf_hdl, PCI_CONF_STAT);
9452df1fe9randyf	if ((status & PCI_STAT_CAP) == 0) {
9462df1fe9randyf		return (DDI_FAILURE);
9472df1fe9randyf	}
9482df1fe9randyf
9492df1fe9randyf	cap_ptr = pci_config_get8(conf_hdl, PCI_CONF_CAP_PTR);
9502df1fe9randyf
9512df1fe9randyf	/*
9522df1fe9randyf	 * Walk the capabilities searching for a PM entry.
9532df1fe9randyf	 */
9542df1fe9randyf	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
9552df1fe9randyf		cap_id = pci_config_get8(conf_hdl, cap_ptr + PCI_CAP_ID);
9562df1fe9randyf		if (cap_id == PCI_CAP_ID_PM) {
9572df1fe9randyf			break;
9582df1fe9randyf		}
9592df1fe9randyf		cap_ptr = pci_config_get8(conf_hdl,
9602df1fe9randyf		    cap_ptr + PCI_CAP_NEXT_PTR);
9612df1fe9randyf	}
9622df1fe9randyf
9632df1fe9randyf	if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) {
9642df1fe9randyf		return (DDI_FAILURE);
9652df1fe9randyf	}
9662df1fe9randyf	*pmcap_offsetp = cap_ptr;
9672df1fe9randyf	return (DDI_SUCCESS);
9682df1fe9randyf}
9692df1fe9randyf
9702df1fe9randyf/*
9712df1fe9randyf * Do common pci-specific suspend actions:
9722df1fe9randyf *  - enable wakeup if appropriate for the device
9732df1fe9randyf *  - put device in lowest D-state that supports wakeup, or D3 if none
9742df1fe9randyf *  - turn off bus mastering in control register
9752df1fe9randyf * For lack of per-dip storage (parent private date is pretty busy)
9762df1fe9randyf * we use properties to store the necessary context
9772df1fe9randyf * To avoid grotting through pci config space on every suspend,
9782df1fe9randyf * we leave the prop in existence after resume, cause we know that
9792df1fe9randyf * the detach framework code will dispose of it for us.
9802df1fe9randyf */
9812df1fe9randyf
9822df1fe9randyftypedef struct pci_pm_context {
9832df1fe9randyf	int		ppc_flags;
9842df1fe9randyf	uint16_t	ppc_cap_offset;	/* offset in config space to pm cap */
9852df1fe9randyf	uint16_t	ppc_pmcsr;	/* need this too */
9862df1fe9randyf	uint16_t	ppc_suspend_level;
9872df1fe9randyf} pci_pm_context_t;
9882df1fe9randyf
9892df1fe9randyf#define	SAVED_PM_CONTEXT	"pci-pm-context"
9902df1fe9randyf
9912df1fe9randyf/* values for ppc_flags	*/
9922df1fe9randyf#define	PPCF_NOPMCAP	1
9932df1fe9randyf
9942df1fe9randyf/*
9952df1fe9randyf * Handle pci-specific suspend processing
9962df1fe9randyf *   PM CSR and PCI CMD are saved by pci_save_config_regs().
9972df1fe9randyf *   If device can wake up system via PME, enable it to do so
9982df1fe9randyf *   Set device power level to lowest that can generate PME, or D3 if none can
9992df1fe9randyf *   Turn off bus master enable in pci command register
10002df1fe9randyf */
10012df1fe9randyf#if defined(__x86)
10022df1fe9randyfextern int acpi_ddi_setwake(dev_info_t *dip, int level);
10032df1fe9randyf#endif
10042df1fe9randyf
10052df1fe9randyfint
10062df1fe9randyfpci_post_suspend(dev_info_t *dip)
10072df1fe9randyf{
10082df1fe9randyf	pci_pm_context_t *p;
1009c6f039cToomas Soome	uint16_t pmcap, pmcsr, pcicmd;
10102df1fe9randyf	uint_t length;
10112df1fe9randyf	int ret;
10122df1fe9randyf	int fromprop = 1;	/* source of memory *p */
10132df1fe9randyf	ddi_acc_handle_t hdl;
10142df1fe9randyf
10152df1fe9randyf	PMD(PMD_SX, ("pci_post_suspend %s:%d\n",
10162df1fe9randyf	    ddi_driver_name(dip), ddi_get_instance(dip)))
10172df1fe9randyf
10182df1fe9randyf	if (pci_save_config_regs(dip) != DDI_SUCCESS) {
10192df1fe9randyf		return (DDI_FAILURE);
10202df1fe9randyf	}
10212df1fe9randyf
10222df1fe9randyf	if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) {
10232df1fe9randyf		return (DDI_FAILURE);
10242df1fe9randyf	}
10252df1fe9randyf
1026c6f039cToomas Soome	pmcsr = 0;
10272df1fe9randyf	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
10282df1fe9randyf	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
10292df1fe9randyf	    SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) {
10302df1fe9randyf		p = (pci_pm_context_t *)kmem_zalloc(sizeof (*p), KM_SLEEP);
10312df1fe9randyf		fromprop = 0;
10322df1fe9randyf		if (pci_lookup_pmcap(dip, hdl,
10332df1fe9randyf		    &p->ppc_cap_offset) != DDI_SUCCESS) {
10342df1fe9randyf			p->ppc_flags |= PPCF_NOPMCAP;
10352df1fe9randyf			ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
10362df1fe9randyf			    SAVED_PM_CONTEXT, (uchar_t *)p,
10372df1fe9randyf			    sizeof (pci_pm_context_t));
10382df1fe9randyf			if (ret != DDI_PROP_SUCCESS) {
10392df1fe9randyf				(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
10402df1fe9randyf				    SAVED_PM_CONTEXT);
10412df1fe9randyf				ret = DDI_FAILURE;
10422df1fe9randyf			} else {
10432df1fe9randyf				ret = DDI_SUCCESS;
10442df1fe9randyf			}
10456f6c7d2Vincent Wang			goto done;
10462df1fe9randyf		}
10472df1fe9randyf		/*
10482df1fe9randyf		 * Upon suspend, set the power level to the lowest that can
10492df1fe9randyf		 * wake the system.  If none can, then set to lowest.
10502df1fe9randyf		 * XXX later we will need to check policy to see if this
10512df1fe9randyf		 * XXX device has had wakeup disabled
10522df1fe9randyf		 */
10532df1fe9randyf		pmcap = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCAP);
10546f6c7d2Vincent Wang		if ((pmcap & (PCI_PMCAP_D3COLD_PME | PCI_PMCAP_D3HOT_PME)) != 0)
10552df1fe9randyf			p->ppc_suspend_level =
10562df1fe9randyf			    (PCI_PMCSR_PME_EN | PCI_PMCSR_D3HOT);
1057ca3c624Hans Rosenfeld		else if ((pmcap & PCI_PMCAP_D2_PME) != 0)
10582df1fe9randyf			p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D2;
10592df1fe9randyf		else if ((pmcap & PCI_PMCAP_D1_PME) != 0)
10602df1fe9randyf			p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D1;
10612df1fe9randyf		else if ((pmcap & PCI_PMCAP_D0_PME) != 0)
10622df1fe9randyf			p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D0;
10632df1fe9randyf		else
10642df1fe9randyf			p->ppc_suspend_level = PCI_PMCSR_D3HOT;
10652df1fe9randyf
10662df1fe9randyf		/*
10672df1fe9randyf		 * we defer updating the property to catch the saved
10682df1fe9randyf		 * register values as well
10692df1fe9randyf		 */
10702df1fe9randyf	}
10712df1fe9randyf	/* If we set this in kmem_zalloc'd memory, we already returned above */
10722df1fe9randyf	if ((p->ppc_flags & PPCF_NOPMCAP) != 0) {
10736f6c7d2Vincent Wang		goto done;
10742df1fe9randyf	}
10752df1fe9randyf
10762df1fe9randyf	pmcsr = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCSR);
10772df1fe9randyf	p->ppc_pmcsr = pmcsr;
10782df1fe9randyf	pmcsr &= (PCI_PMCSR_STATE_MASK);
10792df1fe9randyf	pmcsr |= (PCI_PMCSR_PME_STAT | p->ppc_suspend_level);
10802df1fe9randyf
10812df1fe9randyf	/*
10822df1fe9randyf	 * Push out saved register values
10832df1fe9randyf	 */
10842df1fe9randyf	ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT,
10852df1fe9randyf	    (uchar_t *)p, sizeof (pci_pm_context_t));
10862df1fe9randyf	if (ret == DDI_PROP_SUCCESS) {
10876f6c7d2Vincent Wang		goto done;
10882df1fe9randyf	}
10892df1fe9randyf	/* Failed; put things back the way we found them */
10902df1fe9randyf	(void) pci_restore_config_regs(dip);
10912df1fe9randyf	if (fromprop)
10922df1fe9randyf		ddi_prop_free(p);
10932df1fe9randyf	else
10942df1fe9randyf		kmem_free(p, sizeof (*p));
10952df1fe9randyf	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT);
10962df1fe9randyf	pci_config_teardown(&hdl);
10972df1fe9randyf	return (DDI_FAILURE);
10986f6c7d2Vincent Wang
10996f6c7d2Vincent Wangdone:
11006f6c7d2Vincent Wang
11016f6c7d2Vincent Wang	/*
11026f6c7d2Vincent Wang	 * According to 8.2.2 of "PCI Bus Power Management Interface
11036f6c7d2Vincent Wang	 * Specification Revision 1.2":
11046f6c7d2Vincent Wang	 * "When placing a function into D3, the operating system software is
11056f6c7d2Vincent Wang	 * required to disable I/O and memory space as well as bus mastering via
11066f6c7d2Vincent Wang	 * the PCI Command register."
11076f6c7d2Vincent Wang	 */
11086f6c7d2Vincent Wang
11096f6c7d2Vincent Wang	pcicmd = pci_config_get16(hdl, PCI_CONF_COMM);
11106f6c7d2Vincent Wang	pcicmd &= ~(PCI_COMM_ME|PCI_COMM_MAE|PCI_COMM_IO);
11116f6c7d2Vincent Wang	pci_config_put16(hdl, PCI_CONF_COMM, pcicmd);
11126f6c7d2Vincent Wang
11136f6c7d2Vincent Wang
11146f6c7d2Vincent Wang#if defined(__x86)
1115ca3c624Hans Rosenfeld	if (pci_enable_wakeup &&
1116ca3c624Hans Rosenfeld	    (p->ppc_suspend_level & PCI_PMCSR_PME_EN) != 0) {
1117ca3c624Hans Rosenfeld		ret = acpi_ddi_setwake(dip, 3);
11186f6c7d2Vincent Wang
11196f6c7d2Vincent Wang		if (ret) {
11206f6c7d2Vincent Wang			PMD(PMD_SX, ("pci_post_suspend, setwake %s@%s rets "
11216f6c7d2Vincent Wang			    "%x\n", PM_NAME(dip), PM_ADDR(dip), ret));
11226f6c7d2Vincent Wang		}
11236f6c7d2Vincent Wang	}
1124