1a23fd11yl/*
2a23fd11yl * CDDL HEADER START
3a23fd11yl *
4a23fd11yl * The contents of this file are subject to the terms of the
5a23fd11yl * Common Development and Distribution License (the "License").
6a23fd11yl * You may not use this file except in compliance with the License.
7a23fd11yl *
8a23fd11yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9a23fd11yl * or http://www.opensolaris.org/os/licensing.
10a23fd11yl * See the License for the specific language governing permissions
11a23fd11yl * and limitations under the License.
12a23fd11yl *
13a23fd11yl * When distributing Covered Code, include this CDDL HEADER in each
14a23fd11yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15a23fd11yl * If applicable, add the following below this CDDL HEADER, with the
16a23fd11yl * fields enclosed by brackets "[]" replaced with your own identifying
17a23fd11yl * information: Portions Copyright [yyyy] [name of copyright owner]
18a23fd11yl *
19a23fd11yl * CDDL HEADER END
20a23fd11yl *
218347601yl * Copyright (c) 2002-2006 Neterion, Inc.
22a23fd11yl */
23a23fd11yl
241939740Sherry Moore/*
251939740Sherry Moore * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
261939740Sherry Moore * Use is subject to license terms.
271939740Sherry Moore */
281939740Sherry Moore
29a23fd11yl#include "xgehal-device.h"
30a23fd11yl#include "xgehal-channel.h"
31a23fd11yl#include "xgehal-fifo.h"
32a23fd11yl#include "xgehal-ring.h"
33a23fd11yl#include "xgehal-driver.h"
34a23fd11yl#include "xgehal-mgmt.h"
35a23fd11yl
36a23fd11yl#define SWITCH_SIGN	0xA5A5A5A5A5A5A5A5ULL
37a23fd11yl#define	END_SIGN	0x0
38a23fd11yl
39a23fd11yl#ifdef XGE_HAL_HERC_EMULATION
40a23fd11yl#undef XGE_HAL_PROCESS_LINK_INT_IN_ISR
41a23fd11yl#endif
42a23fd11yl
43a23fd11yl/*
44a23fd11yl * Jenkins hash key length(in bytes)
45a23fd11yl */
46a23fd11yl#define XGE_HAL_JHASH_MSG_LEN 50
47a23fd11yl
48a23fd11yl/*
49a23fd11yl * mix(a,b,c) used in Jenkins hash algorithm
50a23fd11yl */
51a23fd11yl#define mix(a,b,c) { \
52a23fd11yl	a -= b; a -= c; a ^= (c>>13); \
53a23fd11yl	b -= c; b -= a; b ^= (a<<8);  \
54a23fd11yl	c -= a; c -= b; c ^= (b>>13); \
55a23fd11yl	a -= b; a -= c; a ^= (c>>12); \
56a23fd11yl	b -= c; b -= a; b ^= (a<<16); \
57a23fd11yl	c -= a; c -= b; c ^= (b>>5);  \
58a23fd11yl	a -= b; a -= c; a ^= (c>>3);  \
59a23fd11yl	b -= c; b -= a; b ^= (a<<10); \
60a23fd11yl	c -= a; c -= b; c ^= (b>>15); \
61a23fd11yl}
62a23fd11yl
63a23fd11yl
64a23fd11yl/*
65a23fd11yl * __hal_device_event_queued
66a23fd11yl * @data: pointer to xge_hal_device_t structure
67a23fd11yl *
68a23fd11yl * Will be called when new event succesfully queued.
69a23fd11yl */
70a23fd11ylvoid
71a23fd11yl__hal_device_event_queued(void *data, int event_type)
72a23fd11yl{
73a23fd11yl	xge_assert(((xge_hal_device_t*)data)->magic == XGE_HAL_MAGIC);
74a23fd11yl	if (g_xge_hal_driver->uld_callbacks.event_queued) {
75a23fd11yl		g_xge_hal_driver->uld_callbacks.event_queued(data, event_type);
76a23fd11yl	}
77a23fd11yl}
78a23fd11yl
79a23fd11yl/*
80a23fd11yl * __hal_pio_mem_write32_upper
81a23fd11yl *
82a23fd11yl * Endiann-aware implementation of xge_os_pio_mem_write32().
83a23fd11yl * Since Xframe has 64bit registers, we differintiate uppper and lower
84a23fd11yl * parts.
85a23fd11yl */
86a23fd11ylvoid
87a23fd11yl__hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr)
88a23fd11yl{
89a23fd11yl#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
90a23fd11yl	xge_os_pio_mem_write32(pdev, regh, val, addr);
91a23fd11yl#else
92a23fd11yl	xge_os_pio_mem_write32(pdev, regh, val, (void *)((char *)addr + 4));
93a23fd11yl#endif
94a23fd11yl}
95a23fd11yl
96a23fd11yl/*
97a23fd11yl * __hal_pio_mem_write32_upper
98a23fd11yl *
99a23fd11yl * Endiann-aware implementation of xge_os_pio_mem_write32().
100a23fd11yl * Since Xframe has 64bit registers, we differintiate uppper and lower
101a23fd11yl * parts.
102a23fd11yl */
103a23fd11ylvoid
104a23fd11yl__hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
105a23fd11yl                            void *addr)
106a23fd11yl{
107a23fd11yl#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
108a23fd11yl	xge_os_pio_mem_write32(pdev, regh, val,
109a23fd11yl                               (void *) ((char *)addr +	4));
110a23fd11yl#else
111a23fd11yl	xge_os_pio_mem_write32(pdev, regh, val, addr);
112a23fd11yl#endif
113a23fd11yl}
114a23fd11yl
115a23fd11yl/*
116a23fd11yl * __hal_device_register_poll
117a23fd11yl * @hldev: pointer to xge_hal_device_t structure
118a23fd11yl * @reg: register to poll for
119a23fd11yl * @op: 0 - bit reset, 1 - bit set
120a23fd11yl * @mask: mask for logical "and" condition based on %op
121a23fd11yl * @max_millis: maximum time to try to poll in milliseconds
122a23fd11yl *
123a23fd11yl * Will poll certain register for specified amount of time.
124a23fd11yl * Will poll until masked bit is not cleared.
125a23fd11yl */
126a23fd11ylxge_hal_status_e
127a23fd11yl__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg,
128a23fd11yl			   int op, u64 mask, int max_millis)
129a23fd11yl{
130a23fd11yl	u64 val64;
131a23fd11yl	int i = 0;
1328347601yl	xge_hal_status_e ret = XGE_HAL_FAIL;
1338347601yl
1348347601yl	xge_os_udelay(10);
135a23fd11yl
136a23fd11yl	do {
137a23fd11yl		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg);
1388347601yl		if (op == 0 && !(val64 & mask))
1398347601yl			return XGE_HAL_OK;
1408347601yl		else if (op == 1 && (val64 & mask) == mask)
1418347601yl			return XGE_HAL_OK;
1428347601yl		xge_os_udelay(100);
1438347601yl	} while (++i <= 9);
1448347601yl
1458347601yl	do {
1468347601yl		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg);
1478347601yl		if (op == 0 && !(val64 & mask))
1488347601yl			return XGE_HAL_OK;
1498347601yl		else if (op == 1 && (val64 & mask) == mask)
1508347601yl			return XGE_HAL_OK;
1518347601yl		xge_os_udelay(1000);
1528347601yl	} while (++i < max_millis);
153a23fd11yl
154a23fd11yl	return ret;
155a23fd11yl}
156a23fd11yl
157a23fd11yl/*
158a23fd11yl * __hal_device_wait_quiescent
159a23fd11yl * @hldev: the device
160a23fd11yl * @hw_status: hw_status in case of error
161a23fd11yl *
162a23fd11yl * Will wait until device is quiescent for some blocks.
163a23fd11yl */
164a23fd11ylstatic xge_hal_status_e
165a23fd11yl__hal_device_wait_quiescent(xge_hal_device_t *hldev, u64 *hw_status)
166a23fd11yl{
167a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
168a23fd11yl
169a23fd11yl	/* poll and wait first */
170a23fd11yl#ifdef XGE_HAL_HERC_EMULATION
171a23fd11yl	(void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1,
172a23fd11yl			(XGE_HAL_ADAPTER_STATUS_TDMA_READY |
173a23fd11yl			 XGE_HAL_ADAPTER_STATUS_RDMA_READY |
174a23fd11yl			 XGE_HAL_ADAPTER_STATUS_PFC_READY |
175a23fd11yl			 XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY |
176a23fd11yl			 XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT |
177a23fd11yl			 XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY |
178a23fd11yl			 XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY |
179a23fd11yl			 XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK),
180a23fd11yl			 XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS);
181a23fd11yl#else
182a23fd11yl	(void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1,
183a23fd11yl			(XGE_HAL_ADAPTER_STATUS_TDMA_READY |
184a23fd11yl			 XGE_HAL_ADAPTER_STATUS_RDMA_READY |
185a23fd11yl			 XGE_HAL_ADAPTER_STATUS_PFC_READY |
186a23fd11yl			 XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY |
187a23fd11yl			 XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT |
188a23fd11yl			 XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY |
189a23fd11yl			 XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY |
190a23fd11yl			 XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK |
191a23fd11yl			 XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK),
192a23fd11yl			 XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS);
193a23fd11yl#endif
194a23fd11yl
195a23fd11yl	return xge_hal_device_status(hldev, hw_status);
196a23fd11yl}
197a23fd11yl
198a23fd11yl/**
199a23fd11yl * xge_hal_device_is_slot_freeze
2008347601yl * @devh: the device
201a23fd11yl *
202a23fd11yl * Returns non-zero if the slot is freezed.
203a23fd11yl * The determination is made based on the adapter_status
204a23fd11yl * register which will never give all FFs, unless PCI read
205a23fd11yl * cannot go through.
206a23fd11yl */
207a23fd11ylint
208a23fd11ylxge_hal_device_is_slot_freeze(xge_hal_device_h devh)
209a23fd11yl{
210a23fd11yl	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
211a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
212a23fd11yl	u16 device_id;
213a23fd11yl	u64 adapter_status =
214a23fd11yl		xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
215a23fd11yl				      &bar0->adapter_status);
216a23fd11yl	xge_os_pci_read16(hldev->pdev,hldev->cfgh,
217a23fd11yl			xge_offsetof(xge_hal_pci_config_le_t, device_id),
218a23fd11yl			&device_id);
219a23fd11yl#ifdef TX_DEBUG
2208347601yl	if (adapter_status == XGE_HAL_ALL_FOXES)
221a23fd11yl	{
2228347601yl		u64 dummy;
2238347601yl		dummy = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2248347601yl						&bar0->pcc_enable);
2258347601yl		printf(">>> Slot is frozen!\n");
2268347601yl		brkpoint(0);
227a23fd11yl	}
228a23fd11yl#endif
2298347601yl	return((adapter_status == XGE_HAL_ALL_FOXES) || (device_id == 0xffff));
230a23fd11yl}
231a23fd11yl
232a23fd11yl
233a23fd11yl/*
234a23fd11yl * __hal_device_led_actifity_fix
235a23fd11yl * @hldev: pointer to xge_hal_device_t structure
236a23fd11yl *
237a23fd11yl * SXE-002: Configure link and activity LED to turn it off
238a23fd11yl */
239a23fd11ylstatic void
240a23fd11yl__hal_device_led_actifity_fix(xge_hal_device_t *hldev)
241a23fd11yl{
242a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
243a23fd11yl	u16 subid;
244a23fd11yl	u64 val64;
245a23fd11yl
246a23fd11yl	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
247a23fd11yl		xge_offsetof(xge_hal_pci_config_le_t, subsystem_id), &subid);
248a23fd11yl
249a23fd11yl	/*
250a23fd11yl	 *  In the case of Herc, there is a new register named beacon control
251a23fd11yl	 *  is added which was not present in Xena.
252a23fd11yl	 *  Beacon control register in Herc is at the same offset as
253a23fd11yl	 *  gpio control register in Xena.  It means they are one and same in
254a23fd11yl	 *  the case of Xena. Also, gpio control register offset in Herc and
255a23fd11yl	 *  Xena is different.
256a23fd11yl	 *  The current register map represents Herc(It means we have
257a23fd11yl	 *  both beacon  and gpio control registers in register map).
258a23fd11yl	 *  WRT transition from Xena to Herc, all the code in Xena which was
259a23fd11yl	 *  using  gpio control register for LED handling would  have to
260a23fd11yl	 *  use beacon control register in Herc and the rest of the code
261a23fd11yl	 *  which uses gpio control in Xena  would use the same register
262a23fd11yl	 *  in Herc.
263a23fd11yl	 *  WRT LED handling(following code), In the case of Herc, beacon
264a23fd11yl	 *  control register has to be used. This is applicable for Xena also,
265a23fd11yl	 *  since it represents the gpio control register in Xena.
266a23fd11yl	 */
267a23fd11yl	if ((subid & 0xFF) >= 0x07) {
268a23fd11yl		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
269a23fd11yl		                            &bar0->beacon_control);
270a23fd11yl		val64 |= 0x0000800000000000ULL;
271a23fd11yl		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
272a23fd11yl				     val64, &bar0->beacon_control);
273a23fd11yl		val64 = 0x0411040400000000ULL;
274a23fd11yl		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
275a23fd11yl				    (void *) ((u8 *)bar0 + 0x2700));
276a23fd11yl	}
277a23fd11yl}
278a23fd11yl
279a23fd11yl/* Constants for Fixing the MacAddress problem seen mostly on
280a23fd11yl * Alpha machines.
281a23fd11yl */
282a23fd11ylstatic u64 xena_fix_mac[] = {
283a23fd11yl	0x0060000000000000ULL, 0x0060600000000000ULL,
284a23fd11yl	0x0040600000000000ULL, 0x0000600000000000ULL,
285a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
286a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
287a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
288a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
289a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
290a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
291a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
292a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
293a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
294a23fd11yl	0x0020600000000000ULL, 0x0060600000000000ULL,
295a23fd11yl	0x0020600000000000ULL, 0x0000600000000000ULL,
296a23fd11yl	0x0040600000000000ULL, 0x0060600000000000ULL,
297a23fd11yl	END_SIGN
298a23fd11yl};
299a23fd11yl
300a23fd11yl/*
301a23fd11yl * __hal_device_fix_mac
302a23fd11yl * @hldev: HAL device handle.
303a23fd11yl *
304a23fd11yl * Fix for all "FFs" MAC address problems observed on Alpha platforms.
305a23fd11yl */
306a23fd11ylstatic void
307a23fd11yl__hal_device_xena_fix_mac(xge_hal_device_t *hldev)
308a23fd11yl{
309a23fd11yl	int i = 0;
310a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
311a23fd11yl
312a23fd11yl	/*
313a23fd11yl	 *  In the case of Herc, there is a new register named beacon control
314a23fd11yl	 *  is added which was not present in Xena.
315a23fd11yl	 *  Beacon control register in Herc is at the same offset as
316a23fd11yl	 *  gpio control register in Xena.  It means they are one and same in
317a23fd11yl	 *  the case of Xena. Also, gpio control register offset in Herc and
318a23fd11yl	 *  Xena is different.
319a23fd11yl	 *  The current register map represents Herc(It means we have
320a23fd11yl	 *  both beacon  and gpio control registers in register map).
321a23fd11yl	 *  WRT transition from Xena to Herc, all the code in Xena which was
322a23fd11yl	 *  using  gpio control register for LED handling would  have to
323a23fd11yl	 *  use beacon control register in Herc and the rest of the code
324a23fd11yl	 *  which uses gpio control in Xena  would use the same register
325a23fd11yl	 *  in Herc.
326a23fd11yl	 *  In the following code(xena_fix_mac), beacon control register has
327a23fd11yl	 *  to be used in the case of Xena, since it represents gpio control
328a23fd11yl	 *  register. In the case of Herc, there is no change required.
329a23fd11yl	 */
330a23fd11yl	while (xena_fix_mac[i] != END_SIGN) {
331a23fd11yl		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
332a23fd11yl				xena_fix_mac[i++], &bar0->beacon_control);
333a23fd11yl		xge_os_mdelay(1);
334a23fd11yl	}
335a23fd11yl}
336a23fd11yl
337a23fd11yl/*
338a23fd11yl * xge_hal_device_bcast_enable
339a23fd11yl * @hldev: HAL device handle.
340a23fd11yl *
341a23fd11yl * Enable receiving broadcasts.
342a23fd11yl * The host must first write RMAC_CFG_KEY "key"
343a23fd11yl * register, and then - MAC_CFG register.
344a23fd11yl */
345a23fd11ylvoid
346a23fd11ylxge_hal_device_bcast_enable(xge_hal_device_h devh)
347a23fd11yl{
348a23fd11yl	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
349a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
350a23fd11yl	u64 val64;
351a23fd11yl
352a23fd11yl	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
353a23fd11yl	&bar0->mac_cfg);
354a23fd11yl		val64 |= XGE_HAL_MAC_RMAC_BCAST_ENABLE;
355a23fd11yl
356a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
357a23fd11yl		XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
358a23fd11yl
359a23fd11yl    __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
360a23fd11yl		(u32)(val64 >> 32), &bar0->mac_cfg);
361a23fd11yl
3628347601yl	xge_debug_device(XGE_TRACE, "mac_cfg 0x"XGE_OS_LLXFMT": broadcast %s",
363a23fd11yl		(unsigned long long)val64,
364a23fd11yl		hldev->config.mac.rmac_bcast_en ? "enabled" : "disabled");
365a23fd11yl}
366a23fd11yl
367a23fd11yl/*
368a23fd11yl * xge_hal_device_bcast_disable
369a23fd11yl * @hldev: HAL device handle.
370a23fd11yl *
371a23fd11yl * Disable receiving broadcasts.
372a23fd11yl * The host must first write RMAC_CFG_KEY "key"
373a23fd11yl * register, and then - MAC_CFG register.
374a23fd11yl */
375a23fd11ylvoid
376a23fd11ylxge_hal_device_bcast_disable(xge_hal_device_h devh)
377a23fd11yl{
378a23fd11yl	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
379a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
380a23fd11yl	u64 val64;
381a23fd11yl
382a23fd11yl	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
383a23fd11yl	&bar0->mac_cfg);
384a23fd11yl
385a23fd11yl	val64 &= ~(XGE_HAL_MAC_RMAC_BCAST_ENABLE);
386a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
387a23fd11yl		     XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
388a23fd11yl
389a23fd11yl        __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
390a23fd11yl		    (u32)(val64 >> 32), &bar0->mac_cfg);
391a23fd11yl
3928347601yl	xge_debug_device(XGE_TRACE, "mac_cfg 0x"XGE_OS_LLXFMT": broadcast %s",
393a23fd11yl		(unsigned long long)val64,
394a23fd11yl		hldev->config.mac.rmac_bcast_en ? "enabled" : "disabled");
395a23fd11yl}
396a23fd11yl
397a23fd11yl/*
398a23fd11yl * __hal_device_shared_splits_configure
399a23fd11yl * @hldev: HAL device handle.
400a23fd11yl *
401a23fd11yl * TxDMA will stop Read request if the number of read split had exceeded
402a23fd11yl * the limit set by shared_splits
403a23fd11yl */
404a23fd11ylstatic void
405a23fd11yl__hal_device_shared_splits_configure(xge_hal_device_t *hldev)
406a23fd11yl{
407a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
408a23fd11yl	u64 val64;
409a23fd11yl
410a23fd11yl	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
411a23fd11yl	                            &bar0->pic_control);
412a23fd11yl	val64 |=
413a23fd11yl	XGE_HAL_PIC_CNTL_SHARED_SPLITS(hldev->config.shared_splits);
414a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
415a23fd11yl			     &bar0->pic_control);
416a23fd11yl	xge_debug_device(XGE_TRACE, "%s", "shared splits configured");
417a23fd11yl}
418a23fd11yl
419a23fd11yl/*
420a23fd11yl * __hal_device_rmac_padding_configure
421a23fd11yl * @hldev: HAL device handle.
422a23fd11yl *
423a23fd11yl * Configure RMAC frame padding. Depends on configuration, it
424a23fd11yl * can be send to host or removed by MAC.
425a23fd11yl */
426a23fd11ylstatic void
427a23fd11yl__hal_device_rmac_padding_configure(xge_hal_device_t *hldev)
428a23fd11yl{
429a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
430a23fd11yl	u64 val64;
431a23fd11yl
432a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
433a23fd11yl		    XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
434a23fd11yl	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
435a23fd11yl	&bar0->mac_cfg);
436a23fd11yl	val64 &= ( ~XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE );
437a23fd11yl	val64 &= ( ~XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE );
438a23fd11yl	val64 |= XGE_HAL_MAC_CFG_TMAC_APPEND_PAD;
439a23fd11yl
440a23fd11yl	/*
441a23fd11yl	 * If the RTH enable bit is not set, strip the FCS
442a23fd11yl	 */
443a23fd11yl	if (!hldev->config.rth_en ||
444a23fd11yl	    !(xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
445a23fd11yl			   &bar0->rts_rth_cfg) & XGE_HAL_RTS_RTH_EN)) {
446a23fd11yl		val64 |= XGE_HAL_MAC_CFG_RMAC_STRIP_FCS;
447a23fd11yl	}
448a23fd11yl
449a23fd11yl	val64 &= ( ~XGE_HAL_MAC_CFG_RMAC_STRIP_PAD );
450a23fd11yl	val64 |= XGE_HAL_MAC_RMAC_DISCARD_PFRM;
451a23fd11yl
452a23fd11yl	__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
453a23fd11yl		    (u32)(val64 >> 32), (char*)&bar0->mac_cfg);
454a23fd11yl	xge_os_mdelay(1);
455a23fd11yl
456a23fd11yl	xge_debug_device(XGE_TRACE,
4578347601yl		  "mac_cfg 0x"XGE_OS_LLXFMT": frame padding configured",
4588347601yl		  (unsigned long long)val64);
459a23fd11yl}
460a23fd11yl
461a23fd11yl/*
462a23fd11yl * __hal_device_pause_frames_configure
463a23fd11yl * @hldev: HAL device handle.
464a23fd11yl *
465a23fd11yl * Set Pause threshold.
466a23fd11yl *
467a23fd11yl * Pause frame is generated if the amount of data outstanding
468a23fd11yl * on any queue exceeded the ratio of
469a23fd11yl * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
470a23fd11yl */
471a23fd11ylstatic void
472a23fd11yl__hal_device_pause_frames_configure(xge_hal_device_t *hldev)
473a23fd11yl{
474a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
475a23fd11yl	int i;
476a23fd11yl	u64 val64;
477a23fd11yl
478a23fd11yl	switch (hldev->config.mac.media) {
479a23fd11yl		case XGE_HAL_MEDIA_SR:
480a23fd11yl		case XGE_HAL_MEDIA_SW:
481a23fd11yl			val64=0xfffbfffbfffbfffbULL;
482a23fd11yl			break;
483a23fd11yl		case XGE_HAL_MEDIA_LR:
484a23fd11yl		case XGE_HAL_MEDIA_LW:
485a23fd11yl			val64=0xffbbffbbffbbffbbULL;
486a23fd11yl			break;
487a23fd11yl		case XGE_HAL_MEDIA_ER:
488a23fd11yl		case XGE_HAL_MEDIA_EW:
489a23fd11yl		default:
490a23fd11yl			val64=0xffbbffbbffbbffbbULL;
491a23fd11yl			break;
492a23fd11yl	}
493a23fd11yl
494a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
495a23fd11yl			val64, &bar0->mc_pause_thresh_q0q3);
496a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
497a23fd11yl			val64, &bar0->mc_pause_thresh_q4q7);
498a23fd11yl
499a23fd11yl	/* Set the time value  to be inserted in the pause frame generated
500a23fd11yl	 * by Xframe */
501a23fd11yl	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
502a23fd11yl	                            &bar0->rmac_pause_cfg);
503a23fd11yl	if (hldev->config.mac.rmac_pause_gen_en)
504a23fd11yl		val64 |= XGE_HAL_RMAC_PAUSE_GEN_EN;
505a23fd11yl	else
506a23fd11yl		val64 &= ~(XGE_HAL_RMAC_PAUSE_GEN_EN);
507a23fd11yl	if (hldev->config.mac.rmac_pause_rcv_en)
508a23fd11yl		val64 |= XGE_HAL_RMAC_PAUSE_RCV_EN;
509a23fd11yl	else
510a23fd11yl		val64 &= ~(XGE_HAL_RMAC_PAUSE_RCV_EN);
511a23fd11yl	val64 &= ~(XGE_HAL_RMAC_PAUSE_HG_PTIME(0xffff));
512a23fd11yl	val64 |= XGE_HAL_RMAC_PAUSE_HG_PTIME(hldev->config.mac.rmac_pause_time);
513a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
514a23fd11yl			     &bar0->rmac_pause_cfg);
515a23fd11yl
516a23fd11yl	val64 = 0;
517a23fd11yl	for (i = 0; i<4; i++) {
518a23fd11yl		val64 |=
519a23fd11yl		     (((u64)0xFF00|hldev->config.mac.mc_pause_threshold_q0q3)
520a23fd11yl							<<(i*2*8));
521a23fd11yl	}
522a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
523a23fd11yl			     &bar0->mc_pause_thresh_q0q3);
524a23fd11yl
525a23fd11yl	val64 = 0;
526a23fd11yl	for (i = 0; i<4; i++) {
527a23fd11yl		val64 |=
528a23fd11yl		     (((u64)0xFF00|hldev->config.mac.mc_pause_threshold_q4q7)
529a23fd11yl							<<(i*2*8));
530a23fd11yl	}
531a23fd11yl	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
532a23fd11yl			     &bar0->mc_pause_thresh_q4q7);
533a23fd11yl	xge_debug_device(XGE_TRACE, "%s", "pause frames configured");
534a23fd11yl}
535a23fd11yl
536a23fd11yl/*
537a23fd11yl * Herc's clock rate doubled, unless the slot is 33MHz.
538a23fd11yl */
539a23fd11ylunsigned int __hal_fix_time_ival_herc(xge_hal_device_t *hldev,
540a23fd11yl				      unsigned int time_ival)
541a23fd11yl{
542a23fd11yl	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA)
543a23fd11yl		return time_ival;
544a23fd11yl
545a23fd11yl	xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC);
546a23fd11yl
547a23fd11yl	if (hldev->bus_frequency != XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN &&
548a23fd11yl	    hldev->bus_frequency != XGE_HAL_PCI_BUS_FREQUENCY_33MHZ)
549a23fd11yl		time_ival *= 2;
550a23fd11yl
551a23fd11yl	return time_ival;
552a23fd11yl}
553a23fd11yl
554a23fd11yl
555a23fd11yl/*
556a23fd11yl * __hal_device_bus_master_disable
557a23fd11yl * @hldev: HAL device handle.
558a23fd11yl *
559a23fd11yl * Disable bus mastership.
560a23fd11yl */
561a23fd11ylstatic void
562a23fd11yl__hal_device_bus_master_disable (xge_hal_device_t *hldev)
563a23fd11yl{
564a23fd11yl	u16 cmd;
565a23fd11yl	u16 bus_master = 4;
566a23fd11yl
567a23fd11yl	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
568a23fd11yl			xge_offsetof(xge_hal_pci_config_le_t, command), &cmd);
569a23fd11yl	cmd &= ~bus_master;
570a23fd11yl	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
571a23fd11yl			 xge_offsetof(xge_hal_pci_config_le_t, command), cmd);
572a23fd11yl}
573a23fd11yl
574a23fd11yl/*
575a23fd11yl * __hal_device_bus_master_enable
576a23fd11yl * @hldev: HAL device handle.
577a23fd11yl *
578a23fd11yl * Disable bus mastership.
579a23fd11yl */
580a23fd11ylstatic void
581a23fd11yl__hal_device_bus_master_enable (xge_hal_device_t *hldev)
582a23fd11yl{
583a23fd11yl	u16 cmd;
584a23fd11yl	u16 bus_master = 4;
585a23fd11yl
586a23fd11yl	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
587a23fd11yl			xge_offsetof(xge_hal_pci_config_le_t, command), &cmd);
588a23fd11yl
589a23fd11yl	/* already enabled? do nothing */
590a23fd11yl	if (cmd & bus_master)
591a23fd11yl		return;
592a23fd11yl
593a23fd11yl	cmd |= bus_master;
594a23fd11yl	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
595a23fd11yl			 xge_offsetof(xge_hal_pci_config_le_t, command), cmd);
596a23fd11yl}
597a23fd11yl/*
598a23fd11yl * __hal_device_intr_mgmt
599a23fd11yl * @hldev: HAL device handle.
600a23fd11yl * @mask: mask indicating which Intr block must be modified.
601a23fd11yl * @flag: if true - enable, otherwise - disable interrupts.
602a23fd11yl *
603a23fd11yl * Disable or enable device interrupts. Mask is used to specify
604a23fd11yl * which hardware blocks should produce interrupts. For details
605a23fd11yl * please refer to Xframe User Guide.
606a23fd11yl */
607a23fd11ylstatic void
608a23fd11yl__hal_device_intr_mgmt(xge_hal_device_t *hldev, u64 mask, int flag)
609a23fd11yl{
610a23fd11yl	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
611a23fd11yl	u64 val64 = 0, temp64 = 0;
612a23fd11yl	u64 gim, gim_saved;
613a23fd11yl
614a23fd11yl	gim_saved = gim = xge_os_pio_mem_read64(hldev->pdev,
615a23fd11yl                              hldev->regh0, &bar0->general_int_mask);
616a23fd11yl
617a23fd11yl	/* Top level interrupt classification */
618a23fd11yl	/* PIC Interrupts */
619a23fd11yl	if ((mask & (XGE_HAL_TX_PIC_INTR/* | XGE_HAL_RX_PIC_INTR*/))) {
620a23fd11yl		/* Enable PIC Intrs in the general intr mask register */
621a23fd11yl		val64 = XGE_HAL_TXPIC_INT_M/* | XGE_HAL_PIC_RX_INT_M*/;
622a23fd11yl		if (flag) {
623a23fd11yl			gim &= ~((u64) val64);
624a23fd11yl			temp64 = xge_os_pio_mem_read64(hldev->pdev,
625a23fd11yl					hldev->regh0, &bar0->pic_int_mask);
626a23fd11yl
627a23fd11yl			temp64 &= ~XGE_HAL_PIC_INT_TX;
628a23fd11yl#ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
629a23fd11yl			if (xge_hal_device_check_id(hldev) ==
630a23fd11yl							XGE_HAL_CARD_HERC) {
631a23fd11yl				temp64 &= ~XGE_HAL_PIC_INT_MISC;
632a23fd11yl			}
633a23fd11yl#endif
634a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
635a23fd11yl					     temp64, &bar0->pic_int_mask);
636a23fd11yl#ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
637a23fd11yl			if (xge_hal_device_check_id(hldev) ==
638a23fd11yl							XGE_HAL_CARD_HERC) {
639a23fd11yl				/*
640a23fd11yl				 * Unmask only Link Up interrupt
641a23fd11yl				 */
642a23fd11yl				temp64 = xge_os_pio_mem_read64(hldev->pdev,
643a23fd11yl					hldev->regh0, &bar0->misc_int_mask);
644a23fd11yl				temp64 &= ~XGE_HAL_MISC_INT_REG_LINK_UP_INT;
645a23fd11yl				xge_os_pio_mem_write64(hldev->pdev,
646a23fd11yl					      hldev->regh0, temp64,
647a23fd11yl					      &bar0->misc_int_mask);
648a23fd11yl				xge_debug_device(XGE_TRACE,
6498347601yl					"unmask link up flag "XGE_OS_LLXFMT,
650a23fd11yl					(unsigned long long)temp64);
651a23fd11yl			}
652a23fd11yl#endif
653a23fd11yl		} else { /* flag == 0 */
654a23fd11yl
655a23fd11yl#ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
656a23fd11yl			if (xge_hal_device_check_id(hldev) ==
657a23fd11yl							XGE_HAL_CARD_HERC) {
658a23fd11yl				/*
659a23fd11yl				 * Mask both Link Up and Down interrupts
660a23fd11yl				 */
661a23fd11yl				temp64 = xge_os_pio_mem_read64(hldev->pdev,
662a23fd11yl					hldev->regh0, &bar0->misc_int_mask);
663a23fd11yl				temp64 |= XGE_HAL_MISC_INT_REG_LINK_UP_INT;
664a23fd11yl				temp64 |= XGE_HAL_MISC_INT_REG_LINK_DOWN_INT;
665a23fd11yl				xge_os_pio_mem_write64(hldev->pdev,
666a23fd11yl					      hldev->regh0, temp64,
667a23fd11yl					      &bar0->misc_int_mask);
668a23fd11yl				xge_debug_device(XGE_TRACE,
6698347601yl					"mask link up/down flag "XGE_OS_LLXFMT,
670a23fd11yl					(unsigned long long)temp64);
671a23fd11yl			}
672a23fd11yl#endif
673a23fd11yl			/* Disable PIC Intrs in the general intr mask
674a23fd11yl			 * register */
675a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
676a23fd11yl					     XGE_HAL_ALL_INTRS_DIS,
677a23fd11yl			                     &bar0->pic_int_mask);
678a23fd11yl			gim |= val64;
679a23fd11yl		}
680a23fd11yl	}
681a23fd11yl
682a23fd11yl	/*  DMA Interrupts */
683a23fd11yl	/*  Enabling/Disabling Tx DMA interrupts */
684a23fd11yl	if (mask & XGE_HAL_TX_DMA_INTR) {
685a23fd11yl		/*  Enable TxDMA Intrs in the general intr mask register */
686a23fd11yl		val64 = XGE_HAL_TXDMA_INT_M;
687a23fd11yl		if (flag) {
688a23fd11yl			gim &= ~((u64) val64);
6897eced41xw			/* Enable all TxDMA interrupts */
690a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
6917eced41xw					     0x0, &bar0->txdma_int_mask);
692a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
6937eced41xw					     0x0, &bar0->pfc_err_mask);
6947eced41xw			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
6957eced41xw					     0x0, &bar0->tda_err_mask);
6967eced41xw			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
6977eced41xw					     0x0, &bar0->pcc_err_mask);
6987eced41xw			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
6997eced41xw					     0x0, &bar0->tti_err_mask);
7007eced41xw			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
7017eced41xw					     0x0, &bar0->lso_err_mask);
7027eced41xw			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
7037eced41xw					     0x0, &bar0->tpa_err_mask);
7047eced41xw			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
7057eced41xw					     0x0, &bar0->sm_err_mask);
706a23fd11yl
707a23fd11yl		} else { /* flag == 0 */
708a23fd11yl
709a23fd11yl			/*  Disable TxDMA Intrs in the general intr mask
710a23fd11yl			 *  register */
711a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
712a23fd11yl					     XGE_HAL_ALL_INTRS_DIS,
713a23fd11yl			                     &bar0->txdma_int_mask);
714a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
715a23fd11yl					     XGE_HAL_ALL_INTRS_DIS,
716a23fd11yl			                     &bar0->pfc_err_mask);
717a23fd11yl
718a23fd11yl			gim |= val64;
719a23fd11yl		}
720a23fd11yl	}
721a23fd11yl
722a23fd11yl	/*  Enabling/Disabling Rx DMA interrupts */
723a23fd11yl	if (mask & XGE_HAL_RX_DMA_INTR) {
724a23fd11yl		/*  Enable RxDMA Intrs in the general intr mask register */
725a23fd11yl		val64 = XGE_HAL_RXDMA_INT_M;
726a23fd11yl		if (flag) {
727a23fd11yl
728a23fd11yl			gim &= ~((u64) val64);
729a23fd11yl			/* All RxDMA block interrupts are disabled for now
730a23fd11yl			 * TODO */
731a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
732a23fd11yl					     XGE_HAL_ALL_INTRS_DIS,
733a23fd11yl			                     &bar0->rxdma_int_mask);
734a23fd11yl
735a23fd11yl		} else { /* flag == 0 */
736a23fd11yl
737a23fd11yl			/*  Disable RxDMA Intrs in the general intr mask
738a23fd11yl			 *  register */
739a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
740a23fd11yl					     XGE_HAL_ALL_INTRS_DIS,
741a23fd11yl			                     &bar0->rxdma_int_mask);
742a23fd11yl
743a23fd11yl			gim |= val64;
744a23fd11yl		}
745a23fd11yl	}
746a23fd11yl
747a23fd11yl	/*  MAC Interrupts */
748a23fd11yl	/*  Enabling/Disabling MAC interrupts */
749a23fd11yl	if (mask & (XGE_HAL_TX_MAC_INTR | XGE_HAL_RX_MAC_INTR)) {
750a23fd11yl		val64 = XGE_HAL_TXMAC_INT_M | XGE_HAL_RXMAC_INT_M;
751a23fd11yl		if (flag) {
752a23fd11yl
753a23fd11yl			gim &= ~((u64) val64);
754a23fd11yl
755a23fd11yl			/* All MAC block error inter. are disabled for now. */
756a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
757a23fd11yl			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_int_mask);
758a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
759a23fd11yl			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_rmac_err_mask);
760a23fd11yl
761a23fd11yl		} else { /* flag == 0 */
762a23fd11yl
763a23fd11yl			/* Disable MAC Intrs in the general intr mask
764a23fd11yl			 * register */
765a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
766a23fd11yl			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_int_mask);
767a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
768a23fd11yl			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_rmac_err_mask);
769a23fd11yl
770a23fd11yl			gim |= val64;
771a23fd11yl		}
772a23fd11yl	}
773a23fd11yl
774a23fd11yl	/*  XGXS Interrupts */
775a23fd11yl	if (mask & (XGE_HAL_TX_XGXS_INTR | XGE_HAL_RX_XGXS_INTR)) {
776a23fd11yl		val64 = XGE_HAL_TXXGXS_INT_M | XGE_HAL_RXXGXS_INT_M;
777a23fd11yl		if (flag) {
778a23fd11yl
779a23fd11yl			gim &= ~((u64) val64);
780a23fd11yl			/* All XGXS block error interrupts are disabled for now
781a23fd11yl			 * TODO */
782a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
783a23fd11yl			     XGE_HAL_ALL_INTRS_DIS, &bar0->xgxs_int_mask);
784a23fd11yl
785a23fd11yl		} else { /* flag == 0 */
786a23fd11yl
787a23fd11yl			/* Disable MC Intrs in the general intr mask register */
788a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
789a23fd11yl				XGE_HAL_ALL_INTRS_DIS, &bar0->xgxs_int_mask);
790a23fd11yl
791a23fd11yl			gim |= val64;
792a23fd11yl		}
793a23fd11yl	}
794a23fd11yl
795a23fd11yl	/*  Memory Controller(MC) interrupts */
796a23fd11yl	if (mask & XGE_HAL_MC_INTR) {
797a23fd11yl		val64 = XGE_HAL_MC_INT_M;
798a23fd11yl		if (flag) {
799a23fd11yl
800a23fd11yl			gim &= ~((u64) val64);
801a23fd11yl
802a23fd11yl			/* Enable all MC blocks error interrupts */
803a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
804a23fd11yl				     0x0ULL, &bar0->mc_int_mask);
805a23fd11yl
806a23fd11yl		} else { /* flag == 0 */
807a23fd11yl
808a23fd11yl			/* Disable MC Intrs in the general intr mask
809a23fd11yl			 * register */
810a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
811a23fd11yl				     XGE_HAL_ALL_INTRS_DIS, &bar0->mc_int_mask);
812a23fd11yl
813a23fd11yl			gim |= val64;
814a23fd11yl		}
815a23fd11yl	}
816a23fd11yl
817a23fd11yl
818a23fd11yl	/*  Tx traffic interrupts */
819a23fd11yl	if (mask & XGE_HAL_TX_TRAFFIC_INTR) {
820a23fd11yl		val64 = XGE_HAL_TXTRAFFIC_INT_M;
821a23fd11yl		if (flag) {
822a23fd11yl
823a23fd11yl			gim &= ~((u64) val64);
824a23fd11yl
825a23fd11yl			/* Enable all the Tx side interrupts */
826a23fd11yl			/* '0' Enables all 64 TX interrupt levels. */
827a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x0,
828a23fd11yl			                    &bar0->tx_traffic_mask);
829a23fd11yl
830a23fd11yl		} else { /* flag == 0 */
831a23fd11yl
832a23fd11yl			/* Disable Tx Traffic Intrs in the general intr mask
833a23fd11yl			 * register. */
834a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
835a23fd11yl			                     XGE_HAL_ALL_INTRS_DIS,
836a23fd11yl			                     &bar0->tx_traffic_mask);
837a23fd11yl			gim |= val64;
838a23fd11yl		}
839a23fd11yl	}
840a23fd11yl
841a23fd11yl	/*  Rx traffic interrupts */
842a23fd11yl	if (mask & XGE_HAL_RX_TRAFFIC_INTR) {
843a23fd11yl		val64 = XGE_HAL_RXTRAFFIC_INT_M;
844a23fd11yl		if (flag) {
845a23fd11yl			gim &= ~((u64) val64);
846a23fd11yl			/* '0' Enables all 8 RX interrupt levels. */
847a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x0,
848a23fd11yl			                    &bar0->rx_traffic_mask);
849a23fd11yl
850a23fd11yl		} else { /* flag == 0 */
851a23fd11yl
852a23fd11yl			/* Disable Rx Traffic Intrs in the general intr mask
853a23fd11yl			 * register.
854a23fd11yl			 */
855a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
856a23fd11yl			                     XGE_HAL_ALL_INTRS_DIS,
857a23fd11yl			                     &bar0->rx_traffic_mask);
858a23fd11yl
859a23fd11yl			gim |= val64;
860a23fd11yl		}
861a23fd11yl	}
862a23fd11yl
863a23fd11yl	/* Sched Timer interrupt */
864a23fd11yl	if (mask & XGE_HAL_SCHED_INTR) {
865a23fd11yl		if (flag) {
866a23fd11yl			temp64 = xge_os_pio_mem_read64(hldev->pdev,
867a23fd11yl					hldev->regh0, &bar0->txpic_int_mask);
868a23fd11yl			temp64 &= ~XGE_HAL_TXPIC_INT_SCHED_INTR;
869a23fd11yl			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
870a23fd11yl					temp64, &bar0->txpic_int_mask);
871a23fd11yl
872