xref: /illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/xgehal-config.c (revision 8347601bcb0a439f6e50fc36b4039a73d08700e1)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  *
21  * Copyright (c) 2002-2006 Neterion, Inc.
22  */
23 
24 #include "xgehal-config.h"
25 #include "xge-debug.h"
26 
27 /*
28  * __hal_tti_config_check - Check tti configuration
29  * @new_config: tti configuration information
30  *
31  * Returns: XGE_HAL_OK - success,
32  * otherwise one of the xge_hal_status_e{} enumerated error codes.
33  */
34 static xge_hal_status_e
35 __hal_tti_config_check (xge_hal_tti_config_t *new_config)
36 {
37 	if ((new_config->urange_a < XGE_HAL_MIN_TX_URANGE_A) ||
38 		(new_config->urange_a > XGE_HAL_MAX_TX_URANGE_A)) {
39 		return XGE_HAL_BADCFG_TX_URANGE_A;
40 	}
41 
42 	if ((new_config->ufc_a < XGE_HAL_MIN_TX_UFC_A) ||
43 		(new_config->ufc_a > XGE_HAL_MAX_TX_UFC_A)) {
44 		return XGE_HAL_BADCFG_TX_UFC_A;
45 	}
46 
47 	if ((new_config->urange_b < XGE_HAL_MIN_TX_URANGE_B) ||
48 		(new_config->urange_b > XGE_HAL_MAX_TX_URANGE_B)) {
49 		return XGE_HAL_BADCFG_TX_URANGE_B;
50 	}
51 
52 	if ((new_config->ufc_b < XGE_HAL_MIN_TX_UFC_B) ||
53 		(new_config->ufc_b > XGE_HAL_MAX_TX_UFC_B)) {
54 		return XGE_HAL_BADCFG_TX_UFC_B;
55 	}
56 
57 	if ((new_config->urange_c < XGE_HAL_MIN_TX_URANGE_C) ||
58 		(new_config->urange_c > XGE_HAL_MAX_TX_URANGE_C)) {
59 		return XGE_HAL_BADCFG_TX_URANGE_C;
60 	}
61 
62 	if ((new_config->ufc_c < XGE_HAL_MIN_TX_UFC_C) ||
63 		(new_config->ufc_c > XGE_HAL_MAX_TX_UFC_C)) {
64 		return XGE_HAL_BADCFG_TX_UFC_C;
65 	}
66 
67 	if ((new_config->ufc_d < XGE_HAL_MIN_TX_UFC_D) ||
68 		(new_config->ufc_d > XGE_HAL_MAX_TX_UFC_D)) {
69 		return XGE_HAL_BADCFG_TX_UFC_D;
70 	}
71 
72 	if ((new_config->timer_val_us < XGE_HAL_MIN_TX_TIMER_VAL) ||
73 		(new_config->timer_val_us > XGE_HAL_MAX_TX_TIMER_VAL)) {
74 		return XGE_HAL_BADCFG_TX_TIMER_VAL;
75 	}
76 
77 	if ((new_config->timer_ci_en < XGE_HAL_MIN_TX_TIMER_CI_EN) ||
78 		(new_config->timer_ci_en > XGE_HAL_MAX_TX_TIMER_CI_EN)) {
79 		return XGE_HAL_BADCFG_TX_TIMER_CI_EN;
80 	}
81 
82 	if ((new_config->timer_ac_en < XGE_HAL_MIN_TX_TIMER_AC_EN) ||
83 		(new_config->timer_ac_en > XGE_HAL_MAX_TX_TIMER_AC_EN)) {
84 		return XGE_HAL_BADCFG_TX_TIMER_AC_EN;
85 	}
86 
87 	return XGE_HAL_OK;
88 }
89 
90 /*
91  * __hal_rti_config_check - Check rti configuration
92  * @new_config: rti configuration information
93  *
94  * Returns: XGE_HAL_OK - success,
95  * otherwise one of the xge_hal_status_e{} enumerated error codes.
96  */
97 static xge_hal_status_e
98 __hal_rti_config_check (xge_hal_rti_config_t *new_config)
99 {
100 	if ((new_config->urange_a < XGE_HAL_MIN_RX_URANGE_A) ||
101 		(new_config->urange_a > XGE_HAL_MAX_RX_URANGE_A)) {
102 		return XGE_HAL_BADCFG_RX_URANGE_A;
103 	}
104 
105 	if ((new_config->ufc_a < XGE_HAL_MIN_RX_UFC_A) ||
106 		(new_config->ufc_a > XGE_HAL_MAX_RX_UFC_A)) {
107 		return XGE_HAL_BADCFG_RX_UFC_A;
108 	}
109 
110 	if ((new_config->urange_b < XGE_HAL_MIN_RX_URANGE_B) ||
111 		(new_config->urange_b > XGE_HAL_MAX_RX_URANGE_B)) {
112 		return XGE_HAL_BADCFG_RX_URANGE_B;
113 	}
114 
115 	if ((new_config->ufc_b < XGE_HAL_MIN_RX_UFC_B) ||
116 		(new_config->ufc_b > XGE_HAL_MAX_RX_UFC_B)) {
117 		return XGE_HAL_BADCFG_RX_UFC_B;
118 	}
119 
120 	if ((new_config->urange_c < XGE_HAL_MIN_RX_URANGE_C) ||
121 		(new_config->urange_c > XGE_HAL_MAX_RX_URANGE_C)) {
122 		return XGE_HAL_BADCFG_RX_URANGE_C;
123 	}
124 
125 	if ((new_config->ufc_c < XGE_HAL_MIN_RX_UFC_C) ||
126 		(new_config->ufc_c > XGE_HAL_MAX_RX_UFC_C)) {
127 		return XGE_HAL_BADCFG_RX_UFC_C;
128 	}
129 
130 	if ((new_config->ufc_d < XGE_HAL_MIN_RX_UFC_D) ||
131 		(new_config->ufc_d > XGE_HAL_MAX_RX_UFC_D)) {
132 		return XGE_HAL_BADCFG_RX_UFC_D;
133 	}
134 
135 	if ((new_config->timer_val_us < XGE_HAL_MIN_RX_TIMER_VAL) ||
136 		(new_config->timer_val_us > XGE_HAL_MAX_RX_TIMER_VAL)) {
137 		return XGE_HAL_BADCFG_RX_TIMER_VAL;
138 	}
139 
140 	if ((new_config->timer_ac_en < XGE_HAL_MIN_RX_TIMER_AC_EN) ||
141 		(new_config->timer_ac_en > XGE_HAL_MAX_RX_TIMER_AC_EN)) {
142 		return XGE_HAL_BADCFG_RX_TIMER_AC_EN;
143 	}
144 
145 	return XGE_HAL_OK;
146 }
147 
148 
149 /*
150  * __hal_fifo_queue_check - Check fifo queue configuration
151  * @new_config: fifo queue configuration information
152  *
153  * Returns: XGE_HAL_OK - success,
154  * otherwise one of the xge_hal_status_e{} enumerated error codes.
155  */
156 static xge_hal_status_e
157 __hal_fifo_queue_check (xge_hal_fifo_config_t *new_config,
158 			xge_hal_fifo_queue_t *new_queue)
159 {
160 	int i;
161 
162 	if ((new_queue->initial < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) ||
163 		(new_queue->initial > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) {
164 		return XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH;
165 	}
166 
167 	/* FIXME: queue "grow" feature is not supported.
168 	 *        Use "initial" queue size as the "maximum";
169 	 *        Remove the next line when fixed. */
170 	new_queue->max = new_queue->initial;
171 
172 	if ((new_queue->max < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) ||
173 		(new_queue->max > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) {
174 		return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH;
175 	}
176 
177 	if (new_queue->max < new_config->reserve_threshold) {
178 		return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD;
179 	}
180 
181 	if ((new_queue->intr < XGE_HAL_MIN_FIFO_QUEUE_INTR) ||
182 		(new_queue->intr > XGE_HAL_MAX_FIFO_QUEUE_INTR)) {
183 		return XGE_HAL_BADCFG_FIFO_QUEUE_INTR;
184 	}
185 
186 	for(i = 0;  i < XGE_HAL_MAX_FIFO_TTI_NUM; i++) {
187 		/*
188 		 * Validate the tti configuration parameters only if
189 		 * the TTI feature is enabled.
190 		 */
191 		if (new_queue->tti[i].enabled) {
192 			xge_hal_status_e status;
193 
194 			if ((status = __hal_tti_config_check(
195 				     &new_queue->tti[i])) != XGE_HAL_OK) {
196 				return status;
197 			}
198 		}
199 	}
200 
201 	return XGE_HAL_OK;
202 }
203 
204 /*
205  * __hal_ring_queue_check - Check ring queue configuration
206  * @new_config: ring queue configuration information
207  *
208  * Returns: XGE_HAL_OK - success,
209  * otherwise one of the xge_hal_status_e{} enumerated error codes.
210  */
211 static xge_hal_status_e
212 __hal_ring_queue_check (xge_hal_ring_queue_t *new_config)
213 {
214 
215 	if ((new_config->initial < XGE_HAL_MIN_RING_QUEUE_BLOCKS) ||
216 		(new_config->initial > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) {
217 		return XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS;
218 	}
219 
220 	/* FIXME: queue "grow" feature is not supported.
221 	 *        Use "initial" queue size as the "maximum";
222 	 *        Remove the next line when fixed. */
223 	new_config->max = new_config->initial;
224 
225 	if ((new_config->max < XGE_HAL_MIN_RING_QUEUE_BLOCKS) ||
226 		(new_config->max > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) {
227 		return XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS;
228 	}
229 
230 	if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) &&
231 		(new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) &&
232 		(new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) {
233 		return XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE;
234 	}
235 
236         /*
237 	 * Herc has less DRAM; the check is done later inside
238 	 * device_initialize()
239 	 */
240 	if (((new_config->dram_size_mb < XGE_HAL_MIN_RING_QUEUE_SIZE) ||
241 	     (new_config->dram_size_mb > XGE_HAL_MAX_RING_QUEUE_SIZE_XENA)) &&
242 	      new_config->dram_size_mb != XGE_HAL_DEFAULT_USE_HARDCODE)
243 		return XGE_HAL_BADCFG_RING_QUEUE_SIZE;
244 
245 	if ((new_config->backoff_interval_us <
246 			XGE_HAL_MIN_BACKOFF_INTERVAL_US) ||
247 		(new_config->backoff_interval_us >
248 			XGE_HAL_MAX_BACKOFF_INTERVAL_US)) {
249 		return XGE_HAL_BADCFG_BACKOFF_INTERVAL_US;
250 	}
251 
252 	if ((new_config->max_frm_len < XGE_HAL_MIN_MAX_FRM_LEN) ||
253 		(new_config->max_frm_len > XGE_HAL_MAX_MAX_FRM_LEN)) {
254 		return XGE_HAL_BADCFG_MAX_FRM_LEN;
255 	}
256 
257 	if ((new_config->priority < XGE_HAL_MIN_RING_PRIORITY) ||
258 		(new_config->priority > XGE_HAL_MAX_RING_PRIORITY)) {
259 		return XGE_HAL_BADCFG_RING_PRIORITY;
260 	}
261 
262 	if ((new_config->rth_en < XGE_HAL_MIN_RING_RTH_EN) ||
263 		(new_config->rth_en > XGE_HAL_MAX_RING_RTH_EN)) {
264 		return XGE_HAL_BADCFG_RING_RTH_EN;
265 	}
266 
267 	if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_MAC_EN) ||
268 		(new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_MAC_EN)) {
269 		return XGE_HAL_BADCFG_RING_RTS_MAC_EN;
270 	}
271 
272 	if (new_config->indicate_max_pkts <
273 	XGE_HAL_MIN_RING_INDICATE_MAX_PKTS ||
274 	    new_config->indicate_max_pkts >
275 	    XGE_HAL_MAX_RING_INDICATE_MAX_PKTS) {
276 		return XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS;
277 	}
278 
279 	return __hal_rti_config_check(&new_config->rti);
280 }
281 
282 /*
283  * __hal_mac_config_check - Check mac configuration
284  * @new_config: mac configuration information
285  *
286  * Returns: XGE_HAL_OK - success,
287  * otherwise one of the xge_hal_status_e{} enumerated error codes.
288  */
289 static xge_hal_status_e
290 __hal_mac_config_check (xge_hal_mac_config_t *new_config)
291 {
292 	if ((new_config->tmac_util_period < XGE_HAL_MIN_TMAC_UTIL_PERIOD) ||
293 		(new_config->tmac_util_period > XGE_HAL_MAX_TMAC_UTIL_PERIOD)) {
294 		return XGE_HAL_BADCFG_TMAC_UTIL_PERIOD;
295 	}
296 
297 	if ((new_config->rmac_util_period < XGE_HAL_MIN_RMAC_UTIL_PERIOD) ||
298 		(new_config->rmac_util_period > XGE_HAL_MAX_RMAC_UTIL_PERIOD)) {
299 		return XGE_HAL_BADCFG_RMAC_UTIL_PERIOD;
300 	}
301 
302 	if ((new_config->rmac_bcast_en < XGE_HAL_MIN_RMAC_BCAST_EN) ||
303 		(new_config->rmac_bcast_en > XGE_HAL_MAX_RMAC_BCAST_EN)) {
304 		return XGE_HAL_BADCFG_RMAC_BCAST_EN;
305 	}
306 
307 	if ((new_config->rmac_pause_gen_en < XGE_HAL_MIN_RMAC_PAUSE_GEN_EN) ||
308 		(new_config->rmac_pause_gen_en>XGE_HAL_MAX_RMAC_PAUSE_GEN_EN)) {
309 		return XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN;
310 	}
311 
312 	if ((new_config->rmac_pause_rcv_en < XGE_HAL_MIN_RMAC_PAUSE_RCV_EN) ||
313 		(new_config->rmac_pause_rcv_en>XGE_HAL_MAX_RMAC_PAUSE_RCV_EN)) {
314 		return XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN;
315 	}
316 
317 	if ((new_config->rmac_pause_time < XGE_HAL_MIN_RMAC_HIGH_PTIME) ||
318 		(new_config->rmac_pause_time > XGE_HAL_MAX_RMAC_HIGH_PTIME)) {
319 		return XGE_HAL_BADCFG_RMAC_HIGH_PTIME;
320 	}
321 
322 	if ((new_config->media < XGE_HAL_MIN_MEDIA) ||
323 		(new_config->media > XGE_HAL_MAX_MEDIA)) {
324 		return XGE_HAL_BADCFG_MEDIA;
325 	}
326 
327 	if ((new_config->mc_pause_threshold_q0q3 <
328 			XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3) ||
329 		(new_config->mc_pause_threshold_q0q3 >
330 			XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3)) {
331 		return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3;
332 	}
333 
334 	if ((new_config->mc_pause_threshold_q4q7 <
335 			XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7) ||
336 		(new_config->mc_pause_threshold_q4q7 >
337 			XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7)) {
338 		return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7;
339 	}
340 
341 	return XGE_HAL_OK;
342 }
343 
344 /*
345  * __hal_fifo_config_check - Check fifo configuration
346  * @new_config: fifo configuration information
347  *
348  * Returns: XGE_HAL_OK - success,
349  * otherwise one of the xge_hal_status_e{} enumerated error codes.
350  */
351 static xge_hal_status_e
352 __hal_fifo_config_check (xge_hal_fifo_config_t *new_config)
353 {
354 	int i;
355 
356 	/*
357 	 * recompute max_frags to be multiple of 4,
358 	 * which means, multiple of 128 for TxDL
359 	 */
360 	new_config->max_frags = ((new_config->max_frags + 3) >> 2) << 2;
361 
362 	if ((new_config->max_frags < XGE_HAL_MIN_FIFO_FRAGS) ||
363 		(new_config->max_frags > XGE_HAL_MAX_FIFO_FRAGS))  {
364 		return XGE_HAL_BADCFG_FIFO_FRAGS;
365 	}
366 
367 	if ((new_config->reserve_threshold <
368 			XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD) ||
369 		(new_config->reserve_threshold >
370 			XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD)) {
371 		return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD;
372 	}
373 
374 	if ((new_config->memblock_size < XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE) ||
375 		(new_config->memblock_size > XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE)) {
376 		return XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE;
377 	}
378 
379 	for(i = 0;  i < XGE_HAL_MAX_FIFO_NUM; i++) {
380 		xge_hal_status_e status;
381 
382 		if (!new_config->queue[i].configured)
383                         continue;
384 
385 		if ((status = __hal_fifo_queue_check(new_config,
386 				     &new_config->queue[i])) != XGE_HAL_OK) {
387 			return status;
388 		}
389 	}
390 
391 	return XGE_HAL_OK;
392 }
393 
394 /*
395  * __hal_ring_config_check - Check ring configuration
396  * @new_config: Ring configuration information
397  *
398  * Returns: XGE_HAL_OK - success,
399  * otherwise one of the xge_hal_status_e{} enumerated error codes.
400  */
401 static xge_hal_status_e
402 __hal_ring_config_check (xge_hal_ring_config_t *new_config)
403 {
404 	int i;
405 
406 	if ((new_config->memblock_size < XGE_HAL_MIN_RING_MEMBLOCK_SIZE) ||
407 		(new_config->memblock_size > XGE_HAL_MAX_RING_MEMBLOCK_SIZE)) {
408 		return XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE;
409 	}
410 
411 	for(i = 0;  i < XGE_HAL_MAX_RING_NUM; i++) {
412 		xge_hal_status_e status;
413 
414 		if (!new_config->queue[i].configured)
415                         continue;
416 
417 		if ((status = __hal_ring_queue_check(&new_config->queue[i]))
418 					!= XGE_HAL_OK) {
419 			return status;
420 		}
421 	}
422 
423 	return XGE_HAL_OK;
424 }
425 
426 
427 /*
428  * __hal_device_config_check_common - Check device configuration.
429  * @new_config: Device configuration information
430  *
431  * Check part of configuration that is common to
432  * Xframe-I and Xframe-II.
433  *
434  * Returns: XGE_HAL_OK - success,
435  * otherwise one of the xge_hal_status_e{} enumerated error codes.
436  *
437  * See also: __hal_device_config_check_xena().
438  */
439 xge_hal_status_e
440 __hal_device_config_check_common (xge_hal_device_config_t *new_config)
441 {
442 	xge_hal_status_e status;
443 
444 	if ((new_config->mtu < XGE_HAL_MIN_MTU) ||
445 		(new_config->mtu > XGE_HAL_MAX_MTU)) {
446 		return XGE_HAL_BADCFG_MAX_MTU;
447 	}
448 
449 	if ((new_config->bimodal_interrupts < XGE_HAL_BIMODAL_INTR_MIN) ||
450 		(new_config->bimodal_interrupts > XGE_HAL_BIMODAL_INTR_MAX)) {
451 		return XGE_HAL_BADCFG_BIMODAL_INTR;
452 	}
453 
454 	if (new_config->bimodal_interrupts &&
455 	    ((new_config->bimodal_timer_lo_us < XGE_HAL_BIMODAL_TIMER_LO_US_MIN) ||
456 		(new_config->bimodal_timer_lo_us > XGE_HAL_BIMODAL_TIMER_LO_US_MAX))) {
457 		return XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US;
458 	}
459 
460 	if (new_config->bimodal_interrupts &&
461 	    ((new_config->bimodal_timer_hi_us < XGE_HAL_BIMODAL_TIMER_HI_US_MIN) ||
462 		(new_config->bimodal_timer_hi_us > XGE_HAL_BIMODAL_TIMER_HI_US_MAX))) {
463 		return XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US;
464 	}
465 
466 	if ((new_config->no_isr_events < XGE_HAL_NO_ISR_EVENTS_MIN) ||
467 		(new_config->no_isr_events > XGE_HAL_NO_ISR_EVENTS_MAX)) {
468 		return XGE_HAL_BADCFG_NO_ISR_EVENTS;
469 	}
470 
471 	if ((new_config->isr_polling_cnt < XGE_HAL_MIN_ISR_POLLING_CNT) ||
472 		(new_config->isr_polling_cnt > XGE_HAL_MAX_ISR_POLLING_CNT)) {
473 		return XGE_HAL_BADCFG_ISR_POLLING_CNT;
474 	}
475 
476 	if (new_config->latency_timer &&
477 	    new_config->latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) {
478                 if ((new_config->latency_timer < XGE_HAL_MIN_LATENCY_TIMER) ||
479 		    (new_config->latency_timer > XGE_HAL_MAX_LATENCY_TIMER)) {
480                         return XGE_HAL_BADCFG_LATENCY_TIMER;
481 		}
482 	}
483 
484 	if (new_config->max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS)  {
485 		if ((new_config->max_splits_trans <
486 			XGE_HAL_ONE_SPLIT_TRANSACTION) ||
487 		    (new_config->max_splits_trans >
488 			XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION))
489 		return XGE_HAL_BADCFG_MAX_SPLITS_TRANS;
490 	}
491 
492 	if (new_config->mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT)
493 	{
494 	    if ((new_config->mmrb_count < XGE_HAL_MIN_MMRB_COUNT) ||
495 		    (new_config->mmrb_count > XGE_HAL_MAX_MMRB_COUNT)) {
496     		return XGE_HAL_BADCFG_MMRB_COUNT;
497 	    }
498 	}
499 
500 	if ((new_config->shared_splits < XGE_HAL_MIN_SHARED_SPLITS) ||
501 		(new_config->shared_splits > XGE_HAL_MAX_SHARED_SPLITS)) {
502 		return XGE_HAL_BADCFG_SHARED_SPLITS;
503 	}
504 
505 	if (new_config->stats_refresh_time_sec !=
506 	        XGE_HAL_STATS_REFRESH_DISABLE)  {
507 	        if ((new_config->stats_refresh_time_sec <
508 				        XGE_HAL_MIN_STATS_REFRESH_TIME) ||
509 	            (new_config->stats_refresh_time_sec >
510 				        XGE_HAL_MAX_STATS_REFRESH_TIME)) {
511 		        return XGE_HAL_BADCFG_STATS_REFRESH_TIME;
512 	        }
513 	}
514 
515 	if ((new_config->intr_mode != XGE_HAL_INTR_MODE_IRQLINE) &&
516 		(new_config->intr_mode != XGE_HAL_INTR_MODE_MSI) &&
517 		(new_config->intr_mode != XGE_HAL_INTR_MODE_MSIX)) {
518 		return XGE_HAL_BADCFG_INTR_MODE;
519 	}
520 
521 	if ((new_config->sched_timer_us < XGE_HAL_SCHED_TIMER_MIN) ||
522 		(new_config->sched_timer_us > XGE_HAL_SCHED_TIMER_MAX)) {
523 		return XGE_HAL_BADCFG_SCHED_TIMER_US;
524 	}
525 
526 	if ((new_config->sched_timer_one_shot !=
527 			XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE)  &&
528 		(new_config->sched_timer_one_shot !=
529 			XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE)) {
530 		return XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT;
531 	}
532 
533 	/*
534 	 * Check adaptive schema parameters. Note that there are two
535 	 * configuration variables needs to be enabled in ULD:
536 	 *
537 	 *   a) sched_timer_us should not be zero;
538 	 *   b) rxufca_hi_lim should not be equal to rxufca_lo_lim.
539 	 *
540 	 * The code bellow checking for those conditions.
541 	 */
542 	if (new_config->sched_timer_us &&
543 	    new_config->rxufca_hi_lim != new_config->rxufca_lo_lim) {
544 		if ((new_config->rxufca_intr_thres <
545 					XGE_HAL_RXUFCA_INTR_THRES_MIN) ||
546 		    (new_config->rxufca_intr_thres >
547 					XGE_HAL_RXUFCA_INTR_THRES_MAX)) {
548 			return XGE_HAL_BADCFG_RXUFCA_INTR_THRES;
549 		}
550 
551 		if ((new_config->rxufca_hi_lim < XGE_HAL_RXUFCA_HI_LIM_MIN) ||
552 		    (new_config->rxufca_hi_lim > XGE_HAL_RXUFCA_HI_LIM_MAX)) {
553 			return XGE_HAL_BADCFG_RXUFCA_HI_LIM;
554 		}
555 
556 		if ((new_config->rxufca_lo_lim < XGE_HAL_RXUFCA_LO_LIM_MIN) ||
557 		    (new_config->rxufca_lo_lim > XGE_HAL_RXUFCA_LO_LIM_MAX) ||
558 		    (new_config->rxufca_lo_lim > new_config->rxufca_hi_lim)) {
559 			return XGE_HAL_BADCFG_RXUFCA_LO_LIM;
560 		}
561 
562 		if ((new_config->rxufca_lbolt_period <
563 					XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN) ||
564 		    (new_config->rxufca_lbolt_period >
565 					XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX)) {
566 			return XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD;
567 		}
568 	}
569 
570 	if ((new_config->link_valid_cnt < XGE_HAL_LINK_VALID_CNT_MIN) ||
571 		(new_config->link_valid_cnt > XGE_HAL_LINK_VALID_CNT_MAX)) {
572 		return XGE_HAL_BADCFG_LINK_VALID_CNT;
573 	}
574 
575 	if ((new_config->link_retry_cnt < XGE_HAL_LINK_RETRY_CNT_MIN) ||
576 		(new_config->link_retry_cnt > XGE_HAL_LINK_RETRY_CNT_MAX)) {
577 		return XGE_HAL_BADCFG_LINK_RETRY_CNT;
578 	}
579 
580 	if (new_config->link_valid_cnt > new_config->link_retry_cnt)
581 		return XGE_HAL_BADCFG_LINK_VALID_CNT;
582 
583 	if (new_config->link_stability_period != XGE_HAL_DEFAULT_USE_HARDCODE) {
584 	        if ((new_config->link_stability_period <
585 				        XGE_HAL_MIN_LINK_STABILITY_PERIOD) ||
586 		        (new_config->link_stability_period >
587 				        XGE_HAL_MAX_LINK_STABILITY_PERIOD)) {
588 		        return XGE_HAL_BADCFG_LINK_STABILITY_PERIOD;
589 	        }
590 	}
591 
592 	if (new_config->device_poll_millis !=
593 	                XGE_HAL_DEFAULT_USE_HARDCODE)  {
594 	        if ((new_config->device_poll_millis <
595 			        XGE_HAL_MIN_DEVICE_POLL_MILLIS) ||
596 		        (new_config->device_poll_millis >
597 			        XGE_HAL_MAX_DEVICE_POLL_MILLIS)) {
598 		        return XGE_HAL_BADCFG_DEVICE_POLL_MILLIS;
599 	        }
600         }
601 
602 	if ((new_config->rts_qos_steering_config < XGE_HAL_RTS_QOS_STEERING_DISABLE) ||
603 		(new_config->rts_qos_steering_config > XGE_HAL_RTS_QOS_STEERING_ENABLE)) {
604 		return XGE_HAL_BADCFG_RTS_QOS_STEERING_CONFIG;
605 	}
606 
607 #if defined(XGE_HAL_CONFIG_LRO)
608 	if (new_config->lro_sg_size !=
609 				XGE_HAL_DEFAULT_USE_HARDCODE)  {
610 		if ((new_config->lro_sg_size < XGE_HAL_LRO_MIN_SG_SIZE) ||
611 			(new_config->lro_sg_size > XGE_HAL_LRO_MAX_SG_SIZE)) {
612 			return XGE_HAL_BADCFG_LRO_SG_SIZE;
613 		}
614 	}
615 
616 	if (new_config->lro_frm_len !=
617 				XGE_HAL_DEFAULT_USE_HARDCODE)  {
618 		if ((new_config->lro_frm_len < XGE_HAL_LRO_MIN_FRM_LEN) ||
619 			(new_config->lro_frm_len > XGE_HAL_LRO_MAX_FRM_LEN)) {
620 			return XGE_HAL_BADCFG_LRO_FRM_LEN;
621 		}
622 	}
623 #endif
624 
625 	if ((status = __hal_ring_config_check(&new_config->ring))
626 			!= XGE_HAL_OK) {
627 		return status;
628 	}
629 
630 	if ((status = __hal_mac_config_check(&new_config->mac)) !=
631 	    XGE_HAL_OK) {
632 		return status;
633 	}
634 
635 	if ((status = __hal_fifo_config_check(&new_config->fifo)) !=
636 	    XGE_HAL_OK) {
637 		return status;
638 	}
639 
640 	return XGE_HAL_OK;
641 }
642 
643 /*
644  * __hal_device_config_check_xena - Check Xframe-I configuration
645  * @new_config: Device configuration.
646  *
647  * Check part of configuration that is relevant only to Xframe-I.
648  *
649  * Returns: XGE_HAL_OK - success,
650  * otherwise one of the xge_hal_status_e{} enumerated error codes.
651  *
652  * See also: __hal_device_config_check_common().
653  */
654 xge_hal_status_e
655 __hal_device_config_check_xena (xge_hal_device_config_t *new_config)
656 {
657 	if ((new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_33) &&
658 		(new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_66) &&
659 		(new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_100) &&
660 		(new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_133) &&
661 		(new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_266) &&
662 		(new_config->pci_freq_mherz != XGE_HAL_DEFAULT_USE_HARDCODE)) {
663 		return XGE_HAL_BADCFG_PCI_FREQ_MHERZ;
664 	}
665 
666 	return XGE_HAL_OK;
667 }
668 
669 /*
670  * __hal_device_config_check_herc - Check device configuration
671  * @new_config: Device configuration.
672  *
673  * Check part of configuration that is relevant only to Xframe-II.
674  *
675  * Returns: XGE_HAL_OK - success,
676  * otherwise one of the xge_hal_status_e{} enumerated error codes.
677  *
678  * See also: __hal_device_config_check_common().
679  */
680 xge_hal_status_e
681 __hal_device_config_check_herc (xge_hal_device_config_t *new_config)
682 {
683 	return XGE_HAL_OK;
684 }
685 
686 
687 /*
688  * __hal_driver_config_check - Check HAL configuration
689  * @new_config: Driver configuration information
690  *
691  * Returns: XGE_HAL_OK - success,
692  * otherwise one of the xge_hal_status_e{} enumerated error codes.
693  */
694 xge_hal_status_e
695 __hal_driver_config_check (xge_hal_driver_config_t *new_config)
696 {
697 	if ((new_config->queue_size_initial <
698                 XGE_HAL_MIN_QUEUE_SIZE_INITIAL) ||
699 	    (new_config->queue_size_initial >
700                 XGE_HAL_MAX_QUEUE_SIZE_INITIAL)) {
701 		return XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL;
702 	}
703 
704 	if ((new_config->queue_size_max < XGE_HAL_MIN_QUEUE_SIZE_MAX) ||
705 		(new_config->queue_size_max > XGE_HAL_MAX_QUEUE_SIZE_MAX)) {
706 		return XGE_HAL_BADCFG_QUEUE_SIZE_MAX;
707 	}
708 
709 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR
710 	if ((new_config->tracebuf_size < XGE_HAL_MIN_CIRCULAR_ARR) ||
711 		(new_config->tracebuf_size > XGE_HAL_MAX_CIRCULAR_ARR)) {
712 		return XGE_HAL_BADCFG_TRACEBUF_SIZE;
713 	}
714 #endif
715 
716 	return XGE_HAL_OK;
717 }
718