1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002-2005 Neterion, Inc. 24 * All right Reserved. 25 * 26 * FileName : xgehal-types.h 27 * 28 * Description: HAL commonly used types and enumerations 29 * 30 * Created: 19 May 2004 31 */ 32 33 #ifndef XGE_HAL_TYPES_H 34 #define XGE_HAL_TYPES_H 35 36 #include "xge-os-pal.h" 37 38 /* 39 * BIT(loc) - set bit at offset 40 */ 41 #define BIT(loc) (0x8000000000000000ULL >> (loc)) 42 43 /* 44 * vBIT(val, loc, sz) - set bits at offset 45 */ 46 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 47 #define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 48 49 #define XGE_HAL_BASE_INF 100 50 #define XGE_HAL_BASE_ERR 200 51 #define XGE_HAL_BASE_BADCFG 300 52 53 #define XGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL 54 55 /** 56 * enum xge_hal_status_e - HAL return codes. 57 * @XGE_HAL_OK: Success. 58 * @XGE_HAL_FAIL: Failure. 59 * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 60 * (specific to polling mode completion processing). 61 * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 62 * descriptors. See xge_hal_fifo_dtr_next_completed(). 63 * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 64 * descriptors 65 * are reserved (via xge_hal_fifo_dtr_reserve(), 66 * xge_hal_fifo_dtr_reserve()) 67 * and not yet freed (via xge_hal_fifo_dtr_free(), 68 * xge_hal_ring_dtr_free()). 69 * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for 70 * operation. 71 * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 72 * poll until PIO is executed. 73 * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because 74 * HAL and/or device is not yet initialized. 75 * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 76 * reserve. Internal use only. 77 * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 78 * callback when instructed to exit descriptor processing loop 79 * prematurely. Typical usage: polling mode of processing completed 80 * descriptors. 81 * Upon getting LRO_ISED, ll driver shall 82 * 1) initialise lro struct with mbuf if sg_num == 1. 83 * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 84 * append the new mbuf to the tail of mbuf chain in lro struct. 85 * 86 * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 87 * being initiated. 88 * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame 89 * is appended at the end of existing LRO. 90 * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new 91 * frame is not LRO capable. 92 * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame 93 * triggers LRO flush. 94 * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new 95 * frame triggers LRO flush. Lro frame should be flushed first then 96 * new frame should be flushed next. 97 * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 98 * more LRO sessions can be added. 99 * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 100 * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 101 * allocating descriptors). 102 * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this 103 * error if corresponding channel is not configured. 104 * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 105 * invoked not because of the Xframe-generated interrupt. 106 * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 107 * configure more than XGE_HAL_MAX_MAC_ADDRESSES mac addresses. 108 * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 109 * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 110 * in a scatter-gather list. 111 * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 112 * Typically means wrong sequence of API calls. 113 * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 114 * to set Xframe byte swapper in accordnace with the host 115 * endian-ness. 116 * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 117 * a "quiescent" state. 118 * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by 119 * caller is not in the (64, 9600) range. 120 * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 121 * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 122 * check for zero/non-zero only.) 123 * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base 124 * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 125 * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 126 * register value (with offset) outside of the BAR0 space. 127 * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 128 * (passed by ULD) is invalid. 129 * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 130 * management "get" routines when the retrieved information does 131 * not fit into the provided buffer. 132 * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 133 * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 134 * are not compatible. 135 * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 136 * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 137 * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 138 * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 139 * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 140 * SPDM table. 141 * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 142 * synch ith the actual one. 143 * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency, 144 * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register). 145 * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 146 * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR. 147 * Also returned when PIO read does not go through ("all-foxes") 148 * because of "slot-freeze". 149 * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 150 * Returned by xge_hal_device_reset(). One circumstance when it could 151 * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL). 152 * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See 153 * the structure xge_hal_tti_config_t{} for valid values. 154 * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization 155 * range A. See the structure xge_hal_tti_config_t{} for valid values. 156 * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See 157 * the structure xge_hal_tti_config_t{} for valid values. 158 * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization 159 * range B. See the strucuture xge_hal_tti_config_t{} for valid values. 160 * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See 161 * the structure xge_hal_tti_config_t{} for valid values. 162 * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization 163 * range C. See the structure xge_hal_tti_config_t{} for valid values. 164 * @XGE_HAL_BADCFG_TX_URANGE_D: Invalid Tx link utilization range D. See 165 * the structure xge_hal_tti_config_t{} for valid values. 166 * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization 167 * range D. See the structure xge_hal_tti_config_t{} for valid values. 168 * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the 169 * structure xge_hal_tti_config_t{} for valid values. 170 * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt 171 * enable. See the structure xge_hal_tti_config_t{} for valid values. 172 * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See 173 * the structure xge_hal_rti_config_t{} for valid values. 174 * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization 175 * range A. See the structure xge_hal_rti_config_t{} for valid values. 176 * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See 177 * the structure xge_hal_rti_config_t{} for valid values. 178 * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization 179 * range B. See the structure xge_hal_rti_config_t{} for valid values. 180 * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See 181 * the structure xge_hal_rti_config_t{} for valid values. 182 * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization 183 * range C. See the structure xge_hal_rti_config_t{} for valid values. 184 * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization 185 * range D. See the structure xge_hal_rti_config_t{} for valid values. 186 * @XGE_HAL_BADCFG_RX_TIMER_VAL: Invalid Rx timer value. See the 187 * structure xge_hal_rti_config_t{} for valid values. 188 * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue 189 * length. See the structure xge_hal_fifo_queue_t for valid values. 190 * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length. 191 * See the structure xge_hal_fifo_queue_t for valid values. 192 * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode. 193 * See the structure xge_hal_fifo_queue_t for valid values. 194 * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of 195 * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for 196 * valid values. 197 * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD 198 * blocks for the ring. See the structure xge_hal_ring_queue_t for 199 * valid values. 200 * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See 201 * the structure xge_hal_ring_queue_t for valid values. 202 * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the 203 * structure xge_hal_ring_queue_t for valid values. 204 * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval 205 * for the ring. See the structure xge_hal_ring_queue_t for valid values. 206 * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the 207 * structure xge_hal_ring_queue_t for valid values. 208 * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the 209 * structure xge_hal_ring_queue_t for valid values. 210 * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the 211 * structure xge_hal_mac_config_t{} for valid values. 212 * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the 213 * structure xge_hal_mac_config_t{} for valid values. 214 * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the 215 * structure xge_hal_mac_config_t{} for valid values. 216 * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the 217 * structure xge_hal_mac_config_t{} for valid values. 218 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause 219 * frame generation for queues 0 through 3. See the structure 220 * xge_hal_mac_config_t{} for valid values. 221 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause 222 * frame generation for queues 4 through 7. See the structure 223 * xge_hal_mac_config_t{} for valid values. 224 * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See 225 * the structure xge_hal_fifo_config_t{} for valid values. 226 * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve 227 * threshold. See the structure xge_hal_fifo_config_t{} for valid values. 228 * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock 229 * size. See the structure xge_hal_fifo_config_t{} for valid values. 230 * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock 231 * size. See the structure xge_hal_ring_config_t{} for valid values. 232 * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the 233 * structure xge_hal_device_config_t{} for valid values. 234 * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the 235 * structure xge_hal_device_config_t{} for valid values. 236 * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the 237 * structure xge_hal_device_config_t{} for valid values. 238 * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum number of pci-x 239 * split transactions. See the structure xge_hal_device_config_t{} for valid 240 * values. 241 * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count. See the structure 242 * xge_hal_device_config_t{} for valid values. 243 * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split 244 * transactions that is shared by Tx and Rx requests. See the structure 245 * xge_hal_device_config_t{} for valid values. 246 * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for 247 * automatic statistics transfer to the host. See the structure 248 * xge_hal_device_config_t{} for valid values. 249 * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ: Invalid pci clock frequency. See the 250 * structure xge_hal_device_config_t{} for valid values. 251 * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure 252 * xge_hal_device_config_t{} for valid values. 253 * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure 254 * xge_hal_device_config_t{} for valid values. 255 * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to 256 * generate interrupt. See the structure xge_hal_device_config_t{} 257 * for valid values. 258 * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one 259 * shot. See the structure xge_hal_device_config_t{} for valid values. 260 * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial 261 * size. See the structure xge_hal_driver_config_t{} for valid values. 262 * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size. See 263 * the structure xge_hal_driver_config_t{} for valid values. 264 * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See 265 * the structure xge_hal_ring_queue_t for valid values. 266 * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for 267 * indicate_max_pkts variable. 268 * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer 269 * auto-cancel. See xge_hal_tti_config_t{}. 270 * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer 271 * auto-cancel. See xge_hal_rti_config_t{}. 272 * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO 273 * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO 274 * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO 275 * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO 276 * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular 277 * (in memory) trace buffer either too large or too small. See the 278 * the corresponding header file or README for the acceptable range. 279 * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid 280 * counter cannot have the specified value. Note that the link-valid 281 * counting is done only at device-open time, to determine with the 282 * specified certainty that the link is up. See the 283 * the corresponding header file or README for the acceptable range. 284 * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT. 285 * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified 286 * link-up retry count is out of the valid range. Note that the link-up 287 * retry counting is done only at device-open time. 288 * See also xge_hal_device_config_t{}. 289 * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period. 290 * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval. 291 * See the structure xge_hal_device_config_t{} for valid values. 292 * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer. 293 * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace 294 * past the buffer limits. Used to enable user to load the trace in two 295 * or more reads. 296 * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See 297 * the structure xge_hal_ring_queue_t for valid values. 298 * 299 * Enumerates status and error codes returned by HAL public 300 * API functions. 301 */ 302 typedef enum xge_hal_status_e { 303 XGE_HAL_OK = 0, 304 XGE_HAL_FAIL = 1, 305 XGE_HAL_COMPLETIONS_REMAIN = 2, 306 307 XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1, 308 XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, 309 XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, 310 XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, 311 XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, 312 XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, 313 XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, 314 XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, 315 XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, 316 XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, 317 XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, 318 XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, 319 XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 13, 320 321 XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, 322 XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, 323 XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, 324 XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, 325 XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, 326 XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, 327 XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, 328 XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, 329 XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, 330 XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, 331 XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, 332 XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, 333 XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, 334 XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, 335 XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, 336 XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, 337 XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, 338 XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, 339 XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, 340 XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, 341 XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, 342 XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, 343 XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, 344 XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, 345 XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27, 346 XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, 347 XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, 348 XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, 349 350 XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, 351 XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, 352 XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, 353 XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, 354 XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, 355 XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, 356 XGE_HAL_BADCFG_TX_URANGE_D = XGE_HAL_BASE_BADCFG + 7, 357 XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, 358 XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, 359 XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, 360 XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, 361 XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, 362 XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, 363 XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, 364 XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, 365 XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, 366 XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, 367 XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, 368 XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, 369 XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH = XGE_HAL_BASE_BADCFG + 20, 370 XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, 371 XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, 372 XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, 373 XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, 374 XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, 375 XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, 376 XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, 377 XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, 378 XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, 379 XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, 380 XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, 381 XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, 382 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, 383 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, 384 XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, 385 XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, 386 XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, 387 XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, 388 XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, 389 XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, 390 XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, 391 XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, 392 XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, 393 XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, 394 XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, 395 XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, 396 XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, 397 XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, 398 XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, 399 XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, 400 XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, 401 XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, 402 XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, 403 XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, 404 XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, 405 XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, 406 XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, 407 XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, 408 XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, 409 XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, 410 XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, 411 XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, 412 XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, 413 XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, 414 XGE_HAL_BADCFG_DEVICE_POLL_MILLIS = XGE_HAL_BASE_BADCFG + 66, 415 XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, 416 XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, 417 XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, 418 XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, 419 XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, 420 421 XGE_HAL_EOF_TRACE_BUF = -1 422 } xge_hal_status_e; 423 424 #define XGE_HAL_ETH_ALEN 6 425 typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; 426 427 #define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 428 429 /* frames sizes */ 430 #define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 431 #define XGE_HAL_HEADER_802_2_SIZE 3 432 #define XGE_HAL_HEADER_SNAP_SIZE 5 433 #define XGE_HAL_HEADER_VLAN_SIZE 4 434 #define XGE_HAL_MAC_HEADER_MAX_SIZE \ 435 (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ 436 XGE_HAL_HEADER_802_2_SIZE + \ 437 XGE_HAL_HEADER_SNAP_SIZE) 438 439 #define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) 440 441 /* 32bit alignments */ 442 #define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 443 #define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 444 #define XGE_HAL_HEADER_802_2_ALIGN 3 445 #define XGE_HAL_HEADER_SNAP_ALIGN 1 446 447 #define XGE_HAL_L3_CKSUM_OK 0xFFFF 448 #define XGE_HAL_L4_CKSUM_OK 0xFFFF 449 #define XGE_HAL_MIN_MTU 46 450 #define XGE_HAL_MAX_MTU 9600 451 #define XGE_HAL_DEFAULT_MTU 1500 452 453 #define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 454 455 #define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ 456 #define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ 457 458 /* Highest level interrupt blocks */ 459 #define XGE_HAL_TX_PIC_INTR (0x0001<<0) 460 #define XGE_HAL_TX_DMA_INTR (0x0001<<1) 461 #define XGE_HAL_TX_MAC_INTR (0x0001<<2) 462 #define XGE_HAL_TX_XGXS_INTR (0x0001<<3) 463 #define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4) 464 #define XGE_HAL_RX_PIC_INTR (0x0001<<5) 465 #define XGE_HAL_RX_DMA_INTR (0x0001<<6) 466 #define XGE_HAL_RX_MAC_INTR (0x0001<<7) 467 #define XGE_HAL_RX_XGXS_INTR (0x0001<<8) 468 #define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9) 469 #define XGE_HAL_MC_INTR (0x0001<<10) 470 #define XGE_HAL_SCHED_INTR (0x0001<<11) 471 #define XGE_HAL_ALL_INTRS (XGE_HAL_TX_PIC_INTR | \ 472 XGE_HAL_TX_DMA_INTR | \ 473 XGE_HAL_TX_MAC_INTR | \ 474 XGE_HAL_TX_XGXS_INTR | \ 475 XGE_HAL_TX_TRAFFIC_INTR | \ 476 XGE_HAL_RX_PIC_INTR | \ 477 XGE_HAL_RX_DMA_INTR | \ 478 XGE_HAL_RX_MAC_INTR | \ 479 XGE_HAL_RX_XGXS_INTR | \ 480 XGE_HAL_RX_TRAFFIC_INTR | \ 481 XGE_HAL_MC_INTR | \ 482 XGE_HAL_SCHED_INTR) 483 #define XGE_HAL_GEN_MASK_INTR (0x0001<<12) 484 485 /* Interrupt masks for the general interrupt mask register */ 486 #define XGE_HAL_ALL_INTRS_DIS 0xFFFFFFFFFFFFFFFFULL 487 488 #define XGE_HAL_TXPIC_INT_M BIT(0) 489 #define XGE_HAL_TXDMA_INT_M BIT(1) 490 #define XGE_HAL_TXMAC_INT_M BIT(2) 491 #define XGE_HAL_TXXGXS_INT_M BIT(3) 492 #define XGE_HAL_TXTRAFFIC_INT_M BIT(8) 493 #define XGE_HAL_PIC_RX_INT_M BIT(32) 494 #define XGE_HAL_RXDMA_INT_M BIT(33) 495 #define XGE_HAL_RXMAC_INT_M BIT(34) 496 #define XGE_HAL_MC_INT_M BIT(35) 497 #define XGE_HAL_RXXGXS_INT_M BIT(36) 498 #define XGE_HAL_RXTRAFFIC_INT_M BIT(40) 499 500 /* MSI level Interrupts */ 501 #define XGE_HAL_MAX_MSIX_VECTORS (16) 502 503 /* 504 * xge_hal_msix_vector_t 505 * 506 * Represents MSI-X vector. 507 * 508 */ 509 typedef struct xge_hal_msix_vector_t { 510 int idx; 511 int num; 512 void *data; 513 char desc[16]; 514 u64 msi_addr; 515 u64 msi_data; 516 } xge_hal_msix_vector_t; 517 518 519 typedef struct xge_hal_ipv4 { 520 u32 addr; 521 }xge_hal_ipv4; 522 523 typedef struct xge_hal_ipv6 { 524 u64 addr[2]; 525 }xge_hal_ipv6; 526 527 typedef union xge_hal_ipaddr_t { 528 xge_hal_ipv4 ipv4; 529 xge_hal_ipv6 ipv6; 530 }xge_hal_ipaddr_t; 531 532 /* DMA level Interrupts */ 533 #define XGE_HAL_TXDMA_PFC_INT_M BIT(0) 534 535 /* PFC block interrupts */ 536 #define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO 537 full */ 538 539 /* basic handles */ 540 typedef void* xge_hal_device_h; 541 typedef void* xge_hal_dtr_h; 542 typedef void* xge_hal_channel_h; 543 544 /* 545 * I2C device id. Used in I2C control register for accessing EEPROM device 546 * memory. 547 */ 548 #define XGE_DEV_ID 5 549 550 #endif /* XGE_HAL_TYPES_H */ 551