1a23fd118Syl /* 2a23fd118Syl * CDDL HEADER START 3a23fd118Syl * 4a23fd118Syl * The contents of this file are subject to the terms of the 5a23fd118Syl * Common Development and Distribution License (the "License"). 6a23fd118Syl * You may not use this file except in compliance with the License. 7a23fd118Syl * 8a23fd118Syl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9a23fd118Syl * or http://www.opensolaris.org/os/licensing. 10a23fd118Syl * See the License for the specific language governing permissions 11a23fd118Syl * and limitations under the License. 12a23fd118Syl * 13a23fd118Syl * When distributing Covered Code, include this CDDL HEADER in each 14a23fd118Syl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15a23fd118Syl * If applicable, add the following below this CDDL HEADER, with the 16a23fd118Syl * fields enclosed by brackets "[]" replaced with your own identifying 17a23fd118Syl * information: Portions Copyright [yyyy] [name of copyright owner] 18a23fd118Syl * 19a23fd118Syl * CDDL HEADER END 20a23fd118Syl * 218347601bSyl * Copyright (c) 2002-2006 Neterion, Inc. 22a23fd118Syl */ 23a23fd118Syl 24a23fd118Syl #ifndef XGE_HAL_TYPES_H 25a23fd118Syl #define XGE_HAL_TYPES_H 26a23fd118Syl 27a23fd118Syl #include "xge-os-pal.h" 28a23fd118Syl 298347601bSyl __EXTERN_BEGIN_DECLS 308347601bSyl 31a23fd118Syl /* 32a23fd118Syl * BIT(loc) - set bit at offset 33a23fd118Syl */ 34a23fd118Syl #define BIT(loc) (0x8000000000000000ULL >> (loc)) 35a23fd118Syl 36a23fd118Syl /* 37a23fd118Syl * vBIT(val, loc, sz) - set bits at offset 38a23fd118Syl */ 39a23fd118Syl #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 40a23fd118Syl #define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 41a23fd118Syl 428347601bSyl /* 438347601bSyl * bVALx(bits, loc) - Get the value of x bits at location 448347601bSyl */ 458347601bSyl #define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1) 468347601bSyl #define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3) 478347601bSyl #define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7) 488347601bSyl #define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF) 498347601bSyl #define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F) 508347601bSyl #define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F) 518347601bSyl #define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F) 528347601bSyl #define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF) 538347601bSyl #define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF) 54*7eced415Sxw #define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF) 558347601bSyl #define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF) 568347601bSyl #define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF) 578347601bSyl #define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF) 588347601bSyl #define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF) 598347601bSyl #define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF) 608347601bSyl #define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF) 618347601bSyl #define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF) 628347601bSyl #define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF) 638347601bSyl #define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF) 648347601bSyl #define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF) 658347601bSyl #define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF) 668347601bSyl #define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF) 678347601bSyl #define bVAL60(bits, loc) ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF) 688347601bSyl 69a23fd118Syl #define XGE_HAL_BASE_INF 100 70a23fd118Syl #define XGE_HAL_BASE_ERR 200 71a23fd118Syl #define XGE_HAL_BASE_BADCFG 300 72a23fd118Syl 73a23fd118Syl #define XGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL 74a23fd118Syl 75a23fd118Syl /** 76a23fd118Syl * enum xge_hal_status_e - HAL return codes. 77a23fd118Syl * @XGE_HAL_OK: Success. 78a23fd118Syl * @XGE_HAL_FAIL: Failure. 79a23fd118Syl * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 80a23fd118Syl * (specific to polling mode completion processing). 81a23fd118Syl * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 82a23fd118Syl * descriptors. See xge_hal_fifo_dtr_next_completed(). 83a23fd118Syl * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 84a23fd118Syl * descriptors 85a23fd118Syl * are reserved (via xge_hal_fifo_dtr_reserve(), 86a23fd118Syl * xge_hal_fifo_dtr_reserve()) 87a23fd118Syl * and not yet freed (via xge_hal_fifo_dtr_free(), 88a23fd118Syl * xge_hal_ring_dtr_free()). 89a23fd118Syl * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for 90a23fd118Syl * operation. 91a23fd118Syl * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 92a23fd118Syl * poll until PIO is executed. 93a23fd118Syl * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because 94a23fd118Syl * HAL and/or device is not yet initialized. 95a23fd118Syl * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 96a23fd118Syl * reserve. Internal use only. 97a23fd118Syl * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 98a23fd118Syl * callback when instructed to exit descriptor processing loop 99a23fd118Syl * prematurely. Typical usage: polling mode of processing completed 100a23fd118Syl * descriptors. 101a23fd118Syl * Upon getting LRO_ISED, ll driver shall 102a23fd118Syl * 1) initialise lro struct with mbuf if sg_num == 1. 103a23fd118Syl * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 104a23fd118Syl * append the new mbuf to the tail of mbuf chain in lro struct. 105a23fd118Syl * 106a23fd118Syl * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 107a23fd118Syl * being initiated. 108a23fd118Syl * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame 109a23fd118Syl * is appended at the end of existing LRO. 110a23fd118Syl * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new 111a23fd118Syl * frame is not LRO capable. 112a23fd118Syl * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame 113a23fd118Syl * triggers LRO flush. 114a23fd118Syl * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new 115a23fd118Syl * frame triggers LRO flush. Lro frame should be flushed first then 116a23fd118Syl * new frame should be flushed next. 1178347601bSyl * @XGE_HAL_INF_LRO_END_3: Returned by ULD LRO module, when new 1188347601bSyl * frame triggers close of current LRO session and opening of new LRO session 1198347601bSyl * with the frame. 120a23fd118Syl * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 121a23fd118Syl * more LRO sessions can be added. 1228347601bSyl * @XGE_HAL_INF_NOT_ENOUGH_HW_CQES: TBD 123a23fd118Syl * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 124a23fd118Syl * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 125a23fd118Syl * allocating descriptors). 126a23fd118Syl * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this 127a23fd118Syl * error if corresponding channel is not configured. 128a23fd118Syl * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 129a23fd118Syl * invoked not because of the Xframe-generated interrupt. 130a23fd118Syl * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 131a23fd118Syl * configure more than XGE_HAL_MAX_MAC_ADDRESSES mac addresses. 132a23fd118Syl * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 133a23fd118Syl * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 134a23fd118Syl * in a scatter-gather list. 135a23fd118Syl * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 136a23fd118Syl * Typically means wrong sequence of API calls. 137a23fd118Syl * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 138a23fd118Syl * to set Xframe byte swapper in accordnace with the host 139a23fd118Syl * endian-ness. 140a23fd118Syl * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 141a23fd118Syl * a "quiescent" state. 142a23fd118Syl * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by 143a23fd118Syl * caller is not in the (64, 9600) range. 144a23fd118Syl * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 145a23fd118Syl * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 146a23fd118Syl * check for zero/non-zero only.) 147a23fd118Syl * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base 148a23fd118Syl * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 149a23fd118Syl * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 150a23fd118Syl * register value (with offset) outside of the BAR0 space. 151a23fd118Syl * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 152a23fd118Syl * (passed by ULD) is invalid. 153a23fd118Syl * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 154a23fd118Syl * management "get" routines when the retrieved information does 155a23fd118Syl * not fit into the provided buffer. 156a23fd118Syl * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 157a23fd118Syl * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 158a23fd118Syl * are not compatible. 159a23fd118Syl * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 160a23fd118Syl * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 161a23fd118Syl * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 162a23fd118Syl * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 163a23fd118Syl * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 164a23fd118Syl * SPDM table. 165a23fd118Syl * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 166a23fd118Syl * synch ith the actual one. 167a23fd118Syl * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency, 168a23fd118Syl * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register). 169a23fd118Syl * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 170a23fd118Syl * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR. 171a23fd118Syl * Also returned when PIO read does not go through ("all-foxes") 172a23fd118Syl * because of "slot-freeze". 173a23fd118Syl * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 174a23fd118Syl * Returned by xge_hal_device_reset(). One circumstance when it could 175a23fd118Syl * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL). 176*7eced415Sxw * @XGE_HAL_ERR_TOO_MANY: This error is returned if there were laready 177*7eced415Sxw * maximum number of sessions or queues allocated 178*7eced415Sxw * @XGE_HAL_ERR_PKT_DROP: TBD 179a23fd118Syl * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See 180a23fd118Syl * the structure xge_hal_tti_config_t{} for valid values. 181a23fd118Syl * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization 182a23fd118Syl * range A. See the structure xge_hal_tti_config_t{} for valid values. 183a23fd118Syl * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See 184a23fd118Syl * the structure xge_hal_tti_config_t{} for valid values. 185a23fd118Syl * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization 186a23fd118Syl * range B. See the strucuture xge_hal_tti_config_t{} for valid values. 187a23fd118Syl * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See 188a23fd118Syl * the structure xge_hal_tti_config_t{} for valid values. 189a23fd118Syl * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization 190a23fd118Syl * range C. See the structure xge_hal_tti_config_t{} for valid values. 191a23fd118Syl * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization 192a23fd118Syl * range D. See the structure xge_hal_tti_config_t{} for valid values. 193a23fd118Syl * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the 194a23fd118Syl * structure xge_hal_tti_config_t{} for valid values. 195a23fd118Syl * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt 196a23fd118Syl * enable. See the structure xge_hal_tti_config_t{} for valid values. 197a23fd118Syl * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See 198a23fd118Syl * the structure xge_hal_rti_config_t{} for valid values. 199a23fd118Syl * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization 200a23fd118Syl * range A. See the structure xge_hal_rti_config_t{} for valid values. 201a23fd118Syl * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See 202a23fd118Syl * the structure xge_hal_rti_config_t{} for valid values. 203a23fd118Syl * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization 204a23fd118Syl * range B. See the structure xge_hal_rti_config_t{} for valid values. 205a23fd118Syl * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See 206a23fd118Syl * the structure xge_hal_rti_config_t{} for valid values. 207a23fd118Syl * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization 208a23fd118Syl * range C. See the structure xge_hal_rti_config_t{} for valid values. 209a23fd118Syl * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization 210a23fd118Syl * range D. See the structure xge_hal_rti_config_t{} for valid values. 211a23fd118Syl * @XGE_HAL_BADCFG_RX_TIMER_VAL: Invalid Rx timer value. See the 212a23fd118Syl * structure xge_hal_rti_config_t{} for valid values. 213a23fd118Syl * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue 214a23fd118Syl * length. See the structure xge_hal_fifo_queue_t for valid values. 215a23fd118Syl * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length. 216a23fd118Syl * See the structure xge_hal_fifo_queue_t for valid values. 217a23fd118Syl * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode. 218a23fd118Syl * See the structure xge_hal_fifo_queue_t for valid values. 219a23fd118Syl * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of 220a23fd118Syl * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for 221a23fd118Syl * valid values. 222a23fd118Syl * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD 223a23fd118Syl * blocks for the ring. See the structure xge_hal_ring_queue_t for 224a23fd118Syl * valid values. 225a23fd118Syl * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See 226a23fd118Syl * the structure xge_hal_ring_queue_t for valid values. 227a23fd118Syl * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the 228a23fd118Syl * structure xge_hal_ring_queue_t for valid values. 229a23fd118Syl * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval 230a23fd118Syl * for the ring. See the structure xge_hal_ring_queue_t for valid values. 231a23fd118Syl * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the 232a23fd118Syl * structure xge_hal_ring_queue_t for valid values. 233a23fd118Syl * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the 234a23fd118Syl * structure xge_hal_ring_queue_t for valid values. 235a23fd118Syl * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the 236a23fd118Syl * structure xge_hal_mac_config_t{} for valid values. 237a23fd118Syl * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the 238a23fd118Syl * structure xge_hal_mac_config_t{} for valid values. 239a23fd118Syl * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the 240a23fd118Syl * structure xge_hal_mac_config_t{} for valid values. 241a23fd118Syl * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the 242a23fd118Syl * structure xge_hal_mac_config_t{} for valid values. 243a23fd118Syl * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause 244a23fd118Syl * frame generation for queues 0 through 3. See the structure 245a23fd118Syl * xge_hal_mac_config_t{} for valid values. 246a23fd118Syl * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause 247a23fd118Syl * frame generation for queues 4 through 7. See the structure 248a23fd118Syl * xge_hal_mac_config_t{} for valid values. 249a23fd118Syl * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See 250a23fd118Syl * the structure xge_hal_fifo_config_t{} for valid values. 251a23fd118Syl * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve 252a23fd118Syl * threshold. See the structure xge_hal_fifo_config_t{} for valid values. 253a23fd118Syl * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock 254a23fd118Syl * size. See the structure xge_hal_fifo_config_t{} for valid values. 255a23fd118Syl * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock 256a23fd118Syl * size. See the structure xge_hal_ring_config_t{} for valid values. 257a23fd118Syl * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the 258a23fd118Syl * structure xge_hal_device_config_t{} for valid values. 259a23fd118Syl * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the 260a23fd118Syl * structure xge_hal_device_config_t{} for valid values. 261a23fd118Syl * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the 262a23fd118Syl * structure xge_hal_device_config_t{} for valid values. 263a23fd118Syl * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum number of pci-x 264a23fd118Syl * split transactions. See the structure xge_hal_device_config_t{} for valid 265a23fd118Syl * values. 266a23fd118Syl * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count. See the structure 267a23fd118Syl * xge_hal_device_config_t{} for valid values. 268a23fd118Syl * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split 269a23fd118Syl * transactions that is shared by Tx and Rx requests. See the structure 270a23fd118Syl * xge_hal_device_config_t{} for valid values. 271a23fd118Syl * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for 272a23fd118Syl * automatic statistics transfer to the host. See the structure 273a23fd118Syl * xge_hal_device_config_t{} for valid values. 274a23fd118Syl * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ: Invalid pci clock frequency. See the 275a23fd118Syl * structure xge_hal_device_config_t{} for valid values. 276a23fd118Syl * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure 277a23fd118Syl * xge_hal_device_config_t{} for valid values. 278a23fd118Syl * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure 279a23fd118Syl * xge_hal_device_config_t{} for valid values. 280a23fd118Syl * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to 281a23fd118Syl * generate interrupt. See the structure xge_hal_device_config_t{} 282a23fd118Syl * for valid values. 283a23fd118Syl * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one 284a23fd118Syl * shot. See the structure xge_hal_device_config_t{} for valid values. 285a23fd118Syl * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial 286a23fd118Syl * size. See the structure xge_hal_driver_config_t{} for valid values. 287a23fd118Syl * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size. See 288a23fd118Syl * the structure xge_hal_driver_config_t{} for valid values. 289a23fd118Syl * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See 290a23fd118Syl * the structure xge_hal_ring_queue_t for valid values. 291a23fd118Syl * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for 292a23fd118Syl * indicate_max_pkts variable. 293a23fd118Syl * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer 294a23fd118Syl * auto-cancel. See xge_hal_tti_config_t{}. 295a23fd118Syl * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer 296a23fd118Syl * auto-cancel. See xge_hal_rti_config_t{}. 297a23fd118Syl * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO 298a23fd118Syl * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO 299a23fd118Syl * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO 300a23fd118Syl * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO 301a23fd118Syl * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular 302a23fd118Syl * (in memory) trace buffer either too large or too small. See the 303a23fd118Syl * the corresponding header file or README for the acceptable range. 304a23fd118Syl * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid 305a23fd118Syl * counter cannot have the specified value. Note that the link-valid 306a23fd118Syl * counting is done only at device-open time, to determine with the 307a23fd118Syl * specified certainty that the link is up. See the 308a23fd118Syl * the corresponding header file or README for the acceptable range. 309a23fd118Syl * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT. 310a23fd118Syl * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified 311a23fd118Syl * link-up retry count is out of the valid range. Note that the link-up 312a23fd118Syl * retry counting is done only at device-open time. 313a23fd118Syl * See also xge_hal_device_config_t{}. 314a23fd118Syl * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period. 315a23fd118Syl * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval. 3168347601bSyl * @XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN: TBD 3178347601bSyl * @XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN: TBD 3188347601bSyl * @XGE_HAL_BADCFG_MEDIA: TBD 3198347601bSyl * @XGE_HAL_BADCFG_NO_ISR_EVENTS: TBD 320a23fd118Syl * See the structure xge_hal_device_config_t{} for valid values. 321a23fd118Syl * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer. 322a23fd118Syl * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace 323a23fd118Syl * past the buffer limits. Used to enable user to load the trace in two 324a23fd118Syl * or more reads. 325a23fd118Syl * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See 326a23fd118Syl * the structure xge_hal_ring_queue_t for valid values. 3278347601bSyl * @XGE_HAL_BADCFG_LRO_SG_SIZE : Invalid value of LRO scatter gatter size. 3288347601bSyl * See the structure xge_hal_device_config_t for valid values. 3298347601bSyl * @XGE_HAL_BADCFG_LRO_FRM_LEN : Invalid value of LRO frame length. 3308347601bSyl * See the structure xge_hal_device_config_t for valid values. 3318347601bSyl * @XGE_HAL_BADCFG_WQE_NUM_ODS: TBD 3328347601bSyl * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts 333a23fd118Syl * Enumerates status and error codes returned by HAL public 334a23fd118Syl * API functions. 335*7eced415Sxw * @XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US: TBD 336*7eced415Sxw * @XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US: TBD 337*7eced415Sxw * @XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED: TBD 338*7eced415Sxw * @XGE_HAL_BADCFG_RTS_QOS_EN: TBD 339*7eced415Sxw * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR: TBD 340*7eced415Sxw * @XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR: TBD 341*7eced415Sxw * @XGE_HAL_BADCFG_RTS_PORT_EN: TBD 342*7eced415Sxw * @XGE_HAL_BADCFG_RING_RTS_PORT_EN: TBD 343*7eced415Sxw * 344a23fd118Syl */ 345a23fd118Syl typedef enum xge_hal_status_e { 346a23fd118Syl XGE_HAL_OK = 0, 347a23fd118Syl XGE_HAL_FAIL = 1, 348a23fd118Syl XGE_HAL_COMPLETIONS_REMAIN = 2, 349a23fd118Syl 350a23fd118Syl XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1, 351a23fd118Syl XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, 352a23fd118Syl XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, 353a23fd118Syl XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, 354a23fd118Syl XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, 355a23fd118Syl XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, 356a23fd118Syl XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, 357a23fd118Syl XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, 358a23fd118Syl XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, 359a23fd118Syl XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, 360a23fd118Syl XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, 361a23fd118Syl XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, 3628347601bSyl XGE_HAL_INF_LRO_END_3 = XGE_HAL_BASE_INF + 13, 3638347601bSyl XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 14, 3648347601bSyl XGE_HAL_INF_NOT_ENOUGH_HW_CQES = XGE_HAL_BASE_INF + 15, 365a23fd118Syl XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, 366a23fd118Syl XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, 367a23fd118Syl XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, 368a23fd118Syl XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, 369a23fd118Syl XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, 370a23fd118Syl XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, 371a23fd118Syl XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, 372a23fd118Syl XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, 373a23fd118Syl XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, 374a23fd118Syl XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, 375a23fd118Syl XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, 376a23fd118Syl XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, 377a23fd118Syl XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, 378a23fd118Syl XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, 379a23fd118Syl XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, 380a23fd118Syl XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, 381a23fd118Syl XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, 382a23fd118Syl XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, 383a23fd118Syl XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, 384a23fd118Syl XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, 385a23fd118Syl XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, 386a23fd118Syl XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, 387a23fd118Syl XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, 388a23fd118Syl XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, 389a23fd118Syl XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27, 390a23fd118Syl XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, 391a23fd118Syl XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, 392a23fd118Syl XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, 3938347601bSyl XGE_HAL_ERR_TOO_MANY = XGE_HAL_BASE_ERR + 32, 394*7eced415Sxw XGE_HAL_ERR_PKT_DROP = XGE_HAL_BASE_ERR + 33, 395a23fd118Syl 396a23fd118Syl XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, 397a23fd118Syl XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, 398a23fd118Syl XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, 399a23fd118Syl XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, 400a23fd118Syl XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, 401a23fd118Syl XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, 402a23fd118Syl XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, 403a23fd118Syl XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, 404a23fd118Syl XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, 405a23fd118Syl XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, 406a23fd118Syl XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, 407a23fd118Syl XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, 408a23fd118Syl XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, 409a23fd118Syl XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, 410a23fd118Syl XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, 411a23fd118Syl XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, 412a23fd118Syl XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, 413a23fd118Syl XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, 414a23fd118Syl XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH = XGE_HAL_BASE_BADCFG + 20, 415a23fd118Syl XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, 416a23fd118Syl XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, 417a23fd118Syl XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, 418a23fd118Syl XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, 419a23fd118Syl XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, 420a23fd118Syl XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, 421a23fd118Syl XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, 422a23fd118Syl XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, 423a23fd118Syl XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, 424a23fd118Syl XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, 425a23fd118Syl XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, 426a23fd118Syl XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, 427a23fd118Syl XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, 428a23fd118Syl XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, 429a23fd118Syl XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, 430a23fd118Syl XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, 431a23fd118Syl XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, 432a23fd118Syl XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, 433a23fd118Syl XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, 434a23fd118Syl XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, 435a23fd118Syl XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, 436a23fd118Syl XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, 437a23fd118Syl XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, 438a23fd118Syl XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, 439a23fd118Syl XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, 440a23fd118Syl XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, 441a23fd118Syl XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, 442a23fd118Syl XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, 443a23fd118Syl XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, 444a23fd118Syl XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, 445a23fd118Syl XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, 446a23fd118Syl XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, 447a23fd118Syl XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, 448a23fd118Syl XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, 449a23fd118Syl XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, 450a23fd118Syl XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, 451a23fd118Syl XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, 452a23fd118Syl XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, 453a23fd118Syl XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, 454a23fd118Syl XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, 455a23fd118Syl XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, 456a23fd118Syl XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, 457a23fd118Syl XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, 458a23fd118Syl XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, 459a23fd118Syl XGE_HAL_BADCFG_DEVICE_POLL_MILLIS = XGE_HAL_BASE_BADCFG + 66, 460a23fd118Syl XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, 461a23fd118Syl XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, 462a23fd118Syl XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, 463a23fd118Syl XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, 464a23fd118Syl XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, 4658347601bSyl XGE_HAL_BADCFG_LRO_SG_SIZE = XGE_HAL_BASE_BADCFG + 72, 4668347601bSyl XGE_HAL_BADCFG_LRO_FRM_LEN = XGE_HAL_BASE_BADCFG + 73, 4678347601bSyl XGE_HAL_BADCFG_WQE_NUM_ODS = XGE_HAL_BASE_BADCFG + 74, 4688347601bSyl XGE_HAL_BADCFG_BIMODAL_INTR = XGE_HAL_BASE_BADCFG + 75, 4698347601bSyl XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US = XGE_HAL_BASE_BADCFG + 76, 4708347601bSyl XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US = XGE_HAL_BASE_BADCFG + 77, 4718347601bSyl XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED = XGE_HAL_BASE_BADCFG + 78, 472*7eced415Sxw XGE_HAL_BADCFG_RTS_QOS_EN = XGE_HAL_BASE_BADCFG + 79, 473*7eced415Sxw XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 80, 474*7eced415Sxw XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 81, 475*7eced415Sxw XGE_HAL_BADCFG_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 82, 476*7eced415Sxw XGE_HAL_BADCFG_RING_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 83, 477*7eced415Sxw XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP = XGE_HAL_BASE_BADCFG + 84, 478a23fd118Syl XGE_HAL_EOF_TRACE_BUF = -1 479a23fd118Syl } xge_hal_status_e; 480a23fd118Syl 481a23fd118Syl #define XGE_HAL_ETH_ALEN 6 482a23fd118Syl typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; 483a23fd118Syl 484a23fd118Syl #define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 485a23fd118Syl 486a23fd118Syl /* frames sizes */ 487a23fd118Syl #define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 488a23fd118Syl #define XGE_HAL_HEADER_802_2_SIZE 3 489a23fd118Syl #define XGE_HAL_HEADER_SNAP_SIZE 5 490a23fd118Syl #define XGE_HAL_HEADER_VLAN_SIZE 4 491a23fd118Syl #define XGE_HAL_MAC_HEADER_MAX_SIZE \ 492a23fd118Syl (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ 493a23fd118Syl XGE_HAL_HEADER_802_2_SIZE + \ 494a23fd118Syl XGE_HAL_HEADER_SNAP_SIZE) 495a23fd118Syl 496a23fd118Syl #define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) 497a23fd118Syl 498a23fd118Syl /* 32bit alignments */ 499a23fd118Syl #define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 500a23fd118Syl #define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 501a23fd118Syl #define XGE_HAL_HEADER_802_2_ALIGN 3 502a23fd118Syl #define XGE_HAL_HEADER_SNAP_ALIGN 1 503a23fd118Syl 504a23fd118Syl #define XGE_HAL_L3_CKSUM_OK 0xFFFF 505a23fd118Syl #define XGE_HAL_L4_CKSUM_OK 0xFFFF 506a23fd118Syl #define XGE_HAL_MIN_MTU 46 507a23fd118Syl #define XGE_HAL_MAX_MTU 9600 508a23fd118Syl #define XGE_HAL_DEFAULT_MTU 1500 509a23fd118Syl 510a23fd118Syl #define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 511a23fd118Syl 512a23fd118Syl #define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ 513a23fd118Syl #define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ 514a23fd118Syl 515*7eced415Sxw #define XGE_HAL_MAX_MSIX_MESSAGES 64 516*7eced415Sxw #define XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR XGE_HAL_MAX_MSIX_MESSAGES * 2 517a23fd118Syl /* Highest level interrupt blocks */ 518a23fd118Syl #define XGE_HAL_TX_PIC_INTR (0x0001<<0) 519a23fd118Syl #define XGE_HAL_TX_DMA_INTR (0x0001<<1) 520a23fd118Syl #define XGE_HAL_TX_MAC_INTR (0x0001<<2) 521a23fd118Syl #define XGE_HAL_TX_XGXS_INTR (0x0001<<3) 522a23fd118Syl #define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4) 523a23fd118Syl #define XGE_HAL_RX_PIC_INTR (0x0001<<5) 524a23fd118Syl #define XGE_HAL_RX_DMA_INTR (0x0001<<6) 525a23fd118Syl #define XGE_HAL_RX_MAC_INTR (0x0001<<7) 526a23fd118Syl #define XGE_HAL_RX_XGXS_INTR (0x0001<<8) 527a23fd118Syl #define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9) 528a23fd118Syl #define XGE_HAL_MC_INTR (0x0001<<10) 529a23fd118Syl #define XGE_HAL_SCHED_INTR (0x0001<<11) 530a23fd118Syl #define XGE_HAL_ALL_INTRS (XGE_HAL_TX_PIC_INTR | \ 531a23fd118Syl XGE_HAL_TX_DMA_INTR | \ 532a23fd118Syl XGE_HAL_TX_MAC_INTR | \ 533a23fd118Syl XGE_HAL_TX_XGXS_INTR | \ 534a23fd118Syl XGE_HAL_TX_TRAFFIC_INTR | \ 535a23fd118Syl XGE_HAL_RX_PIC_INTR | \ 536a23fd118Syl XGE_HAL_RX_DMA_INTR | \ 537a23fd118Syl XGE_HAL_RX_MAC_INTR | \ 538a23fd118Syl XGE_HAL_RX_XGXS_INTR | \ 539a23fd118Syl XGE_HAL_RX_TRAFFIC_INTR | \ 540a23fd118Syl XGE_HAL_MC_INTR | \ 541a23fd118Syl XGE_HAL_SCHED_INTR) 542a23fd118Syl #define XGE_HAL_GEN_MASK_INTR (0x0001<<12) 543a23fd118Syl 544a23fd118Syl /* Interrupt masks for the general interrupt mask register */ 545a23fd118Syl #define XGE_HAL_ALL_INTRS_DIS 0xFFFFFFFFFFFFFFFFULL 546a23fd118Syl 547a23fd118Syl #define XGE_HAL_TXPIC_INT_M BIT(0) 548a23fd118Syl #define XGE_HAL_TXDMA_INT_M BIT(1) 549a23fd118Syl #define XGE_HAL_TXMAC_INT_M BIT(2) 550a23fd118Syl #define XGE_HAL_TXXGXS_INT_M BIT(3) 551a23fd118Syl #define XGE_HAL_TXTRAFFIC_INT_M BIT(8) 552a23fd118Syl #define XGE_HAL_PIC_RX_INT_M BIT(32) 553a23fd118Syl #define XGE_HAL_RXDMA_INT_M BIT(33) 554a23fd118Syl #define XGE_HAL_RXMAC_INT_M BIT(34) 555a23fd118Syl #define XGE_HAL_MC_INT_M BIT(35) 556a23fd118Syl #define XGE_HAL_RXXGXS_INT_M BIT(36) 557a23fd118Syl #define XGE_HAL_RXTRAFFIC_INT_M BIT(40) 558a23fd118Syl 559a23fd118Syl /* MSI level Interrupts */ 560a23fd118Syl #define XGE_HAL_MAX_MSIX_VECTORS (16) 561a23fd118Syl 562a23fd118Syl typedef struct xge_hal_ipv4 { 563a23fd118Syl u32 addr; 564a23fd118Syl }xge_hal_ipv4; 565a23fd118Syl 566a23fd118Syl typedef struct xge_hal_ipv6 { 567a23fd118Syl u64 addr[2]; 568a23fd118Syl }xge_hal_ipv6; 569a23fd118Syl 570a23fd118Syl typedef union xge_hal_ipaddr_t { 571a23fd118Syl xge_hal_ipv4 ipv4; 572a23fd118Syl xge_hal_ipv6 ipv6; 573a23fd118Syl }xge_hal_ipaddr_t; 574a23fd118Syl 575a23fd118Syl /* DMA level Interrupts */ 576a23fd118Syl #define XGE_HAL_TXDMA_PFC_INT_M BIT(0) 577a23fd118Syl 578a23fd118Syl /* PFC block interrupts */ 579a23fd118Syl #define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO 580a23fd118Syl full */ 581a23fd118Syl 582a23fd118Syl /* basic handles */ 583a23fd118Syl typedef void* xge_hal_device_h; 584a23fd118Syl typedef void* xge_hal_dtr_h; 585a23fd118Syl typedef void* xge_hal_channel_h; 586*7eced415Sxw 587a23fd118Syl /* 588a23fd118Syl * I2C device id. Used in I2C control register for accessing EEPROM device 589a23fd118Syl * memory. 590a23fd118Syl */ 591a23fd118Syl #define XGE_DEV_ID 5 592a23fd118Syl 5938347601bSyl typedef enum xge_hal_xpak_alarm_type_e { 5948347601bSyl XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, 5958347601bSyl XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2, 5968347601bSyl XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3, 5978347601bSyl } xge_hal_xpak_alarm_type_e; 5988347601bSyl 5998347601bSyl 6008347601bSyl __EXTERN_END_DECLS 6018347601bSyl 602a23fd118Syl #endif /* XGE_HAL_TYPES_H */ 603