1a23fd118Syl /* 2a23fd118Syl * CDDL HEADER START 3a23fd118Syl * 4a23fd118Syl * The contents of this file are subject to the terms of the 5a23fd118Syl * Common Development and Distribution License (the "License"). 6a23fd118Syl * You may not use this file except in compliance with the License. 7a23fd118Syl * 8a23fd118Syl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9a23fd118Syl * or http://www.opensolaris.org/os/licensing. 10a23fd118Syl * See the License for the specific language governing permissions 11a23fd118Syl * and limitations under the License. 12a23fd118Syl * 13a23fd118Syl * When distributing Covered Code, include this CDDL HEADER in each 14a23fd118Syl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15a23fd118Syl * If applicable, add the following below this CDDL HEADER, with the 16a23fd118Syl * fields enclosed by brackets "[]" replaced with your own identifying 17a23fd118Syl * information: Portions Copyright [yyyy] [name of copyright owner] 18a23fd118Syl * 19a23fd118Syl * CDDL HEADER END 20a23fd118Syl * 218347601bSyl * Copyright (c) 2002-2006 Neterion, Inc. 22a23fd118Syl */ 23a23fd118Syl 24a23fd118Syl #ifndef XGE_HAL_RING_H 25a23fd118Syl #define XGE_HAL_RING_H 26a23fd118Syl 27a23fd118Syl #include "xgehal-channel.h" 28a23fd118Syl #include "xgehal-config.h" 29a23fd118Syl #include "xgehal-mm.h" 30a23fd118Syl 318347601bSyl __EXTERN_BEGIN_DECLS 328347601bSyl 33a23fd118Syl /* HW ring configuration */ 34a23fd118Syl #define XGE_HAL_RING_RXDBLOCK_SIZE 0x1000 35a23fd118Syl 36a23fd118Syl #define XGE_HAL_RXD_T_CODE_OK 0x0 37a23fd118Syl #define XGE_HAL_RXD_T_CODE_PARITY 0x1 38a23fd118Syl #define XGE_HAL_RXD_T_CODE_ABORT 0x2 39a23fd118Syl #define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3 40a23fd118Syl #define XGE_HAL_RXD_T_CODE_RDA_FAILURE 0x4 41a23fd118Syl #define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5 42a23fd118Syl #define XGE_HAL_RXD_T_CODE_BAD_FCS 0x6 43a23fd118Syl #define XGE_HAL_RXD_T_CODE_BUFF_SIZE 0x7 44a23fd118Syl #define XGE_HAL_RXD_T_CODE_BAD_ECC 0x8 45a23fd118Syl #define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC 46a23fd118Syl #define XGE_HAL_RXD_T_CODE_UNKNOWN 0xF 47a23fd118Syl 48a23fd118Syl #define XGE_HAL_RING_USE_MTU -1 49a23fd118Syl 50a23fd118Syl /* control_1 and control_2 formatting - same for all buffer modes */ 51a23fd118Syl #define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF) 52a23fd118Syl #define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF)) 53a23fd118Syl 54a23fd118Syl #define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16) 55a23fd118Syl #define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val 56a23fd118Syl #define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF)) 57a23fd118Syl 58a23fd118Syl #define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */ 59a23fd118Syl #define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */ 60a23fd118Syl #define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 61a23fd118Syl #define XGE_HAL_RXD_GET_T_CODE(control_1) \ 62a23fd118Syl ((control_1 & XGE_HAL_RXD_T_CODE)>>48) 63a23fd118Syl #define XGE_HAL_RXD_SET_T_CODE(control_1, val) \ 64a23fd118Syl (control_1 |= (((u64)val & 0xF) << 48)) 65a23fd118Syl 66a23fd118Syl #define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2) 67a23fd118Syl #define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8) 68a23fd118Syl #define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \ 69a23fd118Syl (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37)) 70a23fd118Syl #define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \ 71a23fd118Syl (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32) 72a23fd118Syl #define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24) 73a23fd118Syl #define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27) 74a23fd118Syl #define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28) 75a23fd118Syl #define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29) 76a23fd118Syl #define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30) 77a23fd118Syl #define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31) 78a23fd118Syl #define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \ 79a23fd118Syl XGE_HAL_RXD_FRAME_PROTO_UDP) 80a23fd118Syl 81a23fd118Syl /** 82a23fd118Syl * enum xge_hal_frame_type_e - Ethernet frame format. 83a23fd118Syl * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format. 84a23fd118Syl * @XGE_HAL_FRAME_TYPE_LLC: LLC format. 85a23fd118Syl * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format. 86a23fd118Syl * @XGE_HAL_FRAME_TYPE_IPX: IPX format. 87a23fd118Syl * 88a23fd118Syl * Ethernet frame format. 89a23fd118Syl */ 90a23fd118Syl typedef enum xge_hal_frame_type_e { 91a23fd118Syl XGE_HAL_FRAME_TYPE_DIX = 0x0, 92a23fd118Syl XGE_HAL_FRAME_TYPE_LLC = 0x1, 93a23fd118Syl XGE_HAL_FRAME_TYPE_SNAP = 0x2, 94a23fd118Syl XGE_HAL_FRAME_TYPE_IPX = 0x3, 95a23fd118Syl } xge_hal_frame_type_e; 96a23fd118Syl 97a23fd118Syl /** 98a23fd118Syl * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols. 99a23fd118Syl * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN. 100a23fd118Syl * @XGE_HAL_FRAME_PROTO_IPV4: IPv4. 101a23fd118Syl * @XGE_HAL_FRAME_PROTO_IPV6: IPv6. 102a23fd118Syl * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented. 103a23fd118Syl * @XGE_HAL_FRAME_PROTO_TCP: TCP. 104a23fd118Syl * @XGE_HAL_FRAME_PROTO_UDP: UDP. 105a23fd118Syl * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP. 106a23fd118Syl * 107a23fd118Syl * Higher layer ethernet protocols and options. 108a23fd118Syl */ 109a23fd118Syl typedef enum xge_hal_frame_proto_e { 110a23fd118Syl XGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, 111a23fd118Syl XGE_HAL_FRAME_PROTO_IPV4 = 0x10, 112a23fd118Syl XGE_HAL_FRAME_PROTO_IPV6 = 0x08, 113a23fd118Syl XGE_HAL_FRAME_PROTO_IP_FRAGMENTED = 0x04, 114a23fd118Syl XGE_HAL_FRAME_PROTO_TCP = 0x02, 115a23fd118Syl XGE_HAL_FRAME_PROTO_UDP = 0x01, 116a23fd118Syl XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \ 117a23fd118Syl XGE_HAL_FRAME_PROTO_UDP) 118a23fd118Syl } xge_hal_frame_proto_e; 119a23fd118Syl 120a23fd118Syl /* 121a23fd118Syl * xge_hal_ring_rxd_1_t 122a23fd118Syl */ 123a23fd118Syl typedef struct { 124a23fd118Syl u64 host_control; 125a23fd118Syl u64 control_1; 126a23fd118Syl u64 control_2; 127a23fd118Syl #define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 128a23fd118Syl #define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 129a23fd118Syl #define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \ 130a23fd118Syl (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 131a23fd118Syl #define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \ 132a23fd118Syl (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16) 133a23fd118Syl u64 buffer0_ptr; 134a23fd118Syl } xge_hal_ring_rxd_1_t; 135a23fd118Syl 136a23fd118Syl /* 137a23fd118Syl * xge_hal_ring_rxd_3_t 138a23fd118Syl */ 139a23fd118Syl typedef struct { 140a23fd118Syl u64 host_control; 141a23fd118Syl u64 control_1; 142a23fd118Syl 143a23fd118Syl u64 control_2; 144a23fd118Syl #define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8) 145a23fd118Syl #define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8) 146a23fd118Syl #define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 147a23fd118Syl #define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 148a23fd118Syl #define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 149a23fd118Syl #define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 150a23fd118Syl 151a23fd118Syl 152a23fd118Syl #define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \ 153a23fd118Syl (int)((Control_2 & vBIT(0xFF,8,8))>>48) 154a23fd118Syl #define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \ 155a23fd118Syl (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 156a23fd118Syl #define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \ 157a23fd118Syl (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 158a23fd118Syl 159a23fd118Syl u64 buffer0_ptr; 160a23fd118Syl u64 buffer1_ptr; 161a23fd118Syl u64 buffer2_ptr; 162a23fd118Syl } xge_hal_ring_rxd_3_t; 163a23fd118Syl 164a23fd118Syl /* 165a23fd118Syl * xge_hal_ring_rxd_5_t 166a23fd118Syl */ 167a23fd118Syl typedef struct { 168a23fd118Syl #ifdef XGE_OS_HOST_BIG_ENDIAN 169a23fd118Syl u32 host_control; 170a23fd118Syl u32 control_3; 171a23fd118Syl #else 172a23fd118Syl u32 control_3; 173a23fd118Syl u32 host_control; 174a23fd118Syl #endif 175a23fd118Syl 176a23fd118Syl 177a23fd118Syl #define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16) 178a23fd118Syl #define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16) 179a23fd118Syl #define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16) 180a23fd118Syl #define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16) 181a23fd118Syl 182a23fd118Syl #define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \ 183a23fd118Syl (int)((Control_3 & vBIT(0xFFFF,32,16))>>16) 184a23fd118Syl #define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \ 185a23fd118Syl (int)((Control_3 & vBIT(0xFFFF,48,16))) 186a23fd118Syl 187a23fd118Syl u64 control_1; 188a23fd118Syl u64 control_2; 189a23fd118Syl 190a23fd118Syl #define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 191a23fd118Syl #define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 192a23fd118Syl #define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 193a23fd118Syl #define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 194a23fd118Syl #define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 195a23fd118Syl #define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 196a23fd118Syl 197a23fd118Syl 198a23fd118Syl #define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \ 199a23fd118Syl (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 200a23fd118Syl #define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \ 201a23fd118Syl (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 202a23fd118Syl #define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \ 203a23fd118Syl (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 204a23fd118Syl u64 buffer0_ptr; 205a23fd118Syl u64 buffer1_ptr; 206a23fd118Syl u64 buffer2_ptr; 207a23fd118Syl u64 buffer3_ptr; 208a23fd118Syl u64 buffer4_ptr; 209a23fd118Syl } xge_hal_ring_rxd_5_t; 210a23fd118Syl 211a23fd118Syl #define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \ 212a23fd118Syl (u8)((Control_1 & BIT(18))>>45) 213a23fd118Syl #define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \ 214a23fd118Syl (u8)((Control_1 & BIT(19))>>44) 215a23fd118Syl #define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \ 216a23fd118Syl (u8)((Control_1 & vBIT(0xF,20,4))>>40) 217a23fd118Syl 218a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_NONE 0x0 219a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4 0x1 220a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4 0x2 221a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3 222a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6 0x4 223a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6 0x5 224a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_IPV6 0x6 225a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX 0x7 226a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX 0x8 227a23fd118Syl #define XGE_HAL_RXD_HASH_TYPE_IPV6_EX 0x9 2288347601bSyl 229a23fd118Syl typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE]; 230a23fd118Syl 231a23fd118Syl #define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET 0xFF8 232a23fd118Syl #define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET 0xFF0 233a23fd118Syl 234a23fd118Syl #define XGE_HAL_RING_RXD_SIZEOF(n) \ 235a23fd118Syl (n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \ 236a23fd118Syl (n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \ 237a23fd118Syl sizeof(xge_hal_ring_rxd_5_t))) 238a23fd118Syl 239a23fd118Syl #define XGE_HAL_RING_RXDS_PER_BLOCK(n) \ 240a23fd118Syl (n==1 ? 127 : (n==3 ? 85 : 63)) 241a23fd118Syl 242a23fd118Syl /** 243a23fd118Syl * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data. 244a23fd118Syl * @dma_addr: DMA (mapped) address of _this_ descriptor. 245a23fd118Syl * @dma_handle: DMA handle used to map the descriptor onto device. 246a23fd118Syl * @dma_offset: Descriptor's offset in the memory block. HAL allocates 247a23fd118Syl * descriptors in memory blocks of 248a23fd118Syl * %XGE_HAL_RING_RXDBLOCK_SIZE 249a23fd118Syl * bytes. Each memblock is contiguous DMA-able memory. Each 250a23fd118Syl * memblock contains 1 or more 4KB RxD blocks visible to the 251a23fd118Syl * Xframe hardware. 252a23fd118Syl * @dma_object: DMA address and handle of the memory block that contains 253a23fd118Syl * the descriptor. This member is used only in the "checked" 254a23fd118Syl * version of the HAL (to enforce certain assertions); 255a23fd118Syl * otherwise it gets compiled out. 256a23fd118Syl * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 257a23fd118Syl * 258a23fd118Syl * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA 259a23fd118Syl * information associated with the descriptor. Note that ULD can ask HAL 260a23fd118Syl * to allocate additional per-descriptor space for its own (ULD-specific) 261a23fd118Syl * purposes. 262a23fd118Syl */ 263a23fd118Syl typedef struct xge_hal_ring_rxd_priv_t { 264a23fd118Syl dma_addr_t dma_addr; 265a23fd118Syl pci_dma_h dma_handle; 266a23fd118Syl ptrdiff_t dma_offset; 267a23fd118Syl #ifdef XGE_DEBUG_ASSERT 268a23fd118Syl xge_hal_mempool_dma_t *dma_object; 269a23fd118Syl #endif 270a23fd118Syl #ifdef XGE_OS_MEMORY_CHECK 271a23fd118Syl int allocated; 272a23fd118Syl #endif 273a23fd118Syl } xge_hal_ring_rxd_priv_t; 274a23fd118Syl 275a23fd118Syl /** 276a23fd118Syl * struct xge_hal_ring_t - Ring channel. 277a23fd118Syl * @channel: Channel "base" of this ring, the common part of all HAL 278a23fd118Syl * channels. 279a23fd118Syl * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, 280a23fd118Syl * as per Xframe User Guide. 281a23fd118Syl * @indicate_max_pkts: Maximum number of packets processed within a single 282a23fd118Syl * interrupt. Can be used to limit the time spent inside hw 283a23fd118Syl * interrupt. 284a23fd118Syl * @config: Ring configuration, part of device configuration 285a23fd118Syl * (see xge_hal_device_config_t{}). 286a23fd118Syl * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec, 287a23fd118Syl * 1-buffer mode descriptor is 32 byte long, etc. 288a23fd118Syl * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor 289a23fd118Syl * data (e.g., DMA handle for Solaris) 290a23fd118Syl * @rxds_per_block: Number of descriptors per hardware-defined RxD 291a23fd118Syl * block. Depends on the (1-,3-,5-) buffer mode. 292a23fd118Syl * @mempool: Memory pool, the pool from which descriptors get allocated. 293a23fd118Syl * (See xge_hal_mm.h). 294a23fd118Syl * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal 295a23fd118Syl * usage. Not to confuse with @rxd_priv_size. 296a23fd118Syl * @reserved_rxds_arr: Array of RxD pointers. At any point in time each 297a23fd118Syl * entry in this array is available for allocation 298a23fd118Syl * (via xge_hal_ring_dtr_reserve()) and posting. 299a23fd118Syl * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. 300a23fd118Syl * Used in conjunction with @indicate_max_pkts. 301a23fd118Syl * Ring channel. 302a23fd118Syl * 303a23fd118Syl * Note: The structure is cache line aligned to better utilize 304a23fd118Syl * CPU cache performance. 305a23fd118Syl */ 306a23fd118Syl typedef struct xge_hal_ring_t { 307a23fd118Syl xge_hal_channel_t channel; 308a23fd118Syl int buffer_mode; 309a23fd118Syl int indicate_max_pkts; 310a23fd118Syl xge_hal_ring_config_t *config; 311a23fd118Syl int rxd_size; 312a23fd118Syl int rxd_priv_size; 313a23fd118Syl int rxds_per_block; 314a23fd118Syl xge_hal_mempool_t *mempool; 315a23fd118Syl int rxdblock_priv_size; 316a23fd118Syl void **reserved_rxds_arr; 317a23fd118Syl int cmpl_cnt; 318a23fd118Syl } __xge_os_attr_cacheline_aligned xge_hal_ring_t; 319a23fd118Syl 320a23fd118Syl /** 321a23fd118Syl * struct xge_hal_dtr_info_t - Extended information associated with a 322a23fd118Syl * completed ring descriptor. 323a23fd118Syl * @l3_cksum: Result of IP checksum check (by Xframe hardware). 324a23fd118Syl * This field containing XGE_HAL_L3_CKSUM_OK would mean that 325a23fd118Syl * the checksum is correct, otherwise - the datagram is 326a23fd118Syl * corrupted. 327a23fd118Syl * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware). 328a23fd118Syl * This field containing XGE_HAL_L4_CKSUM_OK would mean that 329a23fd118Syl * the checksum is correct. Otherwise - the packet is 330a23fd118Syl * corrupted. 331a23fd118Syl * @frame: See xge_hal_frame_type_e{}. 332a23fd118Syl * @proto: Reporting bits for various higher-layer protocols, including (but 333a23fd118Syl * note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}. 334a23fd118Syl * @vlan: VLAN tag extracted from the received frame. 335a23fd118Syl * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II 336a23fd118Syl * hardware if RTH is enabled. 337a23fd118Syl * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware 338a23fd118Syl * has a matching entry in the Indirection table. 339a23fd118Syl * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware 340a23fd118Syl * has a matching entry in the Socket Pair Direct Match table. 341a23fd118Syl * @rth_hash_type: RTH hash code of the function used to calculate the hash. 342a23fd118Syl * @reserved_pad: Unused byte. 343a23fd118Syl */ 344a23fd118Syl typedef struct xge_hal_dtr_info_t { 345a23fd118Syl int l3_cksum; 346a23fd118Syl int l4_cksum; 347a23fd118Syl int frame; /* zero or more of xge_hal_frame_type_e flags */ 348a23fd118Syl int proto; /* zero or more of xge_hal_frame_proto_e flags */ 349a23fd118Syl int vlan; 350a23fd118Syl u32 rth_value; 351a23fd118Syl u8 rth_it_hit; 352a23fd118Syl u8 rth_spdm_hit; 353a23fd118Syl u8 rth_hash_type; 354a23fd118Syl u8 reserved_pad; 355a23fd118Syl } xge_hal_dtr_info_t; 356a23fd118Syl 357a23fd118Syl /* ========================== RING PRIVATE API ============================ */ 358a23fd118Syl 359a23fd118Syl xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh, 360a23fd118Syl xge_hal_channel_attr_t *attr); 361a23fd118Syl 362a23fd118Syl void __hal_ring_close(xge_hal_channel_h channelh); 363a23fd118Syl 364a23fd118Syl void __hal_ring_hw_initialize(xge_hal_device_h devh); 365a23fd118Syl 366a23fd118Syl void __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu); 367a23fd118Syl 368a23fd118Syl void __hal_ring_prc_enable(xge_hal_channel_h channelh); 369a23fd118Syl 370a23fd118Syl void __hal_ring_prc_disable(xge_hal_channel_h channelh); 371a23fd118Syl 372a23fd118Syl xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel, 373a23fd118Syl xge_hal_channel_reopen_e reopen); 374a23fd118Syl 375a23fd118Syl #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING) 376a23fd118Syl #define __HAL_STATIC_RING 377a23fd118Syl #define __HAL_INLINE_RING 378a23fd118Syl 379a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING int 380a23fd118Syl __hal_ring_block_memblock_idx(xge_hal_ring_block_t *block); 381a23fd118Syl 382a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 383a23fd118Syl __hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx); 384a23fd118Syl 385a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t 386a23fd118Syl __hal_ring_block_next_pointer(xge_hal_ring_block_t *block); 387a23fd118Syl 388a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 389a23fd118Syl __hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block, 390a23fd118Syl dma_addr_t dma_next); 391a23fd118Syl 392a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t* 393a23fd118Syl __hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh); 394a23fd118Syl 395a23fd118Syl /* =========================== RING PUBLIC API ============================ */ 396a23fd118Syl 397a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 398a23fd118Syl xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 399a23fd118Syl 400a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void* 401a23fd118Syl xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 402a23fd118Syl 403a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 404a23fd118Syl xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size); 405a23fd118Syl 406a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 407a23fd118Syl xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 408a23fd118Syl xge_hal_dtr_info_t *ext_info); 409a23fd118Syl 410a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 411a23fd118Syl xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 412a23fd118Syl dma_addr_t *dma_pointer, int *pkt_length); 413a23fd118Syl 414a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 415a23fd118Syl xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 416a23fd118Syl int sizes[]); 417a23fd118Syl 418a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 419a23fd118Syl xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 420a23fd118Syl dma_addr_t dma_pointers[], int sizes[]); 421a23fd118Syl 422a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 423a23fd118Syl xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 424a23fd118Syl int sizes[]); 425a23fd118Syl 426a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 427a23fd118Syl xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 428a23fd118Syl dma_addr_t dma_pointer[], int sizes[]); 429a23fd118Syl 430a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 431a23fd118Syl xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 432a23fd118Syl 433a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 434a23fd118Syl xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 435a23fd118Syl 436a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 437a23fd118Syl xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 438a23fd118Syl 439*7eced415Sxw __HAL_STATIC_RING __HAL_INLINE_RING void 440*7eced415Sxw xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 441*7eced415Sxw 442a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 443a23fd118Syl xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 444a23fd118Syl u8 *t_code); 445a23fd118Syl 446a23fd118Syl __HAL_STATIC_RING __HAL_INLINE_RING void 447a23fd118Syl xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 448a23fd118Syl 4498347601bSyl __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 4508347601bSyl xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh); 4518347601bSyl 452a23fd118Syl #else /* XGE_FASTPATH_EXTERN */ 453a23fd118Syl #define __HAL_STATIC_RING static 454a23fd118Syl #define __HAL_INLINE_RING inline 455a23fd118Syl #include "xgehal-ring-fp.c" 456a23fd118Syl #endif /* XGE_FASTPATH_INLINE */ 457a23fd118Syl 4588347601bSyl __EXTERN_END_DECLS 459a23fd118Syl 460a23fd118Syl #endif /* XGE_HAL_RING_H */ 461