xref: /illumos-gate/usr/src/uts/common/io/xge/hal/include/xgehal-mgmt.h (revision 7eced415e5dd557aef2d78483b5a7785f0e13670)
1a23fd118Syl /*
2a23fd118Syl  * CDDL HEADER START
3a23fd118Syl  *
4a23fd118Syl  * The contents of this file are subject to the terms of the
5a23fd118Syl  * Common Development and Distribution License (the "License").
6a23fd118Syl  * You may not use this file except in compliance with the License.
7a23fd118Syl  *
8a23fd118Syl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9a23fd118Syl  * or http://www.opensolaris.org/os/licensing.
10a23fd118Syl  * See the License for the specific language governing permissions
11a23fd118Syl  * and limitations under the License.
12a23fd118Syl  *
13a23fd118Syl  * When distributing Covered Code, include this CDDL HEADER in each
14a23fd118Syl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15a23fd118Syl  * If applicable, add the following below this CDDL HEADER, with the
16a23fd118Syl  * fields enclosed by brackets "[]" replaced with your own identifying
17a23fd118Syl  * information: Portions Copyright [yyyy] [name of copyright owner]
18a23fd118Syl  *
19a23fd118Syl  * CDDL HEADER END
20a23fd118Syl  *
218347601bSyl  * Copyright (c) 2002-2006 Neterion, Inc.
22a23fd118Syl  */
23a23fd118Syl 
24a23fd118Syl #ifndef XGE_HAL_MGMT_H
25a23fd118Syl #define XGE_HAL_MGMT_H
26a23fd118Syl 
27a23fd118Syl #include "xge-os-pal.h"
28a23fd118Syl #include "xge-debug.h"
29a23fd118Syl #include "xgehal-types.h"
30a23fd118Syl #include "xgehal-config.h"
31a23fd118Syl #include "xgehal-stats.h"
32a23fd118Syl #include "xgehal-regs.h"
338347601bSyl #include "xgehal-device.h"
348347601bSyl 
358347601bSyl __EXTERN_BEGIN_DECLS
36a23fd118Syl 
37a23fd118Syl /**
38a23fd118Syl  * struct xge_hal_mgmt_about_info_t - About info.
39a23fd118Syl  * @vendor: PCI Vendor ID.
40a23fd118Syl  * @device: PCI Device ID.
41a23fd118Syl  * @subsys_vendor: PCI Subsystem Vendor ID.
42a23fd118Syl  * @subsys_device: PCI Subsystem Device ID.
43a23fd118Syl  * @board_rev: PCI Board revision, e.g. 3 - for Xena 3.
44a23fd118Syl  * @vendor_name: Neterion, Inc.
45a23fd118Syl  * @chip_name: Xframe.
46a23fd118Syl  * @media: Fiber, copper.
47a23fd118Syl  * @hal_major: HAL major version number.
48a23fd118Syl  * @hal_minor: HAL minor version number.
49a23fd118Syl  * @hal_fix: HAL fix number.
50a23fd118Syl  * @hal_build: HAL build number.
51a23fd118Syl  * @ll_major: Link-layer ULD major version number.
52a23fd118Syl  * @ll_minor: Link-layer ULD minor version number.
53a23fd118Syl  * @ll_fix: Link-layer ULD fix version number.
54a23fd118Syl  * @ll_build: Link-layer ULD build number.
55*7eced415Sxw  * @transponder_temperature: TODO
56a23fd118Syl  */
57a23fd118Syl typedef struct xge_hal_mgmt_about_info_t {
58a23fd118Syl 	u16		vendor;
59a23fd118Syl 	u16		device;
60a23fd118Syl 	u16		subsys_vendor;
61a23fd118Syl 	u16		subsys_device;
62a23fd118Syl 	u8		board_rev;
63a23fd118Syl 	char		vendor_name[16];
64a23fd118Syl 	char		chip_name[16];
65a23fd118Syl 	char		media[16];
66a23fd118Syl 	char		hal_major[4];
67a23fd118Syl 	char		hal_minor[4];
68a23fd118Syl 	char		hal_fix[4];
69a23fd118Syl 	char		hal_build[16];
70a23fd118Syl 	char		ll_major[4];
71a23fd118Syl 	char		ll_minor[4];
72a23fd118Syl 	char		ll_fix[4];
73a23fd118Syl 	char		ll_build[16];
748347601bSyl 	u32		transponder_temperature;
75a23fd118Syl } xge_hal_mgmt_about_info_t;
76a23fd118Syl 
77a23fd118Syl typedef xge_hal_stats_hw_info_t		xge_hal_mgmt_hw_stats_t;
78*7eced415Sxw typedef xge_hal_stats_pcim_info_t	xge_hal_mgmt_pcim_stats_t;
79a23fd118Syl typedef xge_hal_stats_sw_err_t		xge_hal_mgmt_sw_stats_t;
80a23fd118Syl typedef xge_hal_stats_device_info_t	xge_hal_mgmt_device_stats_t;
81a23fd118Syl typedef xge_hal_stats_channel_info_t	xge_hal_mgmt_channel_stats_t;
82a23fd118Syl typedef xge_hal_device_config_t		xge_hal_mgmt_device_config_t;
83a23fd118Syl typedef xge_hal_driver_config_t		xge_hal_mgmt_driver_config_t;
84a23fd118Syl typedef xge_hal_pci_config_t		xge_hal_mgmt_pci_config_t;
85a23fd118Syl 
86a23fd118Syl xge_hal_status_e
87a23fd118Syl xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info,
88a23fd118Syl 		int size);
89a23fd118Syl 
90a23fd118Syl xge_hal_status_e
91a23fd118Syl xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats,
92a23fd118Syl 		int size);
93a23fd118Syl 
94a23fd118Syl xge_hal_status_e
95a23fd118Syl xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out);
96a23fd118Syl 
97*7eced415Sxw xge_hal_status_e
98*7eced415Sxw xge_hal_mgmt_pcim_stats(xge_hal_device_h devh,
99*7eced415Sxw 		xge_hal_mgmt_pcim_stats_t *pcim_stats, int size);
100*7eced415Sxw 
101*7eced415Sxw xge_hal_status_e
102*7eced415Sxw xge_hal_mgmt_pcim_stats_off(xge_hal_device_h devh, int off, int size,
103*7eced415Sxw 		char *out);
104*7eced415Sxw 
105a23fd118Syl xge_hal_status_e
106a23fd118Syl xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *hw_stats,
107a23fd118Syl 		int size);
108a23fd118Syl 
109a23fd118Syl xge_hal_status_e
110a23fd118Syl xge_hal_mgmt_device_stats(xge_hal_device_h devh,
111a23fd118Syl 		xge_hal_mgmt_device_stats_t *device_stats, int size);
112a23fd118Syl 
113a23fd118Syl xge_hal_status_e
114a23fd118Syl xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh,
115a23fd118Syl 		xge_hal_mgmt_channel_stats_t *channel_stats, int size);
116a23fd118Syl 
117a23fd118Syl xge_hal_status_e
118a23fd118Syl xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset,
119a23fd118Syl 		u64 *value);
120a23fd118Syl 
121a23fd118Syl xge_hal_status_e
122a23fd118Syl xge_hal_mgmt_reg_write(xge_hal_device_h	devh, int bar_id, unsigned int offset,
123a23fd118Syl 		u64 value);
124a23fd118Syl 
125a23fd118Syl xge_hal_status_e
126a23fd118Syl xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset,
127a23fd118Syl 		int bits, u32 *value);
128a23fd118Syl 
129a23fd118Syl xge_hal_status_e
130a23fd118Syl xge_hal_mgmt_device_config(xge_hal_device_h devh,
131a23fd118Syl 		xge_hal_mgmt_device_config_t *dev_config, int size);
132a23fd118Syl 
133a23fd118Syl xge_hal_status_e
134a23fd118Syl xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config,
135a23fd118Syl 		int size);
136a23fd118Syl 
137a23fd118Syl xge_hal_status_e
138a23fd118Syl xge_hal_mgmt_pci_config(xge_hal_device_h devh,
139a23fd118Syl 		xge_hal_mgmt_pci_config_t *pci_config, int size);
140a23fd118Syl 
1418347601bSyl xge_hal_status_e
1428347601bSyl xge_hal_pma_loopback( xge_hal_device_h devh, int enable );
1438347601bSyl 
1448347601bSyl xge_hal_status_e
1458347601bSyl xge_hal_rldram_test(xge_hal_device_h devh, u64 * data);
1468347601bSyl 
1478347601bSyl u16
1488347601bSyl xge_hal_mdio_read( xge_hal_device_h devh, u32 mmd_type, u64 addr );
1498347601bSyl 
1508347601bSyl xge_hal_status_e
1518347601bSyl xge_hal_mdio_write( xge_hal_device_h devh, u32 mmd_type, u64 addr, u32 value );
1528347601bSyl 
1538347601bSyl u32
1548347601bSyl xge_hal_read_xfp_current_temp(xge_hal_device_h devh);
1558347601bSyl 
156*7eced415Sxw xge_hal_status_e
157*7eced415Sxw xge_hal_read_eeprom(xge_hal_device_h devh, int off, u32* data);
158*7eced415Sxw 
159*7eced415Sxw xge_hal_status_e
160*7eced415Sxw xge_hal_write_eeprom(xge_hal_device_h devh, int off, u32 data, int cnt);
161*7eced415Sxw 
162*7eced415Sxw xge_hal_status_e
163*7eced415Sxw xge_hal_register_test(xge_hal_device_h devh, u64 *data);
164*7eced415Sxw 
165*7eced415Sxw xge_hal_status_e
166*7eced415Sxw xge_hal_eeprom_test(xge_hal_device_h devh, u64 *data);
167*7eced415Sxw 
168*7eced415Sxw xge_hal_status_e
169*7eced415Sxw xge_hal_bist_test(xge_hal_device_h devh, u64 *data);
170*7eced415Sxw 
171*7eced415Sxw xge_hal_status_e
172*7eced415Sxw xge_hal_link_test(xge_hal_device_h devh, u64 *data);
173*7eced415Sxw 
174*7eced415Sxw int
175*7eced415Sxw xge_hal_setpause_data(xge_hal_device_h devh, int tx, int rx);
176*7eced415Sxw 
177*7eced415Sxw void
178*7eced415Sxw xge_hal_getpause_data(xge_hal_device_h devh, int *tx, int *rx);
179*7eced415Sxw 
1808347601bSyl void
1818347601bSyl __hal_updt_stats_xpak(xge_hal_device_t *hldev);
1828347601bSyl 
183*7eced415Sxw void
184*7eced415Sxw __hal_chk_xpak_counter(xge_hal_device_t *hldev, int type, u32 value);
185*7eced415Sxw 
186a23fd118Syl #ifdef XGE_TRACE_INTO_CIRCULAR_ARR
187a23fd118Syl xge_hal_status_e
188a23fd118Syl xge_hal_mgmt_trace_read(char *buffer, unsigned buf_size, unsigned *offset,
189a23fd118Syl 		unsigned *read_length);
190a23fd118Syl #endif
191a23fd118Syl 
192a23fd118Syl void
193a23fd118Syl xge_hal_restore_link_led(xge_hal_device_h devh);
194a23fd118Syl 
195a23fd118Syl 
196a23fd118Syl void
197a23fd118Syl xge_hal_flick_link_led(xge_hal_device_h devh);
198a23fd118Syl 
199a23fd118Syl /*
200a23fd118Syl  * Some set of Xena3 Cards were known to have some link LED
201a23fd118Syl  * Problems. This macro identifies if the card is among them
202a23fd118Syl  * given its Sub system ID.
203a23fd118Syl  */
204a23fd118Syl #define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \
205a23fd118Syl 		((((subid >= 0x600B) && (subid <= 0x600D)) || \
206a23fd118Syl 		 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0)
2078347601bSyl #define CHECKBIT(value, nbit) (value & (1 << nbit))
208a23fd118Syl 
209a23fd118Syl #ifdef XGE_HAL_USE_MGMT_AUX
210a23fd118Syl #include "xgehal-mgmtaux.h"
211a23fd118Syl #endif
212a23fd118Syl 
2138347601bSyl __EXTERN_END_DECLS
2148347601bSyl 
215a23fd118Syl #endif /* XGE_HAL_MGMT_H */
216