1a23fd118Syl /*
2a23fd118Syl  * CDDL HEADER START
3a23fd118Syl  *
4a23fd118Syl  * The contents of this file are subject to the terms of the
5a23fd118Syl  * Common Development and Distribution License (the "License").
6a23fd118Syl  * You may not use this file except in compliance with the License.
7a23fd118Syl  *
8a23fd118Syl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9a23fd118Syl  * or http://www.opensolaris.org/os/licensing.
10a23fd118Syl  * See the License for the specific language governing permissions
11a23fd118Syl  * and limitations under the License.
12a23fd118Syl  *
13a23fd118Syl  * When distributing Covered Code, include this CDDL HEADER in each
14a23fd118Syl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15a23fd118Syl  * If applicable, add the following below this CDDL HEADER, with the
16a23fd118Syl  * fields enclosed by brackets "[]" replaced with your own identifying
17a23fd118Syl  * information: Portions Copyright [yyyy] [name of copyright owner]
18a23fd118Syl  *
19a23fd118Syl  * CDDL HEADER END
20a23fd118Syl  *
218347601bSyl  * Copyright (c) 2002-2006 Neterion, Inc.
22a23fd118Syl  */
24a23fd118Syl #ifndef XGE_HAL_FIFO_H
25a23fd118Syl #define XGE_HAL_FIFO_H
27a23fd118Syl #include "xgehal-channel.h"
28a23fd118Syl #include "xgehal-config.h"
29a23fd118Syl #include "xgehal-mm.h"
318347601bSyl __EXTERN_BEGIN_DECLS
33a23fd118Syl /* HW fifo configuration */
34a23fd118Syl #define	XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD	65
35a23fd118Syl #define XGE_HAL_FIFO_MAX_WRR			5
36a23fd118Syl #define XGE_HAL_FIFO_MAX_PARTITION		4
37a23fd118Syl #define XGE_HAL_FIFO_MAX_WRR_STATE		36
38a23fd118Syl #define XGE_HAL_FIFO_HW_PAIR_OFFSET		0x20000
40*7eced415Sxw /* HW FIFO Weight Calender */
41*7eced415Sxw #define XGE_HAL_FIFO_WRR_0      0x0706050407030602ULL
42*7eced415Sxw #define XGE_HAL_FIFO_WRR_1      0x0507040601070503ULL
43*7eced415Sxw #define XGE_HAL_FIFO_WRR_2      0x0604070205060700ULL
44*7eced415Sxw #define XGE_HAL_FIFO_WRR_3      0x0403060705010207ULL
45*7eced415Sxw #define XGE_HAL_FIFO_WRR_4      0x0604050300000000ULL
46a23fd118Syl /*
47a23fd118Syl  * xge_hal_fifo_hw_pair_t
48a23fd118Syl  *
49a23fd118Syl  * Represent a single fifo in the BAR1 memory space.
50a23fd118Syl  */
51a23fd118Syl typedef struct {
52a23fd118Syl 	u64 txdl_pointer; /* offset 0x0 */
54a23fd118Syl 	u64 reserved[2];
56a23fd118Syl 	u64 list_control; /* offset 0x18 */
57a23fd118Syl #define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
58a23fd118Syl #define XGE_HAL_TX_FIFO_FIRST_LIST             BIT(14)
59a23fd118Syl #define XGE_HAL_TX_FIFO_LAST_LIST              BIT(15)
60a23fd118Syl #define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
61a23fd118Syl #define XGE_HAL_TX_FIFO_SPECIAL_FUNC           BIT(23)
62a23fd118Syl #define XGE_HAL_TX_FIFO_NO_SNOOP(n)            vBIT(n,30,2)
63a23fd118Syl } xge_hal_fifo_hw_pair_t;
66a23fd118Syl /* Bad TxDL transfer codes */
67a23fd118Syl #define XGE_HAL_TXD_T_CODE_OK		        0x0
68a23fd118Syl #define XGE_HAL_TXD_T_CODE_UNUSED_1		0x1
69a23fd118Syl #define XGE_HAL_TXD_T_CODE_ABORT_BUFFER		0x2
70a23fd118Syl #define XGE_HAL_TXD_T_CODE_ABORT_DTOR		0x3
71a23fd118Syl #define XGE_HAL_TXD_T_CODE_UNUSED_5		0x5
72a23fd118Syl #define XGE_HAL_TXD_T_CODE_PARITY		0x7
73a23fd118Syl #define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK		0xA
74a23fd118Syl #define XGE_HAL_TXD_T_CODE_GENERAL_ERR		0xF
77a23fd118Syl /**
78a23fd118Syl  * struct xge_hal_fifo_txd_t - TxD.
79a23fd118Syl  * @control_1: Control_1.
80a23fd118Syl  * @control_2: Control_2.
81a23fd118Syl  * @buffer_pointer: Buffer_Address.
82a23fd118Syl  * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the Xframe
83a23fd118Syl  *            descriptor prior to posting the latter on the channel
84a23fd118Syl  *            via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post().
85a23fd118Syl  *            The %host_control is returned as is to the ULD with each
86a23fd118Syl  *            completed descriptor.
87a23fd118Syl  *
88a23fd118Syl  * Transmit descriptor (TxD).Fifo descriptor contains configured number
89a23fd118Syl  * (list) of TxDs. * For more details please refer to Xframe User Guide,
90a23fd118Syl  * Section 5.4.2 "Transmit Descriptor (TxD) Format".
91a23fd118Syl  */
92a23fd118Syl typedef struct xge_hal_fifo_txd_t {
93a23fd118Syl 	u64 control_1;
94a23fd118Syl #define XGE_HAL_TXD_LIST_OWN_XENA       BIT(7)
95a23fd118Syl #define XGE_HAL_TXD_T_CODE		(BIT(12)|BIT(13)|BIT(14)|BIT(15))
96a23fd118Syl #define XGE_HAL_GET_TXD_T_CODE(val)     ((val & XGE_HAL_TXD_T_CODE)>>48)
97a23fd118Syl #define XGE_HAL_SET_TXD_T_CODE(x, val)  (x |= (((u64)val & 0xF) << 48))
98a23fd118Syl #define XGE_HAL_TXD_GATHER_CODE         (BIT(22) | BIT(23))
99a23fd118Syl #define XGE_HAL_TXD_GATHER_CODE_FIRST   BIT(22)
100a23fd118Syl #define XGE_HAL_TXD_GATHER_CODE_LAST    BIT(23)
101a23fd118Syl #define XGE_HAL_TXD_NO_LSO				0
102a23fd118Syl #define XGE_HAL_TXD_UDF_COF				1
103a23fd118Syl #define XGE_HAL_TXD_TCP_LSO				2
104a23fd118Syl #define XGE_HAL_TXD_UDP_LSO				3
105a23fd118Syl #define XGE_HAL_TXD_LSO_COF_CTRL(val)   vBIT(val,30,2)
106a23fd118Syl #define XGE_HAL_TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
107a23fd118Syl #define XGE_HAL_TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
1088347601bSyl #define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32)
109a23fd118Syl 	u64 control_2;
110a23fd118Syl #define XGE_HAL_TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))
111a23fd118Syl #define XGE_HAL_TXD_TX_CKO_IPV4_EN      BIT(5)
112a23fd118Syl #define XGE_HAL_TXD_TX_CKO_TCP_EN       BIT(6)
113a23fd118Syl #define XGE_HAL_TXD_TX_CKO_UDP_EN       BIT(7)
114a23fd118Syl #define XGE_HAL_TXD_VLAN_ENABLE         BIT(15)
115a23fd118Syl #define XGE_HAL_TXD_VLAN_TAG(val)       vBIT(val,16,16)
116a23fd118Syl #define XGE_HAL_TXD_INT_NUMBER(val)     vBIT(val,34,6)
117a23fd118Syl #define XGE_HAL_TXD_INT_TYPE_PER_LIST   BIT(47)
118a23fd118Syl #define XGE_HAL_TXD_INT_TYPE_UTILZ      BIT(46)
119a23fd118Syl #define XGE_HAL_TXD_SET_MARKER          vBIT(0x6,0,4)
121a23fd118Syl 	u64 buffer_pointer;
123a23fd118Syl 	u64 host_control;
125a23fd118Syl } xge_hal_fifo_txd_t;
127a23fd118Syl typedef xge_hal_fifo_txd_t* xge_hal_fifo_txdl_t;
129a23fd118Syl /**
130a23fd118Syl  * struct xge_hal_fifo_t - Fifo channel.
131a23fd118Syl  * @channel: Channel "base" of this fifo, the common part of all HAL
132a23fd118Syl  *           channels.
133a23fd118Syl  * @post_lock_ptr: Points to a lock that serializes (pointer, control) PIOs.
134a23fd118Syl  *           Note that for Xena the serialization is done across all device
135a23fd118Syl  *           fifos.
136a23fd118Syl  * @hw_pair: Per-fifo (Pointer, Control) pair used to send descriptors to the
137a23fd118Syl  *           Xframe hardware (for details see Xframe user guide).
138a23fd118Syl  * @config: Fifo configuration, part of device configuration
139a23fd118Syl  *          (see xge_hal_device_config_t{}).
140a23fd118Syl  * @no_snoop_bits: See xge_hal_fifo_config_t{}.
141a23fd118Syl  * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
142a23fd118Syl  * on TxDL please refer to Xframe UG.
143a23fd118Syl  * @interrupt_type: FIXME: to-be-defined.
144a23fd118Syl  * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
145a23fd118Syl  *             per-TxDL HAL private space (xge_hal_fifo_txdl_priv_t).
146a23fd118Syl  * @priv_size: Per-Tx descriptor space reserved for upper-layer driver
147a23fd118Syl  *             usage.
148a23fd118Syl  * @mempool: Memory pool, from which descriptors get allocated.
149*7eced415Sxw  * @align_size: TBD
150a23fd118Syl  *
151a23fd118Syl  * Fifo channel.
152a23fd118Syl  * Note: The structure is cache line aligned.
153a23fd118Syl  */
154a23fd118Syl typedef struct xge_hal_fifo_t {
155a23fd118Syl 	xge_hal_channel_t	channel;
156a23fd118Syl 	spinlock_t		*post_lock_ptr;
157a23fd118Syl 	xge_hal_fifo_hw_pair_t	*hw_pair;
158a23fd118Syl 	xge_hal_fifo_config_t	*config;
159a23fd118Syl 	int			no_snoop_bits;
160a23fd118Syl 	int			txdl_per_memblock;
161a23fd118Syl 	u64			interrupt_type;
162a23fd118Syl 	int			txdl_size;
163a23fd118Syl 	int			priv_size;
164a23fd118Syl 	xge_hal_mempool_t	*mempool;
1658347601bSyl 	int			align_size;
166a23fd118Syl } __xge_os_attr_cacheline_aligned xge_hal_fifo_t;
168a23fd118Syl /**
169a23fd118Syl  * struct xge_hal_fifo_txdl_priv_t - Transmit descriptor HAL-private
170a23fd118Syl  * data.
171a23fd118Syl  * @dma_addr: DMA (mapped) address of _this_ descriptor.
172a23fd118Syl  * @dma_handle: DMA handle used to map the descriptor onto device.
173a23fd118Syl  * @dma_offset: Descriptor's offset in the memory block. HAL allocates
174a23fd118Syl  * descriptors in memory blocks (see
175a23fd118Syl  * xge_hal_fifo_config_t{})
176a23fd118Syl  * Each memblock is a contiguous block of DMA-able memory.
177a23fd118Syl  * @frags: Total number of fragments (that is, contiguous data buffers)
178a23fd118Syl  * carried by this TxDL.
179a23fd118Syl  * @align_vaddr_start: (TODO).
180a23fd118Syl  * @align_vaddr: Virtual address of the per-TxDL area in memory used for
181a23fd118Syl  * alignement. Used to place one or more mis-aligned fragments
182a23fd118Syl  * (the maximum defined by configration variable
183a23fd118Syl  * @max_aligned_frags).
184a23fd118Syl  * @align_dma_addr: DMA address translated from the @align_vaddr.
185a23fd118Syl  * @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
186a23fd118Syl  * @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
187a23fd118Syl  * @align_dma_offset: The current offset into the @align_vaddr area.
188a23fd118Syl  * Grows while filling the descriptor, gets reset.
189a23fd118Syl  * @align_used_frags: (TODO).
190a23fd118Syl  * @alloc_frags: Total number of fragments allocated.
191a23fd118Syl  * @dang_frags: Number of fragments kept from release until this TxDL is freed.
192*7eced415Sxw  * @bytes_sent: TODO
193*7eced415Sxw  * @unused: TODO
194a23fd118Syl  * @dang_txdl: (TODO).
195a23fd118Syl  * @next_txdl_priv: (TODO).
196a23fd118Syl  * @first_txdp: (TODO).
197a23fd118Syl  * @dang_dtrh: Pointer to TxDL (list) kept from release until this TxDL
198a23fd118Syl  * is freed.
199a23fd118Syl  * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
200a23fd118Syl  * TxDL list.
201a23fd118Syl  * @dtrh: Corresponding dtrh to this TxDL.
202a23fd118Syl  * @memblock: Pointer to the TxDL memory block or memory page.
203a23fd118Syl  * on the next send operation.
204a23fd118Syl  * @dma_object: DMA address and handle of the memory block that contains
205a23fd118Syl  * the descriptor. This member is used only in the "checked"
206a23fd118Syl  * version of the HAL (to enforce certain assertions);
207a23fd118Syl  * otherwise it gets compiled out.
208a23fd118Syl  * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
209a23fd118Syl  *
210a23fd118Syl  * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
211a23fd118Syl  * information associated with the descriptor. Note that ULD can ask HAL
212a23fd118Syl  * to allocate additional per-descriptor space for its own (ULD-specific)
213a23fd118Syl  * purposes.
214a23fd118Syl  *
215a23fd118Syl  * See also: xge_hal_ring_rxd_priv_t{}.
216a23fd118Syl  */
217a23fd118Syl typedef struct xge_hal_fifo_txdl_priv_t {
218a23fd118Syl 	dma_addr_t				dma_addr;
219a23fd118Syl 	pci_dma_h				dma_handle;
220a23fd118Syl 	ptrdiff_t				dma_offset;
221a23fd118Syl 	int					frags;
222a23fd118Syl 	char					*align_vaddr_start;
223a23fd118Syl 	char					*align_vaddr;
224a23fd118Syl 	dma_addr_t				align_dma_addr;
225a23fd118Syl 	pci_dma_h				align_dma_handle;
226a23fd118Syl 	pci_dma_acc_h				align_dma_acch;
227a23fd118Syl 	ptrdiff_t				align_dma_offset;
228a23fd118Syl 	int					align_used_frags;
229a23fd118Syl 	int					alloc_frags;
230a23fd118Syl 	int					dang_frags;
2318347601bSyl 	unsigned int				bytes_sent;
2328347601bSyl 	int					unused;
233a23fd118Syl 	xge_hal_fifo_txd_t			*dang_txdl;
234a23fd118Syl 	struct xge_hal_fifo_txdl_priv_t		*next_txdl_priv;
235a23fd118Syl 	xge_hal_fifo_txd_t			*first_txdp;
236a23fd118Syl 	void					*memblock;
237a23fd118Syl #ifdef XGE_DEBUG_ASSERT
238a23fd118Syl 	xge_hal_mempool_dma_t			*dma_object;
239a23fd118Syl #endif
240a23fd118Syl #ifdef XGE_OS_MEMORY_CHECK
241a23fd118Syl 	int					allocated;
242a23fd118Syl #endif
243a23fd118Syl } xge_hal_fifo_txdl_priv_t;
245a23fd118Syl /**
246a23fd118Syl  * xge_hal_fifo_get_max_frags_cnt - Return the max fragments allocated
247a23fd118Syl  * for the fifo.
248a23fd118Syl  * @channelh: Channel handle.
249a23fd118Syl  */
250a23fd118Syl static inline int
xge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh)251a23fd118Syl xge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh)
252a23fd118Syl {
253a23fd118Syl 	return ((xge_hal_fifo_t *)channelh)->config->max_frags;
254a23fd118Syl }
255a23fd118Syl /* ========================= FIFO PRIVATE API ============================= */
257a23fd118Syl xge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh,
258a23fd118Syl 			xge_hal_channel_attr_t *attr);
260a23fd118Syl void __hal_fifo_close(xge_hal_channel_h channelh);
262a23fd118Syl void __hal_fifo_hw_initialize(xge_hal_device_h hldev);
264a23fd118Syl xge_hal_status_e
265a23fd118Syl __hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
267a23fd118Syl void
268a23fd118Syl __hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
270a23fd118Syl #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_FIFO)
271a23fd118Syl #define __HAL_STATIC_FIFO
272a23fd118Syl #define __HAL_INLINE_FIFO
274a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t*
275a23fd118Syl __hal_fifo_txdl_priv(xge_hal_dtr_h dtrh);
277a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
278a23fd118Syl __hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
279a23fd118Syl 			u64 ctrl_1);
280a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
281a23fd118Syl __hal_fifo_txdl_restore_many(xge_hal_channel_h channelh,
282a23fd118Syl 			  xge_hal_fifo_txd_t *txdp, int txdl_count);
284a23fd118Syl /* ========================= FIFO PUBLIC API ============================== */
286a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
287a23fd118Syl xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
289*7eced415Sxw __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
290*7eced415Sxw xge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
291*7eced415Sxw     const int frags);
293a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void*
294a23fd118Syl xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh);
296a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO int
297a23fd118Syl xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh);
299a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
300a23fd118Syl xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size,
301a23fd118Syl 			xge_hal_dtr_h dtr_sp);
303a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
304a23fd118Syl xge_hal_fifo_dtr_post(xge_hal_channel_h	channelh, xge_hal_dtr_h dtrh);
306a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
307a23fd118Syl xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num,
308a23fd118Syl 			xge_hal_dtr_h dtrs[]);
310a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
311a23fd118Syl xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
312a23fd118Syl 			u8 *t_code);
314a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
315a23fd118Syl xge_hal_fifo_dtr_free(xge_hal_channel_h	channelh, xge_hal_dtr_h dtr);
317a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
318a23fd118Syl xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
319a23fd118Syl 			int frag_idx, dma_addr_t dma_pointer, int size);
321a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
322a23fd118Syl xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh,
323a23fd118Syl 			xge_hal_dtr_h dtrh, int frag_idx, void *vaddr,
324a23fd118Syl 			dma_addr_t dma_pointer, int size, int misaligned_size);
326a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
327a23fd118Syl xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
328a23fd118Syl 		void *vaddr, int size);
330a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
331a23fd118Syl xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
332a23fd118Syl 		int frag_idx);
334a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
335a23fd118Syl xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss);
337a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
338a23fd118Syl xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits);
340a23fd118Syl __HAL_STATIC_FIFO __HAL_INLINE_FIFO void
341a23fd118Syl xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h	dtrh, u16 vlan_tag);
3438347601bSyl __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
3448347601bSyl xge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh);
346a23fd118Syl #else /* XGE_FASTPATH_EXTERN */
347a23fd118Syl #define __HAL_STATIC_FIFO static
348a23fd118Syl #define __HAL_INLINE_FIFO inline
349a23fd118Syl #include "xgehal-fifo-fp.c"
350a23fd118Syl #endif /* XGE_FASTPATH_INLINE */
3528347601bSyl __EXTERN_END_DECLS
354a23fd118Syl #endif /* XGE_HAL_FIFO_H */