xref: /illumos-gate/usr/src/uts/common/io/xge/hal/include/xgehal-device.h (revision a23fd118e437af0a7877dd313db8fdaa3537c675)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  *  Copyright (c) 2002-2005 Neterion, Inc.
24  *  All right Reserved.
25  *
26  *  FileName :    xgehal-device.h
27  *
28  *  Description:  HAL device object functionality
29  *
30  *  Created:      14 May 2004
31  */
32 
33 #ifndef XGE_HAL_DEVICE_H
34 #define XGE_HAL_DEVICE_H
35 
36 #include "xge-os-pal.h"
37 #include "xge-queue.h"
38 #include "xgehal-event.h"
39 #include "xgehal-config.h"
40 #include "xgehal-regs.h"
41 #include "xgehal-channel.h"
42 #include "xgehal-stats.h"
43 
44 #define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS		500
45 #define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS		500
46 #define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS	500
47 #define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS		50
48 #define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS		250
49 #define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS	250  /* TODO */
50 #define XGE_HAL_MAX_MSIX_MESSAGES 64
51 
52 #define XGE_HAL_MAGIC					0x12345678
53 #define XGE_HAL_DEAD					0xDEADDEAD
54 #define XGE_HAL_DUMP_BUF_SIZE                           0x4000
55 
56 #define XGE_HAL_MAX_LRO_SESSIONS			15
57 
58 /**
59  * enum xge_hal_card_e - Xframe adapter type.
60  * @XGE_HAL_CARD_UNKNOWN: Unknown device.
61  * @XGE_HAL_CARD_XENA: Xframe I device.
62  * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
63  *
64  * Enumerates Xframe adapter types. The corresponding PCI device
65  * IDs are listed in the file xgehal-defs.h.
66  * (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
67  *
68  * See also: xge_hal_device_check_id().
69  */
70 typedef enum xge_hal_card_e {
71 	XGE_HAL_CARD_UNKNOWN	= 0,
72 	XGE_HAL_CARD_XENA	= 1,
73 	XGE_HAL_CARD_HERC	= 2,
74 } xge_hal_card_e;
75 
76 /**
77  * struct xge_hal_device_attr_t - Device memory spaces.
78  * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
79  *         (Linux and the rest.)
80  * @regh1: BAR1 mapped memory handle. Same comment as above.
81  * @bar0: BAR0 virtual address.
82  * @bar1: BAR1 virtual address.
83  * @bar2: BAR2 virtual address.
84  * @irqh: IRQ handle (Solaris).
85  * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
86  * @pdev: PCI device object.
87  *
88  * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
89  * mapped memories. Also, includes a pointer to OS-specific PCI device object.
90  */
91 typedef struct xge_hal_device_attr_t {
92 	pci_reg_h		regh0;
93 	pci_reg_h		regh1;
94 	pci_reg_h		regh2;
95 	char			*bar0;
96 	char			*bar1;
97 	char			*bar2;
98 	pci_irq_h		irqh;
99 	pci_cfg_h		cfgh;
100 	pci_dev_h		pdev;
101 } xge_hal_device_attr_t;
102 
103 /**
104  * enum xge_hal_device_link_state_e - Link state enumeration.
105  * @XGE_HAL_LINK_NONE: Invalid link state.
106  * @XGE_HAL_LINK_DOWN: Link is down.
107  * @XGE_HAL_LINK_UP: Link is up.
108  *
109  */
110 typedef enum xge_hal_device_link_state_e {
111 	XGE_HAL_LINK_NONE,
112 	XGE_HAL_LINK_DOWN,
113 	XGE_HAL_LINK_UP
114 } xge_hal_device_link_state_e;
115 
116 
117 /**
118  * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
119  * @XGE_HAL_PCI_33MHZ_MODE:		33 MHZ pci mode.
120  * @XGE_HAL_PCI_66MHZ_MODE:		66 MHZ pci mode.
121  * @XGE_HAL_PCIX_M1_66MHZ_MODE:		PCIX M1 66MHZ mode.
122  * @XGE_HAL_PCIX_M1_100MHZ_MODE:	PCIX M1 100MHZ mode.
123  * @XGE_HAL_PCIX_M1_133MHZ_MODE:	PCIX M1 133MHZ mode.
124  * @XGE_HAL_PCIX_M2_66MHZ_MODE:		PCIX M2 66MHZ mode.
125  * @XGE_HAL_PCIX_M2_100MHZ_MODE:	PCIX M2 100MHZ mode.
126  * @XGE_HAL_PCIX_M2_133MHZ_MODE:	PCIX M3 133MHZ mode.
127  * @XGE_HAL_PCIX_M1_RESERVED:		PCIX M1 reserved mode.
128  * @XGE_HAL_PCIX_M1_66MHZ_NS:		PCIX M1 66MHZ mode not supported.
129  * @XGE_HAL_PCIX_M1_100MHZ_NS:		PCIX M1 100MHZ mode not supported.
130  * @XGE_HAL_PCIX_M1_133MHZ_NS:		PCIX M1 133MHZ not supported.
131  * @XGE_HAL_PCIX_M2_RESERVED:		PCIX M2 reserved.
132  * @XGE_HAL_PCIX_533_RESERVED:		PCIX 533 reserved.
133  * @XGE_HAL_PCI_BASIC_MODE:		PCI basic mode, XENA specific value.
134  * @XGE_HAL_PCIX_BASIC_MODE:		PCIX basic mode, XENA specific value.
135  * @XGE_HAL_PCI_INVALID_MODE:		Invalid PCI or PCIX mode.
136  *
137  */
138 typedef enum xge_hal_pci_mode_e {
139 	XGE_HAL_PCI_33MHZ_MODE		= 0x0,
140 	XGE_HAL_PCI_66MHZ_MODE		= 0x1,
141 	XGE_HAL_PCIX_M1_66MHZ_MODE	= 0x2,
142 	XGE_HAL_PCIX_M1_100MHZ_MODE	= 0x3,
143 	XGE_HAL_PCIX_M1_133MHZ_MODE	= 0x4,
144 	XGE_HAL_PCIX_M2_66MHZ_MODE	= 0x5,
145 	XGE_HAL_PCIX_M2_100MHZ_MODE	= 0x6,
146 	XGE_HAL_PCIX_M2_133MHZ_MODE	= 0x7,
147 	XGE_HAL_PCIX_M1_RESERVED	= 0x8,
148 	XGE_HAL_PCIX_M1_66MHZ_NS	= 0xA,
149 	XGE_HAL_PCIX_M1_100MHZ_NS	= 0xB,
150 	XGE_HAL_PCIX_M1_133MHZ_NS	= 0xC,
151 	XGE_HAL_PCIX_M2_RESERVED	= 0xD,
152 	XGE_HAL_PCIX_533_RESERVED	= 0xE,
153 	XGE_HAL_PCI_BASIC_MODE		= 0x10,
154 	XGE_HAL_PCIX_BASIC_MODE		= 0x11,
155 	XGE_HAL_PCI_INVALID_MODE	= 0x12,
156 } xge_hal_pci_mode_e;
157 
158 /**
159  * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
160  * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ:	PCI bus frequency 33MHZ
161  * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ:	PCI bus frequency 66MHZ
162  * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ:	PCI bus frequency 100MHZ
163  * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ:	PCI bus frequency 133MHZ
164  * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ:	PCI bus frequency 266MHZ
165  * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN:	Unrecognized PCI bus frequency value.
166  *
167  */
168 typedef enum xge_hal_pci_bus_frequency_e {
169 	XGE_HAL_PCI_BUS_FREQUENCY_33MHZ		= 33,
170 	XGE_HAL_PCI_BUS_FREQUENCY_66MHZ		= 66,
171 	XGE_HAL_PCI_BUS_FREQUENCY_100MHZ	= 100,
172 	XGE_HAL_PCI_BUS_FREQUENCY_133MHZ	= 133,
173 	XGE_HAL_PCI_BUS_FREQUENCY_200MHZ	= 200,
174 	XGE_HAL_PCI_BUS_FREQUENCY_266MHZ	= 266,
175 	XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN	= 0
176 } xge_hal_pci_bus_frequency_e;
177 
178 /**
179  * enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
180  * @XGE_HAL_PCI_BUS_WIDTH_64BIT:	64 bit bus width.
181  * @XGE_HAL_PCI_BUS_WIDTH_32BIT:	32 bit bus width.
182  * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN:  unknown bus width.
183  *
184  */
185 typedef enum xge_hal_pci_bus_width_e {
186 	XGE_HAL_PCI_BUS_WIDTH_64BIT	= 0,
187 	XGE_HAL_PCI_BUS_WIDTH_32BIT	= 1,
188 	XGE_HAL_PCI_BUS_WIDTH_UNKNOWN	= 2,
189 } xge_hal_pci_bus_width_e;
190 
191 #if defined (XGE_HAL_CONFIG_LRO)
192 
193 #define IP_TOTAL_LENGTH_OFFSET			2
194 #define IP_FAST_PATH_HDR_MASK			0x45
195 #define TCP_FAST_PATH_HDR_MASK1			0x50
196 #define TCP_FAST_PATH_HDR_MASK2			0x10
197 #define TCP_FAST_PATH_HDR_MASK3			0x18
198 #define IP_SOURCE_ADDRESS_OFFSET		12
199 #define IP_DESTINATION_ADDRESS_OFFSET		16
200 #define TCP_DESTINATION_PORT_OFFSET		2
201 #define TCP_SOURCE_PORT_OFFSET			0
202 #define TCP_DATA_OFFSET_OFFSET			12
203 #define TCP_WINDOW_OFFSET			14
204 #define TCP_SEQUENCE_NUMBER_OFFSET		4
205 #define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET	8
206 
207 typedef struct tcplro {
208 	u16   source;
209 	u16   dest;
210 	u32   seq;
211 	u32   ack_seq;
212 	u8    doff_res;
213 	u8    ctrl;
214 	u16   window;
215 	u16   check;
216 	u16   urg_ptr;
217 } tcplro_t;
218 
219 typedef struct iplro {
220 	u8    version_ihl;
221 	u8    tos;
222 	u16   tot_len;
223 	u16   id;
224 	u16   frag_off;
225 	u8    ttl;
226 	u8    protocol;
227 	u16   check;
228 	u32   saddr;
229 	u32   daddr;
230 	/*The options start here. */
231 } iplro_t;
232 
233 /*
234  * LRO object, one per each LRO session.
235 */
236 typedef struct lro {
237 	/* non-linear: contains scatter-gather list of
238 	xframe-mapped received buffers */
239 	OS_NETSTACK_BUF		os_buf;
240 	OS_NETSTACK_BUF		os_buf_end;
241 
242 	/* link layer header of the first frame;
243 	remains intack throughout the processing */
244 	u8			*ll_hdr;
245 
246 	/* IP header - gets _collapsed_ */
247 	iplro_t			*ip_hdr;
248 
249 	/* transport header - gets _collapsed_ */
250 	tcplro_t		*tcp_hdr;
251 
252 	/* Next tcp sequence number */
253 	u32			tcp_next_seq_num;
254 	/* Current tcp seq & ack */
255 	u32			tcp_seq_num;
256 	u32			tcp_ack_num;
257 
258 	/* total number of accumulated (so far) frames */
259 	int			sg_num;
260 
261 	/* total data length */
262 	int			total_length;
263 
264 	/* receive side hash value, available from Hercules */
265 	u32			rth_value;
266 
267 	/* In use */
268 	u8			in_use;
269 
270 	/* Total length of the fragments clubbed with the inital frame */
271 	u32			frags_len;
272 } lro_t;
273 #endif
274 
275 /*
276  * xge_hal_spdm_entry_t
277  *
278  * Represents a single spdm entry in the SPDM table.
279  */
280 typedef struct xge_hal_spdm_entry_t {
281 	xge_hal_ipaddr_t  src_ip;
282 	xge_hal_ipaddr_t  dst_ip;
283 	u32 jhash_value;
284 	u16 l4_sp;
285 	u16 l4_dp;
286 	u16 spdm_entry;
287 	u8  in_use;
288 	u8  is_tcp;
289 	u8  is_ipv4;
290 	u8  tgt_queue;
291 } xge_hal_spdm_entry_t;
292 
293 
294 /*
295  * xge_hal_device_t
296  *
297  * HAL device object. Represents Xframe.
298  */
299 typedef struct {
300 	int			magic;
301 	pci_reg_h		regh0;
302 	pci_reg_h		regh1;
303 	pci_reg_h		regh2;
304 	char			*bar0;
305 	char			*isrbar0;
306 	char			*bar1;
307 	char			*bar2;
308 	pci_irq_h		irqh;
309 	pci_cfg_h		cfgh;
310 	pci_dev_h		pdev;
311 	xge_hal_pci_config_t	pci_config_space;
312 #if defined(XGE_HAL_MSI_X)
313 	u64					msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES * 2];
314 #endif
315 	xge_hal_device_config_t	config;
316 	xge_list_t		free_channels;
317 	xge_list_t		fifo_channels;
318 	xge_list_t		ring_channels;
319 	volatile int		is_initialized;
320 	volatile int		terminating;
321 	xge_hal_stats_t		stats;
322 	macaddr_t		macaddr[1];
323 	xge_queue_h		queueh;
324 	volatile int		mcast_refcnt;
325 	int			is_promisc;
326 	volatile xge_hal_device_link_state_e	link_state;
327 	void			*upper_layer_info;
328 	xge_hal_device_attr_t	orig_attr;
329 	u16			device_id;
330 	u8			revision;
331 	int			msi_enabled;
332 	int			hw_is_initialized;
333 	u64			inject_serr;
334 	u64			inject_ecc;
335 	u8			inject_bad_tcode;
336 	int			inject_bad_tcode_for_chan_type;
337         int                     reset_needed_after_close;
338 	char			*spdm_mem_base;
339 	u16			spdm_max_entries;
340 	xge_hal_spdm_entry_t	**spdm_table;
341 	spinlock_t		spdm_lock;
342 #if defined(XGE_HAL_MSI)
343 	u32			msi_mask;
344 #endif
345 #if defined(XGE_HAL_CONFIG_LRO)
346 	lro_t			g_lro_pool[XGE_HAL_MAX_LRO_SESSIONS];
347 #endif
348 	spinlock_t		xena_post_lock;
349 	u64			rxufca_lbolt;
350 	u64			rxufca_lbolt_time;
351 	u64			rxufca_intr_thres;
352 	char*                   dump_buf;
353 	int			mtu_first_time_set;
354 	xge_hal_pci_mode_e	pci_mode;
355 	xge_hal_pci_bus_frequency_e bus_frequency;
356 	xge_hal_pci_bus_width_e	bus_width;
357 	volatile int		in_poll;
358 } xge_hal_device_t;
359 
360 
361 /* ========================== PRIVATE API ================================= */
362 
363 void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
364 			void *addr);
365 
366 void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
367 			void *addr);
368 
369 xge_hal_status_e
370 __hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
371 
372 xge_hal_status_e
373 __hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
374 
375 xge_hal_status_e
376 __hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
377 
378 xge_hal_status_e
379 __hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
380 
381 xge_hal_status_e
382 __hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
383 
384 xge_hal_status_e
385 __hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
386 
387 xge_hal_status_e
388 __hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
389 
390 xge_hal_status_e
391 __hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
392 
393 xge_hal_status_e
394 __hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
395 
396 xge_hal_status_e
397 __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
398 			int max_millis);
399 xge_hal_status_e
400 __hal_device_rts_mac_configure(xge_hal_device_t *hldev);
401 
402 /* =========================== PUBLIC API ================================= */
403 
404 unsigned int
405 __hal_fix_time_ival_herc(xge_hal_device_t *hldev,
406 			 unsigned int time_ival);
407 xge_hal_status_e
408 xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
409 		u32 itable_size);
410 
411 void
412 xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
413 		u16 bucket_size);
414 
415 void
416 xge_hal_rts_rth_init(xge_hal_device_t *hldev);
417 
418 void
419 xge_hal_rts_rth_clr(xge_hal_device_t *hldev);
420 
421 void
422 xge_hal_rts_rth_start(xge_hal_device_t *hldev);
423 
424 void
425 xge_hal_rts_rth_stop(xge_hal_device_t *hldev);
426 
427 void
428 xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
429 
430 xge_hal_status_e
431 xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
432 
433 xge_hal_status_e
434 xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
435 
436 
437 /**
438  * xge_hal_device_is_initialized - Returns 0 if device is not
439  * initialized, non-zero otherwise.
440  * @devh: HAL device handle.
441  *
442  * Returns 0 if device is not initialized, non-zero otherwise.
443  */
444 static inline int
445 xge_hal_device_is_initialized(xge_hal_device_h devh)
446 {
447 	return ((xge_hal_device_t*)devh)->is_initialized;
448 }
449 
450 
451 /**
452  * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
453  * @devh: HAL device handle.
454  *
455  * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
456  */
457 static inline int
458 xge_hal_device_in_poll(xge_hal_device_h devh)
459 {
460 	return ((xge_hal_device_t*)devh)->in_poll;
461 }
462 
463 
464 /**
465  * xge_hal_device_inject_ecc - Inject ECC error.
466  * @devh: HAL device, pointer to xge_hal_device_t structure.
467  * @err_reg: Contains the error register.
468  *
469  * This function is used to inject ECC error into the driver flow.
470  * This facility can be used to test the driver flow in the
471  * case of ECC error is reported by the firmware.
472  *
473  * Returns: void
474  * See also: xge_hal_device_inject_serr(),
475  * xge_hal_device_inject_bad_tcode()
476  */
477 static inline void
478 xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
479 {
480         ((xge_hal_device_t*)devh)->inject_ecc = err_reg;
481 }
482 
483 
484 /**
485  * xge_hal_device_inject_serr - Inject SERR error.
486  * @devh: HAL device, pointer to xge_hal_device_t structure.
487  * @err_reg: Contains the error register.
488  *
489  * This function is used to inject SERR error into the driver flow.
490  * This facility can be used to test the driver flow in the
491  * case of SERR error is reported by firmware.
492  *
493  * Returns: void
494  * See also: xge_hal_device_inject_ecc(),
495  * xge_hal_device_inject_bad_tcode()
496  */
497 static inline void
498 xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
499 {
500         ((xge_hal_device_t*)devh)->inject_serr = err_reg;
501 }
502 
503 
504 /**
505  * xge_hal_device_inject_bad_tcode - Inject  Bad transfer code.
506  * @devh: HAL device, pointer to xge_hal_device_t structure.
507  * @chan_type: Channel type (fifo/ring).
508  * @t_code: Transfer code.
509  *
510  * This function is used to inject bad (Tx/Rx Data)transfer code
511  * into the driver flow.
512  *
513  * This facility can be used to test the driver flow in the
514  * case of bad transfer code reported by firmware for a Tx/Rx data
515  * transfer.
516  *
517  * Returns: void
518  * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
519  */
520 static inline void
521 xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
522 {
523         ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
524         ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
525 }
526 
527 void xge_hal_device_msi_enable(xge_hal_device_h	devh);
528 
529 /*
530  * xge_hal_device_msi_mode - Is MSI enabled?
531  * @devh: HAL device handle.
532  *
533  * Returns 0 if MSI is enabled for the specified device,
534  * non-zero otherwise.
535  */
536 static inline int
537 xge_hal_device_msi_mode(xge_hal_device_h devh)
538 {
539 	return ((xge_hal_device_t*)devh)->msi_enabled;
540 }
541 
542 /**
543  * xge_hal_device_queue - Get per-device event queue.
544  * @devh: HAL device handle.
545  *
546  * Returns: event queue associated with the specified HAL device.
547  */
548 static inline xge_queue_h
549 xge_hal_device_queue (xge_hal_device_h devh)
550 {
551 	return ((xge_hal_device_t*)devh)->queueh;
552 }
553 
554 /**
555  * xge_hal_device_attr - Get original (user-specified) device
556  * attributes.
557  * @devh: HAL device handle.
558  *
559  * Returns: original (user-specified) device attributes.
560  */
561 static inline xge_hal_device_attr_t*
562 xge_hal_device_attr(xge_hal_device_h devh)
563 {
564 	return &((xge_hal_device_t*)devh)->orig_attr;
565 }
566 
567 /**
568  * xge_hal_device_private_set - Set ULD context.
569  * @devh: HAL device handle.
570  * @data: pointer to ULD context
571  *
572  * Use HAL device to set upper-layer driver (ULD) context.
573  *
574  * See also: xge_hal_device_from_private(), xge_hal_device_private()
575  */
576 static inline void
577 xge_hal_device_private_set(xge_hal_device_h devh, void *data)
578 {
579 	((xge_hal_device_t*)devh)->upper_layer_info = data;
580 }
581 
582 /**
583  * xge_hal_device_private - Get ULD context.
584  * @devh: HAL device handle.
585  *
586  * Use HAL device to get upper-layer driver (ULD) context.
587  *
588  * Returns:  ULD context.
589  *
590  * See also: xge_hal_device_from_private(), xge_hal_device_private_set()
591  */
592 static inline void*
593 xge_hal_device_private(xge_hal_device_h devh)
594 {
595 	return ((xge_hal_device_t*)devh)->upper_layer_info;
596 }
597 
598 /**
599  * xge_hal_device_from_private - Get HAL device object from private.
600  * @info_ptr: ULD context.
601  *
602  * Use ULD context to get HAL device.
603  *
604  * Returns:  Device handle.
605  *
606  * See also: xge_hal_device_private(), xge_hal_device_private_set()
607  */
608 static inline xge_hal_device_h
609 xge_hal_device_from_private(void *info_ptr)
610 {
611 	return xge_container_of(info_ptr, xge_hal_device_t,
612 	upper_layer_info);
613 }
614 
615 /**
616  * xge_hal_device_mtu_check - check MTU value for ranges
617  * @hldev: the device
618  * @new_mtu: new MTU value to check
619  *
620  * Will do sanity check for new MTU value.
621  *
622  * Returns: XGE_HAL_OK - success.
623  * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
624  *
625  * See also: xge_hal_device_mtu_set()
626  */
627 static inline xge_hal_status_e
628 xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
629 {
630 	if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
631 		return XGE_HAL_ERR_INVALID_MTU_SIZE;
632 	}
633 
634 	return XGE_HAL_OK;
635 }
636 
637 void xge_hal_device_bcast_enable(xge_hal_device_h devh);
638 
639 void xge_hal_device_bcast_disable(xge_hal_device_h devh);
640 
641 void xge_hal_device_terminating(xge_hal_device_h devh);
642 
643 xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
644 		xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
645 
646 void xge_hal_device_terminate(xge_hal_device_t *hldev);
647 
648 xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
649 
650 xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
651 		int index,  macaddr_t *macaddr);
652 
653 xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
654 		int index,  macaddr_t macaddr);
655 
656 int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
657 
658 xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
659 
660 xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
661 
662 void xge_hal_device_intr_enable(xge_hal_device_t *hldev);
663 
664 void xge_hal_device_intr_disable(xge_hal_device_t *hldev);
665 
666 xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
667 
668 xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
669 
670 void xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
671 
672 void xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
673 
674 xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
675 
676 xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
677 
678 xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
679 					     xge_hal_dtr_h dtrh,
680 					     u8 t_code);
681 
682 xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
683 			xge_hal_device_link_state_e *ls);
684 
685 void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
686 			int one_shot);
687 
688 void xge_hal_device_poll(xge_hal_device_h devh);
689 
690 xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
691 
692 int xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
693 
694 xge_hal_status_e
695 xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
696 			xge_hal_pci_bus_frequency_e *bus_frequency,
697 			xge_hal_pci_bus_width_e *bus_width);
698 
699 xge_hal_status_e
700 xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
701 			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
702 			u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
703 
704 xge_hal_status_e
705 xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
706 			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
707 			u8 is_tcp, u8 is_ipv4);
708 
709 u32 __hal_calc_jhash(u8 *msg, u32 length, u32 golden_ratio, u32 init_value);
710 
711 int
712 xge_hal_device_is_closed (xge_hal_device_h devh);
713 
714 #if defined(XGE_HAL_MSI)
715 /* Some function protoypes for MSI implementation. */
716 xge_hal_status_e
717 xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi, u32
718 msg_val);
719 void
720 xge_hal_mask_msi(xge_hal_device_t *hldev);
721 void
722 xge_hal_unmask_msi(xge_hal_channel_h channelh);
723 #endif
724 #if defined(XGE_HAL_MSI_X)
725 xge_hal_status_e
726 xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
727 #endif
728 
729 
730 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
731 #define __HAL_STATIC_DEVICE
732 #define __HAL_INLINE_DEVICE
733 
734 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
735 xge_hal_device_rev(xge_hal_device_t *hldev);
736 
737 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
738 xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
739 
740 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
741 xge_hal_device_clear_rx(xge_hal_device_t *hldev);
742 
743 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
744 xge_hal_device_clear_tx(xge_hal_device_t *hldev);
745 
746 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
747 xge_hal_device_continue_irq(xge_hal_device_t *hldev);
748 
749 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
750 xge_hal_device_handle_irq(xge_hal_device_t *hldev);
751 
752 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
753 xge_hal_device_bar0(xge_hal_device_t *hldev);
754 
755 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
756 xge_hal_device_isrbar0(xge_hal_device_t *hldev);
757 
758 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
759 xge_hal_device_bar1(xge_hal_device_t *hldev);
760 
761 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
762 xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
763 
764 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
765 xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0);
766 
767 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
768 xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh,
769 		char *bar1);
770 
771 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
772 xge_hal_device_mask_tx(xge_hal_device_t *hldev);
773 
774 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
775 xge_hal_device_mask_rx(xge_hal_device_t *hldev);
776 
777 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
778 xge_hal_device_mask_all(xge_hal_device_t *hldev);
779 
780 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
781 xge_hal_device_unmask_tx(xge_hal_device_t *hldev);
782 
783 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
784 xge_hal_device_unmask_rx(xge_hal_device_t *hldev);
785 
786 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
787 xge_hal_device_unmask_all(xge_hal_device_t *hldev);
788 
789 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
790 xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev);
791 
792 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
793 xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev);
794 
795 #if defined (XGE_HAL_CONFIG_LRO)
796 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8
797 __hal_header_parse_token_u8(u8 *string,u16 offset);
798 
799 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
800 __hal_header_parse_token_u16(u8 *string,u16 offset);
801 
802 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32
803 __hal_header_parse_token_u32(u8 *string,u16 offset);
804 
805 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
806 __hal_header_update_u8(u8 *string, u16 offset, u8 val);
807 
808 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
809 __hal_header_update_u16(u8 *string, u16 offset, u16 val);
810 
811 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
812 __hal_header_update_u32(u8 *string, u16 offset, u32 val);
813 
814 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
815 __hal_tcp_seg_len(u8 *ip, u8 *tcp);
816 
817 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
818 __hal_ip_lro_capable(u8 *ip, xge_hal_dtr_info_t *ext_info);
819 
820 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
821 __hal_tcp_lro_capable(u8 *ip, u8 *tcp);
822 
823 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
824 __hal_lro_capable(u8 *buffer, u8 **ip, u8 **tcp, xge_hal_dtr_info_t *ext_info,
825 		xge_hal_device_t *hldev);
826 
827 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
828 __hal_get_lro_session(u8 *buffer, u8 *ip, u8 *tcp, lro_t **lro,
829 		xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev);
830 
831 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
832 __hal_lro_under_optimal_thresh(u8 *ip, u8 *tcp, lro_t *lro,
833 		xge_hal_device_t *hldev);
834 
835 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
836 __hal_collapse_ip_hdr(u8 *ip, u8 *tcp, lro_t *lro, xge_hal_device_t *hldev);
837 
838 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
839 __hal_collapse_tcp_hdr(u8 *ip, u8 *tcp, lro_t *lro, xge_hal_device_t *hldev);
840 
841 
842 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
843 __hal_append_lro(u8 *ip, u8 *tcp, u32 *seg_len, lro_t *lro,
844 		xge_hal_device_t *hldev);
845 
846 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
847 xge_hal_accumulate_large_rx(u8 *buffer, u8 **tcp, u32 *seglen, lro_t **lro,
848 		xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev);
849 
850 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
851 xge_hal_lro_free(lro_t *lro, xge_hal_device_t *hldev);
852 
853 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
854 __hal_lro_malloc(xge_hal_device_t *hldev);
855 
856 void
857 xge_hal_lro_terminate(u32 lro_scale xge_hal_device_t *hldev);
858 
859 xge_hal_status_e
860 xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
861 #endif
862 
863 #else /* XGE_FASTPATH_EXTERN */
864 #define __HAL_STATIC_DEVICE static
865 #define __HAL_INLINE_DEVICE inline
866 #include "xgehal-device-fp.c"
867 #endif /* XGE_FASTPATH_INLINE */
868 
869 #endif /* XGE_HAL_DEVICE_H */
870