1a23fd118Syl /* 2a23fd118Syl * CDDL HEADER START 3a23fd118Syl * 4a23fd118Syl * The contents of this file are subject to the terms of the 5a23fd118Syl * Common Development and Distribution License (the "License"). 6a23fd118Syl * You may not use this file except in compliance with the License. 7a23fd118Syl * 8a23fd118Syl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9a23fd118Syl * or http://www.opensolaris.org/os/licensing. 10a23fd118Syl * See the License for the specific language governing permissions 11a23fd118Syl * and limitations under the License. 12a23fd118Syl * 13a23fd118Syl * When distributing Covered Code, include this CDDL HEADER in each 14a23fd118Syl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15a23fd118Syl * If applicable, add the following below this CDDL HEADER, with the 16a23fd118Syl * fields enclosed by brackets "[]" replaced with your own identifying 17a23fd118Syl * information: Portions Copyright [yyyy] [name of copyright owner] 18a23fd118Syl * 19a23fd118Syl * CDDL HEADER END 20a23fd118Syl * 218347601bSyl * Copyright (c) 2002-2006 Neterion, Inc. 22a23fd118Syl */ 23a23fd118Syl 24a23fd118Syl #ifndef XGE_HAL_DEVICE_H 25a23fd118Syl #define XGE_HAL_DEVICE_H 26a23fd118Syl 27a23fd118Syl #include "xge-os-pal.h" 28a23fd118Syl #include "xge-queue.h" 29a23fd118Syl #include "xgehal-event.h" 30a23fd118Syl #include "xgehal-config.h" 31a23fd118Syl #include "xgehal-regs.h" 32a23fd118Syl #include "xgehal-channel.h" 33a23fd118Syl #include "xgehal-stats.h" 348347601bSyl #include "xgehal-ring.h" 358347601bSyl 368347601bSyl __EXTERN_BEGIN_DECLS 37a23fd118Syl 38*7eced415Sxw #define XGE_HAL_VPD_LENGTH 80 39*7eced415Sxw #define XGE_HAL_CARD_XENA_VPD_ADDR 0x50 40*7eced415Sxw #define XGE_HAL_CARD_HERC_VPD_ADDR 0x80 41*7eced415Sxw #define XGE_HAL_VPD_READ_COMPLETE 0x80 42*7eced415Sxw #define XGE_HAL_VPD_BUFFER_SIZE 128 43a23fd118Syl #define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500 44a23fd118Syl #define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500 45a23fd118Syl #define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500 46a23fd118Syl #define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50 47a23fd118Syl #define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250 48a23fd118Syl #define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */ 49a23fd118Syl 50a23fd118Syl #define XGE_HAL_MAGIC 0x12345678 51a23fd118Syl #define XGE_HAL_DEAD 0xDEADDEAD 52a23fd118Syl #define XGE_HAL_DUMP_BUF_SIZE 0x4000 53a23fd118Syl 548347601bSyl #define XGE_HAL_LRO_MAX_BUCKETS 32 55a23fd118Syl 56a23fd118Syl /** 57a23fd118Syl * enum xge_hal_card_e - Xframe adapter type. 58a23fd118Syl * @XGE_HAL_CARD_UNKNOWN: Unknown device. 59a23fd118Syl * @XGE_HAL_CARD_XENA: Xframe I device. 60a23fd118Syl * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device. 61*7eced415Sxw * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device. 62a23fd118Syl * 63a23fd118Syl * Enumerates Xframe adapter types. The corresponding PCI device 64a23fd118Syl * IDs are listed in the file xgehal-defs.h. 65a23fd118Syl * (See XGE_PCI_DEVICE_ID_XENA_1, etc.) 66a23fd118Syl * 67a23fd118Syl * See also: xge_hal_device_check_id(). 68a23fd118Syl */ 69a23fd118Syl typedef enum xge_hal_card_e { 70a23fd118Syl XGE_HAL_CARD_UNKNOWN = 0, 71a23fd118Syl XGE_HAL_CARD_XENA = 1, 72a23fd118Syl XGE_HAL_CARD_HERC = 2, 73*7eced415Sxw XGE_HAL_CARD_TITAN = 3, 74a23fd118Syl } xge_hal_card_e; 75a23fd118Syl 76a23fd118Syl /** 77a23fd118Syl * struct xge_hal_device_attr_t - Device memory spaces. 78a23fd118Syl * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 79a23fd118Syl * (Linux and the rest.) 80a23fd118Syl * @regh1: BAR1 mapped memory handle. Same comment as above. 81a23fd118Syl * @bar0: BAR0 virtual address. 82a23fd118Syl * @bar1: BAR1 virtual address. 83a23fd118Syl * @irqh: IRQ handle (Solaris). 84a23fd118Syl * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux). 85a23fd118Syl * @pdev: PCI device object. 86a23fd118Syl * 87a23fd118Syl * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device 88a23fd118Syl * mapped memories. Also, includes a pointer to OS-specific PCI device object. 89a23fd118Syl */ 90a23fd118Syl typedef struct xge_hal_device_attr_t { 91a23fd118Syl pci_reg_h regh0; 92a23fd118Syl pci_reg_h regh1; 93a23fd118Syl pci_reg_h regh2; 94a23fd118Syl char *bar0; 95a23fd118Syl char *bar1; 96a23fd118Syl char *bar2; 97a23fd118Syl pci_irq_h irqh; 98a23fd118Syl pci_cfg_h cfgh; 99a23fd118Syl pci_dev_h pdev; 100a23fd118Syl } xge_hal_device_attr_t; 101a23fd118Syl 102a23fd118Syl /** 103a23fd118Syl * enum xge_hal_device_link_state_e - Link state enumeration. 104a23fd118Syl * @XGE_HAL_LINK_NONE: Invalid link state. 105a23fd118Syl * @XGE_HAL_LINK_DOWN: Link is down. 106a23fd118Syl * @XGE_HAL_LINK_UP: Link is up. 107a23fd118Syl * 108a23fd118Syl */ 109a23fd118Syl typedef enum xge_hal_device_link_state_e { 110a23fd118Syl XGE_HAL_LINK_NONE, 111a23fd118Syl XGE_HAL_LINK_DOWN, 112a23fd118Syl XGE_HAL_LINK_UP 113a23fd118Syl } xge_hal_device_link_state_e; 114a23fd118Syl 115a23fd118Syl 116a23fd118Syl /** 117a23fd118Syl * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration. 118a23fd118Syl * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode. 119a23fd118Syl * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode. 120a23fd118Syl * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode. 121a23fd118Syl * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode. 122a23fd118Syl * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode. 123a23fd118Syl * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode. 124a23fd118Syl * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode. 125a23fd118Syl * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode. 126a23fd118Syl * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode. 127a23fd118Syl * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported. 128a23fd118Syl * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported. 129a23fd118Syl * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported. 130a23fd118Syl * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved. 131a23fd118Syl * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved. 132a23fd118Syl * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value. 133a23fd118Syl * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value. 134a23fd118Syl * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode. 135a23fd118Syl * 136a23fd118Syl */ 137a23fd118Syl typedef enum xge_hal_pci_mode_e { 138a23fd118Syl XGE_HAL_PCI_33MHZ_MODE = 0x0, 139a23fd118Syl XGE_HAL_PCI_66MHZ_MODE = 0x1, 140a23fd118Syl XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2, 141a23fd118Syl XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3, 142a23fd118Syl XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4, 143a23fd118Syl XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5, 144a23fd118Syl XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6, 145a23fd118Syl XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7, 146a23fd118Syl XGE_HAL_PCIX_M1_RESERVED = 0x8, 147a23fd118Syl XGE_HAL_PCIX_M1_66MHZ_NS = 0xA, 148a23fd118Syl XGE_HAL_PCIX_M1_100MHZ_NS = 0xB, 149a23fd118Syl XGE_HAL_PCIX_M1_133MHZ_NS = 0xC, 150a23fd118Syl XGE_HAL_PCIX_M2_RESERVED = 0xD, 151a23fd118Syl XGE_HAL_PCIX_533_RESERVED = 0xE, 152a23fd118Syl XGE_HAL_PCI_BASIC_MODE = 0x10, 153a23fd118Syl XGE_HAL_PCIX_BASIC_MODE = 0x11, 154a23fd118Syl XGE_HAL_PCI_INVALID_MODE = 0x12, 155a23fd118Syl } xge_hal_pci_mode_e; 156a23fd118Syl 157a23fd118Syl /** 158a23fd118Syl * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration. 159a23fd118Syl * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ 160a23fd118Syl * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ 161a23fd118Syl * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ 162a23fd118Syl * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ 1638347601bSyl * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ 164*7eced415Sxw * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ 165a23fd118Syl * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ 166a23fd118Syl * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value. 167a23fd118Syl * 168a23fd118Syl */ 169a23fd118Syl typedef enum xge_hal_pci_bus_frequency_e { 170a23fd118Syl XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33, 171a23fd118Syl XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66, 172a23fd118Syl XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100, 173a23fd118Syl XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133, 174a23fd118Syl XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200, 175*7eced415Sxw XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250, 176a23fd118Syl XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266, 177a23fd118Syl XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0 178a23fd118Syl } xge_hal_pci_bus_frequency_e; 179a23fd118Syl 180a23fd118Syl /** 181a23fd118Syl * enum xge_hal_pci_bus_width_e - PCI bus width enumeration. 182a23fd118Syl * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width. 183a23fd118Syl * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width. 184a23fd118Syl * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width. 185a23fd118Syl * 186a23fd118Syl */ 187a23fd118Syl typedef enum xge_hal_pci_bus_width_e { 188a23fd118Syl XGE_HAL_PCI_BUS_WIDTH_64BIT = 0, 189a23fd118Syl XGE_HAL_PCI_BUS_WIDTH_32BIT = 1, 190a23fd118Syl XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2, 191a23fd118Syl } xge_hal_pci_bus_width_e; 192a23fd118Syl 193a23fd118Syl #if defined (XGE_HAL_CONFIG_LRO) 194a23fd118Syl 195a23fd118Syl #define IP_TOTAL_LENGTH_OFFSET 2 196a23fd118Syl #define IP_FAST_PATH_HDR_MASK 0x45 197a23fd118Syl #define TCP_FAST_PATH_HDR_MASK1 0x50 198a23fd118Syl #define TCP_FAST_PATH_HDR_MASK2 0x10 199a23fd118Syl #define TCP_FAST_PATH_HDR_MASK3 0x18 200a23fd118Syl #define IP_SOURCE_ADDRESS_OFFSET 12 201a23fd118Syl #define IP_DESTINATION_ADDRESS_OFFSET 16 202a23fd118Syl #define TCP_DESTINATION_PORT_OFFSET 2 203a23fd118Syl #define TCP_SOURCE_PORT_OFFSET 0 204a23fd118Syl #define TCP_DATA_OFFSET_OFFSET 12 205a23fd118Syl #define TCP_WINDOW_OFFSET 14 206a23fd118Syl #define TCP_SEQUENCE_NUMBER_OFFSET 4 207a23fd118Syl #define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8 208a23fd118Syl 209a23fd118Syl typedef struct tcplro { 210a23fd118Syl u16 source; 211a23fd118Syl u16 dest; 212a23fd118Syl u32 seq; 213a23fd118Syl u32 ack_seq; 214a23fd118Syl u8 doff_res; 215a23fd118Syl u8 ctrl; 216a23fd118Syl u16 window; 217a23fd118Syl u16 check; 218a23fd118Syl u16 urg_ptr; 219a23fd118Syl } tcplro_t; 220a23fd118Syl 221a23fd118Syl typedef struct iplro { 222a23fd118Syl u8 version_ihl; 223a23fd118Syl u8 tos; 224a23fd118Syl u16 tot_len; 225a23fd118Syl u16 id; 226a23fd118Syl u16 frag_off; 227a23fd118Syl u8 ttl; 228a23fd118Syl u8 protocol; 229a23fd118Syl u16 check; 230a23fd118Syl u32 saddr; 231a23fd118Syl u32 daddr; 232a23fd118Syl /*The options start here. */ 233a23fd118Syl } iplro_t; 234a23fd118Syl 235a23fd118Syl /* 236a23fd118Syl * LRO object, one per each LRO session. 237a23fd118Syl */ 238a23fd118Syl typedef struct lro { 239a23fd118Syl /* non-linear: contains scatter-gather list of 240a23fd118Syl xframe-mapped received buffers */ 241a23fd118Syl OS_NETSTACK_BUF os_buf; 242a23fd118Syl OS_NETSTACK_BUF os_buf_end; 243a23fd118Syl 244a23fd118Syl /* link layer header of the first frame; 245a23fd118Syl remains intack throughout the processing */ 246a23fd118Syl u8 *ll_hdr; 247a23fd118Syl 248a23fd118Syl /* IP header - gets _collapsed_ */ 249a23fd118Syl iplro_t *ip_hdr; 250a23fd118Syl 251a23fd118Syl /* transport header - gets _collapsed_ */ 252a23fd118Syl tcplro_t *tcp_hdr; 253a23fd118Syl 254a23fd118Syl /* Next tcp sequence number */ 255a23fd118Syl u32 tcp_next_seq_num; 256a23fd118Syl /* Current tcp seq & ack */ 257a23fd118Syl u32 tcp_seq_num; 258a23fd118Syl u32 tcp_ack_num; 259a23fd118Syl 260a23fd118Syl /* total number of accumulated (so far) frames */ 261a23fd118Syl int sg_num; 262a23fd118Syl 263a23fd118Syl /* total data length */ 264a23fd118Syl int total_length; 265a23fd118Syl 266a23fd118Syl /* receive side hash value, available from Hercules */ 267a23fd118Syl u32 rth_value; 268a23fd118Syl 269a23fd118Syl /* In use */ 270a23fd118Syl u8 in_use; 271a23fd118Syl 272a23fd118Syl /* Total length of the fragments clubbed with the inital frame */ 273a23fd118Syl u32 frags_len; 2748347601bSyl 2758347601bSyl /* LRO frame contains time stamp, if (ts_off != -1) */ 2768347601bSyl int ts_off; 2778347601bSyl 278a23fd118Syl } lro_t; 279a23fd118Syl #endif 280a23fd118Syl 281a23fd118Syl /* 282a23fd118Syl * xge_hal_spdm_entry_t 283a23fd118Syl * 284a23fd118Syl * Represents a single spdm entry in the SPDM table. 285a23fd118Syl */ 286a23fd118Syl typedef struct xge_hal_spdm_entry_t { 287a23fd118Syl xge_hal_ipaddr_t src_ip; 288a23fd118Syl xge_hal_ipaddr_t dst_ip; 289a23fd118Syl u32 jhash_value; 290a23fd118Syl u16 l4_sp; 291a23fd118Syl u16 l4_dp; 292a23fd118Syl u16 spdm_entry; 293a23fd118Syl u8 in_use; 294a23fd118Syl u8 is_tcp; 295a23fd118Syl u8 is_ipv4; 296a23fd118Syl u8 tgt_queue; 297a23fd118Syl } xge_hal_spdm_entry_t; 298a23fd118Syl 299*7eced415Sxw #if defined(XGE_HAL_CONFIG_LRO) 300*7eced415Sxw typedef struct { 301*7eced415Sxw lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS]; 302*7eced415Sxw int lro_next_idx; 303*7eced415Sxw lro_t *lro_recent; 304*7eced415Sxw } xge_hal_lro_desc_t; 305*7eced415Sxw #endif 3068347601bSyl /* 307*7eced415Sxw * xge_hal_vpd_data_t 308*7eced415Sxw * 309*7eced415Sxw * Represents vpd capabilty structure 3108347601bSyl */ 311*7eced415Sxw typedef struct xge_hal_vpd_data_t { 312*7eced415Sxw u8 product_name[XGE_HAL_VPD_LENGTH]; 313*7eced415Sxw u8 serial_num[XGE_HAL_VPD_LENGTH]; 314*7eced415Sxw } xge_hal_vpd_data_t; 315a23fd118Syl 316a23fd118Syl /* 317a23fd118Syl * xge_hal_device_t 318a23fd118Syl * 319a23fd118Syl * HAL device object. Represents Xframe. 320a23fd118Syl */ 321a23fd118Syl typedef struct { 3228347601bSyl unsigned int magic; 323a23fd118Syl pci_reg_h regh0; 324a23fd118Syl pci_reg_h regh1; 325a23fd118Syl pci_reg_h regh2; 326a23fd118Syl char *bar0; 327a23fd118Syl char *isrbar0; 328a23fd118Syl char *bar1; 329a23fd118Syl char *bar2; 330a23fd118Syl pci_irq_h irqh; 331a23fd118Syl pci_cfg_h cfgh; 332a23fd118Syl pci_dev_h pdev; 333a23fd118Syl xge_hal_pci_config_t pci_config_space; 334*7eced415Sxw xge_hal_pci_config_t pci_config_space_bios; 335a23fd118Syl xge_hal_device_config_t config; 336a23fd118Syl xge_list_t free_channels; 337a23fd118Syl xge_list_t fifo_channels; 338a23fd118Syl xge_list_t ring_channels; 339a23fd118Syl volatile int is_initialized; 340a23fd118Syl volatile int terminating; 341a23fd118Syl xge_hal_stats_t stats; 342a23fd118Syl macaddr_t macaddr[1]; 343a23fd118Syl xge_queue_h queueh; 344a23fd118Syl volatile int mcast_refcnt; 345a23fd118Syl int is_promisc; 346a23fd118Syl volatile xge_hal_device_link_state_e link_state; 347a23fd118Syl void *upper_layer_info; 348a23fd118Syl xge_hal_device_attr_t orig_attr; 349a23fd118Syl u16 device_id; 350a23fd118Syl u8 revision; 351a23fd118Syl int msi_enabled; 352a23fd118Syl int hw_is_initialized; 353a23fd118Syl u64 inject_serr; 354a23fd118Syl u64 inject_ecc; 355a23fd118Syl u8 inject_bad_tcode; 356a23fd118Syl int inject_bad_tcode_for_chan_type; 357a23fd118Syl int reset_needed_after_close; 3588347601bSyl int tti_enabled; 3598347601bSyl xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM]; 3608347601bSyl int bimodal_timer_val_us; 3618347601bSyl int bimodal_urange_a_en; 3628347601bSyl int bimodal_intr_cnt; 363a23fd118Syl char *spdm_mem_base; 364a23fd118Syl u16 spdm_max_entries; 365a23fd118Syl xge_hal_spdm_entry_t **spdm_table; 366a23fd118Syl spinlock_t spdm_lock; 367a23fd118Syl #if defined(XGE_HAL_CONFIG_LRO) 368*7eced415Sxw xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM]; 369a23fd118Syl #endif 370a23fd118Syl spinlock_t xena_post_lock; 3718347601bSyl 3728347601bSyl /* bimodal workload stats */ 3738347601bSyl int irq_workload_rxd[XGE_HAL_MAX_RING_NUM]; 3748347601bSyl int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM]; 3758347601bSyl int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM]; 3768347601bSyl int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM]; 3778347601bSyl int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM]; 3788347601bSyl int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM]; 3798347601bSyl 3808347601bSyl int mtu_first_time_set; 381a23fd118Syl u64 rxufca_lbolt; 382a23fd118Syl u64 rxufca_lbolt_time; 383a23fd118Syl u64 rxufca_intr_thres; 384a23fd118Syl char* dump_buf; 385a23fd118Syl xge_hal_pci_mode_e pci_mode; 386a23fd118Syl xge_hal_pci_bus_frequency_e bus_frequency; 387a23fd118Syl xge_hal_pci_bus_width_e bus_width; 388*7eced415Sxw xge_hal_vpd_data_t vpd_data; 389a23fd118Syl volatile int in_poll; 390*7eced415Sxw u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR]; 391a23fd118Syl } xge_hal_device_t; 392a23fd118Syl 393a23fd118Syl 394a23fd118Syl /* ========================== PRIVATE API ================================= */ 395a23fd118Syl 396*7eced415Sxw void 397*7eced415Sxw __hal_device_event_queued(void *data, int event_type); 398*7eced415Sxw 399*7eced415Sxw xge_hal_status_e 400*7eced415Sxw __hal_device_set_swapper(xge_hal_device_t *hldev); 401*7eced415Sxw 402*7eced415Sxw xge_hal_status_e 403*7eced415Sxw __hal_device_rth_it_configure(xge_hal_device_t *hldev); 404*7eced415Sxw 405*7eced415Sxw xge_hal_status_e 406*7eced415Sxw __hal_device_rth_spdm_configure(xge_hal_device_t *hldev); 407*7eced415Sxw 408*7eced415Sxw xge_hal_status_e 409*7eced415Sxw __hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status); 410*7eced415Sxw 411*7eced415Sxw xge_hal_status_e 412*7eced415Sxw __hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason); 413*7eced415Sxw 414*7eced415Sxw xge_hal_status_e 415*7eced415Sxw __hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line, 416*7eced415Sxw u16 spdm_entry, u64 *spdm_line_val); 417*7eced415Sxw 418a23fd118Syl void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, 419a23fd118Syl void *addr); 420a23fd118Syl 421a23fd118Syl void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, 422a23fd118Syl void *addr); 423*7eced415Sxw void __hal_device_get_vpd_data(xge_hal_device_t *hldev); 424a23fd118Syl 425a23fd118Syl xge_hal_status_e 426a23fd118Syl __hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason); 427a23fd118Syl 428a23fd118Syl xge_hal_status_e 429a23fd118Syl __hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason); 430a23fd118Syl 431a23fd118Syl xge_hal_status_e 432a23fd118Syl __hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason); 433a23fd118Syl 434a23fd118Syl xge_hal_status_e 435a23fd118Syl __hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason); 436a23fd118Syl 437a23fd118Syl xge_hal_status_e 438a23fd118Syl __hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason); 439a23fd118Syl 440a23fd118Syl xge_hal_status_e 441a23fd118Syl __hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason); 442a23fd118Syl 443a23fd118Syl xge_hal_status_e 444a23fd118Syl __hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason); 445a23fd118Syl 446a23fd118Syl xge_hal_status_e 447a23fd118Syl __hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason); 448a23fd118Syl 449a23fd118Syl xge_hal_status_e 450a23fd118Syl __hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason); 451a23fd118Syl 452a23fd118Syl xge_hal_status_e 453a23fd118Syl __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask, 454a23fd118Syl int max_millis); 455a23fd118Syl xge_hal_status_e 456a23fd118Syl __hal_device_rts_mac_configure(xge_hal_device_t *hldev); 457a23fd118Syl 4588347601bSyl xge_hal_status_e 4598347601bSyl __hal_device_rts_qos_configure(xge_hal_device_t *hldev); 4608347601bSyl 461*7eced415Sxw xge_hal_status_e 462*7eced415Sxw __hal_device_rts_port_configure(xge_hal_device_t *hldev); 463*7eced415Sxw 4648347601bSyl xge_hal_status_e 4658347601bSyl __hal_device_rti_configure(xge_hal_device_t *hldev, int runtime); 4668347601bSyl 467*7eced415Sxw void 468*7eced415Sxw __hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag); 469*7eced415Sxw 470*7eced415Sxw void 471*7eced415Sxw __hal_device_msix_intr_endis(xge_hal_device_t *hldev, 472*7eced415Sxw xge_hal_channel_t *channel, int flag); 473*7eced415Sxw 474a23fd118Syl /* =========================== PUBLIC API ================================= */ 475a23fd118Syl 476a23fd118Syl unsigned int 477a23fd118Syl __hal_fix_time_ival_herc(xge_hal_device_t *hldev, 478a23fd118Syl unsigned int time_ival); 479a23fd118Syl xge_hal_status_e 480a23fd118Syl xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable, 481a23fd118Syl u32 itable_size); 482a23fd118Syl 483a23fd118Syl void 484a23fd118Syl xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type, 485a23fd118Syl u16 bucket_size); 486a23fd118Syl 487a23fd118Syl void 488a23fd118Syl xge_hal_rts_rth_init(xge_hal_device_t *hldev); 489a23fd118Syl 490a23fd118Syl void 491a23fd118Syl xge_hal_rts_rth_clr(xge_hal_device_t *hldev); 492a23fd118Syl 493a23fd118Syl void 494a23fd118Syl xge_hal_rts_rth_start(xge_hal_device_t *hldev); 495a23fd118Syl 496a23fd118Syl void 497a23fd118Syl xge_hal_rts_rth_stop(xge_hal_device_t *hldev); 498a23fd118Syl 499a23fd118Syl void 500a23fd118Syl xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key); 501a23fd118Syl 502a23fd118Syl xge_hal_status_e 503a23fd118Syl xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr); 504a23fd118Syl 505a23fd118Syl xge_hal_status_e 506a23fd118Syl xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index); 507a23fd118Syl 508*7eced415Sxw int xge_hal_reinitialize_hw(xge_hal_device_t * hldev); 509*7eced415Sxw 510*7eced415Sxw xge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev); 5118347601bSyl /** 5128347601bSyl * xge_hal_device_rti_reconfigure 513*7eced415Sxw * @hldev: Hal Device 5148347601bSyl */ 5158347601bSyl static inline xge_hal_status_e 5168347601bSyl xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev) 5178347601bSyl { 5188347601bSyl return __hal_device_rti_configure(hldev, 1); 5198347601bSyl } 520a23fd118Syl 521*7eced415Sxw /** 522*7eced415Sxw * xge_hal_device_rts_port_reconfigure 523*7eced415Sxw * @hldev: Hal Device 524*7eced415Sxw */ 525*7eced415Sxw static inline xge_hal_status_e 526*7eced415Sxw xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev) 527*7eced415Sxw { 528*7eced415Sxw return __hal_device_rts_port_configure(hldev); 529*7eced415Sxw } 530*7eced415Sxw 531a23fd118Syl /** 532a23fd118Syl * xge_hal_device_is_initialized - Returns 0 if device is not 533a23fd118Syl * initialized, non-zero otherwise. 534a23fd118Syl * @devh: HAL device handle. 535a23fd118Syl * 536a23fd118Syl * Returns 0 if device is not initialized, non-zero otherwise. 537a23fd118Syl */ 538a23fd118Syl static inline int 539a23fd118Syl xge_hal_device_is_initialized(xge_hal_device_h devh) 540a23fd118Syl { 541a23fd118Syl return ((xge_hal_device_t*)devh)->is_initialized; 542a23fd118Syl } 543a23fd118Syl 544a23fd118Syl 545a23fd118Syl /** 546a23fd118Syl * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing. 547a23fd118Syl * @devh: HAL device handle. 548a23fd118Syl * 549a23fd118Syl * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise. 550a23fd118Syl */ 551a23fd118Syl static inline int 552a23fd118Syl xge_hal_device_in_poll(xge_hal_device_h devh) 553a23fd118Syl { 554a23fd118Syl return ((xge_hal_device_t*)devh)->in_poll; 555a23fd118Syl } 556a23fd118Syl 557a23fd118Syl 558a23fd118Syl /** 559a23fd118Syl * xge_hal_device_inject_ecc - Inject ECC error. 560a23fd118Syl * @devh: HAL device, pointer to xge_hal_device_t structure. 561a23fd118Syl * @err_reg: Contains the error register. 562a23fd118Syl * 563a23fd118Syl * This function is used to inject ECC error into the driver flow. 564a23fd118Syl * This facility can be used to test the driver flow in the 565a23fd118Syl * case of ECC error is reported by the firmware. 566a23fd118Syl * 567a23fd118Syl * Returns: void 568a23fd118Syl * See also: xge_hal_device_inject_serr(), 569a23fd118Syl * xge_hal_device_inject_bad_tcode() 570a23fd118Syl */ 571a23fd118Syl static inline void 572a23fd118Syl xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg) 573a23fd118Syl { 574a23fd118Syl ((xge_hal_device_t*)devh)->inject_ecc = err_reg; 575a23fd118Syl } 576a23fd118Syl 577a23fd118Syl 578a23fd118Syl /** 579a23fd118Syl * xge_hal_device_inject_serr - Inject SERR error. 580a23fd118Syl * @devh: HAL device, pointer to xge_hal_device_t structure. 581a23fd118Syl * @err_reg: Contains the error register. 582a23fd118Syl * 583a23fd118Syl * This function is used to inject SERR error into the driver flow. 584a23fd118Syl * This facility can be used to test the driver flow in the 585a23fd118Syl * case of SERR error is reported by firmware. 586a23fd118Syl * 587a23fd118Syl * Returns: void 588a23fd118Syl * See also: xge_hal_device_inject_ecc(), 589a23fd118Syl * xge_hal_device_inject_bad_tcode() 590a23fd118Syl */ 591a23fd118Syl static inline void 592a23fd118Syl xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg) 593a23fd118Syl { 594a23fd118Syl ((xge_hal_device_t*)devh)->inject_serr = err_reg; 595a23fd118Syl } 596a23fd118Syl 597a23fd118Syl 598a23fd118Syl /** 599a23fd118Syl * xge_hal_device_inject_bad_tcode - Inject Bad transfer code. 600a23fd118Syl * @devh: HAL device, pointer to xge_hal_device_t structure. 601a23fd118Syl * @chan_type: Channel type (fifo/ring). 602a23fd118Syl * @t_code: Transfer code. 603a23fd118Syl * 604a23fd118Syl * This function is used to inject bad (Tx/Rx Data)transfer code 605a23fd118Syl * into the driver flow. 606a23fd118Syl * 607a23fd118Syl * This facility can be used to test the driver flow in the 608a23fd118Syl * case of bad transfer code reported by firmware for a Tx/Rx data 609a23fd118Syl * transfer. 610a23fd118Syl * 611a23fd118Syl * Returns: void 612a23fd118Syl * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr() 613a23fd118Syl */ 614a23fd118Syl static inline void 615a23fd118Syl xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code) 616a23fd118Syl { 617a23fd118Syl ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type; 618a23fd118Syl ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code; 619a23fd118Syl } 620a23fd118Syl 621a23fd118Syl void xge_hal_device_msi_enable(xge_hal_device_h devh); 622a23fd118Syl 623a23fd118Syl /* 624a23fd118Syl * xge_hal_device_msi_mode - Is MSI enabled? 625a23fd118Syl * @devh: HAL device handle. 626a23fd118Syl * 627a23fd118Syl * Returns 0 if MSI is enabled for the specified device, 628a23fd118Syl * non-zero otherwise. 629a23fd118Syl */ 630a23fd118Syl static inline int 631a23fd118Syl xge_hal_device_msi_mode(xge_hal_device_h devh) 632a23fd118Syl { 633a23fd118Syl return ((xge_hal_device_t*)devh)->msi_enabled; 634a23fd118Syl } 635a23fd118Syl 636a23fd118Syl /** 637a23fd118Syl * xge_hal_device_queue - Get per-device event queue. 638a23fd118Syl * @devh: HAL device handle. 639a23fd118Syl * 640a23fd118Syl * Returns: event queue associated with the specified HAL device. 641a23fd118Syl */ 642a23fd118Syl static inline xge_queue_h 643a23fd118Syl xge_hal_device_queue (xge_hal_device_h devh) 644a23fd118Syl { 645a23fd118Syl return ((xge_hal_device_t*)devh)->queueh; 646a23fd118Syl } 647a23fd118Syl 648a23fd118Syl /** 649a23fd118Syl * xge_hal_device_attr - Get original (user-specified) device 650a23fd118Syl * attributes. 651a23fd118Syl * @devh: HAL device handle. 652a23fd118Syl * 653a23fd118Syl * Returns: original (user-specified) device attributes. 654a23fd118Syl */ 655a23fd118Syl static inline xge_hal_device_attr_t* 656a23fd118Syl xge_hal_device_attr(xge_hal_device_h devh) 657a23fd118Syl { 658a23fd118Syl return &((xge_hal_device_t*)devh)->orig_attr; 659a23fd118Syl } 660a23fd118Syl 661a23fd118Syl /** 662a23fd118Syl * xge_hal_device_private_set - Set ULD context. 663a23fd118Syl * @devh: HAL device handle. 664a23fd118Syl * @data: pointer to ULD context 665a23fd118Syl * 666a23fd118Syl * Use HAL device to set upper-layer driver (ULD) context. 667a23fd118Syl * 668a23fd118Syl * See also: xge_hal_device_from_private(), xge_hal_device_private() 669a23fd118Syl */ 670a23fd118Syl static inline void 671a23fd118Syl xge_hal_device_private_set(xge_hal_device_h devh, void *data) 672a23fd118Syl { 673a23fd118Syl ((xge_hal_device_t*)devh)->upper_layer_info = data; 674a23fd118Syl } 675a23fd118Syl 676a23fd118Syl /** 677a23fd118Syl * xge_hal_device_private - Get ULD context. 678a23fd118Syl * @devh: HAL device handle. 679a23fd118Syl * 680a23fd118Syl * Use HAL device to get upper-layer driver (ULD) context. 681a23fd118Syl * 682a23fd118Syl * Returns: ULD context. 683a23fd118Syl * 684a23fd118Syl * See also: xge_hal_device_from_private(), xge_hal_device_private_set() 685a23fd118Syl */ 686a23fd118Syl static inline void* 687a23fd118Syl xge_hal_device_private(xge_hal_device_h devh) 688a23fd118Syl { 689a23fd118Syl return ((xge_hal_device_t*)devh)->upper_layer_info; 690a23fd118Syl } 691a23fd118Syl 692a23fd118Syl /** 693a23fd118Syl * xge_hal_device_from_private - Get HAL device object from private. 694a23fd118Syl * @info_ptr: ULD context. 695a23fd118Syl * 696a23fd118Syl * Use ULD context to get HAL device. 697a23fd118Syl * 698a23fd118Syl * Returns: Device handle. 699a23fd118Syl * 700a23fd118Syl * See also: xge_hal_device_private(), xge_hal_device_private_set() 701a23fd118Syl */ 702a23fd118Syl static inline xge_hal_device_h 703a23fd118Syl xge_hal_device_from_private(void *info_ptr) 704a23fd118Syl { 705*7eced415Sxw return xge_container_of((void ** ) info_ptr, xge_hal_device_t, 706a23fd118Syl upper_layer_info); 707a23fd118Syl } 708a23fd118Syl 709a23fd118Syl /** 710a23fd118Syl * xge_hal_device_mtu_check - check MTU value for ranges 711a23fd118Syl * @hldev: the device 712a23fd118Syl * @new_mtu: new MTU value to check 713a23fd118Syl * 714a23fd118Syl * Will do sanity check for new MTU value. 715a23fd118Syl * 716a23fd118Syl * Returns: XGE_HAL_OK - success. 717a23fd118Syl * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid. 718a23fd118Syl * 719a23fd118Syl * See also: xge_hal_device_mtu_set() 720a23fd118Syl */ 721a23fd118Syl static inline xge_hal_status_e 722a23fd118Syl xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu) 723a23fd118Syl { 724a23fd118Syl if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) { 725a23fd118Syl return XGE_HAL_ERR_INVALID_MTU_SIZE; 726a23fd118Syl } 727a23fd118Syl 728a23fd118Syl return XGE_HAL_OK; 729a23fd118Syl } 730a23fd118Syl 731a23fd118Syl void xge_hal_device_bcast_enable(xge_hal_device_h devh); 732a23fd118Syl 733a23fd118Syl void xge_hal_device_bcast_disable(xge_hal_device_h devh); 734a23fd118Syl 735a23fd118Syl void xge_hal_device_terminating(xge_hal_device_h devh); 736a23fd118Syl 737a23fd118Syl xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev, 738a23fd118Syl xge_hal_device_attr_t *attr, xge_hal_device_config_t *config); 739a23fd118Syl 740a23fd118Syl void xge_hal_device_terminate(xge_hal_device_t *hldev); 741a23fd118Syl 742a23fd118Syl xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev); 743a23fd118Syl 744a23fd118Syl xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev, 745a23fd118Syl int index, macaddr_t *macaddr); 746a23fd118Syl 747a23fd118Syl xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev, 748a23fd118Syl int index, macaddr_t macaddr); 749a23fd118Syl 750*7eced415Sxw xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev, 751*7eced415Sxw int index); 752*7eced415Sxw 753a23fd118Syl int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted); 754a23fd118Syl 755a23fd118Syl xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu); 756a23fd118Syl 757a23fd118Syl xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status); 758a23fd118Syl 759a23fd118Syl void xge_hal_device_intr_enable(xge_hal_device_t *hldev); 760a23fd118Syl 761a23fd118Syl void xge_hal_device_intr_disable(xge_hal_device_t *hldev); 762a23fd118Syl 763a23fd118Syl xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev); 764a23fd118Syl 765a23fd118Syl xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev); 766a23fd118Syl 767a23fd118Syl void xge_hal_device_promisc_enable(xge_hal_device_t *hldev); 768a23fd118Syl 769a23fd118Syl void xge_hal_device_promisc_disable(xge_hal_device_t *hldev); 770a23fd118Syl 771a23fd118Syl xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev); 772a23fd118Syl 773a23fd118Syl xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev); 774a23fd118Syl 775a23fd118Syl xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh, 776a23fd118Syl xge_hal_dtr_h dtrh, 777a23fd118Syl u8 t_code); 778a23fd118Syl 779a23fd118Syl xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh, 780a23fd118Syl xge_hal_device_link_state_e *ls); 781a23fd118Syl 782a23fd118Syl void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us, 783a23fd118Syl int one_shot); 784a23fd118Syl 785a23fd118Syl void xge_hal_device_poll(xge_hal_device_h devh); 786a23fd118Syl 787a23fd118Syl xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh); 788a23fd118Syl 789a23fd118Syl int xge_hal_device_is_slot_freeze(xge_hal_device_h devh); 790a23fd118Syl 791a23fd118Syl xge_hal_status_e 792a23fd118Syl xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, 793a23fd118Syl xge_hal_pci_bus_frequency_e *bus_frequency, 794a23fd118Syl xge_hal_pci_bus_width_e *bus_width); 795a23fd118Syl 796a23fd118Syl xge_hal_status_e 797a23fd118Syl xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 798a23fd118Syl xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 799a23fd118Syl u8 is_tcp, u8 is_ipv4, u8 tgt_queue); 800a23fd118Syl 801a23fd118Syl xge_hal_status_e 802a23fd118Syl xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 803a23fd118Syl xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 804a23fd118Syl u8 is_tcp, u8 is_ipv4); 805a23fd118Syl 8068347601bSyl xge_hal_status_e 8078347601bSyl xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index); 8088347601bSyl 809a23fd118Syl int 810a23fd118Syl xge_hal_device_is_closed (xge_hal_device_h devh); 811a23fd118Syl 812*7eced415Sxw /* private functions, don't use them in ULD */ 8138347601bSyl 814*7eced415Sxw void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg); 8158347601bSyl 816*7eced415Sxw u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg); 8178347601bSyl 8188347601bSyl 819a23fd118Syl /* Some function protoypes for MSI implementation. */ 820a23fd118Syl xge_hal_status_e 821*7eced415Sxw xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi, 822*7eced415Sxw u32 msg_val); 823a23fd118Syl void 824a23fd118Syl xge_hal_mask_msi(xge_hal_device_t *hldev); 825*7eced415Sxw 826a23fd118Syl void 827a23fd118Syl xge_hal_unmask_msi(xge_hal_channel_h channelh); 828*7eced415Sxw 829a23fd118Syl xge_hal_status_e 830a23fd118Syl xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx); 831a23fd118Syl 832*7eced415Sxw xge_hal_status_e 833*7eced415Sxw xge_hal_mask_msix(xge_hal_device_h devh, int msi_id); 834*7eced415Sxw 835*7eced415Sxw xge_hal_status_e 836*7eced415Sxw xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id); 837*7eced415Sxw 838*7eced415Sxw #if defined(XGE_HAL_CONFIG_LRO) 839*7eced415Sxw xge_hal_status_e 840*7eced415Sxw xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev); 841*7eced415Sxw 842*7eced415Sxw void 843*7eced415Sxw xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev); 844*7eced415Sxw #endif 845a23fd118Syl 846a23fd118Syl #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE) 847a23fd118Syl #define __HAL_STATIC_DEVICE 848a23fd118Syl #define __HAL_INLINE_DEVICE 849a23fd118Syl 850a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int 851a23fd118Syl xge_hal_device_rev(xge_hal_device_t *hldev); 852a23fd118Syl 853a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 854a23fd118Syl xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason); 855a23fd118Syl 856a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 857a23fd118Syl xge_hal_device_clear_rx(xge_hal_device_t *hldev); 858a23fd118Syl 859a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 860a23fd118Syl xge_hal_device_clear_tx(xge_hal_device_t *hldev); 861a23fd118Syl 862a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 863a23fd118Syl xge_hal_device_continue_irq(xge_hal_device_t *hldev); 864a23fd118Syl 865a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 866a23fd118Syl xge_hal_device_handle_irq(xge_hal_device_t *hldev); 867a23fd118Syl 868a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 869a23fd118Syl xge_hal_device_bar0(xge_hal_device_t *hldev); 870a23fd118Syl 871a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 872a23fd118Syl xge_hal_device_isrbar0(xge_hal_device_t *hldev); 873a23fd118Syl 874a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 875a23fd118Syl xge_hal_device_bar1(xge_hal_device_t *hldev); 876a23fd118Syl 877a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 878a23fd118Syl xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0); 879a23fd118Syl 880a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 881a23fd118Syl xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0); 882a23fd118Syl 883a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 884a23fd118Syl xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh, 885a23fd118Syl char *bar1); 886a23fd118Syl 887a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 888a23fd118Syl xge_hal_device_mask_tx(xge_hal_device_t *hldev); 889a23fd118Syl 890a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 891a23fd118Syl xge_hal_device_mask_rx(xge_hal_device_t *hldev); 892a23fd118Syl 893a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 894a23fd118Syl xge_hal_device_mask_all(xge_hal_device_t *hldev); 895a23fd118Syl 896a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 897a23fd118Syl xge_hal_device_unmask_tx(xge_hal_device_t *hldev); 898a23fd118Syl 899a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 900a23fd118Syl xge_hal_device_unmask_rx(xge_hal_device_t *hldev); 901a23fd118Syl 902a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 903a23fd118Syl xge_hal_device_unmask_all(xge_hal_device_t *hldev); 904a23fd118Syl 905a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 9068347601bSyl xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx); 907a23fd118Syl 908a23fd118Syl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 9098347601bSyl xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx); 9108347601bSyl 9118347601bSyl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 9128347601bSyl xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx); 9138347601bSyl 9148347601bSyl __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 9158347601bSyl xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx); 916a23fd118Syl 917a23fd118Syl #if defined (XGE_HAL_CONFIG_LRO) 918a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8 919a23fd118Syl __hal_header_parse_token_u8(u8 *string,u16 offset); 920a23fd118Syl 921a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 922a23fd118Syl __hal_header_parse_token_u16(u8 *string,u16 offset); 923a23fd118Syl 924a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32 925a23fd118Syl __hal_header_parse_token_u32(u8 *string,u16 offset); 926a23fd118Syl 927a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 928a23fd118Syl __hal_header_update_u8(u8 *string, u16 offset, u8 val); 929a23fd118Syl 930a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 931a23fd118Syl __hal_header_update_u16(u8 *string, u16 offset, u16 val); 932a23fd118Syl 933a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 934a23fd118Syl __hal_header_update_u32(u8 *string, u16 offset, u32 val); 935a23fd118Syl 936a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 9378347601bSyl __hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp); 938a23fd118Syl 939a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9408347601bSyl __hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info); 941a23fd118Syl 942a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9438347601bSyl __hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off); 944a23fd118Syl 945a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9468347601bSyl __hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp, 947*7eced415Sxw xge_hal_dtr_info_t *ext_info); 948a23fd118Syl 949a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 950*7eced415Sxw __hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 9518347601bSyl xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 952*7eced415Sxw xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3); 953a23fd118Syl 954a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9558347601bSyl __hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 956a23fd118Syl xge_hal_device_t *hldev); 957a23fd118Syl 958a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9598347601bSyl __hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 9608347601bSyl xge_hal_device_t *hldev); 961a23fd118Syl 962a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9638347601bSyl __hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 9648347601bSyl xge_hal_device_t *hldev); 965a23fd118Syl 966a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9678347601bSyl __hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro, 968a23fd118Syl xge_hal_device_t *hldev); 969a23fd118Syl 970*7eced415Sxw __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 971*7eced415Sxw xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp, 972*7eced415Sxw u32 *seglen, lro_t **p_lro, 973*7eced415Sxw xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 974*7eced415Sxw lro_t **lro_end3); 975*7eced415Sxw 976a23fd118Syl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 9778347601bSyl xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen, 9788347601bSyl lro_t **lro, xge_hal_dtr_info_t *ext_info, 9798347601bSyl xge_hal_device_t *hldev, lro_t **lro_end3); 980a23fd118Syl 981*7eced415Sxw __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 982*7eced415Sxw xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring); 9838347601bSyl 9848347601bSyl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 9858347601bSyl xge_hal_lro_get_next_session(xge_hal_device_t *hldev); 9868347601bSyl 9878347601bSyl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 9888347601bSyl __hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 989*7eced415Sxw xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro, 990*7eced415Sxw int slot, u32 tcp_seg_len, int ts_off); 9918347601bSyl 9928347601bSyl __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 993*7eced415Sxw __hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro); 994a23fd118Syl #endif 995a23fd118Syl 996a23fd118Syl #else /* XGE_FASTPATH_EXTERN */ 997a23fd118Syl #define __HAL_STATIC_DEVICE static 998a23fd118Syl #define __HAL_INLINE_DEVICE inline 999a23fd118Syl #include "xgehal-device-fp.c" 1000a23fd118Syl #endif /* XGE_FASTPATH_INLINE */ 1001a23fd118Syl 10028347601bSyl 10038347601bSyl __EXTERN_END_DECLS 10048347601bSyl 1005a23fd118Syl #endif /* XGE_HAL_DEVICE_H */ 1006