1a23fd11yl/*
2a23fd11yl * CDDL HEADER START
3a23fd11yl *
4a23fd11yl * The contents of this file are subject to the terms of the
5a23fd11yl * Common Development and Distribution License (the "License").
6a23fd11yl * You may not use this file except in compliance with the License.
7a23fd11yl *
8a23fd11yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9a23fd11yl * or http://www.opensolaris.org/os/licensing.
10a23fd11yl * See the License for the specific language governing permissions
11a23fd11yl * and limitations under the License.
12a23fd11yl *
13a23fd11yl * When distributing Covered Code, include this CDDL HEADER in each
14a23fd11yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15a23fd11yl * If applicable, add the following below this CDDL HEADER, with the
16a23fd11yl * fields enclosed by brackets "[]" replaced with your own identifying
17a23fd11yl * information: Portions Copyright [yyyy] [name of copyright owner]
18a23fd11yl *
19a23fd11yl * CDDL HEADER END
20a23fd11yl *
218347601yl * Copyright (c) 2002-2006 Neterion, Inc.
22a23fd11yl */
23a23fd11yl
241939740Sherry Moore/*
251939740Sherry Moore * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
261939740Sherry Moore * Use is subject to license terms.
271939740Sherry Moore */
281939740Sherry Moore
29a23fd11yl#ifndef XGE_HAL_DEVICE_H
30a23fd11yl#define XGE_HAL_DEVICE_H
31a23fd11yl
32a23fd11yl#include "xge-os-pal.h"
33a23fd11yl#include "xge-queue.h"
34a23fd11yl#include "xgehal-event.h"
35a23fd11yl#include "xgehal-config.h"
36a23fd11yl#include "xgehal-regs.h"
37a23fd11yl#include "xgehal-channel.h"
38a23fd11yl#include "xgehal-stats.h"
398347601yl#include "xgehal-ring.h"
408347601yl
418347601yl__EXTERN_BEGIN_DECLS
42a23fd11yl
437eced41xw#define XGE_HAL_VPD_LENGTH                              80
447eced41xw#define XGE_HAL_CARD_XENA_VPD_ADDR                      0x50
457eced41xw#define XGE_HAL_CARD_HERC_VPD_ADDR                      0x80
467eced41xw#define XGE_HAL_VPD_READ_COMPLETE                       0x80
477eced41xw#define XGE_HAL_VPD_BUFFER_SIZE                         128
48a23fd11yl#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS		500
49a23fd11yl#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS		500
50a23fd11yl#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS	500
51a23fd11yl#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS		50
52a23fd11yl#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS		250
53a23fd11yl#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS	250  /* TODO */
54a23fd11yl
55a23fd11yl#define XGE_HAL_MAGIC					0x12345678
56a23fd11yl#define XGE_HAL_DEAD					0xDEADDEAD
57a23fd11yl#define XGE_HAL_DUMP_BUF_SIZE                           0x4000
58a23fd11yl
598347601yl#define XGE_HAL_LRO_MAX_BUCKETS				32
60a23fd11yl
61a23fd11yl/**
62a23fd11yl * enum xge_hal_card_e - Xframe adapter type.
63a23fd11yl * @XGE_HAL_CARD_UNKNOWN: Unknown device.
64a23fd11yl * @XGE_HAL_CARD_XENA: Xframe I device.
65a23fd11yl * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
667eced41xw * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device.
67a23fd11yl *
68a23fd11yl * Enumerates Xframe adapter types. The corresponding PCI device
69a23fd11yl * IDs are listed in the file xgehal-defs.h.
70a23fd11yl * (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
71a23fd11yl *
72a23fd11yl * See also: xge_hal_device_check_id().
73a23fd11yl */
74a23fd11yltypedef enum xge_hal_card_e {
75a23fd11yl	XGE_HAL_CARD_UNKNOWN	= 0,
76a23fd11yl	XGE_HAL_CARD_XENA	= 1,
77a23fd11yl	XGE_HAL_CARD_HERC	= 2,
787eced41xw	XGE_HAL_CARD_TITAN	= 3,
79a23fd11yl} xge_hal_card_e;
80a23fd11yl
81a23fd11yl/**
82a23fd11yl * struct xge_hal_device_attr_t - Device memory spaces.
83a23fd11yl * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
84a23fd11yl *         (Linux and the rest.)
85a23fd11yl * @regh1: BAR1 mapped memory handle. Same comment as above.
86a23fd11yl * @bar0: BAR0 virtual address.
87a23fd11yl * @bar1: BAR1 virtual address.
88a23fd11yl * @irqh: IRQ handle (Solaris).
89a23fd11yl * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
90a23fd11yl * @pdev: PCI device object.
91a23fd11yl *
92a23fd11yl * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
93a23fd11yl * mapped memories. Also, includes a pointer to OS-specific PCI device object.
94a23fd11yl */
95a23fd11yltypedef struct xge_hal_device_attr_t {
96a23fd11yl	pci_reg_h		regh0;
97a23fd11yl	pci_reg_h		regh1;
98a23fd11yl	pci_reg_h		regh2;
99a23fd11yl	char			*bar0;
100a23fd11yl	char			*bar1;
101a23fd11yl	char			*bar2;
102a23fd11yl	pci_irq_h		irqh;
103a23fd11yl	pci_cfg_h		cfgh;
104a23fd11yl	pci_dev_h		pdev;
105a23fd11yl} xge_hal_device_attr_t;
106a23fd11yl
107a23fd11yl/**
108a23fd11yl * enum xge_hal_device_link_state_e - Link state enumeration.
109a23fd11yl * @XGE_HAL_LINK_NONE: Invalid link state.
110a23fd11yl * @XGE_HAL_LINK_DOWN: Link is down.
111a23fd11yl * @XGE_HAL_LINK_UP: Link is up.
112a23fd11yl *
113a23fd11yl */
114a23fd11yltypedef enum xge_hal_device_link_state_e {
115a23fd11yl	XGE_HAL_LINK_NONE,
116a23fd11yl	XGE_HAL_LINK_DOWN,
117a23fd11yl	XGE_HAL_LINK_UP
118a23fd11yl} xge_hal_device_link_state_e;
119a23fd11yl
120a23fd11yl
121a23fd11yl/**
122a23fd11yl * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
123a23fd11yl * @XGE_HAL_PCI_33MHZ_MODE:		33 MHZ pci mode.
124a23fd11yl * @XGE_HAL_PCI_66MHZ_MODE:		66 MHZ pci mode.
125a23fd11yl * @XGE_HAL_PCIX_M1_66MHZ_MODE:		PCIX M1 66MHZ mode.
126a23fd11yl * @XGE_HAL_PCIX_M1_100MHZ_MODE:	PCIX M1 100MHZ mode.
127a23fd11yl * @XGE_HAL_PCIX_M1_133MHZ_MODE:	PCIX M1 133MHZ mode.
128a23fd11yl * @XGE_HAL_PCIX_M2_66MHZ_MODE:		PCIX M2 66MHZ mode.
129a23fd11yl * @XGE_HAL_PCIX_M2_100MHZ_MODE:	PCIX M2 100MHZ mode.
130a23fd11yl * @XGE_HAL_PCIX_M2_133MHZ_MODE:	PCIX M3 133MHZ mode.
131a23fd11yl * @XGE_HAL_PCIX_M1_RESERVED:		PCIX M1 reserved mode.
132a23fd11yl * @XGE_HAL_PCIX_M1_66MHZ_NS:		PCIX M1 66MHZ mode not supported.
133a23fd11yl * @XGE_HAL_PCIX_M1_100MHZ_NS:		PCIX M1 100MHZ mode not supported.
134a23fd11yl * @XGE_HAL_PCIX_M1_133MHZ_NS:		PCIX M1 133MHZ not supported.
135a23fd11yl * @XGE_HAL_PCIX_M2_RESERVED:		PCIX M2 reserved.
136a23fd11yl * @XGE_HAL_PCIX_533_RESERVED:		PCIX 533 reserved.
137a23fd11yl * @XGE_HAL_PCI_BASIC_MODE:		PCI basic mode, XENA specific value.
138a23fd11yl * @XGE_HAL_PCIX_BASIC_MODE:		PCIX basic mode, XENA specific value.
139a23fd11yl * @XGE_HAL_PCI_INVALID_MODE:		Invalid PCI or PCIX mode.
140a23fd11yl *
141a23fd11yl */
142a23fd11yltypedef enum xge_hal_pci_mode_e {
143a23fd11yl	XGE_HAL_PCI_33MHZ_MODE		= 0x0,
144a23fd11yl	XGE_HAL_PCI_66MHZ_MODE		= 0x1,
145a23fd11yl	XGE_HAL_PCIX_M1_66MHZ_MODE	= 0x2,
146a23fd11yl	XGE_HAL_PCIX_M1_100MHZ_MODE	= 0x3,
147a23fd11yl	XGE_HAL_PCIX_M1_133MHZ_MODE	= 0x4,
148a23fd11yl	XGE_HAL_PCIX_M2_66MHZ_MODE	= 0x5,
149a23fd11yl	XGE_HAL_PCIX_M2_100MHZ_MODE	= 0x6,
150a23fd11yl	XGE_HAL_PCIX_M2_133MHZ_MODE	= 0x7,
151a23fd11yl	XGE_HAL_PCIX_M1_RESERVED	= 0x8,
152a23fd11yl	XGE_HAL_PCIX_M1_66MHZ_NS	= 0xA,
153a23fd11yl	XGE_HAL_PCIX_M1_100MHZ_NS	= 0xB,
154a23fd11yl	XGE_HAL_PCIX_M1_133MHZ_NS	= 0xC,
155a23fd11yl	XGE_HAL_PCIX_M2_RESERVED	= 0xD,
156a23fd11yl	XGE_HAL_PCIX_533_RESERVED	= 0xE,
157a23fd11yl	XGE_HAL_PCI_BASIC_MODE		= 0x10,
158a23fd11yl	XGE_HAL_PCIX_BASIC_MODE		= 0x11,
159a23fd11yl	XGE_HAL_PCI_INVALID_MODE	= 0x12,
160a23fd11yl} xge_hal_pci_mode_e;
161a23fd11yl
162a23fd11yl/**
163a23fd11yl * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
164a23fd11yl * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ:	PCI bus frequency 33MHZ
165a23fd11yl * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ:	PCI bus frequency 66MHZ
166a23fd11yl * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ:	PCI bus frequency 100MHZ
167a23fd11yl * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ:	PCI bus frequency 133MHZ
1688347601yl * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ:	PCI bus frequency 200MHZ
1697eced41xw * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ:	PCI bus frequency 250MHZ
170a23fd11yl * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ:	PCI bus frequency 266MHZ
171a23fd11yl * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN:	Unrecognized PCI bus frequency value.
172a23fd11yl *
173a23fd11yl */
174a23fd11yltypedef enum xge_hal_pci_bus_frequency_e {
175a23fd11yl	XGE_HAL_PCI_BUS_FREQUENCY_33MHZ		= 33,
176a23fd11yl	XGE_HAL_PCI_BUS_FREQUENCY_66MHZ		= 66,
177a23fd11yl	XGE_HAL_PCI_BUS_FREQUENCY_100MHZ	= 100,
178a23fd11yl	XGE_HAL_PCI_BUS_FREQUENCY_133MHZ	= 133,
179a23fd11yl	XGE_HAL_PCI_BUS_FREQUENCY_200MHZ	= 200,
1807eced41xw	XGE_HAL_PCI_BUS_FREQUENCY_250MHZ	= 250,
181a23fd11yl	XGE_HAL_PCI_BUS_FREQUENCY_266MHZ	= 266,
182a23fd11yl	XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN	= 0
183a23fd11yl} xge_hal_pci_bus_frequency_e;
184a23fd11yl
185a23fd11yl/**
186a23fd11yl * enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
187a23fd11yl * @XGE_HAL_PCI_BUS_WIDTH_64BIT:	64 bit bus width.
188a23fd11yl * @XGE_HAL_PCI_BUS_WIDTH_32BIT:	32 bit bus width.
189a23fd11yl * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN:  unknown bus width.
190a23fd11yl *
191a23fd11yl */
192a23fd11yltypedef enum xge_hal_pci_bus_width_e {
193a23fd11yl	XGE_HAL_PCI_BUS_WIDTH_64BIT	= 0,
194a23fd11yl	XGE_HAL_PCI_BUS_WIDTH_32BIT	= 1,
195a23fd11yl	XGE_HAL_PCI_BUS_WIDTH_UNKNOWN	= 2,
196a23fd11yl} xge_hal_pci_bus_width_e;
197a23fd11yl
198a23fd11yl#if defined (XGE_HAL_CONFIG_LRO)
199a23fd11yl
200a23fd11yl#define IP_TOTAL_LENGTH_OFFSET			2
201a23fd11yl#define IP_FAST_PATH_HDR_MASK			0x45
202a23fd11yl#define TCP_FAST_PATH_HDR_MASK1			0x50
203a23fd11yl#define TCP_FAST_PATH_HDR_MASK2			0x10
204a23fd11yl#define TCP_FAST_PATH_HDR_MASK3			0x18
205a23fd11yl#define IP_SOURCE_ADDRESS_OFFSET		12
206a23fd11yl#define IP_DESTINATION_ADDRESS_OFFSET		16
207a23fd11yl#define TCP_DESTINATION_PORT_OFFSET		2
208a23fd11yl#define TCP_SOURCE_PORT_OFFSET			0
209a23fd11yl#define TCP_DATA_OFFSET_OFFSET			12
210a23fd11yl#define TCP_WINDOW_OFFSET			14
211a23fd11yl#define TCP_SEQUENCE_NUMBER_OFFSET		4
212a23fd11yl#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET	8
213a23fd11yl
214a23fd11yltypedef struct tcplro {
215a23fd11yl	u16   source;
216a23fd11yl	u16   dest;
217a23fd11yl	u32   seq;
218a23fd11yl	u32   ack_seq;
219a23fd11yl	u8    doff_res;
220a23fd11yl	u8    ctrl;
221a23fd11yl	u16   window;
222a23fd11yl	u16   check;
223a23fd11yl	u16   urg_ptr;
224a23fd11yl} tcplro_t;
225a23fd11yl
226a23fd11yltypedef struct iplro {
227a23fd11yl	u8    version_ihl;
228a23fd11yl	u8    tos;
229a23fd11yl	u16   tot_len;
230a23fd11yl	u16   id;
231a23fd11yl	u16   frag_off;
232a23fd11yl	u8    ttl;
233a23fd11yl	u8    protocol;
234a23fd11yl	u16   check;
235a23fd11yl	u32   saddr;
236a23fd11yl	u32   daddr;
237a23fd11yl	/*The options start here. */
238a23fd11yl} iplro_t;
239a23fd11yl
240a23fd11yl/*
241a23fd11yl * LRO object, one per each LRO session.
242a23fd11yl*/
243a23fd11yltypedef struct lro {
244a23fd11yl	/* non-linear: contains scatter-gather list of
245a23fd11yl	xframe-mapped received buffers */
246a23fd11yl	OS_NETSTACK_BUF		os_buf;
247a23fd11yl	OS_NETSTACK_BUF		os_buf_end;
248a23fd11yl
249a23fd11yl	/* link layer header of the first frame;
250a23fd11yl	remains intack throughout the processing */
251a23fd11yl	u8			*ll_hdr;
252a23fd11yl
253a23fd11yl	/* IP header - gets _collapsed_ */
254a23fd11yl	iplro_t			*ip_hdr;
255a23fd11yl
256a23fd11yl	/* transport header - gets _collapsed_ */
257a23fd11yl	tcplro_t		*tcp_hdr;
258a23fd11yl
259a23fd11yl	/* Next tcp sequence number */
260a23fd11yl	u32			tcp_next_seq_num;
261a23fd11yl	/* Current tcp seq & ack */
262a23fd11yl	u32			tcp_seq_num;
263a23fd11yl	u32			tcp_ack_num;
264a23fd11yl
265a23fd11yl	/* total number of accumulated (so far) frames */
266a23fd11yl	int			sg_num;
267a23fd11yl
268a23fd11yl	/* total data length */
269a23fd11yl	int			total_length;
270a23fd11yl
271a23fd11yl	/* receive side hash value, available from Hercules */
272a23fd11yl	u32			rth_value;
273a23fd11yl
274a23fd11yl	/* In use */
275a23fd11yl	u8			in_use;
276a23fd11yl
277a23fd11yl	/* Total length of the fragments clubbed with the inital frame */
278a23fd11yl	u32			frags_len;
2798347601yl
2808347601yl	/* LRO frame contains time stamp, if (ts_off != -1) */
2818347601yl	int 			ts_off;
2828347601yl
283a23fd11yl} lro_t;
284a23fd11yl#endif
285a23fd11yl
286a23fd11yl/*
287a23fd11yl * xge_hal_spdm_entry_t
288a23fd11yl *
289a23fd11yl * Represents a single spdm entry in the SPDM table.
290a23fd11yl */
291a23fd11yltypedef struct xge_hal_spdm_entry_t {
292a23fd11yl	xge_hal_ipaddr_t  src_ip;
293a23fd11yl	xge_hal_ipaddr_t  dst_ip;
294a23fd11yl	u32 jhash_value;
295a23fd11yl	u16 l4_sp;
296a23fd11yl	u16 l4_dp;
297a23fd11yl	u16 spdm_entry;
298a23fd11yl	u8  in_use;
299a23fd11yl	u8  is_tcp;
300a23fd11yl	u8  is_ipv4;
301a23fd11yl	u8  tgt_queue;
302a23fd11yl} xge_hal_spdm_entry_t;
303a23fd11yl
3047eced41xw#if defined(XGE_HAL_CONFIG_LRO)
3057eced41xwtypedef struct {
3067eced41xw	lro_t			lro_pool[XGE_HAL_LRO_MAX_BUCKETS];
3077eced41xw	int			lro_next_idx;
3087eced41xw	lro_t			*lro_recent;
3097eced41xw} xge_hal_lro_desc_t;
3107eced41xw#endif
3118347601yl/*
3127eced41xw * xge_hal_vpd_data_t
3137eced41xw *
3147eced41xw * Represents vpd capabilty structure
3158347601yl */
3167eced41xwtypedef struct xge_hal_vpd_data_t {
3177eced41xw        u8      product_name[XGE_HAL_VPD_LENGTH];
3187eced41xw        u8      serial_num[XGE_HAL_VPD_LENGTH];
3197eced41xw} xge_hal_vpd_data_t;
320a23fd11yl
321a23fd11yl/*
322a23fd11yl * xge_hal_device_t
323a23fd11yl *
324a23fd11yl * HAL device object. Represents Xframe.
325a23fd11yl */
326a23fd11yltypedef struct {
3278347601yl	unsigned int		magic;
328a23fd11yl	pci_reg_h		regh0;
329a23fd11yl	pci_reg_h		regh1;
330a23fd11yl	pci_reg_h		regh2;
331a23fd11yl	char			*bar0;
332a23fd11yl	char			*isrbar0;
333a23fd11yl	char			*bar1;
334a23fd11yl	char			*bar2;
335a23fd11yl	pci_irq_h		irqh;
336a23fd11yl	pci_cfg_h		cfgh;
337a23fd11yl	pci_dev_h		pdev;
338a23fd11yl	xge_hal_pci_config_t	pci_config_space;
3397eced41xw	xge_hal_pci_config_t	pci_config_space_bios;
340a23fd11yl	xge_hal_device_config_t	config;
341a23fd11yl	xge_list_t		free_channels;
342a23fd11yl	xge_list_t		fifo_channels;
343a23fd11yl	xge_list_t		ring_channels;
344a23fd11yl	volatile int		is_initialized;
345a23fd11yl	volatile int		terminating;
346a23fd11yl	xge_hal_stats_t		stats;
347a23fd11yl	macaddr_t		macaddr[1];
348a23fd11yl	xge_queue_h		queueh;
349a23fd11yl	volatile int		mcast_refcnt;
350a23fd11yl	int			is_promisc;
351a23fd11yl	volatile xge_hal_device_link_state_e	link_state;
352a23fd11yl	void			*upper_layer_info;
353a23fd11yl	xge_hal_device_attr_t	orig_attr;
354a23fd11yl	u16			device_id;
355a23fd11yl	u8			revision;
356a23fd11yl	int			msi_enabled;
357a23fd11yl	int			hw_is_initialized;
358a23fd11yl	u64			inject_serr;
359a23fd11yl	u64			inject_ecc;
360a23fd11yl	u8			inject_bad_tcode;
361a23fd11yl	int			inject_bad_tcode_for_chan_type;
362a23fd11yl        int                     reset_needed_after_close;
3638347601yl	int			tti_enabled;
3648347601yl	xge_hal_tti_config_t	bimodal_tti[XGE_HAL_MAX_RING_NUM];
3658347601yl	int			bimodal_timer_val_us;
3668347601yl	int			bimodal_urange_a_en;
3678347601yl	int			bimodal_intr_cnt;
368a23fd11yl	char			*spdm_mem_base;
369a23fd11yl	u16			spdm_max_entries;
370a23fd11yl	xge_hal_spdm_entry_t	**spdm_table;
371a23fd11yl	spinlock_t		spdm_lock;
372a23fd11yl#if defined(XGE_HAL_CONFIG_LRO)
3737eced41xw        xge_hal_lro_desc_t      lro_desc[XGE_HAL_MAX_RING_NUM];
374a23fd11yl#endif
375a23fd11yl	spinlock_t		xena_post_lock;
3768347601yl
3778347601yl	/* bimodal workload stats */
3788347601yl	int			irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
3798347601yl	int			irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
3808347601yl	int			irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
3818347601yl	int			irq_workload_txd[XGE_HAL_MAX_FIFO_NUM];
3828347601yl	int			irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM];
3838347601yl	int			irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM];
3848347601yl
3858347601yl	int			mtu_first_time_set;
386a23fd11yl	u64			rxufca_lbolt;
387a23fd11yl	u64			rxufca_lbolt_time;
388a23fd11yl	u64			rxufca_intr_thres;
389a23fd11yl	char*                   dump_buf;
390a23fd11yl	xge_hal_pci_mode_e	pci_mode;
391a23fd11yl	xge_hal_pci_bus_frequency_e bus_frequency;
392a23fd11yl	xge_hal_pci_bus_width_e	bus_width;
3937eced41xw	xge_hal_vpd_data_t      vpd_data;
394a23fd11yl	volatile int		in_poll;
3957eced41xw	u64			msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR];
396a23fd11yl} xge_hal_device_t;
397a23fd11yl
398a23fd11yl
399a23fd11yl/* ========================== PRIVATE API ================================= */
400a23fd11yl
4017eced41xwvoid
4027eced41xw__hal_device_event_queued(void *data, int event_type);
4037eced41xw
4047eced41xwxge_hal_status_e
4057eced41xw__hal_device_set_swapper(xge_hal_device_t *hldev);
4067eced41xw
4077eced41xwxge_hal_status_e
4087eced41xw__hal_device_rth_it_configure(xge_hal_device_t *hldev);
4097eced41xw
4107eced41xwxge_hal_status_e
4117eced41xw__hal_device_rth_spdm_configure(xge_hal_device_t *hldev);
4127eced41xw
4137eced41xwxge_hal_status_e
4147eced41xw__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status);
4157eced41xw
4167eced41xwxge_hal_status_e
4177eced41xw__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason);
4187eced41xw
4197eced41xwxge_hal_status_e
4207eced41xw__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line,
4217eced41xw                        u16 spdm_entry, u64 *spdm_line_val);
4227eced41xw
423a23fd11ylvoid __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
424a23fd11yl			void *addr);
425a23fd11yl
426a23fd11ylvoid __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
427a23fd11yl			void *addr);
4287eced41xwvoid __hal_device_get_vpd_data(xge_hal_device_t *hldev);
429a23fd11yl
430a23fd11ylxge_hal_status_e
431a23fd11yl__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
432a23fd11yl
433a23fd11ylxge_hal_status_e
434a23fd11yl__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
435a23fd11yl
436a23fd11ylxge_hal_status_e
437a23fd11yl__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
438a23fd11yl
439a23fd11ylxge_hal_status_e
440a23fd11yl__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
441a23fd11yl
442a23fd11ylxge_hal_status_e
443a23fd11yl__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
444a23fd11yl
445a23fd11ylxge_hal_status_e
446a23fd11yl__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
447a23fd11yl
448a23fd11ylxge_hal_status_e
449a23fd11yl__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
450a23fd11yl
451a23fd11ylxge_hal_status_e
452a23fd11yl__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
453a23fd11yl
454a23fd11ylxge_hal_status_e
455a23fd11yl__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
456a23fd11yl
457a23fd11ylxge_hal_status_e
458a23fd11yl__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
459a23fd11yl			int max_millis);
460a23fd11ylxge_hal_status_e
461a23fd11yl__hal_device_rts_mac_configure(xge_hal_device_t *hldev);
462a23fd11yl
4638347601ylxge_hal_status_e
4648347601yl__hal_device_rts_qos_configure(xge_hal_device_t *hldev);
4658347601yl
4668347601ylxge_hal_status_e
4677eced41xw__hal_device_rts_port_configure(xge_hal_device_t *hldev);
4687eced41xw
4697eced41xwxge_hal_status_e
4708347601yl__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime);
4718347601yl
4727eced41xwvoid
4737eced41xw__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag);
4747eced41xw
4757eced41xwvoid
4767eced41xw__hal_device_msix_intr_endis(xge_hal_device_t *hldev,
4777eced41xw			      xge_hal_channel_t *channel, int flag);
4787eced41xw
479a23fd11yl/* =========================== PUBLIC API ================================= */
480a23fd11yl
481a23fd11ylunsigned int
482a23fd11yl__hal_fix_time_ival_herc(xge_hal_device_t *hldev,
483a23fd11yl			 unsigned int time_ival);
484a23fd11ylxge_hal_status_e
485a23fd11ylxge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
486a23fd11yl		u32 itable_size);
487a23fd11yl
488a23fd11ylvoid
489a23fd11ylxge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
490a23fd11yl		u16 bucket_size);
491a23fd11yl
492a23fd11ylvoid
493a23fd11ylxge_hal_rts_rth_init(xge_hal_device_t *hldev);
494a23fd11yl
495a23fd11ylvoid
496a23fd11ylxge_hal_rts_rth_clr(xge_hal_device_t *hldev);
497a23fd11yl
498a23fd11ylvoid
499a23fd11ylxge_hal_rts_rth_start(xge_hal_device_t *hldev);
500a23fd11yl
501a23fd11ylvoid
502a23fd11ylxge_hal_rts_rth_stop(xge_hal_device_t *hldev);
503a23fd11yl
504a23fd11ylvoid
505a23fd11ylxge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
506a23fd11yl
507a23fd11ylxge_hal_status_e
508a23fd11ylxge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
509a23fd11yl
510a23fd11ylxge_hal_status_e
511a23fd11ylxge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
512a23fd11yl
5137eced41xwint xge_hal_reinitialize_hw(xge_hal_device_t * hldev);
5147eced41xw
5157eced41xwxge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev);
5168347601yl/**
5178347601yl * xge_hal_device_rti_reconfigure
5187eced41xw * @hldev: Hal Device
5198347601yl */
5208347601ylstatic inline xge_hal_status_e
5218347601ylxge_hal_device_rti_reconfigure(xge_hal_device_t *hldev)
5228347601yl{
5238347601yl	return __hal_device_rti_configure(hldev, 1);
5248347601yl}
525a23fd11yl
526a23fd11yl/**
5277eced41xw * xge_hal_device_rts_port_reconfigure
5287eced41xw * @hldev: Hal Device
5297eced41xw */
5307eced41xwstatic inline xge_hal_status_e
5317eced41xwxge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev)
5327eced41xw{
5337eced41xw	return __hal_device_rts_port_configure(hldev);
5347eced41xw}
5357eced41xw
5367eced41xw/**
537a23fd11yl * xge_hal_device_is_initialized - Returns 0 if device is not
538a23fd11yl * initialized, non-zero otherwise.
539a23fd11yl * @devh: HAL device handle.
540a23fd11yl *
541a23fd11yl * Returns 0 if device is not initialized, non-zero otherwise.
542a23fd11yl */
543a23fd11ylstatic inline int
544a23fd11ylxge_hal_device_is_initialized(xge_hal_device_h devh)
545a23fd11yl{
546a23fd11yl	return ((xge_hal_device_t*)devh)->is_initialized;
547a23fd11yl}
548a23fd11yl
549a23fd11yl
550a23fd11yl/**
551a23fd11yl * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
552a23fd11yl * @devh: HAL device handle.
553a23fd11yl *
554a23fd11yl * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
555a23fd11yl */
556a23fd11ylstatic inline int
557a23fd11ylxge_hal_device_in_poll(xge_hal_device_h devh)
558a23fd11yl{
559a23fd11yl	return ((xge_hal_device_t*)devh)->in_poll;
560a23fd11yl}
561a23fd11yl
562a23fd11yl
563a23fd11yl/**
564a23fd11yl * xge_hal_device_inject_ecc - Inject ECC error.
565a23fd11yl * @devh: HAL device, pointer to xge_hal_device_t structure.
566a23fd11yl * @err_reg: Contains the error register.
567a23fd11yl *
568a23fd11yl * This function is used to inject ECC error into the driver flow.
569a23fd11yl * This facility can be used to test the driver flow in the
570a23fd11yl * case of ECC error is reported by the firmware.
571a23fd11yl *
572a23fd11yl * Returns: void
573a23fd11yl * See also: xge_hal_device_inject_serr(),
574a23fd11yl * xge_hal_device_inject_bad_tcode()
575a23fd11yl */
576a23fd11ylstatic inline void
577a23fd11ylxge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
578a23fd11yl{
579a23fd11yl        ((xge_hal_device_t*)devh)->inject_ecc = err_reg;
580a23fd11yl}
581a23fd11yl
582a23fd11yl
583a23fd11yl/**
584a23fd11yl * xge_hal_device_inject_serr - Inject SERR error.
585a23fd11yl * @devh: HAL device, pointer to xge_hal_device_t structure.
586a23fd11yl * @err_reg: Contains the error register.
587a23fd11yl *
588a23fd11yl * This function is used to inject SERR error into the driver flow.
589a23fd11yl * This facility can be used to test the driver flow in the
590a23fd11yl * case of SERR error is reported by firmware.
591a23fd11yl *
592a23fd11yl * Returns: void
593a23fd11yl * See also: xge_hal_device_inject_ecc(),
594a23fd11yl * xge_hal_device_inject_bad_tcode()
595a23fd11yl */
596a23fd11ylstatic inline void
597a23fd11ylxge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
598a23fd11yl{
599a23fd11yl        ((xge_hal_device_t*)devh)->inject_serr = err_reg;
600a23fd11yl}
601a23fd11yl
602a23fd11yl
603a23fd11yl/**
604a23fd11yl * xge_hal_device_inject_bad_tcode - Inject  Bad transfer code.
605a23fd11yl * @devh: HAL device, pointer to xge_hal_device_t structure.
606a23fd11yl * @chan_type: Channel type (fifo/ring).
607a23fd11yl * @t_code: Transfer code.
608a23fd11yl *
609a23fd11yl * This function is used to inject bad (Tx/Rx Data)transfer code
610a23fd11yl * into the driver flow.
611a23fd11yl *
612a23fd11yl * This facility can be used to test the driver flow in the
613a23fd11yl * case of bad transfer code reported by firmware for a Tx/Rx data
614a23fd11yl * transfer.
615a23fd11yl *
616a23fd11yl * Returns: void
617a23fd11yl * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
618a23fd11yl */
619a23fd11ylstatic inline void
620a23fd11ylxge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
621a23fd11yl{
622a23fd11yl        ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
623a23fd11yl        ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
624a23fd11yl}
625a23fd11yl
626a23fd11ylvoid xge_hal_device_msi_enable(xge_hal_device_h	devh);
627a23fd11yl
628a23fd11yl/*
629a23fd11yl * xge_hal_device_msi_mode - Is MSI enabled?
630a23fd11yl * @devh: HAL device handle.
631a23fd11yl *
632a23fd11yl * Returns 0 if MSI is enabled for the specified device,
633a23fd11yl * non-zero otherwise.
634a23fd11yl */
635a23fd11ylstatic inline int
636a23fd11ylxge_hal_device_msi_mode(xge_hal_device_h devh)
637a23fd11yl{
638a23fd11yl	return ((xge_hal_device_t*)devh)->msi_enabled;
639a23fd11yl}
640a23fd11yl
641a23fd11yl/**
642a23fd11yl * xge_hal_device_queue - Get per-device event queue.
643a23fd11yl * @devh: HAL device handle.
644a23fd11yl *
645a23fd11yl * Returns: event queue associated with the specified HAL device.
646a23fd11yl */
647a23fd11ylstatic inline xge_queue_h
648a23fd11ylxge_hal_device_queue (xge_hal_device_h devh)
649a23fd11yl{
650a23fd11yl	return ((xge_hal_device_t*)devh)->queueh;
651a23fd11yl}
652a23fd11yl
653a23fd11yl/**
654a23fd11yl * xge_hal_device_attr - Get original (user-specified) device
655a23fd11yl * attributes.
656a23fd11yl * @devh: HAL device handle.
657a23fd11yl *
658a23fd11yl * Returns: original (user-specified) device attributes.
659a23fd11yl */
660a23fd11ylstatic inline xge_hal_device_attr_t*
661a23fd11ylxge_hal_device_attr(xge_hal_device_h devh)
662a23fd11yl{
663a23fd11yl	return &((xge_hal_device_t*)devh)->orig_attr;
664a23fd11yl}
665a23fd11yl
666a23fd11yl/**
667a23fd11yl * xge_hal_device_private_set - Set ULD context.
668a23fd11yl * @devh: HAL device handle.
669a23fd11yl * @data: pointer to ULD context
670a23fd11yl *
671a23fd11yl * Use HAL device to set upper-layer driver (ULD) context.
672a23fd11yl *
673a23fd11yl * See also: xge_hal_device_from_private(), xge_hal_device_private()
674a23fd11yl */
675a23fd11ylstatic inline void
676a23fd11ylxge_hal_device_private_set(xge_hal_device_h devh, void *data)
677a23fd11yl{
678a23fd11yl	((xge_hal_device_t*)devh)->upper_layer_info = data;
679a23fd11yl}
680a23fd11yl
681a23fd11yl/**
682a23fd11yl * xge_hal_device_private - Get ULD context.
683a23fd11yl * @devh: HAL device handle.
684a23fd11yl *
685a23fd11yl * Use HAL device to get upper-layer driver (ULD) context.
686a23fd11yl *
687a23fd11yl * Returns:  ULD context.
688a23fd11yl *
689a23fd11yl * See also: xge_hal_device_from_private(), xge_hal_device_private_set()
690a23fd11yl */
691a23fd11ylstatic inline void*
692a23fd11ylxge_hal_device_private(xge_hal_device_h devh)
693a23fd11yl{
694a23fd11yl	return ((xge_hal_device_t*)devh)->upper_layer_info;
695a23fd11yl}
696a23fd11yl
697a23fd11yl/**
698a23fd11yl * xge_hal_device_from_private - Get HAL device object from private.
699a23fd11yl * @info_ptr: ULD context.
700a23fd11yl *
701a23fd11yl * Use ULD context to get HAL device.
702a23fd11yl *
703a23fd11yl * Returns:  Device handle.
704a23fd11yl *
705a23fd11yl * See also: xge_hal_device_private(), xge_hal_device_private_set()
706a23fd11yl */
707a23fd11ylstatic inline xge_hal_device_h
708a23fd11ylxge_hal_device_from_private(void *info_ptr)
709a23fd11yl{
7107eced41xw	return xge_container_of((void ** ) info_ptr, xge_hal_device_t,
711a23fd11yl	upper_layer_info);
712a23fd11yl}
713a23fd11yl
714a23fd11yl/**
715a23fd11yl * xge_hal_device_mtu_check - check MTU value for ranges
716a23fd11yl * @hldev: the device
717a23fd11yl * @new_mtu: new MTU value to check
718a23fd11yl *
719a23fd11yl * Will do sanity check for new MTU value.
720a23fd11yl *
721a23fd11yl * Returns: XGE_HAL_OK - success.
722a23fd11yl * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
723a23fd11yl *
724a23fd11yl * See also: xge_hal_device_mtu_set()
725a23fd11yl */
726a23fd11ylstatic inline xge_hal_status_e
727a23fd11ylxge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
728a23fd11yl{
729a23fd11yl	if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
730a23fd11yl		return XGE_HAL_ERR_INVALID_MTU_SIZE;
731a23fd11yl	}
732a23fd11yl
733a23fd11yl	return XGE_HAL_OK;
734a23fd11yl}
735a23fd11yl
736a23fd11ylvoid xge_hal_device_bcast_enable(xge_hal_device_h devh);
737a23fd11yl
738a23fd11ylvoid xge_hal_device_bcast_disable(xge_hal_device_h devh);
739a23fd11yl
740a23fd11ylvoid xge_hal_device_terminating(xge_hal_device_h devh);
741a23fd11yl
742a23fd11ylxge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
743a23fd11yl		xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
744a23fd11yl
745a23fd11ylvoid xge_hal_device_terminate(xge_hal_device_t *hldev);
746a23fd11yl
747a23fd11ylxge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
748a23fd11yl
749a23fd11ylxge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
750a23fd11yl		int index,  macaddr_t *macaddr);
751a23fd11yl
752a23fd11ylxge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
753a23fd11yl		int index,  macaddr_t macaddr);
754a23fd11yl
7557eced41xwxge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev,
7567eced41xw		int index);
7577eced41xw
758a23fd11ylint xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
759a23fd11yl
760a23fd11ylxge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
761a23fd11yl
762a23fd11ylxge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
763a23fd11yl
764a23fd11ylvoid xge_hal_device_intr_enable(xge_hal_device_t *hldev);
765a23fd11yl
766a23fd11ylvoid xge_hal_device_intr_disable(xge_hal_device_t *hldev);
767a23fd11yl
768a23fd11ylxge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
769a23fd11yl
770a23fd11ylxge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
771a23fd11yl
772a23fd11ylvoid xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
773a23fd11yl
774a23fd11ylvoid xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
775a23fd11yl
776a23fd11ylxge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
777a23fd11yl
778a23fd11ylxge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
779a23fd11yl
780a23fd11ylxge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
781a23fd11yl					     xge_hal_dtr_h dtrh,
782a23fd11yl					     u8 t_code);
783a23fd11yl
784a23fd11ylxge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
785a23fd11yl			xge_hal_device_link_state_e *ls);
786a23fd11yl
787a23fd11ylvoid xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
788a23fd11yl			int one_shot);
789a23fd11yl
790a23fd11ylvoid xge_hal_device_poll(xge_hal_device_h devh);
791a23fd11yl
792a23fd11ylxge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
793a23fd11yl
794a23fd11ylint xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
795a23fd11yl
7961939740Sherry Moorevoid xge_hal_device_quiesce(xge_hal_device_t *hldev, xge_hal_device_h devh);
7971939740Sherry Moore
798a23fd11ylxge_hal_status_e
799a23fd11ylxge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
800a23fd11yl			xge_hal_pci_bus_frequency_e *bus_frequency,
801a23fd11yl			xge_hal_pci_bus_width_e *bus_width);
802a23fd11yl
803a23fd11ylxge_hal_status_e
804a23fd11ylxge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
805a23fd11yl			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
806a23fd11yl			u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
807a23fd11yl
808a23fd11ylxge_hal_status_e
809a23fd11ylxge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
810a23fd11yl			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
811a23fd11yl			u8 is_tcp, u8 is_ipv4);
812a23fd11yl
8138347601ylxge_hal_status_e
8148347601ylxge_hal_device_rts_section_enable(xge_hal_device_h devh, int index);
8158347601yl
816a23fd11ylint
817a23fd11ylxge_hal_device_is_closed (xge_hal_device_h devh);
818a23fd11yl
8197eced41xw/* private functions, don't use them in ULD */
8208347601yl
8217eced41xwvoid __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
8228347601yl
8237eced41xwu64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
8248347601yl
8258347601yl
826a23fd11yl/* Some function protoypes for MSI implementation. */
827a23fd11ylxge_hal_status_e
8287eced41xwxge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi,
8297eced41xw			 u32 msg_val);
830a23fd11ylvoid
831a23fd11ylxge_hal_mask_msi(xge_hal_device_t *hldev);
8327eced41xw
833a23fd11ylvoid
834a23fd11ylxge_hal_unmask_msi(xge_hal_channel_h channelh);
8357eced41xw
836a23fd11ylxge_hal_status_e
837a23fd11ylxge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
838a23fd11yl
8397eced41xwxge_hal_status_e
8407eced41xwxge_hal_mask_msix(xge_hal_device_h devh, int msi_id);
8417eced41xw
8427eced41xwxge_hal_status_e
8437eced41xwxge_hal_unmask_msix(xge_hal_device_h devh, int msi_id);
8447eced41xw
8457eced41xw#if defined(XGE_HAL_CONFIG_LRO)
8467eced41xwxge_hal_status_e
8477eced41xwxge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
8487eced41xw
8497eced41xwvoid
8507eced41xwxge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev);
8517eced41xw#endif
852a23fd11yl
853a23fd11yl#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
854a23fd11yl#define __HAL_STATIC_DEVICE
855a23fd11yl#define __HAL_INLINE_DEVICE
856a23fd11yl
857a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
858a23fd11ylxge_hal_device_rev(xge_hal_device_t *hldev);
859a23fd11yl
860a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
861a23fd11ylxge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
862a23fd11yl
863a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
864a23fd11ylxge_hal_device_clear_rx(xge_hal_device_t *hldev);
865a23fd11yl
866a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
867a23fd11ylxge_hal_device_clear_tx(xge_hal_device_t *hldev);
868a23fd11yl
869a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
870a23fd11ylxge_hal_device_continue_irq(xge_hal_device_t *hldev);
871a23fd11yl
872a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
873a23fd11ylxge_hal_device_handle_irq(xge_hal_device_t *hldev);
874a23fd11yl
875a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
876a23fd11ylxge_hal_device_bar0(xge_hal_device_t *hldev);
877a23fd11yl
878a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
879a23fd11ylxge_hal_device_isrbar0(xge_hal_device_t *hldev);
880a23fd11yl
881a23fd11yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
882a23fd11ylxge_hal_device_bar1(xge_hal_device_t *hldev);
883a23fd11yl
884