1a23fd118Syl /* 2a23fd118Syl * CDDL HEADER START 3a23fd118Syl * 4a23fd118Syl * The contents of this file are subject to the terms of the 5a23fd118Syl * Common Development and Distribution License (the "License"). 6a23fd118Syl * You may not use this file except in compliance with the License. 7a23fd118Syl * 8a23fd118Syl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9a23fd118Syl * or http://www.opensolaris.org/os/licensing. 10a23fd118Syl * See the License for the specific language governing permissions 11a23fd118Syl * and limitations under the License. 12a23fd118Syl * 13a23fd118Syl * When distributing Covered Code, include this CDDL HEADER in each 14a23fd118Syl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15a23fd118Syl * If applicable, add the following below this CDDL HEADER, with the 16a23fd118Syl * fields enclosed by brackets "[]" replaced with your own identifying 17a23fd118Syl * information: Portions Copyright [yyyy] [name of copyright owner] 18a23fd118Syl * 19a23fd118Syl * CDDL HEADER END 20a23fd118Syl * 218347601bSyl * Copyright (c) 2002-2006 Neterion, Inc. 22a23fd118Syl */ 23a23fd118Syl 24a23fd118Syl #ifndef XGE_HAL_CONFIG_H 25a23fd118Syl #define XGE_HAL_CONFIG_H 26a23fd118Syl 27a23fd118Syl #include "xge-os-pal.h" 28a23fd118Syl #include "xgehal-types.h" 29*7eced415Sxw #include "xge-queue.h" 30a23fd118Syl 318347601bSyl __EXTERN_BEGIN_DECLS 328347601bSyl 33a23fd118Syl #define XGE_HAL_DEFAULT_USE_HARDCODE -1 34a23fd118Syl 35*7eced415Sxw #define XGE_HAL_MAX_VIRTUAL_PATHS 8 36*7eced415Sxw #define XGE_HAL_MAX_INTR_PER_VP 4 37*7eced415Sxw 38a23fd118Syl 39a23fd118Syl /** 40a23fd118Syl * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 41a23fd118Syl * @enabled: Set to 1, if TTI feature is enabled. 42a23fd118Syl * @urange_a: Link utilization range A. The value from 0 to 100%. 43a23fd118Syl * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 44a23fd118Syl * each time when (and only when) the line is utilized no more 45a23fd118Syl * than @urange_a percent in the transmit direction, 46a23fd118Syl * and number of transmitted frames is greater or equal @ufc_a. 47a23fd118Syl * @urange_b: Link utilization range B. 48a23fd118Syl * @ufc_b: Frame count for the utilization range B. 49a23fd118Syl * @urange_c: Link utilization range C. 50a23fd118Syl * @ufc_c: Frame count for the utilization range C. 51a23fd118Syl * @urange_d: Link utilization range D. 52a23fd118Syl * @ufc_d: Frame count for the utilization range D. 53a23fd118Syl * @timer_val_us: Interval of time, in microseconds, at which transmit timer 54a23fd118Syl * interrupt is to be generated. Note that unless @timer_ci_en 55a23fd118Syl * is set, the timer interrupt is generated only in presence 56a23fd118Syl * of the transmit traffic. Note also that timer interrupt 57a23fd118Syl * and utilization interrupt are two separate interrupt 58a23fd118Syl * sources. 59a23fd118Syl * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 60a23fd118Syl * interrupt was generated during the interval. 61a23fd118Syl * @timer_ci_en: Enable/disable continuous interrupt. Set this value 62a23fd118Syl * to 1 in order to generate continuous interrupt 63a23fd118Syl * at fixed @timer_val intervals of time, independently 64a23fd118Syl * of whether there is transmit traffic or not. 65a23fd118Syl * @enabled: Set to 1, if TTI feature is enabled. 66a23fd118Syl * 67a23fd118Syl * Xframe transmit interrupt configuration. 68a23fd118Syl * See Xframe User Guide, Section 3.5 "Device Interrupts" 69a23fd118Syl * for more details. Note also (min, max) 70a23fd118Syl * ranges in the body of the xge_hal_tx_intr_config_t structure. 71a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 72a23fd118Syl * the xge_hal_tti_config_t{} structure. Please refer to the 73a23fd118Syl * corresponding header file. 74a23fd118Syl */ 75a23fd118Syl typedef struct xge_hal_tti_config_t { 76a23fd118Syl 77a23fd118Syl int enabled; 78a23fd118Syl #define XGE_HAL_TTI_ENABLE 1 79a23fd118Syl #define XGE_HAL_TTI_DISABLE 0 80a23fd118Syl 81a23fd118Syl /* Line utilization interrupts */ 82a23fd118Syl 83a23fd118Syl int urange_a; 84a23fd118Syl #define XGE_HAL_MIN_TX_URANGE_A 0 85a23fd118Syl #define XGE_HAL_MAX_TX_URANGE_A 100 86a23fd118Syl 87a23fd118Syl int ufc_a; 88a23fd118Syl #define XGE_HAL_MIN_TX_UFC_A 0 89a23fd118Syl #define XGE_HAL_MAX_TX_UFC_A 65535 90a23fd118Syl 91a23fd118Syl int urange_b; 92a23fd118Syl #define XGE_HAL_MIN_TX_URANGE_B 0 93a23fd118Syl #define XGE_HAL_MAX_TX_URANGE_B 100 94a23fd118Syl 95a23fd118Syl int ufc_b; 96a23fd118Syl #define XGE_HAL_MIN_TX_UFC_B 0 97a23fd118Syl #define XGE_HAL_MAX_TX_UFC_B 65535 98a23fd118Syl 99a23fd118Syl int urange_c; 100a23fd118Syl #define XGE_HAL_MIN_TX_URANGE_C 0 101a23fd118Syl #define XGE_HAL_MAX_TX_URANGE_C 100 102a23fd118Syl 103a23fd118Syl int ufc_c; 104a23fd118Syl #define XGE_HAL_MIN_TX_UFC_C 0 105a23fd118Syl #define XGE_HAL_MAX_TX_UFC_C 65535 106a23fd118Syl 107a23fd118Syl int ufc_d; 108a23fd118Syl #define XGE_HAL_MIN_TX_UFC_D 0 109a23fd118Syl #define XGE_HAL_MAX_TX_UFC_D 65535 110a23fd118Syl 111a23fd118Syl int timer_val_us; 1128347601bSyl #define XGE_HAL_MIN_TX_TIMER_VAL 0 1138347601bSyl #define XGE_HAL_MAX_TX_TIMER_VAL 65535 114a23fd118Syl 115a23fd118Syl int timer_ac_en; 116a23fd118Syl #define XGE_HAL_MIN_TX_TIMER_AC_EN 0 117a23fd118Syl #define XGE_HAL_MAX_TX_TIMER_AC_EN 1 118a23fd118Syl 119a23fd118Syl int timer_ci_en; 120a23fd118Syl #define XGE_HAL_MIN_TX_TIMER_CI_EN 0 121a23fd118Syl #define XGE_HAL_MAX_TX_TIMER_CI_EN 1 122a23fd118Syl 123a23fd118Syl 124a23fd118Syl } xge_hal_tti_config_t; 125a23fd118Syl 126a23fd118Syl /** 127a23fd118Syl * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 128a23fd118Syl * @urange_a: Link utilization range A. The value from 0 to 100%. 129a23fd118Syl * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 130a23fd118Syl * each time when (and only when) the line is utilized no more 131a23fd118Syl * than @urange_a percent inbound, 132a23fd118Syl * and number of received frames is greater or equal @ufc_a. 133a23fd118Syl * @urange_b: Link utilization range B. 134a23fd118Syl * @ufc_b: Frame count for the utilization range B. 135a23fd118Syl * @urange_c: Link utilization range C. 136a23fd118Syl * @ufc_c: Frame count for the utilization range C. 137a23fd118Syl * @urange_d: Link utilization range D. 138a23fd118Syl * @ufc_d: Frame count for the utilization range D. 139a23fd118Syl * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 140a23fd118Syl * interrupt was generated during the interval. 141a23fd118Syl * @timer_val_us: Interval of time, in microseconds, at which receive timer 142a23fd118Syl * interrupt is to be generated. The timer interrupt is generated 143a23fd118Syl * only in presence of the inbound traffic. Note also that timer 144a23fd118Syl * interrupt and utilization interrupt are two separate interrupt 145a23fd118Syl * sources. 146a23fd118Syl * 147a23fd118Syl * Xframe receive interrupt configuration. 148a23fd118Syl * See Xframe User Guide, Section 3.5 "Device Interrupts" 149a23fd118Syl * for more details. Note also (min, max) 150a23fd118Syl * ranges in the body of the xge_hal_intr_config_t structure. 151a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 152a23fd118Syl * the xge_hal_rti_config_t{} structure. Please refer to the 153a23fd118Syl * corresponding header file. 154a23fd118Syl */ 155a23fd118Syl typedef struct xge_hal_rti_config_t { 156a23fd118Syl 157a23fd118Syl int urange_a; 158a23fd118Syl #define XGE_HAL_MIN_RX_URANGE_A 0 159a23fd118Syl #define XGE_HAL_MAX_RX_URANGE_A 127 160a23fd118Syl 161a23fd118Syl int ufc_a; 162a23fd118Syl #define XGE_HAL_MIN_RX_UFC_A 0 163a23fd118Syl #define XGE_HAL_MAX_RX_UFC_A 65535 164a23fd118Syl 165a23fd118Syl int urange_b; 166a23fd118Syl #define XGE_HAL_MIN_RX_URANGE_B 0 167a23fd118Syl #define XGE_HAL_MAX_RX_URANGE_B 127 168a23fd118Syl 169a23fd118Syl int ufc_b; 170a23fd118Syl #define XGE_HAL_MIN_RX_UFC_B 0 171a23fd118Syl #define XGE_HAL_MAX_RX_UFC_B 65535 172a23fd118Syl 173a23fd118Syl int urange_c; 174a23fd118Syl #define XGE_HAL_MIN_RX_URANGE_C 0 175a23fd118Syl #define XGE_HAL_MAX_RX_URANGE_C 127 176a23fd118Syl 177a23fd118Syl int ufc_c; 178a23fd118Syl #define XGE_HAL_MIN_RX_UFC_C 0 179a23fd118Syl #define XGE_HAL_MAX_RX_UFC_C 65535 180a23fd118Syl 181a23fd118Syl int ufc_d; 182a23fd118Syl #define XGE_HAL_MIN_RX_UFC_D 0 183a23fd118Syl #define XGE_HAL_MAX_RX_UFC_D 65535 184a23fd118Syl 185a23fd118Syl int timer_ac_en; 186a23fd118Syl #define XGE_HAL_MIN_RX_TIMER_AC_EN 0 187a23fd118Syl #define XGE_HAL_MAX_RX_TIMER_AC_EN 1 188a23fd118Syl 189a23fd118Syl int timer_val_us; 1908347601bSyl #define XGE_HAL_MIN_RX_TIMER_VAL 0 1918347601bSyl #define XGE_HAL_MAX_RX_TIMER_VAL 65535 192a23fd118Syl 193a23fd118Syl } xge_hal_rti_config_t; 194a23fd118Syl 195a23fd118Syl /** 196a23fd118Syl * struct xge_hal_fifo_queue_t - Single fifo configuration. 197a23fd118Syl * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 198a23fd118Syl * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 199a23fd118Syl * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 200a23fd118Syl * Use 0 otherwise. 201*7eced415Sxw * @intr_vector: TBD 202a23fd118Syl * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 203a23fd118Syl * which generally improves latency of the host bridge operation 204a23fd118Syl * (see PCI specification). For valid values please refer 205a23fd118Syl * to xge_hal_fifo_queue_t{} in the driver sources. 206*7eced415Sxw * @priority: TBD 207a23fd118Syl * @configured: Boolean. Use 1 to specify that the fifo is configured. 208a23fd118Syl * Only "configured" fifos can be activated and used to post 209a23fd118Syl * Tx descriptors. Any subset of 8 available fifos can be 210a23fd118Syl * "configured". 211*7eced415Sxw * @tti: TBD 212a23fd118Syl * 213a23fd118Syl * Single fifo configuration. 214a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 215a23fd118Syl * the xge_hal_fifo_queue_t{} structure. Please refer to the 216a23fd118Syl * corresponding header file. 217a23fd118Syl * See also: xge_hal_fifo_config_t{} 218a23fd118Syl */ 219a23fd118Syl typedef struct xge_hal_fifo_queue_t { 220a23fd118Syl int max; 221a23fd118Syl int initial; 222a23fd118Syl #define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 223a23fd118Syl #define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 224a23fd118Syl 225a23fd118Syl int intr; 226a23fd118Syl #define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 227a23fd118Syl #define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 228a23fd118Syl 229*7eced415Sxw int intr_vector; 230*7eced415Sxw #define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 231*7eced415Sxw #define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 232*7eced415Sxw 233a23fd118Syl int no_snoop_bits; 234a23fd118Syl #define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 235a23fd118Syl #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 236a23fd118Syl #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 237a23fd118Syl #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 238a23fd118Syl 2398347601bSyl int priority; 2408347601bSyl #define XGE_HAL_MIN_FIFO_PRIORITY 0 2418347601bSyl #define XGE_HAL_MAX_FIFO_PRIORITY 63 2428347601bSyl 243a23fd118Syl int configured; 244a23fd118Syl #define XGE_HAL_MIN_FIFO_CONFIGURED 0 245a23fd118Syl #define XGE_HAL_MAX_FIFO_CONFIGURED 1 246a23fd118Syl 2478347601bSyl #define XGE_HAL_MAX_FIFO_TTI_NUM 7 2488347601bSyl #define XGE_HAL_MAX_FIFO_TTI_RING_0 56 2498347601bSyl xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; 2508347601bSyl 251a23fd118Syl } xge_hal_fifo_queue_t; 252a23fd118Syl 253a23fd118Syl /** 254a23fd118Syl * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 255a23fd118Syl * @max_frags: Max number of Tx buffers per TxDL (that is, per single 256a23fd118Syl * transmit operation). 257a23fd118Syl * No more than 256 transmit buffers can be specified. 258a23fd118Syl * @max_aligned_frags: Number of fragments to be aligned out of 259a23fd118Syl * maximum fragments (see @max_frags). 260a23fd118Syl * @reserve_threshold: Descriptor reservation threshold. 261a23fd118Syl * At least @reserve_threshold descriptors will remain 262a23fd118Syl * unallocated at all times. 263a23fd118Syl * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 264a23fd118Syl * bytes. Setting @memblock_size to page size ensures 265a23fd118Syl * by-page allocation of descriptors. 128K bytes is the 266a23fd118Syl * maximum supported block size. 267a23fd118Syl * @queue: Array of per-fifo configurations. 268a23fd118Syl * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 269a23fd118Syl * (e.g., to align on a cache line). 270a23fd118Syl * 271a23fd118Syl * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 272a23fd118Syl * structures. 273a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 274a23fd118Syl * the xge_hal_fifo_config_t{} structure. Please refer to the 275a23fd118Syl * corresponding header file. 276a23fd118Syl * See also: xge_hal_ring_queue_t{}. 277a23fd118Syl */ 278a23fd118Syl typedef struct xge_hal_fifo_config_t { 279a23fd118Syl int max_frags; 280a23fd118Syl #define XGE_HAL_MIN_FIFO_FRAGS 1 281a23fd118Syl #define XGE_HAL_MAX_FIFO_FRAGS 256 282a23fd118Syl 283a23fd118Syl int reserve_threshold; 284a23fd118Syl #define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 285a23fd118Syl #define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 286a23fd118Syl 287a23fd118Syl int memblock_size; 288a23fd118Syl #define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 289a23fd118Syl #define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 290a23fd118Syl 291a23fd118Syl int alignment_size; 292a23fd118Syl #define XGE_HAL_MIN_ALIGNMENT_SIZE 0 293a23fd118Syl #define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 294a23fd118Syl 295a23fd118Syl int max_aligned_frags; 296a23fd118Syl /* range: (1, @max_frags) */ 297a23fd118Syl 298a23fd118Syl #define XGE_HAL_MIN_FIFO_NUM 1 299*7eced415Sxw #define XGE_HAL_MAX_FIFO_NUM_HERC 8 300*7eced415Sxw #define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 301*7eced415Sxw #define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 302a23fd118Syl xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 303a23fd118Syl } xge_hal_fifo_config_t; 304a23fd118Syl 305*7eced415Sxw /** 306*7eced415Sxw * struct xge_hal_rts_port_t - RTS port entry 307*7eced415Sxw * @num: Port number 308*7eced415Sxw * @udp: Port is UDP (default TCP) 309*7eced415Sxw * @src: Port is Source (default Destination) 310*7eced415Sxw */ 311*7eced415Sxw typedef struct xge_hal_rts_port_t { 312*7eced415Sxw int num; 313*7eced415Sxw int udp; 314*7eced415Sxw int src; 315*7eced415Sxw } xge_hal_rts_port_t; 316*7eced415Sxw 317a23fd118Syl /** 318a23fd118Syl * struct xge_hal_ring_queue_t - Single ring configuration. 319a23fd118Syl * @max: Max numbers of RxD blocks per queue 320a23fd118Syl * @initial: Initial numbers of RxD blocks per queue 321a23fd118Syl * (can grow up to @max) 322*7eced415Sxw * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 323a23fd118Syl * to Xframe User Guide. 324a23fd118Syl * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 325a23fd118Syl * Note that 64MB of available 326a23fd118Syl * on-board DRAM is shared between receive rings. 327a23fd118Syl * If a single ring is used, @dram_size_mb can be set to 64. 328a23fd118Syl * Sum of all rings' @dram_size_mb cannot exceed 64. 329*7eced415Sxw * @intr_vector: TBD 330a23fd118Syl * @backoff_interval_us: Time (in microseconds), after which Xframe 331a23fd118Syl * tries to download RxDs posted by the host. 332a23fd118Syl * Note that the "backoff" does not happen if host posts receive 333a23fd118Syl * descriptors in the timely fashion. 334a23fd118Syl * @max_frm_len: Maximum frame length that can be received on _that_ ring. 335a23fd118Syl * Setting this field to -1 ensures that the ring will 336a23fd118Syl * "accept" MTU-size frames (note that MTU can be changed at 337a23fd118Syl * runtime). 338a23fd118Syl * Any value other than (-1) specifies a certain "hard" 339a23fd118Syl * limit on the receive frame sizes. 340a23fd118Syl * The field can be used to activate receive frame-length based 341a23fd118Syl * steering. 342a23fd118Syl * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 343a23fd118Syl * to give prioritized access to PCI-X. See Xframe documentation 344a23fd118Syl * for details. 345a23fd118Syl * @rth_en: Enable Receive Traffic Hashing (RTH). 346a23fd118Syl * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 347a23fd118Syl * which generally improves latency of the host bridge operation 348a23fd118Syl * (see PCI specification). For valid values please refer 349a23fd118Syl * to xge_hal_ring_queue_t{} in the driver sources. 350a23fd118Syl * @indicate_max_pkts: Sets maximum number of received frames to be processed 351a23fd118Syl * within single interrupt. 352a23fd118Syl * @configured: Boolean. Use 1 to specify that the ring is configured. 353a23fd118Syl * Only "configured" rings can be activated and used to post 354a23fd118Syl * Rx descriptors. Any subset of 8 available rings can be 355a23fd118Syl * "configured". 356a23fd118Syl * @rts_mac_en: 1 - To enable Receive MAC address steering. 357a23fd118Syl * 0 - To disable Receive MAC address steering. 358*7eced415Sxw * @rth_en: TBD 359*7eced415Sxw * @rts_port_en: TBD 360*7eced415Sxw * @rts_ports: TBD 361a23fd118Syl * @rti: Xframe receive interrupt configuration. 362a23fd118Syl * 363a23fd118Syl * Single ring configuration. 364a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 365a23fd118Syl * the xge_hal_ring_queue_t{} structure. Please refer to the 366a23fd118Syl * corresponding header file. 367a23fd118Syl * See also: xge_hal_fifo_config_t{}. 368a23fd118Syl */ 369*7eced415Sxw typedef struct xge_hal_ring_queue_t { 370a23fd118Syl int max; 371a23fd118Syl int initial; 372a23fd118Syl #define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 373a23fd118Syl #define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 374a23fd118Syl 375a23fd118Syl int buffer_mode; 376*7eced415Sxw #define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 377*7eced415Sxw #define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 378*7eced415Sxw #define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 379*7eced415Sxw #define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 380a23fd118Syl 381a23fd118Syl int dram_size_mb; 382a23fd118Syl #define XGE_HAL_MIN_RING_QUEUE_SIZE 0 383a23fd118Syl #define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 384a23fd118Syl #define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 385a23fd118Syl 386*7eced415Sxw int intr_vector; 387*7eced415Sxw #define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 388*7eced415Sxw #define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 389*7eced415Sxw 390a23fd118Syl int backoff_interval_us; 391a23fd118Syl #define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 392a23fd118Syl #define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 393a23fd118Syl 394a23fd118Syl int max_frm_len; 395a23fd118Syl #define XGE_HAL_MIN_MAX_FRM_LEN -1 396a23fd118Syl #define XGE_HAL_MAX_MAX_FRM_LEN 9622 397a23fd118Syl 398a23fd118Syl int priority; 399*7eced415Sxw #define XGE_HAL_MIN_RING_PRIORITY 0 400*7eced415Sxw #define XGE_HAL_MAX_RING_PRIORITY 7 401a23fd118Syl 402a23fd118Syl int no_snoop_bits; 403a23fd118Syl #define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 404a23fd118Syl #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 405a23fd118Syl #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 406a23fd118Syl #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 407a23fd118Syl 408a23fd118Syl int indicate_max_pkts; 409a23fd118Syl #define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 410a23fd118Syl #define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 411a23fd118Syl 412a23fd118Syl int configured; 413a23fd118Syl #define XGE_HAL_MIN_RING_CONFIGURED 0 414a23fd118Syl #define XGE_HAL_MAX_RING_CONFIGURED 1 415a23fd118Syl 416a23fd118Syl int rts_mac_en; 417a23fd118Syl #define XGE_HAL_MIN_RING_RTS_MAC_EN 0 418a23fd118Syl #define XGE_HAL_MAX_RING_RTS_MAC_EN 1 419a23fd118Syl 420*7eced415Sxw int rth_en; 421*7eced415Sxw #define XGE_HAL_MIN_RING_RTH_EN 0 422*7eced415Sxw #define XGE_HAL_MAX_RING_RTH_EN 1 423*7eced415Sxw 424*7eced415Sxw int rts_port_en; 425*7eced415Sxw #define XGE_HAL_MIN_RING_RTS_PORT_EN 0 426*7eced415Sxw #define XGE_HAL_MAX_RING_RTS_PORT_EN 1 427*7eced415Sxw 428*7eced415Sxw #define XGE_HAL_MAX_STEERABLE_PORTS 32 429*7eced415Sxw xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; 430*7eced415Sxw 431a23fd118Syl xge_hal_rti_config_t rti; 432a23fd118Syl 433a23fd118Syl } xge_hal_ring_queue_t; 434a23fd118Syl 435a23fd118Syl /** 436a23fd118Syl * struct xge_hal_ring_config_t - Array of ring configurations. 437a23fd118Syl * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 438a23fd118Syl * bytes. Setting @memblock_size to page size ensures 439a23fd118Syl * by-page allocation of descriptors. 128K bytes is the 440a23fd118Syl * upper limit. 441a23fd118Syl * @scatter_mode: Xframe supports two receive scatter modes: A and B. 442a23fd118Syl * For details please refer to Xframe User Guide. 4438347601bSyl * @strip_vlan_tag: TBD 444a23fd118Syl * @queue: Array of all Xframe ring configurations. 445a23fd118Syl * 446a23fd118Syl * Array of ring configurations. 447a23fd118Syl * See also: xge_hal_ring_queue_t{}. 448a23fd118Syl */ 449a23fd118Syl typedef struct xge_hal_ring_config_t { 450a23fd118Syl 451a23fd118Syl int memblock_size; 452a23fd118Syl #define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 453a23fd118Syl #define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 454a23fd118Syl 455a23fd118Syl int scatter_mode; 456a23fd118Syl #define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 457a23fd118Syl #define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 458a23fd118Syl 459a23fd118Syl int strip_vlan_tag; 460a23fd118Syl #define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 461a23fd118Syl #define XGE_HAL_RING_STRIP_VLAN_TAG 1 462a23fd118Syl 463a23fd118Syl #define XGE_HAL_MIN_RING_NUM 1 464*7eced415Sxw #define XGE_HAL_MAX_RING_NUM_HERC 8 465*7eced415Sxw #define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 466*7eced415Sxw #define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 467a23fd118Syl xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 468a23fd118Syl 469a23fd118Syl } xge_hal_ring_config_t; 470a23fd118Syl 471a23fd118Syl /** 472a23fd118Syl * struct xge_hal_mac_config_t - MAC configuration. 4738347601bSyl * @media: Transponder type. 474a23fd118Syl * @tmac_util_period: The sampling period over which the transmit utilization 475a23fd118Syl * is calculated. 476a23fd118Syl * @rmac_util_period: The sampling period over which the receive utilization 477a23fd118Syl * is calculated. 478a23fd118Syl * @rmac_strip_pad: Determines whether padding of received frames is removed by 479a23fd118Syl * the MAC or sent to the host. 480a23fd118Syl * @rmac_bcast_en: Enable frames containing broadcast address to be 481a23fd118Syl * passed to the host. 482*7eced415Sxw * @rmac_pause_gen_en: Received pause generation enable. 4838347601bSyl * @rmac_pause_rcv_en: Receive pause enable. 484a23fd118Syl * @rmac_pause_time: The value to be inserted in outgoing pause frames. 485a23fd118Syl * Has units of pause quanta (one pause quanta = 512 bit times). 486a23fd118Syl * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 487a23fd118Syl * for queues 0 through 3. The threshold value indicates portion of the 488a23fd118Syl * individual receive buffer queue size. Thresholds have a range of 0 to 489a23fd118Syl * 255, allowing 256 possible watermarks in a queue. 490a23fd118Syl * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 491a23fd118Syl * for queues 4 through 7. The threshold value indicates portion of the 492a23fd118Syl * individual receive buffer queue size. Thresholds have a range of 0 to 493a23fd118Syl * 255, allowing 256 possible watermarks in a queue. 494a23fd118Syl * 495a23fd118Syl * MAC configuration. This includes various aspects of configuration, including: 496a23fd118Syl * - Pause frame threshold; 497a23fd118Syl * - sampling rate to calculate link utilization; 498a23fd118Syl * - enabling/disabling broadcasts. 499a23fd118Syl * 500a23fd118Syl * See Xframe User Guide for more details. 501a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 502a23fd118Syl * the xge_hal_mac_config_t{} structure. Please refer to the 503a23fd118Syl * corresponding include file. 504a23fd118Syl */ 505a23fd118Syl typedef struct xge_hal_mac_config_t { 506a23fd118Syl int media; 507a23fd118Syl #define XGE_HAL_MIN_MEDIA 0 508a23fd118Syl #define XGE_HAL_MEDIA_SR 0 509a23fd118Syl #define XGE_HAL_MEDIA_SW 1 510a23fd118Syl #define XGE_HAL_MEDIA_LR 2 511a23fd118Syl #define XGE_HAL_MEDIA_LW 3 512a23fd118Syl #define XGE_HAL_MEDIA_ER 4 513a23fd118Syl #define XGE_HAL_MEDIA_EW 5 514a23fd118Syl #define XGE_HAL_MAX_MEDIA 5 515a23fd118Syl 516a23fd118Syl int tmac_util_period; 517a23fd118Syl #define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 518a23fd118Syl #define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 519a23fd118Syl 520a23fd118Syl int rmac_util_period; 521a23fd118Syl #define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 522a23fd118Syl #define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 523a23fd118Syl 524a23fd118Syl int rmac_bcast_en; 525a23fd118Syl #define XGE_HAL_MIN_RMAC_BCAST_EN 0 526a23fd118Syl #define XGE_HAL_MAX_RMAC_BCAST_EN 1 527a23fd118Syl 528a23fd118Syl int rmac_pause_gen_en; 529a23fd118Syl #define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 530a23fd118Syl #define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 531a23fd118Syl 532a23fd118Syl int rmac_pause_rcv_en; 533a23fd118Syl #define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 534a23fd118Syl #define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 535a23fd118Syl 536a23fd118Syl int rmac_pause_time; 537a23fd118Syl #define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 538a23fd118Syl #define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 539a23fd118Syl 540a23fd118Syl int mc_pause_threshold_q0q3; 541a23fd118Syl #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 542a23fd118Syl #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 543a23fd118Syl 544a23fd118Syl int mc_pause_threshold_q4q7; 545a23fd118Syl #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 546a23fd118Syl #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 547a23fd118Syl 548a23fd118Syl } xge_hal_mac_config_t; 549a23fd118Syl 550a23fd118Syl /** 551a23fd118Syl * struct xge_hal_device_config_t - Device configuration. 552a23fd118Syl * @mtu: Current mtu size. 553a23fd118Syl * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 554a23fd118Syl * completions. Used in xge_hal_device_handle_irq(). 555a23fd118Syl * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 556a23fd118Syl * with the PCI Specification, the value of the Latency Timer 557a23fd118Syl * for this PCI bus master. 558a23fd118Syl * Specify either zero or -1 to use BIOS default. 559a23fd118Syl * @napi_weight: (TODO) 560a23fd118Syl * @max_splits_trans: Maximum number of PCI-X split transactions. 561a23fd118Syl * Specify (-1) to use BIOS default. 562a23fd118Syl * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 563a23fd118Syl * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 564a23fd118Syl * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 565a23fd118Syl * @shared_splits: The number of Outstanding Split Transactions that is 566a23fd118Syl * shared by Tx and Rx requests. The device stops issuing Tx 567a23fd118Syl * requests once the number of Outstanding Split Transactions is 568a23fd118Syl * equal to the value of Shared_Splits. 569a23fd118Syl * A value of zero indicates that the Tx and Rx share all allocated 570a23fd118Syl * Split Requests, i.e. the device can issue both types (Tx and Rx) 571a23fd118Syl * of read requests until the number of Maximum Outstanding Split 572a23fd118Syl * Transactions is reached. 573a23fd118Syl * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 574a23fd118Syl * to the host. This includes MAC stats as well as PCI stats. 575a23fd118Syl * See xge_hal_stats_hw_info_t{}. 576a23fd118Syl * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 577a23fd118Syl * @intr_mode: Line, MSI, or MSI-X interrupt. 578a23fd118Syl * @sched_timer_us: If greater than zero, specifies time interval 579a23fd118Syl * (in microseconds) for the device to generate 580a23fd118Syl * interrupt. Note that unlike tti and rti interrupts, 581a23fd118Syl * the scheduled interrupt is generated independently of 582a23fd118Syl * whether there is transmit or receive traffic, respectively. 583a23fd118Syl * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 584a23fd118Syl * 0 - generate scheduled interrupt periodically at the specified 585a23fd118Syl * @sched_timer_us interval. 586a23fd118Syl * 587a23fd118Syl * @ring: See xge_hal_ring_config_t{}. 588a23fd118Syl * @mac: See xge_hal_mac_config_t{}. 589a23fd118Syl * @tti: See xge_hal_tti_config_t{}. 590a23fd118Syl * @fifo: See xge_hal_fifo_config_t{}. 591a23fd118Syl * 592a23fd118Syl * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 593a23fd118Syl * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 594a23fd118Syl * ECC error. 595a23fd118Syl * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 596a23fd118Syl * parity error. 597a23fd118Syl * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 598a23fd118Syl * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 599a23fd118Syl * xge_hal_device_config_t{} in the driver sources. 600a23fd118Syl * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 601a23fd118Syl * Direct Match). 602a23fd118Syl * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 603a23fd118Syl * hash value in the RTH SPDM based steering. 604a23fd118Syl * @rxufca_intr_thres: (TODO) 605a23fd118Syl * @rxufca_lo_lim: (TODO) 606a23fd118Syl * @rxufca_hi_lim: (TODO) 607a23fd118Syl * @rxufca_lbolt_period: (TODO) 608a23fd118Syl * @link_valid_cnt: link-valid counting is done only at device-open time, 609a23fd118Syl * to determine with the specified certainty that the link is up. See also 610a23fd118Syl * @link_retry_cnt. 611a23fd118Syl * @link_retry_cnt: Max number of polls for link-up. Done only at device 612a23fd118Syl * open time. Reducing this value as well as the previous @link_valid_cnt, 613a23fd118Syl * speeds up device startup, which may be important if the driver 614a23fd118Syl * is compiled into OS. 615a23fd118Syl * @link_stability_period: Specify the period for which the link must be 616a23fd118Syl * stable in order for the adapter to declare "LINK UP". 617a23fd118Syl * The enumerated settings (see Xframe-II UG) are: 6188347601bSyl * 0 ........... instantaneous 6198347601bSyl * 1 ........... 500 �s 6208347601bSyl * 2 ........... 1 ms 6218347601bSyl * 3 ........... 64 ms 6228347601bSyl * 4 ........... 256 ms 6238347601bSyl * 5 ........... 512 ms 6248347601bSyl * 6 ........... 1 s 625a23fd118Syl * 7 ........... 2 s 626a23fd118Syl * @device_poll_millis: Specify the interval (in mulliseconds) between 627a23fd118Syl * successive xge_hal_device_poll() runs. 628a23fd118Syl * stable in order for the adapter to declare "LINK UP". 629*7eced415Sxw * @no_isr_events: TBD 6308347601bSyl * @lro_sg_size: TBD 6318347601bSyl * @lro_frm_len: TBD 6328347601bSyl * @bimodal_interrupts: Enable bimodal interrupts in device 633*7eced415Sxw * @bimodal_timer_lo_us: TBD 634*7eced415Sxw * @bimodal_timer_hi_us: TBD 635*7eced415Sxw * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 636*7eced415Sxw * @rts_qos_en: TBD 637*7eced415Sxw * @rts_port_en: TBD 638*7eced415Sxw * @vp_config: Configuration for virtual paths 6398347601bSyl * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 6408347601bSyl * can own at any one time. 6418347601bSyl * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 6428347601bSyl * this S-RQ can own at any one time. 6438347601bSyl * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 6448347601bSyl * WQEs before generating a message or interrupt. 6458347601bSyl * @refill_threshold_high:This field provides a hysteresis upper bound for 6468347601bSyl * automatic adapter refill operations. 6478347601bSyl * @refill_threshold_low:This field provides a hysteresis lower bound for 6488347601bSyl * automatic adapter refill operations. 6498347601bSyl * @eol_policy:This field sets the policy for handling the end of list condition. 6508347601bSyl * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. 6518347601bSyl * 2'b01 - Send UMQ message when EOL is reached. 6528347601bSyl * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message 6538347601bSyl * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for 6548347601bSyl * a non-zero block wrapper before giving up and sending a UMQ message 6558347601bSyl * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held 6568347601bSyl * by a session at any one time. 657*7eced415Sxw * @poll_or_doorbell: TBD 658a23fd118Syl * 659a23fd118Syl * Xframe configuration. 660a23fd118Syl * Contains per-device configuration parameters, including: 661a23fd118Syl * - latency timer (settable via PCI configuration space); 662a23fd118Syl * - maximum number of split transactions; 663a23fd118Syl * - maximum number of shared splits; 664a23fd118Syl * - stats sampling interval, etc. 665a23fd118Syl * 666a23fd118Syl * In addition, xge_hal_device_config_t{} includes "subordinate" 667a23fd118Syl * configurations, including: 668a23fd118Syl * - fifos and rings; 669a23fd118Syl * - MAC (see xge_hal_mac_config_t{}). 670a23fd118Syl * 671a23fd118Syl * See Xframe User Guide for more details. 672a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 673a23fd118Syl * the xge_hal_device_config_t{} structure. Please refer to the 674a23fd118Syl * corresponding include file. 675a23fd118Syl * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 676a23fd118Syl * xge_hal_mac_config_t{}. 677a23fd118Syl */ 678a23fd118Syl typedef struct xge_hal_device_config_t { 679a23fd118Syl int mtu; 680a23fd118Syl #define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 681a23fd118Syl #define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 682a23fd118Syl 683a23fd118Syl int isr_polling_cnt; 684a23fd118Syl #define XGE_HAL_MIN_ISR_POLLING_CNT 0 685a23fd118Syl #define XGE_HAL_MAX_ISR_POLLING_CNT 65536 686a23fd118Syl 687a23fd118Syl int latency_timer; 688a23fd118Syl #define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 689a23fd118Syl #define XGE_HAL_MIN_LATENCY_TIMER 8 690a23fd118Syl #define XGE_HAL_MAX_LATENCY_TIMER 255 691a23fd118Syl 692a23fd118Syl int napi_weight; 693a23fd118Syl #define XGE_HAL_DEF_NAPI_WEIGHT 64 694a23fd118Syl 695a23fd118Syl int max_splits_trans; 696a23fd118Syl #define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 697a23fd118Syl #define XGE_HAL_ONE_SPLIT_TRANSACTION 0 698a23fd118Syl #define XGE_HAL_TWO_SPLIT_TRANSACTION 1 699a23fd118Syl #define XGE_HAL_THREE_SPLIT_TRANSACTION 2 700a23fd118Syl #define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 701a23fd118Syl #define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 702a23fd118Syl #define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 703a23fd118Syl #define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 704a23fd118Syl #define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 705a23fd118Syl 706a23fd118Syl int mmrb_count; 707a23fd118Syl #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 708a23fd118Syl #define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 709a23fd118Syl #define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 710a23fd118Syl 711a23fd118Syl int shared_splits; 712a23fd118Syl #define XGE_HAL_MIN_SHARED_SPLITS 0 713a23fd118Syl #define XGE_HAL_MAX_SHARED_SPLITS 31 714a23fd118Syl 715a23fd118Syl int stats_refresh_time_sec; 716a23fd118Syl #define XGE_HAL_STATS_REFRESH_DISABLE 0 717a23fd118Syl #define XGE_HAL_MIN_STATS_REFRESH_TIME 1 718a23fd118Syl #define XGE_HAL_MAX_STATS_REFRESH_TIME 300 719a23fd118Syl 720a23fd118Syl int pci_freq_mherz; 721a23fd118Syl #define XGE_HAL_PCI_FREQ_MHERZ_33 33 722a23fd118Syl #define XGE_HAL_PCI_FREQ_MHERZ_66 66 723a23fd118Syl #define XGE_HAL_PCI_FREQ_MHERZ_100 100 724a23fd118Syl #define XGE_HAL_PCI_FREQ_MHERZ_133 133 725a23fd118Syl #define XGE_HAL_PCI_FREQ_MHERZ_266 266 726a23fd118Syl 727a23fd118Syl int intr_mode; 728a23fd118Syl #define XGE_HAL_INTR_MODE_IRQLINE 0 729a23fd118Syl #define XGE_HAL_INTR_MODE_MSI 1 730a23fd118Syl #define XGE_HAL_INTR_MODE_MSIX 2 731a23fd118Syl 732a23fd118Syl int sched_timer_us; 733a23fd118Syl #define XGE_HAL_SCHED_TIMER_DISABLED 0 734a23fd118Syl #define XGE_HAL_SCHED_TIMER_MIN 0 735a23fd118Syl #define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 736a23fd118Syl 737a23fd118Syl int sched_timer_one_shot; 738a23fd118Syl #define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 739a23fd118Syl #define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 740a23fd118Syl 741a23fd118Syl xge_hal_ring_config_t ring; 742a23fd118Syl xge_hal_mac_config_t mac; 743a23fd118Syl xge_hal_fifo_config_t fifo; 744a23fd118Syl 745a23fd118Syl int dump_on_serr; 746a23fd118Syl #define XGE_HAL_DUMP_ON_SERR_DISABLE 0 747a23fd118Syl #define XGE_HAL_DUMP_ON_SERR_ENABLE 1 748a23fd118Syl 749a23fd118Syl int dump_on_eccerr; 750a23fd118Syl #define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 751a23fd118Syl #define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 752a23fd118Syl 753a23fd118Syl int dump_on_parityerr; 754a23fd118Syl #define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 755a23fd118Syl #define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 756a23fd118Syl 757a23fd118Syl int rth_en; 758a23fd118Syl #define XGE_HAL_RTH_DISABLE 0 759a23fd118Syl #define XGE_HAL_RTH_ENABLE 1 760a23fd118Syl 761a23fd118Syl int rth_bucket_size; 762a23fd118Syl #define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 763a23fd118Syl #define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 764a23fd118Syl 765a23fd118Syl int rth_spdm_en; 766a23fd118Syl #define XGE_HAL_RTH_SPDM_DISABLE 0 767a23fd118Syl #define XGE_HAL_RTH_SPDM_ENABLE 1 768a23fd118Syl 769a23fd118Syl int rth_spdm_use_l4; 770a23fd118Syl #define XGE_HAL_RTH_SPDM_USE_L4 1 771a23fd118Syl 772a23fd118Syl int rxufca_intr_thres; 773a23fd118Syl #define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 774a23fd118Syl #define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 775a23fd118Syl 776a23fd118Syl int rxufca_lo_lim; 777a23fd118Syl #define XGE_HAL_RXUFCA_LO_LIM_MIN 1 778a23fd118Syl #define XGE_HAL_RXUFCA_LO_LIM_MAX 16 779a23fd118Syl 780a23fd118Syl int rxufca_hi_lim; 781a23fd118Syl #define XGE_HAL_RXUFCA_HI_LIM_MIN 1 782a23fd118Syl #define XGE_HAL_RXUFCA_HI_LIM_MAX 256 783a23fd118Syl 784a23fd118Syl int rxufca_lbolt_period; 785a23fd118Syl #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 786a23fd118Syl #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 787a23fd118Syl 788a23fd118Syl int link_valid_cnt; 789a23fd118Syl #define XGE_HAL_LINK_VALID_CNT_MIN 0 790a23fd118Syl #define XGE_HAL_LINK_VALID_CNT_MAX 127 791a23fd118Syl 792a23fd118Syl int link_retry_cnt; 793a23fd118Syl #define XGE_HAL_LINK_RETRY_CNT_MIN 0 794a23fd118Syl #define XGE_HAL_LINK_RETRY_CNT_MAX 127 795a23fd118Syl 796a23fd118Syl int link_stability_period; 797a23fd118Syl #define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 798a23fd118Syl #define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 799a23fd118Syl #define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 800a23fd118Syl 801a23fd118Syl int device_poll_millis; 802a23fd118Syl #define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 803a23fd118Syl #define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 804a23fd118Syl #define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 805a23fd118Syl 806a23fd118Syl int no_isr_events; 807a23fd118Syl #define XGE_HAL_NO_ISR_EVENTS_MIN 0 808a23fd118Syl #define XGE_HAL_NO_ISR_EVENTS_MAX 1 809a23fd118Syl 8108347601bSyl int lro_sg_size; 8118347601bSyl #define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 8128347601bSyl #define XGE_HAL_LRO_MIN_SG_SIZE 1 8138347601bSyl #define XGE_HAL_LRO_MAX_SG_SIZE 64 8148347601bSyl 8158347601bSyl int lro_frm_len; 8168347601bSyl #define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 8178347601bSyl #define XGE_HAL_LRO_MIN_FRM_LEN 4096 8188347601bSyl #define XGE_HAL_LRO_MAX_FRM_LEN 65536 8198347601bSyl 8208347601bSyl int bimodal_interrupts; 8218347601bSyl #define XGE_HAL_BIMODAL_INTR_MIN -1 8228347601bSyl #define XGE_HAL_BIMODAL_INTR_MAX 1 8238347601bSyl 8248347601bSyl int bimodal_timer_lo_us; 8258347601bSyl #define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 8268347601bSyl #define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 8278347601bSyl 8288347601bSyl int bimodal_timer_hi_us; 8298347601bSyl #define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 8308347601bSyl #define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 8318347601bSyl 832*7eced415Sxw int rts_mac_en; 833*7eced415Sxw #define XGE_HAL_RTS_MAC_DISABLE 0 834*7eced415Sxw #define XGE_HAL_RTS_MAC_ENABLE 1 8358347601bSyl 836*7eced415Sxw int rts_qos_en; 837*7eced415Sxw #define XGE_HAL_RTS_QOS_DISABLE 0 838*7eced415Sxw #define XGE_HAL_RTS_QOS_ENABLE 1 8398347601bSyl 840*7eced415Sxw int rts_port_en; 841*7eced415Sxw #define XGE_HAL_RTS_PORT_DISABLE 0 842*7eced415Sxw #define XGE_HAL_RTS_PORT_ENABLE 1 8438347601bSyl 844a23fd118Syl } xge_hal_device_config_t; 845a23fd118Syl 846a23fd118Syl /** 847a23fd118Syl * struct xge_hal_driver_config_t - HAL (layer) configuration. 848a23fd118Syl * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 849a23fd118Syl * periodically poll HAL, i.e, invoke 850a23fd118Syl * xge_hal_device_poll(). 851a23fd118Syl * Note that HAL does not maintain its own 852a23fd118Syl * polling context. HAL relies on ULD to 853a23fd118Syl * provide one. 854a23fd118Syl * @queue_size_initial: Initial size of the HAL protected event queue. 855a23fd118Syl * The queue is shared by HAL and upper-layer drivers. 856a23fd118Syl * The queue is used to exchange and process slow-path 857a23fd118Syl * events. See xge_hal_event_e. 858a23fd118Syl * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 859a23fd118Syl * the queue may grow at run-time up to @queue_max_size. 860a23fd118Syl * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 861a23fd118Syl * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 862a23fd118Syl * HAL devices.) 863a23fd118Syl * Currently this structure contains just a few basic values. 864a23fd118Syl * Note: Valid (min, max) range for each attribute is specified in the body of 865a23fd118Syl * the structure. Please refer to the corresponding header file. 866a23fd118Syl * See also: xge_hal_device_poll() 867a23fd118Syl */ 868a23fd118Syl typedef struct xge_hal_driver_config_t { 869a23fd118Syl int queue_size_initial; 870a23fd118Syl #define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 871a23fd118Syl #define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 872a23fd118Syl 873a23fd118Syl int queue_size_max; 874a23fd118Syl #define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 875a23fd118Syl #define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 876a23fd118Syl 877a23fd118Syl #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 878a23fd118Syl int tracebuf_size; 879a23fd118Syl #define XGE_HAL_MIN_CIRCULAR_ARR 4096 880*7eced415Sxw #define XGE_HAL_MAX_CIRCULAR_ARR 1048576 881*7eced415Sxw #define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE 882*7eced415Sxw 883*7eced415Sxw int tracebuf_timestamp_en; 884*7eced415Sxw #define XGE_HAL_MIN_TIMESTAMP_EN 0 885*7eced415Sxw #define XGE_HAL_MAX_TIMESTAMP_EN 1 886a23fd118Syl #endif 887a23fd118Syl 888a23fd118Syl } xge_hal_driver_config_t; 889a23fd118Syl 890a23fd118Syl 891a23fd118Syl /* ========================== PRIVATE API ================================= */ 892a23fd118Syl 893a23fd118Syl xge_hal_status_e 894a23fd118Syl __hal_device_config_check_common (xge_hal_device_config_t *new_config); 895a23fd118Syl 896a23fd118Syl xge_hal_status_e 897a23fd118Syl __hal_device_config_check_xena (xge_hal_device_config_t *new_config); 898a23fd118Syl 899a23fd118Syl xge_hal_status_e 900a23fd118Syl __hal_device_config_check_herc (xge_hal_device_config_t *new_config); 901a23fd118Syl 902a23fd118Syl xge_hal_status_e 903a23fd118Syl __hal_driver_config_check (xge_hal_driver_config_t *new_config); 904a23fd118Syl 9058347601bSyl __EXTERN_END_DECLS 9068347601bSyl 907a23fd118Syl #endif /* XGE_HAL_CONFIG_H */ 908