1*a23fd118Syl /* 2*a23fd118Syl * CDDL HEADER START 3*a23fd118Syl * 4*a23fd118Syl * The contents of this file are subject to the terms of the 5*a23fd118Syl * Common Development and Distribution License (the "License"). 6*a23fd118Syl * You may not use this file except in compliance with the License. 7*a23fd118Syl * 8*a23fd118Syl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*a23fd118Syl * or http://www.opensolaris.org/os/licensing. 10*a23fd118Syl * See the License for the specific language governing permissions 11*a23fd118Syl * and limitations under the License. 12*a23fd118Syl * 13*a23fd118Syl * When distributing Covered Code, include this CDDL HEADER in each 14*a23fd118Syl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*a23fd118Syl * If applicable, add the following below this CDDL HEADER, with the 16*a23fd118Syl * fields enclosed by brackets "[]" replaced with your own identifying 17*a23fd118Syl * information: Portions Copyright [yyyy] [name of copyright owner] 18*a23fd118Syl * 19*a23fd118Syl * CDDL HEADER END 20*a23fd118Syl */ 21*a23fd118Syl 22*a23fd118Syl /* 23*a23fd118Syl * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24*a23fd118Syl * Use is subject to license terms. 25*a23fd118Syl */ 26*a23fd118Syl 27*a23fd118Syl /* 28*a23fd118Syl * Copyright (c) 2002-2005 Neterion, Inc. 29*a23fd118Syl * All right Reserved. 30*a23fd118Syl * 31*a23fd118Syl * FileName : xge_osdep.h 32*a23fd118Syl * 33*a23fd118Syl * Description: OSPAL - Solaris 34*a23fd118Syl * 35*a23fd118Syl */ 36*a23fd118Syl 37*a23fd118Syl #ifndef _SYS_XGE_OSDEP_H 38*a23fd118Syl #define _SYS_XGE_OSDEP_H 39*a23fd118Syl 40*a23fd118Syl #pragma ident "%Z%%M% %I% %E% SMI" 41*a23fd118Syl 42*a23fd118Syl #include <sys/ddi.h> 43*a23fd118Syl #include <sys/sunddi.h> 44*a23fd118Syl #include <sys/varargs.h> 45*a23fd118Syl #include <sys/atomic.h> 46*a23fd118Syl #include <sys/policy.h> 47*a23fd118Syl #include <sys/int_fmtio.h> 48*a23fd118Syl #include <sys/thread.h> 49*a23fd118Syl #include <sys/cpuvar.h> 50*a23fd118Syl 51*a23fd118Syl #include <inet/common.h> 52*a23fd118Syl #include <inet/ip.h> 53*a23fd118Syl #include <inet/mi.h> 54*a23fd118Syl #include <inet/nd.h> 55*a23fd118Syl 56*a23fd118Syl #ifdef __cplusplus 57*a23fd118Syl extern "C" { 58*a23fd118Syl #endif 59*a23fd118Syl 60*a23fd118Syl /* ------------------------- includes and defines ------------------------- */ 61*a23fd118Syl 62*a23fd118Syl #define XGE_HAL_TX_MULTI_POST_IRQ 1 63*a23fd118Syl #define XGE_HAL_TX_MULTI_RESERVE_IRQ 1 64*a23fd118Syl #define XGE_HAL_TX_MULTI_FREE_IRQ 1 65*a23fd118Syl #define XGE_HAL_RX_MULTI_FREE 1 66*a23fd118Syl #define XGE_HAL_DMA_DTR_CONSISTENT 1 67*a23fd118Syl #define XGE_HAL_DMA_STATS_STREAMING 1 68*a23fd118Syl 69*a23fd118Syl #if defined(__sparc) 70*a23fd118Syl #define XGE_OS_DMA_REQUIRES_SYNC 1 71*a23fd118Syl #define XGELL_TX_NOMAP_COPY 1 72*a23fd118Syl #define XGE_HAL_ALIGN_XMIT 1 73*a23fd118Syl #endif 74*a23fd118Syl 75*a23fd118Syl #ifdef _BIG_ENDIAN 76*a23fd118Syl #define XGE_OS_HOST_BIG_ENDIAN 1 77*a23fd118Syl #else 78*a23fd118Syl #define XGE_OS_HOST_LITTLE_ENDIAN 1 79*a23fd118Syl #endif 80*a23fd118Syl 81*a23fd118Syl #if defined(_LP64) 82*a23fd118Syl #define XGE_OS_PLATFORM_64BIT 1 83*a23fd118Syl #else 84*a23fd118Syl #define XGE_OS_PLATFORM_32BIT 1 85*a23fd118Syl #endif 86*a23fd118Syl 87*a23fd118Syl #define XGE_OS_HAS_SNPRINTF 1 88*a23fd118Syl 89*a23fd118Syl /* ---------------------- fixed size primitive types ----------------------- */ 90*a23fd118Syl 91*a23fd118Syl #define u8 uint8_t 92*a23fd118Syl #define u16 uint16_t 93*a23fd118Syl #define u32 uint32_t 94*a23fd118Syl #define u64 uint64_t 95*a23fd118Syl typedef u64 dma_addr_t; 96*a23fd118Syl #define ulong_t ulong_t 97*a23fd118Syl #define ptrdiff_t ptrdiff_t 98*a23fd118Syl typedef kmutex_t spinlock_t; 99*a23fd118Syl typedef dev_info_t *pci_dev_h; 100*a23fd118Syl typedef ddi_acc_handle_t pci_reg_h; 101*a23fd118Syl typedef ddi_acc_handle_t pci_cfg_h; 102*a23fd118Syl typedef ddi_iblock_cookie_t pci_irq_h; 103*a23fd118Syl typedef ddi_dma_handle_t pci_dma_h; 104*a23fd118Syl typedef ddi_acc_handle_t pci_dma_acc_h; 105*a23fd118Syl 106*a23fd118Syl /* -------------------------- "libc" functionality ------------------------- */ 107*a23fd118Syl 108*a23fd118Syl #define xge_os_strcpy (void) strcpy 109*a23fd118Syl #define xge_os_strlen strlen 110*a23fd118Syl #define xge_os_snprintf snprintf 111*a23fd118Syl #define xge_os_memzero(addr, size) bzero(addr, size) 112*a23fd118Syl #define xge_os_memcpy(dst, src, size) bcopy(src, dst, size) 113*a23fd118Syl #define xge_os_memcmp(src1, src2, size) bcmp(src1, src2, size) 114*a23fd118Syl 115*a23fd118Syl #ifdef __GNUC__ 116*a23fd118Syl #define xge_os_printf(fmt...) cmn_err(CE_CONT, fmt) 117*a23fd118Syl #define xge_os_sprintf(buf, fmt...) strlen(sprintf(buf, fmt)) 118*a23fd118Syl #else 119*a23fd118Syl #define xge_os_vaprintf(fmt) { \ 120*a23fd118Syl va_list va; \ 121*a23fd118Syl va_start(va, fmt); \ 122*a23fd118Syl vcmn_err(CE_CONT, fmt, va); \ 123*a23fd118Syl va_end(va); \ 124*a23fd118Syl } 125*a23fd118Syl 126*a23fd118Syl static inline void xge_os_printf(char *fmt, ...) { 127*a23fd118Syl xge_os_vaprintf(fmt); 128*a23fd118Syl } 129*a23fd118Syl 130*a23fd118Syl #define xge_os_vasprintf(buf, fmt) { \ 131*a23fd118Syl va_list va; \ 132*a23fd118Syl va_start(va, fmt); \ 133*a23fd118Syl (void) vsprintf(buf, fmt, va); \ 134*a23fd118Syl va_end(va); \ 135*a23fd118Syl } 136*a23fd118Syl 137*a23fd118Syl static inline int xge_os_sprintf(char *buf, char *fmt, ...) { 138*a23fd118Syl xge_os_vasprintf(buf, fmt); 139*a23fd118Syl return (strlen(buf)); 140*a23fd118Syl } 141*a23fd118Syl #endif 142*a23fd118Syl 143*a23fd118Syl #define xge_os_timestamp(buf) { \ 144*a23fd118Syl todinfo_t todinfo = utc_to_tod(ddi_get_time()); \ 145*a23fd118Syl (void) xge_os_sprintf(buf, "%2d/%2d/%2d.%2d:%2d:%2d: ", \ 146*a23fd118Syl todinfo.tod_day, todinfo.tod_month, \ 147*a23fd118Syl (1970 + todinfo.tod_year - 70), \ 148*a23fd118Syl todinfo.tod_hour, todinfo.tod_min, todinfo.tod_sec); \ 149*a23fd118Syl } 150*a23fd118Syl 151*a23fd118Syl #define xge_os_println xge_os_printf 152*a23fd118Syl 153*a23fd118Syl /* -------------------- synchronization primitives ------------------------- */ 154*a23fd118Syl 155*a23fd118Syl #define xge_os_spin_lock_init(lockp, ctxh) \ 156*a23fd118Syl mutex_init(lockp, NULL, MUTEX_DRIVER, NULL) 157*a23fd118Syl #define xge_os_spin_lock_init_irq(lockp, irqh) \ 158*a23fd118Syl mutex_init(lockp, NULL, MUTEX_DRIVER, irqh) 159*a23fd118Syl #define xge_os_spin_lock_destroy(lockp, cthx) \ 160*a23fd118Syl (cthx = cthx, mutex_destroy(lockp)) 161*a23fd118Syl #define xge_os_spin_lock_destroy_irq(lockp, cthx) \ 162*a23fd118Syl (cthx = cthx, mutex_destroy(lockp)) 163*a23fd118Syl #define xge_os_spin_lock(lockp) mutex_enter(lockp) 164*a23fd118Syl #define xge_os_spin_unlock(lockp) mutex_exit(lockp) 165*a23fd118Syl #define xge_os_spin_lock_irq(lockp, flags) (flags = flags, mutex_enter(lockp)) 166*a23fd118Syl #define xge_os_spin_unlock_irq(lockp, flags) mutex_exit(lockp) 167*a23fd118Syl 168*a23fd118Syl /* x86 arch will never re-order writes, Sparc can */ 169*a23fd118Syl #define xge_os_wmb() membar_producer() 170*a23fd118Syl 171*a23fd118Syl #define xge_os_udelay(us) drv_usecwait(us) 172*a23fd118Syl #define xge_os_mdelay(ms) drv_usecwait(ms * 1000) 173*a23fd118Syl 174*a23fd118Syl #define xge_os_cmpxchg(targetp, cmp, newval) \ 175*a23fd118Syl sizeof (*(targetp)) == 4 ? \ 176*a23fd118Syl cas32((uint32_t *)targetp, cmp, newval) : \ 177*a23fd118Syl cas64((uint64_t *)targetp, cmp, newval) 178*a23fd118Syl 179*a23fd118Syl /* ------------------------- misc primitives ------------------------------- */ 180*a23fd118Syl 181*a23fd118Syl #define xge_os_unlikely(x) (x) 182*a23fd118Syl #define xge_os_prefetch(a) (a = a) 183*a23fd118Syl #define xge_os_prefetchw 184*a23fd118Syl #ifdef __GNUC__ 185*a23fd118Syl #define xge_os_bug(fmt...) cmn_err(CE_PANIC, fmt) 186*a23fd118Syl #else 187*a23fd118Syl static inline void xge_os_bug(char *fmt, ...) { 188*a23fd118Syl va_list ap; 189*a23fd118Syl 190*a23fd118Syl va_start(ap, fmt); 191*a23fd118Syl vcmn_err(CE_PANIC, fmt, ap); 192*a23fd118Syl va_end(ap); 193*a23fd118Syl } 194*a23fd118Syl #endif 195*a23fd118Syl 196*a23fd118Syl /* -------------------------- compiler stuffs ------------------------------ */ 197*a23fd118Syl 198*a23fd118Syl #if defined(__i386) 199*a23fd118Syl #define __xge_os_cacheline_size 64 /* L1-cache line size: x86_64 */ 200*a23fd118Syl #else 201*a23fd118Syl #define __xge_os_cacheline_size 64 /* L1-cache line size: sparcv9 */ 202*a23fd118Syl #endif 203*a23fd118Syl 204*a23fd118Syl #ifdef __GNUC__ 205*a23fd118Syl #define __xge_os_attr_cacheline_aligned \ 206*a23fd118Syl __attribute__((__aligned__(__xge_os_cacheline_size))) 207*a23fd118Syl #else 208*a23fd118Syl #define __xge_os_attr_cacheline_aligned 209*a23fd118Syl #endif 210*a23fd118Syl 211*a23fd118Syl /* ---------------------- memory primitives -------------------------------- */ 212*a23fd118Syl 213*a23fd118Syl static inline void *__xge_os_malloc(pci_dev_h pdev, unsigned long size, 214*a23fd118Syl char *file, int line) 215*a23fd118Syl { 216*a23fd118Syl void *vaddr = kmem_alloc(size, KM_SLEEP); 217*a23fd118Syl 218*a23fd118Syl XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line); 219*a23fd118Syl return (vaddr); 220*a23fd118Syl } 221*a23fd118Syl 222*a23fd118Syl static inline void xge_os_free(pci_dev_h pdev, const void *vaddr, 223*a23fd118Syl unsigned long size) 224*a23fd118Syl { 225*a23fd118Syl XGE_OS_MEMORY_CHECK_FREE(vaddr, size); 226*a23fd118Syl kmem_free((void*)vaddr, size); 227*a23fd118Syl } 228*a23fd118Syl 229*a23fd118Syl #define xge_os_malloc(pdev, size) \ 230*a23fd118Syl __xge_os_malloc(pdev, size, __FILE__, __LINE__) 231*a23fd118Syl 232*a23fd118Syl static inline void *__xge_os_dma_malloc(pci_dev_h pdev, unsigned long size, 233*a23fd118Syl int dma_flags, pci_dma_h *p_dmah, pci_dma_acc_h *p_dma_acch, char *file, 234*a23fd118Syl int line) 235*a23fd118Syl { 236*a23fd118Syl void *vaddr; 237*a23fd118Syl int ret; 238*a23fd118Syl size_t real_size; 239*a23fd118Syl extern ddi_device_acc_attr_t *p_xge_dev_attr; 240*a23fd118Syl extern struct ddi_dma_attr *p_hal_dma_attr; 241*a23fd118Syl extern struct ddi_dma_attr *p_hal_dma_attr_aligned; 242*a23fd118Syl 243*a23fd118Syl ret = ddi_dma_alloc_handle(pdev, 244*a23fd118Syl (dma_flags & XGE_OS_DMA_CACHELINE_ALIGNED ? 245*a23fd118Syl p_hal_dma_attr_aligned : p_hal_dma_attr), 246*a23fd118Syl DDI_DMA_DONTWAIT, 0, p_dmah); 247*a23fd118Syl if (ret != DDI_SUCCESS) { 248*a23fd118Syl return (NULL); 249*a23fd118Syl } 250*a23fd118Syl 251*a23fd118Syl ret = ddi_dma_mem_alloc(*p_dmah, size, p_xge_dev_attr, 252*a23fd118Syl (dma_flags & XGE_OS_DMA_CONSISTENT ? 253*a23fd118Syl DDI_DMA_CONSISTENT : DDI_DMA_STREAMING), 254*a23fd118Syl DDI_DMA_DONTWAIT, 0, (caddr_t *)&vaddr, &real_size, p_dma_acch); 255*a23fd118Syl if (ret != DDI_SUCCESS) { 256*a23fd118Syl ddi_dma_free_handle(p_dmah); 257*a23fd118Syl return (NULL); 258*a23fd118Syl } 259*a23fd118Syl 260*a23fd118Syl if (size > real_size) { 261*a23fd118Syl ddi_dma_mem_free(p_dma_acch); 262*a23fd118Syl ddi_dma_free_handle(p_dmah); 263*a23fd118Syl return (NULL); 264*a23fd118Syl } 265*a23fd118Syl 266*a23fd118Syl XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line); 267*a23fd118Syl 268*a23fd118Syl return (vaddr); 269*a23fd118Syl } 270*a23fd118Syl 271*a23fd118Syl #define xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch) \ 272*a23fd118Syl __xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch, \ 273*a23fd118Syl __FILE__, __LINE__) 274*a23fd118Syl 275*a23fd118Syl static inline void xge_os_dma_free(pci_dev_h pdev, const void *vaddr, int size, 276*a23fd118Syl pci_dma_acc_h *p_dma_acch, pci_dma_h *p_dmah) 277*a23fd118Syl { 278*a23fd118Syl XGE_OS_MEMORY_CHECK_FREE(vaddr, 0); 279*a23fd118Syl ddi_dma_mem_free(p_dma_acch); 280*a23fd118Syl ddi_dma_free_handle(p_dmah); 281*a23fd118Syl } 282*a23fd118Syl 283*a23fd118Syl 284*a23fd118Syl /* --------------------------- pci primitives ------------------------------ */ 285*a23fd118Syl 286*a23fd118Syl #define xge_os_pci_read8(pdev, cfgh, where, val) \ 287*a23fd118Syl (*(val) = pci_config_get8(cfgh, where)) 288*a23fd118Syl 289*a23fd118Syl #define xge_os_pci_write8(pdev, cfgh, where, val) \ 290*a23fd118Syl pci_config_put8(cfgh, where, val) 291*a23fd118Syl 292*a23fd118Syl #define xge_os_pci_read16(pdev, cfgh, where, val) \ 293*a23fd118Syl (*(val) = pci_config_get16(cfgh, where)) 294*a23fd118Syl 295*a23fd118Syl #define xge_os_pci_write16(pdev, cfgh, where, val) \ 296*a23fd118Syl pci_config_put16(cfgh, where, val) 297*a23fd118Syl 298*a23fd118Syl #define xge_os_pci_read32(pdev, cfgh, where, val) \ 299*a23fd118Syl (*(val) = pci_config_get32(cfgh, where)) 300*a23fd118Syl 301*a23fd118Syl #define xge_os_pci_write32(pdev, cfgh, where, val) \ 302*a23fd118Syl pci_config_put32(cfgh, where, val) 303*a23fd118Syl 304*a23fd118Syl /* --------------------------- io primitives ------------------------------- */ 305*a23fd118Syl 306*a23fd118Syl #define xge_os_pio_mem_read8(pdev, regh, addr) \ 307*a23fd118Syl (ddi_get8(regh, (uint8_t *)(addr))) 308*a23fd118Syl 309*a23fd118Syl #define xge_os_pio_mem_write8(pdev, regh, val, addr) \ 310*a23fd118Syl (ddi_put8(regh, (uint8_t *)(addr), val)) 311*a23fd118Syl 312*a23fd118Syl #define xge_os_pio_mem_read16(pdev, regh, addr) \ 313*a23fd118Syl (ddi_get16(regh, (uint16_t *)(addr))) 314*a23fd118Syl 315*a23fd118Syl #define xge_os_pio_mem_write16(pdev, regh, val, addr) \ 316*a23fd118Syl (ddi_put16(regh, (uint16_t *)(addr), val)) 317*a23fd118Syl 318*a23fd118Syl #define xge_os_pio_mem_read32(pdev, regh, addr) \ 319*a23fd118Syl (ddi_get32(regh, (uint32_t *)(addr))) 320*a23fd118Syl 321*a23fd118Syl #define xge_os_pio_mem_write32(pdev, regh, val, addr) \ 322*a23fd118Syl (ddi_put32(regh, (uint32_t *)(addr), val)) 323*a23fd118Syl 324*a23fd118Syl #define xge_os_pio_mem_read64(pdev, regh, addr) \ 325*a23fd118Syl (ddi_get64(regh, (uint64_t *)(addr))) 326*a23fd118Syl 327*a23fd118Syl #define xge_os_pio_mem_write64(pdev, regh, val, addr) \ 328*a23fd118Syl (ddi_put64(regh, (uint64_t *)(addr), val)) 329*a23fd118Syl 330*a23fd118Syl #define xge_os_flush_bridge xge_os_pio_mem_read64 331*a23fd118Syl 332*a23fd118Syl /* --------------------------- dma primitives ----------------------------- */ 333*a23fd118Syl 334*a23fd118Syl #define XGE_OS_DMA_DIR_TODEVICE DDI_DMA_SYNC_FORDEV 335*a23fd118Syl #define XGE_OS_DMA_DIR_FROMDEVICE DDI_DMA_SYNC_FORKERNEL 336*a23fd118Syl #define XGE_OS_DMA_DIR_BIDIRECTIONAL -1 337*a23fd118Syl #if defined(__x86) 338*a23fd118Syl #define XGE_OS_DMA_USES_IOMMU 0 339*a23fd118Syl #else 340*a23fd118Syl #define XGE_OS_DMA_USES_IOMMU 1 341*a23fd118Syl #endif 342*a23fd118Syl 343*a23fd118Syl #define XGE_OS_INVALID_DMA_ADDR ((dma_addr_t)0) 344*a23fd118Syl 345*a23fd118Syl static inline dma_addr_t xge_os_dma_map(pci_dev_h pdev, pci_dma_h dmah, 346*a23fd118Syl void *vaddr, size_t size, int dir, int dma_flags) { 347*a23fd118Syl int ret; 348*a23fd118Syl uint_t flags; 349*a23fd118Syl uint_t ncookies; 350*a23fd118Syl ddi_dma_cookie_t dma_cookie; 351*a23fd118Syl 352*a23fd118Syl switch (dir) { 353*a23fd118Syl case XGE_OS_DMA_DIR_TODEVICE: 354*a23fd118Syl flags = DDI_DMA_WRITE; 355*a23fd118Syl break; 356*a23fd118Syl case XGE_OS_DMA_DIR_FROMDEVICE: 357*a23fd118Syl flags = DDI_DMA_READ; 358*a23fd118Syl break; 359*a23fd118Syl case XGE_OS_DMA_DIR_BIDIRECTIONAL: 360*a23fd118Syl flags = DDI_DMA_RDWR; 361*a23fd118Syl break; 362*a23fd118Syl default: 363*a23fd118Syl return (0); 364*a23fd118Syl } 365*a23fd118Syl 366*a23fd118Syl flags |= (dma_flags & XGE_OS_DMA_CONSISTENT) ? 367*a23fd118Syl DDI_DMA_CONSISTENT : DDI_DMA_STREAMING; 368*a23fd118Syl 369*a23fd118Syl ret = ddi_dma_addr_bind_handle(dmah, NULL, vaddr, size, flags, 370*a23fd118Syl DDI_DMA_SLEEP, 0, &dma_cookie, &ncookies); 371*a23fd118Syl if (ret != DDI_SUCCESS) { 372*a23fd118Syl return (0); 373*a23fd118Syl } 374*a23fd118Syl 375*a23fd118Syl if (ncookies != 1 || dma_cookie.dmac_size < size) { 376*a23fd118Syl (void) ddi_dma_unbind_handle(dmah); 377*a23fd118Syl return (0); 378*a23fd118Syl } 379*a23fd118Syl 380*a23fd118Syl return (dma_cookie.dmac_laddress); 381*a23fd118Syl } 382*a23fd118Syl 383*a23fd118Syl static inline void xge_os_dma_unmap(pci_dev_h pdev, pci_dma_h dmah, 384*a23fd118Syl dma_addr_t dma_addr, size_t size, int dir) 385*a23fd118Syl { 386*a23fd118Syl (void) ddi_dma_unbind_handle(dmah); 387*a23fd118Syl } 388*a23fd118Syl 389*a23fd118Syl static inline void xge_os_dma_sync(pci_dev_h pdev, pci_dma_h dmah, 390*a23fd118Syl dma_addr_t dma_addr, u64 dma_offset, size_t length, int dir) 391*a23fd118Syl { 392*a23fd118Syl (void) ddi_dma_sync(dmah, dma_offset, length, dir); 393*a23fd118Syl } 394*a23fd118Syl 395*a23fd118Syl #ifdef __cplusplus 396*a23fd118Syl } 397*a23fd118Syl #endif 398*a23fd118Syl 399*a23fd118Syl #endif /* _SYS_XGE_OSDEP_H */ 400