1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef _VR_H
28#define	_VR_H
29
30#ifdef __cplusplus
31	extern "C" {
32#endif
33
34/*
35 * Number of descriptor entries for each ring. The no. of descriptors is bound
36 * to 4K per ring (256 entries a 16 bytes).
37 */
38#define	VR_TX_N_DESC		128
39#define	VR_RX_N_DESC		256
40
41/*
42 * The number of TX interrupts to "schedule" on the ring.
43 */
44#define	VR_TX_INTRS_RING	3
45
46/*
47 * The the periodic check interval of 2 seconds, in nano seconds
48 */
49#define	VR_CHECK_INTERVAL	(2000 * 1000 * 1000)
50
51/*
52 * The number of TX checks that must pass without progress before we decide
53 * to reset the adapter.
54 */
55#define	VR_MAXTXCHECKS		12
56
57/*
58 * All possible interrupts with the unwanted commented.
59 */
60#define	VR_ICR0_CFG	(VR_ICR0_RX_DONE	| \
61			    VR_ICR0_TX_DONE	| \
62			    VR_ICR0_RX_ERR	| \
63			    VR_ICR0_TX_ERR	| \
64			    VR_ICR0_TX_BUF_UFLOW| \
65			    VR_ICR0_RX_LINKERR	| \
66			    VR_ICR0_BUSERR	| \
67			    /* VR_ICR0_STATSMAX	| */ \
68			    /* VR_ICR0_RX_EARLY	| */ \
69			    VR_ICR0_TX_FIFO_UFLOW	| \
70			    VR_ICR0_RX_FIFO_OFLOW	| \
71			    VR_ICR0_RX_DROPPED	| \
72			    VR_ICR0_RX_NOBUF  	| \
73			    VR_ICR0_TX_ABORT	| \
74			    VR_ICR0_LINKSTATUS	| \
75			    VR_ICR0_GENERAL)
76
77#define	VR_ICR1_CFG	(/* VR_ICR1_TIMER0	| */ \
78			    /* VR_ICR1_TIMER1	| */ \
79			    /* VR_ICR1_PHYEVENT	| */ \
80			    /* VR_ICR1_TDERR	| */ \
81			    /* VR_ICR1_SSRCI	| */ \
82			    /* VR_ICR1_UINTR_SET| */ \
83			    /* VR_ICR1_UINTR_CLR| */ \
84			    /* VR_ICR1_PWEI */)
85
86/*
87 * Our definitions of RX and TX errors.
88 */
89#define	VR_ISR_TX_ERR_BITS	(VR_ICR0_TX_ERR | \
90					VR_ICR0_TX_BUF_UFLOW | \
91					VR_ICR0_TX_FIFO_UFLOW | \
92					VR_ICR0_TX_ABORT)
93
94#define	VR_ISR_RX_ERR_BITS	(VR_ICR0_RX_ERR | \
95					VR_ICR0_RX_LINKERR | \
96					VR_ICR0_RX_FIFO_OFLOW | \
97					VR_ICR0_RX_DROPPED | \
98					VR_ICR0_RX_NOBUF)
99
100#define	VR_ISR_SYS_ERR_BITS	(VR_ICR0_BUSERR)
101
102#define	VR_ISR_ERR_BITS		(VR_ISR_TX_ERR_BITS | \
103					VR_ISR_RX_ERR_BITS | \
104					VR_ISR_SYS_ERR_BITS)
105#define	VR_TX_MAX_INTR_DISTANCE \
106			(VR_TX_N_DESC / VR_TX_INTRS_RING)
107
108
109#define	MODULENAME		"vr"	/* Our name */
110#define	VR_SLOPSZ		2
111#define	VR_MAX_PKTSZ		(ETHERMAX + ETHERFCSL + VLAN_TAGSZ + VR_SLOPSZ)
112#define	VR_DMABUFSZ		(VR_MAX_PKTSZ)
113#define	VR_MMI_WAITINCR		(10)
114#define	VR_MMI_WAITMAX		(10000)
115#define	VR_CAM_SZ		(32)
116
117/*
118 * PCI identification for the Rhine's.
119 */
120#define	VR_PCI_VIA_VENID		0x1106
121#define	VR_PCI_DEVID_RHINE		0x3043
122#define	VR_PCI_DEVID_RHINE_IIIM		0x3053
123#define	VR_PCI_DEVID_RHINE_II2		0x3065
124#define	VR_PCI_DEVID_RHINE_III		0x3106
125#define	VR_PCI_DEVID_RHINE_II		0x6100
126
127#define	VR_PCI_REVID_VT86C100A_E	0x04
128#define	VR_PCI_REVID_VT6102_A		0x40
129#define	VR_PCI_REVID_VT6102_C		0x42
130#define	VR_PCI_REVID_VT6105_A0		0x80
131#define	VR_PCI_REVID_VT6105_B0		0x83
132#define	VR_PCI_REVID_VT6105_LOM		0x8A
133#define	VR_PCI_REVID_VT6107_A0		0x8C
134#define	VR_PCI_REVID_VT6107_A1		0x8D
135#define	VR_PCI_REVID_VT6105M_A0		0x90
136#define	VR_PCI_REVID_VT6105M_B1		0x94
137
138/*
139 * Feature bits for the different cards.
140 */
141#define	VR_FEATURE_NONE			(0)
142#define	VR_FEATURE_RX_PAUSE_CAP		(1 << 0) /* can receive pauses */
143#define	VR_FEATURE_TX_PAUSE_CAP		(1 << 1) /* can transmit pauses */
144#define	VR_FEATURE_MRDLNMULTIPLE	(1 << 2) /* can read mult cache lines */
145#define	VR_FEATURE_TXCHKSUM		(1 << 3) /* can do TX TCP checksum */
146#define	VR_FEATURE_RXCHKSUM		(1 << 4) /* can do RX TCP checksum */
147#define	VR_FEATURE_CAMSUPPORT		(1 << 5) /* has a CAM filter */
148#define	VR_FEATURE_VLANTAGGING		(1 << 6) /* can do VLAN tagging */
149#define	VR_FEATURE_MIBCOUNTER		(1 << 7) /* has a MIB counter */
150
151/*
152 * Bug bits for the different cards.
153 */
154#define	VR_BUG_NONE			(0)
155#define	VR_BUG_TXALIGN			(1 << 0) /* needs aligned TX */
156#define	VR_BUG_NEEDMODE10T		(1 << 1) /* chip needs mode10t secret */
157#define	VR_BUG_NEEDMIION		(1 << 2) /* chip needs miion secret */
158#define	VR_BUG_NEEDMODE2PCEROPT		(1 << 3) /* chip needs pceropt */
159#define	VR_BUG_NO_TXQUEUEING		(1 << 4) /* chip cannot queue tx */
160#define	VR_BUG_NO_MEMIO			(1 << 5) /* chip cannot memory space */
161#define	VR_BUG_MIIPOLLSTOP		(1 << 6) /* special to stop polling */
162
163#define	VR_GET8(acc, p)		\
164		ddi_get8((acc)->hdl,	\
165		    (uint8_t *)((void *)((acc)->addr + (p))))
166#define	VR_GET16(acc, p)	\
167		ddi_get16((acc)->hdl,	\
168		    (uint16_t *)((void *)((acc)->addr + (p))))
169#define	VR_GET32(acc, p)	\
170		ddi_get32((acc)->hdl,	\
171		    (uint32_t *)((void *)((acc)->addr + (p))))
172
173#define	VR_PUT8(acc, p, v)	\
174		ddi_put8((acc)->hdl,	\
175		    (uint8_t *)((void *)((acc)->addr + (p))), v)
176#define	VR_PUT16(acc, p, v)	\
177		ddi_put16((acc)->hdl,	\
178		    (uint16_t *)((void *)((acc)->addr + (p))), v)
179#define	VR_PUT32(acc, p, v)	\
180		ddi_put32((acc)->hdl,	\
181		    (uint32_t *)((void *)((acc)->addr + (p))), v)
182
183/*
184 * Clear bit b in register r.
185 */
186#define	VR_CLRBIT8(acc, r, b)			\
187		VR_PUT8(acc, r, VR_GET8(acc, r) & ~(b))
188#define	VR_CLRBIT16(acc, r, b)			\
189		VR_PUT16(acc, r, VR_GET16(acc, r) & ~(b))
190#define	VR_CLRBIT32(acc, r, b)			\
191		VR_PUT32(acc, r, VR_GET32(acc, r) & ~(b))
192
193/*
194 * Set bit b in register r.
195 */
196#define	VR_SETBIT8(acc, r, b)			\
197		VR_PUT8(acc, r, (VR_GET8(acc, r) | (b)))
198#define	VR_SETBIT16(acc, r, b)			\
199		VR_PUT16(acc, r, (VR_GET16(acc, r) | (b)))
200#define	VR_SETBIT32(acc, r, b)			\
201		VR_PUT32(acc, r, (VR_GET32(acc, r) | (b)))
202
203/*
204 * Set bits b in register r to value v.
205 */
206#define	VR_SETBITS8(acc, r, b, v)			\
207		VR_PUT8(acc, r, (VR_GET8(acc, r) & ~(b)) | (v))
208#define	VR_SETBITS16(acc, r, b, v)			\
209		VR_PUT16(acc, r, (VR_GET16(acc, r) & ~(b)) | (v))
210#define	VR_SETBITS32(acc, r, b, v)			\
211		VR_PUT32(acc, r, (VR_GET32(acc, r) & ~(b)) | (v))
212
213/*
214 * The descriptor as used by the MAC.
215 */
216typedef struct {
217	uint32_t stat0;
218	uint32_t stat1;
219	uint32_t data;
220	uint32_t next;
221} vr_chip_desc_t;
222
223/*
224 * A structure describing an DMA object.
225 */
226typedef struct data_dma {
227	ddi_dma_handle_t	handle;
228	ddi_acc_handle_t	acchdl;
229	uint32_t		paddr;
230	char			*buf;
231	size_t			bufsz;
232} vr_data_dma_t;
233
234/*
235 * A descriptor as used by the host.
236 */
237typedef struct vr_desc {
238	vr_chip_desc_t		*cdesc;
239	uint32_t		paddr;		/* paddr of cdesc */
240	uint32_t		offset;		/* offset to paddr */
241	struct vr_desc		*next;
242	vr_data_dma_t		dmabuf;
243} vr_desc_t;
244
245typedef struct vr_ring {
246	vr_desc_t		*desc;
247	vr_chip_desc_t		*cdesc;
248	uint32_t		cdesc_paddr;
249	ddi_dma_handle_t	handle;
250	ddi_acc_handle_t	acchdl;
251} vr_ring_t;
252
253typedef struct {
254	kmutex_t		lock;
255	uint32_t		ndesc;
256	uint32_t		nfree;
257	uint32_t		stallticks;
258	uint32_t		resched;
259	uint32_t		intr_distance;
260	vr_desc_t		*ring;
261	vr_desc_t		*wp;			/* write pointer */
262	vr_desc_t		*cp;			/* claim pointer */
263} vr_tx_t;
264
265typedef struct {
266	uint32_t		ndesc;
267	vr_desc_t		*ring;
268	vr_desc_t		*rp;			/* read pointer */
269} vr_rx_t;
270
271typedef enum {
272	VR_LINK_STATE_UNKNOWN = LINK_STATE_UNKNOWN,
273	VR_LINK_STATE_DOWN = LINK_STATE_DOWN,
274	VR_LINK_STATE_UP = LINK_STATE_UP
275} vr_link_state_t;
276
277typedef enum {
278	VR_LINK_SPEED_UNKNOWN,
279	VR_LINK_SPEED_10MBS,
280	VR_LINK_SPEED_100MBS
281} vr_link_speed_t;
282
283typedef enum {
284	VR_LINK_DUPLEX_UNKNOWN = LINK_DUPLEX_UNKNOWN,
285	VR_LINK_DUPLEX_FULL = LINK_DUPLEX_FULL,
286	VR_LINK_DUPLEX_HALF = LINK_DUPLEX_HALF
287} vr_link_duplex_t;
288
289typedef enum {
290	VR_LINK_AUTONEG_UNKNOWN,
291	VR_LINK_AUTONEG_OFF,
292	VR_LINK_AUTONEG_ON
293} vr_link_autoneg_t;
294
295/*
296 * Pause variations.
297 */
298typedef enum {
299	VR_PAUSE_UNKNOWN,
300	VR_PAUSE_NONE = LINK_FLOWCTRL_NONE,
301	VR_PAUSE_TRANSMIT = LINK_FLOWCTRL_TX,
302	VR_PAUSE_RECEIVE = LINK_FLOWCTRL_RX,
303	VR_PAUSE_BIDIRECTIONAL = LINK_FLOWCTRL_BI
304} vr_link_flowctrl_t;
305
306/*
307 * Type of medium attachement unit.
308 */
309typedef enum {
310	VR_MAU_UNKNOWN = XCVR_UNDEFINED,
311	VR_MAU_NONE = XCVR_NONE,
312	VR_MAU_10 = XCVR_10,
313	VR_MAU_100T4 = XCVR_100T4,
314	VR_MAU_100X = XCVR_100X,
315	VR_MAU_100T2 = XCVR_100T2,
316	VR_MAU_1000X = XCVR_1000X,
317	VR_MAU_1000T = XCVR_1000T
318} vr_mau_t;
319
320typedef struct {
321	vr_link_state_t		state;
322	vr_link_speed_t		speed;
323	vr_link_duplex_t	duplex;
324	vr_link_flowctrl_t	flowctrl;
325	vr_mau_t		mau;
326} vr_link_t;
327
328typedef enum {
329	CHIPSTATE_UNKNOWN,
330	CHIPSTATE_INITIALIZED,
331	CHIPSTATE_RUNNING,
332	CHIPSTATE_STOPPED,
333	CHIPSTATE_SLEEPING,
334	CHIPSTATE_SUSPENDED,
335	CHIPSTATE_SUSPENDED_RUNNING,
336	CHIPSTATE_ERROR
337} vr_chip_state_t;
338
339typedef struct {
340	uint16_t	control;
341	uint16_t	status;
342	uint16_t	identh;
343	uint16_t	identl;
344	uint16_t	anadv;
345	uint16_t	lpable;
346	uint16_t	anexp;
347} mii_t;
348
349/*
350 * A structure defining the various types of cards and their habits.
351 */
352typedef struct {
353	uint8_t		revmin;
354	uint8_t		revmax;
355	char		name[128];
356	uint32_t	bugs;
357	uint32_t	features;
358} chip_info_t;
359
360/*
361 * A structure describing the card.
362 */
363typedef struct {
364	uint16_t		vendor;
365	uint16_t		device;
366	uint8_t			revision;
367	vr_chip_state_t		state;
368	mii_t			mii;
369	vr_link_t		link;
370	chip_info_t		info;
371	uint32_t		phyaddr;
372} vr_chip_t;
373
374/*
375 * Operational parameters.
376 */
377typedef struct {
378	uint16_t		anadv_en;
379	uint16_t		an_phymask;
380	uint16_t		an_macmask;
381	vr_link_autoneg_t	an_en;
382	uint32_t		mtu;
383} vr_param_t;
384
385typedef enum {
386	VR_SUCCESS = 0,
387	VR_FAILURE = 1
388} vr_result_t;
389
390typedef struct {
391	uint64_t	ether_stat_align_errors;
392	uint64_t	ether_stat_carrier_errors;
393	uint64_t	ether_stat_ex_collisions;
394	uint64_t	ether_stat_fcs_errors;
395	uint64_t	ether_stat_first_collisions;
396	uint64_t	ether_stat_macrcv_errors;
397	uint64_t	ether_stat_macxmt_errors;
398	uint64_t	ether_stat_multi_collisions;
399	uint64_t	ether_stat_toolong_errors;
400	uint64_t	ether_stat_tooshort_errors;
401	uint64_t	ether_stat_tx_late_collisions;
402	uint64_t	ether_stat_defer_xmts;
403	uint64_t	mac_stat_brdcstrcv;
404	uint64_t	mac_stat_brdcstxmt;
405	uint64_t	mac_stat_multixmt;
406	uint64_t	mac_stat_collisions;
407	uint64_t	mac_stat_ierrors;
408	uint64_t	mac_stat_ipackets;
409	uint64_t	mac_stat_multircv;
410	uint64_t	mac_stat_norcvbuf;
411	uint64_t	mac_stat_noxmtbuf;
412	uint64_t	mac_stat_obytes;
413	uint64_t	mac_stat_opackets;
414	uint64_t	mac_stat_rbytes;
415	uint64_t	mac_stat_underflows;
416	uint64_t	mac_stat_overflows;
417	uint64_t	cyclics;
418	uint64_t	txchecks;
419	uint64_t	intr_claimed;
420	uint64_t	intr_unclaimed;
421	uint64_t	linkchanges;
422	uint64_t	txcpybytes;
423	uint64_t	txmapbytes;
424	uint64_t	rxcpybytes;
425	uint64_t	rxmapbytes;
426	uint64_t	txreclaim0;
427	uint64_t	txreclaims;
428	uint32_t	txstalls;
429	uint32_t	resets;
430	uint32_t	allocbfail;
431} vr_stats_t;
432
433/*
434 * Access attributes for the card.
435 */
436typedef struct {
437	ddi_acc_handle_t	hdl;
438	caddr_t			addr;
439	pci_regspec_t		reg;
440} vr_acc_t;
441
442/*
443 * Instance state structure.
444 */
445typedef struct {
446	kmutex_t		oplock;
447	dev_info_t		*devinfo;
448	uint8_t			vendor_ether_addr [ETHERADDRL];
449	char			ifname[12];
450	mac_handle_t		machdl;
451	ddi_intr_handle_t	intr_hdl;
452	uint_t			intr_pri;
453	kmutex_t		intrlock;
454	vr_chip_t		chip;
455	vr_ring_t		txring;
456	vr_ring_t		rxring;
457	vr_rx_t			rx;
458	vr_tx_t			tx;
459	ddi_periodic_t		periodic_id;
460	int			nsets;
461	vr_acc_t		*regset;
462	vr_acc_t		*acc_mem;
463	vr_acc_t		*acc_io;
464	vr_acc_t		*acc_cfg;
465	vr_acc_t		*acc_reg;
466	vr_param_t		param;
467	vr_stats_t		stats;
468	struct kstat		*ksp;
469	vr_param_t		defaults;
470	uint32_t		promisc;
471	uint32_t		mhash0;
472	uint32_t		mhash1;
473	uint32_t		mcount;
474	uint32_t		reset;
475} vr_t;
476
477/*
478 * Function prototypes.
479 */
480int			vr_mac_getstat(void *arg, uint_t stat, uint64_t *val);
481int			vr_mac_start(void *vrp);
482void			vr_mac_stop(void *vrp);
483int			vr_mac_set_promisc(void *vrp, boolean_t promiscflag);
484int			vr_mac_set_multicast(void *vrp, boolean_t add,
485			    const uint8_t *mca);
486int			vr_mac_set_ether_addr(void *vrp,
487			    const uint8_t *macaddr);
488mblk_t			*vr_mac_tx_enqueue_list(void *p, mblk_t *mp);
489int			vr_mac_getprop(void *arg, const char *pr_name,
490			    mac_prop_id_t pr_num, uint_t pr_valsize,
491			    void *pr_val);
492int			vr_mac_setprop(void *arg, const char *pr_name,
493			    mac_prop_id_t pr_num,
494			    uint_t pr_valsize, const void *pr_val);
495void			vr_mac_propinfo(void *arg, const char *pr_name,
496			    mac_prop_id_t pr_num, mac_prop_info_handle_t prh);
497uint_t			vr_intr(caddr_t arg1, caddr_t arg2);
498#ifdef __cplusplus
499}
500#endif
501#endif	/* _VR_H */
502