1*6716431bSRobert Mustacchi /* 2*6716431bSRobert Mustacchi * @(#)rtl8150reg.h 1.1 04/09/16 3*6716431bSRobert Mustacchi * Macro definitions for Realtek 8150 USB to fast ethernet controller 4*6716431bSRobert Mustacchi * based on Realtek RTL8150 data sheet 5*6716431bSRobert Mustacchi * This file is public domain. Coded by M.Murayama (KHF04453@nifty.com) 6*6716431bSRobert Mustacchi */ 7*6716431bSRobert Mustacchi 8*6716431bSRobert Mustacchi #ifndef __RTL8150REG_H__ 9*6716431bSRobert Mustacchi #define __RTL8150REG_H__ 10*6716431bSRobert Mustacchi 11*6716431bSRobert Mustacchi /* 12*6716431bSRobert Mustacchi * Register offset 13*6716431bSRobert Mustacchi */ 14*6716431bSRobert Mustacchi #define IDR 0x0120 /* Base of ID registers */ 15*6716431bSRobert Mustacchi #define MAR 0x0126 /* Base of multicast registers */ 16*6716431bSRobert Mustacchi #define CR 0x012e /* Command register */ 17*6716431bSRobert Mustacchi #define TCR 0x012f /* Transmit Configuration register */ 18*6716431bSRobert Mustacchi #define RCR 0x0130 /* Receive Configuration register */ 19*6716431bSRobert Mustacchi #define TSR 0x0132 /* Transmit Status register */ 20*6716431bSRobert Mustacchi #define RSR 0x0133 /* Receive Status register */ 21*6716431bSRobert Mustacchi #define CON0 0x0135 /* Configuration register 0 */ 22*6716431bSRobert Mustacchi #define CON1 0x0136 /* Configuration register 1 */ 23*6716431bSRobert Mustacchi #define MSR 0x0137 /* Media Status register */ 24*6716431bSRobert Mustacchi #define PHYADD 0x0138 /* PHY address register */ 25*6716431bSRobert Mustacchi #define PHYDAT 0x0139 /* PHY data register */ 26*6716431bSRobert Mustacchi #define PHYCNT 0x013b /* PHY control register */ 27*6716431bSRobert Mustacchi #define GPPC 0x013d /* General purpose pin control */ 28*6716431bSRobert Mustacchi #define WAKECNT 0x013e /* Wake up event control */ 29*6716431bSRobert Mustacchi #define BMCR 0x0140 /* Basic Mode Control register */ 30*6716431bSRobert Mustacchi #define BMSR 0x0142 /* Basic Mode Status register */ 31*6716431bSRobert Mustacchi #define ANAR 0x0144 /* Auto Negotiation Advertisement register */ 32*6716431bSRobert Mustacchi #define ANLP 0x0146 /* Auto Negotiation Link Partner register */ 33*6716431bSRobert Mustacchi #define ANER 0x0148 /* Auto Negotiation Expansion register */ 34*6716431bSRobert Mustacchi #define NWAYT 0x014a /* Nway test register */ 35*6716431bSRobert Mustacchi #define CSCR 0x014c /* CS configuration register */ 36*6716431bSRobert Mustacchi #define CRC0 0x014e /* Power management register for wakeup frame0 */ 37*6716431bSRobert Mustacchi #define CRC1 0x0150 /* Power management register for wakeup frame1 */ 38*6716431bSRobert Mustacchi #define CRC2 0x0152 /* Power management register for wakeup frame2 */ 39*6716431bSRobert Mustacchi #define CRC3 0x0154 /* Power management register for wakeup frame3 */ 40*6716431bSRobert Mustacchi #define CRC4 0x0156 /* Power management register for wakeup frame4 */ 41*6716431bSRobert Mustacchi #define BYTEMASK0 0x0158 /* Power management wakeup frame0 bytemask */ 42*6716431bSRobert Mustacchi #define BYTEMASK1 0x0160 /* Power management wakeup frame1 bytemask */ 43*6716431bSRobert Mustacchi #define BYTEMASK2 0x0168 /* Power management wakeup frame2 bytemask */ 44*6716431bSRobert Mustacchi #define BYTEMASK3 0x0170 /* Power management wakeup frame3 bytemask */ 45*6716431bSRobert Mustacchi #define BYTEMASK4 0x0178 /* Power management wakeup frame4 bytemask */ 46*6716431bSRobert Mustacchi #define PHY1 0x0180 /* PHY parameter 1 */ 47*6716431bSRobert Mustacchi #define PHY2 0x0184 /* PHY parameter 2 */ 48*6716431bSRobert Mustacchi #define TW1 0x0186 /* Twister parameter 1 */ 49*6716431bSRobert Mustacchi 50*6716431bSRobert Mustacchi /* 51*6716431bSRobert Mustacchi * Bit field definitions 52*6716431bSRobert Mustacchi */ 53*6716431bSRobert Mustacchi /* CR : Command register (uint8_t) */ 54*6716431bSRobert Mustacchi #define CR_WEPROM 0x20 /* EEPROM write enable */ 55*6716431bSRobert Mustacchi #define CR_SOFT_RST 0x10 /* Reset */ 56*6716431bSRobert Mustacchi #define CR_RE 0x08 /* Ethernet receive enable */ 57*6716431bSRobert Mustacchi #define CR_TE 0x04 /* Ethernet transmit enable */ 58*6716431bSRobert Mustacchi #define CR_EP3CLREN 0x02 /* clear performance counter after EP3 */ 59*6716431bSRobert Mustacchi #define CR_AUTOLOAD 0x01 /* autoload contents of 93c46 */ 60*6716431bSRobert Mustacchi 61*6716431bSRobert Mustacchi #define CR_BITS "\020\006WEPROM\005SOFT_RST\004RE\003TE\002EP3CLREN\001AUTOLOAD" 62*6716431bSRobert Mustacchi 63*6716431bSRobert Mustacchi /* TCR: Transmit Configuration register */ 64*6716431bSRobert Mustacchi #define TCR_TXRR 0xc0 /* Tx retry count */ 65*6716431bSRobert Mustacchi #define TCR_TXRR_SHIFT 6 66*6716431bSRobert Mustacchi #define TCR_IFG 0x18 /* Interframe Gap */ 67*6716431bSRobert Mustacchi #define TCR_IFG_SHIFT 3 68*6716431bSRobert Mustacchi #define TCR_IFG_802_3 (3 << TCR_IFG_SHIFT) /* 802.3 standard */ 69*6716431bSRobert Mustacchi #define TCR_NOCRC 0x01 /* Inhibit Appending CRC */ 70*6716431bSRobert Mustacchi 71*6716431bSRobert Mustacchi #define TCR_BITS "\020\001NOCRC" 72*6716431bSRobert Mustacchi 73*6716431bSRobert Mustacchi /* Receive Configuration register */ 74*6716431bSRobert Mustacchi #define RCR_TAIL 0x0080 /* Rx header forward to host in CRC field */ 75*6716431bSRobert Mustacchi #define RCR_AER 0x0040 /* Accept Error packet */ 76*6716431bSRobert Mustacchi #define RCR_AR 0x0020 /* Accept runt */ 77*6716431bSRobert Mustacchi #define RCR_AM 0x0010 /* Accept multicast */ 78*6716431bSRobert Mustacchi #define RCR_AB 0x0008 /* Accept broadcast */ 79*6716431bSRobert Mustacchi #define RCR_AD 0x0004 /* Accept physical match */ 80*6716431bSRobert Mustacchi #define RCR_AAM 0x0002 /* Accept all Multicast */ 81*6716431bSRobert Mustacchi #define RCR_AAP 0x0001 /* Accept all physical */ 82*6716431bSRobert Mustacchi 83*6716431bSRobert Mustacchi #define RCR_ACCEPT_MODE \ 84*6716431bSRobert Mustacchi (RCR_AER | RCR_AR | RCR_AM | RCR_AB | RCR_AD | RCR_AAM | RCR_AAP) 85*6716431bSRobert Mustacchi 86*6716431bSRobert Mustacchi #define RCR_BITS \ 87*6716431bSRobert Mustacchi "\020\010TAIL\007AER\006AR\005AM\004AB\003AD\002AAM\001AAP" 88*6716431bSRobert Mustacchi 89*6716431bSRobert Mustacchi /* Transmit Status register */ 90*6716431bSRobert Mustacchi 91*6716431bSRobert Mustacchi #define TSR_ECOL 0x20 /* excessive collision indication */ 92*6716431bSRobert Mustacchi #define TSR_LCOL 0x10 /* late collision indication */ 93*6716431bSRobert Mustacchi #define TSR_LOSS_CRS 0x08 /* lost of carrier indication */ 94*6716431bSRobert Mustacchi #define TSR_JBR 0x04 /* jabber time out indication */ 95*6716431bSRobert Mustacchi #define TSR_BUF_EMPTY 0x02 /* Tx buffer is empty */ 96*6716431bSRobert Mustacchi #define TSR_BUF_FULL 0x01 /* Tx buffer is full */ 97*6716431bSRobert Mustacchi 98*6716431bSRobert Mustacchi #define TSR_BITS \ 99*6716431bSRobert Mustacchi "\020" \ 100*6716431bSRobert Mustacchi "\006ECOL" \ 101*6716431bSRobert Mustacchi "\005LCOL" \ 102*6716431bSRobert Mustacchi "\004LOSS_CRS" \ 103*6716431bSRobert Mustacchi "\003JBR" \ 104*6716431bSRobert Mustacchi "\002BUF_EMPTY" \ 105*6716431bSRobert Mustacchi "\001BUF_FULL" 106*6716431bSRobert Mustacchi 107*6716431bSRobert Mustacchi /* Receive status register in Rx packet field */ 108*6716431bSRobert Mustacchi #define RSR_WEVENT 0x80 /* Wakeup event indication */ 109*6716431bSRobert Mustacchi #define RSR_RX_BUF_FULL 0x40 /* Receive buffer full indication */ 110*6716431bSRobert Mustacchi #define RSR_LKCHG 0x20 /* Link change indication */ 111*6716431bSRobert Mustacchi #define RSR_RUNT 0x10 /* short packet indication */ 112*6716431bSRobert Mustacchi #define RSR_LONG 0x08 /* Long packet indication */ 113*6716431bSRobert Mustacchi #define RSR_CRC 0x04 /* CRC error indication */ 114*6716431bSRobert Mustacchi #define RSR_FAE 0x02 /* Frame alignment error */ 115*6716431bSRobert Mustacchi #define RSR_ROK 0x01 /* Receive OK indication */ 116*6716431bSRobert Mustacchi 117*6716431bSRobert Mustacchi #define RSR_ERRS (RSR_RUNT | RSR_LONG | RSR_CRC | RSR_FAE) 118*6716431bSRobert Mustacchi #define RSR_BITS \ 119*6716431bSRobert Mustacchi "\020" \ 120*6716431bSRobert Mustacchi "\010WEVENT" \ 121*6716431bSRobert Mustacchi "\007RX_BUF_FULL" \ 122*6716431bSRobert Mustacchi "\006LKCHG" \ 123*6716431bSRobert Mustacchi "\005RUNT" \ 124*6716431bSRobert Mustacchi "\004LONG" \ 125*6716431bSRobert Mustacchi "\003CRC" \ 126*6716431bSRobert Mustacchi "\002FAE" \ 127*6716431bSRobert Mustacchi "\001ROK" 128*6716431bSRobert Mustacchi 129*6716431bSRobert Mustacchi /* Config 0 */ 130*6716431bSRobert Mustacchi 131*6716431bSRobert Mustacchi #define CON0_SUSLED 0x80 132*6716431bSRobert Mustacchi #define CON0_PARM_EN 0x40 /* parameter enable */ 133*6716431bSRobert Mustacchi #define CON0_LDPS 0x08 134*6716431bSRobert Mustacchi #define CON0_MSEL 0x04 /* media select 1:MII, 0:auto */ 135*6716431bSRobert Mustacchi #define CON0_LEDS 0x03 /* LED pattern */ 136*6716431bSRobert Mustacchi 137*6716431bSRobert Mustacchi /* Config 1 */ 138*6716431bSRobert Mustacchi #define CON0_BWF 0x40 /* Broadcast wakeup function 1:on 0:off */ 139*6716431bSRobert Mustacchi #define CON0_MWF 0x20 /* Multicast wakeup function 1:on 0:off */ 140*6716431bSRobert Mustacchi #define CON0_UWF 0x10 /* Unicast wakeup function 1:on 0:off */ 141*6716431bSRobert Mustacchi #define CON0_LONGWF1 0x02 /* */ 142*6716431bSRobert Mustacchi #define CON0_LONGWF0 0x01 /* */ 143*6716431bSRobert Mustacchi 144*6716431bSRobert Mustacchi 145*6716431bSRobert Mustacchi /* MSR : Media Status register */ 146*6716431bSRobert Mustacchi #define MSR_TXFCE 0x80 /* Tx Flow control enable */ 147*6716431bSRobert Mustacchi #define MSR_RXFCE 0x40 /* Rx Flow control enable */ 148*6716431bSRobert Mustacchi #define MSR_DUPLEX 0x10 /* full duplex */ 149*6716431bSRobert Mustacchi #define MSR_SPEED_100 0x08 /* 100Mbps mode */ 150*6716431bSRobert Mustacchi #define MSR_LINK 0x04 /* link status */ 151*6716431bSRobert Mustacchi #define MSR_TXPF 0x02 /* 8150 sends pause packet */ 152*6716431bSRobert Mustacchi #define MSR_RXPF 0x01 /* 8150 is in backoff state */ 153*6716431bSRobert Mustacchi 154*6716431bSRobert Mustacchi #define MSR_BITS \ 155*6716431bSRobert Mustacchi "\020" \ 156*6716431bSRobert Mustacchi "\010TXFCE" \ 157*6716431bSRobert Mustacchi "\007RXFCE" \ 158*6716431bSRobert Mustacchi "\005DUPLEX" \ 159*6716431bSRobert Mustacchi "\004SPEED_100" \ 160*6716431bSRobert Mustacchi "\003LINK" \ 161*6716431bSRobert Mustacchi "\002TXPF" \ 162*6716431bSRobert Mustacchi "\001RXPF" 163*6716431bSRobert Mustacchi 164*6716431bSRobert Mustacchi /* MII PHY Address */ 165*6716431bSRobert Mustacchi #define PHYADD_MASK 0x1f 166*6716431bSRobert Mustacchi 167*6716431bSRobert Mustacchi /* MII PHY Data */ 168*6716431bSRobert Mustacchi #define PHYCNT_OWN 0x40 /* 8150 owns:1 not owns:0 */ 169*6716431bSRobert Mustacchi #define PHYCNT_RWCR 0x20 /* write:1 read:0 */ 170*6716431bSRobert Mustacchi #define PHYCNT_PHYOFF 0x1f 171*6716431bSRobert Mustacchi 172*6716431bSRobert Mustacchi /* BMCR (almost same with MII_CONTROL register) */ 173*6716431bSRobert Mustacchi #define BMCR_RESET 0x8000 /* PHY reset */ 174*6716431bSRobert Mustacchi #define BMCR_Spd_Set 0x2000 /* 100Mbps */ 175*6716431bSRobert Mustacchi #define BMCR_ANE 0x1000 /* auto negotiation enable */ 176*6716431bSRobert Mustacchi #define BMCR_RSA 0x0200 /* restart auto negotiation */ 177*6716431bSRobert Mustacchi #define BMCR_duplex 0x0100 /* 100Mbps */ 178*6716431bSRobert Mustacchi 179*6716431bSRobert Mustacchi /* Basic mode status register */ 180*6716431bSRobert Mustacchi /* Auto-negotiation Advertisement register */ 181*6716431bSRobert Mustacchi /* Auto-negotiation Link Partner Ability register */ 182*6716431bSRobert Mustacchi /* Auto-negotiation Expansion register */ 183*6716431bSRobert Mustacchi 184*6716431bSRobert Mustacchi /* Nway test register */ 185*6716431bSRobert Mustacchi #define NWAYT_NWLPBK 0x0080 186*6716431bSRobert Mustacchi #define NWAYT_ENNWLE 0x0008 187*6716431bSRobert Mustacchi #define NWAYT_FLAGABD 0x0004 188*6716431bSRobert Mustacchi #define NWAYT_FLAGPDF 0x0002 189*6716431bSRobert Mustacchi #define NWAYT_FLAGLSC 0x0001 190*6716431bSRobert Mustacchi 191*6716431bSRobert Mustacchi /* CS configuration register */ 192*6716431bSRobert Mustacchi #define CS_TESTFUN 0x8000 /* */ 193*6716431bSRobert Mustacchi #define CS_LD 0x0200 /* */ 194*6716431bSRobert Mustacchi #define CS_HEARTBEAT 0x0100 /* */ 195*6716431bSRobert Mustacchi #define CS_JBEN 0x0080 /* */ 196*6716431bSRobert Mustacchi #define CS_F_LINK100 0x0040 /* */ 197*6716431bSRobert Mustacchi #define CS_F_CONNECT 0x0020 /* */ 198*6716431bSRobert Mustacchi #define CS_CON_STATUS 0x0008 /* */ 199*6716431bSRobert Mustacchi #define CS_CON_STATUS_EN 0x0004 /* */ 200*6716431bSRobert Mustacchi #define CS_PASS_SCR 0x0001 /* bypass scramble function */ 201*6716431bSRobert Mustacchi 202*6716431bSRobert Mustacchi /* 203*6716431bSRobert Mustacchi * header format of rx packet 204*6716431bSRobert Mustacchi */ 205*6716431bSRobert Mustacchi #define RXHD_MULT 0x8000 /* multicast packet */ 206*6716431bSRobert Mustacchi #define RXHD_PHYS 0x4000 /* physical match packet */ 207*6716431bSRobert Mustacchi #define RXHD_RUNT 0x2000 /* too short */ 208*6716431bSRobert Mustacchi #define RXHD_VALID 0x1000 /* packet is ok */ 209*6716431bSRobert Mustacchi #define RXHD_BYTECNT 0x0fff /* rx byte count */ 210*6716431bSRobert Mustacchi 211*6716431bSRobert Mustacchi #define RXHD_BITS \ 212*6716431bSRobert Mustacchi "\020" \ 213*6716431bSRobert Mustacchi "\020MULT" \ 214*6716431bSRobert Mustacchi "\017PHYS" \ 215*6716431bSRobert Mustacchi "\016RUNT" \ 216*6716431bSRobert Mustacchi "\015VALID" 217*6716431bSRobert Mustacchi /* 218*6716431bSRobert Mustacchi * Offset to EPROM contents 219*6716431bSRobert Mustacchi */ 220*6716431bSRobert Mustacchi #define URF_EEPROM_BASE 0x1200 221*6716431bSRobert Mustacchi #define EPROM_EthernetID 0x0002 222*6716431bSRobert Mustacchi 223*6716431bSRobert Mustacchi #endif /* __RTL8150REG_H__ */ 224