1*40db2e2bSzf /* 2*40db2e2bSzf * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3*40db2e2bSzf * Use is subject to license terms. 4*40db2e2bSzf */ 5*40db2e2bSzf 6*40db2e2bSzf /* 7*40db2e2bSzf * Copyright (c) 2005, 2006 8*40db2e2bSzf * Damien Bergamini <damien.bergamini@free.fr> 9*40db2e2bSzf * 10*40db2e2bSzf * Permission to use, copy, modify, and distribute this software for any 11*40db2e2bSzf * purpose with or without fee is hereby granted, provided that the above 12*40db2e2bSzf * copyright notice and this permission notice appear in all copies. 13*40db2e2bSzf * 14*40db2e2bSzf * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15*40db2e2bSzf * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16*40db2e2bSzf * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17*40db2e2bSzf * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18*40db2e2bSzf * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19*40db2e2bSzf * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20*40db2e2bSzf * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21*40db2e2bSzf */ 22*40db2e2bSzf #ifndef _URAL_REG_H 23*40db2e2bSzf #define _URAL_REG_H 24*40db2e2bSzf 25*40db2e2bSzf #ifdef __cplusplus 26*40db2e2bSzf extern "C" { 27*40db2e2bSzf #endif 28*40db2e2bSzf 29*40db2e2bSzf #define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) 30*40db2e2bSzf #define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) 31*40db2e2bSzf 32*40db2e2bSzf #define RAL_CONFIG_NO 1 33*40db2e2bSzf #define RAL_IFACE_INDEX 0 34*40db2e2bSzf 35*40db2e2bSzf #define RAL_VENDOR_REQUEST 0x01 36*40db2e2bSzf #define RAL_WRITE_MAC 0x02 37*40db2e2bSzf #define RAL_READ_MAC 0x03 38*40db2e2bSzf #define RAL_WRITE_MULTI_MAC 0x06 39*40db2e2bSzf #define RAL_READ_MULTI_MAC 0x07 40*40db2e2bSzf #define RAL_READ_EEPROM 0x09 41*40db2e2bSzf 42*40db2e2bSzf /* 43*40db2e2bSzf * MAC registers. 44*40db2e2bSzf */ 45*40db2e2bSzf #define RAL_MAC_CSR0 0x0400 /* ASIC Version */ 46*40db2e2bSzf #define RAL_MAC_CSR1 0x0402 /* System control */ 47*40db2e2bSzf #define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ 48*40db2e2bSzf #define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ 49*40db2e2bSzf #define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ 50*40db2e2bSzf #define RAL_MAC_CSR5 0x040a /* BSSID0 */ 51*40db2e2bSzf #define RAL_MAC_CSR6 0x040c /* BSSID1 */ 52*40db2e2bSzf #define RAL_MAC_CSR7 0x040e /* BSSID2 */ 53*40db2e2bSzf #define RAL_MAC_CSR8 0x0410 /* Max frame length */ 54*40db2e2bSzf #define RAL_MAC_CSR9 0x0412 /* Timer control */ 55*40db2e2bSzf #define RAL_MAC_CSR10 0x0414 /* Slot time */ 56*40db2e2bSzf #define RAL_MAC_CSR11 0x0416 /* IFS */ 57*40db2e2bSzf #define RAL_MAC_CSR12 0x0418 /* EIFS */ 58*40db2e2bSzf #define RAL_MAC_CSR13 0x041a /* Power mode0 */ 59*40db2e2bSzf #define RAL_MAC_CSR14 0x041c /* Power mode1 */ 60*40db2e2bSzf #define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ 61*40db2e2bSzf #define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ 62*40db2e2bSzf #define RAL_MAC_CSR17 0x0422 /* Power state control */ 63*40db2e2bSzf #define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ 64*40db2e2bSzf #define RAL_MAC_CSR19 0x0426 /* GPIO control */ 65*40db2e2bSzf #define RAL_MAC_CSR20 0x0428 /* LED control0 */ 66*40db2e2bSzf #define RAL_MAC_CSR22 0x042c /* Not documented */ 67*40db2e2bSzf 68*40db2e2bSzf /* 69*40db2e2bSzf * Tx/Rx Registers. 70*40db2e2bSzf */ 71*40db2e2bSzf #define RAL_TXRX_CSR0 0x0440 /* Security control */ 72*40db2e2bSzf #define RAL_TXRX_CSR2 0x0444 /* Rx control */ 73*40db2e2bSzf #define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ 74*40db2e2bSzf #define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ 75*40db2e2bSzf #define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ 76*40db2e2bSzf #define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ 77*40db2e2bSzf #define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ 78*40db2e2bSzf #define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ 79*40db2e2bSzf #define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ 80*40db2e2bSzf #define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ 81*40db2e2bSzf #define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ 82*40db2e2bSzf #define RAL_TXRX_CSR21 0x046a /* Not documented */ 83*40db2e2bSzf 84*40db2e2bSzf /* 85*40db2e2bSzf * Security registers. 86*40db2e2bSzf */ 87*40db2e2bSzf #define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ 88*40db2e2bSzf 89*40db2e2bSzf /* 90*40db2e2bSzf * PHY registers. 91*40db2e2bSzf */ 92*40db2e2bSzf #define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ 93*40db2e2bSzf #define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ 94*40db2e2bSzf #define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ 95*40db2e2bSzf #define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ 96*40db2e2bSzf #define RAL_PHY_CSR7 0x04ce /* BBP serial control */ 97*40db2e2bSzf #define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ 98*40db2e2bSzf #define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ 99*40db2e2bSzf #define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ 100*40db2e2bSzf 101*40db2e2bSzf /* 102*40db2e2bSzf * Statistics registers. 103*40db2e2bSzf */ 104*40db2e2bSzf #define RAL_STA_CSR0 0x04e0 /* FCS error */ 105*40db2e2bSzf 106*40db2e2bSzf 107*40db2e2bSzf #define RAL_DISABLE_RX (1 << 0) 108*40db2e2bSzf #define RAL_DROP_CRC (1 << 1) 109*40db2e2bSzf #define RAL_DROP_PHY (1 << 2) 110*40db2e2bSzf #define RAL_DROP_CTL (1 << 3) 111*40db2e2bSzf #define RAL_DROP_NOT_TO_ME (1 << 4) 112*40db2e2bSzf #define RAL_DROP_TODS (1 << 5) 113*40db2e2bSzf #define RAL_DROP_BAD_VERSION (1 << 6) 114*40db2e2bSzf #define RAL_DROP_MULTICAST (1 << 9) 115*40db2e2bSzf #define RAL_DROP_BROADCAST (1 << 10) 116*40db2e2bSzf 117*40db2e2bSzf #define RAL_SHORT_PREAMBLE (1 << 2) 118*40db2e2bSzf 119*40db2e2bSzf #define RAL_RESET_ASIC (1 << 0) 120*40db2e2bSzf #define RAL_RESET_BBP (1 << 1) 121*40db2e2bSzf #define RAL_HOST_READY (1 << 2) 122*40db2e2bSzf 123*40db2e2bSzf #define RAL_ENABLE_TSF (1 << 0) 124*40db2e2bSzf #define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 125*40db2e2bSzf #define RAL_ENABLE_TBCN (1 << 3) 126*40db2e2bSzf #define RAL_ENABLE_BEACON_GENERATOR (1 << 4) 127*40db2e2bSzf 128*40db2e2bSzf #define RAL_RF_AWAKE (3 << 7) 129*40db2e2bSzf #define RAL_BBP_AWAKE (3 << 5) 130*40db2e2bSzf 131*40db2e2bSzf #define RAL_BBP_WRITE (1 << 15) 132*40db2e2bSzf #define RAL_BBP_BUSY (1 << 0) 133*40db2e2bSzf 134*40db2e2bSzf #define RAL_RF1_AUTOTUNE 0x08000 135*40db2e2bSzf #define RAL_RF3_AUTOTUNE 0x00040 136*40db2e2bSzf 137*40db2e2bSzf #define RAL_RF_2522 0x00 138*40db2e2bSzf #define RAL_RF_2523 0x01 139*40db2e2bSzf #define RAL_RF_2524 0x02 140*40db2e2bSzf #define RAL_RF_2525 0x03 141*40db2e2bSzf #define RAL_RF_2525E 0x04 142*40db2e2bSzf #define RAL_RF_2526 0x05 143*40db2e2bSzf /* dual-band RF */ 144*40db2e2bSzf #define RAL_RF_5222 0x10 145*40db2e2bSzf 146*40db2e2bSzf #define RAL_BBP_VERSION 0 147*40db2e2bSzf #define RAL_BBP_TX 2 148*40db2e2bSzf #define RAL_BBP_RX 14 149*40db2e2bSzf 150*40db2e2bSzf #define RAL_BBP_ANTA 0x00 151*40db2e2bSzf #define RAL_BBP_DIVERSITY 0x01 152*40db2e2bSzf #define RAL_BBP_ANTB 0x02 153*40db2e2bSzf #define RAL_BBP_ANTMASK 0x03 154*40db2e2bSzf #define RAL_BBP_FLIPIQ 0x04 155*40db2e2bSzf 156*40db2e2bSzf #define RAL_JAPAN_FILTER 0x08 157*40db2e2bSzf 158*40db2e2bSzf #pragma pack(1) 159*40db2e2bSzf struct ural_tx_desc { 160*40db2e2bSzf uint32_t flags; 161*40db2e2bSzf #define RAL_TX_RETRY(x) ((x) << 4) 162*40db2e2bSzf #define RAL_TX_MORE_FRAG (1 << 8) 163*40db2e2bSzf #define RAL_TX_ACK (1 << 9) 164*40db2e2bSzf #define RAL_TX_TIMESTAMP (1 << 10) 165*40db2e2bSzf #define RAL_TX_OFDM (1 << 11) 166*40db2e2bSzf #define RAL_TX_NEWSEQ (1 << 12) 167*40db2e2bSzf 168*40db2e2bSzf #define RAL_TX_IFS_MASK 0x00006000 169*40db2e2bSzf #define RAL_TX_IFS_BACKOFF (0 << 13) 170*40db2e2bSzf #define RAL_TX_IFS_SIFS (1 << 13) 171*40db2e2bSzf #define RAL_TX_IFS_NEWBACKOFF (2 << 13) 172*40db2e2bSzf #define RAL_TX_IFS_NONE (3 << 13) 173*40db2e2bSzf 174*40db2e2bSzf uint16_t wme; 175*40db2e2bSzf #define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) 176*40db2e2bSzf #define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) 177*40db2e2bSzf #define RAL_AIFSN(x) (((x) & 0x3) << 6) 178*40db2e2bSzf #define RAL_IVOFFSET(x) (((x) & 0x3f)) 179*40db2e2bSzf 180*40db2e2bSzf uint16_t reserved1; 181*40db2e2bSzf uint8_t plcp_signal; 182*40db2e2bSzf uint8_t plcp_service; 183*40db2e2bSzf #define RAL_PLCP_LENGEXT 0x80 184*40db2e2bSzf 185*40db2e2bSzf uint8_t plcp_length_lo; 186*40db2e2bSzf uint8_t plcp_length_hi; 187*40db2e2bSzf uint32_t iv; 188*40db2e2bSzf uint32_t eiv; 189*40db2e2bSzf }; 190*40db2e2bSzf #pragma pack() 191*40db2e2bSzf 192*40db2e2bSzf #pragma pack(1) 193*40db2e2bSzf struct ural_rx_desc { 194*40db2e2bSzf uint32_t flags; 195*40db2e2bSzf #define RAL_RX_CRC_ERROR (1 << 5) 196*40db2e2bSzf #define RAL_RX_OFDM (1 << 6) 197*40db2e2bSzf #define RAL_RX_PHY_ERROR (1 << 7) 198*40db2e2bSzf 199*40db2e2bSzf uint8_t rssi; 200*40db2e2bSzf uint8_t rate; 201*40db2e2bSzf uint16_t reserved; 202*40db2e2bSzf 203*40db2e2bSzf uint32_t iv; 204*40db2e2bSzf uint32_t eiv; 205*40db2e2bSzf }; 206*40db2e2bSzf #pragma pack() 207*40db2e2bSzf 208*40db2e2bSzf #define RAL_RF_LOBUSY (1 << 15) 209*40db2e2bSzf #define RAL_RF_BUSY ((uint32_t)1 << 31) 210*40db2e2bSzf #define RAL_RF_20BIT (20 << 24) 211*40db2e2bSzf 212*40db2e2bSzf #define RAL_RF1 0 213*40db2e2bSzf #define RAL_RF2 2 214*40db2e2bSzf #define RAL_RF3 1 215*40db2e2bSzf #define RAL_RF4 3 216*40db2e2bSzf 217*40db2e2bSzf #define RAL_EEPROM_ADDRESS 0x0004 218*40db2e2bSzf #define RAL_EEPROM_TXPOWER 0x003c 219*40db2e2bSzf #define RAL_EEPROM_CONFIG0 0x0016 220*40db2e2bSzf #define RAL_EEPROM_BBP_BASE 0x001c 221*40db2e2bSzf 222*40db2e2bSzf #ifdef __cplusplus 223*40db2e2bSzf } 224*40db2e2bSzf #endif 225*40db2e2bSzf 226*40db2e2bSzf #endif /* _URAL_REG_H */ 227