xref: /illumos-gate/usr/src/uts/common/io/udmf/dm9601reg.h (revision 6716431b)
1*6716431bSRobert Mustacchi /*
2*6716431bSRobert Mustacchi  * Macro definitions for Davicom DM9601 USB to fast ethernet controler
3*6716431bSRobert Mustacchi  * based on Davicom DM9601E data sheet
4*6716431bSRobert Mustacchi  * This file is public domain. Coded by M.Murayama (KHF04453@nifty.com)
5*6716431bSRobert Mustacchi  */
6*6716431bSRobert Mustacchi 
7*6716431bSRobert Mustacchi #ifndef __DM9601_H__
8*6716431bSRobert Mustacchi #define	__DM9601_H__
9*6716431bSRobert Mustacchi 
10*6716431bSRobert Mustacchi /*
11*6716431bSRobert Mustacchi  * offset of registers
12*6716431bSRobert Mustacchi  */
13*6716431bSRobert Mustacchi #define	NCR	0x00U	/* network control register */
14*6716431bSRobert Mustacchi #define	NSR	0x01U	/* network status register */
15*6716431bSRobert Mustacchi #define	TCR	0x02U	/* tx control register */
16*6716431bSRobert Mustacchi #define	TSR1	0x03U	/* tx status register 1 */
17*6716431bSRobert Mustacchi #define	TSR2	0x04U	/* tx status register 2 */
18*6716431bSRobert Mustacchi #define	RCR	0x05U	/* rx control register */
19*6716431bSRobert Mustacchi #define	RSR	0x06U	/* rx status register */
20*6716431bSRobert Mustacchi #define	ROCR	0x07U	/* rx overflow counter register */
21*6716431bSRobert Mustacchi #define	BPTR	0x08U	/* back pressure threshold regster */
22*6716431bSRobert Mustacchi #define	FCTR	0x09U	/* flow control threshold regster */
23*6716431bSRobert Mustacchi #define	FCR	0x0aU	/* flow control threshold regster */
24*6716431bSRobert Mustacchi #define	EPCR	0x0bU	/* eeprom & phy control register */
25*6716431bSRobert Mustacchi #define	EPAR	0x0cU	/* eeprom & phy address register */
26*6716431bSRobert Mustacchi #define	EPDR	0x0dU	/* eeprom & phy data register (2byte) */
27*6716431bSRobert Mustacchi #define	WCR	0x0fU	/* wake up control register */
28*6716431bSRobert Mustacchi #define	PAR	0x10U	/* physical address register (6byte) */
29*6716431bSRobert Mustacchi #define	MAR	0x16U	/* multicast address register (8byte) */
30*6716431bSRobert Mustacchi #define	GPCR	0x1eU	/* general purpose control register */
31*6716431bSRobert Mustacchi #define	GPR	0x1fU	/* general purpose register */
32*6716431bSRobert Mustacchi #define	VID	0x28U	/* vendor ID (2byte) */
33*6716431bSRobert Mustacchi #define	PID	0x2aU	/* product ID (2byte) */
34*6716431bSRobert Mustacchi #define	CHIPR	0x2cU	/* chip revision */
35*6716431bSRobert Mustacchi #define	USBDA	0xf0U	/* usb device address register */
36*6716431bSRobert Mustacchi #define	RXC	0xf1U	/* received packet counter register */
37*6716431bSRobert Mustacchi #define	TUSC	0xf2U	/* tx packet counter/usb status register */
38*6716431bSRobert Mustacchi #define	USBC	0xf4U	/* usb control register */
39*6716431bSRobert Mustacchi 
40*6716431bSRobert Mustacchi /*
41*6716431bSRobert Mustacchi  * register definitions
42*6716431bSRobert Mustacchi  */
43*6716431bSRobert Mustacchi /* network control register */
44*6716431bSRobert Mustacchi #define	NCR_EXT_PHY	0x80U	/* 1: select external phy */
45*6716431bSRobert Mustacchi #define	NCR_WAKEEN	0x40U	/* 1: wake up event enable */
46*6716431bSRobert Mustacchi #define	NCR_FCOL	0x10U	/* force collision mode for test */
47*6716431bSRobert Mustacchi #define	NCR_FDX		0x08U	/* 1: full duplex mode (for external phy) */
48*6716431bSRobert Mustacchi #define	NCR_LBK		0x06U
49*6716431bSRobert Mustacchi #define		NCR_LBK_SHIFT		1
50*6716431bSRobert Mustacchi #define		NCR_LBK_NORMAL	(0U << NCR_LBK_SHIFT)
51*6716431bSRobert Mustacchi #define		NCR_LBK_MAC	(1U << NCR_LBK_SHIFT)
52*6716431bSRobert Mustacchi #define		NCR_LBK_PHY_D	(2U << NCR_LBK_SHIFT)
53*6716431bSRobert Mustacchi #define		NCR_LBK_PHY_A	(3U << NCR_LBK_SHIFT)
54*6716431bSRobert Mustacchi #define	NCR_RST		0x01U	/* 1: reset, auto clear */
55*6716431bSRobert Mustacchi 
56*6716431bSRobert Mustacchi #define	NCR_BITS	\
57*6716431bSRobert Mustacchi 	"\020"	\
58*6716431bSRobert Mustacchi 	"\010EXT_PHY"	\
59*6716431bSRobert Mustacchi 	"\007WAKEEN"	\
60*6716431bSRobert Mustacchi 	"\005FCOL"	\
61*6716431bSRobert Mustacchi 	"\004FDX"	\
62*6716431bSRobert Mustacchi 	"\001RST"
63*6716431bSRobert Mustacchi 
64*6716431bSRobert Mustacchi /* network status register */
65*6716431bSRobert Mustacchi #define	NSR_SPEED	0x80U	/* 1:10M 0:100M */
66*6716431bSRobert Mustacchi #define	NSR_LINKST	0x40U	/* 1:ok 0:fail */
67*6716431bSRobert Mustacchi #define	NSR_WAKEST	0x20U	/* 1:enabled */
68*6716431bSRobert Mustacchi #define	NSR_TXFULL	0x10U	/* 1:tx fifo full */
69*6716431bSRobert Mustacchi #define	NSR_TX2END	0x08U	/* tx packet2 complete status */
70*6716431bSRobert Mustacchi #define	NSR_TX1END	0x04U	/* tx packet1 complete status */
71*6716431bSRobert Mustacchi #define	NSR_RXOV	0x02U	/* rx fifo overflow */
72*6716431bSRobert Mustacchi #define	NSR_RXRDY	0x01U	/* rx packet ready */
73*6716431bSRobert Mustacchi 
74*6716431bSRobert Mustacchi #define	NSR_BITS	\
75*6716431bSRobert Mustacchi 	"\020"	\
76*6716431bSRobert Mustacchi 	"\010SPEED_10"	\
77*6716431bSRobert Mustacchi 	"\007LINKST_UP"	\
78*6716431bSRobert Mustacchi 	"\006WAKEST"	\
79*6716431bSRobert Mustacchi 	"\005TXFULL"	\
80*6716431bSRobert Mustacchi 	"\004TX2END"	\
81*6716431bSRobert Mustacchi 	"\003TX1END"	\
82*6716431bSRobert Mustacchi 	"\002RXOV"	\
83*6716431bSRobert Mustacchi 	"\001RXRDY"
84*6716431bSRobert Mustacchi 
85*6716431bSRobert Mustacchi /* tx control register */
86*6716431bSRobert Mustacchi #define	TCR_TJDIS	0x40U	/* tx jitter control */
87*6716431bSRobert Mustacchi #define	TCR_EXCEDM	0x20U	/* excessive collision mode */
88*6716431bSRobert Mustacchi #define	TCR_PAD_DIS2	0x10U	/* PAD appends disable for pkt2 */
89*6716431bSRobert Mustacchi #define	TCR_CRC_DIS2	0x08U	/* CRC appends disable for pkt2 */
90*6716431bSRobert Mustacchi #define	TCR_PAD_DIS1	0x04U	/* PAD appends disable for pkt1 */
91*6716431bSRobert Mustacchi #define	TCR_CRC_DIS1	0x02U	/* CRC appends disable for pkt1 */
92*6716431bSRobert Mustacchi 
93*6716431bSRobert Mustacchi #define	TCR_BITS	\
94*6716431bSRobert Mustacchi 	"\020"	\
95*6716431bSRobert Mustacchi 	"\007TJDIS"	\
96*6716431bSRobert Mustacchi 	"\006EXCEDM"	\
97*6716431bSRobert Mustacchi 	"\005PAD_DIS2"	\
98*6716431bSRobert Mustacchi 	"\004CRC_DIS2"	\
99*6716431bSRobert Mustacchi 	"\003PAD_DIS1"	\
100*6716431bSRobert Mustacchi 	"\002CRC_DIS1"
101*6716431bSRobert Mustacchi 
102*6716431bSRobert Mustacchi /* tx status register (ro) */
103*6716431bSRobert Mustacchi #define	TSR_TJTO	0x80U	/* tx jabber time out */
104*6716431bSRobert Mustacchi #define	TSR_LC		0x40U	/* loss of carrier */
105*6716431bSRobert Mustacchi #define	TSR_NC		0x20U	/* no carrier */
106*6716431bSRobert Mustacchi #define	TSR_LATEC	0x10U	/* late collision */
107*6716431bSRobert Mustacchi #define	TSR_COL		0x08U	/* late collision */
108*6716431bSRobert Mustacchi #define	TSR_EL		0x04U	/* excessive collision */
109*6716431bSRobert Mustacchi 
110*6716431bSRobert Mustacchi #define	TSR_BITS	\
111*6716431bSRobert Mustacchi 	"\020"		\
112*6716431bSRobert Mustacchi 	"\010TJTO"	\
113*6716431bSRobert Mustacchi 	"\007LC"	\
114*6716431bSRobert Mustacchi 	"\006NC"	\
115*6716431bSRobert Mustacchi 	"\005LATEC"	\
116*6716431bSRobert Mustacchi 	"\004COL"	\
117*6716431bSRobert Mustacchi 	"\003EL"
118*6716431bSRobert Mustacchi 
119*6716431bSRobert Mustacchi /* rx control register */
120*6716431bSRobert Mustacchi #define	RCR_WTDIS	0x40U	/* watch dog timer disable */
121*6716431bSRobert Mustacchi #define	RCR_DIS_LONG	0x20U	/* discard longer packets than 1522 */
122*6716431bSRobert Mustacchi #define	RCR_DIS_CRC	0x10U	/* discard crc error packets */
123*6716431bSRobert Mustacchi #define	RCR_ALL		0x08U	/* pass all multicast */
124*6716431bSRobert Mustacchi #define	RCR_RUNT	0x04U	/* pass runt packets */
125*6716431bSRobert Mustacchi #define	RCR_PRMSC	0x02U	/* promiscuous mode */
126*6716431bSRobert Mustacchi #define	RCR_RXEN	0x01U	/* rx enable */
127*6716431bSRobert Mustacchi 
128*6716431bSRobert Mustacchi #define	RCR_BITS	\
129*6716431bSRobert Mustacchi 	"\020"		\
130*6716431bSRobert Mustacchi 	"\007WTDIS"	\
131*6716431bSRobert Mustacchi 	"\006DIS_LONG"	\
132*6716431bSRobert Mustacchi 	"\005DIS_CRC"	\
133*6716431bSRobert Mustacchi 	"\004ALL"	\
134*6716431bSRobert Mustacchi 	"\003RUNT"	\
135*6716431bSRobert Mustacchi 	"\002PRMSC"	\
136*6716431bSRobert Mustacchi 	"\001RXEN"
137*6716431bSRobert Mustacchi 
138*6716431bSRobert Mustacchi /* rx status register */
139*6716431bSRobert Mustacchi #define	RSR_RF		0x80U	/* runt frame */
140*6716431bSRobert Mustacchi #define	RSR_MF		0x40U	/* multicast frame */
141*6716431bSRobert Mustacchi #define	RSR_LCS		0x20U	/* late collision seen */
142*6716431bSRobert Mustacchi #define	RSR_RWTO	0x10U	/* receive watchdog timeout */
143*6716431bSRobert Mustacchi #define	RSR_PLE		0x08U	/* physical layer error */
144*6716431bSRobert Mustacchi #define	RSR_AE		0x04U	/* alignment error */
145*6716431bSRobert Mustacchi #define	RSR_CE		0x02U	/* crc error */
146*6716431bSRobert Mustacchi #define	RSR_FOE		0x01U	/* fifo overflow error */
147*6716431bSRobert Mustacchi 
148*6716431bSRobert Mustacchi #define	RSR_BITS	\
149*6716431bSRobert Mustacchi 	"\020"		\
150*6716431bSRobert Mustacchi 	"\010RF"	\
151*6716431bSRobert Mustacchi 	"\007MF"	\
152*6716431bSRobert Mustacchi 	"\006LCS"	\
153*6716431bSRobert Mustacchi 	"\005RWTO"	\
154*6716431bSRobert Mustacchi 	"\004PLE"	\
155*6716431bSRobert Mustacchi 	"\003AE"	\
156*6716431bSRobert Mustacchi 	"\002CE"	\
157*6716431bSRobert Mustacchi 	"\001FOE"
158*6716431bSRobert Mustacchi 
159*6716431bSRobert Mustacchi /* receive overflow counter register */
160*6716431bSRobert Mustacchi #define	ROCR_RXFU	0x80U	/* receive overflow counter overflow */
161*6716431bSRobert Mustacchi #define	ROCR_ROC	0x7fU	/* receive overflow counter */
162*6716431bSRobert Mustacchi 
163*6716431bSRobert Mustacchi #define	ROCR_BITS	\
164*6716431bSRobert Mustacchi 	"\020"		\
165*6716431bSRobert Mustacchi 	"\010RXFU"
166*6716431bSRobert Mustacchi 
167*6716431bSRobert Mustacchi /* back pressure threshold register */
168*6716431bSRobert Mustacchi #define	BPTR_BPHW	0xf0U	/* high water overflow threshold */
169*6716431bSRobert Mustacchi #define		BPTR_BPHW_SHIFT	4
170*6716431bSRobert Mustacchi #define		BPTR_BPHW_UNIT	1024U
171*6716431bSRobert Mustacchi #define		BPTR_BPHW_DEFAULT	(3 << BPTR_BPHW_SHIFT)	/* 3k */
172*6716431bSRobert Mustacchi #define	BPTR_JPT	0x0fU	/* jam pattern time */
173*6716431bSRobert Mustacchi #define		BPTR_JPT_SHIFT	0
174*6716431bSRobert Mustacchi #define		BPTR_JPT_5us	(0U << BPTR_JPT_SHIFT)
175*6716431bSRobert Mustacchi #define		BPTR_JPT_10us	(1U << BPTR_JPT_SHIFT)
176*6716431bSRobert Mustacchi #define		BPTR_JPT_15us	(2U << BPTR_JPT_SHIFT)
177*6716431bSRobert Mustacchi #define		BPTR_JPT_25us	(3U << BPTR_JPT_SHIFT)
178*6716431bSRobert Mustacchi #define		BPTR_JPT_50us	(4U << BPTR_JPT_SHIFT)
179*6716431bSRobert Mustacchi #define		BPTR_JPT_100us	(5U << BPTR_JPT_SHIFT)
180*6716431bSRobert Mustacchi #define		BPTR_JPT_150us	(6U << BPTR_JPT_SHIFT)
181*6716431bSRobert Mustacchi #define		BPTR_JPT_200us	(7U << BPTR_JPT_SHIFT)
182*6716431bSRobert Mustacchi #define		BPTR_JPT_250us	(8U << BPTR_JPT_SHIFT)
183*6716431bSRobert Mustacchi #define		BPTR_JPT_300us	(9U << BPTR_JPT_SHIFT)
184*6716431bSRobert Mustacchi #define		BPTR_JPT_350us	(10U << BPTR_JPT_SHIFT)
185*6716431bSRobert Mustacchi #define		BPTR_JPT_400us	(11U << BPTR_JPT_SHIFT)
186*6716431bSRobert Mustacchi #define		BPTR_JPT_450us	(12U << BPTR_JPT_SHIFT)
187*6716431bSRobert Mustacchi #define		BPTR_JPT_500us	(13U << BPTR_JPT_SHIFT)
188*6716431bSRobert Mustacchi #define		BPTR_JPT_550us	(14U << BPTR_JPT_SHIFT)
189*6716431bSRobert Mustacchi #define		BPTR_JPT_600us	(15U << BPTR_JPT_SHIFT)
190*6716431bSRobert Mustacchi 
191*6716431bSRobert Mustacchi /* flow control threshold register */
192*6716431bSRobert Mustacchi #define	FCTR_HWOT	0xf0U	/* rx fifo high water overflow threshold */
193*6716431bSRobert Mustacchi #define		FCTR_HWOT_SHIFT	4
194*6716431bSRobert Mustacchi #define		FCTR_HWOT_UNIT	1024U
195*6716431bSRobert Mustacchi #define	FCTR_LWOT	0x0fU	/* rx fifo low water overflow threshold */
196*6716431bSRobert Mustacchi #define		FCTR_LWOT_SHIFT	0
197*6716431bSRobert Mustacchi #define		FCTR_LWOT_UNIT	1024U
198*6716431bSRobert Mustacchi 
199*6716431bSRobert Mustacchi /* rx/tx flow control register */
200*6716431bSRobert Mustacchi #define	FCR_TXPO	0x80U	/* tx pause packet */
201*6716431bSRobert Mustacchi #define	FCR_TXPF	0x40U	/* tx pause packet */
202*6716431bSRobert Mustacchi #define	FCR_TXPEN	0x20U	/* tx pause packet */
203*6716431bSRobert Mustacchi #define	FCR_BKPA	0x10U	/* back pressure mode */
204*6716431bSRobert Mustacchi #define	FCR_BKPM	0x08U	/* back pressure mode */
205*6716431bSRobert Mustacchi #define	FCR_BKPS	0x04U	/* rx pause packet current status (r/c) */
206*6716431bSRobert Mustacchi #define	FCR_RXPCS	0x02U	/* rx pause packet current status (ro) */
207*6716431bSRobert Mustacchi #define	FCR_FLCE	0x01U	/* flow control enbale */
208*6716431bSRobert Mustacchi 
209*6716431bSRobert Mustacchi #define	FCR_BITS	\
210*6716431bSRobert Mustacchi 	"\020"		\
211*6716431bSRobert Mustacchi 	"\000TXPO"	\
212*6716431bSRobert Mustacchi 	"\000TXPF"	\
213*6716431bSRobert Mustacchi 	"\000TXPEN"	\
214*6716431bSRobert Mustacchi 	"\000BKPA"	\
215*6716431bSRobert Mustacchi 	"\000BKPM"	\
216*6716431bSRobert Mustacchi 	"\000BKPS"	\
217*6716431bSRobert Mustacchi 	"\000RXPCS"	\
218*6716431bSRobert Mustacchi 	"\000FLCE"
219*6716431bSRobert Mustacchi 
220*6716431bSRobert Mustacchi /* EEPROM & PHY control register (0x0b) */
221*6716431bSRobert Mustacchi #define	EPCR_REEP	0x20U	/* reload eeprom */
222*6716431bSRobert Mustacchi #define	EPCR_WEP	0x10U	/* write eeprom enable */
223*6716431bSRobert Mustacchi #define	EPCR_EPOS	0x08U	/* select device, 0:eeprom, 1:phy */
224*6716431bSRobert Mustacchi #define	EPCR_ERPRR	0x04U	/* read command */
225*6716431bSRobert Mustacchi #define	EPCR_ERPRW	0x02U	/* write command */
226*6716431bSRobert Mustacchi #define	EPCR_ERRE	0x01U	/* eeprom/phy access in progress (ro) */
227*6716431bSRobert Mustacchi 
228*6716431bSRobert Mustacchi #define	EPCR_BITS	\
229*6716431bSRobert Mustacchi 	"\020"		\
230*6716431bSRobert Mustacchi 	"\005REEP"	\
231*6716431bSRobert Mustacchi 	"\004WEP"	\
232*6716431bSRobert Mustacchi 	"\003EPOS"	\
233*6716431bSRobert Mustacchi 	"\002ERPRR"	\
234*6716431bSRobert Mustacchi 	"\001ERPRW"	\
235*6716431bSRobert Mustacchi 	"\000ERRE"
236*6716431bSRobert Mustacchi 
237*6716431bSRobert Mustacchi /* EEPROM & PHY access register (0x0c) */
238*6716431bSRobert Mustacchi #define	EPAR_PHYADR	0xc0U	/* phy address, internal phy(1) or external */
239*6716431bSRobert Mustacchi #define		EPAR_PHYADR_SHIFT	6
240*6716431bSRobert Mustacchi #define	EPAR_EROA	0x3fU	/* eeprom word addr or phy register addr */
241*6716431bSRobert Mustacchi #define		EPAR_EROA_SHIFT	0
242*6716431bSRobert Mustacchi 
243*6716431bSRobert Mustacchi /* EEPROM & PHY data register (0x0d(low)-0x0e(hi)) */
244*6716431bSRobert Mustacchi 
245*6716431bSRobert Mustacchi /* wake up control register (0x0f) */
246*6716431bSRobert Mustacchi #define	WCR_LINKEN	0x20U	/* enable link status event */
247*6716431bSRobert Mustacchi #define	WCR_SAMPLEEN	0x10U	/* enable sample frame event */
248*6716431bSRobert Mustacchi #define	WCR_MAGICEN	0x08U	/* enable magic pkt event */
249*6716431bSRobert Mustacchi #define	WCR_LINKST	0x04U	/* link status change occur ro */
250*6716431bSRobert Mustacchi #define	WCR_SAMPLEST	0x02U	/* sample frame rx occur ro */
251*6716431bSRobert Mustacchi #define	WCR_MAGICST	0x01U	/* magic pkt rx occur ro */
252*6716431bSRobert Mustacchi 
253*6716431bSRobert Mustacchi #define	WCR_BITS	\
254*6716431bSRobert Mustacchi 	"\020"		\
255*6716431bSRobert Mustacchi 	"\000LINKEN"	\
256*6716431bSRobert Mustacchi 	"\000SAMPLEEN"	\
257*6716431bSRobert Mustacchi 	"\000MAGICEN"	\
258*6716431bSRobert Mustacchi 	"\000LINKST"	\
259*6716431bSRobert Mustacchi 	"\000SAMPLEST"	\
260*6716431bSRobert Mustacchi 	"\000MAGICST"
261*6716431bSRobert Mustacchi 
262*6716431bSRobert Mustacchi /* physical address register (0x10-0x15) */
263*6716431bSRobert Mustacchi /* multicast address register (0x16-0x1c) */
264*6716431bSRobert Mustacchi /* general purpose control register (0x1e) */
265*6716431bSRobert Mustacchi #define	GPCR_GEPCTRL	0x7f
266*6716431bSRobert Mustacchi #define		GPCR_OUT(n)	(1U << (n))
267*6716431bSRobert Mustacchi 
268*6716431bSRobert Mustacchi #define	GPCR_BITS	\
269*6716431bSRobert Mustacchi 	"\020"		\
270*6716431bSRobert Mustacchi 	"\006OUT5"	\
271*6716431bSRobert Mustacchi 	"\005OUT4"	\
272*6716431bSRobert Mustacchi 	"\004OUT3"	\
273*6716431bSRobert Mustacchi 	"\003OUT2"	\
274*6716431bSRobert Mustacchi 	"\002OUT1"	\
275*6716431bSRobert Mustacchi 	"\001OUT0"
276*6716431bSRobert Mustacchi 
277*6716431bSRobert Mustacchi /* general purpose register (0x1f) */
278*6716431bSRobert Mustacchi #define	GPR_GEPIO5	0x20U
279*6716431bSRobert Mustacchi #define	GPR_GEPIO4	0x10U
280*6716431bSRobert Mustacchi #define	GPR_GEPIO3	0x08U
281*6716431bSRobert Mustacchi #define	GPR_GEPIO2	0x04U
282*6716431bSRobert Mustacchi #define	GPR_GEPIO1	0x02U
283*6716431bSRobert Mustacchi #define	GPR_GEPIO0	0x01U
284*6716431bSRobert Mustacchi 
285*6716431bSRobert Mustacchi #define	GPR_BITS	\
286*6716431bSRobert Mustacchi 	"\020"		\
287*6716431bSRobert Mustacchi 	"\006GEPIO5"	\
288*6716431bSRobert Mustacchi 	"\005GEPIO4"	\
289*6716431bSRobert Mustacchi 	"\004GEPIO3"	\
290*6716431bSRobert Mustacchi 	"\003GEPIO2"	\
291*6716431bSRobert Mustacchi 	"\002GEPIO1"	\
292*6716431bSRobert Mustacchi 	"\001GEPIO0"
293*6716431bSRobert Mustacchi 
294*6716431bSRobert Mustacchi /* vendor id register (0x28-0x29) */
295*6716431bSRobert Mustacchi /* product id register (0x2a-0x2b) */
296*6716431bSRobert Mustacchi /* chip revision register (0x2c) */
297*6716431bSRobert Mustacchi 
298*6716431bSRobert Mustacchi /* usb device address register (0xf0) */
299*6716431bSRobert Mustacchi #define	USBDA_USBFA	0x3fU	/* usb device address */
300*6716431bSRobert Mustacchi #define		USBDA_USBFA_SHIFT	0
301*6716431bSRobert Mustacchi 
302*6716431bSRobert Mustacchi /* receive packet counter register (0xf1) */
303*6716431bSRobert Mustacchi 
304*6716431bSRobert Mustacchi /* transmitpacket counter/usb status register (0xf2) */
305*6716431bSRobert Mustacchi #define	TUSR_RXFAULT	0x80U	/* indicate rx has unexpected condition */
306*6716431bSRobert Mustacchi #define	TUSR_SUSFLAG	0x40U	/* indicate device has suspended condition */
307*6716431bSRobert Mustacchi #define	TUSR_EP1RDY	0x20U	/* ready for read from ep1 pipe */
308*6716431bSRobert Mustacchi #define	TUSR_SRAM	0x18U	/* sram size 0:32K, 1:48K, 2:16K, 3:64K */
309*6716431bSRobert Mustacchi #define		TUSR_SRAM_SHIFT	3
310*6716431bSRobert Mustacchi #define		TUSR_SRAM_32K	(0U << TUSR_SRAM_SHIFT)
311*6716431bSRobert Mustacchi #define		TUSR_SRAM_48K	(1U << TUSR_SRAM_SHIFT)
312*6716431bSRobert Mustacchi #define		TUSR_SRAM_16K	(2U << TUSR_SRAM_SHIFT)
313*6716431bSRobert Mustacchi #define		TUSR_SRAM_64K	(3U << TUSR_SRAM_SHIFT)
314*6716431bSRobert Mustacchi #define	TUSR_TXC2	0x04U	/* two or more packets in tx buffer */
315*6716431bSRobert Mustacchi #define	TUSR_TXC1	0x02U	/* one packet in tx buffer */
316*6716431bSRobert Mustacchi #define	TUSR_TXC0	0x01U	/* no packet in tx buffer */
317*6716431bSRobert Mustacchi 
318*6716431bSRobert Mustacchi #define	TUSR_BITS	\
319*6716431bSRobert Mustacchi 	"\020"		\
320*6716431bSRobert Mustacchi 	"\010RXFAULT"	\
321*6716431bSRobert Mustacchi 	"\007SUSFLAG"	\
322*6716431bSRobert Mustacchi 	"\006EP1RDY"	\
323*6716431bSRobert Mustacchi 	"\003TXC2"	\
324*6716431bSRobert Mustacchi 	"\002TXC1"	\
325*6716431bSRobert Mustacchi 	"\001TXC0"
326*6716431bSRobert Mustacchi 
327*6716431bSRobert Mustacchi /* usb control register (0xf4) */
328*6716431bSRobert Mustacchi #define	USBC_EP3ACK	0x20U	/* ep3 will alway return 8byte data if NAK=0 */
329*6716431bSRobert Mustacchi #define	USBC_EP3NACK	0x10U	/* ep3 will alway return NAK */
330*6716431bSRobert Mustacchi #define	USBC_MEMTST	0x01U
331*6716431bSRobert Mustacchi 
332*6716431bSRobert Mustacchi /* bulk message format */
333*6716431bSRobert Mustacchi #define	TX_HEADER_SIZE	2
334*6716431bSRobert Mustacchi #define	RX_HEADER_SIZE	3
335*6716431bSRobert Mustacchi 
336*6716431bSRobert Mustacchi /* interrupt msg format */
337*6716431bSRobert Mustacchi struct intr_msg {
338*6716431bSRobert Mustacchi 	uint8_t	im_nsr;
339*6716431bSRobert Mustacchi 	uint8_t	im_tsr1;
340*6716431bSRobert Mustacchi 	uint8_t	im_tsr2;
341*6716431bSRobert Mustacchi 	uint8_t	im_rsr;
342*6716431bSRobert Mustacchi 	uint8_t	im_rocr;
343*6716431bSRobert Mustacchi 	uint8_t	im_rxc;
344*6716431bSRobert Mustacchi 	uint8_t	im_txc;
345*6716431bSRobert Mustacchi 	uint8_t	im_gpr;
346*6716431bSRobert Mustacchi };
347*6716431bSRobert Mustacchi #endif /* __DM9601_H__ */
348