1f8919bdaSduboff /* 2f8919bdaSduboff * sfereg.h: SiS900/DP83815 register definition 3f8919bdaSduboff * 4f8919bdaSduboff * Copyright (c) 2002-2007 Masayuki Murayama. All rights reserved. 5f8919bdaSduboff * 6f8919bdaSduboff * Redistribution and use in source and binary forms, with or without 7f8919bdaSduboff * modification, are permitted provided that the following conditions are met: 8f8919bdaSduboff * 9f8919bdaSduboff * 1. Redistributions of source code must retain the above copyright notice, 10f8919bdaSduboff * this list of conditions and the following disclaimer. 11f8919bdaSduboff * 12f8919bdaSduboff * 2. Redistributions in binary form must reproduce the above copyright notice, 13f8919bdaSduboff * this list of conditions and the following disclaimer in the documentation 14f8919bdaSduboff * and/or other materials provided with the distribution. 15f8919bdaSduboff * 16f8919bdaSduboff * 3. Neither the name of the author nor the names of its contributors may be 17f8919bdaSduboff * used to endorse or promote products derived from this software without 18f8919bdaSduboff * specific prior written permission. 19f8919bdaSduboff * 20f8919bdaSduboff * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21f8919bdaSduboff * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22f8919bdaSduboff * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23f8919bdaSduboff * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24f8919bdaSduboff * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25f8919bdaSduboff * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26f8919bdaSduboff * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27f8919bdaSduboff * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28f8919bdaSduboff * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29f8919bdaSduboff * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30f8919bdaSduboff * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31f8919bdaSduboff * DAMAGE. 32f8919bdaSduboff */ 33*23d366e3Sduboff 34f8919bdaSduboff #ifndef _SFEREG_H_ 35f8919bdaSduboff #define _SFEREG_H_ 36f8919bdaSduboff /* 37f8919bdaSduboff * Tx/Rx descriptor 38f8919bdaSduboff */ 39f8919bdaSduboff struct sfe_desc { 40f8919bdaSduboff volatile uint32_t d_link; /* link to the next */ 41f8919bdaSduboff volatile uint32_t d_cmdsts; /* command/status field */ 42f8919bdaSduboff volatile uint32_t d_bufptr; /* ptr to the first fragment */ 43f8919bdaSduboff }; 44f8919bdaSduboff 45f8919bdaSduboff /* CMDSTS common Bit Definition */ 46f8919bdaSduboff #define CMDSTS_OWN 0x80000000U /* 1: data consumer owns */ 47f8919bdaSduboff #define CMDSTS_MORE 0x40000000U /* Not the last descriptor */ 48f8919bdaSduboff #define CMDSTS_INTR 0x20000000U 49f8919bdaSduboff #define CMDSTS_SUPCRC 0x10000000U 50f8919bdaSduboff #define CMDSTS_INCCRC CMDSTS_SUPCRC 51f8919bdaSduboff #define CMDSTS_OK 0x08000000U /* Packet is OK */ 52f8919bdaSduboff #define CMDSTS_SIZE 0x00000fffU /* Descriptor byte count */ 53f8919bdaSduboff 54f8919bdaSduboff /* Transmit Status Bit Definition */ 55f8919bdaSduboff #define CMDSTS_TXA 0x04000000U /* Transmit abort */ 56f8919bdaSduboff #define CMDSTS_TFU 0x02000000U /* Transmit FIFO Underrun */ 57f8919bdaSduboff #define CMDSTS_CRS 0x01000000U /* Carrier sense lost */ 58f8919bdaSduboff #define CMDSTS_TD 0x00800000U /* Transmit deferred */ 59f8919bdaSduboff #define CMDSTS_ED 0x00400000U /* Exessive deferrral */ 60f8919bdaSduboff #define CMDSTS_OWC 0x00200000U /* Out of window collision */ 61f8919bdaSduboff #define CMDSTS_EC 0x00100000U /* Excessive collision */ 62f8919bdaSduboff #define CMDSTS_CCNT 0x000f0000U /* Collision count */ 63f8919bdaSduboff #define CMDSTS_CCNT_SHIFT (16) 64f8919bdaSduboff #define CCNT_MASK 0xfU /* Collision count mask */ 65f8919bdaSduboff 66f8919bdaSduboff #define TXSTAT_BITS \ 67f8919bdaSduboff "\020" \ 68f8919bdaSduboff "\040Own" \ 69f8919bdaSduboff "\037More" \ 70f8919bdaSduboff "\036Intr" \ 71f8919bdaSduboff "\035SupCrc" \ 72f8919bdaSduboff "\034Ok" \ 73f8919bdaSduboff "\033Abort" \ 74f8919bdaSduboff "\032UnderRun" \ 75f8919bdaSduboff "\031NoCarrier" \ 76f8919bdaSduboff "\030Deferd" \ 77f8919bdaSduboff "\027ExcDefer" \ 78f8919bdaSduboff "\026OWColl" \ 79f8919bdaSduboff "\025ExcColl" 80f8919bdaSduboff 81f8919bdaSduboff #define RXSTAT_BITS \ 82f8919bdaSduboff "\020" \ 83f8919bdaSduboff "\040Own" \ 84f8919bdaSduboff "\037More" \ 85f8919bdaSduboff "\036Intr" \ 86f8919bdaSduboff "\035IncCrc" \ 87f8919bdaSduboff "\034Ok" \ 88f8919bdaSduboff "\032OverRun" \ 89f8919bdaSduboff "\031MCast" \ 90f8919bdaSduboff "\030UniMatch" \ 91f8919bdaSduboff "\027TooLong" \ 92f8919bdaSduboff "\026Runt" \ 93f8919bdaSduboff "\025RxISErr" \ 94f8919bdaSduboff "\024CrcErr" \ 95f8919bdaSduboff "\023FaErr" \ 96f8919bdaSduboff "\022LoopBk" \ 97f8919bdaSduboff "\021RxCol" 98f8919bdaSduboff 99f8919bdaSduboff 100f8919bdaSduboff /* Receive Status Bit Definitions */ 101f8919bdaSduboff #define CMDSTS_RXA 0x04000000U /* Receive abort */ 102f8919bdaSduboff #define CMDSTS_RXO 0x02000000U /* Receive overrun */ 103f8919bdaSduboff #define CMDSTS_DEST 0x01800000U /* Destination class */ 104f8919bdaSduboff #define CMDSTS_DEST_SHIFT 23 /* Destination class */ 105f8919bdaSduboff #define DEST_REJECT 0U 106f8919bdaSduboff #define DEST_NODE 1U 107f8919bdaSduboff #define DEST_MULTI 2U 108f8919bdaSduboff #define DEST_BROAD 3U 109f8919bdaSduboff #define CMDSTS_LONG 0x00400000U /* Too long packet received */ 110f8919bdaSduboff #define CMDSTS_RUNT 0x00200000U /* Runt packet received */ 111f8919bdaSduboff #define CMDSTS_ISE 0x00100000U /* Invalid symbol error */ 112f8919bdaSduboff #define CMDSTS_CRCE 0x00080000U /* CRC error */ 113f8919bdaSduboff #define CMDSTS_FAE 0x00040000U /* Frame alignment */ 114f8919bdaSduboff #define CMDSTS_LBP 0x00020000U /* Loopback packet */ 115f8919bdaSduboff #define CMDSTS_COL 0x00010000U /* Collision activety */ 116f8919bdaSduboff 117f8919bdaSduboff /* 118f8919bdaSduboff * Offsets of MAC Operational Registers 119f8919bdaSduboff */ 120f8919bdaSduboff #define CR 0x00 /* Command register */ 121f8919bdaSduboff #define CFG 0x04 /* Configuration register */ 122f8919bdaSduboff #define EROMAR 0x08 /* EEPROM access register */ 123f8919bdaSduboff #define MEAR 0x08 /* alias for MII access register (sis900) */ 124f8919bdaSduboff #define PTSCR 0x0c /* PCI test control register */ 125f8919bdaSduboff #define ISR 0x10 /* Interrupt status register */ 126f8919bdaSduboff #define IMR 0x14 /* Interrupt mask register */ 127f8919bdaSduboff #define IER 0x18 /* Interrupt enable register */ 128f8919bdaSduboff #define ENPHY 0x1c /* Enhanced PHY access register */ 129f8919bdaSduboff #define TXDP 0x20 /* Transmit descriptor pointer reg */ 130f8919bdaSduboff #define TXCFG 0x24 /* Transmit configuration register */ 131f8919bdaSduboff #define RXDP 0x30 /* Receive descriptor pointer reg */ 132f8919bdaSduboff #define RXCFG 0x34 /* Receive configration register */ 133f8919bdaSduboff #define FLOWCTL 0x38 /* Flow control register (sis900) */ 134f8919bdaSduboff #define CCSR 0x3c /* Clock run status register (dp83815) */ 135f8919bdaSduboff #define PCR 0x44 /* Pause control register (dp83815) */ 136f8919bdaSduboff #define RFCR 0x48 /* Receive filter control register */ 137f8919bdaSduboff #define RFDR 0x4c /* Receive filter data register */ 138f8919bdaSduboff #define SRR 0x58 /* silicon revision register */ 139f8919bdaSduboff #define MII_REGS_BASE 0x80 /* DP83815 only */ 140f8919bdaSduboff #define PMCTL 0xb0 /* Power management control register */ 141f8919bdaSduboff #define PMEVT 0xb4 /* Power management wake-up event reg */ 142f8919bdaSduboff #define WAKECRC 0xbc /* Wake-up sample frame CRC register */ 143f8919bdaSduboff #define WAKEMASK 0xc0 /* Wake-up sample frame mask register */ 144f8919bdaSduboff 145f8919bdaSduboff 146f8919bdaSduboff /* Command register */ 147f8919bdaSduboff #define CR_RELOAD 0x0400U /* reload mac address */ 148f8919bdaSduboff #define CR_ACCESSMODE 0x0200U /* mii access mode */ 149f8919bdaSduboff #define CR_RST 0x0100U /* Reset */ 150f8919bdaSduboff #define CR_SWI 0x0080U /* Software interrupt */ 151f8919bdaSduboff #define CR_RXR 0x0020U /* Receiver reset */ 152f8919bdaSduboff #define CR_TXR 0x0010U /* Transmit reset */ 153f8919bdaSduboff #define CR_RXD 0x0008U /* Receiver disable */ 154f8919bdaSduboff #define CR_RXE 0x0004U /* Receiver enable */ 155f8919bdaSduboff #define CR_TXD 0x0002U /* Transmit disable */ 156f8919bdaSduboff #define CR_TXE 0x0001U /* Transmit enable */ 157f8919bdaSduboff 158f8919bdaSduboff #define CR_BITS \ 159f8919bdaSduboff "\020" \ 160f8919bdaSduboff "\011Reset" \ 161f8919bdaSduboff "\010SWI" \ 162f8919bdaSduboff "\006RxReset" \ 163f8919bdaSduboff "\005TxReset" \ 164f8919bdaSduboff "\004RxDisable" \ 165f8919bdaSduboff "\003RxEnable" \ 166f8919bdaSduboff "\002TxDisable" \ 167f8919bdaSduboff "\001TxEnable" 168f8919bdaSduboff 169f8919bdaSduboff /* Configration register */ 170f8919bdaSduboff #define CFG_LNKSTS 0x80000000U /* Link up (83815) */ 171f8919bdaSduboff #define CFG_SPEED100 0x40000000U /* 100Mbps (83815) */ 172f8919bdaSduboff #define CFG_FDUP 0x20000000U /* full duplex (83815) */ 173f8919bdaSduboff #define CFG_POL 0x10000000U /* 10Mbps polarity indication (83815) */ 174f8919bdaSduboff #define CFG_ANEG_DN 0x08000000U /* auto negotiation done (83815) */ 175*23d366e3Sduboff #define CFG_PHY_CFG 0x00fc0000U /* internal PHY configuration (83815) */ 176f8919bdaSduboff #define CFG_PINT_ACEN 0x00020000U /* PHY interrupt auto clear (83815) */ 177f8919bdaSduboff #define CFG_PAUSE_ADV 0x00010000U /* Advertise pause (83815) */ 178f8919bdaSduboff #define CFG_ANEG_SEL 0x0000e000U /* Auto-nego default (83815) */ 179f8919bdaSduboff #define CFG_EDB_MASTER 0x00002000U /* sis635, sis900B, sis96x */ 180f8919bdaSduboff #define CFG_EXT_PHY 0x00001000U /* External PHY support (83815) */ 181f8919bdaSduboff #define CFG_PHY_RST 0x00000400U /* Internal PHY reset (83815) */ 182f8919bdaSduboff #define CFG_RND_CNT 0x00000400U /* sis635 & 900B */ 183f8919bdaSduboff #define CFG_PHY_DIS 0x00000200U /* Internal PHY disable (83815) */ 184f8919bdaSduboff #define CFG_FAIR_BCKOFF 0x00000200U /* sis635 & 900B */ 185f8919bdaSduboff #define CFG_EUPHCOMP 0x00000100U /* DP83810 compatibility (83815) */ 186f8919bdaSduboff #define CFG_DESCRFMT 0x00000100U /* sis7016 */ 187f8919bdaSduboff #define CFG_REQALG 0x00000080U /* PCI Bus request algorithm */ 188f8919bdaSduboff #define CFG_SB 0x00000040U /* Single backoff */ 189f8919bdaSduboff #define CFG_POW 0x00000020U /* Program out of window timer */ 190f8919bdaSduboff #define CFG_EXD 0x00000010U /* Excessive deferral timer disable */ 191f8919bdaSduboff #define CFG_PESEL 0x00000008U /* Parity error detection action */ 192f8919bdaSduboff #define CFG_BROM_DIS 0x00000004U /* BootRom disable (83815) */ 193f8919bdaSduboff #define CFG_BEM 0x00000001U /* Big endian mode */ 194f8919bdaSduboff 195f8919bdaSduboff #define CFG_BITS_DP83815 \ 196f8919bdaSduboff "\020" \ 197f8919bdaSduboff "\040CFG_LNKSTS" \ 198f8919bdaSduboff "\037SPEED100" \ 199f8919bdaSduboff "\036FDUP" \ 200f8919bdaSduboff "\035POL" \ 201f8919bdaSduboff "\034ANEG_DN" \ 202f8919bdaSduboff "\022PINT_ACEN" \ 203f8919bdaSduboff "\021PAUSE_ADV" \ 204f8919bdaSduboff "\015EXT_PHY" \ 205f8919bdaSduboff "\013PHY_RST" \ 206f8919bdaSduboff "\012PHY_DIS" \ 207f8919bdaSduboff "\011EUPHCOMP" \ 208f8919bdaSduboff "\010REQALG" \ 209f8919bdaSduboff "\007SB" \ 210f8919bdaSduboff "\006POW" \ 211f8919bdaSduboff "\005EXD" \ 212f8919bdaSduboff "\004PESEL" \ 213f8919bdaSduboff "\003BROM_DIS" \ 214f8919bdaSduboff "\001BEM" 215f8919bdaSduboff 216f8919bdaSduboff #define CFG_BITS_SIS900 \ 217f8919bdaSduboff "\020" \ 218f8919bdaSduboff "\016EDB_EN" \ 219f8919bdaSduboff "\013RND_CNT" \ 220f8919bdaSduboff "\010REQALG" \ 221f8919bdaSduboff "\007SB" \ 222f8919bdaSduboff "\006POW" \ 223f8919bdaSduboff "\005EXD" \ 224f8919bdaSduboff "\004PESEL" \ 225f8919bdaSduboff "\001BEM" 226f8919bdaSduboff 227f8919bdaSduboff /* Serial EEPROM access register */ 228f8919bdaSduboff #define EROMAR_EECS 0x00000008U /* EEPROM chip select */ 229f8919bdaSduboff #define EROMAR_EESK 0x00000004U /* EEPROM serial clock */ 230f8919bdaSduboff #define EROMAR_EEDO 0x00000002U /* EEPROM data out */ 231f8919bdaSduboff #define EROMAR_EEDO_SHIFT 1 232f8919bdaSduboff #define EROMAR_EEDI 0x00000001U /* EEPROM data in + */ 233f8919bdaSduboff #define EROMAR_EEDI_SHIFT 0 234f8919bdaSduboff #define EROMAR_EEREQ 0x00000400U /* for sis963 eeprom mamagement */ 235f8919bdaSduboff #define EROMAR_EEDONE 0x00000200U /* for sis963 eeprom mamagement */ 236f8919bdaSduboff #define EROMAR_EEGNT 0x00000100U /* for sis963 eeprom mamagement */ 237f8919bdaSduboff 238f8919bdaSduboff #define MEAR_MDC 0x00000040U 239f8919bdaSduboff #define MEAR_MDDIR 0x00000020U 240f8919bdaSduboff #define MEAR_MDIO 0x00000010U 241f8919bdaSduboff #define MEAR_MDIO_SHIFT 4 242f8919bdaSduboff 243f8919bdaSduboff /* PCI Test Control register */ 244f8919bdaSduboff #define DISCARD_TEST 0x40000000U /* Discard timer test mode */ 245f8919bdaSduboff 246f8919bdaSduboff /* Interrupt status register */ 247f8919bdaSduboff #define ISR_WAKEEVT 0x10000000U /* sis900 */ 248f8919bdaSduboff #define ISR_PAUSE_END 0x08000000U /* sis900 */ 249f8919bdaSduboff #define ISR_PAUSE_ST 0x04000000U /* sis900 */ 250f8919bdaSduboff #define ISR_TXRCMP 0x02000000U 251f8919bdaSduboff #define ISR_RXRCMP 0x01000000U 252f8919bdaSduboff #define ISR_DPERR 0x00800000U /* Detected parity error */ 253f8919bdaSduboff #define ISR_SSERR 0x00400000U /* Signaled system error */ 254f8919bdaSduboff #define ISR_RMABT 0x00200000U /* Received master abort */ 255f8919bdaSduboff #define ISR_RTABT 0x00100000U /* Received target abort */ 256f8919bdaSduboff #define ISR_RXSOVR 0x00010000U /* Received status FIFO overrun */ 257f8919bdaSduboff #define ISR_HIBERR 0x00008000U 258f8919bdaSduboff #define ISR_SWI 0x00001000U 259f8919bdaSduboff #define ISR_TXURN 0x00000400U 260f8919bdaSduboff #define ISR_TXIDLE 0x00000200U 261f8919bdaSduboff #define ISR_TXERR 0x00000100U 262f8919bdaSduboff #define ISR_TXDESC 0x00000080U 263f8919bdaSduboff #define ISR_TXOK 0x00000040U 264f8919bdaSduboff #define ISR_RXORN 0x00000020U 265f8919bdaSduboff #define ISR_RXIDLE 0x00000010U 266f8919bdaSduboff #define ISR_RXEARLY 0x00000008U 267f8919bdaSduboff #define ISR_RXERR 0x00000004U 268f8919bdaSduboff #define ISR_RXDESC 0x00000002U 269f8919bdaSduboff #define ISR_RXOK 0x00000001U 270f8919bdaSduboff 271f8919bdaSduboff #define INTR_BITS \ 272f8919bdaSduboff "\020" \ 273f8919bdaSduboff "\035WakeEvt" \ 274f8919bdaSduboff "\034PauseEnd" \ 275f8919bdaSduboff "\033PauseST" \ 276f8919bdaSduboff "\032TXRCMP" \ 277f8919bdaSduboff "\031RXRCMP" \ 278f8919bdaSduboff "\030DPErr" \ 279f8919bdaSduboff "\027SSErr" \ 280f8919bdaSduboff "\026RMAbt" \ 281f8919bdaSduboff "\025RTAbt" \ 282f8919bdaSduboff "\021RxSOVR" \ 283f8919bdaSduboff "\020HIBErr" \ 284f8919bdaSduboff "\015SWI" \ 285f8919bdaSduboff "\013TxUrn" \ 286f8919bdaSduboff "\012TxIdle" \ 287f8919bdaSduboff "\011TxErr" \ 288f8919bdaSduboff "\010TxDesc" \ 289f8919bdaSduboff "\007TxOk" \ 290f8919bdaSduboff "\006RxORN" \ 291f8919bdaSduboff "\005RxIdle" \ 292f8919bdaSduboff "\004RxEarly" \ 293f8919bdaSduboff "\003RxErr" \ 294f8919bdaSduboff "\002RxDesc" \ 295f8919bdaSduboff "\001RxOk" 296f8919bdaSduboff 297f8919bdaSduboff 298f8919bdaSduboff /* Interrupt enable reigster */ 299f8919bdaSduboff #define IER_IE 0x00000001 /* Interrupt enable */ 300f8919bdaSduboff 301f8919bdaSduboff /* Enhanced PHY acces register */ 302f8919bdaSduboff #define ENPHY_DATA 0xffff0000U /* data */ 303f8919bdaSduboff #define ENPHY_DATA_SHIFT 16 304f8919bdaSduboff #define ENPHY_ADDR 0x0000f800U /* phy address */ 305f8919bdaSduboff #define ENPHY_ADDR_SHIFT 11 306f8919bdaSduboff #define ENPHY_OFFSET 0x000007c0U /* offset */ 307f8919bdaSduboff #define ENPHY_OFFSET_SHIFT 6 308f8919bdaSduboff #define ENPHY_RDCMD 0x00000020U /* read */ 309f8919bdaSduboff #define ENPHY_ACCESS 0x00000010U /* busy */ 310f8919bdaSduboff 311f8919bdaSduboff 312f8919bdaSduboff /* Transmit configuration register */ 313f8919bdaSduboff #define TXCFG_CSI 0x80000000U /* carrier sense ignore */ 314f8919bdaSduboff #define TXCFG_HBI 0x40000000U /* heart beat ignore */ 315f8919bdaSduboff #define TXCFG_MLB 0x20000000U /* MAC loop back */ 316f8919bdaSduboff #define TXCFG_ATP 0x10000000U /* Automatic transmit padding */ 317f8919bdaSduboff #define TXCFG_MXDMA 0x00700000U /* max dma burst size */ 318f8919bdaSduboff #define TXCFG_MXDMA_SHIFT 20 319f8919bdaSduboff #define TXCFG_MXDMA_512 (0U << TXCFG_MXDMA_SHIFT) 320f8919bdaSduboff #define TXCFG_MXDMA_4 (1U << TXCFG_MXDMA_SHIFT) 321f8919bdaSduboff #define TXCFG_MXDMA_8 (2U << TXCFG_MXDMA_SHIFT) 322f8919bdaSduboff #define TXCFG_MXDMA_16 (3U << TXCFG_MXDMA_SHIFT) 323f8919bdaSduboff #define TXCFG_MXDMA_32 (4U << TXCFG_MXDMA_SHIFT) 324f8919bdaSduboff #define TXCFG_MXDMA_64 (5U << TXCFG_MXDMA_SHIFT) 325f8919bdaSduboff #define TXCFG_MXDMA_128 (6U << TXCFG_MXDMA_SHIFT) 326f8919bdaSduboff #define TXCFG_MXDMA_256 (7U << TXCFG_MXDMA_SHIFT) 327f8919bdaSduboff #define TXCFG_FLTH 0x00003f00U /* Tx fill threshold */ 328f8919bdaSduboff #define TXCFG_FLTH_SHIFT 8 329f8919bdaSduboff #define TXCFG_DRTH 0x0000003fU /* Tx drain threshold */ 330f8919bdaSduboff 331f8919bdaSduboff #define TXFIFOSIZE 2048U 332f8919bdaSduboff #define TXCFG_FIFO_UNIT 32U 333f8919bdaSduboff 334f8919bdaSduboff #define TXCFG_BITS "\020\040CSI\037HBI\036MLB\035ATP" 335f8919bdaSduboff 336f8919bdaSduboff /* RXCFG:43 Reveive configuration register */ 337f8919bdaSduboff #define RXCFG_AEP 0x80000000U /* accept error packets */ 338f8919bdaSduboff #define RXCFG_ARP 0x40000000U /* accept runt packets */ 339f8919bdaSduboff #define RXCFG_ATX 0x10000000U /* accept transmit packets */ 340f8919bdaSduboff #define RXCFG_AJAB 0x08000000U /* accept jabber packets */ 341f8919bdaSduboff #define RXCFG_ALP_DP83815 0x08000000U /* accept long pakets */ 342f8919bdaSduboff #define RXCFG_MXDMA 0x00700000U /* max dma burst size */ 343f8919bdaSduboff #define RXCFG_MXDMA_SHIFT (20) 344f8919bdaSduboff #define RXCFG_MXDMA_512 (0U << RXCFG_MXDMA_SHIFT) 345f8919bdaSduboff #define RXCFG_MXDMA_4 (1U << RXCFG_MXDMA_SHIFT) 346f8919bdaSduboff #define RXCFG_MXDMA_8 (2U << RXCFG_MXDMA_SHIFT) 347f8919bdaSduboff #define RXCFG_MXDMA_16 (3U << RXCFG_MXDMA_SHIFT) 348f8919bdaSduboff #define RXCFG_MXDMA_32 (4U << RXCFG_MXDMA_SHIFT) 349f8919bdaSduboff #define RXCFG_MXDMA_64 (5U << RXCFG_MXDMA_SHIFT) 350f8919bdaSduboff #define RXCFG_MXDMA_128 (6U << RXCFG_MXDMA_SHIFT) 351f8919bdaSduboff #define RXCFG_MXDMA_256 (7U << RXCFG_MXDMA_SHIFT) 352f8919bdaSduboff #define RXCFG_DRTH 0x0000003eU /* Rx drain threshold */ 353f8919bdaSduboff #define RXCFG_DRTH_SHIFT 1 354f8919bdaSduboff 355f8919bdaSduboff #define RXFIFOSIZE 2048U 356f8919bdaSduboff #define RXCFG_FIFO_UNIT 8U 357f8919bdaSduboff 358f8919bdaSduboff #define RXCFG_BITS "\020\040AEP\037ARP\035ATX\034AJAB" 359f8919bdaSduboff 360f8919bdaSduboff 361f8919bdaSduboff /* FLWCRL:0x38 Flow Control register */ 362f8919bdaSduboff #define FLOWCTL_PAUSE 0x00000002U /* PAUSE flag */ 363f8919bdaSduboff #define FLOWCTL_FLOWEN 0x00000001U /* flow control enable */ 364f8919bdaSduboff 365f8919bdaSduboff #define FLOWCTL_BITS "\020\002PAUSE\001FLOWEN" 366f8919bdaSduboff 367f8919bdaSduboff /* CCSR:0x3c Clock run Control status register */ 368f8919bdaSduboff #define CCSR_PMESTS 0x00008000U 369f8919bdaSduboff #define CCSR_PMEEN 0x00000100U 370f8919bdaSduboff #define CCSR_CLKRUN_EN 0x00000001U 371f8919bdaSduboff 372f8919bdaSduboff /* PCR:0x44 Pause control/status register (DP83815) */ 373f8919bdaSduboff #define PCR_PSEN 0x80000000U /* Pause Enable */ 374f8919bdaSduboff #define PCR_PS_MCAST 0x40000000U /* Pause on multicast */ 375f8919bdaSduboff #define PCR_PS_DA 0x20000000U /* Pause on DA */ 376f8919bdaSduboff #define PCR_PS_ACT 0x00800000U /* Pause active */ 377f8919bdaSduboff #define PCR_PS_RCVD 0x00400000U /* Pause frame receved */ 378f8919bdaSduboff #define PCR_PSNEG 0x00200000U /* Pause negotiated */ 379f8919bdaSduboff #define PCR_MLD_EN 0x00010000U /* Manual load enable */ 380f8919bdaSduboff #define PCR_PAUSE_CNT 0x0000ffffU /* Pause counter value */ 381f8919bdaSduboff 382f8919bdaSduboff #define PCR_BITS \ 383f8919bdaSduboff "\020" \ 384f8919bdaSduboff "\040PCR_PSEN" \ 385f8919bdaSduboff "\037PCR_PS_MCAST" \ 386f8919bdaSduboff "\036PCR_PS_DA" \ 387f8919bdaSduboff "\030PCR_PS_ACT" \ 388f8919bdaSduboff "\027PCR_PS_RCVD" \ 389f8919bdaSduboff "\026PCR_PSNEG" \ 390f8919bdaSduboff "\021PCR_MLD_EN" 391f8919bdaSduboff 392f8919bdaSduboff /* RFCR:0x48 Receive filter control register */ 393f8919bdaSduboff #define RFCR_RFEN 0x80000000U /* receive filter enable */ 394f8919bdaSduboff #define RFCR_AAB 0x40000000U /* accept all broadcast */ 395f8919bdaSduboff #define RFCR_AAM 0x20000000U /* accept all multicast */ 396f8919bdaSduboff #define RFCR_AAP 0x10000000U /* accept all physical */ 397f8919bdaSduboff #define RFCR_APM_DP83815 0x08000000U /* accept perfect match */ 398f8919bdaSduboff #define RFCR_APAT_DP83815 0x07800000U /* accept on pattern match */ 399f8919bdaSduboff #define RFCR_APAT_SHIFT 23 /* pattern match base */ 400f8919bdaSduboff #define RFCR_AARP_DP83815 0x00400000U /* accept arp packets */ 401f8919bdaSduboff #define RFCR_MHEN_DP83815 0x00200000U /* multicast hash enable */ 402f8919bdaSduboff #define RFCR_UHEN_DP83815 0x00100000U /* unicast hash enable */ 403f8919bdaSduboff #define RFCR_ULM_DP83815 0x00080000U /* U/L bit mask */ 404f8919bdaSduboff #define RFCR_RFADDR_SIS900 0x000f0000U /* receive filter address */ 405f8919bdaSduboff #define RFCR_RFADDR_SHIFT_SIS900 16 406f8919bdaSduboff #define RFCR_RFADDR_DP83815 0x000003ffU 407f8919bdaSduboff #define RFCR_RFADDR_SHIFT_DP83815 0 408f8919bdaSduboff 409f8919bdaSduboff /* Receive filter offset */ 410f8919bdaSduboff #define RFADDR_MAC_SIS900 0U 411f8919bdaSduboff #define RFADDR_MULTICAST_SIS900 4U 412f8919bdaSduboff 413f8919bdaSduboff #define RFADDR_MAC_DP83815 0x000U 414f8919bdaSduboff #define RFADDR_PCOUNT01_DP83815 0x006U 415f8919bdaSduboff #define RFADDR_PCOUNT23_DP83815 0x008U 416f8919bdaSduboff #define RFADDR_MULTICAST_DP83815 0x200U 417f8919bdaSduboff #define RFADDR_PMATCH0_DP83815 0x280U 418f8919bdaSduboff #define RFADDR_PMATCH1_DP83815 0x282U 419f8919bdaSduboff #define RFADDR_PMATCH2_DP83815 0x300U 420f8919bdaSduboff #define RFADDR_PMATCH3_DP83815 0x302U 421f8919bdaSduboff 422f8919bdaSduboff /* Receive filter data register */ 423f8919bdaSduboff 424f8919bdaSduboff /* dp83815 Silicon revision register */ 425f8919bdaSduboff #define SRR_REV 0x0000ffffU 426*23d366e3Sduboff #define SRR_REV_DP83815CVNG 0x0302U 427*23d366e3Sduboff #define SRR_REV_DP83815DVNG 0x0403U 428*23d366e3Sduboff #define SRR_REV_DP83816AVNG 0x0505U 429f8919bdaSduboff 430f8919bdaSduboff /* sis900 revisions */ 431f8919bdaSduboff #define SIS630A_900_REV 0x80 432f8919bdaSduboff #define SIS630E_900_REV 0x81 433f8919bdaSduboff #define SIS630S_900_REV 0x82 434f8919bdaSduboff #define SIS630EA1_900_REV 0x83 435f8919bdaSduboff #define SIS630ET_900_REV 0x84 436f8919bdaSduboff #define SIS635A_900_REV 0x90 437f8919bdaSduboff #define SIS962_900_REV 0X91 438f8919bdaSduboff #define SIS900B_900_REV 0x03 439f8919bdaSduboff 440f8919bdaSduboff #define SIS630A0 0x00 441f8919bdaSduboff #define SIS630A1 0x01 442f8919bdaSduboff #define SIS630B0 0x10 443f8919bdaSduboff #define SIS630B1 0x11 444f8919bdaSduboff 445f8919bdaSduboff 446f8919bdaSduboff #endif /* _SFEREG_H_ */ 447