1f8919bdaSduboff /*
2f8919bdaSduboff * sfe.c : DP83815/DP83816/SiS900 Fast Ethernet MAC driver for Solaris
3f8919bdaSduboff *
423d366e3Sduboff * Copyright (c) 2002-2008 Masayuki Murayama. All rights reserved.
5f8919bdaSduboff *
6f8919bdaSduboff * Redistribution and use in source and binary forms, with or without
7f8919bdaSduboff * modification, are permitted provided that the following conditions are met:
8f8919bdaSduboff *
9f8919bdaSduboff * 1. Redistributions of source code must retain the above copyright notice,
10f8919bdaSduboff * this list of conditions and the following disclaimer.
11f8919bdaSduboff *
12f8919bdaSduboff * 2. Redistributions in binary form must reproduce the above copyright notice,
13f8919bdaSduboff * this list of conditions and the following disclaimer in the documentation
14f8919bdaSduboff * and/or other materials provided with the distribution.
15f8919bdaSduboff *
16f8919bdaSduboff * 3. Neither the name of the author nor the names of its contributors may be
17f8919bdaSduboff * used to endorse or promote products derived from this software without
18f8919bdaSduboff * specific prior written permission.
19f8919bdaSduboff *
20f8919bdaSduboff * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21f8919bdaSduboff * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22f8919bdaSduboff * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23f8919bdaSduboff * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24f8919bdaSduboff * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25f8919bdaSduboff * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26f8919bdaSduboff * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
27f8919bdaSduboff * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28f8919bdaSduboff * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29f8919bdaSduboff * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30f8919bdaSduboff * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31f8919bdaSduboff * DAMAGE.
32f8919bdaSduboff */
33f8919bdaSduboff
3419397407SSherry Moore /*
3553560dfaSSherry Moore * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
3619397407SSherry Moore * Use is subject to license terms.
3719397407SSherry Moore */
38f8919bdaSduboff
39f8919bdaSduboff /*
40f8919bdaSduboff * System Header files.
41f8919bdaSduboff */
42f8919bdaSduboff #include <sys/types.h>
43f8919bdaSduboff #include <sys/conf.h>
44f8919bdaSduboff #include <sys/debug.h>
45f8919bdaSduboff #include <sys/kmem.h>
46f8919bdaSduboff #include <sys/modctl.h>
47f8919bdaSduboff #include <sys/errno.h>
48f8919bdaSduboff #include <sys/ddi.h>
49f8919bdaSduboff #include <sys/sunddi.h>
50f8919bdaSduboff #include <sys/byteorder.h>
51f8919bdaSduboff #include <sys/ethernet.h>
52f8919bdaSduboff #include <sys/pci.h>
53f8919bdaSduboff
54f8919bdaSduboff #include "sfe_mii.h"
55f8919bdaSduboff #include "sfe_util.h"
56f8919bdaSduboff #include "sfereg.h"
57f8919bdaSduboff
5853560dfaSSherry Moore char ident[] = "sis900/dp83815 driver v" "2.6.1t30os";
59f8919bdaSduboff
60f8919bdaSduboff /* Debugging support */
61f8919bdaSduboff #ifdef DEBUG_LEVEL
62f8919bdaSduboff static int sfe_debug = DEBUG_LEVEL;
63f8919bdaSduboff #if DEBUG_LEVEL > 4
64f8919bdaSduboff #define CONS "^"
65f8919bdaSduboff #else
66f8919bdaSduboff #define CONS "!"
67f8919bdaSduboff #endif
68f8919bdaSduboff #define DPRINTF(n, args) if (sfe_debug > (n)) cmn_err args
69f8919bdaSduboff #else
70f8919bdaSduboff #define CONS "!"
71f8919bdaSduboff #define DPRINTF(n, args)
72f8919bdaSduboff #endif
73f8919bdaSduboff
74f8919bdaSduboff /*
75f8919bdaSduboff * Useful macros and typedefs
76f8919bdaSduboff */
77f8919bdaSduboff #define ONESEC (drv_usectohz(1*1000000))
78f8919bdaSduboff #define ROUNDUP2(x, a) (((x) + (a) - 1) & ~((a) - 1))
79f8919bdaSduboff
80f8919bdaSduboff /*
81f8919bdaSduboff * Our configuration
82f8919bdaSduboff */
83f8919bdaSduboff #define MAXTXFRAGS 1
84f8919bdaSduboff #define MAXRXFRAGS 1
85f8919bdaSduboff
86f8919bdaSduboff #ifndef TX_BUF_SIZE
87f8919bdaSduboff #define TX_BUF_SIZE 64
88f8919bdaSduboff #endif
89f8919bdaSduboff #ifndef TX_RING_SIZE
90f8919bdaSduboff #if MAXTXFRAGS == 1
91f8919bdaSduboff #define TX_RING_SIZE TX_BUF_SIZE
92f8919bdaSduboff #else
93f8919bdaSduboff #define TX_RING_SIZE (TX_BUF_SIZE * 4)
94f8919bdaSduboff #endif
95f8919bdaSduboff #endif
96f8919bdaSduboff
97f8919bdaSduboff #ifndef RX_BUF_SIZE
98f8919bdaSduboff #define RX_BUF_SIZE 256
99f8919bdaSduboff #endif
100f8919bdaSduboff #ifndef RX_RING_SIZE
101f8919bdaSduboff #define RX_RING_SIZE RX_BUF_SIZE
102f8919bdaSduboff #endif
103f8919bdaSduboff
104f8919bdaSduboff #define OUR_INTR_BITS \
105f8919bdaSduboff (ISR_DPERR | ISR_SSERR | ISR_RMABT | ISR_RTABT | ISR_RXSOVR | \
106f8919bdaSduboff ISR_TXURN | ISR_TXDESC | ISR_TXERR | \
107f8919bdaSduboff ISR_RXORN | ISR_RXIDLE | ISR_RXOK | ISR_RXERR)
108f8919bdaSduboff
109f8919bdaSduboff #define USE_MULTICAST_HASHTBL
110f8919bdaSduboff
111f8919bdaSduboff static int sfe_tx_copy_thresh = 256;
112f8919bdaSduboff static int sfe_rx_copy_thresh = 256;
113f8919bdaSduboff
114f8919bdaSduboff /* special PHY registers for SIS900 */
115f8919bdaSduboff #define MII_CONFIG1 0x0010
116f8919bdaSduboff #define MII_CONFIG2 0x0011
117f8919bdaSduboff #define MII_MASK 0x0013
118f8919bdaSduboff #define MII_RESV 0x0014
119f8919bdaSduboff
120f8919bdaSduboff #define PHY_MASK 0xfffffff0
121f8919bdaSduboff #define PHY_SIS900_INTERNAL 0x001d8000
122f8919bdaSduboff #define PHY_ICS1893 0x0015f440
123f8919bdaSduboff
124f8919bdaSduboff
125f8919bdaSduboff #define SFE_DESC_SIZE 16 /* including pads rounding up to power of 2 */
126f8919bdaSduboff
127f8919bdaSduboff /*
128f8919bdaSduboff * Supported chips
129f8919bdaSduboff */
130f8919bdaSduboff struct chip_info {
131f8919bdaSduboff uint16_t venid;
132f8919bdaSduboff uint16_t devid;
133f8919bdaSduboff char *chip_name;
134f8919bdaSduboff int chip_type;
135f8919bdaSduboff #define CHIPTYPE_DP83815 0
136f8919bdaSduboff #define CHIPTYPE_SIS900 1
137f8919bdaSduboff };
138f8919bdaSduboff
139f8919bdaSduboff /*
140f8919bdaSduboff * Chip dependent MAC state
141f8919bdaSduboff */
142f8919bdaSduboff struct sfe_dev {
143f8919bdaSduboff /* misc HW information */
144f8919bdaSduboff struct chip_info *chip;
145f8919bdaSduboff uint32_t our_intr_bits;
14623d366e3Sduboff uint32_t isr_pended;
147f8919bdaSduboff uint32_t cr;
148f8919bdaSduboff uint_t tx_drain_threshold;
149f8919bdaSduboff uint_t tx_fill_threshold;
150f8919bdaSduboff uint_t rx_drain_threshold;
151f8919bdaSduboff uint_t rx_fill_threshold;
152f8919bdaSduboff uint8_t revid; /* revision from PCI configuration */
153f8919bdaSduboff boolean_t (*get_mac_addr)(struct gem_dev *);
154f8919bdaSduboff uint8_t mac_addr[ETHERADDRL];
155f8919bdaSduboff uint8_t bridge_revid;
156f8919bdaSduboff };
157f8919bdaSduboff
158f8919bdaSduboff /*
159f8919bdaSduboff * Hardware information
160f8919bdaSduboff */
161f8919bdaSduboff struct chip_info sfe_chiptbl[] = {
162f8919bdaSduboff { 0x1039, 0x0900, "SiS900", CHIPTYPE_SIS900, },
163f8919bdaSduboff { 0x100b, 0x0020, "DP83815/83816", CHIPTYPE_DP83815, },
164f8919bdaSduboff { 0x1039, 0x7016, "SiS7016", CHIPTYPE_SIS900, },
165f8919bdaSduboff };
166f8919bdaSduboff #define CHIPTABLESIZE (sizeof (sfe_chiptbl)/sizeof (struct chip_info))
167f8919bdaSduboff
168f8919bdaSduboff /* ======================================================== */
169f8919bdaSduboff
170f8919bdaSduboff /* mii operations */
171f8919bdaSduboff static void sfe_mii_sync_dp83815(struct gem_dev *);
172f8919bdaSduboff static void sfe_mii_sync_sis900(struct gem_dev *);
173f8919bdaSduboff static uint16_t sfe_mii_read_dp83815(struct gem_dev *, uint_t);
174f8919bdaSduboff static uint16_t sfe_mii_read_sis900(struct gem_dev *, uint_t);
175f8919bdaSduboff static void sfe_mii_write_dp83815(struct gem_dev *, uint_t, uint16_t);
176f8919bdaSduboff static void sfe_mii_write_sis900(struct gem_dev *, uint_t, uint16_t);
177*3b8e6442SToomas Soome static void sfe_set_eq_sis630(struct gem_dev *);
178f8919bdaSduboff /* nic operations */
179f8919bdaSduboff static int sfe_reset_chip_sis900(struct gem_dev *);
180f8919bdaSduboff static int sfe_reset_chip_dp83815(struct gem_dev *);
181f8919bdaSduboff static int sfe_init_chip(struct gem_dev *);
182f8919bdaSduboff static int sfe_start_chip(struct gem_dev *);
183f8919bdaSduboff static int sfe_stop_chip(struct gem_dev *);
184f8919bdaSduboff static int sfe_set_media(struct gem_dev *);
185f8919bdaSduboff static int sfe_set_rx_filter_dp83815(struct gem_dev *);
186f8919bdaSduboff static int sfe_set_rx_filter_sis900(struct gem_dev *);
187f8919bdaSduboff static int sfe_get_stats(struct gem_dev *);
188f8919bdaSduboff static int sfe_attach_chip(struct gem_dev *);
189f8919bdaSduboff
190f8919bdaSduboff /* descriptor operations */
191f8919bdaSduboff static int sfe_tx_desc_write(struct gem_dev *dp, int slot,
192f8919bdaSduboff ddi_dma_cookie_t *dmacookie, int frags, uint64_t flags);
193f8919bdaSduboff static void sfe_tx_start(struct gem_dev *dp, int startslot, int nslot);
194f8919bdaSduboff static void sfe_rx_desc_write(struct gem_dev *dp, int slot,
195f8919bdaSduboff ddi_dma_cookie_t *dmacookie, int frags);
196f8919bdaSduboff static uint_t sfe_tx_desc_stat(struct gem_dev *dp, int slot, int ndesc);
197f8919bdaSduboff static uint64_t sfe_rx_desc_stat(struct gem_dev *dp, int slot, int ndesc);
198f8919bdaSduboff
199f8919bdaSduboff static void sfe_tx_desc_init(struct gem_dev *dp, int slot);
200f8919bdaSduboff static void sfe_rx_desc_init(struct gem_dev *dp, int slot);
201f8919bdaSduboff static void sfe_tx_desc_clean(struct gem_dev *dp, int slot);
202f8919bdaSduboff static void sfe_rx_desc_clean(struct gem_dev *dp, int slot);
203f8919bdaSduboff
204f8919bdaSduboff /* interrupt handler */
205f8919bdaSduboff static uint_t sfe_interrupt(struct gem_dev *dp);
206f8919bdaSduboff
207f8919bdaSduboff /* ======================================================== */
208f8919bdaSduboff
209f8919bdaSduboff /* mapping attributes */
210f8919bdaSduboff /* Data access requirements. */
211f8919bdaSduboff static struct ddi_device_acc_attr sfe_dev_attr = {
212f8919bdaSduboff DDI_DEVICE_ATTR_V0,
213f8919bdaSduboff DDI_STRUCTURE_LE_ACC,
214f8919bdaSduboff DDI_STRICTORDER_ACC
215f8919bdaSduboff };
216f8919bdaSduboff
217f8919bdaSduboff /* On sparc, Buffers should be native endian for speed */
218f8919bdaSduboff static struct ddi_device_acc_attr sfe_buf_attr = {
219f8919bdaSduboff DDI_DEVICE_ATTR_V0,
220f8919bdaSduboff DDI_NEVERSWAP_ACC, /* native endianness */
221f8919bdaSduboff DDI_STRICTORDER_ACC
222f8919bdaSduboff };
223f8919bdaSduboff
224f8919bdaSduboff static ddi_dma_attr_t sfe_dma_attr_buf = {
225f8919bdaSduboff DMA_ATTR_V0, /* dma_attr_version */
226f8919bdaSduboff 0, /* dma_attr_addr_lo */
227f8919bdaSduboff 0xffffffffull, /* dma_attr_addr_hi */
228f8919bdaSduboff 0x00000fffull, /* dma_attr_count_max */
229f8919bdaSduboff 0, /* patched later */ /* dma_attr_align */
230f8919bdaSduboff 0x000003fc, /* dma_attr_burstsizes */
231f8919bdaSduboff 1, /* dma_attr_minxfer */
232f8919bdaSduboff 0x00000fffull, /* dma_attr_maxxfer */
233f8919bdaSduboff 0xffffffffull, /* dma_attr_seg */
234f8919bdaSduboff 0, /* patched later */ /* dma_attr_sgllen */
235f8919bdaSduboff 1, /* dma_attr_granular */
236f8919bdaSduboff 0 /* dma_attr_flags */
237f8919bdaSduboff };
238f8919bdaSduboff
239f8919bdaSduboff static ddi_dma_attr_t sfe_dma_attr_desc = {
240f8919bdaSduboff DMA_ATTR_V0, /* dma_attr_version */
241f8919bdaSduboff 16, /* dma_attr_addr_lo */
242f8919bdaSduboff 0xffffffffull, /* dma_attr_addr_hi */
243f8919bdaSduboff 0xffffffffull, /* dma_attr_count_max */
244f8919bdaSduboff 16, /* dma_attr_align */
245f8919bdaSduboff 0x000003fc, /* dma_attr_burstsizes */
246f8919bdaSduboff 1, /* dma_attr_minxfer */
247f8919bdaSduboff 0xffffffffull, /* dma_attr_maxxfer */
248f8919bdaSduboff 0xffffffffull, /* dma_attr_seg */
249f8919bdaSduboff 1, /* dma_attr_sgllen */
250f8919bdaSduboff 1, /* dma_attr_granular */
251f8919bdaSduboff 0 /* dma_attr_flags */
252f8919bdaSduboff };
253f8919bdaSduboff
254f8919bdaSduboff uint32_t sfe_use_pcimemspace = 0;
255f8919bdaSduboff
256f8919bdaSduboff /* ======================================================== */
257f8919bdaSduboff /*
258f8919bdaSduboff * HW manipulation routines
259f8919bdaSduboff */
260f8919bdaSduboff /* ======================================================== */
261f8919bdaSduboff
262f8919bdaSduboff #define SFE_EEPROM_DELAY(dp) \
263f8919bdaSduboff { (void) INL(dp, EROMAR); (void) INL(dp, EROMAR); }
264f8919bdaSduboff #define EE_CMD_READ 6
265f8919bdaSduboff #define EE_CMD_SHIFT 6
266f8919bdaSduboff
267f8919bdaSduboff static uint16_t
sfe_read_eeprom(struct gem_dev * dp,uint_t offset)268f8919bdaSduboff sfe_read_eeprom(struct gem_dev *dp, uint_t offset)
269f8919bdaSduboff {
270f8919bdaSduboff int eedi;
271f8919bdaSduboff int i;
272f8919bdaSduboff uint16_t ret;
273f8919bdaSduboff
274f8919bdaSduboff /* ensure de-assert chip select */
275f8919bdaSduboff OUTL(dp, EROMAR, 0);
276f8919bdaSduboff SFE_EEPROM_DELAY(dp);
277f8919bdaSduboff OUTL(dp, EROMAR, EROMAR_EESK);
278f8919bdaSduboff SFE_EEPROM_DELAY(dp);
279f8919bdaSduboff
280f8919bdaSduboff /* assert chip select */
281f8919bdaSduboff offset |= EE_CMD_READ << EE_CMD_SHIFT;
282f8919bdaSduboff
283f8919bdaSduboff for (i = 8; i >= 0; i--) {
284f8919bdaSduboff /* make command */
285f8919bdaSduboff eedi = ((offset >> i) & 1) << EROMAR_EEDI_SHIFT;
286f8919bdaSduboff
287f8919bdaSduboff /* send 1 bit */
288f8919bdaSduboff OUTL(dp, EROMAR, EROMAR_EECS | eedi);
289f8919bdaSduboff SFE_EEPROM_DELAY(dp);
290f8919bdaSduboff OUTL(dp, EROMAR, EROMAR_EECS | eedi | EROMAR_EESK);
291f8919bdaSduboff SFE_EEPROM_DELAY(dp);
292f8919bdaSduboff }
293f8919bdaSduboff
294f8919bdaSduboff OUTL(dp, EROMAR, EROMAR_EECS);
295f8919bdaSduboff
296f8919bdaSduboff ret = 0;
297f8919bdaSduboff for (i = 0; i < 16; i++) {
298f8919bdaSduboff /* Get 1 bit */
299f8919bdaSduboff OUTL(dp, EROMAR, EROMAR_EECS);
300f8919bdaSduboff SFE_EEPROM_DELAY(dp);
301f8919bdaSduboff OUTL(dp, EROMAR, EROMAR_EECS | EROMAR_EESK);
302f8919bdaSduboff SFE_EEPROM_DELAY(dp);
303f8919bdaSduboff
304f8919bdaSduboff ret = (ret << 1) | ((INL(dp, EROMAR) >> EROMAR_EEDO_SHIFT) & 1);
305f8919bdaSduboff }
306f8919bdaSduboff
307f8919bdaSduboff OUTL(dp, EROMAR, 0);
308f8919bdaSduboff SFE_EEPROM_DELAY(dp);
309f8919bdaSduboff
310f8919bdaSduboff return (ret);
311f8919bdaSduboff }
312f8919bdaSduboff #undef SFE_EEPROM_DELAY
313f8919bdaSduboff
314f8919bdaSduboff static boolean_t
sfe_get_mac_addr_dp83815(struct gem_dev * dp)315f8919bdaSduboff sfe_get_mac_addr_dp83815(struct gem_dev *dp)
316f8919bdaSduboff {
317f8919bdaSduboff uint8_t *mac;
318f8919bdaSduboff uint_t val;
319f8919bdaSduboff int i;
320f8919bdaSduboff
321f8919bdaSduboff #define BITSET(p, ix, v) (p)[(ix)/8] |= ((v) ? 1 : 0) << ((ix) & 0x7)
322f8919bdaSduboff
323f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
324f8919bdaSduboff
325f8919bdaSduboff mac = dp->dev_addr.ether_addr_octet;
326f8919bdaSduboff
327f8919bdaSduboff /* first of all, clear MAC address buffer */
328f8919bdaSduboff bzero(mac, ETHERADDRL);
329f8919bdaSduboff
330f8919bdaSduboff /* get bit 0 */
331f8919bdaSduboff val = sfe_read_eeprom(dp, 0x6);
332f8919bdaSduboff BITSET(mac, 0, val & 1);
333f8919bdaSduboff
334f8919bdaSduboff /* get bit 1 - 16 */
335f8919bdaSduboff val = sfe_read_eeprom(dp, 0x7);
336f8919bdaSduboff for (i = 0; i < 16; i++) {
337f8919bdaSduboff BITSET(mac, 1 + i, val & (1 << (15 - i)));
338f8919bdaSduboff }
339f8919bdaSduboff
340f8919bdaSduboff /* get bit 17 - 32 */
341f8919bdaSduboff val = sfe_read_eeprom(dp, 0x8);
342f8919bdaSduboff for (i = 0; i < 16; i++) {
343f8919bdaSduboff BITSET(mac, 17 + i, val & (1 << (15 - i)));
344f8919bdaSduboff }
345f8919bdaSduboff
346f8919bdaSduboff /* get bit 33 - 47 */
347f8919bdaSduboff val = sfe_read_eeprom(dp, 0x9);
348f8919bdaSduboff for (i = 0; i < 15; i++) {
349f8919bdaSduboff BITSET(mac, 33 + i, val & (1 << (15 - i)));
350f8919bdaSduboff }
351f8919bdaSduboff
352f8919bdaSduboff return (B_TRUE);
353f8919bdaSduboff #undef BITSET
354f8919bdaSduboff }
355f8919bdaSduboff
356f8919bdaSduboff static boolean_t
sfe_get_mac_addr_sis900(struct gem_dev * dp)357f8919bdaSduboff sfe_get_mac_addr_sis900(struct gem_dev *dp)
358f8919bdaSduboff {
359f8919bdaSduboff uint_t val;
360f8919bdaSduboff int i;
361f8919bdaSduboff uint8_t *mac;
362f8919bdaSduboff
363f8919bdaSduboff mac = dp->dev_addr.ether_addr_octet;
364f8919bdaSduboff
365f8919bdaSduboff for (i = 0; i < ETHERADDRL/2; i++) {
366f8919bdaSduboff val = sfe_read_eeprom(dp, 0x8 + i);
367f8919bdaSduboff *mac++ = (uint8_t)val;
368f8919bdaSduboff *mac++ = (uint8_t)(val >> 8);
369f8919bdaSduboff }
370f8919bdaSduboff
371f8919bdaSduboff return (B_TRUE);
372f8919bdaSduboff }
373f8919bdaSduboff
374f8919bdaSduboff static dev_info_t *
sfe_search_pci_dev_subr(dev_info_t * cur_node,int vendor_id,int device_id)375f8919bdaSduboff sfe_search_pci_dev_subr(dev_info_t *cur_node, int vendor_id, int device_id)
376f8919bdaSduboff {
377f8919bdaSduboff dev_info_t *child_id;
378f8919bdaSduboff dev_info_t *ret;
379f8919bdaSduboff int vid, did;
380f8919bdaSduboff
381f8919bdaSduboff if (cur_node == NULL) {
382f8919bdaSduboff return (NULL);
383f8919bdaSduboff }
384f8919bdaSduboff
385f8919bdaSduboff /* check brothers */
386f8919bdaSduboff do {
387f8919bdaSduboff vid = ddi_prop_get_int(DDI_DEV_T_ANY, cur_node,
388f8919bdaSduboff DDI_PROP_DONTPASS, "vendor-id", -1);
389f8919bdaSduboff did = ddi_prop_get_int(DDI_DEV_T_ANY, cur_node,
390f8919bdaSduboff DDI_PROP_DONTPASS, "device-id", -1);
391f8919bdaSduboff
392f8919bdaSduboff if (vid == vendor_id && did == device_id) {
393f8919bdaSduboff /* found */
394f8919bdaSduboff return (cur_node);
395f8919bdaSduboff }
396f8919bdaSduboff
397f8919bdaSduboff /* check children */
398f8919bdaSduboff if ((child_id = ddi_get_child(cur_node)) != NULL) {
399f8919bdaSduboff if ((ret = sfe_search_pci_dev_subr(child_id,
400f8919bdaSduboff vendor_id, device_id)) != NULL) {
401f8919bdaSduboff return (ret);
402f8919bdaSduboff }
403f8919bdaSduboff }
404f8919bdaSduboff
405f8919bdaSduboff } while ((cur_node = ddi_get_next_sibling(cur_node)) != NULL);
406f8919bdaSduboff
407f8919bdaSduboff /* not found */
408f8919bdaSduboff return (NULL);
409f8919bdaSduboff }
410f8919bdaSduboff
411f8919bdaSduboff static dev_info_t *
sfe_search_pci_dev(int vendor_id,int device_id)412f8919bdaSduboff sfe_search_pci_dev(int vendor_id, int device_id)
413f8919bdaSduboff {
414f8919bdaSduboff return (sfe_search_pci_dev_subr(ddi_root_node(), vendor_id, device_id));
415f8919bdaSduboff }
416f8919bdaSduboff
417f8919bdaSduboff static boolean_t
sfe_get_mac_addr_sis962(struct gem_dev * dp)418f8919bdaSduboff sfe_get_mac_addr_sis962(struct gem_dev *dp)
419f8919bdaSduboff {
420f8919bdaSduboff boolean_t ret;
421f8919bdaSduboff int i;
422f8919bdaSduboff
423f8919bdaSduboff ret = B_FALSE;
424f8919bdaSduboff
425f8919bdaSduboff /* rise request signal to access EEPROM */
426f8919bdaSduboff OUTL(dp, MEAR, EROMAR_EEREQ);
427f8919bdaSduboff for (i = 0; (INL(dp, MEAR) & EROMAR_EEGNT) == 0; i++) {
428f8919bdaSduboff if (i > 200) {
429f8919bdaSduboff /* failed to acquire eeprom */
430f8919bdaSduboff cmn_err(CE_NOTE,
431f8919bdaSduboff CONS "%s: failed to access eeprom", dp->name);
432f8919bdaSduboff goto x;
433f8919bdaSduboff }
434f8919bdaSduboff drv_usecwait(10);
435f8919bdaSduboff }
436f8919bdaSduboff ret = sfe_get_mac_addr_sis900(dp);
437f8919bdaSduboff x:
438f8919bdaSduboff /* release EEPROM */
439f8919bdaSduboff OUTL(dp, MEAR, EROMAR_EEDONE);
440f8919bdaSduboff
441f8919bdaSduboff return (ret);
442f8919bdaSduboff }
443f8919bdaSduboff
444f8919bdaSduboff static int
sfe_reset_chip_sis900(struct gem_dev * dp)445f8919bdaSduboff sfe_reset_chip_sis900(struct gem_dev *dp)
446f8919bdaSduboff {
447f8919bdaSduboff int i;
448f8919bdaSduboff uint32_t done;
449f8919bdaSduboff uint32_t val;
450f8919bdaSduboff struct sfe_dev *lp = dp->private;
451f8919bdaSduboff
452f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS "%s: %s called", dp->name, __func__));
453f8919bdaSduboff
454f8919bdaSduboff /* invalidate mac addr cache */
455f8919bdaSduboff bzero(lp->mac_addr, sizeof (lp->mac_addr));
456f8919bdaSduboff
457f8919bdaSduboff lp->cr = 0;
458f8919bdaSduboff
459f8919bdaSduboff /* inhibit interrupt */
460f8919bdaSduboff OUTL(dp, IMR, 0);
46123d366e3Sduboff lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits;
462f8919bdaSduboff
463915ebf8dSAlan Duboff OUTLINL(dp, RFCR, 0);
464f8919bdaSduboff
465f8919bdaSduboff OUTL(dp, CR, CR_RST | CR_TXR | CR_RXR);
466f8919bdaSduboff drv_usecwait(10);
467f8919bdaSduboff
468f8919bdaSduboff done = 0;
469f8919bdaSduboff for (i = 0; done != (ISR_TXRCMP | ISR_RXRCMP); i++) {
470f8919bdaSduboff if (i > 1000) {
471f8919bdaSduboff cmn_err(CE_WARN, "%s: chip reset timeout", dp->name);
472f8919bdaSduboff return (GEM_FAILURE);
473f8919bdaSduboff }
474f8919bdaSduboff done |= INL(dp, ISR) & (ISR_TXRCMP | ISR_RXRCMP);
475f8919bdaSduboff drv_usecwait(10);
476f8919bdaSduboff }
477f8919bdaSduboff
478f8919bdaSduboff if (lp->revid == SIS630ET_900_REV) {
479f8919bdaSduboff lp->cr |= CR_ACCESSMODE;
480f8919bdaSduboff OUTL(dp, CR, lp->cr | INL(dp, CR));
481f8919bdaSduboff }
482f8919bdaSduboff
483f8919bdaSduboff /* Configuration register: enable PCI parity */
484f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b",
485f8919bdaSduboff dp->name, INL(dp, CFG), CFG_BITS_SIS900));
48623d366e3Sduboff val = 0;
487f8919bdaSduboff if (lp->revid >= SIS635A_900_REV ||
488f8919bdaSduboff lp->revid == SIS900B_900_REV) {
489f8919bdaSduboff /* what is this ? */
490f8919bdaSduboff val |= CFG_RND_CNT;
491f8919bdaSduboff }
492f8919bdaSduboff OUTL(dp, CFG, val);
493f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", dp->name,
494f8919bdaSduboff INL(dp, CFG), CFG_BITS_SIS900));
495f8919bdaSduboff
496f8919bdaSduboff return (GEM_SUCCESS);
497f8919bdaSduboff }
498f8919bdaSduboff
499f8919bdaSduboff static int
sfe_reset_chip_dp83815(struct gem_dev * dp)500f8919bdaSduboff sfe_reset_chip_dp83815(struct gem_dev *dp)
501f8919bdaSduboff {
502f8919bdaSduboff int i;
50323d366e3Sduboff uint32_t val;
504f8919bdaSduboff struct sfe_dev *lp = dp->private;
505f8919bdaSduboff
506f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS "%s: %s called", dp->name, __func__));
507f8919bdaSduboff
508f8919bdaSduboff /* invalidate mac addr cache */
509f8919bdaSduboff bzero(lp->mac_addr, sizeof (lp->mac_addr));
510f8919bdaSduboff
511f8919bdaSduboff lp->cr = 0;
512f8919bdaSduboff
513f8919bdaSduboff /* inhibit interrupts */
514f8919bdaSduboff OUTL(dp, IMR, 0);
51523d366e3Sduboff lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits;
516f8919bdaSduboff
517f8919bdaSduboff OUTL(dp, RFCR, 0);
518f8919bdaSduboff
519f8919bdaSduboff OUTL(dp, CR, CR_RST);
520f8919bdaSduboff drv_usecwait(10);
521f8919bdaSduboff
522f8919bdaSduboff for (i = 0; INL(dp, CR) & CR_RST; i++) {
523f8919bdaSduboff if (i > 100) {
524f8919bdaSduboff cmn_err(CE_WARN, "!%s: chip reset timeout", dp->name);
525f8919bdaSduboff return (GEM_FAILURE);
526f8919bdaSduboff }
527f8919bdaSduboff drv_usecwait(10);
528f8919bdaSduboff }
529f8919bdaSduboff DPRINTF(0, (CE_CONT, "!%s: chip reset in %duS", dp->name, i*10));
530f8919bdaSduboff
531f8919bdaSduboff OUTL(dp, CCSR, CCSR_PMESTS);
532f8919bdaSduboff OUTL(dp, CCSR, 0);
533f8919bdaSduboff
534f8919bdaSduboff /* Configuration register: enable PCI parity */
535f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b",
536f8919bdaSduboff dp->name, INL(dp, CFG), CFG_BITS_DP83815));
53723d366e3Sduboff val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
53823d366e3Sduboff OUTL(dp, CFG, val | CFG_PAUSE_ADV);
539f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", dp->name,
540f8919bdaSduboff INL(dp, CFG), CFG_BITS_DP83815));
541f8919bdaSduboff
542f8919bdaSduboff return (GEM_SUCCESS);
543f8919bdaSduboff }
544f8919bdaSduboff
545f8919bdaSduboff static int
sfe_init_chip(struct gem_dev * dp)546f8919bdaSduboff sfe_init_chip(struct gem_dev *dp)
547f8919bdaSduboff {
548f8919bdaSduboff /* Configuration register: have been set up in sfe_chip_reset */
549f8919bdaSduboff
550f8919bdaSduboff /* PCI test control register: do nothing */
551f8919bdaSduboff
552f8919bdaSduboff /* Interrupt status register : do nothing */
553f8919bdaSduboff
554f8919bdaSduboff /* Interrupt mask register: clear, but leave lp->our_intr_bits */
555f8919bdaSduboff OUTL(dp, IMR, 0);
556f8919bdaSduboff
557f8919bdaSduboff /* Enhanced PHY Access register (sis900): do nothing */
558f8919bdaSduboff
559f8919bdaSduboff /* Transmit Descriptor Pointer register: base addr of TX ring */
560f8919bdaSduboff OUTL(dp, TXDP, dp->tx_ring_dma);
561f8919bdaSduboff
562f8919bdaSduboff /* Receive descriptor pointer register: base addr of RX ring */
563f8919bdaSduboff OUTL(dp, RXDP, dp->rx_ring_dma);
564f8919bdaSduboff
565f8919bdaSduboff return (GEM_SUCCESS);
566f8919bdaSduboff }
567f8919bdaSduboff
568f8919bdaSduboff static uint_t
sfe_mcast_hash(struct gem_dev * dp,uint8_t * addr)569f8919bdaSduboff sfe_mcast_hash(struct gem_dev *dp, uint8_t *addr)
570f8919bdaSduboff {
571f8919bdaSduboff return (gem_ether_crc_be(addr, ETHERADDRL));
572f8919bdaSduboff }
573f8919bdaSduboff
574f8919bdaSduboff #ifdef DEBUG_LEVEL
575f8919bdaSduboff static void
sfe_rxfilter_dump(struct gem_dev * dp,int start,int end)576f8919bdaSduboff sfe_rxfilter_dump(struct gem_dev *dp, int start, int end)
577f8919bdaSduboff {
578f8919bdaSduboff int i;
579f8919bdaSduboff int j;
580f8919bdaSduboff uint16_t ram[0x10];
581f8919bdaSduboff
582f8919bdaSduboff cmn_err(CE_CONT, "!%s: rx filter ram dump:", dp->name);
583f8919bdaSduboff #define WORDS_PER_LINE 4
584f8919bdaSduboff for (i = start; i < end; i += WORDS_PER_LINE*2) {
585f8919bdaSduboff for (j = 0; j < WORDS_PER_LINE; j++) {
586f8919bdaSduboff OUTL(dp, RFCR, RFADDR_MAC_DP83815 + i + j*2);
587f8919bdaSduboff ram[j] = INL(dp, RFDR);
588f8919bdaSduboff }
589f8919bdaSduboff
590f8919bdaSduboff cmn_err(CE_CONT, "!0x%02x: 0x%04x 0x%04x 0x%04x 0x%04x",
591f8919bdaSduboff i, ram[0], ram[1], ram[2], ram[3]);
592f8919bdaSduboff }
593f8919bdaSduboff
594f8919bdaSduboff #undef WORDS_PER_LINE
595f8919bdaSduboff }
596f8919bdaSduboff #endif
597f8919bdaSduboff
598f8919bdaSduboff static uint_t sfe_rf_perfect_base_dp83815[] = {
599f8919bdaSduboff RFADDR_PMATCH0_DP83815,
600f8919bdaSduboff RFADDR_PMATCH1_DP83815,
601f8919bdaSduboff RFADDR_PMATCH2_DP83815,
602f8919bdaSduboff RFADDR_PMATCH3_DP83815,
603f8919bdaSduboff };
604f8919bdaSduboff
605f8919bdaSduboff static int
sfe_set_rx_filter_dp83815(struct gem_dev * dp)606f8919bdaSduboff sfe_set_rx_filter_dp83815(struct gem_dev *dp)
607f8919bdaSduboff {
608f8919bdaSduboff int i;
609f8919bdaSduboff int j;
610f8919bdaSduboff uint32_t mode;
611f8919bdaSduboff uint8_t *mac = dp->cur_addr.ether_addr_octet;
612f8919bdaSduboff uint16_t hash_tbl[32];
613f8919bdaSduboff struct sfe_dev *lp = dp->private;
614f8919bdaSduboff
615f8919bdaSduboff DPRINTF(1, (CE_CONT, CONS "%s: %s: called, mc_count:%d, mode:0x%b",
616f8919bdaSduboff dp->name, __func__, dp->mc_count, dp->rxmode, RXMODE_BITS));
617f8919bdaSduboff
618f8919bdaSduboff #if DEBUG_LEVEL > 0
619f8919bdaSduboff for (i = 0; i < dp->mc_count; i++) {
620f8919bdaSduboff cmn_err(CE_CONT,
621f8919bdaSduboff "!%s: adding mcast(%d) %02x:%02x:%02x:%02x:%02x:%02x",
622f8919bdaSduboff dp->name, i,
623f8919bdaSduboff dp->mc_list[i].addr.ether_addr_octet[0],
624f8919bdaSduboff dp->mc_list[i].addr.ether_addr_octet[1],
625f8919bdaSduboff dp->mc_list[i].addr.ether_addr_octet[2],
626f8919bdaSduboff dp->mc_list[i].addr.ether_addr_octet[3],
627f8919bdaSduboff dp->mc_list[i].addr.ether_addr_octet[4],
628f8919bdaSduboff dp->mc_list[i].addr.ether_addr_octet[5]);
629f8919bdaSduboff }
630f8919bdaSduboff #endif
631f8919bdaSduboff if ((dp->rxmode & RXMODE_ENABLE) == 0) {
632f8919bdaSduboff /* disable rx filter */
633f8919bdaSduboff OUTL(dp, RFCR, 0);
634f8919bdaSduboff return (GEM_SUCCESS);
635f8919bdaSduboff }
636f8919bdaSduboff
637f8919bdaSduboff /*
638f8919bdaSduboff * Set Receive filter control register
639f8919bdaSduboff */
640f8919bdaSduboff if (dp->rxmode & RXMODE_PROMISC) {
641f8919bdaSduboff /* all broadcast, all multicast, all physical */
642f8919bdaSduboff mode = RFCR_AAB | RFCR_AAM | RFCR_AAP;
643f8919bdaSduboff } else if ((dp->rxmode & RXMODE_ALLMULTI) || dp->mc_count > 16*32/2) {
644f8919bdaSduboff /* all broadcast, all multicast, physical for the chip */
645f8919bdaSduboff mode = RFCR_AAB | RFCR_AAM | RFCR_APM_DP83815;
646f8919bdaSduboff } else if (dp->mc_count > 4) {
647f8919bdaSduboff /*
648f8919bdaSduboff * Use multicast hash table,
649f8919bdaSduboff * accept all broadcast and physical for the chip.
650f8919bdaSduboff */
651f8919bdaSduboff mode = RFCR_AAB | RFCR_MHEN_DP83815 | RFCR_APM_DP83815;
652f8919bdaSduboff
653f8919bdaSduboff bzero(hash_tbl, sizeof (hash_tbl));
654f8919bdaSduboff for (i = 0; i < dp->mc_count; i++) {
655f8919bdaSduboff j = dp->mc_list[i].hash >> (32 - 9);
656f8919bdaSduboff hash_tbl[j / 16] |= 1 << (j % 16);
657f8919bdaSduboff }
658f8919bdaSduboff } else {
659f8919bdaSduboff /*
660f8919bdaSduboff * Use pattern mach filter for multicast address,
661f8919bdaSduboff * accept all broadcast and physical for the chip
662f8919bdaSduboff */
663f8919bdaSduboff /* need to enable corresponding pattern registers */
664f8919bdaSduboff mode = RFCR_AAB | RFCR_APM_DP83815 |
665f8919bdaSduboff (((1 << dp->mc_count) - 1) << RFCR_APAT_SHIFT);
666f8919bdaSduboff }
667f8919bdaSduboff
668f8919bdaSduboff #if DEBUG_LEVEL > 1
669f8919bdaSduboff cmn_err(CE_CONT,
670f8919bdaSduboff "!%s: mac %02x:%02x:%02x:%02x:%02x:%02x"
671f8919bdaSduboff " cache %02x:%02x:%02x:%02x:%02x:%02x",
672f8919bdaSduboff dp->name, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
673f8919bdaSduboff lp->mac_addr[0], lp->mac_addr[1],
674f8919bdaSduboff lp->mac_addr[2], lp->mac_addr[3],
675f8919bdaSduboff lp->mac_addr[4], lp->mac_addr[5]);
676f8919bdaSduboff #endif
677f8919bdaSduboff if (bcmp(mac, lp->mac_addr, ETHERADDRL) != 0) {
678f8919bdaSduboff /*
679f8919bdaSduboff * XXX - need to *disable* rx filter to load mac address for
680f8919bdaSduboff * the chip. otherwise, we cannot setup rxfilter correctly.
681f8919bdaSduboff */
682f8919bdaSduboff /* setup perfect match register for my station address */
683f8919bdaSduboff for (i = 0; i < ETHERADDRL; i += 2) {
684f8919bdaSduboff OUTL(dp, RFCR, RFADDR_MAC_DP83815 + i);
685f8919bdaSduboff OUTL(dp, RFDR, (mac[i+1] << 8) | mac[i]);
686f8919bdaSduboff }
687f8919bdaSduboff
688f8919bdaSduboff bcopy(mac, lp->mac_addr, ETHERADDRL);
689f8919bdaSduboff }
690f8919bdaSduboff
691f8919bdaSduboff #if DEBUG_LEVEL > 3
692f8919bdaSduboff /* clear pattern ram */
693f8919bdaSduboff for (j = 0x200; j < 0x380; j += 2) {
694f8919bdaSduboff OUTL(dp, RFCR, j);
695f8919bdaSduboff OUTL(dp, RFDR, 0);
696f8919bdaSduboff }
697f8919bdaSduboff #endif
698f8919bdaSduboff if (mode & RFCR_APAT_DP83815) {
699f8919bdaSduboff /* setup multicast address into pattern match registers */
700f8919bdaSduboff for (j = 0; j < dp->mc_count; j++) {
701f8919bdaSduboff mac = &dp->mc_list[j].addr.ether_addr_octet[0];
702f8919bdaSduboff for (i = 0; i < ETHERADDRL; i += 2) {
703f8919bdaSduboff OUTL(dp, RFCR,
704f8919bdaSduboff sfe_rf_perfect_base_dp83815[j] + i*2);
705f8919bdaSduboff OUTL(dp, RFDR, (mac[i+1] << 8) | mac[i]);
706f8919bdaSduboff }
707f8919bdaSduboff }
708f8919bdaSduboff
709f8919bdaSduboff /* setup pattern count registers */
710f8919bdaSduboff OUTL(dp, RFCR, RFADDR_PCOUNT01_DP83815);
711f8919bdaSduboff OUTL(dp, RFDR, (ETHERADDRL << 8) | ETHERADDRL);
712f8919bdaSduboff OUTL(dp, RFCR, RFADDR_PCOUNT23_DP83815);
713f8919bdaSduboff OUTL(dp, RFDR, (ETHERADDRL << 8) | ETHERADDRL);
714f8919bdaSduboff }
715f8919bdaSduboff
716f8919bdaSduboff if (mode & RFCR_MHEN_DP83815) {
717f8919bdaSduboff /* Load Multicast hash table */
718f8919bdaSduboff for (i = 0; i < 32; i++) {
719f8919bdaSduboff /* for DP83815, index is in byte */
720f8919bdaSduboff OUTL(dp, RFCR, RFADDR_MULTICAST_DP83815 + i*2);
721f8919bdaSduboff OUTL(dp, RFDR, hash_tbl[i]);
722f8919bdaSduboff }
723f8919bdaSduboff }
724f8919bdaSduboff #if DEBUG_LEVEL > 2
725f8919bdaSduboff sfe_rxfilter_dump(dp, 0, 0x10);
726f8919bdaSduboff sfe_rxfilter_dump(dp, 0x200, 0x380);
727f8919bdaSduboff #endif
728f8919bdaSduboff /* Set rx filter mode and enable rx filter */
729f8919bdaSduboff OUTL(dp, RFCR, RFCR_RFEN | mode);
730f8919bdaSduboff
731f8919bdaSduboff return (GEM_SUCCESS);
732f8919bdaSduboff }
733f8919bdaSduboff
734f8919bdaSduboff static int
sfe_set_rx_filter_sis900(struct gem_dev * dp)735f8919bdaSduboff sfe_set_rx_filter_sis900(struct gem_dev *dp)
736f8919bdaSduboff {
737f8919bdaSduboff int i;
738f8919bdaSduboff uint32_t mode;
739f8919bdaSduboff uint16_t hash_tbl[16];
740f8919bdaSduboff uint8_t *mac = dp->cur_addr.ether_addr_octet;
741f8919bdaSduboff int hash_size;
742f8919bdaSduboff int hash_shift;
743f8919bdaSduboff struct sfe_dev *lp = dp->private;
744f8919bdaSduboff
745f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
746f8919bdaSduboff
747f8919bdaSduboff if ((dp->rxmode & RXMODE_ENABLE) == 0) {
748915ebf8dSAlan Duboff /* disable rx filter */
749915ebf8dSAlan Duboff OUTLINL(dp, RFCR, 0);
750f8919bdaSduboff return (GEM_SUCCESS);
751f8919bdaSduboff }
752f8919bdaSduboff
753f8919bdaSduboff /*
754f8919bdaSduboff * determine hardware hash table size in word.
755f8919bdaSduboff */
756f8919bdaSduboff hash_shift = 25;
757f8919bdaSduboff if (lp->revid >= SIS635A_900_REV || lp->revid == SIS900B_900_REV) {
758f8919bdaSduboff hash_shift = 24;
759f8919bdaSduboff }
760f8919bdaSduboff hash_size = (1 << (32 - hash_shift)) / 16;
761f8919bdaSduboff bzero(hash_tbl, sizeof (hash_tbl));
762f8919bdaSduboff
763f8919bdaSduboff /* Set Receive filter control register */
764f8919bdaSduboff
765f8919bdaSduboff if (dp->rxmode & RXMODE_PROMISC) {
766f8919bdaSduboff /* all broadcast, all multicast, all physical */
767f8919bdaSduboff mode = RFCR_AAB | RFCR_AAM | RFCR_AAP;
768f8919bdaSduboff } else if ((dp->rxmode & RXMODE_ALLMULTI) ||
769f8919bdaSduboff dp->mc_count > hash_size*16/2) {
770f8919bdaSduboff /* all broadcast, all multicast, physical for the chip */
771f8919bdaSduboff mode = RFCR_AAB | RFCR_AAM;
772f8919bdaSduboff } else {
773f8919bdaSduboff /* all broadcast, physical for the chip */
774f8919bdaSduboff mode = RFCR_AAB;
775f8919bdaSduboff }
776f8919bdaSduboff
777f8919bdaSduboff /* make hash table */
778f8919bdaSduboff for (i = 0; i < dp->mc_count; i++) {
779f8919bdaSduboff uint_t h;
780f8919bdaSduboff h = dp->mc_list[i].hash >> hash_shift;
781f8919bdaSduboff hash_tbl[h / 16] |= 1 << (h % 16);
782f8919bdaSduboff }
783f8919bdaSduboff
784f8919bdaSduboff if (bcmp(mac, lp->mac_addr, ETHERADDRL) != 0) {
785f8919bdaSduboff /* Disable Rx filter and load mac address */
786f8919bdaSduboff for (i = 0; i < ETHERADDRL/2; i++) {
787f8919bdaSduboff /* For sis900, index is in word */
788915ebf8dSAlan Duboff OUTLINL(dp, RFCR,
789f8919bdaSduboff (RFADDR_MAC_SIS900+i) << RFCR_RFADDR_SHIFT_SIS900);
790915ebf8dSAlan Duboff OUTLINL(dp, RFDR, (mac[i*2+1] << 8) | mac[i*2]);
791f8919bdaSduboff }
792f8919bdaSduboff
793f8919bdaSduboff bcopy(mac, lp->mac_addr, ETHERADDRL);
794f8919bdaSduboff }
795f8919bdaSduboff
796f8919bdaSduboff /* Load Multicast hash table */
797f8919bdaSduboff for (i = 0; i < hash_size; i++) {
798f8919bdaSduboff /* For sis900, index is in word */
799915ebf8dSAlan Duboff OUTLINL(dp, RFCR,
800f8919bdaSduboff (RFADDR_MULTICAST_SIS900 + i) << RFCR_RFADDR_SHIFT_SIS900);
801915ebf8dSAlan Duboff OUTLINL(dp, RFDR, hash_tbl[i]);
802f8919bdaSduboff }
803f8919bdaSduboff
804f8919bdaSduboff /* Load rx filter mode and enable rx filter */
805915ebf8dSAlan Duboff OUTLINL(dp, RFCR, RFCR_RFEN | mode);
806f8919bdaSduboff
807f8919bdaSduboff return (GEM_SUCCESS);
808f8919bdaSduboff }
809f8919bdaSduboff
810f8919bdaSduboff static int
sfe_start_chip(struct gem_dev * dp)811f8919bdaSduboff sfe_start_chip(struct gem_dev *dp)
812f8919bdaSduboff {
813f8919bdaSduboff struct sfe_dev *lp = dp->private;
814f8919bdaSduboff
815f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
816f8919bdaSduboff
817f8919bdaSduboff /*
818f8919bdaSduboff * setup interrupt mask, which shouldn't include ISR_TOK
819f8919bdaSduboff * to improve performance.
820f8919bdaSduboff */
821f8919bdaSduboff lp->our_intr_bits = OUR_INTR_BITS;
822f8919bdaSduboff
823f8919bdaSduboff /* enable interrupt */
824f8919bdaSduboff if ((dp->misc_flag & GEM_NOINTR) == 0) {
825f8919bdaSduboff OUTL(dp, IER, 1);
826f8919bdaSduboff OUTL(dp, IMR, lp->our_intr_bits);
827f8919bdaSduboff }
828f8919bdaSduboff
829f8919bdaSduboff /* Kick RX */
830f8919bdaSduboff OUTL(dp, CR, lp->cr | CR_RXE);
831f8919bdaSduboff
832f8919bdaSduboff return (GEM_SUCCESS);
833f8919bdaSduboff }
834f8919bdaSduboff
835f8919bdaSduboff /*
836f8919bdaSduboff * Stop nic core gracefully.
837f8919bdaSduboff */
838f8919bdaSduboff static int
sfe_stop_chip(struct gem_dev * dp)839f8919bdaSduboff sfe_stop_chip(struct gem_dev *dp)
840f8919bdaSduboff {
841f8919bdaSduboff struct sfe_dev *lp = dp->private;
842f8919bdaSduboff uint32_t done;
843f8919bdaSduboff int i;
84423d366e3Sduboff uint32_t val;
845f8919bdaSduboff
846f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
847f8919bdaSduboff
848f8919bdaSduboff /*
849f8919bdaSduboff * Although we inhibit interrupt here, we don't clear soft copy of
850f8919bdaSduboff * interrupt mask to avoid bogus interrupts.
851f8919bdaSduboff */
852f8919bdaSduboff OUTL(dp, IMR, 0);
853f8919bdaSduboff
854f8919bdaSduboff /* stop TX and RX immediately */
855f8919bdaSduboff OUTL(dp, CR, lp->cr | CR_TXR | CR_RXR);
856f8919bdaSduboff
857f8919bdaSduboff done = 0;
858f8919bdaSduboff for (i = 0; done != (ISR_RXRCMP | ISR_TXRCMP); i++) {
859f8919bdaSduboff if (i > 1000) {
860f8919bdaSduboff /*
861f8919bdaSduboff * As gem layer will call sfe_reset_chip(),
862f8919bdaSduboff * we don't neet to reset futher
863f8919bdaSduboff */
864f8919bdaSduboff cmn_err(CE_NOTE, "!%s: %s: Tx/Rx reset timeout",
865f8919bdaSduboff dp->name, __func__);
866f8919bdaSduboff
867f8919bdaSduboff return (GEM_FAILURE);
868f8919bdaSduboff }
86923d366e3Sduboff val = INL(dp, ISR);
87023d366e3Sduboff done |= val & (ISR_RXRCMP | ISR_TXRCMP);
87123d366e3Sduboff lp->isr_pended |= val & lp->our_intr_bits;
872f8919bdaSduboff drv_usecwait(10);
873f8919bdaSduboff }
874f8919bdaSduboff
875f8919bdaSduboff return (GEM_SUCCESS);
876f8919bdaSduboff }
877f8919bdaSduboff
87853560dfaSSherry Moore #ifndef __sparc
87953560dfaSSherry Moore /*
88053560dfaSSherry Moore * Stop nic core gracefully for quiesce
88153560dfaSSherry Moore */
88253560dfaSSherry Moore static int
sfe_stop_chip_quiesce(struct gem_dev * dp)88353560dfaSSherry Moore sfe_stop_chip_quiesce(struct gem_dev *dp)
88453560dfaSSherry Moore {
88553560dfaSSherry Moore struct sfe_dev *lp = dp->private;
88653560dfaSSherry Moore uint32_t done;
88753560dfaSSherry Moore int i;
88853560dfaSSherry Moore uint32_t val;
88953560dfaSSherry Moore
89053560dfaSSherry Moore /*
89153560dfaSSherry Moore * Although we inhibit interrupt here, we don't clear soft copy of
89253560dfaSSherry Moore * interrupt mask to avoid bogus interrupts.
89353560dfaSSherry Moore */
89453560dfaSSherry Moore OUTL(dp, IMR, 0);
89553560dfaSSherry Moore
89653560dfaSSherry Moore /* stop TX and RX immediately */
89753560dfaSSherry Moore OUTL(dp, CR, CR_TXR | CR_RXR);
89853560dfaSSherry Moore
89953560dfaSSherry Moore done = 0;
90053560dfaSSherry Moore for (i = 0; done != (ISR_RXRCMP | ISR_TXRCMP); i++) {
90153560dfaSSherry Moore if (i > 1000) {
90253560dfaSSherry Moore /*
90353560dfaSSherry Moore * As gem layer will call sfe_reset_chip(),
90453560dfaSSherry Moore * we don't neet to reset futher
90553560dfaSSherry Moore */
90653560dfaSSherry Moore
90753560dfaSSherry Moore return (DDI_FAILURE);
90853560dfaSSherry Moore }
90953560dfaSSherry Moore val = INL(dp, ISR);
91053560dfaSSherry Moore done |= val & (ISR_RXRCMP | ISR_TXRCMP);
91153560dfaSSherry Moore lp->isr_pended |= val & lp->our_intr_bits;
91253560dfaSSherry Moore drv_usecwait(10);
91353560dfaSSherry Moore }
91453560dfaSSherry Moore return (DDI_SUCCESS);
91553560dfaSSherry Moore }
91653560dfaSSherry Moore #endif
91753560dfaSSherry Moore
918f8919bdaSduboff /*
919f8919bdaSduboff * Setup media mode
920f8919bdaSduboff */
921f8919bdaSduboff static uint_t
922f8919bdaSduboff sfe_mxdma_value[] = { 512, 4, 8, 16, 32, 64, 128, 256, };
923f8919bdaSduboff
924f8919bdaSduboff static uint_t
sfe_encode_mxdma(uint_t burstsize)925f8919bdaSduboff sfe_encode_mxdma(uint_t burstsize)
926f8919bdaSduboff {
927f8919bdaSduboff int i;
928f8919bdaSduboff
929f8919bdaSduboff if (burstsize > 256) {
930f8919bdaSduboff /* choose 512 */
931f8919bdaSduboff return (0);
932f8919bdaSduboff }
933f8919bdaSduboff
934f8919bdaSduboff for (i = 1; i < 8; i++) {
935f8919bdaSduboff if (burstsize <= sfe_mxdma_value[i]) {
936f8919bdaSduboff break;
937f8919bdaSduboff }
938f8919bdaSduboff }
939f8919bdaSduboff return (i);
940f8919bdaSduboff }
941f8919bdaSduboff
942f8919bdaSduboff static int
sfe_set_media(struct gem_dev * dp)943f8919bdaSduboff sfe_set_media(struct gem_dev *dp)
944f8919bdaSduboff {
945f8919bdaSduboff uint32_t txcfg;
946f8919bdaSduboff uint32_t rxcfg;
947f8919bdaSduboff uint32_t pcr;
948f8919bdaSduboff uint32_t val;
949f8919bdaSduboff uint32_t txmxdma;
950f8919bdaSduboff uint32_t rxmxdma;
951f8919bdaSduboff struct sfe_dev *lp = dp->private;
952f8919bdaSduboff #ifdef DEBUG_LEVEL
953f8919bdaSduboff extern int gem_speed_value[];
954f8919bdaSduboff #endif
955f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: %s: %s duplex, %d Mbps",
956f8919bdaSduboff dp->name, __func__,
957f8919bdaSduboff dp->full_duplex ? "full" : "half", gem_speed_value[dp->speed]));
958f8919bdaSduboff
959f8919bdaSduboff /* initialize txcfg and rxcfg */
960f8919bdaSduboff txcfg = TXCFG_ATP;
961f8919bdaSduboff if (dp->full_duplex) {
962f8919bdaSduboff txcfg |= (TXCFG_CSI | TXCFG_HBI);
963f8919bdaSduboff }
96423d366e3Sduboff rxcfg = RXCFG_AEP | RXCFG_ARP;
965f8919bdaSduboff if (dp->full_duplex) {
966f8919bdaSduboff rxcfg |= RXCFG_ATX;
967f8919bdaSduboff }
968f8919bdaSduboff
969f8919bdaSduboff /* select txmxdma and rxmxdma, maxmum burst length */
970f8919bdaSduboff if (lp->chip->chip_type == CHIPTYPE_SIS900) {
971f8919bdaSduboff #ifdef DEBUG_SIS900_EDB
972f8919bdaSduboff val = CFG_EDB_MASTER;
973f8919bdaSduboff #else
974f8919bdaSduboff val = INL(dp, CFG) & CFG_EDB_MASTER;
975f8919bdaSduboff #endif
976f8919bdaSduboff if (val) {
977f8919bdaSduboff /*
978f8919bdaSduboff * sis900 built-in cores:
979f8919bdaSduboff * max burst length must be fixed to 64
980f8919bdaSduboff */
981f8919bdaSduboff txmxdma = 64;
982f8919bdaSduboff rxmxdma = 64;
983f8919bdaSduboff } else {
984f8919bdaSduboff /*
985f8919bdaSduboff * sis900 pci chipset:
986f8919bdaSduboff * the vendor recommended to fix max burst length
987f8919bdaSduboff * to 512
988f8919bdaSduboff */
989f8919bdaSduboff txmxdma = 512;
990f8919bdaSduboff rxmxdma = 512;
991f8919bdaSduboff }
992f8919bdaSduboff } else {
993f8919bdaSduboff /*
994f8919bdaSduboff * NS dp83815/816:
995f8919bdaSduboff * use user defined or default for tx/rx max burst length
996f8919bdaSduboff */
997f8919bdaSduboff txmxdma = max(dp->txmaxdma, 256);
998f8919bdaSduboff rxmxdma = max(dp->rxmaxdma, 256);
999f8919bdaSduboff }
1000f8919bdaSduboff
1001f8919bdaSduboff
1002f8919bdaSduboff /* tx high water mark */
1003f8919bdaSduboff lp->tx_drain_threshold = ROUNDUP2(dp->txthr, TXCFG_FIFO_UNIT);
1004f8919bdaSduboff
1005f8919bdaSduboff /* determine tx_fill_threshold accroding drain threshold */
1006f8919bdaSduboff lp->tx_fill_threshold =
1007f8919bdaSduboff TXFIFOSIZE - lp->tx_drain_threshold - TXCFG_FIFO_UNIT;
1008f8919bdaSduboff
1009f8919bdaSduboff /* tune txmxdma not to exceed tx_fill_threshold */
1010f8919bdaSduboff for (; ; ) {
1011f8919bdaSduboff /* normalize txmxdma requested */
1012f8919bdaSduboff val = sfe_encode_mxdma(txmxdma);
1013f8919bdaSduboff txmxdma = sfe_mxdma_value[val];
1014f8919bdaSduboff
1015f8919bdaSduboff if (txmxdma <= lp->tx_fill_threshold) {
1016f8919bdaSduboff break;
1017f8919bdaSduboff }
1018f8919bdaSduboff /* select new txmxdma */
1019f8919bdaSduboff txmxdma = txmxdma / 2;
1020f8919bdaSduboff }
1021f8919bdaSduboff txcfg |= val << TXCFG_MXDMA_SHIFT;
1022f8919bdaSduboff
1023f8919bdaSduboff /* encode rxmxdma, maxmum burst length for rx */
1024f8919bdaSduboff val = sfe_encode_mxdma(rxmxdma);
102523d366e3Sduboff rxcfg |= val << RXCFG_MXDMA_SHIFT;
1026f8919bdaSduboff rxmxdma = sfe_mxdma_value[val];
1027f8919bdaSduboff
1028f8919bdaSduboff /* receive starting threshold - it have only 5bit-wide field */
1029f8919bdaSduboff val = ROUNDUP2(max(dp->rxthr, ETHERMIN), RXCFG_FIFO_UNIT);
1030f8919bdaSduboff lp->rx_drain_threshold =
1031f8919bdaSduboff min(val, (RXCFG_DRTH >> RXCFG_DRTH_SHIFT) * RXCFG_FIFO_UNIT);
1032f8919bdaSduboff
1033f8919bdaSduboff DPRINTF(0, (CE_CONT,
1034f8919bdaSduboff "%s: %s: tx: drain:%d(rest %d) fill:%d mxdma:%d,"
1035f8919bdaSduboff " rx: drain:%d mxdma:%d",
1036f8919bdaSduboff dp->name, __func__,
1037f8919bdaSduboff lp->tx_drain_threshold, TXFIFOSIZE - lp->tx_drain_threshold,
1038f8919bdaSduboff lp->tx_fill_threshold, txmxdma,
1039f8919bdaSduboff lp->rx_drain_threshold, rxmxdma));
1040f8919bdaSduboff
1041f8919bdaSduboff ASSERT(lp->tx_drain_threshold < 64*TXCFG_FIFO_UNIT);
1042f8919bdaSduboff ASSERT(lp->tx_fill_threshold < 64*TXCFG_FIFO_UNIT);
1043f8919bdaSduboff ASSERT(lp->rx_drain_threshold < 32*RXCFG_FIFO_UNIT);
1044f8919bdaSduboff
1045f8919bdaSduboff txcfg |= ((lp->tx_fill_threshold/TXCFG_FIFO_UNIT) << TXCFG_FLTH_SHIFT)
1046f8919bdaSduboff | (lp->tx_drain_threshold/TXCFG_FIFO_UNIT);
1047f8919bdaSduboff OUTL(dp, TXCFG, txcfg);
1048f8919bdaSduboff
1049f8919bdaSduboff rxcfg |= ((lp->rx_drain_threshold/RXCFG_FIFO_UNIT) << RXCFG_DRTH_SHIFT);
1050f8919bdaSduboff if (lp->chip->chip_type == CHIPTYPE_DP83815) {
1051f8919bdaSduboff rxcfg |= RXCFG_ALP_DP83815;
1052f8919bdaSduboff }
1053f8919bdaSduboff OUTL(dp, RXCFG, rxcfg);
1054f8919bdaSduboff
1055f8919bdaSduboff DPRINTF(0, (CE_CONT, CONS "%s: %s: txcfg:%b rxcfg:%b",
1056f8919bdaSduboff dp->name, __func__,
1057f8919bdaSduboff txcfg, TXCFG_BITS, rxcfg, RXCFG_BITS));
1058f8919bdaSduboff
1059f8919bdaSduboff /* Flow control */
1060f8919bdaSduboff if (lp->chip->chip_type == CHIPTYPE_DP83815) {
1061f8919bdaSduboff pcr = INL(dp, PCR);
1062f8919bdaSduboff switch (dp->flow_control) {
1063f8919bdaSduboff case FLOW_CONTROL_SYMMETRIC:
1064f8919bdaSduboff case FLOW_CONTROL_RX_PAUSE:
1065f8919bdaSduboff OUTL(dp, PCR, pcr | PCR_PSEN | PCR_PS_MCAST);
1066f8919bdaSduboff break;
1067f8919bdaSduboff
1068f8919bdaSduboff default:
1069f8919bdaSduboff OUTL(dp, PCR,
1070f8919bdaSduboff pcr & ~(PCR_PSEN | PCR_PS_MCAST | PCR_PS_DA));
1071f8919bdaSduboff break;
1072f8919bdaSduboff }
1073f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: PCR: %b", dp->name,
1074f8919bdaSduboff INL(dp, PCR), PCR_BITS));
1075f8919bdaSduboff
1076f8919bdaSduboff } else if (lp->chip->chip_type == CHIPTYPE_SIS900) {
1077f8919bdaSduboff switch (dp->flow_control) {
1078f8919bdaSduboff case FLOW_CONTROL_SYMMETRIC:
1079f8919bdaSduboff case FLOW_CONTROL_RX_PAUSE:
1080f8919bdaSduboff OUTL(dp, FLOWCTL, FLOWCTL_FLOWEN);
1081f8919bdaSduboff break;
1082f8919bdaSduboff default:
1083f8919bdaSduboff OUTL(dp, FLOWCTL, 0);
1084f8919bdaSduboff break;
1085f8919bdaSduboff }
1086f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: FLOWCTL: %b",
1087f8919bdaSduboff dp->name, INL(dp, FLOWCTL), FLOWCTL_BITS));
1088f8919bdaSduboff }
1089f8919bdaSduboff return (GEM_SUCCESS);
1090f8919bdaSduboff }
1091f8919bdaSduboff
1092f8919bdaSduboff static int
sfe_get_stats(struct gem_dev * dp)1093f8919bdaSduboff sfe_get_stats(struct gem_dev *dp)
1094f8919bdaSduboff {
1095f8919bdaSduboff /* do nothing */
1096f8919bdaSduboff return (GEM_SUCCESS);
1097f8919bdaSduboff }
1098f8919bdaSduboff
1099f8919bdaSduboff /*
1100f8919bdaSduboff * descriptor manipulations
1101f8919bdaSduboff */
1102f8919bdaSduboff static int
sfe_tx_desc_write(struct gem_dev * dp,int slot,ddi_dma_cookie_t * dmacookie,int frags,uint64_t flags)1103f8919bdaSduboff sfe_tx_desc_write(struct gem_dev *dp, int slot,
1104*3b8e6442SToomas Soome ddi_dma_cookie_t *dmacookie, int frags, uint64_t flags)
1105f8919bdaSduboff {
1106f8919bdaSduboff uint32_t mark;
1107f8919bdaSduboff struct sfe_desc *tdp;
1108f8919bdaSduboff ddi_dma_cookie_t *dcp;
110923d366e3Sduboff uint32_t tmp0;
111023d366e3Sduboff #if DEBUG_LEVEL > 2
1111f8919bdaSduboff int i;
1112f8919bdaSduboff
1113f8919bdaSduboff cmn_err(CE_CONT,
1114f8919bdaSduboff CONS "%s: time:%d %s seqnum: %d, slot %d, frags: %d flags: %llx",
1115f8919bdaSduboff dp->name, ddi_get_lbolt(), __func__,
1116f8919bdaSduboff dp->tx_desc_tail, slot, frags, flags);
1117f8919bdaSduboff
1118f8919bdaSduboff for (i = 0; i < frags; i++) {
1119f8919bdaSduboff cmn_err(CE_CONT, CONS "%d: addr: 0x%x, len: 0x%x",
1120f8919bdaSduboff i, dmacookie[i].dmac_address, dmacookie[i].dmac_size);
112123d366e3Sduboff }
1122f8919bdaSduboff #endif
1123f8919bdaSduboff /*
1124f8919bdaSduboff * write tx descriptor in reversed order.
1125f8919bdaSduboff */
1126f8919bdaSduboff #if DEBUG_LEVEL > 3
1127f8919bdaSduboff flags |= GEM_TXFLAG_INTR;
1128f8919bdaSduboff #endif
1129f8919bdaSduboff mark = (flags & GEM_TXFLAG_INTR)
113023d366e3Sduboff ? (CMDSTS_OWN | CMDSTS_INTR) : CMDSTS_OWN;
1131f8919bdaSduboff
1132f8919bdaSduboff ASSERT(frags == 1);
1133f8919bdaSduboff dcp = &dmacookie[0];
1134f8919bdaSduboff if (flags & GEM_TXFLAG_HEAD) {
1135f8919bdaSduboff mark &= ~CMDSTS_OWN;
1136f8919bdaSduboff }
1137f8919bdaSduboff
1138f8919bdaSduboff tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot];
113923d366e3Sduboff tmp0 = (uint32_t)dcp->dmac_address;
114023d366e3Sduboff mark |= (uint32_t)dcp->dmac_size;
114123d366e3Sduboff tdp->d_bufptr = LE_32(tmp0);
114223d366e3Sduboff tdp->d_cmdsts = LE_32(mark);
1143f8919bdaSduboff
1144f8919bdaSduboff return (frags);
1145f8919bdaSduboff }
1146f8919bdaSduboff
1147f8919bdaSduboff static void
sfe_tx_start(struct gem_dev * dp,int start_slot,int nslot)1148f8919bdaSduboff sfe_tx_start(struct gem_dev *dp, int start_slot, int nslot)
1149f8919bdaSduboff {
115023d366e3Sduboff uint_t tx_ring_size = dp->gc.gc_tx_ring_size;
1151f8919bdaSduboff struct sfe_desc *tdp;
1152f8919bdaSduboff struct sfe_dev *lp = dp->private;
1153f8919bdaSduboff
1154f8919bdaSduboff if (nslot > 1) {
1155f8919bdaSduboff gem_tx_desc_dma_sync(dp,
115623d366e3Sduboff SLOT(start_slot + 1, tx_ring_size),
1157f8919bdaSduboff nslot - 1, DDI_DMA_SYNC_FORDEV);
1158f8919bdaSduboff }
1159f8919bdaSduboff
1160f8919bdaSduboff tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * start_slot];
1161f8919bdaSduboff tdp->d_cmdsts |= LE_32(CMDSTS_OWN);
1162f8919bdaSduboff
1163f8919bdaSduboff gem_tx_desc_dma_sync(dp, start_slot, 1, DDI_DMA_SYNC_FORDEV);
1164f8919bdaSduboff
1165f8919bdaSduboff /*
1166f8919bdaSduboff * Let the Transmit Buffer Manager Fill state machine active.
1167f8919bdaSduboff */
1168f8919bdaSduboff if (dp->mac_active) {
1169f8919bdaSduboff OUTL(dp, CR, lp->cr | CR_TXE);
1170f8919bdaSduboff }
1171f8919bdaSduboff }
1172f8919bdaSduboff
1173f8919bdaSduboff static void
sfe_rx_desc_write(struct gem_dev * dp,int slot,ddi_dma_cookie_t * dmacookie,int frags)1174f8919bdaSduboff sfe_rx_desc_write(struct gem_dev *dp, int slot,
1175*3b8e6442SToomas Soome ddi_dma_cookie_t *dmacookie, int frags)
1176f8919bdaSduboff {
1177f8919bdaSduboff struct sfe_desc *rdp;
117823d366e3Sduboff uint32_t tmp0;
117923d366e3Sduboff uint32_t tmp1;
1180f8919bdaSduboff #if DEBUG_LEVEL > 2
1181f8919bdaSduboff int i;
1182f8919bdaSduboff
1183f8919bdaSduboff ASSERT(frags == 1);
1184f8919bdaSduboff
1185f8919bdaSduboff cmn_err(CE_CONT, CONS
1186f8919bdaSduboff "%s: %s seqnum: %d, slot %d, frags: %d",
1187f8919bdaSduboff dp->name, __func__, dp->rx_active_tail, slot, frags);
1188f8919bdaSduboff for (i = 0; i < frags; i++) {
1189f8919bdaSduboff cmn_err(CE_CONT, CONS " frag: %d addr: 0x%llx, len: 0x%lx",
1190f8919bdaSduboff i, dmacookie[i].dmac_address, dmacookie[i].dmac_size);
1191f8919bdaSduboff }
1192f8919bdaSduboff #endif
1193f8919bdaSduboff /* for the last slot of the packet */
1194f8919bdaSduboff rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1195f8919bdaSduboff
119623d366e3Sduboff tmp0 = (uint32_t)dmacookie->dmac_address;
119723d366e3Sduboff tmp1 = CMDSTS_INTR | (uint32_t)dmacookie->dmac_size;
119823d366e3Sduboff rdp->d_bufptr = LE_32(tmp0);
119923d366e3Sduboff rdp->d_cmdsts = LE_32(tmp1);
1200f8919bdaSduboff }
1201f8919bdaSduboff
1202f8919bdaSduboff static uint_t
sfe_tx_desc_stat(struct gem_dev * dp,int slot,int ndesc)1203f8919bdaSduboff sfe_tx_desc_stat(struct gem_dev *dp, int slot, int ndesc)
1204f8919bdaSduboff {
120523d366e3Sduboff uint_t tx_ring_size = dp->gc.gc_tx_ring_size;
1206f8919bdaSduboff struct sfe_desc *tdp;
1207f8919bdaSduboff uint32_t status;
1208f8919bdaSduboff int cols;
120923d366e3Sduboff struct sfe_dev *lp = dp->private;
1210f8919bdaSduboff #ifdef DEBUG_LEVEL
1211f8919bdaSduboff int i;
1212f8919bdaSduboff clock_t delay;
1213f8919bdaSduboff #endif
1214f8919bdaSduboff /* check status of the last descriptor */
1215f8919bdaSduboff tdp = (void *)
121623d366e3Sduboff &dp->tx_ring[SFE_DESC_SIZE * SLOT(slot + ndesc - 1, tx_ring_size)];
1217f8919bdaSduboff
121823d366e3Sduboff /*
121923d366e3Sduboff * Don't use LE_32() directly to refer tdp->d_cmdsts.
122023d366e3Sduboff * It is not atomic for big endian cpus.
122123d366e3Sduboff */
122223d366e3Sduboff status = tdp->d_cmdsts;
122323d366e3Sduboff status = LE_32(status);
1224f8919bdaSduboff
1225f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: time:%ld %s: slot:%d, status:0x%b",
1226f8919bdaSduboff dp->name, ddi_get_lbolt(), __func__,
1227f8919bdaSduboff slot, status, TXSTAT_BITS));
1228f8919bdaSduboff
1229f8919bdaSduboff if (status & CMDSTS_OWN) {
1230f8919bdaSduboff /*
1231f8919bdaSduboff * not yet transmitted
1232f8919bdaSduboff */
123323d366e3Sduboff /* workaround for tx hang */
123423d366e3Sduboff if (lp->chip->chip_type == CHIPTYPE_DP83815 &&
123523d366e3Sduboff dp->mac_active) {
123623d366e3Sduboff OUTL(dp, CR, lp->cr | CR_TXE);
123723d366e3Sduboff }
1238f8919bdaSduboff return (0);
1239f8919bdaSduboff }
1240f8919bdaSduboff
1241f8919bdaSduboff if (status & CMDSTS_MORE) {
1242f8919bdaSduboff /* XXX - the hardware problem but don't panic the system */
1243f8919bdaSduboff /* avoid lint bug for %b format string including 32nd bit */
1244f8919bdaSduboff cmn_err(CE_NOTE, CONS
1245f8919bdaSduboff "%s: tx status bits incorrect: slot:%d, status:0x%x",
1246f8919bdaSduboff dp->name, slot, status);
1247f8919bdaSduboff }
1248f8919bdaSduboff
1249f8919bdaSduboff #if DEBUG_LEVEL > 3
1250f8919bdaSduboff delay = (ddi_get_lbolt() - dp->tx_buf_head->txb_stime) * 10;
1251f8919bdaSduboff if (delay >= 50) {
1252f8919bdaSduboff DPRINTF(0, (CE_NOTE, "%s: tx deferred %d mS: slot %d",
1253f8919bdaSduboff dp->name, delay, slot));
1254f8919bdaSduboff }
1255f8919bdaSduboff #endif
1256f8919bdaSduboff
1257f8919bdaSduboff #if DEBUG_LEVEL > 3
1258f8919bdaSduboff for (i = 0; i < nfrag-1; i++) {
1259f8919bdaSduboff uint32_t s;
1260f8919bdaSduboff int n;
1261f8919bdaSduboff
126223d366e3Sduboff n = SLOT(slot + i, tx_ring_size);
1263f8919bdaSduboff s = LE_32(
1264f8919bdaSduboff ((struct sfe_desc *)((void *)
1265f8919bdaSduboff &dp->tx_ring[SFE_DESC_SIZE * n]))->d_cmdsts);
1266f8919bdaSduboff
1267f8919bdaSduboff ASSERT(s & CMDSTS_MORE);
1268f8919bdaSduboff ASSERT((s & CMDSTS_OWN) == 0);
1269f8919bdaSduboff }
1270f8919bdaSduboff #endif
1271f8919bdaSduboff
1272f8919bdaSduboff /*
1273f8919bdaSduboff * collect statistics
1274f8919bdaSduboff */
1275f8919bdaSduboff if ((status & CMDSTS_OK) == 0) {
1276f8919bdaSduboff
1277f8919bdaSduboff /* failed to transmit the packet */
1278f8919bdaSduboff
1279f8919bdaSduboff DPRINTF(0, (CE_CONT, CONS "%s: Transmit error, Tx status %b",
1280f8919bdaSduboff dp->name, status, TXSTAT_BITS));
1281f8919bdaSduboff
1282f8919bdaSduboff dp->stats.errxmt++;
1283f8919bdaSduboff
1284f8919bdaSduboff if (status & CMDSTS_TFU) {
1285f8919bdaSduboff dp->stats.underflow++;
1286f8919bdaSduboff } else if (status & CMDSTS_CRS) {
1287f8919bdaSduboff dp->stats.nocarrier++;
1288f8919bdaSduboff } else if (status & CMDSTS_OWC) {
1289f8919bdaSduboff dp->stats.xmtlatecoll++;
1290f8919bdaSduboff } else if ((!dp->full_duplex) && (status & CMDSTS_EC)) {
1291f8919bdaSduboff dp->stats.excoll++;
1292f8919bdaSduboff dp->stats.collisions += 16;
1293f8919bdaSduboff } else {
1294f8919bdaSduboff dp->stats.xmit_internal_err++;
1295f8919bdaSduboff }
1296f8919bdaSduboff } else if (!dp->full_duplex) {
1297f8919bdaSduboff cols = (status >> CMDSTS_CCNT_SHIFT) & CCNT_MASK;
1298f8919bdaSduboff
1299f8919bdaSduboff if (cols > 0) {
1300f8919bdaSduboff if (cols == 1) {
1301f8919bdaSduboff dp->stats.first_coll++;
1302f8919bdaSduboff } else /* (cols > 1) */ {
1303f8919bdaSduboff dp->stats.multi_coll++;
1304f8919bdaSduboff }
1305f8919bdaSduboff dp->stats.collisions += cols;
1306f8919bdaSduboff } else if (status & CMDSTS_TD) {
1307f8919bdaSduboff dp->stats.defer++;
1308f8919bdaSduboff }
1309f8919bdaSduboff }
1310f8919bdaSduboff return (GEM_TX_DONE);
1311f8919bdaSduboff }
1312f8919bdaSduboff
1313f8919bdaSduboff static uint64_t
sfe_rx_desc_stat(struct gem_dev * dp,int slot,int ndesc)1314f8919bdaSduboff sfe_rx_desc_stat(struct gem_dev *dp, int slot, int ndesc)
1315f8919bdaSduboff {
1316f8919bdaSduboff struct sfe_desc *rdp;
1317f8919bdaSduboff uint_t len;
1318f8919bdaSduboff uint_t flag;
1319f8919bdaSduboff uint32_t status;
1320f8919bdaSduboff
1321f8919bdaSduboff flag = GEM_RX_DONE;
1322f8919bdaSduboff
1323f8919bdaSduboff /* Dont read ISR because we cannot ack only to rx interrupt. */
1324f8919bdaSduboff
1325f8919bdaSduboff rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1326f8919bdaSduboff
132723d366e3Sduboff /*
132823d366e3Sduboff * Don't use LE_32() directly to refer rdp->d_cmdsts.
132923d366e3Sduboff * It is not atomic for big endian cpus.
133023d366e3Sduboff */
133123d366e3Sduboff status = rdp->d_cmdsts;
133223d366e3Sduboff status = LE_32(status);
1333f8919bdaSduboff
1334f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "%s: time:%ld %s: slot:%d, status:0x%b",
1335f8919bdaSduboff dp->name, ddi_get_lbolt(), __func__,
1336f8919bdaSduboff slot, status, RXSTAT_BITS));
1337f8919bdaSduboff
1338f8919bdaSduboff if ((status & CMDSTS_OWN) == 0) {
1339f8919bdaSduboff /*
1340f8919bdaSduboff * No more received packets because
1341f8919bdaSduboff * this buffer is owned by NIC.
1342f8919bdaSduboff */
1343f8919bdaSduboff return (0);
1344f8919bdaSduboff }
1345f8919bdaSduboff
1346f8919bdaSduboff #define RX_ERR_BITS \
1347f8919bdaSduboff (CMDSTS_RXA | CMDSTS_RXO | CMDSTS_LONG | CMDSTS_RUNT | \
1348f8919bdaSduboff CMDSTS_ISE | CMDSTS_CRCE | CMDSTS_FAE | CMDSTS_MORE)
1349f8919bdaSduboff
1350f8919bdaSduboff if (status & RX_ERR_BITS) {
1351f8919bdaSduboff /*
1352f8919bdaSduboff * Packet with error received
1353f8919bdaSduboff */
1354f8919bdaSduboff DPRINTF(0, (CE_CONT, CONS "%s: Corrupted packet "
1355f8919bdaSduboff "received, buffer status: %b",
1356f8919bdaSduboff dp->name, status, RXSTAT_BITS));
1357f8919bdaSduboff
1358f8919bdaSduboff /* collect statistics information */
1359f8919bdaSduboff dp->stats.errrcv++;
1360f8919bdaSduboff
1361f8919bdaSduboff if (status & CMDSTS_RXO) {
1362f8919bdaSduboff dp->stats.overflow++;
1363f8919bdaSduboff } else if (status & (CMDSTS_LONG | CMDSTS_MORE)) {
1364f8919bdaSduboff dp->stats.frame_too_long++;
1365f8919bdaSduboff } else if (status & CMDSTS_RUNT) {
1366f8919bdaSduboff dp->stats.runt++;
1367f8919bdaSduboff } else if (status & (CMDSTS_ISE | CMDSTS_FAE)) {
1368f8919bdaSduboff dp->stats.frame++;
1369f8919bdaSduboff } else if (status & CMDSTS_CRCE) {
1370f8919bdaSduboff dp->stats.crc++;
1371f8919bdaSduboff } else {
1372f8919bdaSduboff dp->stats.rcv_internal_err++;
1373f8919bdaSduboff }
1374f8919bdaSduboff
1375f8919bdaSduboff return (flag | GEM_RX_ERR);
1376f8919bdaSduboff }
1377f8919bdaSduboff
1378f8919bdaSduboff /*
1379f8919bdaSduboff * this packet was received without errors
1380f8919bdaSduboff */
1381f8919bdaSduboff if ((len = (status & CMDSTS_SIZE)) >= ETHERFCSL) {
1382f8919bdaSduboff len -= ETHERFCSL;
1383f8919bdaSduboff }
1384f8919bdaSduboff
1385f8919bdaSduboff #if DEBUG_LEVEL > 10
1386f8919bdaSduboff {
1387f8919bdaSduboff int i;
1388f8919bdaSduboff uint8_t *bp = dp->rx_buf_head->rxb_buf;
1389f8919bdaSduboff
1390f8919bdaSduboff cmn_err(CE_CONT, CONS "%s: len:%d", dp->name, len);
1391f8919bdaSduboff
1392f8919bdaSduboff for (i = 0; i < 60; i += 10) {
1393f8919bdaSduboff cmn_err(CE_CONT, CONS
1394f8919bdaSduboff "%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1395f8919bdaSduboff bp[0], bp[1], bp[2], bp[3], bp[4],
1396f8919bdaSduboff bp[5], bp[6], bp[7], bp[8], bp[9]);
1397f8919bdaSduboff }
1398f8919bdaSduboff bp += 10;
1399f8919bdaSduboff }
1400f8919bdaSduboff #endif
1401f8919bdaSduboff return (flag | (len & GEM_RX_LEN));
1402f8919bdaSduboff }
1403f8919bdaSduboff
1404f8919bdaSduboff static void
sfe_tx_desc_init(struct gem_dev * dp,int slot)1405f8919bdaSduboff sfe_tx_desc_init(struct gem_dev *dp, int slot)
1406f8919bdaSduboff {
140723d366e3Sduboff uint_t tx_ring_size = dp->gc.gc_tx_ring_size;
1408f8919bdaSduboff struct sfe_desc *tdp;
1409f8919bdaSduboff uint32_t here;
1410f8919bdaSduboff
1411f8919bdaSduboff tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot];
1412f8919bdaSduboff
1413f8919bdaSduboff /* don't clear d_link field, which have a valid pointer */
1414f8919bdaSduboff tdp->d_cmdsts = 0;
1415f8919bdaSduboff
1416f8919bdaSduboff /* make a link to this from the previous descriptor */
1417f8919bdaSduboff here = ((uint32_t)dp->tx_ring_dma) + SFE_DESC_SIZE*slot;
1418f8919bdaSduboff
1419f8919bdaSduboff tdp = (void *)
142023d366e3Sduboff &dp->tx_ring[SFE_DESC_SIZE * SLOT(slot - 1, tx_ring_size)];
1421f8919bdaSduboff tdp->d_link = LE_32(here);
1422f8919bdaSduboff }
1423f8919bdaSduboff
1424f8919bdaSduboff static void
sfe_rx_desc_init(struct gem_dev * dp,int slot)1425f8919bdaSduboff sfe_rx_desc_init(struct gem_dev *dp, int slot)
1426f8919bdaSduboff {
142723d366e3Sduboff uint_t rx_ring_size = dp->gc.gc_rx_ring_size;
1428f8919bdaSduboff struct sfe_desc *rdp;
1429f8919bdaSduboff uint32_t here;
1430f8919bdaSduboff
1431f8919bdaSduboff rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1432f8919bdaSduboff
1433f8919bdaSduboff /* don't clear d_link field, which have a valid pointer */
1434f8919bdaSduboff rdp->d_cmdsts = LE_32(CMDSTS_OWN);
1435f8919bdaSduboff
1436f8919bdaSduboff /* make a link to this from the previous descriptor */
1437f8919bdaSduboff here = ((uint32_t)dp->rx_ring_dma) + SFE_DESC_SIZE*slot;
1438f8919bdaSduboff
1439f8919bdaSduboff rdp = (void *)
144023d366e3Sduboff &dp->rx_ring[SFE_DESC_SIZE * SLOT(slot - 1, rx_ring_size)];
1441f8919bdaSduboff rdp->d_link = LE_32(here);
1442f8919bdaSduboff }
1443f8919bdaSduboff
1444f8919bdaSduboff static void
sfe_tx_desc_clean(struct gem_dev * dp,int slot)1445f8919bdaSduboff sfe_tx_desc_clean(struct gem_dev *dp, int slot)
1446f8919bdaSduboff {
1447f8919bdaSduboff struct sfe_desc *tdp;
1448f8919bdaSduboff
1449f8919bdaSduboff tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot];
1450f8919bdaSduboff tdp->d_cmdsts = 0;
1451f8919bdaSduboff }
1452f8919bdaSduboff
1453f8919bdaSduboff static void
sfe_rx_desc_clean(struct gem_dev * dp,int slot)1454f8919bdaSduboff sfe_rx_desc_clean(struct gem_dev *dp, int slot)
1455f8919bdaSduboff {
1456f8919bdaSduboff struct sfe_desc *rdp;
1457f8919bdaSduboff
1458f8919bdaSduboff rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1459f8919bdaSduboff rdp->d_cmdsts = LE_32(CMDSTS_OWN);
1460f8919bdaSduboff }
1461f8919bdaSduboff
1462f8919bdaSduboff /*
1463f8919bdaSduboff * Device depend interrupt handler
1464f8919bdaSduboff */
1465f8919bdaSduboff static uint_t
sfe_interrupt(struct gem_dev * dp)1466f8919bdaSduboff sfe_interrupt(struct gem_dev *dp)
1467f8919bdaSduboff {
146823d366e3Sduboff uint_t rx_ring_size = dp->gc.gc_rx_ring_size;
1469f8919bdaSduboff uint32_t isr;
147023d366e3Sduboff uint32_t isr_bogus;
1471f8919bdaSduboff uint_t flags = 0;
1472f8919bdaSduboff boolean_t need_to_reset = B_FALSE;
1473f8919bdaSduboff struct sfe_dev *lp = dp->private;
1474f8919bdaSduboff
1475f8919bdaSduboff /* read reason and clear interrupt */
1476f8919bdaSduboff isr = INL(dp, ISR);
1477f8919bdaSduboff
147823d366e3Sduboff isr_bogus = lp->isr_pended;
147923d366e3Sduboff lp->isr_pended = 0;
148023d366e3Sduboff
148123d366e3Sduboff if (((isr | isr_bogus) & lp->our_intr_bits) == 0) {
1482f8919bdaSduboff /* we are not the interrupt source */
1483f8919bdaSduboff return (DDI_INTR_UNCLAIMED);
1484f8919bdaSduboff }
1485f8919bdaSduboff
1486f8919bdaSduboff DPRINTF(3, (CE_CONT,
1487f8919bdaSduboff CONS "%s: time:%ld %s:called: isr:0x%b rx_active_head: %d",
1488f8919bdaSduboff dp->name, ddi_get_lbolt(), __func__,
1489f8919bdaSduboff isr, INTR_BITS, dp->rx_active_head));
1490f8919bdaSduboff
1491f8919bdaSduboff if (!dp->mac_active) {
1492f8919bdaSduboff /* the device is going to stop */
1493f8919bdaSduboff lp->our_intr_bits = 0;
1494f8919bdaSduboff return (DDI_INTR_CLAIMED);
1495f8919bdaSduboff }
1496f8919bdaSduboff
1497f8919bdaSduboff isr &= lp->our_intr_bits;
1498f8919bdaSduboff
1499f8919bdaSduboff if (isr & (ISR_RXSOVR | ISR_RXORN | ISR_RXIDLE | ISR_RXERR |
1500f8919bdaSduboff ISR_RXDESC | ISR_RXOK)) {
1501f8919bdaSduboff (void) gem_receive(dp);
1502f8919bdaSduboff
1503f8919bdaSduboff if (isr & (ISR_RXSOVR | ISR_RXORN)) {
1504f8919bdaSduboff DPRINTF(0, (CE_CONT,
1505f8919bdaSduboff CONS "%s: rx fifo overrun: isr %b",
1506f8919bdaSduboff dp->name, isr, INTR_BITS));
1507f8919bdaSduboff /* no need restart rx */
1508f8919bdaSduboff dp->stats.overflow++;
1509f8919bdaSduboff }
1510f8919bdaSduboff
1511f8919bdaSduboff if (isr & ISR_RXIDLE) {
1512f8919bdaSduboff DPRINTF(0, (CE_CONT,
1513f8919bdaSduboff CONS "%s: rx buffer ran out: isr %b",
1514f8919bdaSduboff dp->name, isr, INTR_BITS));
1515f8919bdaSduboff
1516f8919bdaSduboff dp->stats.norcvbuf++;
1517f8919bdaSduboff
1518f8919bdaSduboff /*
1519f8919bdaSduboff * Make RXDP points the head of receive
1520f8919bdaSduboff * buffer list.
1521f8919bdaSduboff */
1522f8919bdaSduboff OUTL(dp, RXDP, dp->rx_ring_dma +
1523f8919bdaSduboff SFE_DESC_SIZE *
152423d366e3Sduboff SLOT(dp->rx_active_head, rx_ring_size));
1525f8919bdaSduboff
1526f8919bdaSduboff /* Restart the receive engine */
1527f8919bdaSduboff OUTL(dp, CR, lp->cr | CR_RXE);
1528f8919bdaSduboff }
1529f8919bdaSduboff }
1530f8919bdaSduboff
1531f8919bdaSduboff if (isr & (ISR_TXURN | ISR_TXERR | ISR_TXDESC |
1532f8919bdaSduboff ISR_TXIDLE | ISR_TXOK)) {
1533f8919bdaSduboff /* need to reclaim tx buffers */
1534f8919bdaSduboff if (gem_tx_done(dp)) {
1535f8919bdaSduboff flags |= INTR_RESTART_TX;
1536f8919bdaSduboff }
1537f8919bdaSduboff /*
1538f8919bdaSduboff * XXX - tx error statistics will be counted in
1539f8919bdaSduboff * sfe_tx_desc_stat() and no need to restart tx on errors.
1540f8919bdaSduboff */
1541f8919bdaSduboff }
1542f8919bdaSduboff
1543f8919bdaSduboff if (isr & (ISR_DPERR | ISR_SSERR | ISR_RMABT | ISR_RTABT)) {
1544f8919bdaSduboff cmn_err(CE_WARN, "%s: ERROR interrupt: isr %b.",
1545f8919bdaSduboff dp->name, isr, INTR_BITS);
1546f8919bdaSduboff need_to_reset = B_TRUE;
1547f8919bdaSduboff }
1548f8919bdaSduboff reset:
1549f8919bdaSduboff if (need_to_reset) {
1550f8919bdaSduboff (void) gem_restart_nic(dp, GEM_RESTART_KEEP_BUF);
1551f8919bdaSduboff flags |= INTR_RESTART_TX;
1552f8919bdaSduboff }
1553f8919bdaSduboff
1554f8919bdaSduboff DPRINTF(5, (CE_CONT, CONS "%s: %s: return: isr: %b",
1555f8919bdaSduboff dp->name, __func__, isr, INTR_BITS));
1556f8919bdaSduboff
1557f8919bdaSduboff return (DDI_INTR_CLAIMED | flags);
1558f8919bdaSduboff }
1559f8919bdaSduboff
1560f8919bdaSduboff /* ======================================================== */
1561f8919bdaSduboff /*
1562f8919bdaSduboff * HW depend MII routine
1563f8919bdaSduboff */
1564f8919bdaSduboff /* ======================================================== */
1565f8919bdaSduboff
1566f8919bdaSduboff /*
1567f8919bdaSduboff * MII routines for NS DP83815
1568f8919bdaSduboff */
1569f8919bdaSduboff static void
sfe_mii_sync_dp83815(struct gem_dev * dp)1570f8919bdaSduboff sfe_mii_sync_dp83815(struct gem_dev *dp)
1571f8919bdaSduboff {
1572f8919bdaSduboff /* do nothing */
1573f8919bdaSduboff }
1574f8919bdaSduboff
1575f8919bdaSduboff static uint16_t
sfe_mii_read_dp83815(struct gem_dev * dp,uint_t offset)1576f8919bdaSduboff sfe_mii_read_dp83815(struct gem_dev *dp, uint_t offset)
1577f8919bdaSduboff {
1578f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS"%s: %s: offset 0x%x",
1579f8919bdaSduboff dp->name, __func__, offset));
1580f8919bdaSduboff return ((uint16_t)INL(dp, MII_REGS_BASE + offset*4));
1581f8919bdaSduboff }
1582f8919bdaSduboff
1583f8919bdaSduboff static void
sfe_mii_write_dp83815(struct gem_dev * dp,uint_t offset,uint16_t val)1584f8919bdaSduboff sfe_mii_write_dp83815(struct gem_dev *dp, uint_t offset, uint16_t val)
1585f8919bdaSduboff {
1586f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS"%s: %s: offset 0x%x 0x%x",
1587f8919bdaSduboff dp->name, __func__, offset, val));
1588f8919bdaSduboff OUTL(dp, MII_REGS_BASE + offset*4, val);
1589f8919bdaSduboff }
1590f8919bdaSduboff
1591f8919bdaSduboff static int
sfe_mii_config_dp83815(struct gem_dev * dp)1592f8919bdaSduboff sfe_mii_config_dp83815(struct gem_dev *dp)
1593f8919bdaSduboff {
1594f8919bdaSduboff uint32_t srr;
1595f8919bdaSduboff
1596f8919bdaSduboff srr = INL(dp, SRR) & SRR_REV;
1597f8919bdaSduboff
1598f8919bdaSduboff DPRINTF(0, (CE_CONT, CONS "%s: srr:0x%04x %04x %04x %04x %04x %04x",
1599f8919bdaSduboff dp->name, srr,
1600f8919bdaSduboff INW(dp, 0x00cc), /* PGSEL */
1601f8919bdaSduboff INW(dp, 0x00e4), /* PMDCSR */
1602f8919bdaSduboff INW(dp, 0x00fc), /* TSTDAT */
1603f8919bdaSduboff INW(dp, 0x00f4), /* DSPCFG */
1604f8919bdaSduboff INW(dp, 0x00f8))); /* SDCFG */
1605f8919bdaSduboff
160623d366e3Sduboff if (srr == SRR_REV_DP83815CVNG) {
1607f8919bdaSduboff /*
1608f8919bdaSduboff * NS datasheet says that DP83815CVNG needs following
1609f8919bdaSduboff * registers to be patched for optimizing its performance.
161023d366e3Sduboff * A report said that CRC errors on RX disappeared
1611f8919bdaSduboff * with the patch.
1612f8919bdaSduboff */
1613f8919bdaSduboff OUTW(dp, 0x00cc, 0x0001); /* PGSEL */
1614f8919bdaSduboff OUTW(dp, 0x00e4, 0x189c); /* PMDCSR */
1615f8919bdaSduboff OUTW(dp, 0x00fc, 0x0000); /* TSTDAT */
1616f8919bdaSduboff OUTW(dp, 0x00f4, 0x5040); /* DSPCFG */
1617f8919bdaSduboff OUTW(dp, 0x00f8, 0x008c); /* SDCFG */
161823d366e3Sduboff OUTW(dp, 0x00cc, 0x0000); /* PGSEL */
1619f8919bdaSduboff
1620f8919bdaSduboff DPRINTF(0, (CE_CONT,
1621f8919bdaSduboff CONS "%s: PHY patched %04x %04x %04x %04x %04x",
1622f8919bdaSduboff dp->name,
1623f8919bdaSduboff INW(dp, 0x00cc), /* PGSEL */
1624f8919bdaSduboff INW(dp, 0x00e4), /* PMDCSR */
1625f8919bdaSduboff INW(dp, 0x00fc), /* TSTDAT */
1626f8919bdaSduboff INW(dp, 0x00f4), /* DSPCFG */
1627f8919bdaSduboff INW(dp, 0x00f8))); /* SDCFG */
162823d366e3Sduboff } else if (((srr ^ SRR_REV_DP83815DVNG) & 0xff00) == 0 ||
162923d366e3Sduboff ((srr ^ SRR_REV_DP83816AVNG) & 0xff00) == 0) {
163023d366e3Sduboff /*
163123d366e3Sduboff * Additional packets for later chipset
163223d366e3Sduboff */
163323d366e3Sduboff OUTW(dp, 0x00cc, 0x0001); /* PGSEL */
163423d366e3Sduboff OUTW(dp, 0x00e4, 0x189c); /* PMDCSR */
163523d366e3Sduboff OUTW(dp, 0x00cc, 0x0000); /* PGSEL */
163623d366e3Sduboff
163723d366e3Sduboff DPRINTF(0, (CE_CONT,
163823d366e3Sduboff CONS "%s: PHY patched %04x %04x",
163923d366e3Sduboff dp->name,
164023d366e3Sduboff INW(dp, 0x00cc), /* PGSEL */
164123d366e3Sduboff INW(dp, 0x00e4))); /* PMDCSR */
1642f8919bdaSduboff }
1643f8919bdaSduboff
1644f8919bdaSduboff return (gem_mii_config_default(dp));
1645f8919bdaSduboff }
1646f8919bdaSduboff
164723d366e3Sduboff static int
sfe_mii_probe_dp83815(struct gem_dev * dp)164823d366e3Sduboff sfe_mii_probe_dp83815(struct gem_dev *dp)
164923d366e3Sduboff {
165023d366e3Sduboff uint32_t val;
165123d366e3Sduboff
165223d366e3Sduboff /* try external phy first */
165323d366e3Sduboff DPRINTF(0, (CE_CONT, CONS "%s: %s: trying external phy",
165423d366e3Sduboff dp->name, __func__));
165523d366e3Sduboff dp->mii_phy_addr = 0;
165623d366e3Sduboff dp->gc.gc_mii_sync = &sfe_mii_sync_sis900;
165723d366e3Sduboff dp->gc.gc_mii_read = &sfe_mii_read_sis900;
165823d366e3Sduboff dp->gc.gc_mii_write = &sfe_mii_write_sis900;
165923d366e3Sduboff
166023d366e3Sduboff val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
166123d366e3Sduboff OUTL(dp, CFG, val | CFG_EXT_PHY | CFG_PHY_DIS);
166223d366e3Sduboff
166323d366e3Sduboff if (gem_mii_probe_default(dp) == GEM_SUCCESS) {
166423d366e3Sduboff return (GEM_SUCCESS);
166523d366e3Sduboff }
166623d366e3Sduboff
166723d366e3Sduboff /* switch to internal phy */
166823d366e3Sduboff DPRINTF(0, (CE_CONT, CONS "%s: %s: switching to internal phy",
166923d366e3Sduboff dp->name, __func__));
167023d366e3Sduboff dp->mii_phy_addr = -1;
167123d366e3Sduboff dp->gc.gc_mii_sync = &sfe_mii_sync_dp83815;
167223d366e3Sduboff dp->gc.gc_mii_read = &sfe_mii_read_dp83815;
167323d366e3Sduboff dp->gc.gc_mii_write = &sfe_mii_write_dp83815;
167423d366e3Sduboff
167523d366e3Sduboff val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
167623d366e3Sduboff OUTL(dp, CFG, val | CFG_PAUSE_ADV | CFG_PHY_RST);
167723d366e3Sduboff drv_usecwait(100); /* keep to assert RST bit for a while */
167823d366e3Sduboff OUTL(dp, CFG, val | CFG_PAUSE_ADV);
167923d366e3Sduboff
168023d366e3Sduboff /* wait for PHY reset */
168123d366e3Sduboff delay(drv_usectohz(10000));
168223d366e3Sduboff
168323d366e3Sduboff return (gem_mii_probe_default(dp));
168423d366e3Sduboff }
168523d366e3Sduboff
168623d366e3Sduboff static int
sfe_mii_init_dp83815(struct gem_dev * dp)168723d366e3Sduboff sfe_mii_init_dp83815(struct gem_dev *dp)
168823d366e3Sduboff {
168923d366e3Sduboff uint32_t val;
169023d366e3Sduboff
169123d366e3Sduboff val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
169223d366e3Sduboff
169323d366e3Sduboff if (dp->mii_phy_addr == -1) {
169423d366e3Sduboff /* select internal phy */
169523d366e3Sduboff OUTL(dp, CFG, val | CFG_PAUSE_ADV);
169623d366e3Sduboff } else {
169723d366e3Sduboff /* select external phy */
169823d366e3Sduboff OUTL(dp, CFG, val | CFG_EXT_PHY | CFG_PHY_DIS);
169923d366e3Sduboff }
170023d366e3Sduboff
170123d366e3Sduboff return (GEM_SUCCESS);
170223d366e3Sduboff }
1703f8919bdaSduboff
1704f8919bdaSduboff /*
1705f8919bdaSduboff * MII routines for SiS900
1706f8919bdaSduboff */
170723d366e3Sduboff #define MDIO_DELAY(dp) {(void) INL(dp, MEAR); (void) INL(dp, MEAR); }
1708f8919bdaSduboff static void
sfe_mii_sync_sis900(struct gem_dev * dp)1709f8919bdaSduboff sfe_mii_sync_sis900(struct gem_dev *dp)
1710f8919bdaSduboff {
1711f8919bdaSduboff int i;
1712f8919bdaSduboff
171323d366e3Sduboff /* send 32 ONE's to make MII line idle */
1714f8919bdaSduboff for (i = 0; i < 32; i++) {
1715f8919bdaSduboff OUTL(dp, MEAR, MEAR_MDDIR | MEAR_MDIO);
1716f8919bdaSduboff MDIO_DELAY(dp);
1717f8919bdaSduboff OUTL(dp, MEAR, MEAR_MDDIR | MEAR_MDIO | MEAR_MDC);
1718f8919bdaSduboff MDIO_DELAY(dp);
1719f8919bdaSduboff }
1720f8919bdaSduboff }
1721f8919bdaSduboff
1722f8919bdaSduboff static int
sfe_mii_config_sis900(struct gem_dev * dp)1723f8919bdaSduboff sfe_mii_config_sis900(struct gem_dev *dp)
1724f8919bdaSduboff {
1725f8919bdaSduboff struct sfe_dev *lp = dp->private;
1726f8919bdaSduboff
1727f8919bdaSduboff /* Do chip depend setup */
1728f8919bdaSduboff if ((dp->mii_phy_id & PHY_MASK) == PHY_ICS1893) {
1729f8919bdaSduboff /* workaround for ICS1893 PHY */
1730f8919bdaSduboff gem_mii_write(dp, 0x0018, 0xD200);
1731f8919bdaSduboff }
1732f8919bdaSduboff
1733f8919bdaSduboff if (lp->revid == SIS630E_900_REV) {
1734f8919bdaSduboff /*
1735f8919bdaSduboff * SiS 630E has bugs on default values
1736f8919bdaSduboff * of PHY registers
1737f8919bdaSduboff */
1738f8919bdaSduboff gem_mii_write(dp, MII_AN_ADVERT, 0x05e1);
1739f8919bdaSduboff gem_mii_write(dp, MII_CONFIG1, 0x0022);
1740f8919bdaSduboff gem_mii_write(dp, MII_CONFIG2, 0xff00);
1741f8919bdaSduboff gem_mii_write(dp, MII_MASK, 0xffc0);
1742f8919bdaSduboff }
1743f8919bdaSduboff sfe_set_eq_sis630(dp);
1744f8919bdaSduboff
1745f8919bdaSduboff return (gem_mii_config_default(dp));
1746f8919bdaSduboff }
1747f8919bdaSduboff
1748f8919bdaSduboff static uint16_t
sfe_mii_read_sis900(struct gem_dev * dp,uint_t reg)1749f8919bdaSduboff sfe_mii_read_sis900(struct gem_dev *dp, uint_t reg)
1750f8919bdaSduboff {
1751f8919bdaSduboff uint32_t cmd;
1752f8919bdaSduboff uint16_t ret;
1753f8919bdaSduboff int i;
1754f8919bdaSduboff uint32_t data;
1755f8919bdaSduboff
1756f8919bdaSduboff cmd = MII_READ_CMD(dp->mii_phy_addr, reg);
1757f8919bdaSduboff
1758f8919bdaSduboff for (i = 31; i >= 18; i--) {
1759f8919bdaSduboff data = ((cmd >> i) & 1) << MEAR_MDIO_SHIFT;
1760f8919bdaSduboff OUTL(dp, MEAR, data | MEAR_MDDIR);
1761f8919bdaSduboff MDIO_DELAY(dp);
1762f8919bdaSduboff OUTL(dp, MEAR, data | MEAR_MDDIR | MEAR_MDC);
1763f8919bdaSduboff MDIO_DELAY(dp);
1764f8919bdaSduboff }
1765f8919bdaSduboff
1766f8919bdaSduboff /* turn around cycle */
176723d366e3Sduboff OUTL(dp, MEAR, 0);
1768f8919bdaSduboff MDIO_DELAY(dp);
1769f8919bdaSduboff
1770f8919bdaSduboff /* get response from PHY */
1771f8919bdaSduboff OUTL(dp, MEAR, MEAR_MDC);
1772f8919bdaSduboff MDIO_DELAY(dp);
1773f8919bdaSduboff
177423d366e3Sduboff OUTL(dp, MEAR, 0);
1775f8919bdaSduboff #if DEBUG_LEBEL > 0
177623d366e3Sduboff (void) INL(dp, MEAR); /* delay */
1777f8919bdaSduboff if (INL(dp, MEAR) & MEAR_MDIO) {
1778f8919bdaSduboff cmn_err(CE_WARN, "%s: PHY@%d not responded",
1779f8919bdaSduboff dp->name, dp->mii_phy_addr);
1780f8919bdaSduboff }
178123d366e3Sduboff #else
178223d366e3Sduboff MDIO_DELAY(dp);
1783f8919bdaSduboff #endif
1784f8919bdaSduboff /* terminate response cycle */
1785f8919bdaSduboff OUTL(dp, MEAR, MEAR_MDC);
178623d366e3Sduboff MDIO_DELAY(dp);
1787f8919bdaSduboff
1788f8919bdaSduboff ret = 0; /* to avoid lint errors */
1789f8919bdaSduboff for (i = 16; i > 0; i--) {
1790f8919bdaSduboff OUTL(dp, MEAR, 0);
179123d366e3Sduboff (void) INL(dp, MEAR); /* delay */
1792f8919bdaSduboff ret = (ret << 1) | ((INL(dp, MEAR) >> MEAR_MDIO_SHIFT) & 1);
1793f8919bdaSduboff OUTL(dp, MEAR, MEAR_MDC);
1794f8919bdaSduboff MDIO_DELAY(dp);
1795f8919bdaSduboff }
1796f8919bdaSduboff
179723d366e3Sduboff /* send two idle(Z) bits to terminate the read cycle */
179823d366e3Sduboff for (i = 0; i < 2; i++) {
179923d366e3Sduboff OUTL(dp, MEAR, 0);
180023d366e3Sduboff MDIO_DELAY(dp);
180123d366e3Sduboff OUTL(dp, MEAR, MEAR_MDC);
180223d366e3Sduboff MDIO_DELAY(dp);
180323d366e3Sduboff }
1804f8919bdaSduboff
1805f8919bdaSduboff return (ret);
1806f8919bdaSduboff }
1807f8919bdaSduboff
1808f8919bdaSduboff static void
sfe_mii_write_sis900(struct gem_dev * dp,uint_t reg,uint16_t val)1809f8919bdaSduboff sfe_mii_write_sis900(struct gem_dev *dp, uint_t reg, uint16_t val)
1810f8919bdaSduboff {
1811f8919bdaSduboff uint32_t cmd;
1812f8919bdaSduboff int i;
1813f8919bdaSduboff uint32_t data;
1814f8919bdaSduboff
1815f8919bdaSduboff cmd = MII_WRITE_CMD(dp->mii_phy_addr, reg, val);
1816f8919bdaSduboff
1817f8919bdaSduboff for (i = 31; i >= 0; i--) {
1818f8919bdaSduboff data = ((cmd >> i) & 1) << MEAR_MDIO_SHIFT;
1819f8919bdaSduboff OUTL(dp, MEAR, data | MEAR_MDDIR);
1820f8919bdaSduboff MDIO_DELAY(dp);
1821f8919bdaSduboff OUTL(dp, MEAR, data | MEAR_MDDIR | MEAR_MDC);
1822f8919bdaSduboff MDIO_DELAY(dp);
1823f8919bdaSduboff }
1824f8919bdaSduboff
182523d366e3Sduboff /* send two idle(Z) bits to terminate the write cycle. */
1826f8919bdaSduboff for (i = 0; i < 2; i++) {
182723d366e3Sduboff OUTL(dp, MEAR, 0);
1828f8919bdaSduboff MDIO_DELAY(dp);
182923d366e3Sduboff OUTL(dp, MEAR, MEAR_MDC);
1830f8919bdaSduboff MDIO_DELAY(dp);
1831f8919bdaSduboff }
1832f8919bdaSduboff }
1833f8919bdaSduboff #undef MDIO_DELAY
1834f8919bdaSduboff
1835f8919bdaSduboff static void
sfe_set_eq_sis630(struct gem_dev * dp)1836f8919bdaSduboff sfe_set_eq_sis630(struct gem_dev *dp)
1837f8919bdaSduboff {
1838f8919bdaSduboff uint16_t reg14h;
1839f8919bdaSduboff uint16_t eq_value;
1840f8919bdaSduboff uint16_t max_value;
1841f8919bdaSduboff uint16_t min_value;
1842f8919bdaSduboff int i;
1843f8919bdaSduboff uint8_t rev;
1844f8919bdaSduboff struct sfe_dev *lp = dp->private;
1845f8919bdaSduboff
1846f8919bdaSduboff rev = lp->revid;
1847f8919bdaSduboff
1848f8919bdaSduboff if (!(rev == SIS630E_900_REV || rev == SIS630EA1_900_REV ||
1849f8919bdaSduboff rev == SIS630A_900_REV || rev == SIS630ET_900_REV)) {
1850f8919bdaSduboff /* it doesn't have a internal PHY */
1851f8919bdaSduboff return;
1852f8919bdaSduboff }
1853f8919bdaSduboff
1854f8919bdaSduboff if (dp->mii_state == MII_STATE_LINKUP) {
1855f8919bdaSduboff reg14h = gem_mii_read(dp, MII_RESV);
1856f8919bdaSduboff gem_mii_write(dp, MII_RESV, (0x2200 | reg14h) & 0xBFFF);
1857f8919bdaSduboff
1858f8919bdaSduboff eq_value = (0x00f8 & gem_mii_read(dp, MII_RESV)) >> 3;
1859f8919bdaSduboff max_value = min_value = eq_value;
1860f8919bdaSduboff for (i = 1; i < 10; i++) {
1861f8919bdaSduboff eq_value = (0x00f8 & gem_mii_read(dp, MII_RESV)) >> 3;
1862f8919bdaSduboff max_value = max(eq_value, max_value);
1863f8919bdaSduboff min_value = min(eq_value, min_value);
1864f8919bdaSduboff }
1865f8919bdaSduboff
1866f8919bdaSduboff /* for 630E, rule to determine the equalizer value */
1867f8919bdaSduboff if (rev == SIS630E_900_REV || rev == SIS630EA1_900_REV ||
1868f8919bdaSduboff rev == SIS630ET_900_REV) {
1869f8919bdaSduboff if (max_value < 5) {
1870f8919bdaSduboff eq_value = max_value;
1871f8919bdaSduboff } else if (5 <= max_value && max_value < 15) {
1872f8919bdaSduboff eq_value =
1873f8919bdaSduboff max(max_value + 1,
1874f8919bdaSduboff min_value + 2);
1875f8919bdaSduboff } else if (15 <= max_value) {
1876f8919bdaSduboff eq_value =
1877f8919bdaSduboff max(max_value + 5,
1878f8919bdaSduboff min_value + 6);
1879f8919bdaSduboff }
1880f8919bdaSduboff }
1881f8919bdaSduboff /* for 630B0&B1, rule to determine the equalizer value */
1882f8919bdaSduboff else
1883f8919bdaSduboff if (rev == SIS630A_900_REV &&
1884f8919bdaSduboff (lp->bridge_revid == SIS630B0 ||
1885f8919bdaSduboff lp->bridge_revid == SIS630B1)) {
1886f8919bdaSduboff
1887f8919bdaSduboff if (max_value == 0) {
1888f8919bdaSduboff eq_value = 3;
1889f8919bdaSduboff } else {
1890f8919bdaSduboff eq_value = (max_value + min_value + 1)/2;
1891f8919bdaSduboff }
1892f8919bdaSduboff }
1893f8919bdaSduboff /* write equalizer value and setting */
1894f8919bdaSduboff reg14h = gem_mii_read(dp, MII_RESV) & ~0x02f8;
1895f8919bdaSduboff reg14h |= 0x6000 | (eq_value << 3);
1896f8919bdaSduboff gem_mii_write(dp, MII_RESV, reg14h);
1897f8919bdaSduboff } else {
1898f8919bdaSduboff reg14h = (gem_mii_read(dp, MII_RESV) & ~0x4000) | 0x2000;
1899f8919bdaSduboff if (rev == SIS630A_900_REV &&
1900f8919bdaSduboff (lp->bridge_revid == SIS630B0 ||
1901f8919bdaSduboff lp->bridge_revid == SIS630B1)) {
1902f8919bdaSduboff
1903f8919bdaSduboff reg14h |= 0x0200;
1904f8919bdaSduboff }
1905f8919bdaSduboff gem_mii_write(dp, MII_RESV, reg14h);
1906f8919bdaSduboff }
1907f8919bdaSduboff }
1908f8919bdaSduboff
1909f8919bdaSduboff /* ======================================================== */
1910f8919bdaSduboff /*
1911f8919bdaSduboff * OS depend (device driver) routine
1912f8919bdaSduboff */
1913f8919bdaSduboff /* ======================================================== */
1914f8919bdaSduboff static void
sfe_chipinfo_init_sis900(struct gem_dev * dp)1915f8919bdaSduboff sfe_chipinfo_init_sis900(struct gem_dev *dp)
1916f8919bdaSduboff {
1917f8919bdaSduboff int rev;
1918f8919bdaSduboff struct sfe_dev *lp = (struct sfe_dev *)dp->private;
1919f8919bdaSduboff
1920f8919bdaSduboff rev = lp->revid;
1921f8919bdaSduboff
1922*3b8e6442SToomas Soome if (rev == SIS962_900_REV /* 0x91 */) {
1923f8919bdaSduboff /* sis962 or later */
1924f8919bdaSduboff lp->get_mac_addr = &sfe_get_mac_addr_sis962;
1925f8919bdaSduboff } else {
1926f8919bdaSduboff /* sis900 */
1927f8919bdaSduboff lp->get_mac_addr = &sfe_get_mac_addr_sis900;
1928f8919bdaSduboff }
1929f8919bdaSduboff
1930f8919bdaSduboff lp->bridge_revid = 0;
1931f8919bdaSduboff
1932f8919bdaSduboff if (rev == SIS630E_900_REV || rev == SIS630EA1_900_REV ||
1933f8919bdaSduboff rev == SIS630A_900_REV || rev == SIS630ET_900_REV) {
1934f8919bdaSduboff /*
1935f8919bdaSduboff * read host bridge revision
1936f8919bdaSduboff */
1937f8919bdaSduboff dev_info_t *bridge;
1938f8919bdaSduboff ddi_acc_handle_t bridge_handle;
1939f8919bdaSduboff
1940f8919bdaSduboff if ((bridge = sfe_search_pci_dev(0x1039, 0x630)) == NULL) {
1941f8919bdaSduboff cmn_err(CE_WARN,
1942f8919bdaSduboff "%s: cannot find host bridge (pci1039,630)",
1943f8919bdaSduboff dp->name);
1944f8919bdaSduboff return;
1945f8919bdaSduboff }
1946f8919bdaSduboff
1947f8919bdaSduboff if (pci_config_setup(bridge, &bridge_handle) != DDI_SUCCESS) {
1948f8919bdaSduboff cmn_err(CE_WARN, "%s: pci_config_setup failed",
1949f8919bdaSduboff dp->name);
1950f8919bdaSduboff return;
1951f8919bdaSduboff }
1952f8919bdaSduboff
1953f8919bdaSduboff lp->bridge_revid =
1954f8919bdaSduboff pci_config_get8(bridge_handle, PCI_CONF_REVID);
1955f8919bdaSduboff pci_config_teardown(&bridge_handle);
1956f8919bdaSduboff }
1957f8919bdaSduboff }
1958f8919bdaSduboff
1959f8919bdaSduboff static int
sfe_attach_chip(struct gem_dev * dp)1960f8919bdaSduboff sfe_attach_chip(struct gem_dev *dp)
1961f8919bdaSduboff {
1962f8919bdaSduboff struct sfe_dev *lp = (struct sfe_dev *)dp->private;
1963f8919bdaSduboff
1964f8919bdaSduboff DPRINTF(4, (CE_CONT, CONS "!%s: %s called", dp->name, __func__));
1965f8919bdaSduboff
1966f8919bdaSduboff /* setup chip-depend get_mac_address function */
1967f8919bdaSduboff if (lp->chip->chip_type == CHIPTYPE_SIS900) {
1968f8919bdaSduboff sfe_chipinfo_init_sis900(dp);
1969f8919bdaSduboff } else {
1970f8919bdaSduboff lp->get_mac_addr = &sfe_get_mac_addr_dp83815;
1971f8919bdaSduboff }
1972f8919bdaSduboff
1973f8919bdaSduboff /* read MAC address */
1974f8919bdaSduboff if (!(lp->get_mac_addr)(dp)) {
1975f8919bdaSduboff cmn_err(CE_WARN,
1976f8919bdaSduboff "!%s: %s: failed to get factory mac address"
1977f8919bdaSduboff " please specify a mac address in sfe.conf",
1978f8919bdaSduboff dp->name, __func__);
1979f8919bdaSduboff return (GEM_FAILURE);
1980f8919bdaSduboff }
1981f8919bdaSduboff
1982f8919bdaSduboff if (lp->chip->chip_type == CHIPTYPE_DP83815) {
1983f8919bdaSduboff dp->mii_phy_addr = -1; /* no need to scan PHY */
1984f8919bdaSduboff dp->misc_flag |= GEM_VLAN_SOFT;
1985f8919bdaSduboff dp->txthr += 4; /* VTAG_SIZE */
1986f8919bdaSduboff }
1987f8919bdaSduboff dp->txthr = min(dp->txthr, TXFIFOSIZE - 2);
1988f8919bdaSduboff
1989f8919bdaSduboff return (GEM_SUCCESS);
1990f8919bdaSduboff }
1991f8919bdaSduboff
1992f8919bdaSduboff static int
sfeattach(dev_info_t * dip,ddi_attach_cmd_t cmd)1993f8919bdaSduboff sfeattach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1994f8919bdaSduboff {
1995f8919bdaSduboff int unit;
1996f8919bdaSduboff const char *drv_name;
1997f8919bdaSduboff int i;
1998f8919bdaSduboff ddi_acc_handle_t conf_handle;
1999f8919bdaSduboff uint16_t vid;
2000f8919bdaSduboff uint16_t did;
2001f8919bdaSduboff uint8_t rev;
2002f8919bdaSduboff #ifdef DEBUG_LEVEL
2003f8919bdaSduboff uint32_t iline;
2004f8919bdaSduboff uint8_t latim;
2005f8919bdaSduboff #endif
2006f8919bdaSduboff struct chip_info *p;
2007f8919bdaSduboff struct gem_dev *dp;
2008f8919bdaSduboff struct sfe_dev *lp;
2009f8919bdaSduboff caddr_t base;
2010f8919bdaSduboff ddi_acc_handle_t regs_ha;
2011f8919bdaSduboff struct gem_conf *gcp;
2012f8919bdaSduboff
2013f8919bdaSduboff unit = ddi_get_instance(dip);
2014f8919bdaSduboff drv_name = ddi_driver_name(dip);
2015f8919bdaSduboff
2016f8919bdaSduboff DPRINTF(3, (CE_CONT, CONS "%s%d: sfeattach: called", drv_name, unit));
2017f8919bdaSduboff
2018f8919bdaSduboff /*
2019f8919bdaSduboff * Common codes after power-up
2020f8919bdaSduboff */
2021f8919bdaSduboff if (pci_config_setup(dip, &conf_handle) != DDI_SUCCESS) {
2022f8919bdaSduboff cmn_err(CE_WARN, "%s%d: ddi_regs_map_setup failed",
2023f8919bdaSduboff drv_name, unit);
2024f8919bdaSduboff goto err;
2025f8919bdaSduboff }
2026f8919bdaSduboff
2027f8919bdaSduboff vid = pci_config_get16(conf_handle, PCI_CONF_VENID);
2028f8919bdaSduboff did = pci_config_get16(conf_handle, PCI_CONF_DEVID);
2029f8919bdaSduboff rev = pci_config_get16(conf_handle, PCI_CONF_REVID);
2030f8919bdaSduboff #ifdef DEBUG_LEVEL
203123d366e3Sduboff iline = pci_config_get32(conf_handle, PCI_CONF_ILINE);
203223d366e3Sduboff latim = pci_config_get8(conf_handle, PCI_CONF_LATENCY_TIMER);
2033f8919bdaSduboff #endif
2034f8919bdaSduboff #ifdef DEBUG_BUILT_IN_SIS900
2035f8919bdaSduboff rev = SIS630E_900_REV;
2036f8919bdaSduboff #endif
2037f8919bdaSduboff for (i = 0, p = sfe_chiptbl; i < CHIPTABLESIZE; i++, p++) {
2038f8919bdaSduboff if (p->venid == vid && p->devid == did) {
2039f8919bdaSduboff /* found */
2040f8919bdaSduboff goto chip_found;
2041f8919bdaSduboff }
2042f8919bdaSduboff }
2043f8919bdaSduboff
2044f8919bdaSduboff /* Not found */
2045f8919bdaSduboff cmn_err(CE_WARN,
2046f8919bdaSduboff "%s%d: sfe_attach: wrong PCI venid/devid (0x%x, 0x%x)",
2047f8919bdaSduboff drv_name, unit, vid, did);
2048f8919bdaSduboff pci_config_teardown(&conf_handle);
2049f8919bdaSduboff goto err;
2050f8919bdaSduboff
2051f8919bdaSduboff chip_found:
2052f8919bdaSduboff pci_config_put16(conf_handle, PCI_CONF_COMM,
2053f8919bdaSduboff PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME |
2054f8919bdaSduboff pci_config_get16(conf_handle, PCI_CONF_COMM));
2055f8919bdaSduboff
2056f8919bdaSduboff /* ensure D0 mode */
2057f8919bdaSduboff (void) gem_pci_set_power_state(dip, conf_handle, PCI_PMCSR_D0);
2058f8919bdaSduboff
2059f8919bdaSduboff pci_config_teardown(&conf_handle);
2060f8919bdaSduboff
2061f8919bdaSduboff switch (cmd) {
2062f8919bdaSduboff case DDI_RESUME:
2063f8919bdaSduboff return (gem_resume(dip));
2064f8919bdaSduboff
2065f8919bdaSduboff case DDI_ATTACH:
2066f8919bdaSduboff
2067f8919bdaSduboff DPRINTF(0, (CE_CONT,
2068f8919bdaSduboff CONS "%s%d: ilr 0x%08x, latency_timer:0x%02x",
2069f8919bdaSduboff drv_name, unit, iline, latim));
2070f8919bdaSduboff
2071f8919bdaSduboff /*
2072f8919bdaSduboff * Map in the device registers.
2073f8919bdaSduboff */
2074f8919bdaSduboff if (gem_pci_regs_map_setup(dip,
2075f8919bdaSduboff (sfe_use_pcimemspace && p->chip_type == CHIPTYPE_DP83815)
2076f8919bdaSduboff ? PCI_ADDR_MEM32 : PCI_ADDR_IO, PCI_ADDR_MASK,
2077f8919bdaSduboff &sfe_dev_attr, &base, ®s_ha) != DDI_SUCCESS) {
2078f8919bdaSduboff cmn_err(CE_WARN,
2079f8919bdaSduboff "%s%d: ddi_regs_map_setup failed",
2080f8919bdaSduboff drv_name, unit);
2081f8919bdaSduboff goto err;
2082f8919bdaSduboff }
2083f8919bdaSduboff
2084f8919bdaSduboff /*
2085f8919bdaSduboff * construct gem configuration
2086f8919bdaSduboff */
2087f8919bdaSduboff gcp = kmem_zalloc(sizeof (*gcp), KM_SLEEP);
2088f8919bdaSduboff
2089f8919bdaSduboff /* name */
2090f8919bdaSduboff (void) sprintf(gcp->gc_name, "%s%d", drv_name, unit);
2091f8919bdaSduboff
2092f8919bdaSduboff /* consistency on tx and rx */
2093f8919bdaSduboff gcp->gc_tx_buf_align = sizeof (uint8_t) - 1;
2094f8919bdaSduboff gcp->gc_tx_max_frags = MAXTXFRAGS;
2095f8919bdaSduboff gcp->gc_tx_max_descs_per_pkt = gcp->gc_tx_max_frags;
2096f8919bdaSduboff gcp->gc_tx_desc_unit_shift = 4; /* 16 byte */
2097f8919bdaSduboff gcp->gc_tx_buf_size = TX_BUF_SIZE;
2098f8919bdaSduboff gcp->gc_tx_buf_limit = gcp->gc_tx_buf_size;
2099f8919bdaSduboff gcp->gc_tx_ring_size = TX_RING_SIZE;
2100f8919bdaSduboff gcp->gc_tx_ring_limit = gcp->gc_tx_ring_size;
2101f8919bdaSduboff gcp->gc_tx_auto_pad = B_TRUE;
2102f8919bdaSduboff gcp->gc_tx_copy_thresh = sfe_tx_copy_thresh;
2103f8919bdaSduboff gcp->gc_tx_desc_write_oo = B_TRUE;
2104f8919bdaSduboff
2105f8919bdaSduboff gcp->gc_rx_buf_align = sizeof (uint8_t) - 1;
2106f8919bdaSduboff gcp->gc_rx_max_frags = MAXRXFRAGS;
2107f8919bdaSduboff gcp->gc_rx_desc_unit_shift = 4;
2108f8919bdaSduboff gcp->gc_rx_ring_size = RX_RING_SIZE;
2109f8919bdaSduboff gcp->gc_rx_buf_max = RX_BUF_SIZE;
2110f8919bdaSduboff gcp->gc_rx_copy_thresh = sfe_rx_copy_thresh;
2111f8919bdaSduboff
2112f8919bdaSduboff /* map attributes */
2113f8919bdaSduboff gcp->gc_dev_attr = sfe_dev_attr;
2114f8919bdaSduboff gcp->gc_buf_attr = sfe_buf_attr;
2115f8919bdaSduboff gcp->gc_desc_attr = sfe_buf_attr;
2116f8919bdaSduboff
2117f8919bdaSduboff /* dma attributes */
2118f8919bdaSduboff gcp->gc_dma_attr_desc = sfe_dma_attr_desc;
2119f8919bdaSduboff
2120f8919bdaSduboff gcp->gc_dma_attr_txbuf = sfe_dma_attr_buf;
2121f8919bdaSduboff gcp->gc_dma_attr_txbuf.dma_attr_align = gcp->gc_tx_buf_align+1;
2122f8919bdaSduboff gcp->gc_dma_attr_txbuf.dma_attr_sgllen = gcp->gc_tx_max_frags;
2123f8919bdaSduboff
2124f8919bdaSduboff gcp->gc_dma_attr_rxbuf = sfe_dma_attr_buf;
2125f8919bdaSduboff gcp->gc_dma_attr_rxbuf.dma_attr_align = gcp->gc_rx_buf_align+1;
2126f8919bdaSduboff gcp->gc_dma_attr_rxbuf.dma_attr_sgllen = gcp->gc_rx_max_frags;
2127f8919bdaSduboff
2128f8919bdaSduboff /* time out parameters */
2129f8919bdaSduboff gcp->gc_tx_timeout = 3*ONESEC;
2130f8919bdaSduboff gcp->gc_tx_timeout_interval = ONESEC;
213123d366e3Sduboff if (p->chip_type == CHIPTYPE_DP83815) {
213223d366e3Sduboff /* workaround for tx hang */
213323d366e3Sduboff gcp->gc_tx_timeout_interval = ONESEC/20; /* 50mS */
213423d366e3Sduboff }
2135f8919bdaSduboff
2136f8919bdaSduboff /* MII timeout parameters */
2137f8919bdaSduboff gcp->gc_mii_link_watch_interval = ONESEC;
2138f8919bdaSduboff gcp->gc_mii_an_watch_interval = ONESEC/5;
2139f8919bdaSduboff gcp->gc_mii_reset_timeout = MII_RESET_TIMEOUT; /* 1 sec */
2140f8919bdaSduboff gcp->gc_mii_an_timeout = MII_AN_TIMEOUT; /* 5 sec */
2141f8919bdaSduboff gcp->gc_mii_an_wait = 0;
2142f8919bdaSduboff gcp->gc_mii_linkdown_timeout = MII_LINKDOWN_TIMEOUT;
2143f8919bdaSduboff
2144f8919bdaSduboff /* setting for general PHY */
2145f8919bdaSduboff gcp->gc_mii_an_delay = 0;
2146f8919bdaSduboff gcp->gc_mii_linkdown_action = MII_ACTION_RSA;
2147f8919bdaSduboff gcp->gc_mii_linkdown_timeout_action = MII_ACTION_RESET;
2148f8919bdaSduboff gcp->gc_mii_dont_reset = B_FALSE;
2149f8919bdaSduboff
2150f8919bdaSduboff
2151f8919bdaSduboff /* I/O methods */
2152f8919bdaSduboff
2153f8919bdaSduboff /* mac operation */
2154f8919bdaSduboff gcp->gc_attach_chip = &sfe_attach_chip;
2155f8919bdaSduboff if (p->chip_type == CHIPTYPE_DP83815) {
2156f8919bdaSduboff gcp->gc_reset_chip = &sfe_reset_chip_dp83815;
2157f8919bdaSduboff } else {
2158f8919bdaSduboff gcp->gc_reset_chip = &sfe_reset_chip_sis900;
2159f8919bdaSduboff }
2160f8919bdaSduboff gcp->gc_init_chip = &sfe_init_chip;
2161f8919bdaSduboff gcp->gc_start_chip = &sfe_start_chip;
2162f8919bdaSduboff gcp->gc_stop_chip = &sfe_stop_chip;
2163f8919bdaSduboff #ifdef USE_MULTICAST_HASHTBL
2164f8919bdaSduboff gcp->gc_multicast_hash = &sfe_mcast_hash;
2165f8919bdaSduboff #endif
2166f8919bdaSduboff if (p->chip_type == CHIPTYPE_DP83815) {
2167f8919bdaSduboff gcp->gc_set_rx_filter = &sfe_set_rx_filter_dp83815;
2168f8919bdaSduboff } else {
2169f8919bdaSduboff gcp->gc_set_rx_filter = &sfe_set_rx_filter_sis900;
2170f8919bdaSduboff }
2171f8919bdaSduboff gcp->gc_set_media = &sfe_set_media;
2172f8919bdaSduboff gcp->gc_get_stats = &sfe_get_stats;
2173f8919bdaSduboff gcp->gc_interrupt = &sfe_interrupt;
2174f8919bdaSduboff
2175f8919bdaSduboff /* descriptor operation */
2176f8919bdaSduboff gcp->gc_tx_desc_write = &sfe_tx_desc_write;
2177f8919bdaSduboff gcp->gc_tx_start = &sfe_tx_start;
2178f8919bdaSduboff gcp->gc_rx_desc_write = &sfe_rx_desc_write;
2179f8919bdaSduboff gcp->gc_rx_start = NULL;
2180f8919bdaSduboff
2181f8919bdaSduboff gcp->gc_tx_desc_stat = &sfe_tx_desc_stat;
2182f8919bdaSduboff gcp->gc_rx_desc_stat = &sfe_rx_desc_stat;
2183f8919bdaSduboff gcp->gc_tx_desc_init = &sfe_tx_desc_init;
2184f8919bdaSduboff gcp->gc_rx_desc_init = &sfe_rx_desc_init;
2185f8919bdaSduboff gcp->gc_tx_desc_clean = &sfe_tx_desc_clean;
2186f8919bdaSduboff gcp->gc_rx_desc_clean = &sfe_rx_desc_clean;
2187f8919bdaSduboff
2188f8919bdaSduboff /* mii operations */
2189f8919bdaSduboff if (p->chip_type == CHIPTYPE_DP83815) {
219023d366e3Sduboff gcp->gc_mii_probe = &sfe_mii_probe_dp83815;
219123d366e3Sduboff gcp->gc_mii_init = &sfe_mii_init_dp83815;
2192f8919bdaSduboff gcp->gc_mii_config = &sfe_mii_config_dp83815;
2193f8919bdaSduboff gcp->gc_mii_sync = &sfe_mii_sync_dp83815;
2194f8919bdaSduboff gcp->gc_mii_read = &sfe_mii_read_dp83815;
2195f8919bdaSduboff gcp->gc_mii_write = &sfe_mii_write_dp83815;
2196f8919bdaSduboff gcp->gc_mii_tune_phy = NULL;
2197f8919bdaSduboff gcp->gc_flow_control = FLOW_CONTROL_NONE;
2198f8919bdaSduboff } else {
2199f8919bdaSduboff gcp->gc_mii_probe = &gem_mii_probe_default;
2200f8919bdaSduboff gcp->gc_mii_init = NULL;
2201f8919bdaSduboff gcp->gc_mii_config = &sfe_mii_config_sis900;
2202f8919bdaSduboff gcp->gc_mii_sync = &sfe_mii_sync_sis900;
2203f8919bdaSduboff gcp->gc_mii_read = &sfe_mii_read_sis900;
2204f8919bdaSduboff gcp->gc_mii_write = &sfe_mii_write_sis900;
2205f8919bdaSduboff gcp->gc_mii_tune_phy = &sfe_set_eq_sis630;
2206f8919bdaSduboff gcp->gc_flow_control = FLOW_CONTROL_RX_PAUSE;
2207f8919bdaSduboff }
2208f8919bdaSduboff
2209f8919bdaSduboff lp = kmem_zalloc(sizeof (*lp), KM_SLEEP);
2210f8919bdaSduboff lp->chip = p;
2211f8919bdaSduboff lp->revid = rev;
221223d366e3Sduboff lp->our_intr_bits = 0;
221323d366e3Sduboff lp->isr_pended = 0;
2214f8919bdaSduboff
2215f8919bdaSduboff cmn_err(CE_CONT, CONS "%s%d: chip:%s rev:0x%02x",
2216f8919bdaSduboff drv_name, unit, p->chip_name, rev);
2217f8919bdaSduboff
2218f8919bdaSduboff dp = gem_do_attach(dip, 0, gcp, base, ®s_ha,
2219f8919bdaSduboff lp, sizeof (*lp));
2220f8919bdaSduboff kmem_free(gcp, sizeof (*gcp));
2221f8919bdaSduboff
2222f8919bdaSduboff if (dp == NULL) {
2223f8919bdaSduboff goto err_freelp;
2224f8919bdaSduboff }
2225f8919bdaSduboff
2226f8919bdaSduboff return (DDI_SUCCESS);
2227f8919bdaSduboff
2228f8919bdaSduboff err_freelp:
2229f8919bdaSduboff kmem_free(lp, sizeof (struct sfe_dev));
2230f8919bdaSduboff err:
2231f8919bdaSduboff return (DDI_FAILURE);
2232f8919bdaSduboff }
2233f8919bdaSduboff return (DDI_FAILURE);
2234f8919bdaSduboff }
2235f8919bdaSduboff
2236f8919bdaSduboff static int
sfedetach(dev_info_t * dip,ddi_detach_cmd_t cmd)2237f8919bdaSduboff sfedetach(dev_info_t *dip, ddi_detach_cmd_t cmd)
2238f8919bdaSduboff {
2239f8919bdaSduboff switch (cmd) {
2240f8919bdaSduboff case DDI_SUSPEND:
2241f8919bdaSduboff return (gem_suspend(dip));
2242f8919bdaSduboff
2243f8919bdaSduboff case DDI_DETACH:
2244f8919bdaSduboff return (gem_do_detach(dip));
2245f8919bdaSduboff }
2246f8919bdaSduboff return (DDI_FAILURE);
2247f8919bdaSduboff }
2248f8919bdaSduboff
224953560dfaSSherry Moore /*
225053560dfaSSherry Moore * quiesce(9E) entry point.
225153560dfaSSherry Moore *
225253560dfaSSherry Moore * This function is called when the system is single-threaded at high
225353560dfaSSherry Moore * PIL with preemption disabled. Therefore, this function must not be
225453560dfaSSherry Moore * blocked.
225553560dfaSSherry Moore *
225653560dfaSSherry Moore * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
225753560dfaSSherry Moore * DDI_FAILURE indicates an error condition and should almost never happen.
225853560dfaSSherry Moore */
225953560dfaSSherry Moore #ifdef __sparc
226053560dfaSSherry Moore #define sfe_quiesce ddi_quiesce_not_supported
226153560dfaSSherry Moore #else
226253560dfaSSherry Moore static int
sfe_quiesce(dev_info_t * dip)226353560dfaSSherry Moore sfe_quiesce(dev_info_t *dip)
226453560dfaSSherry Moore {
226553560dfaSSherry Moore struct gem_dev *dp;
226653560dfaSSherry Moore int ret = 0;
226753560dfaSSherry Moore
226853560dfaSSherry Moore dp = GEM_GET_DEV(dip);
226953560dfaSSherry Moore
227053560dfaSSherry Moore if (dp == NULL)
227153560dfaSSherry Moore return (DDI_FAILURE);
227253560dfaSSherry Moore
227353560dfaSSherry Moore ret = sfe_stop_chip_quiesce(dp);
227453560dfaSSherry Moore
227553560dfaSSherry Moore return (ret);
227653560dfaSSherry Moore }
227753560dfaSSherry Moore #endif
227853560dfaSSherry Moore
2279f8919bdaSduboff /* ======================================================== */
2280f8919bdaSduboff /*
2281f8919bdaSduboff * OS depend (loadable streams driver) routine
2282f8919bdaSduboff */
2283f8919bdaSduboff /* ======================================================== */
2284f8919bdaSduboff DDI_DEFINE_STREAM_OPS(sfe_ops, nulldev, nulldev, sfeattach, sfedetach,
2285*3b8e6442SToomas Soome nodev, NULL, D_MP, NULL, sfe_quiesce);
2286f8919bdaSduboff
2287f8919bdaSduboff static struct modldrv modldrv = {
2288f8919bdaSduboff &mod_driverops, /* Type of module. This one is a driver */
2289f8919bdaSduboff ident,
2290f8919bdaSduboff &sfe_ops, /* driver ops */
2291f8919bdaSduboff };
2292f8919bdaSduboff
2293f8919bdaSduboff static struct modlinkage modlinkage = {
2294f8919bdaSduboff MODREV_1, &modldrv, NULL
2295f8919bdaSduboff };
2296f8919bdaSduboff
2297f8919bdaSduboff /* ======================================================== */
2298f8919bdaSduboff /*
2299f8919bdaSduboff * Loadable module support
2300f8919bdaSduboff */
2301f8919bdaSduboff /* ======================================================== */
2302f8919bdaSduboff int
_init(void)2303f8919bdaSduboff _init(void)
2304f8919bdaSduboff {
2305*3b8e6442SToomas Soome int status;
2306f8919bdaSduboff
2307f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "sfe: _init: called"));
2308f8919bdaSduboff gem_mod_init(&sfe_ops, "sfe");
2309f8919bdaSduboff status = mod_install(&modlinkage);
2310f8919bdaSduboff if (status != DDI_SUCCESS) {
2311f8919bdaSduboff gem_mod_fini(&sfe_ops);
2312f8919bdaSduboff }
2313f8919bdaSduboff return (status);
2314f8919bdaSduboff }
2315f8919bdaSduboff
2316f8919bdaSduboff /*
2317f8919bdaSduboff * _fini : done
2318f8919bdaSduboff */
2319f8919bdaSduboff int
_fini(void)2320f8919bdaSduboff _fini(void)
2321f8919bdaSduboff {
2322f8919bdaSduboff int status;
2323f8919bdaSduboff
2324f8919bdaSduboff DPRINTF(2, (CE_CONT, CONS "sfe: _fini: called"));
2325f8919bdaSduboff status = mod_remove(&modlinkage);
2326f8919bdaSduboff if (status == DDI_SUCCESS) {
2327f8919bdaSduboff gem_mod_fini(&sfe_ops);
2328f8919bdaSduboff }
2329f8919bdaSduboff return (status);
2330f8919bdaSduboff }
2331f8919bdaSduboff
2332f8919bdaSduboff int
_info(struct modinfo * modinfop)2333f8919bdaSduboff _info(struct modinfo *modinfop)
2334f8919bdaSduboff {
2335f8919bdaSduboff return (mod_info(&modlinkage, modinfop));
2336f8919bdaSduboff }
2337