1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 25 * Copyright (c) 2017, Joyent, Inc. 26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved. 27 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 28 */ 29 30 /* 31 * Copyright (c) 2000 to 2010, LSI Corporation. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms of all code within 35 * this file that is exclusively owned by LSI, with or without 36 * modification, is permitted provided that, in addition to the CDDL 1.0 37 * License requirements, the following conditions are met: 38 * 39 * Neither the name of the author nor the names of its contributors may be 40 * used to endorse or promote products derived from this software without 41 * specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 54 * DAMAGE. 55 */ 56 57 /* 58 * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface. 59 * 60 */ 61 62 #if defined(lint) || defined(DEBUG) 63 #define MPTSAS_DEBUG 64 #endif 65 66 /* 67 * standard header files. 68 */ 69 #include <sys/note.h> 70 #include <sys/scsi/scsi.h> 71 #include <sys/pci.h> 72 #include <sys/file.h> 73 #include <sys/policy.h> 74 #include <sys/model.h> 75 #include <sys/sysevent.h> 76 #include <sys/sysevent/eventdefs.h> 77 #include <sys/sysevent/dr.h> 78 #include <sys/sata/sata_defs.h> 79 #include <sys/sata/sata_hba.h> 80 #include <sys/scsi/generic/sas.h> 81 #include <sys/scsi/impl/scsi_sas.h> 82 83 #pragma pack(1) 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 92 #pragma pack() 93 94 /* 95 * private header files. 96 * 97 */ 98 #include <sys/scsi/impl/scsi_reset_notify.h> 99 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 100 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 101 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h> 102 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 103 #include <sys/raidioctl.h> 104 105 #include <sys/fs/dv_node.h> /* devfs_clean */ 106 107 /* 108 * FMA header files 109 */ 110 #include <sys/ddifm.h> 111 #include <sys/fm/protocol.h> 112 #include <sys/fm/util.h> 113 #include <sys/fm/io/ddi.h> 114 115 /* 116 * autoconfiguration data and routines. 117 */ 118 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 119 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 120 static int mptsas_power(dev_info_t *dip, int component, int level); 121 122 /* 123 * cb_ops function 124 */ 125 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 126 cred_t *credp, int *rval); 127 #ifdef __sparc 128 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 129 #else /* __sparc */ 130 static int mptsas_quiesce(dev_info_t *devi); 131 #endif /* __sparc */ 132 133 /* 134 * Resource initilaization for hardware 135 */ 136 static void mptsas_setup_cmd_reg(mptsas_t *mpt); 137 static void mptsas_disable_bus_master(mptsas_t *mpt); 138 static void mptsas_hba_fini(mptsas_t *mpt); 139 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 140 static int mptsas_hba_setup(mptsas_t *mpt); 141 static void mptsas_hba_teardown(mptsas_t *mpt); 142 static int mptsas_config_space_init(mptsas_t *mpt); 143 static void mptsas_config_space_fini(mptsas_t *mpt); 144 static void mptsas_iport_register(mptsas_t *mpt); 145 static int mptsas_smp_setup(mptsas_t *mpt); 146 static void mptsas_smp_teardown(mptsas_t *mpt); 147 static int mptsas_enc_setup(mptsas_t *mpt); 148 static void mptsas_enc_teardown(mptsas_t *mpt); 149 static int mptsas_cache_create(mptsas_t *mpt); 150 static void mptsas_cache_destroy(mptsas_t *mpt); 151 static int mptsas_alloc_request_frames(mptsas_t *mpt); 152 static int mptsas_alloc_sense_bufs(mptsas_t *mpt); 153 static int mptsas_alloc_reply_frames(mptsas_t *mpt); 154 static int mptsas_alloc_free_queue(mptsas_t *mpt); 155 static int mptsas_alloc_post_queue(mptsas_t *mpt); 156 static void mptsas_alloc_reply_args(mptsas_t *mpt); 157 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 158 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 159 static int mptsas_init_chip(mptsas_t *mpt, int first_time); 160 static void mptsas_update_hashtab(mptsas_t *mpt); 161 162 /* 163 * SCSA function prototypes 164 */ 165 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 166 static int mptsas_scsi_reset(struct scsi_address *ap, int level); 167 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 168 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 169 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 170 int tgtonly); 171 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 172 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 173 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 174 int tgtlen, int flags, int (*callback)(), caddr_t arg); 175 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 176 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 177 struct scsi_pkt *pkt); 178 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 179 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 180 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 181 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 182 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 183 void (*callback)(caddr_t), caddr_t arg); 184 static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 185 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 186 static int mptsas_scsi_quiesce(dev_info_t *dip); 187 static int mptsas_scsi_unquiesce(dev_info_t *dip); 188 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 189 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 190 191 /* 192 * SMP functions 193 */ 194 static int mptsas_smp_start(struct smp_pkt *smp_pkt); 195 196 /* 197 * internal function prototypes. 198 */ 199 static void mptsas_list_add(mptsas_t *mpt); 200 static void mptsas_list_del(mptsas_t *mpt); 201 202 static int mptsas_quiesce_bus(mptsas_t *mpt); 203 static int mptsas_unquiesce_bus(mptsas_t *mpt); 204 205 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 206 static void mptsas_free_handshake_msg(mptsas_t *mpt); 207 208 static void mptsas_ncmds_checkdrain(void *arg); 209 210 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 211 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 212 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 213 static void mptsas_accept_tx_waitq(mptsas_t *mpt); 214 215 static int mptsas_do_detach(dev_info_t *dev); 216 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 217 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 218 struct scsi_pkt *pkt); 219 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 220 221 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 222 static void mptsas_handle_event(void *args); 223 static int mptsas_handle_event_sync(void *args); 224 static void mptsas_handle_dr(void *args); 225 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 226 dev_info_t *pdip); 227 228 static void mptsas_restart_cmd(void *); 229 230 static void mptsas_flush_hba(mptsas_t *mpt); 231 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 232 uint8_t tasktype); 233 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 234 uchar_t reason, uint_t stat); 235 236 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 237 static void mptsas_process_intr(mptsas_t *mpt, 238 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 239 static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 240 pMpi2ReplyDescriptorsUnion_t reply_desc); 241 static void mptsas_handle_address_reply(mptsas_t *mpt, 242 pMpi2ReplyDescriptorsUnion_t reply_desc); 243 static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 244 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 245 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 246 247 static void mptsas_watch(void *arg); 248 static void mptsas_watchsubr(mptsas_t *mpt); 249 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt); 250 251 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 252 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 253 uint8_t *data, uint32_t request_size, uint32_t reply_size, 254 uint32_t data_size, uint32_t direction, uint8_t *dataout, 255 uint32_t dataout_size, short timeout, int mode); 256 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 257 258 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 259 uint32_t unique_id); 260 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 261 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 262 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 263 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 264 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 265 uint32_t diag_type); 266 static int mptsas_diag_register(mptsas_t *mpt, 267 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 268 static int mptsas_diag_unregister(mptsas_t *mpt, 269 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 270 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 271 uint32_t *return_code); 272 static int mptsas_diag_read_buffer(mptsas_t *mpt, 273 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 274 uint32_t *return_code, int ioctl_mode); 275 static int mptsas_diag_release(mptsas_t *mpt, 276 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 277 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 278 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 279 int ioctl_mode); 280 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 281 int mode); 282 283 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 284 int cmdlen, int tgtlen, int statuslen, int kf); 285 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 286 287 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 288 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 289 290 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 291 int kmflags); 292 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 293 294 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 295 mptsas_cmd_t *cmd); 296 static void mptsas_check_task_mgt(mptsas_t *mpt, 297 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 298 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 299 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 300 int *resid); 301 302 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 303 static void mptsas_free_active_slots(mptsas_t *mpt); 304 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 305 306 static void mptsas_restart_hba(mptsas_t *mpt); 307 static void mptsas_restart_waitq(mptsas_t *mpt); 308 309 static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 310 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 311 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 312 313 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 314 static void mptsas_doneq_empty(mptsas_t *mpt); 315 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 316 317 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 318 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 319 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt); 320 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 321 322 323 static void mptsas_start_watch_reset_delay(); 324 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 325 static void mptsas_watch_reset_delay(void *arg); 326 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 327 328 /* 329 * helper functions 330 */ 331 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 332 333 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 334 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 335 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 336 int lun); 337 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 338 int lun); 339 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 340 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 341 342 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 343 int *lun); 344 static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 345 346 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, 347 mptsas_phymask_t phymask, uint8_t phy); 348 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, 349 mptsas_phymask_t phymask, uint64_t wwid); 350 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, 351 mptsas_phymask_t phymask, uint64_t wwid); 352 353 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 354 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 355 356 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 357 uint16_t *handle, mptsas_target_t **pptgt); 358 static void mptsas_update_phymask(mptsas_t *mpt); 359 360 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 361 uint32_t *status, uint8_t cmd); 362 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev, 363 mptsas_phymask_t *phymask); 364 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, 365 mptsas_phymask_t phymask); 366 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt); 367 368 369 /* 370 * Enumeration / DR functions 371 */ 372 static void mptsas_config_all(dev_info_t *pdip); 373 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 374 dev_info_t **lundip); 375 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 376 dev_info_t **lundip); 377 378 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 379 static int mptsas_offline_target(dev_info_t *pdip, char *name); 380 381 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 382 dev_info_t **dip); 383 384 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 385 static int mptsas_probe_lun(dev_info_t *pdip, int lun, 386 dev_info_t **dip, mptsas_target_t *ptgt); 387 388 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 389 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 390 391 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 392 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 393 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 394 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 395 int lun); 396 397 static void mptsas_offline_missed_luns(dev_info_t *pdip, 398 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 399 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 400 mdi_pathinfo_t *rpip, uint_t flags); 401 402 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 403 dev_info_t **smp_dip); 404 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 405 uint_t flags); 406 407 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 408 int mode, int *rval); 409 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 410 int mode, int *rval); 411 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 412 int mode, int *rval); 413 static void mptsas_record_event(void *args); 414 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 415 int mode); 416 417 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t, 418 uint32_t, mptsas_phymask_t, uint8_t); 419 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *); 420 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 421 dev_info_t **smp_dip); 422 423 /* 424 * Power management functions 425 */ 426 static int mptsas_get_pci_cap(mptsas_t *mpt); 427 static int mptsas_init_pm(mptsas_t *mpt); 428 429 /* 430 * MPT MSI tunable: 431 * 432 * By default MSI is enabled on all supported platforms. 433 */ 434 boolean_t mptsas_enable_msi = B_TRUE; 435 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE; 436 437 /* 438 * Global switch for use of MPI2.5 FAST PATH. 439 * We don't really know what FAST PATH actually does, so if it is suspected 440 * to cause problems it can be turned off by setting this variable to B_FALSE. 441 */ 442 boolean_t mptsas_use_fastpath = B_TRUE; 443 444 static int mptsas_register_intrs(mptsas_t *); 445 static void mptsas_unregister_intrs(mptsas_t *); 446 static int mptsas_add_intrs(mptsas_t *, int); 447 static void mptsas_rem_intrs(mptsas_t *); 448 449 /* 450 * FMA Prototypes 451 */ 452 static void mptsas_fm_init(mptsas_t *mpt); 453 static void mptsas_fm_fini(mptsas_t *mpt); 454 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 455 456 extern pri_t minclsyspri, maxclsyspri; 457 458 /* 459 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 460 * under this device that the paths to a physical device are created when 461 * MPxIO is used. 462 */ 463 extern dev_info_t *scsi_vhci_dip; 464 465 /* 466 * Tunable timeout value for Inquiry VPD page 0x83 467 * By default the value is 30 seconds. 468 */ 469 int mptsas_inq83_retry_timeout = 30; 470 471 /* 472 * This is used to allocate memory for message frame storage, not for 473 * data I/O DMA. All message frames must be stored in the first 4G of 474 * physical memory. 475 */ 476 ddi_dma_attr_t mptsas_dma_attrs = { 477 DMA_ATTR_V0, /* attribute layout version */ 478 0x0ull, /* address low - should be 0 (longlong) */ 479 0xffffffffull, /* address high - 32-bit max range */ 480 0x00ffffffull, /* count max - max DMA object size */ 481 4, /* allocation alignment requirements */ 482 0x78, /* burstsizes - binary encoded values */ 483 1, /* minxfer - gran. of DMA engine */ 484 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 485 0xffffffffull, /* max segment size (DMA boundary) */ 486 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 487 512, /* granularity - device transfer size */ 488 0 /* flags, set to 0 */ 489 }; 490 491 /* 492 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 493 * physical addresses are supported.) 494 */ 495 ddi_dma_attr_t mptsas_dma_attrs64 = { 496 DMA_ATTR_V0, /* attribute layout version */ 497 0x0ull, /* address low - should be 0 (longlong) */ 498 0xffffffffffffffffull, /* address high - 64-bit max */ 499 0x00ffffffull, /* count max - max DMA object size */ 500 4, /* allocation alignment requirements */ 501 0x78, /* burstsizes - binary encoded values */ 502 1, /* minxfer - gran. of DMA engine */ 503 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 504 0xffffffffull, /* max segment size (DMA boundary) */ 505 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 506 512, /* granularity - device transfer size */ 507 0 /* flags, set to 0 */ 508 }; 509 510 ddi_device_acc_attr_t mptsas_dev_attr = { 511 DDI_DEVICE_ATTR_V1, 512 DDI_STRUCTURE_LE_ACC, 513 DDI_STRICTORDER_ACC, 514 DDI_DEFAULT_ACC 515 }; 516 517 static struct cb_ops mptsas_cb_ops = { 518 scsi_hba_open, /* open */ 519 scsi_hba_close, /* close */ 520 nodev, /* strategy */ 521 nodev, /* print */ 522 nodev, /* dump */ 523 nodev, /* read */ 524 nodev, /* write */ 525 mptsas_ioctl, /* ioctl */ 526 nodev, /* devmap */ 527 nodev, /* mmap */ 528 nodev, /* segmap */ 529 nochpoll, /* chpoll */ 530 ddi_prop_op, /* cb_prop_op */ 531 NULL, /* streamtab */ 532 D_MP, /* cb_flag */ 533 CB_REV, /* rev */ 534 nodev, /* aread */ 535 nodev /* awrite */ 536 }; 537 538 static struct dev_ops mptsas_ops = { 539 DEVO_REV, /* devo_rev, */ 540 0, /* refcnt */ 541 ddi_no_info, /* info */ 542 nulldev, /* identify */ 543 nulldev, /* probe */ 544 mptsas_attach, /* attach */ 545 mptsas_detach, /* detach */ 546 #ifdef __sparc 547 mptsas_reset, 548 #else 549 nodev, /* reset */ 550 #endif /* __sparc */ 551 &mptsas_cb_ops, /* driver operations */ 552 NULL, /* bus operations */ 553 mptsas_power, /* power management */ 554 #ifdef __sparc 555 ddi_quiesce_not_needed 556 #else 557 mptsas_quiesce /* quiesce */ 558 #endif /* __sparc */ 559 }; 560 561 562 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24" 563 564 static struct modldrv modldrv = { 565 &mod_driverops, /* Type of module. This one is a driver */ 566 MPTSAS_MOD_STRING, /* Name of the module. */ 567 &mptsas_ops, /* driver ops */ 568 }; 569 570 static struct modlinkage modlinkage = { 571 MODREV_1, &modldrv, NULL 572 }; 573 #define TARGET_PROP "target" 574 #define LUN_PROP "lun" 575 #define LUN64_PROP "lun64" 576 #define SAS_PROP "sas-mpt" 577 #define MDI_GUID "wwn" 578 #define NDI_GUID "guid" 579 #define MPTSAS_DEV_GONE "mptsas_dev_gone" 580 581 /* 582 * Local static data 583 */ 584 #if defined(MPTSAS_DEBUG) 585 /* 586 * Flags to indicate which debug messages are to be printed and which go to the 587 * debug log ring buffer. Default is to not print anything, and to log 588 * everything except the watchsubr() output which normally happens every second. 589 */ 590 uint32_t mptsas_debugprt_flags = 0x0; 591 uint32_t mptsas_debuglog_flags = ~(1U << 30); 592 #endif /* defined(MPTSAS_DEBUG) */ 593 uint32_t mptsas_debug_resets = 0; 594 595 static kmutex_t mptsas_global_mutex; 596 static void *mptsas_state; /* soft state ptr */ 597 static krwlock_t mptsas_global_rwlock; 598 599 static kmutex_t mptsas_log_mutex; 600 static char mptsas_log_buf[256]; 601 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 602 603 static mptsas_t *mptsas_head, *mptsas_tail; 604 static clock_t mptsas_scsi_watchdog_tick; 605 static clock_t mptsas_tick; 606 static timeout_id_t mptsas_reset_watch; 607 static timeout_id_t mptsas_timeout_id; 608 static int mptsas_timeouts_enabled = 0; 609 610 /* 611 * Default length for extended auto request sense buffers. 612 * All sense buffers need to be under the same alloc because there 613 * is only one common top 32bits (of 64bits) address register. 614 * Most requests only require 32 bytes, but some request >256. 615 * We use rmalloc()/rmfree() on this additional memory to manage the 616 * "extended" requests. 617 */ 618 int mptsas_extreq_sense_bufsize = 256*64; 619 620 /* 621 * We believe that all software resrictions of having to run with DMA 622 * attributes to limit allocation to the first 4G are removed. 623 * However, this flag remains to enable quick switchback should suspicious 624 * problems emerge. 625 * Note that scsi_alloc_consistent_buf() does still adhere to allocating 626 * 32 bit addressable memory, but we can cope if that is changed now. 627 */ 628 int mptsas_use_64bit_msgaddr = 1; 629 630 /* 631 * warlock directives 632 */ 633 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 634 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 635 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 636 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 637 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 638 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 639 640 /* 641 * SM - HBA statics 642 */ 643 char *mptsas_driver_rev = MPTSAS_MOD_STRING; 644 645 #ifdef MPTSAS_DEBUG 646 void debug_enter(char *); 647 #endif 648 649 /* 650 * Notes: 651 * - scsi_hba_init(9F) initializes SCSI HBA modules 652 * - must call scsi_hba_fini(9F) if modload() fails 653 */ 654 int 655 _init(void) 656 { 657 int status; 658 /* CONSTCOND */ 659 ASSERT(NO_COMPETING_THREADS); 660 661 NDBG0(("_init")); 662 663 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 664 MPTSAS_INITIAL_SOFT_SPACE); 665 if (status != 0) { 666 return (status); 667 } 668 669 if ((status = scsi_hba_init(&modlinkage)) != 0) { 670 ddi_soft_state_fini(&mptsas_state); 671 return (status); 672 } 673 674 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 675 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 676 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 677 678 if ((status = mod_install(&modlinkage)) != 0) { 679 mutex_destroy(&mptsas_log_mutex); 680 rw_destroy(&mptsas_global_rwlock); 681 mutex_destroy(&mptsas_global_mutex); 682 ddi_soft_state_fini(&mptsas_state); 683 scsi_hba_fini(&modlinkage); 684 } 685 686 return (status); 687 } 688 689 /* 690 * Notes: 691 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 692 */ 693 int 694 _fini(void) 695 { 696 int status; 697 /* CONSTCOND */ 698 ASSERT(NO_COMPETING_THREADS); 699 700 NDBG0(("_fini")); 701 702 if ((status = mod_remove(&modlinkage)) == 0) { 703 ddi_soft_state_fini(&mptsas_state); 704 scsi_hba_fini(&modlinkage); 705 mutex_destroy(&mptsas_global_mutex); 706 rw_destroy(&mptsas_global_rwlock); 707 mutex_destroy(&mptsas_log_mutex); 708 } 709 return (status); 710 } 711 712 /* 713 * The loadable-module _info(9E) entry point 714 */ 715 int 716 _info(struct modinfo *modinfop) 717 { 718 /* CONSTCOND */ 719 ASSERT(NO_COMPETING_THREADS); 720 NDBG0(("mptsas _info")); 721 722 return (mod_info(&modlinkage, modinfop)); 723 } 724 725 static int 726 mptsas_target_eval_devhdl(const void *op, void *arg) 727 { 728 uint16_t dh = *(uint16_t *)arg; 729 const mptsas_target_t *tp = op; 730 731 return ((int)tp->m_devhdl - (int)dh); 732 } 733 734 static int 735 mptsas_target_eval_slot(const void *op, void *arg) 736 { 737 mptsas_led_control_t *lcp = arg; 738 const mptsas_target_t *tp = op; 739 740 if (tp->m_enclosure != lcp->Enclosure) 741 return ((int)tp->m_enclosure - (int)lcp->Enclosure); 742 743 return ((int)tp->m_slot_num - (int)lcp->Slot); 744 } 745 746 static int 747 mptsas_target_eval_nowwn(const void *op, void *arg) 748 { 749 uint8_t phy = *(uint8_t *)arg; 750 const mptsas_target_t *tp = op; 751 752 if (tp->m_addr.mta_wwn != 0) 753 return (-1); 754 755 return ((int)tp->m_phynum - (int)phy); 756 } 757 758 static int 759 mptsas_smp_eval_devhdl(const void *op, void *arg) 760 { 761 uint16_t dh = *(uint16_t *)arg; 762 const mptsas_smp_t *sp = op; 763 764 return ((int)sp->m_devhdl - (int)dh); 765 } 766 767 static uint64_t 768 mptsas_target_addr_hash(const void *tp) 769 { 770 const mptsas_target_addr_t *tap = tp; 771 772 return ((tap->mta_wwn & 0xffffffffffffULL) | 773 ((uint64_t)tap->mta_phymask << 48)); 774 } 775 776 static int 777 mptsas_target_addr_cmp(const void *a, const void *b) 778 { 779 const mptsas_target_addr_t *aap = a; 780 const mptsas_target_addr_t *bap = b; 781 782 if (aap->mta_wwn < bap->mta_wwn) 783 return (-1); 784 if (aap->mta_wwn > bap->mta_wwn) 785 return (1); 786 return ((int)bap->mta_phymask - (int)aap->mta_phymask); 787 } 788 789 static uint64_t 790 mptsas_tmp_target_hash(const void *tp) 791 { 792 return ((uint64_t)(uintptr_t)tp); 793 } 794 795 static int 796 mptsas_tmp_target_cmp(const void *a, const void *b) 797 { 798 if (a > b) 799 return (1); 800 if (b < a) 801 return (-1); 802 803 return (0); 804 } 805 806 static void 807 mptsas_target_free(void *op) 808 { 809 kmem_free(op, sizeof (mptsas_target_t)); 810 } 811 812 static void 813 mptsas_smp_free(void *op) 814 { 815 kmem_free(op, sizeof (mptsas_smp_t)); 816 } 817 818 static void 819 mptsas_destroy_hashes(mptsas_t *mpt) 820 { 821 mptsas_target_t *tp; 822 mptsas_smp_t *sp; 823 824 for (tp = refhash_first(mpt->m_targets); tp != NULL; 825 tp = refhash_next(mpt->m_targets, tp)) { 826 refhash_remove(mpt->m_targets, tp); 827 } 828 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 829 sp = refhash_next(mpt->m_smp_targets, sp)) { 830 refhash_remove(mpt->m_smp_targets, sp); 831 } 832 refhash_destroy(mpt->m_tmp_targets); 833 refhash_destroy(mpt->m_targets); 834 refhash_destroy(mpt->m_smp_targets); 835 mpt->m_targets = NULL; 836 mpt->m_smp_targets = NULL; 837 } 838 839 static int 840 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 841 { 842 dev_info_t *pdip; 843 mptsas_t *mpt; 844 scsi_hba_tran_t *hba_tran; 845 char *iport = NULL; 846 char phymask[MPTSAS_MAX_PHYS]; 847 mptsas_phymask_t phy_mask = 0; 848 int dynamic_port = 0; 849 uint32_t page_address; 850 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 851 int rval = DDI_FAILURE; 852 int i = 0; 853 uint8_t numphys = 0; 854 uint8_t phy_id; 855 uint8_t phy_port = 0; 856 uint16_t attached_devhdl = 0; 857 uint32_t dev_info; 858 uint64_t attached_sas_wwn; 859 uint16_t dev_hdl; 860 uint16_t pdev_hdl; 861 uint16_t bay_num, enclosure, io_flags; 862 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 863 864 /* CONSTCOND */ 865 ASSERT(NO_COMPETING_THREADS); 866 867 switch (cmd) { 868 case DDI_ATTACH: 869 break; 870 871 case DDI_RESUME: 872 /* 873 * If this a scsi-iport node, nothing to do here. 874 */ 875 return (DDI_SUCCESS); 876 877 default: 878 return (DDI_FAILURE); 879 } 880 881 pdip = ddi_get_parent(dip); 882 883 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 884 NULL) { 885 cmn_err(CE_WARN, "Failed attach iport because fail to " 886 "get tran vector for the HBA node"); 887 return (DDI_FAILURE); 888 } 889 890 mpt = TRAN2MPT(hba_tran); 891 ASSERT(mpt != NULL); 892 if (mpt == NULL) 893 return (DDI_FAILURE); 894 895 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 896 NULL) { 897 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 898 "get tran vector for the iport node"); 899 return (DDI_FAILURE); 900 } 901 902 /* 903 * Overwrite parent's tran_hba_private to iport's tran vector 904 */ 905 hba_tran->tran_hba_private = mpt; 906 907 ddi_report_dev(dip); 908 909 /* 910 * Get SAS address for initiator port according dev_handle 911 */ 912 iport = ddi_get_name_addr(dip); 913 if (iport && strncmp(iport, "v0", 2) == 0) { 914 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 915 MPTSAS_VIRTUAL_PORT, 1) != 916 DDI_PROP_SUCCESS) { 917 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 918 MPTSAS_VIRTUAL_PORT); 919 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 920 "prop update failed"); 921 return (DDI_FAILURE); 922 } 923 return (DDI_SUCCESS); 924 } 925 926 mutex_enter(&mpt->m_mutex); 927 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 928 bzero(phymask, sizeof (phymask)); 929 (void) sprintf(phymask, 930 "%x", mpt->m_phy_info[i].phy_mask); 931 if (strcmp(phymask, iport) == 0) { 932 break; 933 } 934 } 935 936 if (i == MPTSAS_MAX_PHYS) { 937 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 938 "seems not exist", iport); 939 mutex_exit(&mpt->m_mutex); 940 return (DDI_FAILURE); 941 } 942 943 phy_mask = mpt->m_phy_info[i].phy_mask; 944 945 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 946 dynamic_port = 1; 947 else 948 dynamic_port = 0; 949 950 /* 951 * Update PHY info for smhba 952 */ 953 if (mptsas_smhba_phy_init(mpt)) { 954 mutex_exit(&mpt->m_mutex); 955 mptsas_log(mpt, CE_WARN, "mptsas phy update " 956 "failed"); 957 return (DDI_FAILURE); 958 } 959 960 mutex_exit(&mpt->m_mutex); 961 962 numphys = 0; 963 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 964 if ((phy_mask >> i) & 0x01) { 965 numphys++; 966 } 967 } 968 969 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 970 (void) sprintf(initiator_wwnstr, "w%016"PRIx64, 971 mpt->un.m_base_wwid); 972 973 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 974 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) != 975 DDI_PROP_SUCCESS) { 976 (void) ddi_prop_remove(DDI_DEV_T_NONE, 977 dip, SCSI_ADDR_PROP_INITIATOR_PORT); 978 mptsas_log(mpt, CE_WARN, "mptsas Initiator port " 979 "prop update failed"); 980 return (DDI_FAILURE); 981 } 982 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 983 MPTSAS_NUM_PHYS, numphys) != 984 DDI_PROP_SUCCESS) { 985 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS); 986 return (DDI_FAILURE); 987 } 988 989 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 990 "phymask", phy_mask) != 991 DDI_PROP_SUCCESS) { 992 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 993 mptsas_log(mpt, CE_WARN, "mptsas phy mask " 994 "prop update failed"); 995 return (DDI_FAILURE); 996 } 997 998 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 999 "dynamic-port", dynamic_port) != 1000 DDI_PROP_SUCCESS) { 1001 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 1002 mptsas_log(mpt, CE_WARN, "mptsas dynamic port " 1003 "prop update failed"); 1004 return (DDI_FAILURE); 1005 } 1006 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 1007 MPTSAS_VIRTUAL_PORT, 0) != 1008 DDI_PROP_SUCCESS) { 1009 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 1010 MPTSAS_VIRTUAL_PORT); 1011 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 1012 "prop update failed"); 1013 return (DDI_FAILURE); 1014 } 1015 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask, 1016 &attached_devhdl); 1017 1018 mutex_enter(&mpt->m_mutex); 1019 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 1020 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl; 1021 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 1022 &attached_sas_wwn, &dev_info, &phy_port, &phy_id, 1023 &pdev_hdl, &bay_num, &enclosure, &io_flags); 1024 if (rval != DDI_SUCCESS) { 1025 mptsas_log(mpt, CE_WARN, 1026 "Failed to get device page0 for handle:%d", 1027 attached_devhdl); 1028 mutex_exit(&mpt->m_mutex); 1029 return (DDI_FAILURE); 1030 } 1031 1032 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1033 bzero(phymask, sizeof (phymask)); 1034 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 1035 if (strcmp(phymask, iport) == 0) { 1036 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0], 1037 "%x", 1038 mpt->m_phy_info[i].phy_mask); 1039 } 1040 } 1041 mutex_exit(&mpt->m_mutex); 1042 1043 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 1044 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 1045 attached_sas_wwn); 1046 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 1047 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 1048 DDI_PROP_SUCCESS) { 1049 (void) ddi_prop_remove(DDI_DEV_T_NONE, 1050 dip, SCSI_ADDR_PROP_ATTACHED_PORT); 1051 return (DDI_FAILURE); 1052 } 1053 1054 /* Create kstats for each phy on this iport */ 1055 1056 mptsas_create_phy_stats(mpt, iport, dip); 1057 1058 /* 1059 * register sas hba iport with mdi (MPxIO/vhci) 1060 */ 1061 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 1062 dip, 0) == MDI_SUCCESS) { 1063 mpt->m_mpxio_enable = TRUE; 1064 } 1065 return (DDI_SUCCESS); 1066 } 1067 1068 /* 1069 * Notes: 1070 * Set up all device state and allocate data structures, 1071 * mutexes, condition variables, etc. for device operation. 1072 * Add interrupts needed. 1073 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 1074 */ 1075 static int 1076 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1077 { 1078 mptsas_t *mpt = NULL; 1079 int instance, i, j; 1080 int doneq_thread_num; 1081 char intr_added = 0; 1082 char map_setup = 0; 1083 char config_setup = 0; 1084 char hba_attach_setup = 0; 1085 char smp_attach_setup = 0; 1086 char enc_attach_setup = 0; 1087 char mutex_init_done = 0; 1088 char event_taskq_create = 0; 1089 char dr_taskq_create = 0; 1090 char doneq_thread_create = 0; 1091 char added_watchdog = 0; 1092 scsi_hba_tran_t *hba_tran; 1093 uint_t mem_bar = MEM_SPACE; 1094 int rval = DDI_FAILURE; 1095 1096 /* CONSTCOND */ 1097 ASSERT(NO_COMPETING_THREADS); 1098 1099 if (scsi_hba_iport_unit_address(dip)) { 1100 return (mptsas_iport_attach(dip, cmd)); 1101 } 1102 1103 switch (cmd) { 1104 case DDI_ATTACH: 1105 break; 1106 1107 case DDI_RESUME: 1108 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 1109 return (DDI_FAILURE); 1110 1111 mpt = TRAN2MPT(hba_tran); 1112 1113 if (!mpt) { 1114 return (DDI_FAILURE); 1115 } 1116 1117 /* 1118 * Reset hardware and softc to "no outstanding commands" 1119 * Note that a check condition can result on first command 1120 * to a target. 1121 */ 1122 mutex_enter(&mpt->m_mutex); 1123 1124 /* 1125 * raise power. 1126 */ 1127 if (mpt->m_options & MPTSAS_OPT_PM) { 1128 mutex_exit(&mpt->m_mutex); 1129 (void) pm_busy_component(dip, 0); 1130 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0); 1131 if (rval == DDI_SUCCESS) { 1132 mutex_enter(&mpt->m_mutex); 1133 } else { 1134 /* 1135 * The pm_raise_power() call above failed, 1136 * and that can only occur if we were unable 1137 * to reset the hardware. This is probably 1138 * due to unhealty hardware, and because 1139 * important filesystems(such as the root 1140 * filesystem) could be on the attached disks, 1141 * it would not be a good idea to continue, 1142 * as we won't be entirely certain we are 1143 * writing correct data. So we panic() here 1144 * to not only prevent possible data corruption, 1145 * but to give developers or end users a hope 1146 * of identifying and correcting any problems. 1147 */ 1148 fm_panic("mptsas could not reset hardware " 1149 "during resume"); 1150 } 1151 } 1152 1153 mpt->m_suspended = 0; 1154 1155 /* 1156 * Reinitialize ioc 1157 */ 1158 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1159 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 1160 mutex_exit(&mpt->m_mutex); 1161 if (mpt->m_options & MPTSAS_OPT_PM) { 1162 (void) pm_idle_component(dip, 0); 1163 } 1164 fm_panic("mptsas init chip fail during resume"); 1165 } 1166 /* 1167 * mptsas_update_driver_data needs interrupts so enable them 1168 * first. 1169 */ 1170 MPTSAS_ENABLE_INTR(mpt); 1171 mptsas_update_driver_data(mpt); 1172 1173 /* start requests, if possible */ 1174 mptsas_restart_hba(mpt); 1175 1176 mutex_exit(&mpt->m_mutex); 1177 1178 /* 1179 * Restart watch thread 1180 */ 1181 mutex_enter(&mptsas_global_mutex); 1182 if (mptsas_timeout_id == 0) { 1183 mptsas_timeout_id = timeout(mptsas_watch, NULL, 1184 mptsas_tick); 1185 mptsas_timeouts_enabled = 1; 1186 } 1187 mutex_exit(&mptsas_global_mutex); 1188 1189 /* report idle status to pm framework */ 1190 if (mpt->m_options & MPTSAS_OPT_PM) { 1191 (void) pm_idle_component(dip, 0); 1192 } 1193 1194 return (DDI_SUCCESS); 1195 1196 default: 1197 return (DDI_FAILURE); 1198 1199 } 1200 1201 instance = ddi_get_instance(dip); 1202 1203 /* 1204 * Allocate softc information. 1205 */ 1206 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 1207 mptsas_log(NULL, CE_WARN, 1208 "mptsas%d: cannot allocate soft state", instance); 1209 goto fail; 1210 } 1211 1212 mpt = ddi_get_soft_state(mptsas_state, instance); 1213 1214 if (mpt == NULL) { 1215 mptsas_log(NULL, CE_WARN, 1216 "mptsas%d: cannot get soft state", instance); 1217 goto fail; 1218 } 1219 1220 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 1221 scsi_size_clean(dip); 1222 1223 mpt->m_dip = dip; 1224 mpt->m_instance = instance; 1225 1226 /* Make a per-instance copy of the structures */ 1227 mpt->m_io_dma_attr = mptsas_dma_attrs64; 1228 if (mptsas_use_64bit_msgaddr) { 1229 mpt->m_msg_dma_attr = mptsas_dma_attrs64; 1230 } else { 1231 mpt->m_msg_dma_attr = mptsas_dma_attrs; 1232 } 1233 mpt->m_reg_acc_attr = mptsas_dev_attr; 1234 mpt->m_dev_acc_attr = mptsas_dev_attr; 1235 1236 /* 1237 * Size of individual request sense buffer 1238 */ 1239 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE; 1240 1241 /* 1242 * Initialize FMA 1243 */ 1244 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 1245 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 1246 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 1247 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1248 1249 mptsas_fm_init(mpt); 1250 1251 if (mptsas_alloc_handshake_msg(mpt, 1252 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 1253 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 1254 goto fail; 1255 } 1256 1257 /* 1258 * Setup configuration space 1259 */ 1260 if (mptsas_config_space_init(mpt) == FALSE) { 1261 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1262 goto fail; 1263 } 1264 config_setup++; 1265 1266 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1267 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1268 mptsas_log(mpt, CE_WARN, "map setup failed"); 1269 goto fail; 1270 } 1271 map_setup++; 1272 1273 /* 1274 * A taskq is created for dealing with the event handler 1275 */ 1276 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1277 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1278 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1279 goto fail; 1280 } 1281 event_taskq_create++; 1282 1283 /* 1284 * A taskq is created for dealing with dr events 1285 */ 1286 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1287 "mptsas_dr_taskq", 1288 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1289 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1290 "failed"); 1291 goto fail; 1292 } 1293 dr_taskq_create++; 1294 1295 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1296 0, "mptsas_doneq_thread_threshold_prop", 10); 1297 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1298 0, "mptsas_doneq_length_threshold_prop", 8); 1299 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1300 0, "mptsas_doneq_thread_n_prop", 8); 1301 1302 if (mpt->m_doneq_thread_n) { 1303 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1304 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1305 1306 mutex_enter(&mpt->m_doneq_mutex); 1307 mpt->m_doneq_thread_id = 1308 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1309 * mpt->m_doneq_thread_n, KM_SLEEP); 1310 1311 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1312 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1313 CV_DRIVER, NULL); 1314 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1315 MUTEX_DRIVER, NULL); 1316 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1317 mpt->m_doneq_thread_id[j].flag |= 1318 MPTSAS_DONEQ_THREAD_ACTIVE; 1319 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1320 mpt->m_doneq_thread_id[j].arg.t = j; 1321 mpt->m_doneq_thread_id[j].threadp = 1322 thread_create(NULL, 0, mptsas_doneq_thread, 1323 &mpt->m_doneq_thread_id[j].arg, 1324 0, &p0, TS_RUN, minclsyspri); 1325 mpt->m_doneq_thread_id[j].donetail = 1326 &mpt->m_doneq_thread_id[j].doneq; 1327 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1328 } 1329 mutex_exit(&mpt->m_doneq_mutex); 1330 doneq_thread_create++; 1331 } 1332 1333 /* 1334 * Disable hardware interrupt since we're not ready to 1335 * handle it yet. 1336 */ 1337 MPTSAS_DISABLE_INTR(mpt); 1338 if (mptsas_register_intrs(mpt) == FALSE) 1339 goto fail; 1340 intr_added++; 1341 1342 /* Initialize mutex used in interrupt handler */ 1343 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1344 DDI_INTR_PRI(mpt->m_intr_pri)); 1345 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL); 1346 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER, 1347 DDI_INTR_PRI(mpt->m_intr_pri)); 1348 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1349 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex, 1350 NULL, MUTEX_DRIVER, 1351 DDI_INTR_PRI(mpt->m_intr_pri)); 1352 } 1353 1354 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1355 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1356 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1357 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1358 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1359 cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL); 1360 mutex_init_done++; 1361 1362 mutex_enter(&mpt->m_mutex); 1363 /* 1364 * Initialize power management component 1365 */ 1366 if (mpt->m_options & MPTSAS_OPT_PM) { 1367 if (mptsas_init_pm(mpt)) { 1368 mutex_exit(&mpt->m_mutex); 1369 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1370 "failed"); 1371 goto fail; 1372 } 1373 } 1374 1375 /* 1376 * Initialize chip using Message Unit Reset, if allowed 1377 */ 1378 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1379 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1380 mutex_exit(&mpt->m_mutex); 1381 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1382 goto fail; 1383 } 1384 1385 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT, 1386 mptsas_target_addr_hash, mptsas_target_addr_cmp, 1387 mptsas_target_free, sizeof (mptsas_target_t), 1388 offsetof(mptsas_target_t, m_link), 1389 offsetof(mptsas_target_t, m_addr), KM_SLEEP); 1390 1391 /* 1392 * The refhash for temporary targets uses the address of the target 1393 * struct itself as tag, so the tag offset is 0. See the implementation 1394 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp(). 1395 */ 1396 mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT, 1397 mptsas_tmp_target_hash, mptsas_tmp_target_cmp, 1398 mptsas_target_free, sizeof (mptsas_target_t), 1399 offsetof(mptsas_target_t, m_link), 0, KM_SLEEP); 1400 1401 /* 1402 * Fill in the phy_info structure and get the base WWID 1403 */ 1404 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 1405 mptsas_log(mpt, CE_WARN, 1406 "mptsas_get_manufacture_page5 failed!"); 1407 goto fail; 1408 } 1409 1410 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 1411 mptsas_log(mpt, CE_WARN, 1412 "mptsas_get_sas_io_unit_page_hndshk failed!"); 1413 goto fail; 1414 } 1415 1416 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) { 1417 mptsas_log(mpt, CE_WARN, 1418 "mptsas_get_manufacture_page0 failed!"); 1419 goto fail; 1420 } 1421 1422 mutex_exit(&mpt->m_mutex); 1423 1424 /* 1425 * Register the iport for multiple port HBA 1426 */ 1427 mptsas_iport_register(mpt); 1428 1429 /* 1430 * initialize SCSI HBA transport structure 1431 */ 1432 if (mptsas_hba_setup(mpt) == FALSE) 1433 goto fail; 1434 hba_attach_setup++; 1435 1436 if (mptsas_smp_setup(mpt) == FALSE) 1437 goto fail; 1438 smp_attach_setup++; 1439 1440 if (mptsas_enc_setup(mpt) == FALSE) 1441 goto fail; 1442 enc_attach_setup++; 1443 1444 if (mptsas_cache_create(mpt) == FALSE) 1445 goto fail; 1446 1447 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1448 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1449 if (mpt->m_scsi_reset_delay == 0) { 1450 mptsas_log(mpt, CE_NOTE, 1451 "scsi_reset_delay of 0 is not recommended," 1452 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1453 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1454 } 1455 1456 /* 1457 * Initialize the wait and done FIFO queue 1458 */ 1459 mpt->m_donetail = &mpt->m_doneq; 1460 mpt->m_waitqtail = &mpt->m_waitq; 1461 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 1462 mpt->m_tx_draining = 0; 1463 1464 /* 1465 * ioc cmd queue initialize 1466 */ 1467 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1468 mpt->m_dev_handle = 0xFFFF; 1469 1470 MPTSAS_ENABLE_INTR(mpt); 1471 1472 /* 1473 * enable event notification 1474 */ 1475 mutex_enter(&mpt->m_mutex); 1476 if (mptsas_ioc_enable_event_notification(mpt)) { 1477 mutex_exit(&mpt->m_mutex); 1478 goto fail; 1479 } 1480 mutex_exit(&mpt->m_mutex); 1481 1482 /* 1483 * used for mptsas_watch 1484 */ 1485 mptsas_list_add(mpt); 1486 1487 mutex_enter(&mptsas_global_mutex); 1488 if (mptsas_timeouts_enabled == 0) { 1489 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1490 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1491 1492 mptsas_tick = mptsas_scsi_watchdog_tick * 1493 drv_usectohz((clock_t)1000000); 1494 1495 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1496 mptsas_timeouts_enabled = 1; 1497 } 1498 mutex_exit(&mptsas_global_mutex); 1499 added_watchdog++; 1500 1501 /* 1502 * Initialize PHY info for smhba. 1503 * This requires watchdog to be enabled otherwise if interrupts 1504 * don't work the system will hang. 1505 */ 1506 if (mptsas_smhba_setup(mpt)) { 1507 mptsas_log(mpt, CE_WARN, "mptsas phy initialization " 1508 "failed"); 1509 goto fail; 1510 } 1511 1512 /* Check all dma handles allocated in attach */ 1513 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1514 != DDI_SUCCESS) || 1515 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) 1516 != DDI_SUCCESS) || 1517 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1518 != DDI_SUCCESS) || 1519 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1520 != DDI_SUCCESS) || 1521 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1522 != DDI_SUCCESS) || 1523 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1524 != DDI_SUCCESS)) { 1525 goto fail; 1526 } 1527 1528 /* Check all acc handles allocated in attach */ 1529 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1530 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1531 != DDI_SUCCESS) || 1532 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) 1533 != DDI_SUCCESS) || 1534 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1535 != DDI_SUCCESS) || 1536 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1537 != DDI_SUCCESS) || 1538 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1539 != DDI_SUCCESS) || 1540 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1541 != DDI_SUCCESS) || 1542 (mptsas_check_acc_handle(mpt->m_config_handle) 1543 != DDI_SUCCESS)) { 1544 goto fail; 1545 } 1546 1547 /* 1548 * After this point, we are not going to fail the attach. 1549 */ 1550 1551 /* Print message of HBA present */ 1552 ddi_report_dev(dip); 1553 1554 /* report idle status to pm framework */ 1555 if (mpt->m_options & MPTSAS_OPT_PM) { 1556 (void) pm_idle_component(dip, 0); 1557 } 1558 1559 return (DDI_SUCCESS); 1560 1561 fail: 1562 mptsas_log(mpt, CE_WARN, "attach failed"); 1563 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1564 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1565 if (mpt) { 1566 /* deallocate in reverse order */ 1567 if (added_watchdog) { 1568 mptsas_list_del(mpt); 1569 mutex_enter(&mptsas_global_mutex); 1570 1571 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1572 timeout_id_t tid = mptsas_timeout_id; 1573 mptsas_timeouts_enabled = 0; 1574 mptsas_timeout_id = 0; 1575 mutex_exit(&mptsas_global_mutex); 1576 (void) untimeout(tid); 1577 mutex_enter(&mptsas_global_mutex); 1578 } 1579 mutex_exit(&mptsas_global_mutex); 1580 } 1581 1582 mptsas_cache_destroy(mpt); 1583 1584 if (smp_attach_setup) { 1585 mptsas_smp_teardown(mpt); 1586 } 1587 if (enc_attach_setup) { 1588 mptsas_enc_teardown(mpt); 1589 } 1590 if (hba_attach_setup) { 1591 mptsas_hba_teardown(mpt); 1592 } 1593 1594 if (mpt->m_tmp_targets) 1595 refhash_destroy(mpt->m_tmp_targets); 1596 if (mpt->m_targets) 1597 refhash_destroy(mpt->m_targets); 1598 if (mpt->m_smp_targets) 1599 refhash_destroy(mpt->m_smp_targets); 1600 1601 if (mpt->m_active) { 1602 mptsas_free_active_slots(mpt); 1603 } 1604 if (intr_added) { 1605 mptsas_unregister_intrs(mpt); 1606 } 1607 1608 if (doneq_thread_create) { 1609 mutex_enter(&mpt->m_doneq_mutex); 1610 doneq_thread_num = mpt->m_doneq_thread_n; 1611 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1612 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1613 mpt->m_doneq_thread_id[j].flag &= 1614 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1615 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1616 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1617 } 1618 while (mpt->m_doneq_thread_n) { 1619 cv_wait(&mpt->m_doneq_thread_cv, 1620 &mpt->m_doneq_mutex); 1621 } 1622 for (j = 0; j < doneq_thread_num; j++) { 1623 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1624 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1625 } 1626 kmem_free(mpt->m_doneq_thread_id, 1627 sizeof (mptsas_doneq_thread_list_t) 1628 * doneq_thread_num); 1629 mutex_exit(&mpt->m_doneq_mutex); 1630 cv_destroy(&mpt->m_doneq_thread_cv); 1631 mutex_destroy(&mpt->m_doneq_mutex); 1632 } 1633 if (event_taskq_create) { 1634 ddi_taskq_destroy(mpt->m_event_taskq); 1635 } 1636 if (dr_taskq_create) { 1637 ddi_taskq_destroy(mpt->m_dr_taskq); 1638 } 1639 if (mutex_init_done) { 1640 mutex_destroy(&mpt->m_tx_waitq_mutex); 1641 mutex_destroy(&mpt->m_passthru_mutex); 1642 mutex_destroy(&mpt->m_mutex); 1643 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1644 mutex_destroy( 1645 &mpt->m_phy_info[i].smhba_info.phy_mutex); 1646 } 1647 cv_destroy(&mpt->m_cv); 1648 cv_destroy(&mpt->m_passthru_cv); 1649 cv_destroy(&mpt->m_fw_cv); 1650 cv_destroy(&mpt->m_config_cv); 1651 cv_destroy(&mpt->m_fw_diag_cv); 1652 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 1653 } 1654 1655 if (map_setup) { 1656 mptsas_cfg_fini(mpt); 1657 } 1658 if (config_setup) { 1659 mptsas_config_space_fini(mpt); 1660 } 1661 mptsas_free_handshake_msg(mpt); 1662 mptsas_hba_fini(mpt); 1663 1664 mptsas_fm_fini(mpt); 1665 ddi_soft_state_free(mptsas_state, instance); 1666 ddi_prop_remove_all(dip); 1667 } 1668 return (DDI_FAILURE); 1669 } 1670 1671 static int 1672 mptsas_suspend(dev_info_t *devi) 1673 { 1674 mptsas_t *mpt, *g; 1675 scsi_hba_tran_t *tran; 1676 1677 if (scsi_hba_iport_unit_address(devi)) { 1678 return (DDI_SUCCESS); 1679 } 1680 1681 if ((tran = ddi_get_driver_private(devi)) == NULL) 1682 return (DDI_SUCCESS); 1683 1684 mpt = TRAN2MPT(tran); 1685 if (!mpt) { 1686 return (DDI_SUCCESS); 1687 } 1688 1689 mutex_enter(&mpt->m_mutex); 1690 1691 if (mpt->m_suspended++) { 1692 mutex_exit(&mpt->m_mutex); 1693 return (DDI_SUCCESS); 1694 } 1695 1696 /* 1697 * Cancel timeout threads for this mpt 1698 */ 1699 if (mpt->m_quiesce_timeid) { 1700 timeout_id_t tid = mpt->m_quiesce_timeid; 1701 mpt->m_quiesce_timeid = 0; 1702 mutex_exit(&mpt->m_mutex); 1703 (void) untimeout(tid); 1704 mutex_enter(&mpt->m_mutex); 1705 } 1706 1707 if (mpt->m_restart_cmd_timeid) { 1708 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1709 mpt->m_restart_cmd_timeid = 0; 1710 mutex_exit(&mpt->m_mutex); 1711 (void) untimeout(tid); 1712 mutex_enter(&mpt->m_mutex); 1713 } 1714 1715 mutex_exit(&mpt->m_mutex); 1716 1717 (void) pm_idle_component(mpt->m_dip, 0); 1718 1719 /* 1720 * Cancel watch threads if all mpts suspended 1721 */ 1722 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1723 for (g = mptsas_head; g != NULL; g = g->m_next) { 1724 if (!g->m_suspended) 1725 break; 1726 } 1727 rw_exit(&mptsas_global_rwlock); 1728 1729 mutex_enter(&mptsas_global_mutex); 1730 if (g == NULL) { 1731 timeout_id_t tid; 1732 1733 mptsas_timeouts_enabled = 0; 1734 if (mptsas_timeout_id) { 1735 tid = mptsas_timeout_id; 1736 mptsas_timeout_id = 0; 1737 mutex_exit(&mptsas_global_mutex); 1738 (void) untimeout(tid); 1739 mutex_enter(&mptsas_global_mutex); 1740 } 1741 if (mptsas_reset_watch) { 1742 tid = mptsas_reset_watch; 1743 mptsas_reset_watch = 0; 1744 mutex_exit(&mptsas_global_mutex); 1745 (void) untimeout(tid); 1746 mutex_enter(&mptsas_global_mutex); 1747 } 1748 } 1749 mutex_exit(&mptsas_global_mutex); 1750 1751 mutex_enter(&mpt->m_mutex); 1752 1753 /* 1754 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1755 */ 1756 if ((mpt->m_options & MPTSAS_OPT_PM) && 1757 (mpt->m_power_level != PM_LEVEL_D0)) { 1758 mutex_exit(&mpt->m_mutex); 1759 return (DDI_SUCCESS); 1760 } 1761 1762 /* Disable HBA interrupts in hardware */ 1763 MPTSAS_DISABLE_INTR(mpt); 1764 /* 1765 * Send RAID action system shutdown to sync IR 1766 */ 1767 mptsas_raid_action_system_shutdown(mpt); 1768 1769 mutex_exit(&mpt->m_mutex); 1770 1771 /* drain the taskq */ 1772 ddi_taskq_wait(mpt->m_event_taskq); 1773 ddi_taskq_wait(mpt->m_dr_taskq); 1774 1775 return (DDI_SUCCESS); 1776 } 1777 1778 #ifdef __sparc 1779 /*ARGSUSED*/ 1780 static int 1781 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1782 { 1783 mptsas_t *mpt; 1784 scsi_hba_tran_t *tran; 1785 1786 /* 1787 * If this call is for iport, just return. 1788 */ 1789 if (scsi_hba_iport_unit_address(devi)) 1790 return (DDI_SUCCESS); 1791 1792 if ((tran = ddi_get_driver_private(devi)) == NULL) 1793 return (DDI_SUCCESS); 1794 1795 if ((mpt = TRAN2MPT(tran)) == NULL) 1796 return (DDI_SUCCESS); 1797 1798 /* 1799 * Send RAID action system shutdown to sync IR. Disable HBA 1800 * interrupts in hardware first. 1801 */ 1802 MPTSAS_DISABLE_INTR(mpt); 1803 mptsas_raid_action_system_shutdown(mpt); 1804 1805 return (DDI_SUCCESS); 1806 } 1807 #else /* __sparc */ 1808 /* 1809 * quiesce(9E) entry point. 1810 * 1811 * This function is called when the system is single-threaded at high 1812 * PIL with preemption disabled. Therefore, this function must not be 1813 * blocked. 1814 * 1815 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1816 * DDI_FAILURE indicates an error condition and should almost never happen. 1817 */ 1818 static int 1819 mptsas_quiesce(dev_info_t *devi) 1820 { 1821 mptsas_t *mpt; 1822 scsi_hba_tran_t *tran; 1823 1824 /* 1825 * If this call is for iport, just return. 1826 */ 1827 if (scsi_hba_iport_unit_address(devi)) 1828 return (DDI_SUCCESS); 1829 1830 if ((tran = ddi_get_driver_private(devi)) == NULL) 1831 return (DDI_SUCCESS); 1832 1833 if ((mpt = TRAN2MPT(tran)) == NULL) 1834 return (DDI_SUCCESS); 1835 1836 /* Disable HBA interrupts in hardware */ 1837 MPTSAS_DISABLE_INTR(mpt); 1838 /* Send RAID action system shutdonw to sync IR */ 1839 mptsas_raid_action_system_shutdown(mpt); 1840 1841 return (DDI_SUCCESS); 1842 } 1843 #endif /* __sparc */ 1844 1845 /* 1846 * detach(9E). Remove all device allocations and system resources; 1847 * disable device interrupts. 1848 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1849 */ 1850 static int 1851 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1852 { 1853 /* CONSTCOND */ 1854 ASSERT(NO_COMPETING_THREADS); 1855 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1856 1857 switch (cmd) { 1858 case DDI_DETACH: 1859 return (mptsas_do_detach(devi)); 1860 1861 case DDI_SUSPEND: 1862 return (mptsas_suspend(devi)); 1863 1864 default: 1865 return (DDI_FAILURE); 1866 } 1867 /* NOTREACHED */ 1868 } 1869 1870 static int 1871 mptsas_do_detach(dev_info_t *dip) 1872 { 1873 mptsas_t *mpt; 1874 scsi_hba_tran_t *tran; 1875 int circ = 0; 1876 int circ1 = 0; 1877 mdi_pathinfo_t *pip = NULL; 1878 int i; 1879 int doneq_thread_num = 0; 1880 1881 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1882 1883 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1884 return (DDI_FAILURE); 1885 1886 mpt = TRAN2MPT(tran); 1887 if (!mpt) { 1888 return (DDI_FAILURE); 1889 } 1890 /* 1891 * Still have pathinfo child, should not detach mpt driver 1892 */ 1893 if (scsi_hba_iport_unit_address(dip)) { 1894 if (mpt->m_mpxio_enable) { 1895 /* 1896 * MPxIO enabled for the iport 1897 */ 1898 ndi_devi_enter(scsi_vhci_dip, &circ1); 1899 ndi_devi_enter(dip, &circ); 1900 while ((pip = mdi_get_next_client_path(dip, NULL)) != 1901 NULL) { 1902 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1903 continue; 1904 } 1905 ndi_devi_exit(dip, circ); 1906 ndi_devi_exit(scsi_vhci_dip, circ1); 1907 NDBG12(("detach failed because of " 1908 "outstanding path info")); 1909 return (DDI_FAILURE); 1910 } 1911 ndi_devi_exit(dip, circ); 1912 ndi_devi_exit(scsi_vhci_dip, circ1); 1913 (void) mdi_phci_unregister(dip, 0); 1914 } 1915 1916 ddi_prop_remove_all(dip); 1917 1918 return (DDI_SUCCESS); 1919 } 1920 1921 /* Make sure power level is D0 before accessing registers */ 1922 if (mpt->m_options & MPTSAS_OPT_PM) { 1923 (void) pm_busy_component(dip, 0); 1924 if (mpt->m_power_level != PM_LEVEL_D0) { 1925 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1926 DDI_SUCCESS) { 1927 mptsas_log(mpt, CE_WARN, 1928 "mptsas%d: Raise power request failed.", 1929 mpt->m_instance); 1930 (void) pm_idle_component(dip, 0); 1931 return (DDI_FAILURE); 1932 } 1933 } 1934 } 1935 1936 /* 1937 * Send RAID action system shutdown to sync IR. After action, send a 1938 * Message Unit Reset. Since after that DMA resource will be freed, 1939 * set ioc to READY state will avoid HBA initiated DMA operation. 1940 */ 1941 mutex_enter(&mpt->m_mutex); 1942 MPTSAS_DISABLE_INTR(mpt); 1943 mptsas_raid_action_system_shutdown(mpt); 1944 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1945 (void) mptsas_ioc_reset(mpt, FALSE); 1946 mutex_exit(&mpt->m_mutex); 1947 mptsas_rem_intrs(mpt); 1948 ddi_taskq_destroy(mpt->m_event_taskq); 1949 ddi_taskq_destroy(mpt->m_dr_taskq); 1950 1951 if (mpt->m_doneq_thread_n) { 1952 mutex_enter(&mpt->m_doneq_mutex); 1953 doneq_thread_num = mpt->m_doneq_thread_n; 1954 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1955 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1956 mpt->m_doneq_thread_id[i].flag &= 1957 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1958 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1959 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1960 } 1961 while (mpt->m_doneq_thread_n) { 1962 cv_wait(&mpt->m_doneq_thread_cv, 1963 &mpt->m_doneq_mutex); 1964 } 1965 for (i = 0; i < doneq_thread_num; i++) { 1966 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1967 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1968 } 1969 kmem_free(mpt->m_doneq_thread_id, 1970 sizeof (mptsas_doneq_thread_list_t) 1971 * doneq_thread_num); 1972 mutex_exit(&mpt->m_doneq_mutex); 1973 cv_destroy(&mpt->m_doneq_thread_cv); 1974 mutex_destroy(&mpt->m_doneq_mutex); 1975 } 1976 1977 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1978 1979 mptsas_list_del(mpt); 1980 1981 /* 1982 * Cancel timeout threads for this mpt 1983 */ 1984 mutex_enter(&mpt->m_mutex); 1985 if (mpt->m_quiesce_timeid) { 1986 timeout_id_t tid = mpt->m_quiesce_timeid; 1987 mpt->m_quiesce_timeid = 0; 1988 mutex_exit(&mpt->m_mutex); 1989 (void) untimeout(tid); 1990 mutex_enter(&mpt->m_mutex); 1991 } 1992 1993 if (mpt->m_restart_cmd_timeid) { 1994 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1995 mpt->m_restart_cmd_timeid = 0; 1996 mutex_exit(&mpt->m_mutex); 1997 (void) untimeout(tid); 1998 mutex_enter(&mpt->m_mutex); 1999 } 2000 2001 mutex_exit(&mpt->m_mutex); 2002 2003 /* 2004 * last mpt? ... if active, CANCEL watch threads. 2005 */ 2006 mutex_enter(&mptsas_global_mutex); 2007 if (mptsas_head == NULL) { 2008 timeout_id_t tid; 2009 /* 2010 * Clear mptsas_timeouts_enable so that the watch thread 2011 * gets restarted on DDI_ATTACH 2012 */ 2013 mptsas_timeouts_enabled = 0; 2014 if (mptsas_timeout_id) { 2015 tid = mptsas_timeout_id; 2016 mptsas_timeout_id = 0; 2017 mutex_exit(&mptsas_global_mutex); 2018 (void) untimeout(tid); 2019 mutex_enter(&mptsas_global_mutex); 2020 } 2021 if (mptsas_reset_watch) { 2022 tid = mptsas_reset_watch; 2023 mptsas_reset_watch = 0; 2024 mutex_exit(&mptsas_global_mutex); 2025 (void) untimeout(tid); 2026 mutex_enter(&mptsas_global_mutex); 2027 } 2028 } 2029 mutex_exit(&mptsas_global_mutex); 2030 2031 /* 2032 * Delete Phy stats 2033 */ 2034 mptsas_destroy_phy_stats(mpt); 2035 2036 mptsas_destroy_hashes(mpt); 2037 2038 /* 2039 * Delete nt_active. 2040 */ 2041 mutex_enter(&mpt->m_mutex); 2042 mptsas_free_active_slots(mpt); 2043 mutex_exit(&mpt->m_mutex); 2044 2045 /* deallocate everything that was allocated in mptsas_attach */ 2046 mptsas_cache_destroy(mpt); 2047 2048 mptsas_hba_fini(mpt); 2049 mptsas_cfg_fini(mpt); 2050 2051 /* Lower the power informing PM Framework */ 2052 if (mpt->m_options & MPTSAS_OPT_PM) { 2053 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 2054 mptsas_log(mpt, CE_WARN, 2055 "!mptsas%d: Lower power request failed " 2056 "during detach, ignoring.", 2057 mpt->m_instance); 2058 } 2059 2060 mutex_destroy(&mpt->m_tx_waitq_mutex); 2061 mutex_destroy(&mpt->m_passthru_mutex); 2062 mutex_destroy(&mpt->m_mutex); 2063 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 2064 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex); 2065 } 2066 cv_destroy(&mpt->m_cv); 2067 cv_destroy(&mpt->m_passthru_cv); 2068 cv_destroy(&mpt->m_fw_cv); 2069 cv_destroy(&mpt->m_config_cv); 2070 cv_destroy(&mpt->m_fw_diag_cv); 2071 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 2072 2073 mptsas_smp_teardown(mpt); 2074 mptsas_enc_teardown(mpt); 2075 mptsas_hba_teardown(mpt); 2076 2077 mptsas_config_space_fini(mpt); 2078 2079 mptsas_free_handshake_msg(mpt); 2080 2081 mptsas_fm_fini(mpt); 2082 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 2083 ddi_prop_remove_all(dip); 2084 2085 return (DDI_SUCCESS); 2086 } 2087 2088 static void 2089 mptsas_list_add(mptsas_t *mpt) 2090 { 2091 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2092 2093 if (mptsas_head == NULL) { 2094 mptsas_head = mpt; 2095 } else { 2096 mptsas_tail->m_next = mpt; 2097 } 2098 mptsas_tail = mpt; 2099 rw_exit(&mptsas_global_rwlock); 2100 } 2101 2102 static void 2103 mptsas_list_del(mptsas_t *mpt) 2104 { 2105 mptsas_t *m; 2106 /* 2107 * Remove device instance from the global linked list 2108 */ 2109 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2110 if (mptsas_head == mpt) { 2111 m = mptsas_head = mpt->m_next; 2112 } else { 2113 for (m = mptsas_head; m != NULL; m = m->m_next) { 2114 if (m->m_next == mpt) { 2115 m->m_next = mpt->m_next; 2116 break; 2117 } 2118 } 2119 if (m == NULL) { 2120 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 2121 } 2122 } 2123 2124 if (mptsas_tail == mpt) { 2125 mptsas_tail = m; 2126 } 2127 rw_exit(&mptsas_global_rwlock); 2128 } 2129 2130 static int 2131 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 2132 { 2133 ddi_dma_attr_t task_dma_attrs; 2134 2135 mpt->m_hshk_dma_size = 0; 2136 task_dma_attrs = mpt->m_msg_dma_attr; 2137 task_dma_attrs.dma_attr_sgllen = 1; 2138 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 2139 2140 /* allocate Task Management ddi_dma resources */ 2141 if (mptsas_dma_addr_create(mpt, task_dma_attrs, 2142 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp, 2143 alloc_size, NULL) == FALSE) { 2144 return (DDI_FAILURE); 2145 } 2146 mpt->m_hshk_dma_size = alloc_size; 2147 2148 return (DDI_SUCCESS); 2149 } 2150 2151 static void 2152 mptsas_free_handshake_msg(mptsas_t *mpt) 2153 { 2154 if (mpt->m_hshk_dma_size == 0) 2155 return; 2156 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl); 2157 mpt->m_hshk_dma_size = 0; 2158 } 2159 2160 static int 2161 mptsas_hba_setup(mptsas_t *mpt) 2162 { 2163 scsi_hba_tran_t *hba_tran; 2164 int tran_flags; 2165 2166 /* Allocate a transport structure */ 2167 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip, 2168 SCSI_HBA_CANSLEEP); 2169 ASSERT(mpt->m_tran != NULL); 2170 2171 hba_tran->tran_hba_private = mpt; 2172 hba_tran->tran_tgt_private = NULL; 2173 2174 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 2175 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 2176 2177 hba_tran->tran_start = mptsas_scsi_start; 2178 hba_tran->tran_reset = mptsas_scsi_reset; 2179 hba_tran->tran_abort = mptsas_scsi_abort; 2180 hba_tran->tran_getcap = mptsas_scsi_getcap; 2181 hba_tran->tran_setcap = mptsas_scsi_setcap; 2182 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 2183 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 2184 2185 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 2186 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 2187 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 2188 2189 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 2190 hba_tran->tran_get_name = mptsas_get_name; 2191 2192 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 2193 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 2194 hba_tran->tran_bus_reset = NULL; 2195 2196 hba_tran->tran_add_eventcall = NULL; 2197 hba_tran->tran_get_eventcookie = NULL; 2198 hba_tran->tran_post_event = NULL; 2199 hba_tran->tran_remove_eventcall = NULL; 2200 2201 hba_tran->tran_bus_config = mptsas_bus_config; 2202 2203 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 2204 2205 /* 2206 * All children of the HBA are iports. We need tran was cloned. 2207 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 2208 * inherited to iport's tran vector. 2209 */ 2210 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 2211 2212 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr, 2213 hba_tran, tran_flags) != DDI_SUCCESS) { 2214 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 2215 scsi_hba_tran_free(hba_tran); 2216 mpt->m_tran = NULL; 2217 return (FALSE); 2218 } 2219 return (TRUE); 2220 } 2221 2222 static void 2223 mptsas_hba_teardown(mptsas_t *mpt) 2224 { 2225 (void) scsi_hba_detach(mpt->m_dip); 2226 if (mpt->m_tran != NULL) { 2227 scsi_hba_tran_free(mpt->m_tran); 2228 mpt->m_tran = NULL; 2229 } 2230 } 2231 2232 static void 2233 mptsas_iport_register(mptsas_t *mpt) 2234 { 2235 int i, j; 2236 mptsas_phymask_t mask = 0x0; 2237 /* 2238 * initial value of mask is 0 2239 */ 2240 mutex_enter(&mpt->m_mutex); 2241 for (i = 0; i < mpt->m_num_phys; i++) { 2242 mptsas_phymask_t phy_mask = 0x0; 2243 char phy_mask_name[MPTSAS_MAX_PHYS]; 2244 uint8_t current_port; 2245 2246 if (mpt->m_phy_info[i].attached_devhdl == 0) 2247 continue; 2248 2249 bzero(phy_mask_name, sizeof (phy_mask_name)); 2250 2251 current_port = mpt->m_phy_info[i].port_num; 2252 2253 if ((mask & (1 << i)) != 0) 2254 continue; 2255 2256 for (j = 0; j < mpt->m_num_phys; j++) { 2257 if (mpt->m_phy_info[j].attached_devhdl && 2258 (mpt->m_phy_info[j].port_num == current_port)) { 2259 phy_mask |= (1 << j); 2260 } 2261 } 2262 mask = mask | phy_mask; 2263 2264 for (j = 0; j < mpt->m_num_phys; j++) { 2265 if ((phy_mask >> j) & 0x01) { 2266 mpt->m_phy_info[j].phy_mask = phy_mask; 2267 } 2268 } 2269 2270 (void) sprintf(phy_mask_name, "%x", phy_mask); 2271 2272 mutex_exit(&mpt->m_mutex); 2273 /* 2274 * register a iport 2275 */ 2276 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 2277 mutex_enter(&mpt->m_mutex); 2278 } 2279 mutex_exit(&mpt->m_mutex); 2280 /* 2281 * register a virtual port for RAID volume always 2282 */ 2283 (void) scsi_hba_iport_register(mpt->m_dip, "v0"); 2284 2285 } 2286 2287 static int 2288 mptsas_smp_setup(mptsas_t *mpt) 2289 { 2290 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip); 2291 ASSERT(mpt->m_smptran != NULL); 2292 mpt->m_smptran->smp_tran_hba_private = mpt; 2293 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 2294 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) { 2295 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 2296 smp_hba_tran_free(mpt->m_smptran); 2297 mpt->m_smptran = NULL; 2298 return (FALSE); 2299 } 2300 /* 2301 * Initialize smp hash table 2302 */ 2303 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT, 2304 mptsas_target_addr_hash, mptsas_target_addr_cmp, 2305 mptsas_smp_free, sizeof (mptsas_smp_t), 2306 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr), 2307 KM_SLEEP); 2308 mpt->m_smp_devhdl = 0xFFFF; 2309 2310 return (TRUE); 2311 } 2312 2313 static void 2314 mptsas_smp_teardown(mptsas_t *mpt) 2315 { 2316 (void) smp_hba_detach(mpt->m_dip); 2317 if (mpt->m_smptran != NULL) { 2318 smp_hba_tran_free(mpt->m_smptran); 2319 mpt->m_smptran = NULL; 2320 } 2321 mpt->m_smp_devhdl = 0; 2322 } 2323 2324 static int 2325 mptsas_enc_setup(mptsas_t *mpt) 2326 { 2327 list_create(&mpt->m_enclosures, sizeof (mptsas_enclosure_t), 2328 offsetof(mptsas_enclosure_t, me_link)); 2329 return (TRUE); 2330 } 2331 2332 static void 2333 mptsas_enc_teardown(mptsas_t *mpt) 2334 { 2335 mptsas_enclosure_t *mep; 2336 2337 while ((mep = list_remove_head(&mpt->m_enclosures)) != NULL) { 2338 kmem_free(mep, sizeof (mptsas_enclosure_t)); 2339 } 2340 list_destroy(&mpt->m_enclosures); 2341 } 2342 2343 static mptsas_enclosure_t * 2344 mptsas_enc_lookup(mptsas_t *mpt, uint16_t hdl) 2345 { 2346 mptsas_enclosure_t *mep; 2347 2348 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 2349 2350 for (mep = list_head(&mpt->m_enclosures); mep != NULL; 2351 mep = list_next(&mpt->m_enclosures, mep)) { 2352 if (hdl == mep->me_enchdl) { 2353 return (mep); 2354 } 2355 } 2356 2357 return (NULL); 2358 } 2359 2360 static int 2361 mptsas_cache_create(mptsas_t *mpt) 2362 { 2363 int instance = mpt->m_instance; 2364 char buf[64]; 2365 2366 /* 2367 * create kmem cache for packets 2368 */ 2369 (void) sprintf(buf, "mptsas%d_cache", instance); 2370 mpt->m_kmem_cache = kmem_cache_create(buf, 2371 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 2372 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 2373 NULL, (void *)mpt, NULL, 0); 2374 2375 if (mpt->m_kmem_cache == NULL) { 2376 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 2377 return (FALSE); 2378 } 2379 2380 /* 2381 * create kmem cache for extra SGL frames if SGL cannot 2382 * be accomodated into main request frame. 2383 */ 2384 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 2385 mpt->m_cache_frames = kmem_cache_create(buf, 2386 sizeof (mptsas_cache_frames_t), 8, 2387 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 2388 NULL, (void *)mpt, NULL, 0); 2389 2390 if (mpt->m_cache_frames == NULL) { 2391 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 2392 return (FALSE); 2393 } 2394 2395 return (TRUE); 2396 } 2397 2398 static void 2399 mptsas_cache_destroy(mptsas_t *mpt) 2400 { 2401 /* deallocate in reverse order */ 2402 if (mpt->m_cache_frames) { 2403 kmem_cache_destroy(mpt->m_cache_frames); 2404 mpt->m_cache_frames = NULL; 2405 } 2406 if (mpt->m_kmem_cache) { 2407 kmem_cache_destroy(mpt->m_kmem_cache); 2408 mpt->m_kmem_cache = NULL; 2409 } 2410 } 2411 2412 static int 2413 mptsas_power(dev_info_t *dip, int component, int level) 2414 { 2415 #ifndef __lock_lint 2416 _NOTE(ARGUNUSED(component)) 2417 #endif 2418 mptsas_t *mpt; 2419 int rval = DDI_SUCCESS; 2420 int polls = 0; 2421 uint32_t ioc_status; 2422 2423 if (scsi_hba_iport_unit_address(dip) != 0) 2424 return (DDI_SUCCESS); 2425 2426 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2427 if (mpt == NULL) { 2428 return (DDI_FAILURE); 2429 } 2430 2431 mutex_enter(&mpt->m_mutex); 2432 2433 /* 2434 * If the device is busy, don't lower its power level 2435 */ 2436 if (mpt->m_busy && (mpt->m_power_level > level)) { 2437 mutex_exit(&mpt->m_mutex); 2438 return (DDI_FAILURE); 2439 } 2440 switch (level) { 2441 case PM_LEVEL_D0: 2442 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2443 MPTSAS_POWER_ON(mpt); 2444 /* 2445 * Wait up to 30 seconds for IOC to come out of reset. 2446 */ 2447 while (((ioc_status = ddi_get32(mpt->m_datap, 2448 &mpt->m_reg->Doorbell)) & 2449 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2450 if (polls++ > 3000) { 2451 break; 2452 } 2453 delay(drv_usectohz(10000)); 2454 } 2455 /* 2456 * If IOC is not in operational state, try to hard reset it. 2457 */ 2458 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2459 MPI2_IOC_STATE_OPERATIONAL) { 2460 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 2461 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2462 mptsas_log(mpt, CE_WARN, 2463 "mptsas_power: hard reset failed"); 2464 mutex_exit(&mpt->m_mutex); 2465 return (DDI_FAILURE); 2466 } 2467 } 2468 mpt->m_power_level = PM_LEVEL_D0; 2469 break; 2470 case PM_LEVEL_D3: 2471 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2472 MPTSAS_POWER_OFF(mpt); 2473 break; 2474 default: 2475 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2476 mpt->m_instance, level); 2477 rval = DDI_FAILURE; 2478 break; 2479 } 2480 mutex_exit(&mpt->m_mutex); 2481 return (rval); 2482 } 2483 2484 /* 2485 * Initialize configuration space and figure out which 2486 * chip and revison of the chip the mpt driver is using. 2487 */ 2488 static int 2489 mptsas_config_space_init(mptsas_t *mpt) 2490 { 2491 NDBG0(("mptsas_config_space_init")); 2492 2493 if (mpt->m_config_handle != NULL) 2494 return (TRUE); 2495 2496 if (pci_config_setup(mpt->m_dip, 2497 &mpt->m_config_handle) != DDI_SUCCESS) { 2498 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 2499 return (FALSE); 2500 } 2501 2502 /* 2503 * This is a workaround for a XMITS ASIC bug which does not 2504 * drive the CBE upper bits. 2505 */ 2506 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 2507 PCI_STAT_PERROR) { 2508 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 2509 PCI_STAT_PERROR); 2510 } 2511 2512 mptsas_setup_cmd_reg(mpt); 2513 2514 /* 2515 * Get the chip device id: 2516 */ 2517 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2518 2519 /* 2520 * Save the revision. 2521 */ 2522 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2523 2524 /* 2525 * Save the SubSystem Vendor and Device IDs 2526 */ 2527 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2528 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2529 2530 /* 2531 * Set the latency timer to 0x40 as specified by the upa -> pci 2532 * bridge chip design team. This may be done by the sparc pci 2533 * bus nexus driver, but the driver should make sure the latency 2534 * timer is correct for performance reasons. 2535 */ 2536 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2537 MPTSAS_LATENCY_TIMER); 2538 2539 (void) mptsas_get_pci_cap(mpt); 2540 return (TRUE); 2541 } 2542 2543 static void 2544 mptsas_config_space_fini(mptsas_t *mpt) 2545 { 2546 if (mpt->m_config_handle != NULL) { 2547 mptsas_disable_bus_master(mpt); 2548 pci_config_teardown(&mpt->m_config_handle); 2549 mpt->m_config_handle = NULL; 2550 } 2551 } 2552 2553 static void 2554 mptsas_setup_cmd_reg(mptsas_t *mpt) 2555 { 2556 ushort_t cmdreg; 2557 2558 /* 2559 * Set the command register to the needed values. 2560 */ 2561 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2562 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2563 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2564 cmdreg &= ~PCI_COMM_IO; 2565 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2566 } 2567 2568 static void 2569 mptsas_disable_bus_master(mptsas_t *mpt) 2570 { 2571 ushort_t cmdreg; 2572 2573 /* 2574 * Clear the master enable bit in the PCI command register. 2575 * This prevents any bus mastering activity like DMA. 2576 */ 2577 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2578 cmdreg &= ~PCI_COMM_ME; 2579 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2580 } 2581 2582 int 2583 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2584 { 2585 ddi_dma_attr_t attrs; 2586 2587 attrs = mpt->m_io_dma_attr; 2588 attrs.dma_attr_sgllen = 1; 2589 2590 ASSERT(dma_statep != NULL); 2591 2592 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle, 2593 &dma_statep->accessp, &dma_statep->memp, dma_statep->size, 2594 &dma_statep->cookie) == FALSE) { 2595 return (DDI_FAILURE); 2596 } 2597 2598 return (DDI_SUCCESS); 2599 } 2600 2601 void 2602 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2603 { 2604 ASSERT(dma_statep != NULL); 2605 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp); 2606 dma_statep->size = 0; 2607 } 2608 2609 int 2610 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2611 { 2612 ddi_dma_attr_t attrs; 2613 ddi_dma_handle_t dma_handle; 2614 caddr_t memp; 2615 ddi_acc_handle_t accessp; 2616 int rval; 2617 2618 ASSERT(mutex_owned(&mpt->m_mutex)); 2619 2620 attrs = mpt->m_msg_dma_attr; 2621 attrs.dma_attr_sgllen = 1; 2622 attrs.dma_attr_granular = size; 2623 2624 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle, 2625 &accessp, &memp, size, NULL) == FALSE) { 2626 return (DDI_FAILURE); 2627 } 2628 2629 rval = (*callback) (mpt, memp, var, accessp); 2630 2631 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2632 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2633 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2634 rval = DDI_FAILURE; 2635 } 2636 2637 mptsas_dma_addr_destroy(&dma_handle, &accessp); 2638 return (rval); 2639 2640 } 2641 2642 static int 2643 mptsas_alloc_request_frames(mptsas_t *mpt) 2644 { 2645 ddi_dma_attr_t frame_dma_attrs; 2646 caddr_t memp; 2647 ddi_dma_cookie_t cookie; 2648 size_t mem_size; 2649 2650 /* 2651 * re-alloc when it has already alloced 2652 */ 2653 if (mpt->m_dma_req_frame_hdl) 2654 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2655 &mpt->m_acc_req_frame_hdl); 2656 2657 /* 2658 * The size of the request frame pool is: 2659 * Number of Request Frames * Request Frame Size 2660 */ 2661 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2662 2663 /* 2664 * set the DMA attributes. System Request Message Frames must be 2665 * aligned on a 16-byte boundry. 2666 */ 2667 frame_dma_attrs = mpt->m_msg_dma_attr; 2668 frame_dma_attrs.dma_attr_align = 16; 2669 frame_dma_attrs.dma_attr_sgllen = 1; 2670 2671 /* 2672 * allocate the request frame pool. 2673 */ 2674 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2675 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp, 2676 mem_size, &cookie) == FALSE) { 2677 return (DDI_FAILURE); 2678 } 2679 2680 /* 2681 * Store the request frame memory address. This chip uses this 2682 * address to dma to and from the driver's frame. The second 2683 * address is the address mpt uses to fill in the frame. 2684 */ 2685 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2686 mpt->m_req_frame = memp; 2687 2688 /* 2689 * Clear the request frame pool. 2690 */ 2691 bzero(mpt->m_req_frame, mem_size); 2692 2693 return (DDI_SUCCESS); 2694 } 2695 2696 static int 2697 mptsas_alloc_sense_bufs(mptsas_t *mpt) 2698 { 2699 ddi_dma_attr_t sense_dma_attrs; 2700 caddr_t memp; 2701 ddi_dma_cookie_t cookie; 2702 size_t mem_size; 2703 int num_extrqsense_bufs; 2704 2705 ASSERT(mpt->m_extreq_sense_refcount == 0); 2706 2707 /* 2708 * re-alloc when it has already alloced 2709 */ 2710 if (mpt->m_dma_req_sense_hdl) { 2711 rmfreemap(mpt->m_erqsense_map); 2712 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 2713 &mpt->m_acc_req_sense_hdl); 2714 } 2715 2716 /* 2717 * The size of the request sense pool is: 2718 * (Number of Request Frames - 2 ) * Request Sense Size + 2719 * extra memory for extended sense requests. 2720 */ 2721 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) + 2722 mptsas_extreq_sense_bufsize; 2723 2724 /* 2725 * set the DMA attributes. ARQ buffers 2726 * aligned on a 16-byte boundry. 2727 */ 2728 sense_dma_attrs = mpt->m_msg_dma_attr; 2729 sense_dma_attrs.dma_attr_align = 16; 2730 sense_dma_attrs.dma_attr_sgllen = 1; 2731 2732 /* 2733 * allocate the request sense buffer pool. 2734 */ 2735 if (mptsas_dma_addr_create(mpt, sense_dma_attrs, 2736 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp, 2737 mem_size, &cookie) == FALSE) { 2738 return (DDI_FAILURE); 2739 } 2740 2741 /* 2742 * Store the request sense base memory address. This chip uses this 2743 * address to dma the request sense data. The second 2744 * address is the address mpt uses to access the data. 2745 * The third is the base for the extended rqsense buffers. 2746 */ 2747 mpt->m_req_sense_dma_addr = cookie.dmac_laddress; 2748 mpt->m_req_sense = memp; 2749 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size; 2750 mpt->m_extreq_sense = memp; 2751 2752 /* 2753 * The extra memory is divided up into multiples of the base 2754 * buffer size in order to allocate via rmalloc(). 2755 * Note that the rmallocmap cannot start at zero! 2756 */ 2757 num_extrqsense_bufs = mptsas_extreq_sense_bufsize / 2758 mpt->m_req_sense_size; 2759 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs); 2760 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1); 2761 2762 /* 2763 * Clear the pool. 2764 */ 2765 bzero(mpt->m_req_sense, mem_size); 2766 2767 return (DDI_SUCCESS); 2768 } 2769 2770 static int 2771 mptsas_alloc_reply_frames(mptsas_t *mpt) 2772 { 2773 ddi_dma_attr_t frame_dma_attrs; 2774 caddr_t memp; 2775 ddi_dma_cookie_t cookie; 2776 size_t mem_size; 2777 2778 /* 2779 * re-alloc when it has already alloced 2780 */ 2781 if (mpt->m_dma_reply_frame_hdl) { 2782 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2783 &mpt->m_acc_reply_frame_hdl); 2784 } 2785 2786 /* 2787 * The size of the reply frame pool is: 2788 * Number of Reply Frames * Reply Frame Size 2789 */ 2790 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2791 2792 /* 2793 * set the DMA attributes. System Reply Message Frames must be 2794 * aligned on a 4-byte boundry. This is the default. 2795 */ 2796 frame_dma_attrs = mpt->m_msg_dma_attr; 2797 frame_dma_attrs.dma_attr_sgllen = 1; 2798 2799 /* 2800 * allocate the reply frame pool 2801 */ 2802 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2803 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp, 2804 mem_size, &cookie) == FALSE) { 2805 return (DDI_FAILURE); 2806 } 2807 2808 /* 2809 * Store the reply frame memory address. This chip uses this 2810 * address to dma to and from the driver's frame. The second 2811 * address is the address mpt uses to process the frame. 2812 */ 2813 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2814 mpt->m_reply_frame = memp; 2815 2816 /* 2817 * Clear the reply frame pool. 2818 */ 2819 bzero(mpt->m_reply_frame, mem_size); 2820 2821 return (DDI_SUCCESS); 2822 } 2823 2824 static int 2825 mptsas_alloc_free_queue(mptsas_t *mpt) 2826 { 2827 ddi_dma_attr_t frame_dma_attrs; 2828 caddr_t memp; 2829 ddi_dma_cookie_t cookie; 2830 size_t mem_size; 2831 2832 /* 2833 * re-alloc when it has already alloced 2834 */ 2835 if (mpt->m_dma_free_queue_hdl) { 2836 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2837 &mpt->m_acc_free_queue_hdl); 2838 } 2839 2840 /* 2841 * The reply free queue size is: 2842 * Reply Free Queue Depth * 4 2843 * The "4" is the size of one 32 bit address (low part of 64-bit 2844 * address) 2845 */ 2846 mem_size = mpt->m_free_queue_depth * 4; 2847 2848 /* 2849 * set the DMA attributes The Reply Free Queue must be aligned on a 2850 * 16-byte boundry. 2851 */ 2852 frame_dma_attrs = mpt->m_msg_dma_attr; 2853 frame_dma_attrs.dma_attr_align = 16; 2854 frame_dma_attrs.dma_attr_sgllen = 1; 2855 2856 /* 2857 * allocate the reply free queue 2858 */ 2859 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2860 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp, 2861 mem_size, &cookie) == FALSE) { 2862 return (DDI_FAILURE); 2863 } 2864 2865 /* 2866 * Store the reply free queue memory address. This chip uses this 2867 * address to read from the reply free queue. The second address 2868 * is the address mpt uses to manage the queue. 2869 */ 2870 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2871 mpt->m_free_queue = memp; 2872 2873 /* 2874 * Clear the reply free queue memory. 2875 */ 2876 bzero(mpt->m_free_queue, mem_size); 2877 2878 return (DDI_SUCCESS); 2879 } 2880 2881 static int 2882 mptsas_alloc_post_queue(mptsas_t *mpt) 2883 { 2884 ddi_dma_attr_t frame_dma_attrs; 2885 caddr_t memp; 2886 ddi_dma_cookie_t cookie; 2887 size_t mem_size; 2888 2889 /* 2890 * re-alloc when it has already alloced 2891 */ 2892 if (mpt->m_dma_post_queue_hdl) { 2893 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2894 &mpt->m_acc_post_queue_hdl); 2895 } 2896 2897 /* 2898 * The reply descriptor post queue size is: 2899 * Reply Descriptor Post Queue Depth * 8 2900 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2901 */ 2902 mem_size = mpt->m_post_queue_depth * 8; 2903 2904 /* 2905 * set the DMA attributes. The Reply Descriptor Post Queue must be 2906 * aligned on a 16-byte boundry. 2907 */ 2908 frame_dma_attrs = mpt->m_msg_dma_attr; 2909 frame_dma_attrs.dma_attr_align = 16; 2910 frame_dma_attrs.dma_attr_sgllen = 1; 2911 2912 /* 2913 * allocate the reply post queue 2914 */ 2915 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2916 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp, 2917 mem_size, &cookie) == FALSE) { 2918 return (DDI_FAILURE); 2919 } 2920 2921 /* 2922 * Store the reply descriptor post queue memory address. This chip 2923 * uses this address to write to the reply descriptor post queue. The 2924 * second address is the address mpt uses to manage the queue. 2925 */ 2926 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2927 mpt->m_post_queue = memp; 2928 2929 /* 2930 * Clear the reply post queue memory. 2931 */ 2932 bzero(mpt->m_post_queue, mem_size); 2933 2934 return (DDI_SUCCESS); 2935 } 2936 2937 static void 2938 mptsas_alloc_reply_args(mptsas_t *mpt) 2939 { 2940 if (mpt->m_replyh_args == NULL) { 2941 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 2942 mpt->m_max_replies, KM_SLEEP); 2943 } 2944 } 2945 2946 static int 2947 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2948 { 2949 mptsas_cache_frames_t *frames = NULL; 2950 if (cmd->cmd_extra_frames == NULL) { 2951 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2952 if (frames == NULL) { 2953 return (DDI_FAILURE); 2954 } 2955 cmd->cmd_extra_frames = frames; 2956 } 2957 return (DDI_SUCCESS); 2958 } 2959 2960 static void 2961 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2962 { 2963 if (cmd->cmd_extra_frames) { 2964 kmem_cache_free(mpt->m_cache_frames, 2965 (void *)cmd->cmd_extra_frames); 2966 cmd->cmd_extra_frames = NULL; 2967 } 2968 } 2969 2970 static void 2971 mptsas_cfg_fini(mptsas_t *mpt) 2972 { 2973 NDBG0(("mptsas_cfg_fini")); 2974 ddi_regs_map_free(&mpt->m_datap); 2975 } 2976 2977 static void 2978 mptsas_hba_fini(mptsas_t *mpt) 2979 { 2980 NDBG0(("mptsas_hba_fini")); 2981 2982 /* 2983 * Free up any allocated memory 2984 */ 2985 if (mpt->m_dma_req_frame_hdl) { 2986 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2987 &mpt->m_acc_req_frame_hdl); 2988 } 2989 2990 if (mpt->m_dma_req_sense_hdl) { 2991 rmfreemap(mpt->m_erqsense_map); 2992 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 2993 &mpt->m_acc_req_sense_hdl); 2994 } 2995 2996 if (mpt->m_dma_reply_frame_hdl) { 2997 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2998 &mpt->m_acc_reply_frame_hdl); 2999 } 3000 3001 if (mpt->m_dma_free_queue_hdl) { 3002 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 3003 &mpt->m_acc_free_queue_hdl); 3004 } 3005 3006 if (mpt->m_dma_post_queue_hdl) { 3007 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 3008 &mpt->m_acc_post_queue_hdl); 3009 } 3010 3011 if (mpt->m_replyh_args != NULL) { 3012 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 3013 * mpt->m_max_replies); 3014 } 3015 } 3016 3017 static int 3018 mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 3019 { 3020 int lun = 0; 3021 char *sas_wwn = NULL; 3022 int phynum = -1; 3023 int reallen = 0; 3024 3025 /* Get the target num */ 3026 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 3027 LUN_PROP, 0); 3028 3029 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 3030 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 3031 /* 3032 * Stick in the address of form "pPHY,LUN" 3033 */ 3034 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 3035 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, 3036 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) 3037 == DDI_PROP_SUCCESS) { 3038 /* 3039 * Stick in the address of the form "wWWN,LUN" 3040 */ 3041 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun); 3042 ddi_prop_free(sas_wwn); 3043 } else { 3044 return (DDI_FAILURE); 3045 } 3046 3047 ASSERT(reallen < len); 3048 if (reallen >= len) { 3049 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 3050 "length too small, it needs to be %d bytes", reallen + 1); 3051 } 3052 return (DDI_SUCCESS); 3053 } 3054 3055 /* 3056 * tran_tgt_init(9E) - target device instance initialization 3057 */ 3058 static int 3059 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3060 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3061 { 3062 #ifndef __lock_lint 3063 _NOTE(ARGUNUSED(hba_tran)) 3064 #endif 3065 3066 /* 3067 * At this point, the scsi_device structure already exists 3068 * and has been initialized. 3069 * 3070 * Use this function to allocate target-private data structures, 3071 * if needed by this HBA. Add revised flow-control and queue 3072 * properties for child here, if desired and if you can tell they 3073 * support tagged queueing by now. 3074 */ 3075 mptsas_t *mpt; 3076 int lun = sd->sd_address.a_lun; 3077 mdi_pathinfo_t *pip = NULL; 3078 mptsas_tgt_private_t *tgt_private = NULL; 3079 mptsas_target_t *ptgt = NULL; 3080 char *psas_wwn = NULL; 3081 mptsas_phymask_t phymask = 0; 3082 uint64_t sas_wwn = 0; 3083 mptsas_target_addr_t addr; 3084 mpt = SDEV2MPT(sd); 3085 3086 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 3087 3088 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 3089 (void *)hba_dip, (void *)tgt_dip, lun)); 3090 3091 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 3092 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 3093 ddi_set_name_addr(tgt_dip, NULL); 3094 return (DDI_FAILURE); 3095 } 3096 /* 3097 * phymask is 0 means the virtual port for RAID 3098 */ 3099 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 3100 "phymask", 0); 3101 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3102 if ((pip = (void *)(sd->sd_private)) == NULL) { 3103 /* 3104 * Very bad news if this occurs. Somehow scsi_vhci has 3105 * lost the pathinfo node for this target. 3106 */ 3107 return (DDI_NOT_WELL_FORMED); 3108 } 3109 3110 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 3111 DDI_PROP_SUCCESS) { 3112 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 3113 return (DDI_FAILURE); 3114 } 3115 3116 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 3117 &psas_wwn) == MDI_SUCCESS) { 3118 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3119 sas_wwn = 0; 3120 } 3121 (void) mdi_prop_free(psas_wwn); 3122 } 3123 } else { 3124 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 3125 DDI_PROP_DONTPASS, LUN_PROP, 0); 3126 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 3127 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 3128 DDI_PROP_SUCCESS) { 3129 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3130 sas_wwn = 0; 3131 } 3132 ddi_prop_free(psas_wwn); 3133 } else { 3134 sas_wwn = 0; 3135 } 3136 } 3137 3138 ASSERT((sas_wwn != 0) || (phymask != 0)); 3139 addr.mta_wwn = sas_wwn; 3140 addr.mta_phymask = phymask; 3141 mutex_enter(&mpt->m_mutex); 3142 ptgt = refhash_lookup(mpt->m_targets, &addr); 3143 mutex_exit(&mpt->m_mutex); 3144 if (ptgt == NULL) { 3145 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 3146 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 3147 sas_wwn); 3148 return (DDI_FAILURE); 3149 } 3150 if (hba_tran->tran_tgt_private == NULL) { 3151 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 3152 KM_SLEEP); 3153 tgt_private->t_lun = lun; 3154 tgt_private->t_private = ptgt; 3155 hba_tran->tran_tgt_private = tgt_private; 3156 } 3157 3158 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3159 return (DDI_SUCCESS); 3160 } 3161 mutex_enter(&mpt->m_mutex); 3162 3163 if (ptgt->m_deviceinfo & 3164 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 3165 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 3166 uchar_t *inq89 = NULL; 3167 int inq89_len = 0x238; 3168 int reallen = 0; 3169 int rval = 0; 3170 struct sata_id *sid = NULL; 3171 char model[SATA_ID_MODEL_LEN + 1]; 3172 char fw[SATA_ID_FW_LEN + 1]; 3173 char *vid, *pid; 3174 3175 mutex_exit(&mpt->m_mutex); 3176 /* 3177 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 3178 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 3179 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 3180 */ 3181 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 3182 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 3183 inq89, inq89_len, &reallen, 1); 3184 3185 if (rval != 0) { 3186 if (inq89 != NULL) { 3187 kmem_free(inq89, inq89_len); 3188 } 3189 3190 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 3191 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 3192 return (DDI_SUCCESS); 3193 } 3194 sid = (void *)(&inq89[60]); 3195 3196 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 3197 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 3198 3199 model[SATA_ID_MODEL_LEN] = 0; 3200 fw[SATA_ID_FW_LEN] = 0; 3201 3202 sata_split_model(model, &vid, &pid); 3203 3204 /* 3205 * override SCSA "inquiry-*" properties 3206 */ 3207 if (vid) 3208 (void) scsi_device_prop_update_inqstring(sd, 3209 INQUIRY_VENDOR_ID, vid, strlen(vid)); 3210 if (pid) 3211 (void) scsi_device_prop_update_inqstring(sd, 3212 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 3213 (void) scsi_device_prop_update_inqstring(sd, 3214 INQUIRY_REVISION_ID, fw, strlen(fw)); 3215 3216 if (inq89 != NULL) { 3217 kmem_free(inq89, inq89_len); 3218 } 3219 } else { 3220 mutex_exit(&mpt->m_mutex); 3221 } 3222 3223 return (DDI_SUCCESS); 3224 } 3225 /* 3226 * tran_tgt_free(9E) - target device instance deallocation 3227 */ 3228 static void 3229 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3230 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3231 { 3232 #ifndef __lock_lint 3233 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 3234 #endif 3235 3236 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 3237 3238 if (tgt_private != NULL) { 3239 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 3240 hba_tran->tran_tgt_private = NULL; 3241 } 3242 } 3243 3244 /* 3245 * scsi_pkt handling 3246 * 3247 * Visible to the external world via the transport structure. 3248 */ 3249 3250 /* 3251 * Notes: 3252 * - transport the command to the addressed SCSI target/lun device 3253 * - normal operation is to schedule the command to be transported, 3254 * and return TRAN_ACCEPT if this is successful. 3255 * - if NO_INTR, tran_start must poll device for command completion 3256 */ 3257 static int 3258 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 3259 { 3260 #ifndef __lock_lint 3261 _NOTE(ARGUNUSED(ap)) 3262 #endif 3263 mptsas_t *mpt = PKT2MPT(pkt); 3264 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3265 int rval; 3266 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3267 3268 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 3269 ASSERT(ptgt); 3270 if (ptgt == NULL) 3271 return (TRAN_FATAL_ERROR); 3272 3273 /* 3274 * prepare the pkt before taking mutex. 3275 */ 3276 rval = mptsas_prepare_pkt(cmd); 3277 if (rval != TRAN_ACCEPT) { 3278 return (rval); 3279 } 3280 3281 /* 3282 * Send the command to target/lun, however your HBA requires it. 3283 * If busy, return TRAN_BUSY; if there's some other formatting error 3284 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 3285 * return of TRAN_ACCEPT. 3286 * 3287 * Remember that access to shared resources, including the mptsas_t 3288 * data structure and the HBA hardware registers, must be protected 3289 * with mutexes, here and everywhere. 3290 * 3291 * Also remember that at interrupt time, you'll get an argument 3292 * to the interrupt handler which is a pointer to your mptsas_t 3293 * structure; you'll have to remember which commands are outstanding 3294 * and which scsi_pkt is the currently-running command so the 3295 * interrupt handler can refer to the pkt to set completion 3296 * status, call the target driver back through pkt_comp, etc. 3297 * 3298 * If the instance lock is held by other thread, don't spin to wait 3299 * for it. Instead, queue the cmd and next time when the instance lock 3300 * is not held, accept all the queued cmd. A extra tx_waitq is 3301 * introduced to protect the queue. 3302 * 3303 * The polled cmd will not be queud and accepted as usual. 3304 * 3305 * Under the tx_waitq mutex, record whether a thread is draining 3306 * the tx_waitq. An IO requesting thread that finds the instance 3307 * mutex contended appends to the tx_waitq and while holding the 3308 * tx_wait mutex, if the draining flag is not set, sets it and then 3309 * proceeds to spin for the instance mutex. This scheme ensures that 3310 * the last cmd in a burst be processed. 3311 * 3312 * we enable this feature only when the helper threads are enabled, 3313 * at which we think the loads are heavy. 3314 * 3315 * per instance mutex m_tx_waitq_mutex is introduced to protect the 3316 * m_tx_waitqtail, m_tx_waitq, m_tx_draining. 3317 */ 3318 3319 if (mpt->m_doneq_thread_n) { 3320 if (mutex_tryenter(&mpt->m_mutex) != 0) { 3321 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3322 mutex_exit(&mpt->m_mutex); 3323 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3324 mutex_enter(&mpt->m_mutex); 3325 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3326 mutex_exit(&mpt->m_mutex); 3327 } else { 3328 mutex_enter(&mpt->m_tx_waitq_mutex); 3329 /* 3330 * ptgt->m_dr_flag is protected by m_mutex or 3331 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex 3332 * is acquired. 3333 */ 3334 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3335 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3336 /* 3337 * The command should be allowed to 3338 * retry by returning TRAN_BUSY to 3339 * to stall the I/O's which come from 3340 * scsi_vhci since the device/path is 3341 * in unstable state now. 3342 */ 3343 mutex_exit(&mpt->m_tx_waitq_mutex); 3344 return (TRAN_BUSY); 3345 } else { 3346 /* 3347 * The device is offline, just fail the 3348 * command by returning 3349 * TRAN_FATAL_ERROR. 3350 */ 3351 mutex_exit(&mpt->m_tx_waitq_mutex); 3352 return (TRAN_FATAL_ERROR); 3353 } 3354 } 3355 if (mpt->m_tx_draining) { 3356 cmd->cmd_flags |= CFLAG_TXQ; 3357 *mpt->m_tx_waitqtail = cmd; 3358 mpt->m_tx_waitqtail = &cmd->cmd_linkp; 3359 mutex_exit(&mpt->m_tx_waitq_mutex); 3360 } else { /* drain the queue */ 3361 mpt->m_tx_draining = 1; 3362 mutex_exit(&mpt->m_tx_waitq_mutex); 3363 mutex_enter(&mpt->m_mutex); 3364 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3365 mutex_exit(&mpt->m_mutex); 3366 } 3367 } 3368 } else { 3369 mutex_enter(&mpt->m_mutex); 3370 /* 3371 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3372 * in this case, m_mutex is acquired. 3373 */ 3374 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3375 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3376 /* 3377 * commands should be allowed to retry by 3378 * returning TRAN_BUSY to stall the I/O's 3379 * which come from scsi_vhci since the device/ 3380 * path is in unstable state now. 3381 */ 3382 mutex_exit(&mpt->m_mutex); 3383 return (TRAN_BUSY); 3384 } else { 3385 /* 3386 * The device is offline, just fail the 3387 * command by returning TRAN_FATAL_ERROR. 3388 */ 3389 mutex_exit(&mpt->m_mutex); 3390 return (TRAN_FATAL_ERROR); 3391 } 3392 } 3393 rval = mptsas_accept_pkt(mpt, cmd); 3394 mutex_exit(&mpt->m_mutex); 3395 } 3396 3397 return (rval); 3398 } 3399 3400 /* 3401 * Accept all the queued cmds(if any) before accept the current one. 3402 */ 3403 static int 3404 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3405 { 3406 int rval; 3407 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3408 3409 ASSERT(mutex_owned(&mpt->m_mutex)); 3410 /* 3411 * The call to mptsas_accept_tx_waitq() must always be performed 3412 * because that is where mpt->m_tx_draining is cleared. 3413 */ 3414 mutex_enter(&mpt->m_tx_waitq_mutex); 3415 mptsas_accept_tx_waitq(mpt); 3416 mutex_exit(&mpt->m_tx_waitq_mutex); 3417 /* 3418 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3419 * in this case, m_mutex is acquired. 3420 */ 3421 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3422 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3423 /* 3424 * The command should be allowed to retry by returning 3425 * TRAN_BUSY to stall the I/O's which come from 3426 * scsi_vhci since the device/path is in unstable state 3427 * now. 3428 */ 3429 return (TRAN_BUSY); 3430 } else { 3431 /* 3432 * The device is offline, just fail the command by 3433 * return TRAN_FATAL_ERROR. 3434 */ 3435 return (TRAN_FATAL_ERROR); 3436 } 3437 } 3438 rval = mptsas_accept_pkt(mpt, cmd); 3439 3440 return (rval); 3441 } 3442 3443 static int 3444 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3445 { 3446 int rval = TRAN_ACCEPT; 3447 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3448 3449 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3450 3451 ASSERT(mutex_owned(&mpt->m_mutex)); 3452 3453 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3454 rval = mptsas_prepare_pkt(cmd); 3455 if (rval != TRAN_ACCEPT) { 3456 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3457 return (rval); 3458 } 3459 } 3460 3461 /* 3462 * reset the throttle if we were draining 3463 */ 3464 if ((ptgt->m_t_ncmds == 0) && 3465 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3466 NDBG23(("reset throttle")); 3467 ASSERT(ptgt->m_reset_delay == 0); 3468 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3469 } 3470 3471 /* 3472 * If HBA is being reset, the DevHandles are being re-initialized, 3473 * which means that they could be invalid even if the target is still 3474 * attached. Check if being reset and if DevHandle is being 3475 * re-initialized. If this is the case, return BUSY so the I/O can be 3476 * retried later. 3477 */ 3478 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) { 3479 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 3480 if (cmd->cmd_flags & CFLAG_TXQ) { 3481 mptsas_doneq_add(mpt, cmd); 3482 mptsas_doneq_empty(mpt); 3483 return (rval); 3484 } else { 3485 return (TRAN_BUSY); 3486 } 3487 } 3488 3489 /* 3490 * If device handle has already been invalidated, just 3491 * fail the command. In theory, command from scsi_vhci 3492 * client is impossible send down command with invalid 3493 * devhdl since devhdl is set after path offline, target 3494 * driver is not suppose to select a offlined path. 3495 */ 3496 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3497 NDBG3(("rejecting command, it might because invalid devhdl " 3498 "request.")); 3499 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3500 if (cmd->cmd_flags & CFLAG_TXQ) { 3501 mptsas_doneq_add(mpt, cmd); 3502 mptsas_doneq_empty(mpt); 3503 return (rval); 3504 } else { 3505 return (TRAN_FATAL_ERROR); 3506 } 3507 } 3508 /* 3509 * The first case is the normal case. mpt gets a command from the 3510 * target driver and starts it. 3511 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3512 * commands is m_max_requests - 2. 3513 */ 3514 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 3515 (ptgt->m_t_throttle > HOLD_THROTTLE) && 3516 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3517 (ptgt->m_reset_delay == 0) && 3518 (ptgt->m_t_nwait == 0) && 3519 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3520 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3521 (void) mptsas_start_cmd(mpt, cmd); 3522 } else { 3523 mptsas_waitq_add(mpt, cmd); 3524 } 3525 } else { 3526 /* 3527 * Add this pkt to the work queue 3528 */ 3529 mptsas_waitq_add(mpt, cmd); 3530 3531 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3532 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3533 3534 /* 3535 * Only flush the doneq if this is not a TM 3536 * cmd. For TM cmds the flushing of the 3537 * doneq will be done in those routines. 3538 */ 3539 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3540 mptsas_doneq_empty(mpt); 3541 } 3542 } 3543 } 3544 return (rval); 3545 } 3546 3547 int 3548 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3549 { 3550 mptsas_slots_t *slots = mpt->m_active; 3551 uint_t slot, start_rotor; 3552 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3553 3554 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 3555 3556 /* 3557 * Account for reserved TM request slot and reserved SMID of 0. 3558 */ 3559 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2)); 3560 3561 /* 3562 * Find the next available slot, beginning at m_rotor. If no slot is 3563 * available, we'll return FALSE to indicate that. This mechanism 3564 * considers only the normal slots, not the reserved slot 0 nor the 3565 * task management slot m_n_normal + 1. The rotor is left to point to 3566 * the normal slot after the one we select, unless we select the last 3567 * normal slot in which case it returns to slot 1. 3568 */ 3569 start_rotor = slots->m_rotor; 3570 do { 3571 slot = slots->m_rotor++; 3572 if (slots->m_rotor > slots->m_n_normal) 3573 slots->m_rotor = 1; 3574 3575 if (slots->m_rotor == start_rotor) 3576 break; 3577 } while (slots->m_slot[slot] != NULL); 3578 3579 if (slots->m_slot[slot] != NULL) 3580 return (FALSE); 3581 3582 ASSERT(slot != 0 && slot <= slots->m_n_normal); 3583 3584 cmd->cmd_slot = slot; 3585 slots->m_slot[slot] = cmd; 3586 mpt->m_ncmds++; 3587 3588 /* 3589 * only increment per target ncmds if this is not a 3590 * command that has no target associated with it (i.e. a 3591 * event acknoledgment) 3592 */ 3593 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3594 /* 3595 * Expiration time is set in mptsas_start_cmd 3596 */ 3597 ptgt->m_t_ncmds++; 3598 cmd->cmd_active_expiration = 0; 3599 } else { 3600 /* 3601 * Initialize expiration time for passthrough commands, 3602 */ 3603 cmd->cmd_active_expiration = gethrtime() + 3604 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC; 3605 } 3606 return (TRUE); 3607 } 3608 3609 /* 3610 * prepare the pkt: 3611 * the pkt may have been resubmitted or just reused so 3612 * initialize some fields and do some checks. 3613 */ 3614 static int 3615 mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3616 { 3617 struct scsi_pkt *pkt = CMD2PKT(cmd); 3618 3619 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3620 3621 /* 3622 * Reinitialize some fields that need it; the packet may 3623 * have been resubmitted 3624 */ 3625 pkt->pkt_reason = CMD_CMPLT; 3626 pkt->pkt_state = 0; 3627 pkt->pkt_statistics = 0; 3628 pkt->pkt_resid = 0; 3629 cmd->cmd_age = 0; 3630 cmd->cmd_pkt_flags = pkt->pkt_flags; 3631 3632 /* 3633 * zero status byte. 3634 */ 3635 *(pkt->pkt_scbp) = 0; 3636 3637 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3638 pkt->pkt_resid = cmd->cmd_dmacount; 3639 3640 /* 3641 * consistent packets need to be sync'ed first 3642 * (only for data going out) 3643 */ 3644 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3645 (cmd->cmd_flags & CFLAG_DMASEND)) { 3646 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3647 DDI_DMA_SYNC_FORDEV); 3648 } 3649 } 3650 3651 cmd->cmd_flags = 3652 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3653 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3654 3655 return (TRAN_ACCEPT); 3656 } 3657 3658 /* 3659 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3660 * 3661 * One of three possibilities: 3662 * - allocate scsi_pkt 3663 * - allocate scsi_pkt and DMA resources 3664 * - allocate DMA resources to an already-allocated pkt 3665 */ 3666 static struct scsi_pkt * 3667 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3668 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3669 int (*callback)(), caddr_t arg) 3670 { 3671 mptsas_cmd_t *cmd, *new_cmd; 3672 mptsas_t *mpt = ADDR2MPT(ap); 3673 uint_t oldcookiec; 3674 mptsas_target_t *ptgt = NULL; 3675 int rval; 3676 mptsas_tgt_private_t *tgt_private; 3677 int kf; 3678 3679 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3680 3681 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3682 tran_tgt_private; 3683 ASSERT(tgt_private != NULL); 3684 if (tgt_private == NULL) { 3685 return (NULL); 3686 } 3687 ptgt = tgt_private->t_private; 3688 ASSERT(ptgt != NULL); 3689 if (ptgt == NULL) 3690 return (NULL); 3691 ap->a_target = ptgt->m_devhdl; 3692 ap->a_lun = tgt_private->t_lun; 3693 3694 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3695 #ifdef MPTSAS_TEST_EXTRN_ALLOC 3696 statuslen *= 100; tgtlen *= 4; 3697 #endif 3698 NDBG3(("mptsas_scsi_init_pkt:\n" 3699 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3700 ap->a_target, (void *)pkt, (void *)bp, 3701 cmdlen, statuslen, tgtlen, flags)); 3702 3703 /* 3704 * Allocate the new packet. 3705 */ 3706 if (pkt == NULL) { 3707 ddi_dma_handle_t save_dma_handle; 3708 3709 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3710 if (cmd == NULL) 3711 return (NULL); 3712 3713 save_dma_handle = cmd->cmd_dmahandle; 3714 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3715 cmd->cmd_dmahandle = save_dma_handle; 3716 3717 pkt = (void *)((uchar_t *)cmd + 3718 sizeof (struct mptsas_cmd)); 3719 pkt->pkt_ha_private = (opaque_t)cmd; 3720 pkt->pkt_address = *ap; 3721 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3722 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3723 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3724 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3725 cmd->cmd_cdblen = (uchar_t)cmdlen; 3726 cmd->cmd_scblen = statuslen; 3727 cmd->cmd_rqslen = SENSE_LENGTH; 3728 cmd->cmd_tgt_addr = ptgt; 3729 3730 if ((cmdlen > sizeof (cmd->cmd_cdb)) || 3731 (tgtlen > PKT_PRIV_LEN) || 3732 (statuslen > EXTCMDS_STATUS_SIZE)) { 3733 int failure; 3734 3735 /* 3736 * We are going to allocate external packet space which 3737 * might include the sense data buffer for DMA so we 3738 * need to increase the reference counter here. In a 3739 * case the HBA is in reset we just simply free the 3740 * allocated packet and bail out. 3741 */ 3742 mutex_enter(&mpt->m_mutex); 3743 if (mpt->m_in_reset) { 3744 mutex_exit(&mpt->m_mutex); 3745 3746 cmd->cmd_flags = CFLAG_FREE; 3747 kmem_cache_free(mpt->m_kmem_cache, cmd); 3748 return (NULL); 3749 } 3750 mpt->m_extreq_sense_refcount++; 3751 ASSERT(mpt->m_extreq_sense_refcount > 0); 3752 mutex_exit(&mpt->m_mutex); 3753 3754 /* 3755 * if extern alloc fails, all will be 3756 * deallocated, including cmd 3757 */ 3758 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3759 cmdlen, tgtlen, statuslen, kf); 3760 3761 if (failure != 0 || cmd->cmd_extrqslen == 0) { 3762 /* 3763 * If the external packet space allocation 3764 * failed, or we didn't allocate the sense 3765 * data buffer for DMA we need to decrease the 3766 * reference counter. 3767 */ 3768 mutex_enter(&mpt->m_mutex); 3769 ASSERT(mpt->m_extreq_sense_refcount > 0); 3770 mpt->m_extreq_sense_refcount--; 3771 if (mpt->m_extreq_sense_refcount == 0) 3772 cv_broadcast( 3773 &mpt->m_extreq_sense_refcount_cv); 3774 mutex_exit(&mpt->m_mutex); 3775 3776 if (failure != 0) { 3777 /* 3778 * if extern allocation fails, it will 3779 * deallocate the new pkt as well 3780 */ 3781 return (NULL); 3782 } 3783 } 3784 } 3785 new_cmd = cmd; 3786 3787 } else { 3788 cmd = PKT2CMD(pkt); 3789 new_cmd = NULL; 3790 } 3791 3792 3793 /* grab cmd->cmd_cookiec here as oldcookiec */ 3794 3795 oldcookiec = cmd->cmd_cookiec; 3796 3797 /* 3798 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3799 * greater than 0 and we'll need to grab the next dma window 3800 */ 3801 /* 3802 * SLM-not doing extra command frame right now; may add later 3803 */ 3804 3805 if (cmd->cmd_nwin > 0) { 3806 3807 /* 3808 * Make sure we havn't gone past the the total number 3809 * of windows 3810 */ 3811 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3812 return (NULL); 3813 } 3814 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3815 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3816 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3817 return (NULL); 3818 } 3819 goto get_dma_cookies; 3820 } 3821 3822 3823 if (flags & PKT_XARQ) { 3824 cmd->cmd_flags |= CFLAG_XARQ; 3825 } 3826 3827 /* 3828 * DMA resource allocation. This version assumes your 3829 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3830 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3831 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3832 */ 3833 if (bp && (bp->b_bcount != 0) && 3834 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3835 3836 int cnt, dma_flags; 3837 mptti_t *dmap; /* ptr to the S/G list */ 3838 3839 /* 3840 * Set up DMA memory and position to the next DMA segment. 3841 */ 3842 ASSERT(cmd->cmd_dmahandle != NULL); 3843 3844 if (bp->b_flags & B_READ) { 3845 dma_flags = DDI_DMA_READ; 3846 cmd->cmd_flags &= ~CFLAG_DMASEND; 3847 } else { 3848 dma_flags = DDI_DMA_WRITE; 3849 cmd->cmd_flags |= CFLAG_DMASEND; 3850 } 3851 if (flags & PKT_CONSISTENT) { 3852 cmd->cmd_flags |= CFLAG_CMDIOPB; 3853 dma_flags |= DDI_DMA_CONSISTENT; 3854 } 3855 3856 if (flags & PKT_DMA_PARTIAL) { 3857 dma_flags |= DDI_DMA_PARTIAL; 3858 } 3859 3860 /* 3861 * workaround for byte hole issue on psycho and 3862 * schizo pre 2.1 3863 */ 3864 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3865 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3866 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3867 dma_flags |= DDI_DMA_CONSISTENT; 3868 } 3869 3870 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3871 dma_flags, callback, arg, 3872 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3873 if (rval == DDI_DMA_PARTIAL_MAP) { 3874 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3875 &cmd->cmd_nwin); 3876 cmd->cmd_winindex = 0; 3877 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3878 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3879 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3880 &cmd->cmd_cookiec); 3881 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3882 switch (rval) { 3883 case DDI_DMA_NORESOURCES: 3884 bioerror(bp, 0); 3885 break; 3886 case DDI_DMA_BADATTR: 3887 case DDI_DMA_NOMAPPING: 3888 bioerror(bp, EFAULT); 3889 break; 3890 case DDI_DMA_TOOBIG: 3891 default: 3892 bioerror(bp, EINVAL); 3893 break; 3894 } 3895 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3896 if (new_cmd) { 3897 mptsas_scsi_destroy_pkt(ap, pkt); 3898 } 3899 return ((struct scsi_pkt *)NULL); 3900 } 3901 3902 get_dma_cookies: 3903 cmd->cmd_flags |= CFLAG_DMAVALID; 3904 ASSERT(cmd->cmd_cookiec > 0); 3905 3906 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3907 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3908 cmd->cmd_cookiec); 3909 bioerror(bp, EINVAL); 3910 if (new_cmd) { 3911 mptsas_scsi_destroy_pkt(ap, pkt); 3912 } 3913 return ((struct scsi_pkt *)NULL); 3914 } 3915 3916 /* 3917 * Allocate extra SGL buffer if needed. 3918 */ 3919 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3920 (cmd->cmd_extra_frames == NULL)) { 3921 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3922 DDI_FAILURE) { 3923 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3924 "failed"); 3925 bioerror(bp, ENOMEM); 3926 if (new_cmd) { 3927 mptsas_scsi_destroy_pkt(ap, pkt); 3928 } 3929 return ((struct scsi_pkt *)NULL); 3930 } 3931 } 3932 3933 /* 3934 * Always use scatter-gather transfer 3935 * Use the loop below to store physical addresses of 3936 * DMA segments, from the DMA cookies, into your HBA's 3937 * scatter-gather list. 3938 * We need to ensure we have enough kmem alloc'd 3939 * for the sg entries since we are no longer using an 3940 * array inside mptsas_cmd_t. 3941 * 3942 * We check cmd->cmd_cookiec against oldcookiec so 3943 * the scatter-gather list is correctly allocated 3944 */ 3945 3946 if (oldcookiec != cmd->cmd_cookiec) { 3947 if (cmd->cmd_sg != (mptti_t *)NULL) { 3948 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3949 oldcookiec); 3950 cmd->cmd_sg = NULL; 3951 } 3952 } 3953 3954 if (cmd->cmd_sg == (mptti_t *)NULL) { 3955 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3956 cmd->cmd_cookiec), kf); 3957 3958 if (cmd->cmd_sg == (mptti_t *)NULL) { 3959 mptsas_log(mpt, CE_WARN, 3960 "unable to kmem_alloc enough memory " 3961 "for scatter/gather list"); 3962 /* 3963 * if we have an ENOMEM condition we need to behave 3964 * the same way as the rest of this routine 3965 */ 3966 3967 bioerror(bp, ENOMEM); 3968 if (new_cmd) { 3969 mptsas_scsi_destroy_pkt(ap, pkt); 3970 } 3971 return ((struct scsi_pkt *)NULL); 3972 } 3973 } 3974 3975 dmap = cmd->cmd_sg; 3976 3977 ASSERT(cmd->cmd_cookie.dmac_size != 0); 3978 3979 /* 3980 * store the first segment into the S/G list 3981 */ 3982 dmap->count = cmd->cmd_cookie.dmac_size; 3983 dmap->addr.address64.Low = (uint32_t) 3984 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3985 dmap->addr.address64.High = (uint32_t) 3986 (cmd->cmd_cookie.dmac_laddress >> 32); 3987 3988 /* 3989 * dmacount counts the size of the dma for this window 3990 * (if partial dma is being used). totaldmacount 3991 * keeps track of the total amount of dma we have 3992 * transferred for all the windows (needed to calculate 3993 * the resid value below). 3994 */ 3995 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 3996 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3997 3998 /* 3999 * We already stored the first DMA scatter gather segment, 4000 * start at 1 if we need to store more. 4001 */ 4002 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 4003 /* 4004 * Get next DMA cookie 4005 */ 4006 ddi_dma_nextcookie(cmd->cmd_dmahandle, 4007 &cmd->cmd_cookie); 4008 dmap++; 4009 4010 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 4011 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 4012 4013 /* 4014 * store the segment parms into the S/G list 4015 */ 4016 dmap->count = cmd->cmd_cookie.dmac_size; 4017 dmap->addr.address64.Low = (uint32_t) 4018 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 4019 dmap->addr.address64.High = (uint32_t) 4020 (cmd->cmd_cookie.dmac_laddress >> 32); 4021 } 4022 4023 /* 4024 * If this was partially allocated we set the resid 4025 * the amount of data NOT transferred in this window 4026 * If there is only one window, the resid will be 0 4027 */ 4028 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 4029 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.", 4030 cmd->cmd_dmacount)); 4031 } 4032 return (pkt); 4033 } 4034 4035 /* 4036 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 4037 * 4038 * Notes: 4039 * - also frees DMA resources if allocated 4040 * - implicit DMA synchonization 4041 */ 4042 static void 4043 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4044 { 4045 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4046 mptsas_t *mpt = ADDR2MPT(ap); 4047 4048 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 4049 ap->a_target, (void *)pkt)); 4050 4051 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4052 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4053 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4054 } 4055 4056 if (cmd->cmd_sg) { 4057 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 4058 cmd->cmd_sg = NULL; 4059 } 4060 4061 mptsas_free_extra_sgl_frame(mpt, cmd); 4062 4063 if ((cmd->cmd_flags & 4064 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 4065 CFLAG_SCBEXTERN)) == 0) { 4066 cmd->cmd_flags = CFLAG_FREE; 4067 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4068 } else { 4069 boolean_t extrqslen = cmd->cmd_extrqslen != 0; 4070 4071 mptsas_pkt_destroy_extern(mpt, cmd); 4072 4073 /* 4074 * If the packet had the sense data buffer for DMA allocated we 4075 * need to decrease the reference counter. 4076 */ 4077 if (extrqslen) { 4078 mutex_enter(&mpt->m_mutex); 4079 ASSERT(mpt->m_extreq_sense_refcount > 0); 4080 mpt->m_extreq_sense_refcount--; 4081 if (mpt->m_extreq_sense_refcount == 0) 4082 cv_broadcast(&mpt->m_extreq_sense_refcount_cv); 4083 mutex_exit(&mpt->m_mutex); 4084 } 4085 } 4086 } 4087 4088 /* 4089 * kmem cache constructor and destructor: 4090 * When constructing, we bzero the cmd and allocate the dma handle 4091 * When destructing, just free the dma handle 4092 */ 4093 static int 4094 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 4095 { 4096 mptsas_cmd_t *cmd = buf; 4097 mptsas_t *mpt = cdrarg; 4098 int (*callback)(caddr_t); 4099 4100 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4101 4102 NDBG4(("mptsas_kmem_cache_constructor")); 4103 4104 /* 4105 * allocate a dma handle 4106 */ 4107 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 4108 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 4109 cmd->cmd_dmahandle = NULL; 4110 return (-1); 4111 } 4112 return (0); 4113 } 4114 4115 static void 4116 mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 4117 { 4118 #ifndef __lock_lint 4119 _NOTE(ARGUNUSED(cdrarg)) 4120 #endif 4121 mptsas_cmd_t *cmd = buf; 4122 4123 NDBG4(("mptsas_kmem_cache_destructor")); 4124 4125 if (cmd->cmd_dmahandle) { 4126 ddi_dma_free_handle(&cmd->cmd_dmahandle); 4127 cmd->cmd_dmahandle = NULL; 4128 } 4129 } 4130 4131 static int 4132 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 4133 { 4134 mptsas_cache_frames_t *p = buf; 4135 mptsas_t *mpt = cdrarg; 4136 ddi_dma_attr_t frame_dma_attr; 4137 size_t mem_size, alloc_len; 4138 ddi_dma_cookie_t cookie; 4139 uint_t ncookie; 4140 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 4141 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4142 4143 frame_dma_attr = mpt->m_msg_dma_attr; 4144 frame_dma_attr.dma_attr_align = 0x10; 4145 frame_dma_attr.dma_attr_sgllen = 1; 4146 4147 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 4148 &p->m_dma_hdl) != DDI_SUCCESS) { 4149 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 4150 " extra SGL."); 4151 return (DDI_FAILURE); 4152 } 4153 4154 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 4155 4156 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 4157 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 4158 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 4159 ddi_dma_free_handle(&p->m_dma_hdl); 4160 p->m_dma_hdl = NULL; 4161 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 4162 " extra SGL."); 4163 return (DDI_FAILURE); 4164 } 4165 4166 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 4167 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 4168 &cookie, &ncookie) != DDI_DMA_MAPPED) { 4169 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4170 ddi_dma_free_handle(&p->m_dma_hdl); 4171 p->m_dma_hdl = NULL; 4172 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 4173 " extra SGL"); 4174 return (DDI_FAILURE); 4175 } 4176 4177 /* 4178 * Store the SGL memory address. This chip uses this 4179 * address to dma to and from the driver. The second 4180 * address is the address mpt uses to fill in the SGL. 4181 */ 4182 p->m_phys_addr = cookie.dmac_laddress; 4183 4184 return (DDI_SUCCESS); 4185 } 4186 4187 static void 4188 mptsas_cache_frames_destructor(void *buf, void *cdrarg) 4189 { 4190 #ifndef __lock_lint 4191 _NOTE(ARGUNUSED(cdrarg)) 4192 #endif 4193 mptsas_cache_frames_t *p = buf; 4194 if (p->m_dma_hdl != NULL) { 4195 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 4196 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4197 ddi_dma_free_handle(&p->m_dma_hdl); 4198 p->m_phys_addr = NULL; 4199 p->m_frames_addr = NULL; 4200 p->m_dma_hdl = NULL; 4201 p->m_acc_hdl = NULL; 4202 } 4203 4204 } 4205 4206 /* 4207 * Figure out if we need to use a different method for the request 4208 * sense buffer and allocate from the map if necessary. 4209 */ 4210 static boolean_t 4211 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf) 4212 { 4213 if (senselength > mpt->m_req_sense_size) { 4214 unsigned long i; 4215 4216 /* Sense length is limited to an 8 bit value in MPI Spec. */ 4217 if (senselength > 255) 4218 senselength = 255; 4219 cmd->cmd_extrqschunks = (senselength + 4220 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size; 4221 i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc) 4222 (mpt->m_erqsense_map, cmd->cmd_extrqschunks); 4223 4224 if (i == 0) 4225 return (B_FALSE); 4226 4227 cmd->cmd_extrqslen = (uint16_t)senselength; 4228 cmd->cmd_extrqsidx = i - 1; 4229 cmd->cmd_arq_buf = mpt->m_extreq_sense + 4230 (cmd->cmd_extrqsidx * mpt->m_req_sense_size); 4231 } else { 4232 cmd->cmd_rqslen = (uchar_t)senselength; 4233 } 4234 4235 return (B_TRUE); 4236 } 4237 4238 /* 4239 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 4240 * for non-standard length cdb, pkt_private, status areas 4241 * if allocation fails, then deallocate all external space and the pkt 4242 */ 4243 /* ARGSUSED */ 4244 static int 4245 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 4246 int cmdlen, int tgtlen, int statuslen, int kf) 4247 { 4248 caddr_t cdbp, scbp, tgt; 4249 4250 NDBG3(("mptsas_pkt_alloc_extern: " 4251 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 4252 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 4253 4254 tgt = cdbp = scbp = NULL; 4255 cmd->cmd_scblen = statuslen; 4256 cmd->cmd_privlen = (uchar_t)tgtlen; 4257 4258 if (cmdlen > sizeof (cmd->cmd_cdb)) { 4259 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 4260 goto fail; 4261 } 4262 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 4263 cmd->cmd_flags |= CFLAG_CDBEXTERN; 4264 } 4265 if (tgtlen > PKT_PRIV_LEN) { 4266 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 4267 goto fail; 4268 } 4269 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 4270 cmd->cmd_pkt->pkt_private = tgt; 4271 } 4272 if (statuslen > EXTCMDS_STATUS_SIZE) { 4273 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 4274 goto fail; 4275 } 4276 cmd->cmd_flags |= CFLAG_SCBEXTERN; 4277 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 4278 4279 /* allocate sense data buf for DMA */ 4280 if (mptsas_cmdarqsize(mpt, cmd, statuslen - 4281 MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata), 4282 kf) == B_FALSE) 4283 goto fail; 4284 } 4285 return (0); 4286 fail: 4287 mptsas_pkt_destroy_extern(mpt, cmd); 4288 return (1); 4289 } 4290 4291 /* 4292 * deallocate external pkt space and deallocate the pkt 4293 */ 4294 static void 4295 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 4296 { 4297 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 4298 4299 if (cmd->cmd_flags & CFLAG_FREE) { 4300 mptsas_log(mpt, CE_PANIC, 4301 "mptsas_pkt_destroy_extern: freeing free packet"); 4302 _NOTE(NOT_REACHED) 4303 /* NOTREACHED */ 4304 } 4305 if (cmd->cmd_extrqslen != 0) { 4306 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 4307 cmd->cmd_extrqsidx + 1); 4308 } 4309 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 4310 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 4311 } 4312 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 4313 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4314 } 4315 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4316 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4317 } 4318 cmd->cmd_flags = CFLAG_FREE; 4319 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4320 } 4321 4322 /* 4323 * tran_sync_pkt(9E) - explicit DMA synchronization 4324 */ 4325 /*ARGSUSED*/ 4326 static void 4327 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4328 { 4329 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4330 4331 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4332 ap->a_target, (void *)pkt)); 4333 4334 if (cmd->cmd_dmahandle) { 4335 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4336 (cmd->cmd_flags & CFLAG_DMASEND) ? 4337 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4338 } 4339 } 4340 4341 /* 4342 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4343 */ 4344 /*ARGSUSED*/ 4345 static void 4346 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4347 { 4348 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4349 mptsas_t *mpt = ADDR2MPT(ap); 4350 4351 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4352 ap->a_target, (void *)pkt)); 4353 4354 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4355 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4356 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4357 } 4358 4359 mptsas_free_extra_sgl_frame(mpt, cmd); 4360 } 4361 4362 static void 4363 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4364 { 4365 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4366 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4367 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4368 DDI_DMA_SYNC_FORCPU); 4369 } 4370 (*pkt->pkt_comp)(pkt); 4371 } 4372 4373 static void 4374 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4375 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags) 4376 { 4377 pMpi2SGESimple64_t sge; 4378 mptti_t *dmap; 4379 uint32_t flags; 4380 4381 dmap = cmd->cmd_sg; 4382 4383 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4384 while (cookiec--) { 4385 ddi_put32(acc_hdl, 4386 &sge->Address.Low, dmap->addr.address64.Low); 4387 ddi_put32(acc_hdl, 4388 &sge->Address.High, dmap->addr.address64.High); 4389 ddi_put32(acc_hdl, &sge->FlagsLength, 4390 dmap->count); 4391 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4392 flags |= ((uint32_t) 4393 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4394 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4395 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4396 MPI2_SGE_FLAGS_SHIFT); 4397 4398 /* 4399 * If this is the last cookie, we set the flags 4400 * to indicate so 4401 */ 4402 if (cookiec == 0) { 4403 flags |= end_flags; 4404 } 4405 if (cmd->cmd_flags & CFLAG_DMASEND) { 4406 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4407 MPI2_SGE_FLAGS_SHIFT); 4408 } else { 4409 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4410 MPI2_SGE_FLAGS_SHIFT); 4411 } 4412 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4413 dmap++; 4414 sge++; 4415 } 4416 } 4417 4418 static void 4419 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4420 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4421 { 4422 pMpi2SGESimple64_t sge; 4423 pMpi2SGEChain64_t sgechain; 4424 uint64_t nframe_phys_addr; 4425 uint_t cookiec; 4426 mptti_t *dmap; 4427 uint32_t flags; 4428 4429 /* 4430 * Save the number of entries in the DMA 4431 * Scatter/Gather list 4432 */ 4433 cookiec = cmd->cmd_cookiec; 4434 4435 /* 4436 * Hereby we start to deal with multiple frames. 4437 * The process is as follows: 4438 * 1. Determine how many frames are needed for SGL element 4439 * storage; Note that all frames are stored in contiguous 4440 * memory space and in 64-bit DMA mode each element is 4441 * 3 double-words (12 bytes) long. 4442 * 2. Fill up the main frame. We need to do this separately 4443 * since it contains the SCSI IO request header and needs 4444 * dedicated processing. Note that the last 4 double-words 4445 * of the SCSI IO header is for SGL element storage 4446 * (MPI2_SGE_IO_UNION). 4447 * 3. Fill the chain element in the main frame, so the DMA 4448 * engine can use the following frames. 4449 * 4. Enter a loop to fill the remaining frames. Note that the 4450 * last frame contains no chain element. The remaining 4451 * frames go into the mpt SGL buffer allocated on the fly, 4452 * not immediately following the main message frame, as in 4453 * Gen1. 4454 * Some restrictions: 4455 * 1. For 64-bit DMA, the simple element and chain element 4456 * are both of 3 double-words (12 bytes) in size, even 4457 * though all frames are stored in the first 4G of mem 4458 * range and the higher 32-bits of the address are always 0. 4459 * 2. On some controllers (like the 1064/1068), a frame can 4460 * hold SGL elements with the last 1 or 2 double-words 4461 * (4 or 8 bytes) un-used. On these controllers, we should 4462 * recognize that there's not enough room for another SGL 4463 * element and move the sge pointer to the next frame. 4464 */ 4465 int i, j, k, l, frames, sgemax; 4466 int temp; 4467 uint8_t chainflags; 4468 uint16_t chainlength; 4469 mptsas_cache_frames_t *p; 4470 4471 /* 4472 * Sgemax is the number of SGE's that will fit 4473 * each extra frame and frames is total 4474 * number of frames we'll need. 1 sge entry per 4475 * frame is reseverd for the chain element thus the -1 below. 4476 */ 4477 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4478 - 1); 4479 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4480 4481 /* 4482 * A little check to see if we need to round up the number 4483 * of frames we need 4484 */ 4485 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4486 sgemax) > 1) { 4487 frames = (temp + 1); 4488 } else { 4489 frames = temp; 4490 } 4491 dmap = cmd->cmd_sg; 4492 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4493 4494 /* 4495 * First fill in the main frame 4496 */ 4497 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4498 mptsas_sge_mainframe(cmd, frame, acc_hdl, j, 4499 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) << 4500 MPI2_SGE_FLAGS_SHIFT)); 4501 dmap += j; 4502 sge += j; 4503 j++; 4504 4505 /* 4506 * Fill in the chain element in the main frame. 4507 * About calculation on ChainOffset: 4508 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4509 * in the end reserved for SGL element storage 4510 * (MPI2_SGE_IO_UNION); we should count it in our 4511 * calculation. See its definition in the header file. 4512 * 2. Constant j is the counter of the current SGL element 4513 * that will be processed, and (j - 1) is the number of 4514 * SGL elements that have been processed (stored in the 4515 * main frame). 4516 * 3. ChainOffset value should be in units of double-words (4 4517 * bytes) so the last value should be divided by 4. 4518 */ 4519 ddi_put8(acc_hdl, &frame->ChainOffset, 4520 (sizeof (MPI2_SCSI_IO_REQUEST) - 4521 sizeof (MPI2_SGE_IO_UNION) + 4522 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4523 sgechain = (pMpi2SGEChain64_t)sge; 4524 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4525 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4526 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4527 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4528 4529 /* 4530 * The size of the next frame is the accurate size of space 4531 * (in bytes) used to store the SGL elements. j is the counter 4532 * of SGL elements. (j - 1) is the number of SGL elements that 4533 * have been processed (stored in frames). 4534 */ 4535 if (frames >= 2) { 4536 ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64)); 4537 chainlength = mpt->m_req_frame_size / 4538 sizeof (MPI2_SGE_SIMPLE64) * 4539 sizeof (MPI2_SGE_SIMPLE64); 4540 } else { 4541 chainlength = ((cookiec - (j - 1)) * 4542 sizeof (MPI2_SGE_SIMPLE64)); 4543 } 4544 4545 p = cmd->cmd_extra_frames; 4546 4547 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4548 ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr); 4549 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32); 4550 4551 /* 4552 * If there are more than 2 frames left we have to 4553 * fill in the next chain offset to the location of 4554 * the chain element in the next frame. 4555 * sgemax is the number of simple elements in an extra 4556 * frame. Note that the value NextChainOffset should be 4557 * in double-words (4 bytes). 4558 */ 4559 if (frames >= 2) { 4560 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4561 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4562 } else { 4563 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4564 } 4565 4566 /* 4567 * Jump to next frame; 4568 * Starting here, chain buffers go into the per command SGL. 4569 * This buffer is allocated when chain buffers are needed. 4570 */ 4571 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4572 i = cookiec; 4573 4574 /* 4575 * Start filling in frames with SGE's. If we 4576 * reach the end of frame and still have SGE's 4577 * to fill we need to add a chain element and 4578 * use another frame. j will be our counter 4579 * for what cookie we are at and i will be 4580 * the total cookiec. k is the current frame 4581 */ 4582 for (k = 1; k <= frames; k++) { 4583 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4584 4585 /* 4586 * If we have reached the end of frame 4587 * and we have more SGE's to fill in 4588 * we have to fill the final entry 4589 * with a chain element and then 4590 * continue to the next frame 4591 */ 4592 if ((l == (sgemax + 1)) && (k != frames)) { 4593 sgechain = (pMpi2SGEChain64_t)sge; 4594 j--; 4595 chainflags = ( 4596 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4597 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4598 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4599 ddi_put8(p->m_acc_hdl, 4600 &sgechain->Flags, chainflags); 4601 /* 4602 * k is the frame counter and (k + 1) 4603 * is the number of the next frame. 4604 * Note that frames are in contiguous 4605 * memory space. 4606 */ 4607 nframe_phys_addr = p->m_phys_addr + 4608 (mpt->m_req_frame_size * k); 4609 ddi_put32(p->m_acc_hdl, 4610 &sgechain->Address.Low, 4611 nframe_phys_addr); 4612 ddi_put32(p->m_acc_hdl, 4613 &sgechain->Address.High, 4614 nframe_phys_addr >> 32); 4615 4616 /* 4617 * If there are more than 2 frames left 4618 * we have to next chain offset to 4619 * the location of the chain element 4620 * in the next frame and fill in the 4621 * length of the next chain 4622 */ 4623 if ((frames - k) >= 2) { 4624 ddi_put8(p->m_acc_hdl, 4625 &sgechain->NextChainOffset, 4626 (sgemax * 4627 sizeof (MPI2_SGE_SIMPLE64)) 4628 >> 2); 4629 ddi_put16(p->m_acc_hdl, 4630 &sgechain->Length, 4631 mpt->m_req_frame_size / 4632 sizeof (MPI2_SGE_SIMPLE64) * 4633 sizeof (MPI2_SGE_SIMPLE64)); 4634 } else { 4635 /* 4636 * This is the last frame. Set 4637 * the NextChainOffset to 0 and 4638 * Length is the total size of 4639 * all remaining simple elements 4640 */ 4641 ddi_put8(p->m_acc_hdl, 4642 &sgechain->NextChainOffset, 4643 0); 4644 ddi_put16(p->m_acc_hdl, 4645 &sgechain->Length, 4646 (cookiec - j) * 4647 sizeof (MPI2_SGE_SIMPLE64)); 4648 } 4649 4650 /* Jump to the next frame */ 4651 sge = (pMpi2SGESimple64_t) 4652 ((char *)p->m_frames_addr + 4653 (int)mpt->m_req_frame_size * k); 4654 4655 continue; 4656 } 4657 4658 ddi_put32(p->m_acc_hdl, 4659 &sge->Address.Low, 4660 dmap->addr.address64.Low); 4661 ddi_put32(p->m_acc_hdl, 4662 &sge->Address.High, 4663 dmap->addr.address64.High); 4664 ddi_put32(p->m_acc_hdl, 4665 &sge->FlagsLength, dmap->count); 4666 flags = ddi_get32(p->m_acc_hdl, 4667 &sge->FlagsLength); 4668 flags |= ((uint32_t)( 4669 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4670 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4671 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4672 MPI2_SGE_FLAGS_SHIFT); 4673 4674 /* 4675 * If we are at the end of the frame and 4676 * there is another frame to fill in 4677 * we set the last simple element as last 4678 * element 4679 */ 4680 if ((l == sgemax) && (k != frames)) { 4681 flags |= ((uint32_t) 4682 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4683 MPI2_SGE_FLAGS_SHIFT); 4684 } 4685 4686 /* 4687 * If this is the final cookie we 4688 * indicate it by setting the flags 4689 */ 4690 if (j == i) { 4691 flags |= ((uint32_t) 4692 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4693 MPI2_SGE_FLAGS_END_OF_BUFFER | 4694 MPI2_SGE_FLAGS_END_OF_LIST) << 4695 MPI2_SGE_FLAGS_SHIFT); 4696 } 4697 if (cmd->cmd_flags & CFLAG_DMASEND) { 4698 flags |= 4699 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4700 MPI2_SGE_FLAGS_SHIFT); 4701 } else { 4702 flags |= 4703 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4704 MPI2_SGE_FLAGS_SHIFT); 4705 } 4706 ddi_put32(p->m_acc_hdl, 4707 &sge->FlagsLength, flags); 4708 dmap++; 4709 sge++; 4710 } 4711 } 4712 4713 /* 4714 * Sync DMA with the chain buffers that were just created 4715 */ 4716 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4717 } 4718 4719 static void 4720 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4721 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag) 4722 { 4723 pMpi2IeeeSgeSimple64_t ieeesge; 4724 mptti_t *dmap; 4725 uint8_t flags; 4726 4727 dmap = cmd->cmd_sg; 4728 4729 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec, 4730 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In")); 4731 4732 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4733 while (cookiec--) { 4734 ddi_put32(acc_hdl, 4735 &ieeesge->Address.Low, dmap->addr.address64.Low); 4736 ddi_put32(acc_hdl, 4737 &ieeesge->Address.High, dmap->addr.address64.High); 4738 ddi_put32(acc_hdl, &ieeesge->Length, 4739 dmap->count); 4740 NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count)); 4741 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 4742 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4743 4744 /* 4745 * If this is the last cookie, we set the flags 4746 * to indicate so 4747 */ 4748 if (cookiec == 0) { 4749 flags |= end_flag; 4750 } 4751 4752 ddi_put8(acc_hdl, &ieeesge->Flags, flags); 4753 dmap++; 4754 ieeesge++; 4755 } 4756 } 4757 4758 static void 4759 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4760 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4761 { 4762 pMpi2IeeeSgeSimple64_t ieeesge; 4763 pMpi25IeeeSgeChain64_t ieeesgechain; 4764 uint64_t nframe_phys_addr; 4765 uint_t cookiec; 4766 mptti_t *dmap; 4767 uint8_t flags; 4768 4769 /* 4770 * Save the number of entries in the DMA 4771 * Scatter/Gather list 4772 */ 4773 cookiec = cmd->cmd_cookiec; 4774 4775 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec)); 4776 4777 /* 4778 * Hereby we start to deal with multiple frames. 4779 * The process is as follows: 4780 * 1. Determine how many frames are needed for SGL element 4781 * storage; Note that all frames are stored in contiguous 4782 * memory space and in 64-bit DMA mode each element is 4783 * 4 double-words (16 bytes) long. 4784 * 2. Fill up the main frame. We need to do this separately 4785 * since it contains the SCSI IO request header and needs 4786 * dedicated processing. Note that the last 4 double-words 4787 * of the SCSI IO header is for SGL element storage 4788 * (MPI2_SGE_IO_UNION). 4789 * 3. Fill the chain element in the main frame, so the DMA 4790 * engine can use the following frames. 4791 * 4. Enter a loop to fill the remaining frames. Note that the 4792 * last frame contains no chain element. The remaining 4793 * frames go into the mpt SGL buffer allocated on the fly, 4794 * not immediately following the main message frame, as in 4795 * Gen1. 4796 * Restrictions: 4797 * For 64-bit DMA, the simple element and chain element 4798 * are both of 4 double-words (16 bytes) in size, even 4799 * though all frames are stored in the first 4G of mem 4800 * range and the higher 32-bits of the address are always 0. 4801 */ 4802 int i, j, k, l, frames, sgemax; 4803 int temp; 4804 uint8_t chainflags; 4805 uint32_t chainlength; 4806 mptsas_cache_frames_t *p; 4807 4808 /* 4809 * Sgemax is the number of SGE's that will fit 4810 * each extra frame and frames is total 4811 * number of frames we'll need. 1 sge entry per 4812 * frame is reseverd for the chain element thus the -1 below. 4813 */ 4814 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4815 - 1); 4816 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4817 4818 /* 4819 * A little check to see if we need to round up the number 4820 * of frames we need 4821 */ 4822 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4823 sgemax) > 1) { 4824 frames = (temp + 1); 4825 } else { 4826 frames = temp; 4827 } 4828 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames)); 4829 dmap = cmd->cmd_sg; 4830 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4831 4832 /* 4833 * First fill in the main frame 4834 */ 4835 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4836 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0); 4837 dmap += j; 4838 ieeesge += j; 4839 j++; 4840 4841 /* 4842 * Fill in the chain element in the main frame. 4843 * About calculation on ChainOffset: 4844 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4845 * in the end reserved for SGL element storage 4846 * (MPI2_SGE_IO_UNION); we should count it in our 4847 * calculation. See its definition in the header file. 4848 * 2. Constant j is the counter of the current SGL element 4849 * that will be processed, and (j - 1) is the number of 4850 * SGL elements that have been processed (stored in the 4851 * main frame). 4852 * 3. ChainOffset value should be in units of quad-words (16 4853 * bytes) so the last value should be divided by 16. 4854 */ 4855 ddi_put8(acc_hdl, &frame->ChainOffset, 4856 (sizeof (MPI2_SCSI_IO_REQUEST) - 4857 sizeof (MPI2_SGE_IO_UNION) + 4858 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4859 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4860 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4861 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4862 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags); 4863 4864 /* 4865 * The size of the next frame is the accurate size of space 4866 * (in bytes) used to store the SGL elements. j is the counter 4867 * of SGL elements. (j - 1) is the number of SGL elements that 4868 * have been processed (stored in frames). 4869 */ 4870 if (frames >= 2) { 4871 ASSERT(mpt->m_req_frame_size >= 4872 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4873 chainlength = mpt->m_req_frame_size / 4874 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 4875 sizeof (MPI2_IEEE_SGE_SIMPLE64); 4876 } else { 4877 chainlength = ((cookiec - (j - 1)) * 4878 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4879 } 4880 4881 p = cmd->cmd_extra_frames; 4882 4883 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength); 4884 ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr); 4885 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32); 4886 4887 /* 4888 * If there are more than 2 frames left we have to 4889 * fill in the next chain offset to the location of 4890 * the chain element in the next frame. 4891 * sgemax is the number of simple elements in an extra 4892 * frame. Note that the value NextChainOffset should be 4893 * in double-words (4 bytes). 4894 */ 4895 if (frames >= 2) { 4896 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 4897 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4898 } else { 4899 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0); 4900 } 4901 4902 /* 4903 * Jump to next frame; 4904 * Starting here, chain buffers go into the per command SGL. 4905 * This buffer is allocated when chain buffers are needed. 4906 */ 4907 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr; 4908 i = cookiec; 4909 4910 /* 4911 * Start filling in frames with SGE's. If we 4912 * reach the end of frame and still have SGE's 4913 * to fill we need to add a chain element and 4914 * use another frame. j will be our counter 4915 * for what cookie we are at and i will be 4916 * the total cookiec. k is the current frame 4917 */ 4918 for (k = 1; k <= frames; k++) { 4919 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4920 4921 /* 4922 * If we have reached the end of frame 4923 * and we have more SGE's to fill in 4924 * we have to fill the final entry 4925 * with a chain element and then 4926 * continue to the next frame 4927 */ 4928 if ((l == (sgemax + 1)) && (k != frames)) { 4929 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4930 j--; 4931 chainflags = 4932 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4933 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 4934 ddi_put8(p->m_acc_hdl, 4935 &ieeesgechain->Flags, chainflags); 4936 /* 4937 * k is the frame counter and (k + 1) 4938 * is the number of the next frame. 4939 * Note that frames are in contiguous 4940 * memory space. 4941 */ 4942 nframe_phys_addr = p->m_phys_addr + 4943 (mpt->m_req_frame_size * k); 4944 ddi_put32(p->m_acc_hdl, 4945 &ieeesgechain->Address.Low, 4946 nframe_phys_addr); 4947 ddi_put32(p->m_acc_hdl, 4948 &ieeesgechain->Address.High, 4949 nframe_phys_addr >> 32); 4950 4951 /* 4952 * If there are more than 2 frames left 4953 * we have to next chain offset to 4954 * the location of the chain element 4955 * in the next frame and fill in the 4956 * length of the next chain 4957 */ 4958 if ((frames - k) >= 2) { 4959 ddi_put8(p->m_acc_hdl, 4960 &ieeesgechain->NextChainOffset, 4961 (sgemax * 4962 sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4963 >> 4); 4964 ASSERT(mpt->m_req_frame_size >= 4965 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4966 ddi_put32(p->m_acc_hdl, 4967 &ieeesgechain->Length, 4968 mpt->m_req_frame_size / 4969 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 4970 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4971 } else { 4972 /* 4973 * This is the last frame. Set 4974 * the NextChainOffset to 0 and 4975 * Length is the total size of 4976 * all remaining simple elements 4977 */ 4978 ddi_put8(p->m_acc_hdl, 4979 &ieeesgechain->NextChainOffset, 4980 0); 4981 ddi_put32(p->m_acc_hdl, 4982 &ieeesgechain->Length, 4983 (cookiec - j) * 4984 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4985 } 4986 4987 /* Jump to the next frame */ 4988 ieeesge = (pMpi2IeeeSgeSimple64_t) 4989 ((char *)p->m_frames_addr + 4990 (int)mpt->m_req_frame_size * k); 4991 4992 continue; 4993 } 4994 4995 ddi_put32(p->m_acc_hdl, 4996 &ieeesge->Address.Low, 4997 dmap->addr.address64.Low); 4998 ddi_put32(p->m_acc_hdl, 4999 &ieeesge->Address.High, 5000 dmap->addr.address64.High); 5001 ddi_put32(p->m_acc_hdl, 5002 &ieeesge->Length, dmap->count); 5003 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 5004 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 5005 5006 /* 5007 * If we are at the end of the frame and 5008 * there is another frame to fill in 5009 * do we need to do anything? 5010 * if ((l == sgemax) && (k != frames)) { 5011 * } 5012 */ 5013 5014 /* 5015 * If this is the final cookie set end of list. 5016 */ 5017 if (j == i) { 5018 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 5019 } 5020 5021 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags); 5022 dmap++; 5023 ieeesge++; 5024 } 5025 } 5026 5027 /* 5028 * Sync DMA with the chain buffers that were just created 5029 */ 5030 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 5031 } 5032 5033 static void 5034 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 5035 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 5036 { 5037 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 5038 5039 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec)); 5040 5041 /* 5042 * Set read/write bit in control. 5043 */ 5044 if (cmd->cmd_flags & CFLAG_DMASEND) { 5045 *control |= MPI2_SCSIIO_CONTROL_WRITE; 5046 } else { 5047 *control |= MPI2_SCSIIO_CONTROL_READ; 5048 } 5049 5050 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 5051 5052 /* 5053 * We have 4 cases here. First where we can fit all the 5054 * SG elements into the main frame, and the case 5055 * where we can't. The SG element is also different when using 5056 * MPI2.5 interface. 5057 * If we have more cookies than we can attach to a frame 5058 * we will need to use a chain element to point 5059 * a location of memory where the rest of the S/G 5060 * elements reside. 5061 */ 5062 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 5063 if (mpt->m_MPI25) { 5064 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, 5065 cmd->cmd_cookiec, 5066 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 5067 } else { 5068 mptsas_sge_mainframe(cmd, frame, acc_hdl, 5069 cmd->cmd_cookiec, 5070 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 5071 | MPI2_SGE_FLAGS_END_OF_BUFFER 5072 | MPI2_SGE_FLAGS_END_OF_LIST) << 5073 MPI2_SGE_FLAGS_SHIFT)); 5074 } 5075 } else { 5076 if (mpt->m_MPI25) { 5077 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl); 5078 } else { 5079 mptsas_sge_chain(mpt, cmd, frame, acc_hdl); 5080 } 5081 } 5082 } 5083 5084 /* 5085 * Interrupt handling 5086 * Utility routine. Poll for status of a command sent to HBA 5087 * without interrupts (a FLAG_NOINTR command). 5088 */ 5089 int 5090 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 5091 { 5092 int rval = TRUE; 5093 5094 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 5095 5096 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 5097 mptsas_restart_hba(mpt); 5098 } 5099 5100 /* 5101 * Wait, using drv_usecwait(), long enough for the command to 5102 * reasonably return from the target if the target isn't 5103 * "dead". A polled command may well be sent from scsi_poll, and 5104 * there are retries built in to scsi_poll if the transport 5105 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 5106 * and retries the transport up to scsi_poll_busycnt times 5107 * (currently 60) if 5108 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 5109 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 5110 * 5111 * limit the waiting to avoid a hang in the event that the 5112 * cmd never gets started but we are still receiving interrupts 5113 */ 5114 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 5115 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 5116 NDBG5(("mptsas_poll: command incomplete")); 5117 rval = FALSE; 5118 break; 5119 } 5120 } 5121 5122 if (rval == FALSE) { 5123 5124 /* 5125 * this isn't supposed to happen, the hba must be wedged 5126 * Mark this cmd as a timeout. 5127 */ 5128 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 5129 (STAT_TIMEOUT|STAT_ABORTED)); 5130 5131 if (poll_cmd->cmd_queued == FALSE) { 5132 5133 NDBG5(("mptsas_poll: not on waitq")); 5134 5135 poll_cmd->cmd_pkt->pkt_state |= 5136 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 5137 } else { 5138 5139 /* find and remove it from the waitq */ 5140 NDBG5(("mptsas_poll: delete from waitq")); 5141 mptsas_waitq_delete(mpt, poll_cmd); 5142 } 5143 5144 } 5145 mptsas_fma_check(mpt, poll_cmd); 5146 NDBG5(("mptsas_poll: done")); 5147 return (rval); 5148 } 5149 5150 /* 5151 * Used for polling cmds and TM function 5152 */ 5153 static int 5154 mptsas_wait_intr(mptsas_t *mpt, int polltime) 5155 { 5156 int cnt; 5157 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5158 uint32_t int_mask; 5159 5160 NDBG5(("mptsas_wait_intr")); 5161 5162 mpt->m_polled_intr = 1; 5163 5164 /* 5165 * Get the current interrupt mask and disable interrupts. When 5166 * re-enabling ints, set mask to saved value. 5167 */ 5168 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 5169 MPTSAS_DISABLE_INTR(mpt); 5170 5171 /* 5172 * Keep polling for at least (polltime * 1000) seconds 5173 */ 5174 for (cnt = 0; cnt < polltime; cnt++) { 5175 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5176 DDI_DMA_SYNC_FORCPU); 5177 5178 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5179 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5180 5181 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5182 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5183 ddi_get32(mpt->m_acc_post_queue_hdl, 5184 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5185 drv_usecwait(1000); 5186 continue; 5187 } 5188 5189 /* 5190 * The reply is valid, process it according to its 5191 * type. 5192 */ 5193 mptsas_process_intr(mpt, reply_desc_union); 5194 5195 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5196 mpt->m_post_index = 0; 5197 } 5198 5199 /* 5200 * Update the global reply index 5201 */ 5202 ddi_put32(mpt->m_datap, 5203 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5204 mpt->m_polled_intr = 0; 5205 5206 /* 5207 * Re-enable interrupts and quit. 5208 */ 5209 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 5210 int_mask); 5211 return (TRUE); 5212 5213 } 5214 5215 /* 5216 * Clear polling flag, re-enable interrupts and quit. 5217 */ 5218 mpt->m_polled_intr = 0; 5219 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 5220 return (FALSE); 5221 } 5222 5223 static void 5224 mptsas_handle_scsi_io_success(mptsas_t *mpt, 5225 pMpi2ReplyDescriptorsUnion_t reply_desc) 5226 { 5227 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 5228 uint16_t SMID; 5229 mptsas_slots_t *slots = mpt->m_active; 5230 mptsas_cmd_t *cmd = NULL; 5231 struct scsi_pkt *pkt; 5232 5233 ASSERT(mutex_owned(&mpt->m_mutex)); 5234 5235 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 5236 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID); 5237 5238 /* 5239 * This is a success reply so just complete the IO. First, do a sanity 5240 * check on the SMID. The final slot is used for TM requests, which 5241 * would not come into this reply handler. 5242 */ 5243 if ((SMID == 0) || (SMID > slots->m_n_normal)) { 5244 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 5245 SMID); 5246 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5247 return; 5248 } 5249 5250 cmd = slots->m_slot[SMID]; 5251 5252 /* 5253 * print warning and return if the slot is empty 5254 */ 5255 if (cmd == NULL) { 5256 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 5257 "in slot %d", SMID); 5258 return; 5259 } 5260 5261 pkt = CMD2PKT(cmd); 5262 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 5263 STATE_GOT_STATUS); 5264 if (cmd->cmd_flags & CFLAG_DMAVALID) { 5265 pkt->pkt_state |= STATE_XFERRED_DATA; 5266 } 5267 pkt->pkt_resid = 0; 5268 5269 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 5270 cmd->cmd_flags |= CFLAG_FINISHED; 5271 cv_broadcast(&mpt->m_passthru_cv); 5272 return; 5273 } else { 5274 mptsas_remove_cmd(mpt, cmd); 5275 } 5276 5277 if (cmd->cmd_flags & CFLAG_RETRY) { 5278 /* 5279 * The target returned QFULL or busy, do not add tihs 5280 * pkt to the doneq since the hba will retry 5281 * this cmd. 5282 * 5283 * The pkt has already been resubmitted in 5284 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5285 * Remove this cmd_flag here. 5286 */ 5287 cmd->cmd_flags &= ~CFLAG_RETRY; 5288 } else { 5289 mptsas_doneq_add(mpt, cmd); 5290 } 5291 } 5292 5293 static void 5294 mptsas_handle_address_reply(mptsas_t *mpt, 5295 pMpi2ReplyDescriptorsUnion_t reply_desc) 5296 { 5297 pMpi2AddressReplyDescriptor_t address_reply; 5298 pMPI2DefaultReply_t reply; 5299 mptsas_fw_diagnostic_buffer_t *pBuffer; 5300 uint32_t reply_addr, reply_frame_dma_baseaddr; 5301 uint16_t SMID, iocstatus; 5302 mptsas_slots_t *slots = mpt->m_active; 5303 mptsas_cmd_t *cmd = NULL; 5304 uint8_t function, buffer_type; 5305 m_replyh_arg_t *args; 5306 int reply_frame_no; 5307 5308 ASSERT(mutex_owned(&mpt->m_mutex)); 5309 5310 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 5311 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl, 5312 &address_reply->ReplyFrameAddress); 5313 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID); 5314 5315 /* 5316 * If reply frame is not in the proper range we should ignore this 5317 * message and exit the interrupt handler. 5318 */ 5319 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu; 5320 if ((reply_addr < reply_frame_dma_baseaddr) || 5321 (reply_addr >= (reply_frame_dma_baseaddr + 5322 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 5323 ((reply_addr - reply_frame_dma_baseaddr) % 5324 mpt->m_reply_frame_size != 0)) { 5325 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 5326 "address 0x%x\n", reply_addr); 5327 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5328 return; 5329 } 5330 5331 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 5332 DDI_DMA_SYNC_FORCPU); 5333 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 5334 reply_frame_dma_baseaddr)); 5335 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 5336 5337 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x", 5338 function, reply_addr)); 5339 5340 /* 5341 * don't get slot information and command for events since these values 5342 * don't exist 5343 */ 5344 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 5345 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 5346 /* 5347 * This could be a TM reply, which use the last allocated SMID, 5348 * so allow for that. 5349 */ 5350 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) { 5351 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 5352 "%d\n", SMID); 5353 ddi_fm_service_impact(mpt->m_dip, 5354 DDI_SERVICE_UNAFFECTED); 5355 return; 5356 } 5357 5358 cmd = slots->m_slot[SMID]; 5359 5360 /* 5361 * print warning and return if the slot is empty 5362 */ 5363 if (cmd == NULL) { 5364 mptsas_log(mpt, CE_WARN, "?NULL command for address " 5365 "reply in slot %d", SMID); 5366 return; 5367 } 5368 if ((cmd->cmd_flags & 5369 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 5370 cmd->cmd_rfm = reply_addr; 5371 cmd->cmd_flags |= CFLAG_FINISHED; 5372 cv_broadcast(&mpt->m_passthru_cv); 5373 cv_broadcast(&mpt->m_config_cv); 5374 cv_broadcast(&mpt->m_fw_diag_cv); 5375 return; 5376 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 5377 mptsas_remove_cmd(mpt, cmd); 5378 } 5379 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 5380 } 5381 /* 5382 * Depending on the function, we need to handle 5383 * the reply frame (and cmd) differently. 5384 */ 5385 switch (function) { 5386 case MPI2_FUNCTION_SCSI_IO_REQUEST: 5387 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 5388 break; 5389 case MPI2_FUNCTION_SCSI_TASK_MGMT: 5390 cmd->cmd_rfm = reply_addr; 5391 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 5392 cmd); 5393 break; 5394 case MPI2_FUNCTION_FW_DOWNLOAD: 5395 cmd->cmd_flags |= CFLAG_FINISHED; 5396 cv_signal(&mpt->m_fw_cv); 5397 break; 5398 case MPI2_FUNCTION_EVENT_NOTIFICATION: 5399 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) / 5400 mpt->m_reply_frame_size; 5401 args = &mpt->m_replyh_args[reply_frame_no]; 5402 args->mpt = (void *)mpt; 5403 args->rfm = reply_addr; 5404 5405 /* 5406 * Record the event if its type is enabled in 5407 * this mpt instance by ioctl. 5408 */ 5409 mptsas_record_event(args); 5410 5411 /* 5412 * Handle time critical events 5413 * NOT_RESPONDING/ADDED only now 5414 */ 5415 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 5416 /* 5417 * Would not return main process, 5418 * just let taskq resolve ack action 5419 * and ack would be sent in taskq thread 5420 */ 5421 NDBG20(("send mptsas_handle_event_sync success")); 5422 } 5423 5424 if (mpt->m_in_reset) { 5425 NDBG20(("dropping event received during reset")); 5426 return; 5427 } 5428 5429 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 5430 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5431 mptsas_log(mpt, CE_WARN, "No memory available" 5432 "for dispatch taskq"); 5433 /* 5434 * Return the reply frame to the free queue. 5435 */ 5436 ddi_put32(mpt->m_acc_free_queue_hdl, 5437 &((uint32_t *)(void *) 5438 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 5439 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5440 DDI_DMA_SYNC_FORDEV); 5441 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5442 mpt->m_free_index = 0; 5443 } 5444 5445 ddi_put32(mpt->m_datap, 5446 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 5447 } 5448 return; 5449 case MPI2_FUNCTION_DIAG_BUFFER_POST: 5450 /* 5451 * If SMID is 0, this implies that the reply is due to a 5452 * release function with a status that the buffer has been 5453 * released. Set the buffer flags accordingly. 5454 */ 5455 if (SMID == 0) { 5456 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 5457 &reply->IOCStatus); 5458 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 5459 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 5460 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 5461 pBuffer = 5462 &mpt->m_fw_diag_buffer_list[buffer_type]; 5463 pBuffer->valid_data = TRUE; 5464 pBuffer->owned_by_firmware = FALSE; 5465 pBuffer->immediate = FALSE; 5466 } 5467 } else { 5468 /* 5469 * Normal handling of diag post reply with SMID. 5470 */ 5471 cmd = slots->m_slot[SMID]; 5472 5473 /* 5474 * print warning and return if the slot is empty 5475 */ 5476 if (cmd == NULL) { 5477 mptsas_log(mpt, CE_WARN, "?NULL command for " 5478 "address reply in slot %d", SMID); 5479 return; 5480 } 5481 cmd->cmd_rfm = reply_addr; 5482 cmd->cmd_flags |= CFLAG_FINISHED; 5483 cv_broadcast(&mpt->m_fw_diag_cv); 5484 } 5485 return; 5486 default: 5487 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 5488 break; 5489 } 5490 5491 /* 5492 * Return the reply frame to the free queue. 5493 */ 5494 ddi_put32(mpt->m_acc_free_queue_hdl, 5495 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 5496 reply_addr); 5497 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5498 DDI_DMA_SYNC_FORDEV); 5499 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5500 mpt->m_free_index = 0; 5501 } 5502 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 5503 mpt->m_free_index); 5504 5505 if (cmd->cmd_flags & CFLAG_FW_CMD) 5506 return; 5507 5508 if (cmd->cmd_flags & CFLAG_RETRY) { 5509 /* 5510 * The target returned QFULL or busy, do not add this 5511 * pkt to the doneq since the hba will retry 5512 * this cmd. 5513 * 5514 * The pkt has already been resubmitted in 5515 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5516 * Remove this cmd_flag here. 5517 */ 5518 cmd->cmd_flags &= ~CFLAG_RETRY; 5519 } else { 5520 mptsas_doneq_add(mpt, cmd); 5521 } 5522 } 5523 5524 #ifdef MPTSAS_DEBUG 5525 static uint8_t mptsas_last_sense[256]; 5526 #endif 5527 5528 static void 5529 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 5530 mptsas_cmd_t *cmd) 5531 { 5532 uint8_t scsi_status, scsi_state; 5533 uint16_t ioc_status, cmd_rqs_len; 5534 uint32_t xferred, sensecount, responsedata, loginfo = 0; 5535 struct scsi_pkt *pkt; 5536 struct scsi_arq_status *arqstat; 5537 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5538 uint8_t *sensedata = NULL; 5539 uint64_t sas_wwn; 5540 uint8_t phy; 5541 char wwn_str[MPTSAS_WWN_STRLEN]; 5542 5543 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 5544 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5545 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 5546 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 5547 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 5548 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 5549 &reply->ResponseInfo); 5550 5551 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 5552 sas_wwn = ptgt->m_addr.mta_wwn; 5553 phy = ptgt->m_phynum; 5554 if (sas_wwn == 0) { 5555 (void) sprintf(wwn_str, "p%x", phy); 5556 } else { 5557 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 5558 } 5559 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 5560 &reply->IOCLogInfo); 5561 mptsas_log(mpt, CE_NOTE, 5562 "?Log info 0x%x received for target %d %s.\n" 5563 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5564 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status, 5565 scsi_state); 5566 } 5567 5568 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5569 scsi_status, ioc_status, scsi_state)); 5570 5571 pkt = CMD2PKT(cmd); 5572 *(pkt->pkt_scbp) = scsi_status; 5573 5574 if (loginfo == 0x31170000) { 5575 /* 5576 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5577 * 0x31170000 comes, that means the device missing delay 5578 * is in progressing, the command need retry later. 5579 */ 5580 *(pkt->pkt_scbp) = STATUS_BUSY; 5581 return; 5582 } 5583 5584 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5585 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5586 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5587 pkt->pkt_reason = CMD_INCOMPLETE; 5588 pkt->pkt_state |= STATE_GOT_BUS; 5589 if (ptgt->m_reset_delay == 0) { 5590 mptsas_set_throttle(mpt, ptgt, 5591 DRAIN_THROTTLE); 5592 } 5593 return; 5594 } 5595 5596 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5597 responsedata &= 0x000000FF; 5598 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5599 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5600 pkt->pkt_reason = CMD_TLR_OFF; 5601 return; 5602 } 5603 } 5604 5605 5606 switch (scsi_status) { 5607 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5608 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5609 arqstat = (void*)(pkt->pkt_scbp); 5610 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5611 (pkt->pkt_scbp)); 5612 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5613 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5614 if (cmd->cmd_flags & CFLAG_XARQ) { 5615 pkt->pkt_state |= STATE_XARQ_DONE; 5616 } 5617 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5618 pkt->pkt_state |= STATE_XFERRED_DATA; 5619 } 5620 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5621 arqstat->sts_rqpkt_state = pkt->pkt_state; 5622 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5623 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5624 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5625 cmd_rqs_len = cmd->cmd_extrqslen ? 5626 cmd->cmd_extrqslen : cmd->cmd_rqslen; 5627 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 5628 DDI_DMA_SYNC_FORKERNEL); 5629 #ifdef MPTSAS_DEBUG 5630 bcopy(cmd->cmd_arq_buf, mptsas_last_sense, 5631 ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ? 5632 sizeof (mptsas_last_sense):cmd_rqs_len)); 5633 #endif 5634 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata, 5635 ((cmd_rqs_len >= sensecount) ? sensecount : 5636 cmd_rqs_len)); 5637 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount); 5638 cmd->cmd_flags |= CFLAG_CMDARQ; 5639 /* 5640 * Set proper status for pkt if autosense was valid 5641 */ 5642 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5643 struct scsi_status zero_status = { 0 }; 5644 arqstat->sts_rqpkt_status = zero_status; 5645 } 5646 5647 /* 5648 * ASC=0x47 is parity error 5649 * ASC=0x48 is initiator detected error received 5650 */ 5651 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5652 ((scsi_sense_asc(sensedata) == 0x47) || 5653 (scsi_sense_asc(sensedata) == 0x48))) { 5654 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5655 } 5656 5657 /* 5658 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5659 * ASC/ASCQ=0x25/0x00 means invalid lun 5660 */ 5661 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5662 (scsi_sense_asc(sensedata) == 0x3F) && 5663 (scsi_sense_ascq(sensedata) == 0x0E)) || 5664 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5665 (scsi_sense_asc(sensedata) == 0x25) && 5666 (scsi_sense_ascq(sensedata) == 0x00))) { 5667 mptsas_topo_change_list_t *topo_node = NULL; 5668 5669 topo_node = kmem_zalloc( 5670 sizeof (mptsas_topo_change_list_t), 5671 KM_NOSLEEP); 5672 if (topo_node == NULL) { 5673 mptsas_log(mpt, CE_NOTE, "No memory" 5674 "resource for handle SAS dynamic" 5675 "reconfigure.\n"); 5676 break; 5677 } 5678 topo_node->mpt = mpt; 5679 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5680 topo_node->un.phymask = ptgt->m_addr.mta_phymask; 5681 topo_node->devhdl = ptgt->m_devhdl; 5682 topo_node->object = (void *)ptgt; 5683 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5684 5685 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5686 mptsas_handle_dr, 5687 (void *)topo_node, 5688 DDI_NOSLEEP)) != DDI_SUCCESS) { 5689 kmem_free(topo_node, 5690 sizeof (mptsas_topo_change_list_t)); 5691 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5692 "for handle SAS dynamic reconfigure" 5693 "failed. \n"); 5694 } 5695 } 5696 break; 5697 case MPI2_SCSI_STATUS_GOOD: 5698 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5699 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5700 pkt->pkt_reason = CMD_DEV_GONE; 5701 pkt->pkt_state |= STATE_GOT_BUS; 5702 if (ptgt->m_reset_delay == 0) { 5703 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5704 } 5705 NDBG31(("lost disk for target%d, command:%x", 5706 Tgt(cmd), pkt->pkt_cdbp[0])); 5707 break; 5708 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5709 NDBG31(("data overrun: xferred=%d", xferred)); 5710 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5711 pkt->pkt_reason = CMD_DATA_OVR; 5712 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5713 | STATE_SENT_CMD | STATE_GOT_STATUS 5714 | STATE_XFERRED_DATA); 5715 pkt->pkt_resid = 0; 5716 break; 5717 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5718 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5719 NDBG31(("data underrun: xferred=%d", xferred)); 5720 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5721 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5722 | STATE_SENT_CMD | STATE_GOT_STATUS); 5723 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5724 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5725 pkt->pkt_state |= STATE_XFERRED_DATA; 5726 } 5727 break; 5728 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5729 if (cmd->cmd_active_expiration <= gethrtime()) { 5730 /* 5731 * When timeout requested, propagate 5732 * proper reason and statistics to 5733 * target drivers. 5734 */ 5735 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT, 5736 STAT_BUS_RESET | STAT_TIMEOUT); 5737 } else { 5738 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 5739 STAT_BUS_RESET); 5740 } 5741 break; 5742 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5743 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5744 mptsas_set_pkt_reason(mpt, 5745 cmd, CMD_RESET, STAT_DEV_RESET); 5746 break; 5747 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5748 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5749 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5750 mptsas_set_pkt_reason(mpt, 5751 cmd, CMD_TERMINATED, STAT_TERMINATED); 5752 break; 5753 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5754 case MPI2_IOCSTATUS_BUSY: 5755 /* 5756 * set throttles to drain 5757 */ 5758 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 5759 ptgt = refhash_next(mpt->m_targets, ptgt)) { 5760 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5761 } 5762 5763 /* 5764 * retry command 5765 */ 5766 cmd->cmd_flags |= CFLAG_RETRY; 5767 cmd->cmd_pkt_flags |= FLAG_HEAD; 5768 5769 (void) mptsas_accept_pkt(mpt, cmd); 5770 break; 5771 default: 5772 mptsas_log(mpt, CE_WARN, 5773 "unknown ioc_status = %x\n", ioc_status); 5774 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5775 "count = %x, scsi_status = %x", scsi_state, 5776 xferred, scsi_status); 5777 break; 5778 } 5779 break; 5780 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5781 mptsas_handle_qfull(mpt, cmd); 5782 break; 5783 case MPI2_SCSI_STATUS_BUSY: 5784 NDBG31(("scsi_status busy received")); 5785 break; 5786 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5787 NDBG31(("scsi_status reservation conflict received")); 5788 break; 5789 default: 5790 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5791 scsi_status, ioc_status); 5792 mptsas_log(mpt, CE_WARN, 5793 "mptsas_process_intr: invalid scsi status\n"); 5794 break; 5795 } 5796 } 5797 5798 static void 5799 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5800 mptsas_cmd_t *cmd) 5801 { 5802 uint8_t task_type; 5803 uint16_t ioc_status; 5804 uint32_t log_info; 5805 uint16_t dev_handle; 5806 struct scsi_pkt *pkt = CMD2PKT(cmd); 5807 5808 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5809 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5810 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5811 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5812 5813 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5814 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5815 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5816 task_type, ioc_status, log_info, dev_handle); 5817 pkt->pkt_reason = CMD_INCOMPLETE; 5818 return; 5819 } 5820 5821 switch (task_type) { 5822 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5823 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5824 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5825 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5826 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5827 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5828 break; 5829 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5830 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5831 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5832 /* 5833 * Check for invalid DevHandle of 0 in case application 5834 * sends bad command. DevHandle of 0 could cause problems. 5835 */ 5836 if (dev_handle == 0) { 5837 mptsas_log(mpt, CE_WARN, "!Can't flush target with" 5838 " DevHandle of 0."); 5839 } else { 5840 mptsas_flush_target(mpt, dev_handle, Lun(cmd), 5841 task_type); 5842 } 5843 break; 5844 default: 5845 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5846 task_type); 5847 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5848 break; 5849 } 5850 } 5851 5852 static void 5853 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5854 { 5855 mptsas_t *mpt = arg->mpt; 5856 uint64_t t = arg->t; 5857 mptsas_cmd_t *cmd; 5858 struct scsi_pkt *pkt; 5859 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5860 5861 mutex_enter(&item->mutex); 5862 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5863 if (!item->doneq) { 5864 cv_wait(&item->cv, &item->mutex); 5865 } 5866 pkt = NULL; 5867 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5868 cmd->cmd_flags |= CFLAG_COMPLETED; 5869 pkt = CMD2PKT(cmd); 5870 } 5871 mutex_exit(&item->mutex); 5872 if (pkt) { 5873 mptsas_pkt_comp(pkt, cmd); 5874 } 5875 mutex_enter(&item->mutex); 5876 } 5877 mutex_exit(&item->mutex); 5878 mutex_enter(&mpt->m_doneq_mutex); 5879 mpt->m_doneq_thread_n--; 5880 cv_broadcast(&mpt->m_doneq_thread_cv); 5881 mutex_exit(&mpt->m_doneq_mutex); 5882 } 5883 5884 5885 /* 5886 * mpt interrupt handler. 5887 */ 5888 static uint_t 5889 mptsas_intr(caddr_t arg1, caddr_t arg2) 5890 { 5891 mptsas_t *mpt = (void *)arg1; 5892 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5893 uchar_t did_reply = FALSE; 5894 5895 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5896 5897 mutex_enter(&mpt->m_mutex); 5898 5899 /* 5900 * If interrupts are shared by two channels then check whether this 5901 * interrupt is genuinely for this channel by making sure first the 5902 * chip is in high power state. 5903 */ 5904 if ((mpt->m_options & MPTSAS_OPT_PM) && 5905 (mpt->m_power_level != PM_LEVEL_D0)) { 5906 mutex_exit(&mpt->m_mutex); 5907 return (DDI_INTR_UNCLAIMED); 5908 } 5909 5910 /* 5911 * If polling, interrupt was triggered by some shared interrupt because 5912 * IOC interrupts are disabled during polling, so polling routine will 5913 * handle any replies. Considering this, if polling is happening, 5914 * return with interrupt unclaimed. 5915 */ 5916 if (mpt->m_polled_intr) { 5917 mutex_exit(&mpt->m_mutex); 5918 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5919 return (DDI_INTR_UNCLAIMED); 5920 } 5921 5922 /* 5923 * Read the istat register. 5924 */ 5925 if ((INTPENDING(mpt)) != 0) { 5926 /* 5927 * read fifo until empty. 5928 */ 5929 #ifndef __lock_lint 5930 _NOTE(CONSTCOND) 5931 #endif 5932 while (TRUE) { 5933 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5934 DDI_DMA_SYNC_FORCPU); 5935 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5936 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5937 5938 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5939 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5940 ddi_get32(mpt->m_acc_post_queue_hdl, 5941 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5942 break; 5943 } 5944 5945 /* 5946 * The reply is valid, process it according to its 5947 * type. Also, set a flag for updating the reply index 5948 * after they've all been processed. 5949 */ 5950 did_reply = TRUE; 5951 5952 mptsas_process_intr(mpt, reply_desc_union); 5953 5954 /* 5955 * Increment post index and roll over if needed. 5956 */ 5957 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5958 mpt->m_post_index = 0; 5959 } 5960 } 5961 5962 /* 5963 * Update the global reply index if at least one reply was 5964 * processed. 5965 */ 5966 if (did_reply) { 5967 ddi_put32(mpt->m_datap, 5968 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5969 } 5970 } else { 5971 mutex_exit(&mpt->m_mutex); 5972 return (DDI_INTR_UNCLAIMED); 5973 } 5974 NDBG1(("mptsas_intr complete")); 5975 5976 /* 5977 * If no helper threads are created, process the doneq in ISR. If 5978 * helpers are created, use the doneq length as a metric to measure the 5979 * load on the interrupt CPU. If it is long enough, which indicates the 5980 * load is heavy, then we deliver the IO completions to the helpers. 5981 * This measurement has some limitations, although it is simple and 5982 * straightforward and works well for most of the cases at present. 5983 */ 5984 if (!mpt->m_doneq_thread_n || 5985 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) { 5986 mptsas_doneq_empty(mpt); 5987 } else { 5988 mptsas_deliver_doneq_thread(mpt); 5989 } 5990 5991 /* 5992 * If there are queued cmd, start them now. 5993 */ 5994 if (mpt->m_waitq != NULL) { 5995 mptsas_restart_waitq(mpt); 5996 } 5997 5998 mutex_exit(&mpt->m_mutex); 5999 return (DDI_INTR_CLAIMED); 6000 } 6001 6002 static void 6003 mptsas_process_intr(mptsas_t *mpt, 6004 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 6005 { 6006 uint8_t reply_type; 6007 6008 ASSERT(mutex_owned(&mpt->m_mutex)); 6009 6010 /* 6011 * The reply is valid, process it according to its 6012 * type. Also, set a flag for updated the reply index 6013 * after they've all been processed. 6014 */ 6015 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 6016 &reply_desc_union->Default.ReplyFlags); 6017 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 6018 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || 6019 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) { 6020 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 6021 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 6022 mptsas_handle_address_reply(mpt, reply_desc_union); 6023 } else { 6024 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 6025 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 6026 } 6027 6028 /* 6029 * Clear the reply descriptor for re-use and increment 6030 * index. 6031 */ 6032 ddi_put64(mpt->m_acc_post_queue_hdl, 6033 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 6034 0xFFFFFFFFFFFFFFFF); 6035 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 6036 DDI_DMA_SYNC_FORDEV); 6037 } 6038 6039 /* 6040 * handle qfull condition 6041 */ 6042 static void 6043 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 6044 { 6045 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 6046 6047 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 6048 (ptgt->m_qfull_retries == 0)) { 6049 /* 6050 * We have exhausted the retries on QFULL, or, 6051 * the target driver has indicated that it 6052 * wants to handle QFULL itself by setting 6053 * qfull-retries capability to 0. In either case 6054 * we want the target driver's QFULL handling 6055 * to kick in. We do this by having pkt_reason 6056 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 6057 */ 6058 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 6059 } else { 6060 if (ptgt->m_reset_delay == 0) { 6061 ptgt->m_t_throttle = 6062 max((ptgt->m_t_ncmds - 2), 0); 6063 } 6064 6065 cmd->cmd_pkt_flags |= FLAG_HEAD; 6066 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 6067 cmd->cmd_flags |= CFLAG_RETRY; 6068 6069 (void) mptsas_accept_pkt(mpt, cmd); 6070 6071 /* 6072 * when target gives queue full status with no commands 6073 * outstanding (m_t_ncmds == 0), throttle is set to 0 6074 * (HOLD_THROTTLE), and the queue full handling start 6075 * (see psarc/1994/313); if there are commands outstanding, 6076 * throttle is set to (m_t_ncmds - 2) 6077 */ 6078 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 6079 /* 6080 * By setting throttle to QFULL_THROTTLE, we 6081 * avoid submitting new commands and in 6082 * mptsas_restart_cmd find out slots which need 6083 * their throttles to be cleared. 6084 */ 6085 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 6086 if (mpt->m_restart_cmd_timeid == 0) { 6087 mpt->m_restart_cmd_timeid = 6088 timeout(mptsas_restart_cmd, mpt, 6089 ptgt->m_qfull_retry_interval); 6090 } 6091 } 6092 } 6093 } 6094 6095 mptsas_phymask_t 6096 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 6097 { 6098 mptsas_phymask_t phy_mask = 0; 6099 uint8_t i = 0; 6100 6101 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 6102 6103 ASSERT(mutex_owned(&mpt->m_mutex)); 6104 6105 /* 6106 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 6107 */ 6108 if (physport == 0xFF) { 6109 return (0); 6110 } 6111 6112 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 6113 if (mpt->m_phy_info[i].attached_devhdl && 6114 (mpt->m_phy_info[i].phy_mask != 0) && 6115 (mpt->m_phy_info[i].port_num == physport)) { 6116 phy_mask = mpt->m_phy_info[i].phy_mask; 6117 break; 6118 } 6119 } 6120 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 6121 mpt->m_instance, physport, phy_mask)); 6122 return (phy_mask); 6123 } 6124 6125 /* 6126 * mpt free device handle after device gone, by use of passthrough 6127 */ 6128 static int 6129 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 6130 { 6131 Mpi2SasIoUnitControlRequest_t req; 6132 Mpi2SasIoUnitControlReply_t rep; 6133 int ret; 6134 6135 ASSERT(mutex_owned(&mpt->m_mutex)); 6136 6137 /* 6138 * Need to compose a SAS IO Unit Control request message 6139 * and call mptsas_do_passthru() function 6140 */ 6141 bzero(&req, sizeof (req)); 6142 bzero(&rep, sizeof (rep)); 6143 6144 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 6145 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 6146 req.DevHandle = LE_16(devhdl); 6147 6148 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 6149 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 6150 if (ret != 0) { 6151 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6152 "Control error %d", ret); 6153 return (DDI_FAILURE); 6154 } 6155 6156 /* do passthrough success, check the ioc status */ 6157 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 6158 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6159 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 6160 return (DDI_FAILURE); 6161 } 6162 6163 return (DDI_SUCCESS); 6164 } 6165 6166 /* 6167 * We have a SATA target that has changed, which means the "bridge-port" 6168 * property must be updated to reflect the SAS WWN of the new attachment point. 6169 * This may change if a SATA device changes which bay, and therefore phy, it is 6170 * plugged into. This SATA device may be a multipath virtual device or may be a 6171 * physical device. We have to handle both cases. 6172 */ 6173 static boolean_t 6174 mptsas_update_sata_bridge(mptsas_t *mpt, dev_info_t *parent, 6175 mptsas_target_t *ptgt) 6176 { 6177 int rval; 6178 uint16_t dev_hdl; 6179 uint16_t pdev_hdl; 6180 uint64_t dev_sas_wwn; 6181 uint8_t physport; 6182 uint8_t phy_id; 6183 uint32_t page_address; 6184 uint16_t bay_num, enclosure, io_flags; 6185 uint32_t dev_info; 6186 char uabuf[SCSI_WWN_BUFLEN]; 6187 dev_info_t *dip; 6188 mdi_pathinfo_t *pip; 6189 6190 mutex_enter(&mpt->m_mutex); 6191 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6192 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)ptgt->m_devhdl; 6193 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 6194 &dev_sas_wwn, &dev_info, &physport, &phy_id, &pdev_hdl, &bay_num, 6195 &enclosure, &io_flags); 6196 mutex_exit(&mpt->m_mutex); 6197 if (rval != DDI_SUCCESS) { 6198 mptsas_log(mpt, CE_WARN, "unable to get SAS page 0 for " 6199 "handle %d", page_address); 6200 return (B_FALSE); 6201 } 6202 6203 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 6204 mptsas_log(mpt, CE_WARN, 6205 "mptsas unable to format SATA bridge WWN"); 6206 return (B_FALSE); 6207 } 6208 6209 if (mpt->m_mpxio_enable == TRUE && (pip = mptsas_find_path_addr(parent, 6210 ptgt->m_addr.mta_wwn, 0)) != NULL) { 6211 if (mdi_prop_update_string(pip, SCSI_ADDR_PROP_BRIDGE_PORT, 6212 uabuf) != DDI_SUCCESS) { 6213 mptsas_log(mpt, CE_WARN, 6214 "mptsas unable to create SCSI bridge port " 6215 "property for SATA device"); 6216 return (B_FALSE); 6217 } 6218 return (B_TRUE); 6219 } 6220 6221 if ((dip = mptsas_find_child_addr(parent, ptgt->m_addr.mta_wwn, 6222 0)) != NULL) { 6223 if (ndi_prop_update_string(DDI_DEV_T_NONE, dip, 6224 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != DDI_PROP_SUCCESS) { 6225 mptsas_log(mpt, CE_WARN, 6226 "mptsas unable to create SCSI bridge port " 6227 "property for SATA device"); 6228 return (B_FALSE); 6229 } 6230 return (B_TRUE); 6231 } 6232 6233 mptsas_log(mpt, CE_WARN, "mptsas failed to find dev_info_t or " 6234 "mdi_pathinfo_t for target with WWN %016" PRIx64, 6235 ptgt->m_addr.mta_wwn); 6236 6237 return (B_FALSE); 6238 } 6239 6240 static void 6241 mptsas_update_phymask(mptsas_t *mpt) 6242 { 6243 mptsas_phymask_t mask = 0, phy_mask; 6244 char *phy_mask_name; 6245 uint8_t current_port; 6246 int i, j; 6247 6248 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 6249 6250 ASSERT(mutex_owned(&mpt->m_mutex)); 6251 6252 (void) mptsas_get_sas_io_unit_page(mpt); 6253 6254 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6255 6256 for (i = 0; i < mpt->m_num_phys; i++) { 6257 phy_mask = 0x00; 6258 6259 if (mpt->m_phy_info[i].attached_devhdl == 0) 6260 continue; 6261 6262 bzero(phy_mask_name, sizeof (phy_mask_name)); 6263 6264 current_port = mpt->m_phy_info[i].port_num; 6265 6266 if ((mask & (1 << i)) != 0) 6267 continue; 6268 6269 for (j = 0; j < mpt->m_num_phys; j++) { 6270 if (mpt->m_phy_info[j].attached_devhdl && 6271 (mpt->m_phy_info[j].port_num == current_port)) { 6272 phy_mask |= (1 << j); 6273 } 6274 } 6275 mask = mask | phy_mask; 6276 6277 for (j = 0; j < mpt->m_num_phys; j++) { 6278 if ((phy_mask >> j) & 0x01) { 6279 mpt->m_phy_info[j].phy_mask = phy_mask; 6280 } 6281 } 6282 6283 (void) sprintf(phy_mask_name, "%x", phy_mask); 6284 6285 mutex_exit(&mpt->m_mutex); 6286 /* 6287 * register a iport, if the port has already been existed 6288 * SCSA will do nothing and just return. 6289 */ 6290 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 6291 mutex_enter(&mpt->m_mutex); 6292 } 6293 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6294 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 6295 } 6296 6297 /* 6298 * mptsas_handle_dr is a task handler for DR, the DR action includes: 6299 * 1. Directly attched Device Added/Removed. 6300 * 2. Expander Device Added/Removed. 6301 * 3. Indirectly Attached Device Added/Expander. 6302 * 4. LUNs of a existing device status change. 6303 * 5. RAID volume created/deleted. 6304 * 6. Member of RAID volume is released because of RAID deletion. 6305 * 7. Physical disks are removed because of RAID creation. 6306 */ 6307 static void 6308 mptsas_handle_dr(void *args) 6309 { 6310 mptsas_topo_change_list_t *topo_node = NULL; 6311 mptsas_topo_change_list_t *save_node = NULL; 6312 mptsas_t *mpt; 6313 dev_info_t *parent = NULL; 6314 mptsas_phymask_t phymask = 0; 6315 char *phy_mask_name; 6316 uint8_t flags = 0, physport = 0xff; 6317 uint8_t port_update = 0; 6318 uint_t event; 6319 6320 topo_node = (mptsas_topo_change_list_t *)args; 6321 6322 mpt = topo_node->mpt; 6323 event = topo_node->event; 6324 flags = topo_node->flags; 6325 6326 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6327 6328 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 6329 6330 switch (event) { 6331 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6332 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6333 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 6334 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6335 /* 6336 * Direct attached or expander attached device added 6337 * into system or a Phys Disk that is being unhidden. 6338 */ 6339 port_update = 1; 6340 } 6341 break; 6342 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6343 /* 6344 * New expander added into system, it must be the head 6345 * of topo_change_list_t 6346 */ 6347 port_update = 1; 6348 break; 6349 default: 6350 port_update = 0; 6351 break; 6352 } 6353 /* 6354 * All cases port_update == 1 may cause initiator port form change 6355 */ 6356 mutex_enter(&mpt->m_mutex); 6357 if (mpt->m_port_chng && port_update) { 6358 /* 6359 * mpt->m_port_chng flag indicates some PHYs of initiator 6360 * port have changed to online. So when expander added or 6361 * directly attached device online event come, we force to 6362 * update port information by issueing SAS IO Unit Page and 6363 * update PHYMASKs. 6364 */ 6365 (void) mptsas_update_phymask(mpt); 6366 mpt->m_port_chng = 0; 6367 6368 } 6369 mutex_exit(&mpt->m_mutex); 6370 while (topo_node) { 6371 phymask = 0; 6372 if (parent == NULL) { 6373 physport = topo_node->un.physport; 6374 event = topo_node->event; 6375 flags = topo_node->flags; 6376 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 6377 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 6378 /* 6379 * For all offline events, phymask is known 6380 */ 6381 phymask = topo_node->un.phymask; 6382 goto find_parent; 6383 } 6384 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6385 goto handle_topo_change; 6386 } 6387 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 6388 phymask = topo_node->un.phymask; 6389 goto find_parent; 6390 } 6391 6392 if ((flags == 6393 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 6394 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 6395 /* 6396 * There is no any field in IR_CONFIG_CHANGE 6397 * event indicate physport/phynum, let's get 6398 * parent after SAS Device Page0 request. 6399 */ 6400 goto handle_topo_change; 6401 } 6402 6403 mutex_enter(&mpt->m_mutex); 6404 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6405 /* 6406 * If the direct attached device added or a 6407 * phys disk is being unhidden, argument 6408 * physport actually is PHY#, so we have to get 6409 * phymask according PHY#. 6410 */ 6411 physport = mpt->m_phy_info[physport].port_num; 6412 } 6413 6414 /* 6415 * Translate physport to phymask so that we can search 6416 * parent dip. 6417 */ 6418 phymask = mptsas_physport_to_phymask(mpt, 6419 physport); 6420 mutex_exit(&mpt->m_mutex); 6421 6422 find_parent: 6423 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 6424 /* 6425 * For RAID topology change node, write the iport name 6426 * as v0. 6427 */ 6428 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6429 (void) sprintf(phy_mask_name, "v0"); 6430 } else { 6431 /* 6432 * phymask can bo 0 if the drive has been 6433 * pulled by the time an add event is 6434 * processed. If phymask is 0, just skip this 6435 * event and continue. 6436 */ 6437 if (phymask == 0) { 6438 mutex_enter(&mpt->m_mutex); 6439 save_node = topo_node; 6440 topo_node = topo_node->next; 6441 ASSERT(save_node); 6442 kmem_free(save_node, 6443 sizeof (mptsas_topo_change_list_t)); 6444 mutex_exit(&mpt->m_mutex); 6445 6446 parent = NULL; 6447 continue; 6448 } 6449 (void) sprintf(phy_mask_name, "%x", phymask); 6450 } 6451 parent = scsi_hba_iport_find(mpt->m_dip, 6452 phy_mask_name); 6453 if (parent == NULL) { 6454 mptsas_log(mpt, CE_WARN, "Failed to find an " 6455 "iport, should not happen!"); 6456 goto out; 6457 } 6458 6459 } 6460 ASSERT(parent); 6461 handle_topo_change: 6462 6463 mutex_enter(&mpt->m_mutex); 6464 /* 6465 * If HBA is being reset, don't perform operations depending 6466 * on the IOC. We must free the topo list, however. 6467 */ 6468 if (!mpt->m_in_reset) { 6469 mptsas_handle_topo_change(topo_node, parent); 6470 } else { 6471 NDBG20(("skipping topo change received during reset")); 6472 } 6473 save_node = topo_node; 6474 topo_node = topo_node->next; 6475 ASSERT(save_node); 6476 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 6477 mutex_exit(&mpt->m_mutex); 6478 6479 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6480 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 6481 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 6482 /* 6483 * If direct attached device associated, make sure 6484 * reset the parent before start the next one. But 6485 * all devices associated with expander shares the 6486 * parent. Also, reset parent if this is for RAID. 6487 */ 6488 parent = NULL; 6489 } 6490 } 6491 out: 6492 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6493 } 6494 6495 static void 6496 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 6497 dev_info_t *parent) 6498 { 6499 mptsas_target_t *ptgt = NULL; 6500 mptsas_smp_t *psmp = NULL; 6501 mptsas_t *mpt = (void *)topo_node->mpt; 6502 uint16_t devhdl; 6503 uint16_t attached_devhdl; 6504 uint64_t sas_wwn = 0; 6505 int rval = 0; 6506 uint32_t page_address; 6507 uint8_t phy, flags; 6508 char *addr = NULL; 6509 dev_info_t *lundip; 6510 int circ = 0, circ1 = 0; 6511 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 6512 6513 NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x," 6514 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl, 6515 topo_node->event, topo_node->flags)); 6516 6517 ASSERT(mutex_owned(&mpt->m_mutex)); 6518 6519 switch (topo_node->event) { 6520 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6521 { 6522 char *phy_mask_name; 6523 mptsas_phymask_t phymask = 0; 6524 6525 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6526 /* 6527 * Get latest RAID info. 6528 */ 6529 (void) mptsas_get_raid_info(mpt); 6530 ptgt = refhash_linear_search(mpt->m_targets, 6531 mptsas_target_eval_devhdl, &topo_node->devhdl); 6532 if (ptgt == NULL) 6533 break; 6534 } else { 6535 ptgt = (void *)topo_node->object; 6536 } 6537 6538 if (ptgt == NULL) { 6539 /* 6540 * If a Phys Disk was deleted, RAID info needs to be 6541 * updated to reflect the new topology. 6542 */ 6543 (void) mptsas_get_raid_info(mpt); 6544 6545 /* 6546 * Get sas device page 0 by DevHandle to make sure if 6547 * SSP/SATA end device exist. 6548 */ 6549 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6550 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 6551 topo_node->devhdl; 6552 6553 rval = mptsas_get_target_device_info(mpt, page_address, 6554 &devhdl, &ptgt); 6555 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) { 6556 mptsas_log(mpt, CE_NOTE, 6557 "mptsas_handle_topo_change: target %d is " 6558 "not a SAS/SATA device. \n", 6559 topo_node->devhdl); 6560 } else if (rval == DEV_INFO_FAIL_ALLOC) { 6561 mptsas_log(mpt, CE_NOTE, 6562 "mptsas_handle_topo_change: could not " 6563 "allocate memory. \n"); 6564 } else if (rval == DEV_INFO_FAIL_GUID) { 6565 mptsas_log(mpt, CE_NOTE, 6566 "mptsas_handle_topo_change: could not " 6567 "get SATA GUID for target %d. \n", 6568 topo_node->devhdl); 6569 } 6570 /* 6571 * If rval is DEV_INFO_PHYS_DISK or indicates failure 6572 * then there is nothing else to do, just leave. 6573 */ 6574 if (rval != DEV_INFO_SUCCESS) { 6575 return; 6576 } 6577 } 6578 6579 ASSERT(ptgt->m_devhdl == topo_node->devhdl); 6580 6581 mutex_exit(&mpt->m_mutex); 6582 flags = topo_node->flags; 6583 6584 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) { 6585 phymask = ptgt->m_addr.mta_phymask; 6586 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6587 (void) sprintf(phy_mask_name, "%x", phymask); 6588 parent = scsi_hba_iport_find(mpt->m_dip, 6589 phy_mask_name); 6590 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6591 if (parent == NULL) { 6592 mptsas_log(mpt, CE_WARN, "Failed to find a " 6593 "iport for PD, should not happen!"); 6594 mutex_enter(&mpt->m_mutex); 6595 break; 6596 } 6597 } 6598 6599 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6600 ndi_devi_enter(parent, &circ1); 6601 (void) mptsas_config_raid(parent, topo_node->devhdl, 6602 &lundip); 6603 ndi_devi_exit(parent, circ1); 6604 } else { 6605 /* 6606 * hold nexus for bus configure 6607 */ 6608 ndi_devi_enter(scsi_vhci_dip, &circ); 6609 ndi_devi_enter(parent, &circ1); 6610 rval = mptsas_config_target(parent, ptgt); 6611 /* 6612 * release nexus for bus configure 6613 */ 6614 ndi_devi_exit(parent, circ1); 6615 ndi_devi_exit(scsi_vhci_dip, circ); 6616 6617 /* 6618 * If this is a SATA device, make sure that the 6619 * bridge-port (the SAS WWN that the SATA device is 6620 * plugged into) is updated. This may change if a SATA 6621 * device changes which bay, and therefore phy, it is 6622 * plugged into. 6623 */ 6624 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) { 6625 if (!mptsas_update_sata_bridge(mpt, parent, 6626 ptgt)) { 6627 mutex_enter(&mpt->m_mutex); 6628 return; 6629 } 6630 } 6631 6632 /* 6633 * Add parent's props for SMHBA support 6634 */ 6635 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6636 bzero(attached_wwnstr, 6637 sizeof (attached_wwnstr)); 6638 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 6639 ptgt->m_addr.mta_wwn); 6640 if (ddi_prop_update_string(DDI_DEV_T_NONE, 6641 parent, 6642 SCSI_ADDR_PROP_ATTACHED_PORT, 6643 attached_wwnstr) 6644 != DDI_PROP_SUCCESS) { 6645 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6646 parent, 6647 SCSI_ADDR_PROP_ATTACHED_PORT); 6648 mptsas_log(mpt, CE_WARN, "Failed to" 6649 "attached-port props"); 6650 mutex_enter(&mpt->m_mutex); 6651 return; 6652 } 6653 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6654 MPTSAS_NUM_PHYS, 1) != 6655 DDI_PROP_SUCCESS) { 6656 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6657 parent, MPTSAS_NUM_PHYS); 6658 mptsas_log(mpt, CE_WARN, "Failed to" 6659 " create num-phys props"); 6660 mutex_enter(&mpt->m_mutex); 6661 return; 6662 } 6663 6664 /* 6665 * Update PHY info for smhba 6666 */ 6667 mutex_enter(&mpt->m_mutex); 6668 if (mptsas_smhba_phy_init(mpt)) { 6669 mptsas_log(mpt, CE_WARN, "mptsas phy" 6670 " update failed"); 6671 return; 6672 } 6673 mutex_exit(&mpt->m_mutex); 6674 6675 /* 6676 * topo_node->un.physport is really the PHY# 6677 * for direct attached devices 6678 */ 6679 mptsas_smhba_set_one_phy_props(mpt, parent, 6680 topo_node->un.physport, &attached_devhdl); 6681 6682 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6683 MPTSAS_VIRTUAL_PORT, 0) != 6684 DDI_PROP_SUCCESS) { 6685 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6686 parent, MPTSAS_VIRTUAL_PORT); 6687 mptsas_log(mpt, CE_WARN, 6688 "mptsas virtual-port" 6689 "port prop update failed"); 6690 mutex_enter(&mpt->m_mutex); 6691 return; 6692 } 6693 } 6694 } 6695 mutex_enter(&mpt->m_mutex); 6696 6697 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, " 6698 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl, 6699 ptgt->m_addr.mta_phymask)); 6700 break; 6701 } 6702 case MPTSAS_DR_EVENT_OFFLINE_TARGET: 6703 { 6704 devhdl = topo_node->devhdl; 6705 ptgt = refhash_linear_search(mpt->m_targets, 6706 mptsas_target_eval_devhdl, &devhdl); 6707 if (ptgt == NULL) 6708 break; 6709 6710 sas_wwn = ptgt->m_addr.mta_wwn; 6711 phy = ptgt->m_phynum; 6712 6713 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 6714 6715 if (sas_wwn) { 6716 (void) sprintf(addr, "w%016"PRIx64, sas_wwn); 6717 } else { 6718 (void) sprintf(addr, "p%x", phy); 6719 } 6720 ASSERT(ptgt->m_devhdl == devhdl); 6721 6722 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) || 6723 (topo_node->flags == 6724 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6725 /* 6726 * Get latest RAID info if RAID volume status changes 6727 * or Phys Disk status changes 6728 */ 6729 (void) mptsas_get_raid_info(mpt); 6730 } 6731 /* 6732 * Abort all outstanding command on the device 6733 */ 6734 rval = mptsas_do_scsi_reset(mpt, devhdl); 6735 if (rval) { 6736 NDBG20(("mptsas%d handle_topo_change to reset target " 6737 "before offline devhdl:%x, phymask:%x, rval:%x", 6738 mpt->m_instance, ptgt->m_devhdl, 6739 ptgt->m_addr.mta_phymask, rval)); 6740 } 6741 6742 mutex_exit(&mpt->m_mutex); 6743 6744 ndi_devi_enter(scsi_vhci_dip, &circ); 6745 ndi_devi_enter(parent, &circ1); 6746 rval = mptsas_offline_target(parent, addr); 6747 ndi_devi_exit(parent, circ1); 6748 ndi_devi_exit(scsi_vhci_dip, circ); 6749 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, " 6750 "phymask:%x, rval:%x", mpt->m_instance, 6751 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval)); 6752 6753 kmem_free(addr, SCSI_MAXNAMELEN); 6754 6755 /* 6756 * Clear parent's props for SMHBA support 6757 */ 6758 flags = topo_node->flags; 6759 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6760 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6761 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6762 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6763 DDI_PROP_SUCCESS) { 6764 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6765 SCSI_ADDR_PROP_ATTACHED_PORT); 6766 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6767 "prop update failed"); 6768 mutex_enter(&mpt->m_mutex); 6769 break; 6770 } 6771 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6772 MPTSAS_NUM_PHYS, 0) != 6773 DDI_PROP_SUCCESS) { 6774 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6775 MPTSAS_NUM_PHYS); 6776 mptsas_log(mpt, CE_WARN, "mptsas num phys " 6777 "prop update failed"); 6778 mutex_enter(&mpt->m_mutex); 6779 break; 6780 } 6781 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6782 MPTSAS_VIRTUAL_PORT, 1) != 6783 DDI_PROP_SUCCESS) { 6784 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6785 MPTSAS_VIRTUAL_PORT); 6786 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6787 "prop update failed"); 6788 mutex_enter(&mpt->m_mutex); 6789 break; 6790 } 6791 } 6792 6793 mutex_enter(&mpt->m_mutex); 6794 ptgt->m_led_status = 0; 6795 (void) mptsas_flush_led_status(mpt, ptgt); 6796 if (rval == DDI_SUCCESS) { 6797 refhash_remove(mpt->m_targets, ptgt); 6798 ptgt = NULL; 6799 } else { 6800 /* 6801 * clean DR_INTRANSITION flag to allow I/O down to 6802 * PHCI driver since failover finished. 6803 * Invalidate the devhdl 6804 */ 6805 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL; 6806 ptgt->m_tgt_unconfigured = 0; 6807 mutex_enter(&mpt->m_tx_waitq_mutex); 6808 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE; 6809 mutex_exit(&mpt->m_tx_waitq_mutex); 6810 } 6811 6812 /* 6813 * Send SAS IO Unit Control to free the dev handle 6814 */ 6815 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6816 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) { 6817 rval = mptsas_free_devhdl(mpt, devhdl); 6818 6819 NDBG20(("mptsas%d handle_topo_change to remove " 6820 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6821 rval)); 6822 } 6823 6824 break; 6825 } 6826 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE: 6827 { 6828 devhdl = topo_node->devhdl; 6829 /* 6830 * If this is the remove handle event, do a reset first. 6831 */ 6832 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6833 rval = mptsas_do_scsi_reset(mpt, devhdl); 6834 if (rval) { 6835 NDBG20(("mpt%d reset target before remove " 6836 "devhdl:%x, rval:%x", mpt->m_instance, 6837 devhdl, rval)); 6838 } 6839 } 6840 6841 /* 6842 * Send SAS IO Unit Control to free the dev handle 6843 */ 6844 rval = mptsas_free_devhdl(mpt, devhdl); 6845 NDBG20(("mptsas%d handle_topo_change to remove " 6846 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6847 rval)); 6848 break; 6849 } 6850 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6851 { 6852 mptsas_smp_t smp; 6853 dev_info_t *smpdip; 6854 6855 devhdl = topo_node->devhdl; 6856 6857 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 6858 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl; 6859 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp); 6860 if (rval != DDI_SUCCESS) { 6861 mptsas_log(mpt, CE_WARN, "failed to online smp, " 6862 "handle %x", devhdl); 6863 return; 6864 } 6865 6866 psmp = mptsas_smp_alloc(mpt, &smp); 6867 if (psmp == NULL) { 6868 return; 6869 } 6870 6871 mutex_exit(&mpt->m_mutex); 6872 ndi_devi_enter(parent, &circ1); 6873 (void) mptsas_online_smp(parent, psmp, &smpdip); 6874 ndi_devi_exit(parent, circ1); 6875 6876 mutex_enter(&mpt->m_mutex); 6877 break; 6878 } 6879 case MPTSAS_DR_EVENT_OFFLINE_SMP: 6880 { 6881 devhdl = topo_node->devhdl; 6882 uint32_t dev_info; 6883 6884 psmp = refhash_linear_search(mpt->m_smp_targets, 6885 mptsas_smp_eval_devhdl, &devhdl); 6886 if (psmp == NULL) 6887 break; 6888 /* 6889 * The mptsas_smp_t data is released only if the dip is offlined 6890 * successfully. 6891 */ 6892 mutex_exit(&mpt->m_mutex); 6893 6894 ndi_devi_enter(parent, &circ1); 6895 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE); 6896 ndi_devi_exit(parent, circ1); 6897 6898 dev_info = psmp->m_deviceinfo; 6899 if ((dev_info & DEVINFO_DIRECT_ATTACHED) == 6900 DEVINFO_DIRECT_ATTACHED) { 6901 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6902 MPTSAS_VIRTUAL_PORT, 1) != 6903 DDI_PROP_SUCCESS) { 6904 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6905 MPTSAS_VIRTUAL_PORT); 6906 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6907 "prop update failed"); 6908 mutex_enter(&mpt->m_mutex); 6909 return; 6910 } 6911 /* 6912 * Check whether the smp connected to the iport, 6913 */ 6914 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6915 MPTSAS_NUM_PHYS, 0) != 6916 DDI_PROP_SUCCESS) { 6917 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6918 MPTSAS_NUM_PHYS); 6919 mptsas_log(mpt, CE_WARN, "mptsas num phys" 6920 "prop update failed"); 6921 mutex_enter(&mpt->m_mutex); 6922 return; 6923 } 6924 /* 6925 * Clear parent's attached-port props 6926 */ 6927 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6928 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6929 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6930 DDI_PROP_SUCCESS) { 6931 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6932 SCSI_ADDR_PROP_ATTACHED_PORT); 6933 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6934 "prop update failed"); 6935 mutex_enter(&mpt->m_mutex); 6936 return; 6937 } 6938 } 6939 6940 mutex_enter(&mpt->m_mutex); 6941 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, " 6942 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval)); 6943 if (rval == DDI_SUCCESS) { 6944 refhash_remove(mpt->m_smp_targets, psmp); 6945 } else { 6946 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL; 6947 } 6948 6949 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6950 6951 break; 6952 } 6953 default: 6954 return; 6955 } 6956 } 6957 6958 /* 6959 * Record the event if its type is enabled in mpt instance by ioctl. 6960 */ 6961 static void 6962 mptsas_record_event(void *args) 6963 { 6964 m_replyh_arg_t *replyh_arg; 6965 pMpi2EventNotificationReply_t eventreply; 6966 uint32_t event, rfm; 6967 mptsas_t *mpt; 6968 int i, j; 6969 uint16_t event_data_len; 6970 boolean_t sendAEN = FALSE; 6971 6972 replyh_arg = (m_replyh_arg_t *)args; 6973 rfm = replyh_arg->rfm; 6974 mpt = replyh_arg->mpt; 6975 6976 eventreply = (pMpi2EventNotificationReply_t) 6977 (mpt->m_reply_frame + (rfm - 6978 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 6979 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6980 6981 6982 /* 6983 * Generate a system event to let anyone who cares know that a 6984 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the 6985 * event mask is set to. 6986 */ 6987 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) { 6988 sendAEN = TRUE; 6989 } 6990 6991 /* 6992 * Record the event only if it is not masked. Determine which dword 6993 * and bit of event mask to test. 6994 */ 6995 i = (uint8_t)(event / 32); 6996 j = (uint8_t)(event % 32); 6997 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) { 6998 i = mpt->m_event_index; 6999 mpt->m_events[i].Type = event; 7000 mpt->m_events[i].Number = ++mpt->m_event_number; 7001 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4); 7002 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl, 7003 &eventreply->EventDataLength); 7004 7005 if (event_data_len > 0) { 7006 /* 7007 * Limit data to size in m_event entry 7008 */ 7009 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) { 7010 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH; 7011 } 7012 for (j = 0; j < event_data_len; j++) { 7013 mpt->m_events[i].Data[j] = 7014 ddi_get32(mpt->m_acc_reply_frame_hdl, 7015 &(eventreply->EventData[j])); 7016 } 7017 7018 /* 7019 * check for index wrap-around 7020 */ 7021 if (++i == MPTSAS_EVENT_QUEUE_SIZE) { 7022 i = 0; 7023 } 7024 mpt->m_event_index = (uint8_t)i; 7025 7026 /* 7027 * Set flag to send the event. 7028 */ 7029 sendAEN = TRUE; 7030 } 7031 } 7032 7033 /* 7034 * Generate a system event if flag is set to let anyone who cares know 7035 * that an event has occurred. 7036 */ 7037 if (sendAEN) { 7038 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS", 7039 "SAS", NULL, NULL, DDI_NOSLEEP); 7040 } 7041 } 7042 7043 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS 7044 /* 7045 * handle sync events from ioc in interrupt 7046 * return value: 7047 * DDI_SUCCESS: The event is handled by this func 7048 * DDI_FAILURE: Event is not handled 7049 */ 7050 static int 7051 mptsas_handle_event_sync(void *args) 7052 { 7053 m_replyh_arg_t *replyh_arg; 7054 pMpi2EventNotificationReply_t eventreply; 7055 uint32_t event, rfm; 7056 mptsas_t *mpt; 7057 uint_t iocstatus; 7058 7059 replyh_arg = (m_replyh_arg_t *)args; 7060 rfm = replyh_arg->rfm; 7061 mpt = replyh_arg->mpt; 7062 7063 ASSERT(mutex_owned(&mpt->m_mutex)); 7064 7065 eventreply = (pMpi2EventNotificationReply_t) 7066 (mpt->m_reply_frame + (rfm - 7067 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7068 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7069 7070 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7071 &eventreply->IOCStatus)) != 0) { 7072 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7073 mptsas_log(mpt, CE_WARN, 7074 "!mptsas_handle_event_sync: event 0x%x, " 7075 "IOCStatus=0x%x, " 7076 "IOCLogInfo=0x%x", event, iocstatus, 7077 ddi_get32(mpt->m_acc_reply_frame_hdl, 7078 &eventreply->IOCLogInfo)); 7079 } else { 7080 mptsas_log(mpt, CE_WARN, 7081 "mptsas_handle_event_sync: event 0x%x, " 7082 "IOCStatus=0x%x, " 7083 "(IOCLogInfo=0x%x)", event, iocstatus, 7084 ddi_get32(mpt->m_acc_reply_frame_hdl, 7085 &eventreply->IOCLogInfo)); 7086 } 7087 } 7088 7089 /* 7090 * figure out what kind of event we got and handle accordingly 7091 */ 7092 switch (event) { 7093 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7094 { 7095 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list; 7096 uint8_t num_entries, expstatus, phy; 7097 uint8_t phystatus, physport, state, i; 7098 uint8_t start_phy_num, link_rate; 7099 uint16_t dev_handle, reason_code; 7100 uint16_t enc_handle, expd_handle; 7101 char string[80], curr[80], prev[80]; 7102 mptsas_topo_change_list_t *topo_head = NULL; 7103 mptsas_topo_change_list_t *topo_tail = NULL; 7104 mptsas_topo_change_list_t *topo_node = NULL; 7105 mptsas_target_t *ptgt; 7106 mptsas_smp_t *psmp; 7107 uint8_t flags = 0, exp_flag; 7108 smhba_info_t *pSmhba = NULL; 7109 7110 NDBG20(("mptsas_handle_event_sync: SAS topology change")); 7111 7112 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t) 7113 eventreply->EventData; 7114 7115 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7116 &sas_topo_change_list->EnclosureHandle); 7117 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7118 &sas_topo_change_list->ExpanderDevHandle); 7119 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7120 &sas_topo_change_list->NumEntries); 7121 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 7122 &sas_topo_change_list->StartPhyNum); 7123 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7124 &sas_topo_change_list->ExpStatus); 7125 physport = ddi_get8(mpt->m_acc_reply_frame_hdl, 7126 &sas_topo_change_list->PhysicalPort); 7127 7128 string[0] = 0; 7129 if (expd_handle) { 7130 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED; 7131 switch (expstatus) { 7132 case MPI2_EVENT_SAS_TOPO_ES_ADDED: 7133 (void) sprintf(string, " added"); 7134 /* 7135 * New expander device added 7136 */ 7137 mpt->m_port_chng = 1; 7138 topo_node = kmem_zalloc( 7139 sizeof (mptsas_topo_change_list_t), 7140 KM_SLEEP); 7141 topo_node->mpt = mpt; 7142 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP; 7143 topo_node->un.physport = physport; 7144 topo_node->devhdl = expd_handle; 7145 topo_node->flags = flags; 7146 topo_node->object = NULL; 7147 if (topo_head == NULL) { 7148 topo_head = topo_tail = topo_node; 7149 } else { 7150 topo_tail->next = topo_node; 7151 topo_tail = topo_node; 7152 } 7153 break; 7154 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: 7155 (void) sprintf(string, " not responding, " 7156 "removed"); 7157 psmp = refhash_linear_search(mpt->m_smp_targets, 7158 mptsas_smp_eval_devhdl, &expd_handle); 7159 if (psmp == NULL) 7160 break; 7161 7162 topo_node = kmem_zalloc( 7163 sizeof (mptsas_topo_change_list_t), 7164 KM_SLEEP); 7165 topo_node->mpt = mpt; 7166 topo_node->un.phymask = 7167 psmp->m_addr.mta_phymask; 7168 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP; 7169 topo_node->devhdl = expd_handle; 7170 topo_node->flags = flags; 7171 topo_node->object = NULL; 7172 if (topo_head == NULL) { 7173 topo_head = topo_tail = topo_node; 7174 } else { 7175 topo_tail->next = topo_node; 7176 topo_tail = topo_node; 7177 } 7178 break; 7179 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: 7180 break; 7181 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: 7182 (void) sprintf(string, " not responding, " 7183 "delaying removal"); 7184 break; 7185 default: 7186 break; 7187 } 7188 } else { 7189 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE; 7190 } 7191 7192 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n", 7193 enc_handle, expd_handle, string)); 7194 for (i = 0; i < num_entries; i++) { 7195 phy = i + start_phy_num; 7196 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7197 &sas_topo_change_list->PHY[i].PhyStatus); 7198 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7199 &sas_topo_change_list->PHY[i].AttachedDevHandle); 7200 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK; 7201 /* 7202 * Filter out processing of Phy Vacant Status unless 7203 * the reason code is "Not Responding". Process all 7204 * other combinations of Phy Status and Reason Codes. 7205 */ 7206 if ((phystatus & 7207 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) && 7208 (reason_code != 7209 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) { 7210 continue; 7211 } 7212 curr[0] = 0; 7213 prev[0] = 0; 7214 string[0] = 0; 7215 switch (reason_code) { 7216 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: 7217 { 7218 NDBG20(("mptsas%d phy %d physical_port %d " 7219 "dev_handle %d added", mpt->m_instance, phy, 7220 physport, dev_handle)); 7221 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7222 &sas_topo_change_list->PHY[i].LinkRate); 7223 state = (link_rate & 7224 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7225 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7226 switch (state) { 7227 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7228 (void) sprintf(curr, "is disabled"); 7229 break; 7230 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7231 (void) sprintf(curr, "is offline, " 7232 "failed speed negotiation"); 7233 break; 7234 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7235 (void) sprintf(curr, "SATA OOB " 7236 "complete"); 7237 break; 7238 case SMP_RESET_IN_PROGRESS: 7239 (void) sprintf(curr, "SMP reset in " 7240 "progress"); 7241 break; 7242 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7243 (void) sprintf(curr, "is online at " 7244 "1.5 Gbps"); 7245 break; 7246 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7247 (void) sprintf(curr, "is online at 3.0 " 7248 "Gbps"); 7249 break; 7250 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7251 (void) sprintf(curr, "is online at 6.0 " 7252 "Gbps"); 7253 break; 7254 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7255 (void) sprintf(curr, 7256 "is online at 12.0 Gbps"); 7257 break; 7258 default: 7259 (void) sprintf(curr, "state is " 7260 "unknown"); 7261 break; 7262 } 7263 /* 7264 * New target device added into the system. 7265 * Set association flag according to if an 7266 * expander is used or not. 7267 */ 7268 exp_flag = 7269 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7270 if (flags == 7271 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7272 flags = exp_flag; 7273 } 7274 topo_node = kmem_zalloc( 7275 sizeof (mptsas_topo_change_list_t), 7276 KM_SLEEP); 7277 topo_node->mpt = mpt; 7278 topo_node->event = 7279 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7280 if (expd_handle == 0) { 7281 /* 7282 * Per MPI 2, if expander dev handle 7283 * is 0, it's a directly attached 7284 * device. So driver use PHY to decide 7285 * which iport is associated 7286 */ 7287 physport = phy; 7288 mpt->m_port_chng = 1; 7289 } 7290 topo_node->un.physport = physport; 7291 topo_node->devhdl = dev_handle; 7292 topo_node->flags = flags; 7293 topo_node->object = NULL; 7294 if (topo_head == NULL) { 7295 topo_head = topo_tail = topo_node; 7296 } else { 7297 topo_tail->next = topo_node; 7298 topo_tail = topo_node; 7299 } 7300 break; 7301 } 7302 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: 7303 { 7304 NDBG20(("mptsas%d phy %d physical_port %d " 7305 "dev_handle %d removed", mpt->m_instance, 7306 phy, physport, dev_handle)); 7307 /* 7308 * Set association flag according to if an 7309 * expander is used or not. 7310 */ 7311 exp_flag = 7312 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7313 if (flags == 7314 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7315 flags = exp_flag; 7316 } 7317 /* 7318 * Target device is removed from the system 7319 * Before the device is really offline from 7320 * from system. 7321 */ 7322 ptgt = refhash_linear_search(mpt->m_targets, 7323 mptsas_target_eval_devhdl, &dev_handle); 7324 /* 7325 * If ptgt is NULL here, it means that the 7326 * DevHandle is not in the hash table. This is 7327 * reasonable sometimes. For example, if a 7328 * disk was pulled, then added, then pulled 7329 * again, the disk will not have been put into 7330 * the hash table because the add event will 7331 * have an invalid phymask. BUT, this does not 7332 * mean that the DevHandle is invalid. The 7333 * controller will still have a valid DevHandle 7334 * that must be removed. To do this, use the 7335 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event. 7336 */ 7337 if (ptgt == NULL) { 7338 topo_node = kmem_zalloc( 7339 sizeof (mptsas_topo_change_list_t), 7340 KM_SLEEP); 7341 topo_node->mpt = mpt; 7342 topo_node->un.phymask = 0; 7343 topo_node->event = 7344 MPTSAS_TOPO_FLAG_REMOVE_HANDLE; 7345 topo_node->devhdl = dev_handle; 7346 topo_node->flags = flags; 7347 topo_node->object = NULL; 7348 if (topo_head == NULL) { 7349 topo_head = topo_tail = 7350 topo_node; 7351 } else { 7352 topo_tail->next = topo_node; 7353 topo_tail = topo_node; 7354 } 7355 break; 7356 } 7357 7358 /* 7359 * Update DR flag immediately avoid I/O failure 7360 * before failover finish. Pay attention to the 7361 * mutex protect, we need grab m_tx_waitq_mutex 7362 * during set m_dr_flag because we won't add 7363 * the following command into waitq, instead, 7364 * we need return TRAN_BUSY in the tran_start 7365 * context. 7366 */ 7367 mutex_enter(&mpt->m_tx_waitq_mutex); 7368 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7369 mutex_exit(&mpt->m_tx_waitq_mutex); 7370 7371 topo_node = kmem_zalloc( 7372 sizeof (mptsas_topo_change_list_t), 7373 KM_SLEEP); 7374 topo_node->mpt = mpt; 7375 topo_node->un.phymask = 7376 ptgt->m_addr.mta_phymask; 7377 topo_node->event = 7378 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7379 topo_node->devhdl = dev_handle; 7380 topo_node->flags = flags; 7381 topo_node->object = NULL; 7382 if (topo_head == NULL) { 7383 topo_head = topo_tail = topo_node; 7384 } else { 7385 topo_tail->next = topo_node; 7386 topo_tail = topo_node; 7387 } 7388 break; 7389 } 7390 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: 7391 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7392 &sas_topo_change_list->PHY[i].LinkRate); 7393 state = (link_rate & 7394 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7395 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7396 pSmhba = &mpt->m_phy_info[i].smhba_info; 7397 pSmhba->negotiated_link_rate = state; 7398 switch (state) { 7399 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7400 (void) sprintf(curr, "is disabled"); 7401 mptsas_smhba_log_sysevent(mpt, 7402 ESC_SAS_PHY_EVENT, 7403 SAS_PHY_REMOVE, 7404 &mpt->m_phy_info[i].smhba_info); 7405 mpt->m_phy_info[i].smhba_info. 7406 negotiated_link_rate 7407 = 0x1; 7408 break; 7409 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7410 (void) sprintf(curr, "is offline, " 7411 "failed speed negotiation"); 7412 mptsas_smhba_log_sysevent(mpt, 7413 ESC_SAS_PHY_EVENT, 7414 SAS_PHY_OFFLINE, 7415 &mpt->m_phy_info[i].smhba_info); 7416 break; 7417 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7418 (void) sprintf(curr, "SATA OOB " 7419 "complete"); 7420 break; 7421 case SMP_RESET_IN_PROGRESS: 7422 (void) sprintf(curr, "SMP reset in " 7423 "progress"); 7424 break; 7425 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7426 (void) sprintf(curr, "is online at " 7427 "1.5 Gbps"); 7428 if ((expd_handle == 0) && 7429 (enc_handle == 1)) { 7430 mpt->m_port_chng = 1; 7431 } 7432 mptsas_smhba_log_sysevent(mpt, 7433 ESC_SAS_PHY_EVENT, 7434 SAS_PHY_ONLINE, 7435 &mpt->m_phy_info[i].smhba_info); 7436 break; 7437 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7438 (void) sprintf(curr, "is online at 3.0 " 7439 "Gbps"); 7440 if ((expd_handle == 0) && 7441 (enc_handle == 1)) { 7442 mpt->m_port_chng = 1; 7443 } 7444 mptsas_smhba_log_sysevent(mpt, 7445 ESC_SAS_PHY_EVENT, 7446 SAS_PHY_ONLINE, 7447 &mpt->m_phy_info[i].smhba_info); 7448 break; 7449 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7450 (void) sprintf(curr, "is online at " 7451 "6.0 Gbps"); 7452 if ((expd_handle == 0) && 7453 (enc_handle == 1)) { 7454 mpt->m_port_chng = 1; 7455 } 7456 mptsas_smhba_log_sysevent(mpt, 7457 ESC_SAS_PHY_EVENT, 7458 SAS_PHY_ONLINE, 7459 &mpt->m_phy_info[i].smhba_info); 7460 break; 7461 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7462 (void) sprintf(curr, "is online at " 7463 "12.0 Gbps"); 7464 if ((expd_handle == 0) && 7465 (enc_handle == 1)) { 7466 mpt->m_port_chng = 1; 7467 } 7468 mptsas_smhba_log_sysevent(mpt, 7469 ESC_SAS_PHY_EVENT, 7470 SAS_PHY_ONLINE, 7471 &mpt->m_phy_info[i].smhba_info); 7472 break; 7473 default: 7474 (void) sprintf(curr, "state is " 7475 "unknown"); 7476 break; 7477 } 7478 7479 state = (link_rate & 7480 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >> 7481 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT; 7482 switch (state) { 7483 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7484 (void) sprintf(prev, ", was disabled"); 7485 break; 7486 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7487 (void) sprintf(prev, ", was offline, " 7488 "failed speed negotiation"); 7489 break; 7490 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7491 (void) sprintf(prev, ", was SATA OOB " 7492 "complete"); 7493 break; 7494 case SMP_RESET_IN_PROGRESS: 7495 (void) sprintf(prev, ", was SMP reset " 7496 "in progress"); 7497 break; 7498 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7499 (void) sprintf(prev, ", was online at " 7500 "1.5 Gbps"); 7501 break; 7502 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7503 (void) sprintf(prev, ", was online at " 7504 "3.0 Gbps"); 7505 break; 7506 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7507 (void) sprintf(prev, ", was online at " 7508 "6.0 Gbps"); 7509 break; 7510 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7511 (void) sprintf(prev, ", was online at " 7512 "12.0 Gbps"); 7513 break; 7514 default: 7515 break; 7516 } 7517 (void) sprintf(&string[strlen(string)], "link " 7518 "changed, "); 7519 break; 7520 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: 7521 continue; 7522 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: 7523 (void) sprintf(&string[strlen(string)], 7524 "target not responding, delaying " 7525 "removal"); 7526 break; 7527 } 7528 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n", 7529 mpt->m_instance, phy, dev_handle, string, curr, 7530 prev)); 7531 } 7532 if (topo_head != NULL) { 7533 /* 7534 * Launch DR taskq to handle topology change 7535 */ 7536 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7537 mptsas_handle_dr, (void *)topo_head, 7538 DDI_NOSLEEP)) != DDI_SUCCESS) { 7539 while (topo_head != NULL) { 7540 topo_node = topo_head; 7541 topo_head = topo_head->next; 7542 kmem_free(topo_node, 7543 sizeof (mptsas_topo_change_list_t)); 7544 } 7545 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7546 "for handle SAS DR event failed. \n"); 7547 } 7548 } 7549 break; 7550 } 7551 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7552 { 7553 Mpi2EventDataIrConfigChangeList_t *irChangeList; 7554 mptsas_topo_change_list_t *topo_head = NULL; 7555 mptsas_topo_change_list_t *topo_tail = NULL; 7556 mptsas_topo_change_list_t *topo_node = NULL; 7557 mptsas_target_t *ptgt; 7558 uint8_t num_entries, i, reason; 7559 uint16_t volhandle, diskhandle; 7560 7561 irChangeList = (pMpi2EventDataIrConfigChangeList_t) 7562 eventreply->EventData; 7563 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7564 &irChangeList->NumElements); 7565 7566 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received", 7567 mpt->m_instance)); 7568 7569 for (i = 0; i < num_entries; i++) { 7570 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7571 &irChangeList->ConfigElement[i].ReasonCode); 7572 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7573 &irChangeList->ConfigElement[i].VolDevHandle); 7574 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7575 &irChangeList->ConfigElement[i].PhysDiskDevHandle); 7576 7577 switch (reason) { 7578 case MPI2_EVENT_IR_CHANGE_RC_ADDED: 7579 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: 7580 { 7581 NDBG20(("mptsas %d volume added\n", 7582 mpt->m_instance)); 7583 7584 topo_node = kmem_zalloc( 7585 sizeof (mptsas_topo_change_list_t), 7586 KM_SLEEP); 7587 7588 topo_node->mpt = mpt; 7589 topo_node->event = 7590 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7591 topo_node->un.physport = 0xff; 7592 topo_node->devhdl = volhandle; 7593 topo_node->flags = 7594 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7595 topo_node->object = NULL; 7596 if (topo_head == NULL) { 7597 topo_head = topo_tail = topo_node; 7598 } else { 7599 topo_tail->next = topo_node; 7600 topo_tail = topo_node; 7601 } 7602 break; 7603 } 7604 case MPI2_EVENT_IR_CHANGE_RC_REMOVED: 7605 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: 7606 { 7607 NDBG20(("mptsas %d volume deleted\n", 7608 mpt->m_instance)); 7609 ptgt = refhash_linear_search(mpt->m_targets, 7610 mptsas_target_eval_devhdl, &volhandle); 7611 if (ptgt == NULL) 7612 break; 7613 7614 /* 7615 * Clear any flags related to volume 7616 */ 7617 (void) mptsas_delete_volume(mpt, volhandle); 7618 7619 /* 7620 * Update DR flag immediately avoid I/O failure 7621 */ 7622 mutex_enter(&mpt->m_tx_waitq_mutex); 7623 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7624 mutex_exit(&mpt->m_tx_waitq_mutex); 7625 7626 topo_node = kmem_zalloc( 7627 sizeof (mptsas_topo_change_list_t), 7628 KM_SLEEP); 7629 topo_node->mpt = mpt; 7630 topo_node->un.phymask = 7631 ptgt->m_addr.mta_phymask; 7632 topo_node->event = 7633 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7634 topo_node->devhdl = volhandle; 7635 topo_node->flags = 7636 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7637 topo_node->object = (void *)ptgt; 7638 if (topo_head == NULL) { 7639 topo_head = topo_tail = topo_node; 7640 } else { 7641 topo_tail->next = topo_node; 7642 topo_tail = topo_node; 7643 } 7644 break; 7645 } 7646 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: 7647 case MPI2_EVENT_IR_CHANGE_RC_HIDE: 7648 { 7649 ptgt = refhash_linear_search(mpt->m_targets, 7650 mptsas_target_eval_devhdl, &diskhandle); 7651 if (ptgt == NULL) 7652 break; 7653 7654 /* 7655 * Update DR flag immediately avoid I/O failure 7656 */ 7657 mutex_enter(&mpt->m_tx_waitq_mutex); 7658 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7659 mutex_exit(&mpt->m_tx_waitq_mutex); 7660 7661 topo_node = kmem_zalloc( 7662 sizeof (mptsas_topo_change_list_t), 7663 KM_SLEEP); 7664 topo_node->mpt = mpt; 7665 topo_node->un.phymask = 7666 ptgt->m_addr.mta_phymask; 7667 topo_node->event = 7668 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7669 topo_node->devhdl = diskhandle; 7670 topo_node->flags = 7671 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7672 topo_node->object = (void *)ptgt; 7673 if (topo_head == NULL) { 7674 topo_head = topo_tail = topo_node; 7675 } else { 7676 topo_tail->next = topo_node; 7677 topo_tail = topo_node; 7678 } 7679 break; 7680 } 7681 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: 7682 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: 7683 { 7684 /* 7685 * The physical drive is released by a IR 7686 * volume. But we cannot get the the physport 7687 * or phynum from the event data, so we only 7688 * can get the physport/phynum after SAS 7689 * Device Page0 request for the devhdl. 7690 */ 7691 topo_node = kmem_zalloc( 7692 sizeof (mptsas_topo_change_list_t), 7693 KM_SLEEP); 7694 topo_node->mpt = mpt; 7695 topo_node->un.phymask = 0; 7696 topo_node->event = 7697 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7698 topo_node->devhdl = diskhandle; 7699 topo_node->flags = 7700 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7701 topo_node->object = NULL; 7702 mpt->m_port_chng = 1; 7703 if (topo_head == NULL) { 7704 topo_head = topo_tail = topo_node; 7705 } else { 7706 topo_tail->next = topo_node; 7707 topo_tail = topo_node; 7708 } 7709 break; 7710 } 7711 default: 7712 break; 7713 } 7714 } 7715 7716 if (topo_head != NULL) { 7717 /* 7718 * Launch DR taskq to handle topology change 7719 */ 7720 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7721 mptsas_handle_dr, (void *)topo_head, 7722 DDI_NOSLEEP)) != DDI_SUCCESS) { 7723 while (topo_head != NULL) { 7724 topo_node = topo_head; 7725 topo_head = topo_head->next; 7726 kmem_free(topo_node, 7727 sizeof (mptsas_topo_change_list_t)); 7728 } 7729 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7730 "for handle SAS DR event failed. \n"); 7731 } 7732 } 7733 break; 7734 } 7735 default: 7736 return (DDI_FAILURE); 7737 } 7738 7739 return (DDI_SUCCESS); 7740 } 7741 7742 /* 7743 * handle events from ioc 7744 */ 7745 static void 7746 mptsas_handle_event(void *args) 7747 { 7748 m_replyh_arg_t *replyh_arg; 7749 pMpi2EventNotificationReply_t eventreply; 7750 uint32_t event, iocloginfo, rfm; 7751 uint32_t status; 7752 uint8_t port; 7753 mptsas_t *mpt; 7754 uint_t iocstatus; 7755 7756 replyh_arg = (m_replyh_arg_t *)args; 7757 rfm = replyh_arg->rfm; 7758 mpt = replyh_arg->mpt; 7759 7760 mutex_enter(&mpt->m_mutex); 7761 /* 7762 * If HBA is being reset, drop incoming event. 7763 */ 7764 if (mpt->m_in_reset) { 7765 NDBG20(("dropping event received prior to reset")); 7766 mutex_exit(&mpt->m_mutex); 7767 return; 7768 } 7769 7770 eventreply = (pMpi2EventNotificationReply_t) 7771 (mpt->m_reply_frame + (rfm - 7772 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7773 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7774 7775 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7776 &eventreply->IOCStatus)) != 0) { 7777 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7778 mptsas_log(mpt, CE_WARN, 7779 "!mptsas_handle_event: IOCStatus=0x%x, " 7780 "IOCLogInfo=0x%x", iocstatus, 7781 ddi_get32(mpt->m_acc_reply_frame_hdl, 7782 &eventreply->IOCLogInfo)); 7783 } else { 7784 mptsas_log(mpt, CE_WARN, 7785 "mptsas_handle_event: IOCStatus=0x%x, " 7786 "IOCLogInfo=0x%x", iocstatus, 7787 ddi_get32(mpt->m_acc_reply_frame_hdl, 7788 &eventreply->IOCLogInfo)); 7789 } 7790 } 7791 7792 /* 7793 * figure out what kind of event we got and handle accordingly 7794 */ 7795 switch (event) { 7796 case MPI2_EVENT_LOG_ENTRY_ADDED: 7797 break; 7798 case MPI2_EVENT_LOG_DATA: 7799 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7800 &eventreply->IOCLogInfo); 7801 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance, 7802 iocloginfo)); 7803 break; 7804 case MPI2_EVENT_STATE_CHANGE: 7805 NDBG20(("mptsas%d state change.", mpt->m_instance)); 7806 break; 7807 case MPI2_EVENT_HARD_RESET_RECEIVED: 7808 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7809 break; 7810 case MPI2_EVENT_SAS_DISCOVERY: 7811 { 7812 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery; 7813 char string[80]; 7814 uint8_t rc; 7815 7816 sasdiscovery = 7817 (pMpi2EventDataSasDiscovery_t)eventreply->EventData; 7818 7819 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7820 &sasdiscovery->ReasonCode); 7821 port = ddi_get8(mpt->m_acc_reply_frame_hdl, 7822 &sasdiscovery->PhysicalPort); 7823 status = ddi_get32(mpt->m_acc_reply_frame_hdl, 7824 &sasdiscovery->DiscoveryStatus); 7825 7826 string[0] = 0; 7827 switch (rc) { 7828 case MPI2_EVENT_SAS_DISC_RC_STARTED: 7829 (void) sprintf(string, "STARTING"); 7830 break; 7831 case MPI2_EVENT_SAS_DISC_RC_COMPLETED: 7832 (void) sprintf(string, "COMPLETED"); 7833 break; 7834 default: 7835 (void) sprintf(string, "UNKNOWN"); 7836 break; 7837 } 7838 7839 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string, 7840 port, status)); 7841 7842 break; 7843 } 7844 case MPI2_EVENT_EVENT_CHANGE: 7845 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7846 break; 7847 case MPI2_EVENT_TASK_SET_FULL: 7848 { 7849 pMpi2EventDataTaskSetFull_t taskfull; 7850 7851 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData; 7852 7853 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n", 7854 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7855 &taskfull->CurrentDepth))); 7856 break; 7857 } 7858 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7859 { 7860 /* 7861 * SAS TOPOLOGY CHANGE LIST Event has already been handled 7862 * in mptsas_handle_event_sync() of interrupt context 7863 */ 7864 break; 7865 } 7866 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 7867 { 7868 pMpi2EventDataSasEnclDevStatusChange_t encstatus; 7869 uint8_t rc; 7870 uint16_t enchdl; 7871 char string[80]; 7872 mptsas_enclosure_t *mep; 7873 7874 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t) 7875 eventreply->EventData; 7876 7877 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7878 &encstatus->ReasonCode); 7879 enchdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7880 &encstatus->EnclosureHandle); 7881 7882 switch (rc) { 7883 case MPI2_EVENT_SAS_ENCL_RC_ADDED: 7884 (void) sprintf(string, "added"); 7885 break; 7886 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: 7887 mep = mptsas_enc_lookup(mpt, enchdl); 7888 if (mep != NULL) { 7889 list_remove(&mpt->m_enclosures, mep); 7890 kmem_free(mep, sizeof (*mep)); 7891 } 7892 (void) sprintf(string, ", not responding"); 7893 break; 7894 default: 7895 break; 7896 } 7897 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure " 7898 "%x%s\n", mpt->m_instance, 7899 ddi_get16(mpt->m_acc_reply_frame_hdl, 7900 &encstatus->EnclosureHandle), string)); 7901 7902 /* 7903 * No matter what has happened, update all of our device state 7904 * for enclosures, by retriggering an evaluation. 7905 */ 7906 mpt->m_done_traverse_enc = 0; 7907 mptsas_update_hashtab(mpt); 7908 break; 7909 } 7910 7911 /* 7912 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by 7913 * mptsas_handle_event_sync,in here just send ack message. 7914 */ 7915 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 7916 { 7917 pMpi2EventDataSasDeviceStatusChange_t statuschange; 7918 uint8_t rc; 7919 uint16_t devhdl; 7920 uint64_t wwn = 0; 7921 uint32_t wwn_lo, wwn_hi; 7922 7923 statuschange = (pMpi2EventDataSasDeviceStatusChange_t) 7924 eventreply->EventData; 7925 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7926 &statuschange->ReasonCode); 7927 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7928 (uint32_t *)(void *)&statuschange->SASAddress); 7929 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl, 7930 (uint32_t *)(void *)&statuschange->SASAddress + 1); 7931 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo; 7932 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7933 &statuschange->DevHandle); 7934 7935 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64, 7936 wwn)); 7937 7938 switch (rc) { 7939 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7940 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x", 7941 ddi_get8(mpt->m_acc_reply_frame_hdl, 7942 &statuschange->ASC), 7943 ddi_get8(mpt->m_acc_reply_frame_hdl, 7944 &statuschange->ASCQ))); 7945 break; 7946 7947 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7948 NDBG20(("Device not supported")); 7949 break; 7950 7951 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7952 NDBG20(("IOC internally generated the Target Reset " 7953 "for devhdl:%x", devhdl)); 7954 break; 7955 7956 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: 7957 NDBG20(("IOC's internally generated Target Reset " 7958 "completed for devhdl:%x", devhdl)); 7959 break; 7960 7961 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7962 NDBG20(("IOC internally generated Abort Task")); 7963 break; 7964 7965 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: 7966 NDBG20(("IOC's internally generated Abort Task " 7967 "completed")); 7968 break; 7969 7970 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7971 NDBG20(("IOC internally generated Abort Task Set")); 7972 break; 7973 7974 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7975 NDBG20(("IOC internally generated Clear Task Set")); 7976 break; 7977 7978 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7979 NDBG20(("IOC internally generated Query Task")); 7980 break; 7981 7982 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: 7983 NDBG20(("Device sent an Asynchronous Notification")); 7984 break; 7985 7986 default: 7987 break; 7988 } 7989 break; 7990 } 7991 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7992 { 7993 /* 7994 * IR TOPOLOGY CHANGE LIST Event has already been handled 7995 * in mpt_handle_event_sync() of interrupt context 7996 */ 7997 break; 7998 } 7999 case MPI2_EVENT_IR_OPERATION_STATUS: 8000 { 8001 Mpi2EventDataIrOperationStatus_t *irOpStatus; 8002 char reason_str[80]; 8003 uint8_t rc, percent; 8004 uint16_t handle; 8005 8006 irOpStatus = (pMpi2EventDataIrOperationStatus_t) 8007 eventreply->EventData; 8008 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 8009 &irOpStatus->RAIDOperation); 8010 percent = ddi_get8(mpt->m_acc_reply_frame_hdl, 8011 &irOpStatus->PercentComplete); 8012 handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8013 &irOpStatus->VolDevHandle); 8014 8015 switch (rc) { 8016 case MPI2_EVENT_IR_RAIDOP_RESYNC: 8017 (void) sprintf(reason_str, "resync"); 8018 break; 8019 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: 8020 (void) sprintf(reason_str, "online capacity " 8021 "expansion"); 8022 break; 8023 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: 8024 (void) sprintf(reason_str, "consistency check"); 8025 break; 8026 default: 8027 (void) sprintf(reason_str, "unknown reason %x", 8028 rc); 8029 } 8030 8031 NDBG20(("mptsas%d raid operational status: (%s)" 8032 "\thandle(0x%04x), percent complete(%d)\n", 8033 mpt->m_instance, reason_str, handle, percent)); 8034 break; 8035 } 8036 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 8037 { 8038 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast; 8039 uint8_t phy_num; 8040 uint8_t primitive; 8041 8042 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t) 8043 eventreply->EventData; 8044 8045 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 8046 &sas_broadcast->PhyNum); 8047 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl, 8048 &sas_broadcast->Primitive); 8049 8050 switch (primitive) { 8051 case MPI2_EVENT_PRIMITIVE_CHANGE: 8052 mptsas_smhba_log_sysevent(mpt, 8053 ESC_SAS_HBA_PORT_BROADCAST, 8054 SAS_PORT_BROADCAST_CHANGE, 8055 &mpt->m_phy_info[phy_num].smhba_info); 8056 break; 8057 case MPI2_EVENT_PRIMITIVE_SES: 8058 mptsas_smhba_log_sysevent(mpt, 8059 ESC_SAS_HBA_PORT_BROADCAST, 8060 SAS_PORT_BROADCAST_SES, 8061 &mpt->m_phy_info[phy_num].smhba_info); 8062 break; 8063 case MPI2_EVENT_PRIMITIVE_EXPANDER: 8064 mptsas_smhba_log_sysevent(mpt, 8065 ESC_SAS_HBA_PORT_BROADCAST, 8066 SAS_PORT_BROADCAST_D01_4, 8067 &mpt->m_phy_info[phy_num].smhba_info); 8068 break; 8069 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT: 8070 mptsas_smhba_log_sysevent(mpt, 8071 ESC_SAS_HBA_PORT_BROADCAST, 8072 SAS_PORT_BROADCAST_D04_7, 8073 &mpt->m_phy_info[phy_num].smhba_info); 8074 break; 8075 case MPI2_EVENT_PRIMITIVE_RESERVED3: 8076 mptsas_smhba_log_sysevent(mpt, 8077 ESC_SAS_HBA_PORT_BROADCAST, 8078 SAS_PORT_BROADCAST_D16_7, 8079 &mpt->m_phy_info[phy_num].smhba_info); 8080 break; 8081 case MPI2_EVENT_PRIMITIVE_RESERVED4: 8082 mptsas_smhba_log_sysevent(mpt, 8083 ESC_SAS_HBA_PORT_BROADCAST, 8084 SAS_PORT_BROADCAST_D29_7, 8085 &mpt->m_phy_info[phy_num].smhba_info); 8086 break; 8087 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED: 8088 mptsas_smhba_log_sysevent(mpt, 8089 ESC_SAS_HBA_PORT_BROADCAST, 8090 SAS_PORT_BROADCAST_D24_0, 8091 &mpt->m_phy_info[phy_num].smhba_info); 8092 break; 8093 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED: 8094 mptsas_smhba_log_sysevent(mpt, 8095 ESC_SAS_HBA_PORT_BROADCAST, 8096 SAS_PORT_BROADCAST_D27_4, 8097 &mpt->m_phy_info[phy_num].smhba_info); 8098 break; 8099 default: 8100 NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE" 8101 " %x received", 8102 mpt->m_instance, primitive)); 8103 break; 8104 } 8105 NDBG16(("mptsas%d sas broadcast primitive: " 8106 "\tprimitive(0x%04x), phy(%d) complete\n", 8107 mpt->m_instance, primitive, phy_num)); 8108 break; 8109 } 8110 case MPI2_EVENT_IR_VOLUME: 8111 { 8112 Mpi2EventDataIrVolume_t *irVolume; 8113 uint16_t devhandle; 8114 uint32_t state; 8115 int config, vol; 8116 uint8_t found = FALSE; 8117 8118 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData; 8119 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8120 &irVolume->NewValue); 8121 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8122 &irVolume->VolDevHandle); 8123 8124 NDBG20(("EVENT_IR_VOLUME event is received")); 8125 8126 /* 8127 * Get latest RAID info and then find the DevHandle for this 8128 * event in the configuration. If the DevHandle is not found 8129 * just exit the event. 8130 */ 8131 (void) mptsas_get_raid_info(mpt); 8132 for (config = 0; (config < mpt->m_num_raid_configs) && 8133 (!found); config++) { 8134 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 8135 if (mpt->m_raidconfig[config].m_raidvol[vol]. 8136 m_raidhandle == devhandle) { 8137 found = TRUE; 8138 break; 8139 } 8140 } 8141 } 8142 if (!found) { 8143 break; 8144 } 8145 8146 switch (irVolume->ReasonCode) { 8147 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED: 8148 { 8149 uint32_t i; 8150 mpt->m_raidconfig[config].m_raidvol[vol].m_settings = 8151 state; 8152 8153 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING; 8154 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed" 8155 ", auto-config of hot-swap drives is %s" 8156 ", write caching is %s" 8157 ", hot-spare pool mask is %02x\n", 8158 vol, state & 8159 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE 8160 ? "disabled" : "enabled", 8161 i == MPI2_RAIDVOL0_SETTING_UNCHANGED 8162 ? "controlled by member disks" : 8163 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING 8164 ? "disabled" : 8165 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING 8166 ? "enabled" : 8167 "incorrectly set", 8168 (state >> 16) & 0xff); 8169 break; 8170 } 8171 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED: 8172 { 8173 mpt->m_raidconfig[config].m_raidvol[vol].m_state = 8174 (uint8_t)state; 8175 8176 mptsas_log(mpt, CE_NOTE, 8177 "Volume %d is now %s\n", vol, 8178 state == MPI2_RAID_VOL_STATE_OPTIMAL 8179 ? "optimal" : 8180 state == MPI2_RAID_VOL_STATE_DEGRADED 8181 ? "degraded" : 8182 state == MPI2_RAID_VOL_STATE_ONLINE 8183 ? "online" : 8184 state == MPI2_RAID_VOL_STATE_INITIALIZING 8185 ? "initializing" : 8186 state == MPI2_RAID_VOL_STATE_FAILED 8187 ? "failed" : 8188 state == MPI2_RAID_VOL_STATE_MISSING 8189 ? "missing" : 8190 "state unknown"); 8191 break; 8192 } 8193 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED: 8194 { 8195 mpt->m_raidconfig[config].m_raidvol[vol]. 8196 m_statusflags = state; 8197 8198 mptsas_log(mpt, CE_NOTE, 8199 " Volume %d is now %s%s%s%s%s%s%s%s%s\n", 8200 vol, 8201 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED 8202 ? ", enabled" : ", disabled", 8203 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED 8204 ? ", quiesced" : "", 8205 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 8206 ? ", inactive" : ", active", 8207 state & 8208 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL 8209 ? ", bad block table is full" : "", 8210 state & 8211 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 8212 ? ", resync in progress" : "", 8213 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT 8214 ? ", background initialization in progress" : "", 8215 state & 8216 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION 8217 ? ", capacity expansion in progress" : "", 8218 state & 8219 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK 8220 ? ", consistency check in progress" : "", 8221 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB 8222 ? ", data scrub in progress" : ""); 8223 break; 8224 } 8225 default: 8226 break; 8227 } 8228 break; 8229 } 8230 case MPI2_EVENT_IR_PHYSICAL_DISK: 8231 { 8232 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk; 8233 uint16_t devhandle, enchandle, slot; 8234 uint32_t status, state; 8235 uint8_t physdisknum, reason; 8236 8237 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *) 8238 eventreply->EventData; 8239 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl, 8240 &irPhysDisk->PhysDiskNum); 8241 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8242 &irPhysDisk->PhysDiskDevHandle); 8243 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8244 &irPhysDisk->EnclosureHandle); 8245 slot = ddi_get16(mpt->m_acc_reply_frame_hdl, 8246 &irPhysDisk->Slot); 8247 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8248 &irPhysDisk->NewValue); 8249 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 8250 &irPhysDisk->ReasonCode); 8251 8252 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received")); 8253 8254 switch (reason) { 8255 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED: 8256 mptsas_log(mpt, CE_NOTE, 8257 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8258 "for enclosure with handle 0x%x is now in hot " 8259 "spare pool %d", 8260 physdisknum, devhandle, slot, enchandle, 8261 (state >> 16) & 0xff); 8262 break; 8263 8264 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED: 8265 status = state; 8266 mptsas_log(mpt, CE_NOTE, 8267 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8268 "for enclosure with handle 0x%x is now " 8269 "%s%s%s%s%s\n", physdisknum, devhandle, slot, 8270 enchandle, 8271 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME 8272 ? ", inactive" : ", active", 8273 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 8274 ? ", out of sync" : "", 8275 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED 8276 ? ", quiesced" : "", 8277 status & 8278 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED 8279 ? ", write cache enabled" : "", 8280 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET 8281 ? ", capacity expansion target" : ""); 8282 break; 8283 8284 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED: 8285 mptsas_log(mpt, CE_NOTE, 8286 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8287 "for enclosure with handle 0x%x is now %s\n", 8288 physdisknum, devhandle, slot, enchandle, 8289 state == MPI2_RAID_PD_STATE_OPTIMAL 8290 ? "optimal" : 8291 state == MPI2_RAID_PD_STATE_REBUILDING 8292 ? "rebuilding" : 8293 state == MPI2_RAID_PD_STATE_DEGRADED 8294 ? "degraded" : 8295 state == MPI2_RAID_PD_STATE_HOT_SPARE 8296 ? "a hot spare" : 8297 state == MPI2_RAID_PD_STATE_ONLINE 8298 ? "online" : 8299 state == MPI2_RAID_PD_STATE_OFFLINE 8300 ? "offline" : 8301 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE 8302 ? "not compatible" : 8303 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED 8304 ? "not configured" : 8305 "state unknown"); 8306 break; 8307 } 8308 break; 8309 } 8310 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 8311 { 8312 pMpi26EventDataActiveCableExcept_t actcable; 8313 uint32_t power; 8314 uint8_t reason, id; 8315 8316 actcable = (pMpi26EventDataActiveCableExcept_t) 8317 eventreply->EventData; 8318 power = ddi_get32(mpt->m_acc_reply_frame_hdl, 8319 &actcable->ActiveCablePowerRequirement); 8320 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 8321 &actcable->ReasonCode); 8322 id = ddi_get8(mpt->m_acc_reply_frame_hdl, 8323 &actcable->ReceptacleID); 8324 8325 /* 8326 * It'd be nice if this weren't just logging to the system but 8327 * were telling FMA about the active cable problem and FMA was 8328 * aware of the cable topology and state. 8329 */ 8330 switch (reason) { 8331 case MPI26_EVENT_ACTIVE_CABLE_PRESENT: 8332 /* Don't log anything if it's fine */ 8333 break; 8334 case MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER: 8335 mptsas_log(mpt, CE_WARN, "An active cable (id %u) does " 8336 "not have sufficient power to be enabled. " 8337 "Devices connected to this cable will not be " 8338 "visible to the system.", id); 8339 if (power == UINT32_MAX) { 8340 mptsas_log(mpt, CE_CONT, "The cable's power " 8341 "requirements are unknown.\n"); 8342 } else { 8343 mptsas_log(mpt, CE_CONT, "The cable requires " 8344 "%u mW of power to function.\n", power); 8345 } 8346 break; 8347 case MPI26_EVENT_ACTIVE_CABLE_DEGRADED: 8348 mptsas_log(mpt, CE_WARN, "An active cable (id %u) is " 8349 "degraded and not running at its full speed. " 8350 "Some devices might not appear.", id); 8351 break; 8352 default: 8353 break; 8354 } 8355 break; 8356 } 8357 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: 8358 case MPI2_EVENT_PCIE_ENUMERATION: 8359 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 8360 case MPI2_EVENT_PCIE_LINK_COUNTER: 8361 mptsas_log(mpt, CE_NOTE, "Unhandled mpt_sas PCIe device " 8362 "event received (0x%x)", event); 8363 break; 8364 default: 8365 NDBG20(("mptsas%d: unknown event %x received", 8366 mpt->m_instance, event)); 8367 break; 8368 } 8369 8370 /* 8371 * Return the reply frame to the free queue. 8372 */ 8373 ddi_put32(mpt->m_acc_free_queue_hdl, 8374 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm); 8375 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 8376 DDI_DMA_SYNC_FORDEV); 8377 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 8378 mpt->m_free_index = 0; 8379 } 8380 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 8381 mpt->m_free_index); 8382 mutex_exit(&mpt->m_mutex); 8383 } 8384 8385 /* 8386 * invoked from timeout() to restart qfull cmds with throttle == 0 8387 */ 8388 static void 8389 mptsas_restart_cmd(void *arg) 8390 { 8391 mptsas_t *mpt = arg; 8392 mptsas_target_t *ptgt = NULL; 8393 8394 mutex_enter(&mpt->m_mutex); 8395 8396 mpt->m_restart_cmd_timeid = 0; 8397 8398 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 8399 ptgt = refhash_next(mpt->m_targets, ptgt)) { 8400 if (ptgt->m_reset_delay == 0) { 8401 if (ptgt->m_t_throttle == QFULL_THROTTLE) { 8402 mptsas_set_throttle(mpt, ptgt, 8403 MAX_THROTTLE); 8404 } 8405 } 8406 } 8407 mptsas_restart_hba(mpt); 8408 mutex_exit(&mpt->m_mutex); 8409 } 8410 8411 void 8412 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8413 { 8414 int slot; 8415 mptsas_slots_t *slots = mpt->m_active; 8416 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8417 8418 ASSERT(cmd != NULL); 8419 ASSERT(cmd->cmd_queued == FALSE); 8420 8421 /* 8422 * Task Management cmds are removed in their own routines. Also, 8423 * we don't want to modify timeout based on TM cmds. 8424 */ 8425 if (cmd->cmd_flags & CFLAG_TM_CMD) { 8426 return; 8427 } 8428 8429 slot = cmd->cmd_slot; 8430 8431 /* 8432 * remove the cmd. 8433 */ 8434 if (cmd == slots->m_slot[slot]) { 8435 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags " 8436 "0x%x", (void *)cmd, cmd->cmd_flags)); 8437 slots->m_slot[slot] = NULL; 8438 mpt->m_ncmds--; 8439 8440 /* 8441 * only decrement per target ncmds if command 8442 * has a target associated with it. 8443 */ 8444 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 8445 ptgt->m_t_ncmds--; 8446 /* 8447 * reset throttle if we just ran an untagged command 8448 * to a tagged target 8449 */ 8450 if ((ptgt->m_t_ncmds == 0) && 8451 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) { 8452 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8453 } 8454 8455 /* 8456 * Remove this command from the active queue. 8457 */ 8458 if (cmd->cmd_active_expiration != 0) { 8459 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd, 8460 cmd_active_link); 8461 cmd->cmd_active_expiration = 0; 8462 } 8463 } 8464 } 8465 8466 /* 8467 * This is all we need to do for ioc commands. 8468 */ 8469 if (cmd->cmd_flags & CFLAG_CMDIOC) { 8470 mptsas_return_to_pool(mpt, cmd); 8471 return; 8472 } 8473 8474 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]); 8475 } 8476 8477 /* 8478 * accept all cmds on the tx_waitq if any and then 8479 * start a fresh request from the top of the device queue. 8480 * 8481 * since there are always cmds queued on the tx_waitq, and rare cmds on 8482 * the instance waitq, so this function should not be invoked in the ISR, 8483 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the 8484 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU. 8485 */ 8486 static void 8487 mptsas_restart_hba(mptsas_t *mpt) 8488 { 8489 ASSERT(mutex_owned(&mpt->m_mutex)); 8490 8491 mutex_enter(&mpt->m_tx_waitq_mutex); 8492 if (mpt->m_tx_waitq) { 8493 mptsas_accept_tx_waitq(mpt); 8494 } 8495 mutex_exit(&mpt->m_tx_waitq_mutex); 8496 mptsas_restart_waitq(mpt); 8497 } 8498 8499 /* 8500 * start a fresh request from the top of the device queue 8501 */ 8502 static void 8503 mptsas_restart_waitq(mptsas_t *mpt) 8504 { 8505 mptsas_cmd_t *cmd, *next_cmd; 8506 mptsas_target_t *ptgt = NULL; 8507 8508 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt)); 8509 8510 ASSERT(mutex_owned(&mpt->m_mutex)); 8511 8512 /* 8513 * If there is a reset delay, don't start any cmds. Otherwise, start 8514 * as many cmds as possible. 8515 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 8516 * commands is m_max_requests - 2. 8517 */ 8518 cmd = mpt->m_waitq; 8519 8520 while (cmd != NULL) { 8521 next_cmd = cmd->cmd_linkp; 8522 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 8523 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8524 /* 8525 * passthru command get slot need 8526 * set CFLAG_PREPARED. 8527 */ 8528 cmd->cmd_flags |= CFLAG_PREPARED; 8529 mptsas_waitq_delete(mpt, cmd); 8530 mptsas_start_passthru(mpt, cmd); 8531 } 8532 cmd = next_cmd; 8533 continue; 8534 } 8535 if (cmd->cmd_flags & CFLAG_CONFIG) { 8536 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8537 /* 8538 * Send the config page request and delete it 8539 * from the waitq. 8540 */ 8541 cmd->cmd_flags |= CFLAG_PREPARED; 8542 mptsas_waitq_delete(mpt, cmd); 8543 mptsas_start_config_page_access(mpt, cmd); 8544 } 8545 cmd = next_cmd; 8546 continue; 8547 } 8548 if (cmd->cmd_flags & CFLAG_FW_DIAG) { 8549 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8550 /* 8551 * Send the FW Diag request and delete if from 8552 * the waitq. 8553 */ 8554 cmd->cmd_flags |= CFLAG_PREPARED; 8555 mptsas_waitq_delete(mpt, cmd); 8556 mptsas_start_diag(mpt, cmd); 8557 } 8558 cmd = next_cmd; 8559 continue; 8560 } 8561 8562 ptgt = cmd->cmd_tgt_addr; 8563 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) && 8564 (ptgt->m_t_ncmds == 0)) { 8565 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8566 } 8567 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 8568 (ptgt && (ptgt->m_reset_delay == 0)) && 8569 (ptgt && (ptgt->m_t_ncmds < 8570 ptgt->m_t_throttle))) { 8571 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8572 mptsas_waitq_delete(mpt, cmd); 8573 (void) mptsas_start_cmd(mpt, cmd); 8574 } 8575 } 8576 cmd = next_cmd; 8577 } 8578 } 8579 /* 8580 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait). 8581 * Accept all those queued cmds before new cmd is accept so that the 8582 * cmds are sent in order. 8583 */ 8584 static void 8585 mptsas_accept_tx_waitq(mptsas_t *mpt) 8586 { 8587 mptsas_cmd_t *cmd; 8588 8589 ASSERT(mutex_owned(&mpt->m_mutex)); 8590 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex)); 8591 8592 /* 8593 * A Bus Reset could occur at any time and flush the tx_waitq, 8594 * so we cannot count on the tx_waitq to contain even one cmd. 8595 * And when the m_tx_waitq_mutex is released and run 8596 * mptsas_accept_pkt(), the tx_waitq may be flushed. 8597 */ 8598 cmd = mpt->m_tx_waitq; 8599 for (;;) { 8600 if ((cmd = mpt->m_tx_waitq) == NULL) { 8601 mpt->m_tx_draining = 0; 8602 break; 8603 } 8604 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) { 8605 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 8606 } 8607 cmd->cmd_linkp = NULL; 8608 mutex_exit(&mpt->m_tx_waitq_mutex); 8609 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT) 8610 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed " 8611 "to accept cmd on queue\n"); 8612 mutex_enter(&mpt->m_tx_waitq_mutex); 8613 } 8614 } 8615 8616 8617 /* 8618 * mpt tag type lookup 8619 */ 8620 static char mptsas_tag_lookup[] = 8621 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG}; 8622 8623 static int 8624 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8625 { 8626 struct scsi_pkt *pkt = CMD2PKT(cmd); 8627 uint32_t control = 0; 8628 caddr_t mem, arsbuf; 8629 pMpi2SCSIIORequest_t io_request; 8630 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 8631 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 8632 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8633 uint16_t SMID, io_flags = 0; 8634 uint8_t ars_size; 8635 uint64_t request_desc; 8636 uint32_t ars_dmaaddrlow; 8637 mptsas_cmd_t *c; 8638 8639 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd, 8640 cmd->cmd_flags)); 8641 8642 /* 8643 * Set SMID and increment index. Rollover to 1 instead of 0 if index 8644 * is at the max. 0 is an invalid SMID, so we call the first index 1. 8645 */ 8646 SMID = cmd->cmd_slot; 8647 8648 /* 8649 * It is possible for back to back device reset to 8650 * happen before the reset delay has expired. That's 8651 * ok, just let the device reset go out on the bus. 8652 */ 8653 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8654 ASSERT(ptgt->m_reset_delay == 0); 8655 } 8656 8657 /* 8658 * if a non-tagged cmd is submitted to an active tagged target 8659 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 8660 * to be untagged 8661 */ 8662 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 8663 (ptgt->m_t_ncmds > 1) && 8664 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 8665 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 8666 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8667 NDBG23(("target=%d, untagged cmd, start draining\n", 8668 ptgt->m_devhdl)); 8669 8670 if (ptgt->m_reset_delay == 0) { 8671 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 8672 } 8673 8674 mptsas_remove_cmd(mpt, cmd); 8675 cmd->cmd_pkt_flags |= FLAG_HEAD; 8676 mptsas_waitq_add(mpt, cmd); 8677 } 8678 return (DDI_FAILURE); 8679 } 8680 8681 /* 8682 * Set correct tag bits. 8683 */ 8684 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 8685 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 8686 FLAG_TAGMASK) >> 12)]) { 8687 case MSG_SIMPLE_QTAG: 8688 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8689 break; 8690 case MSG_HEAD_QTAG: 8691 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 8692 break; 8693 case MSG_ORDERED_QTAG: 8694 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 8695 break; 8696 default: 8697 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 8698 break; 8699 } 8700 } else { 8701 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 8702 ptgt->m_t_throttle = 1; 8703 } 8704 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8705 } 8706 8707 if (cmd->cmd_pkt_flags & FLAG_TLR) { 8708 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 8709 } 8710 8711 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 8712 io_request = (pMpi2SCSIIORequest_t)mem; 8713 if (cmd->cmd_extrqslen != 0) { 8714 /* 8715 * Mapping of the buffer was done in mptsas_pkt_alloc_extern(). 8716 * Calculate the DMA address with the same offset. 8717 */ 8718 arsbuf = cmd->cmd_arq_buf; 8719 ars_size = cmd->cmd_extrqslen; 8720 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8721 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 8722 0xffffffffu; 8723 } else { 8724 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1)); 8725 cmd->cmd_arq_buf = arsbuf; 8726 ars_size = mpt->m_req_sense_size; 8727 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8728 (mpt->m_req_sense_size * (SMID-1))) & 8729 0xffffffffu; 8730 } 8731 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 8732 bzero(arsbuf, ars_size); 8733 8734 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 8735 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 8736 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 8737 MPI2_FUNCTION_SCSI_IO_REQUEST); 8738 8739 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 8740 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 8741 8742 io_flags = cmd->cmd_cdblen; 8743 if (mptsas_use_fastpath && 8744 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) { 8745 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH; 8746 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 8747 } else { 8748 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 8749 } 8750 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 8751 /* 8752 * setup the Scatter/Gather DMA list for this request 8753 */ 8754 if (cmd->cmd_cookiec > 0) { 8755 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 8756 } else { 8757 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 8758 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 8759 MPI2_SGE_FLAGS_END_OF_BUFFER | 8760 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 8761 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 8762 } 8763 8764 /* 8765 * save ARQ information 8766 */ 8767 ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size); 8768 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow); 8769 8770 ddi_put32(acc_hdl, &io_request->Control, control); 8771 8772 NDBG31(("starting message=%d(0x%p), with cmd=0x%p", 8773 SMID, (void *)io_request, (void *)cmd)); 8774 8775 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 8776 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 8777 DDI_DMA_SYNC_FORDEV); 8778 8779 /* 8780 * Build request descriptor and write it to the request desc post reg. 8781 */ 8782 request_desc |= (SMID << 16); 8783 request_desc |= (uint64_t)ptgt->m_devhdl << 48; 8784 MPTSAS_START_CMD(mpt, request_desc); 8785 8786 /* 8787 * Start timeout. 8788 */ 8789 cmd->cmd_active_expiration = 8790 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC; 8791 #ifdef MPTSAS_TEST 8792 /* 8793 * Force timeouts to happen immediately. 8794 */ 8795 if (mptsas_test_timeouts) 8796 cmd->cmd_active_expiration = gethrtime(); 8797 #endif 8798 c = TAILQ_FIRST(&ptgt->m_active_cmdq); 8799 if (c == NULL || 8800 c->cmd_active_expiration < cmd->cmd_active_expiration) { 8801 /* 8802 * Common case is that this is the last pending expiration 8803 * (or queue is empty). Insert at head of the queue. 8804 */ 8805 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link); 8806 } else { 8807 /* 8808 * Queue is not empty and first element expires later than 8809 * this command. Search for element expiring sooner. 8810 */ 8811 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) { 8812 if (c->cmd_active_expiration < 8813 cmd->cmd_active_expiration) { 8814 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link); 8815 break; 8816 } 8817 } 8818 if (c == NULL) { 8819 /* 8820 * No element found expiring sooner, append to 8821 * non-empty queue. 8822 */ 8823 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd, 8824 cmd_active_link); 8825 } 8826 } 8827 8828 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 8829 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 8830 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8831 return (DDI_FAILURE); 8832 } 8833 return (DDI_SUCCESS); 8834 } 8835 8836 /* 8837 * Select a helper thread to handle current doneq 8838 */ 8839 static void 8840 mptsas_deliver_doneq_thread(mptsas_t *mpt) 8841 { 8842 uint64_t t, i; 8843 uint32_t min = 0xffffffff; 8844 mptsas_doneq_thread_list_t *item; 8845 8846 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 8847 item = &mpt->m_doneq_thread_id[i]; 8848 /* 8849 * If the completed command on help thread[i] less than 8850 * doneq_thread_threshold, then pick the thread[i]. Otherwise 8851 * pick a thread which has least completed command. 8852 */ 8853 8854 mutex_enter(&item->mutex); 8855 if (item->len < mpt->m_doneq_thread_threshold) { 8856 t = i; 8857 mutex_exit(&item->mutex); 8858 break; 8859 } 8860 if (item->len < min) { 8861 min = item->len; 8862 t = i; 8863 } 8864 mutex_exit(&item->mutex); 8865 } 8866 mutex_enter(&mpt->m_doneq_thread_id[t].mutex); 8867 mptsas_doneq_mv(mpt, t); 8868 cv_signal(&mpt->m_doneq_thread_id[t].cv); 8869 mutex_exit(&mpt->m_doneq_thread_id[t].mutex); 8870 } 8871 8872 /* 8873 * move the current global doneq to the doneq of thead[t] 8874 */ 8875 static void 8876 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t) 8877 { 8878 mptsas_cmd_t *cmd; 8879 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8880 8881 ASSERT(mutex_owned(&item->mutex)); 8882 while ((cmd = mpt->m_doneq) != NULL) { 8883 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) { 8884 mpt->m_donetail = &mpt->m_doneq; 8885 } 8886 cmd->cmd_linkp = NULL; 8887 *item->donetail = cmd; 8888 item->donetail = &cmd->cmd_linkp; 8889 mpt->m_doneq_len--; 8890 item->len++; 8891 } 8892 } 8893 8894 void 8895 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd) 8896 { 8897 struct scsi_pkt *pkt = CMD2PKT(cmd); 8898 8899 /* Check all acc and dma handles */ 8900 if ((mptsas_check_acc_handle(mpt->m_datap) != 8901 DDI_SUCCESS) || 8902 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 8903 DDI_SUCCESS) || 8904 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 8905 DDI_SUCCESS) || 8906 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 8907 DDI_SUCCESS) || 8908 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 8909 DDI_SUCCESS) || 8910 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 8911 DDI_SUCCESS) || 8912 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 8913 DDI_SUCCESS) || 8914 (mptsas_check_acc_handle(mpt->m_config_handle) != 8915 DDI_SUCCESS)) { 8916 ddi_fm_service_impact(mpt->m_dip, 8917 DDI_SERVICE_UNAFFECTED); 8918 ddi_fm_acc_err_clear(mpt->m_config_handle, 8919 DDI_FME_VER0); 8920 pkt->pkt_reason = CMD_TRAN_ERR; 8921 pkt->pkt_statistics = 0; 8922 } 8923 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 8924 DDI_SUCCESS) || 8925 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 8926 DDI_SUCCESS) || 8927 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 8928 DDI_SUCCESS) || 8929 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 8930 DDI_SUCCESS) || 8931 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 8932 DDI_SUCCESS) || 8933 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 8934 DDI_SUCCESS)) { 8935 ddi_fm_service_impact(mpt->m_dip, 8936 DDI_SERVICE_UNAFFECTED); 8937 pkt->pkt_reason = CMD_TRAN_ERR; 8938 pkt->pkt_statistics = 0; 8939 } 8940 if (cmd->cmd_dmahandle && 8941 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 8942 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8943 pkt->pkt_reason = CMD_TRAN_ERR; 8944 pkt->pkt_statistics = 0; 8945 } 8946 if ((cmd->cmd_extra_frames && 8947 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 8948 DDI_SUCCESS) || 8949 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 8950 DDI_SUCCESS)))) { 8951 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8952 pkt->pkt_reason = CMD_TRAN_ERR; 8953 pkt->pkt_statistics = 0; 8954 } 8955 } 8956 8957 /* 8958 * These routines manipulate the queue of commands that 8959 * are waiting for their completion routines to be called. 8960 * The queue is usually in FIFO order but on an MP system 8961 * it's possible for the completion routines to get out 8962 * of order. If that's a problem you need to add a global 8963 * mutex around the code that calls the completion routine 8964 * in the interrupt handler. 8965 */ 8966 static void 8967 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8968 { 8969 struct scsi_pkt *pkt = CMD2PKT(cmd); 8970 8971 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd)); 8972 8973 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0); 8974 cmd->cmd_linkp = NULL; 8975 cmd->cmd_flags |= CFLAG_FINISHED; 8976 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT; 8977 8978 mptsas_fma_check(mpt, cmd); 8979 8980 /* 8981 * only add scsi pkts that have completion routines to 8982 * the doneq. no intr cmds do not have callbacks. 8983 */ 8984 if (pkt && (pkt->pkt_comp)) { 8985 *mpt->m_donetail = cmd; 8986 mpt->m_donetail = &cmd->cmd_linkp; 8987 mpt->m_doneq_len++; 8988 } 8989 } 8990 8991 static mptsas_cmd_t * 8992 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t) 8993 { 8994 mptsas_cmd_t *cmd; 8995 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8996 8997 /* pop one off the done queue */ 8998 if ((cmd = item->doneq) != NULL) { 8999 /* if the queue is now empty fix the tail pointer */ 9000 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd)); 9001 if ((item->doneq = cmd->cmd_linkp) == NULL) { 9002 item->donetail = &item->doneq; 9003 } 9004 cmd->cmd_linkp = NULL; 9005 item->len--; 9006 } 9007 return (cmd); 9008 } 9009 9010 static void 9011 mptsas_doneq_empty(mptsas_t *mpt) 9012 { 9013 if (mpt->m_doneq && !mpt->m_in_callback) { 9014 mptsas_cmd_t *cmd, *next; 9015 struct scsi_pkt *pkt; 9016 9017 mpt->m_in_callback = 1; 9018 cmd = mpt->m_doneq; 9019 mpt->m_doneq = NULL; 9020 mpt->m_donetail = &mpt->m_doneq; 9021 mpt->m_doneq_len = 0; 9022 9023 mutex_exit(&mpt->m_mutex); 9024 /* 9025 * run the completion routines of all the 9026 * completed commands 9027 */ 9028 while (cmd != NULL) { 9029 next = cmd->cmd_linkp; 9030 cmd->cmd_linkp = NULL; 9031 /* run this command's completion routine */ 9032 cmd->cmd_flags |= CFLAG_COMPLETED; 9033 pkt = CMD2PKT(cmd); 9034 mptsas_pkt_comp(pkt, cmd); 9035 cmd = next; 9036 } 9037 mutex_enter(&mpt->m_mutex); 9038 mpt->m_in_callback = 0; 9039 } 9040 } 9041 9042 /* 9043 * These routines manipulate the target's queue of pending requests 9044 */ 9045 void 9046 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 9047 { 9048 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd)); 9049 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 9050 cmd->cmd_queued = TRUE; 9051 if (ptgt) 9052 ptgt->m_t_nwait++; 9053 if (cmd->cmd_pkt_flags & FLAG_HEAD) { 9054 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) { 9055 mpt->m_waitqtail = &cmd->cmd_linkp; 9056 } 9057 mpt->m_waitq = cmd; 9058 } else { 9059 cmd->cmd_linkp = NULL; 9060 *(mpt->m_waitqtail) = cmd; 9061 mpt->m_waitqtail = &cmd->cmd_linkp; 9062 } 9063 } 9064 9065 static mptsas_cmd_t * 9066 mptsas_waitq_rm(mptsas_t *mpt) 9067 { 9068 mptsas_cmd_t *cmd; 9069 mptsas_target_t *ptgt; 9070 NDBG7(("mptsas_waitq_rm")); 9071 9072 MPTSAS_WAITQ_RM(mpt, cmd); 9073 9074 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd)); 9075 if (cmd) { 9076 ptgt = cmd->cmd_tgt_addr; 9077 if (ptgt) { 9078 ptgt->m_t_nwait--; 9079 ASSERT(ptgt->m_t_nwait >= 0); 9080 } 9081 } 9082 return (cmd); 9083 } 9084 9085 /* 9086 * remove specified cmd from the middle of the wait queue. 9087 */ 9088 static void 9089 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 9090 { 9091 mptsas_cmd_t *prevp = mpt->m_waitq; 9092 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 9093 9094 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9095 (void *)mpt, (void *)cmd)); 9096 if (ptgt) { 9097 ptgt->m_t_nwait--; 9098 ASSERT(ptgt->m_t_nwait >= 0); 9099 } 9100 9101 if (prevp == cmd) { 9102 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL) 9103 mpt->m_waitqtail = &mpt->m_waitq; 9104 9105 cmd->cmd_linkp = NULL; 9106 cmd->cmd_queued = FALSE; 9107 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9108 (void *)mpt, (void *)cmd)); 9109 return; 9110 } 9111 9112 while (prevp != NULL) { 9113 if (prevp->cmd_linkp == cmd) { 9114 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 9115 mpt->m_waitqtail = &prevp->cmd_linkp; 9116 9117 cmd->cmd_linkp = NULL; 9118 cmd->cmd_queued = FALSE; 9119 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9120 (void *)mpt, (void *)cmd)); 9121 return; 9122 } 9123 prevp = prevp->cmd_linkp; 9124 } 9125 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch"); 9126 } 9127 9128 static mptsas_cmd_t * 9129 mptsas_tx_waitq_rm(mptsas_t *mpt) 9130 { 9131 mptsas_cmd_t *cmd; 9132 NDBG7(("mptsas_tx_waitq_rm")); 9133 9134 MPTSAS_TX_WAITQ_RM(mpt, cmd); 9135 9136 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd)); 9137 9138 return (cmd); 9139 } 9140 9141 /* 9142 * remove specified cmd from the middle of the tx_waitq. 9143 */ 9144 static void 9145 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 9146 { 9147 mptsas_cmd_t *prevp = mpt->m_tx_waitq; 9148 9149 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9150 (void *)mpt, (void *)cmd)); 9151 9152 if (prevp == cmd) { 9153 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) 9154 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 9155 9156 cmd->cmd_linkp = NULL; 9157 cmd->cmd_queued = FALSE; 9158 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9159 (void *)mpt, (void *)cmd)); 9160 return; 9161 } 9162 9163 while (prevp != NULL) { 9164 if (prevp->cmd_linkp == cmd) { 9165 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 9166 mpt->m_tx_waitqtail = &prevp->cmd_linkp; 9167 9168 cmd->cmd_linkp = NULL; 9169 cmd->cmd_queued = FALSE; 9170 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9171 (void *)mpt, (void *)cmd)); 9172 return; 9173 } 9174 prevp = prevp->cmd_linkp; 9175 } 9176 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch"); 9177 } 9178 9179 /* 9180 * device and bus reset handling 9181 * 9182 * Notes: 9183 * - RESET_ALL: reset the controller 9184 * - RESET_TARGET: reset the target specified in scsi_address 9185 */ 9186 static int 9187 mptsas_scsi_reset(struct scsi_address *ap, int level) 9188 { 9189 mptsas_t *mpt = ADDR2MPT(ap); 9190 int rval; 9191 mptsas_tgt_private_t *tgt_private; 9192 mptsas_target_t *ptgt = NULL; 9193 9194 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private; 9195 ptgt = tgt_private->t_private; 9196 if (ptgt == NULL) { 9197 return (FALSE); 9198 } 9199 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl, 9200 level)); 9201 9202 mutex_enter(&mpt->m_mutex); 9203 /* 9204 * if we are not in panic set up a reset delay for this target 9205 */ 9206 if (!ddi_in_panic()) { 9207 mptsas_setup_bus_reset_delay(mpt); 9208 } else { 9209 drv_usecwait(mpt->m_scsi_reset_delay * 1000); 9210 } 9211 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl); 9212 mutex_exit(&mpt->m_mutex); 9213 9214 /* 9215 * The transport layer expect to only see TRUE and 9216 * FALSE. Therefore, we will adjust the return value 9217 * if mptsas_do_scsi_reset returns FAILED. 9218 */ 9219 if (rval == FAILED) 9220 rval = FALSE; 9221 return (rval); 9222 } 9223 9224 static int 9225 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl) 9226 { 9227 int rval = FALSE; 9228 uint8_t config, disk; 9229 9230 ASSERT(mutex_owned(&mpt->m_mutex)); 9231 9232 if (mptsas_debug_resets) { 9233 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d", 9234 devhdl); 9235 } 9236 9237 /* 9238 * Issue a Target Reset message to the target specified but not to a 9239 * disk making up a raid volume. Just look through the RAID config 9240 * Phys Disk list of DevHandles. If the target's DevHandle is in this 9241 * list, then don't reset this target. 9242 */ 9243 for (config = 0; config < mpt->m_num_raid_configs; config++) { 9244 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 9245 if (devhdl == mpt->m_raidconfig[config]. 9246 m_physdisk_devhdl[disk]) { 9247 return (TRUE); 9248 } 9249 } 9250 } 9251 9252 rval = mptsas_ioc_task_management(mpt, 9253 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0); 9254 9255 mptsas_doneq_empty(mpt); 9256 return (rval); 9257 } 9258 9259 static int 9260 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 9261 void (*callback)(caddr_t), caddr_t arg) 9262 { 9263 mptsas_t *mpt = ADDR2MPT(ap); 9264 9265 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target)); 9266 9267 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg, 9268 &mpt->m_mutex, &mpt->m_reset_notify_listf)); 9269 } 9270 9271 static int 9272 mptsas_get_name(struct scsi_device *sd, char *name, int len) 9273 { 9274 dev_info_t *lun_dip = NULL; 9275 9276 ASSERT(sd != NULL); 9277 ASSERT(name != NULL); 9278 lun_dip = sd->sd_dev; 9279 ASSERT(lun_dip != NULL); 9280 9281 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) { 9282 return (1); 9283 } else { 9284 return (0); 9285 } 9286 } 9287 9288 static int 9289 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len) 9290 { 9291 return (mptsas_get_name(sd, name, len)); 9292 } 9293 9294 void 9295 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what) 9296 { 9297 9298 NDBG25(("mptsas_set_throttle: throttle=%x", what)); 9299 9300 /* 9301 * if the bus is draining/quiesced, no changes to the throttles 9302 * are allowed. Not allowing change of throttles during draining 9303 * limits error recovery but will reduce draining time 9304 * 9305 * all throttles should have been set to HOLD_THROTTLE 9306 */ 9307 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) { 9308 return; 9309 } 9310 9311 if (what == HOLD_THROTTLE) { 9312 ptgt->m_t_throttle = HOLD_THROTTLE; 9313 } else if (ptgt->m_reset_delay == 0) { 9314 ptgt->m_t_throttle = what; 9315 } 9316 } 9317 9318 /* 9319 * Clean up from a device reset. 9320 * For the case of target reset, this function clears the waitq of all 9321 * commands for a particular target. For the case of abort task set, this 9322 * function clears the waitq of all commonds for a particular target/lun. 9323 */ 9324 static void 9325 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype) 9326 { 9327 mptsas_slots_t *slots = mpt->m_active; 9328 mptsas_cmd_t *cmd, *next_cmd; 9329 int slot; 9330 uchar_t reason; 9331 uint_t stat; 9332 hrtime_t timestamp; 9333 9334 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun)); 9335 9336 timestamp = gethrtime(); 9337 9338 /* 9339 * Make sure the I/O Controller has flushed all cmds 9340 * that are associated with this target for a target reset 9341 * and target/lun for abort task set. 9342 * Account for TM requests, which use the last SMID. 9343 */ 9344 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9345 if ((cmd = slots->m_slot[slot]) == NULL) 9346 continue; 9347 reason = CMD_RESET; 9348 stat = STAT_DEV_RESET; 9349 switch (tasktype) { 9350 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9351 if (Tgt(cmd) == target) { 9352 if (cmd->cmd_active_expiration <= timestamp) { 9353 /* 9354 * When timeout requested, propagate 9355 * proper reason and statistics to 9356 * target drivers. 9357 */ 9358 reason = CMD_TIMEOUT; 9359 stat |= STAT_TIMEOUT; 9360 } 9361 NDBG25(("mptsas_flush_target discovered non-" 9362 "NULL cmd in slot %d, tasktype 0x%x", slot, 9363 tasktype)); 9364 mptsas_dump_cmd(mpt, cmd); 9365 mptsas_remove_cmd(mpt, cmd); 9366 mptsas_set_pkt_reason(mpt, cmd, reason, stat); 9367 mptsas_doneq_add(mpt, cmd); 9368 } 9369 break; 9370 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9371 reason = CMD_ABORTED; 9372 stat = STAT_ABORTED; 9373 /*FALLTHROUGH*/ 9374 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9375 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9376 9377 NDBG25(("mptsas_flush_target discovered non-" 9378 "NULL cmd in slot %d, tasktype 0x%x", slot, 9379 tasktype)); 9380 mptsas_dump_cmd(mpt, cmd); 9381 mptsas_remove_cmd(mpt, cmd); 9382 mptsas_set_pkt_reason(mpt, cmd, reason, 9383 stat); 9384 mptsas_doneq_add(mpt, cmd); 9385 } 9386 break; 9387 default: 9388 break; 9389 } 9390 } 9391 9392 /* 9393 * Flush the waitq and tx_waitq of this target's cmds 9394 */ 9395 cmd = mpt->m_waitq; 9396 9397 reason = CMD_RESET; 9398 stat = STAT_DEV_RESET; 9399 9400 switch (tasktype) { 9401 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9402 while (cmd != NULL) { 9403 next_cmd = cmd->cmd_linkp; 9404 if (Tgt(cmd) == target) { 9405 mptsas_waitq_delete(mpt, cmd); 9406 mptsas_set_pkt_reason(mpt, cmd, 9407 reason, stat); 9408 mptsas_doneq_add(mpt, cmd); 9409 } 9410 cmd = next_cmd; 9411 } 9412 mutex_enter(&mpt->m_tx_waitq_mutex); 9413 cmd = mpt->m_tx_waitq; 9414 while (cmd != NULL) { 9415 next_cmd = cmd->cmd_linkp; 9416 if (Tgt(cmd) == target) { 9417 mptsas_tx_waitq_delete(mpt, cmd); 9418 mutex_exit(&mpt->m_tx_waitq_mutex); 9419 mptsas_set_pkt_reason(mpt, cmd, 9420 reason, stat); 9421 mptsas_doneq_add(mpt, cmd); 9422 mutex_enter(&mpt->m_tx_waitq_mutex); 9423 } 9424 cmd = next_cmd; 9425 } 9426 mutex_exit(&mpt->m_tx_waitq_mutex); 9427 break; 9428 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9429 reason = CMD_ABORTED; 9430 stat = STAT_ABORTED; 9431 /*FALLTHROUGH*/ 9432 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9433 while (cmd != NULL) { 9434 next_cmd = cmd->cmd_linkp; 9435 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9436 mptsas_waitq_delete(mpt, cmd); 9437 mptsas_set_pkt_reason(mpt, cmd, 9438 reason, stat); 9439 mptsas_doneq_add(mpt, cmd); 9440 } 9441 cmd = next_cmd; 9442 } 9443 mutex_enter(&mpt->m_tx_waitq_mutex); 9444 cmd = mpt->m_tx_waitq; 9445 while (cmd != NULL) { 9446 next_cmd = cmd->cmd_linkp; 9447 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9448 mptsas_tx_waitq_delete(mpt, cmd); 9449 mutex_exit(&mpt->m_tx_waitq_mutex); 9450 mptsas_set_pkt_reason(mpt, cmd, 9451 reason, stat); 9452 mptsas_doneq_add(mpt, cmd); 9453 mutex_enter(&mpt->m_tx_waitq_mutex); 9454 } 9455 cmd = next_cmd; 9456 } 9457 mutex_exit(&mpt->m_tx_waitq_mutex); 9458 break; 9459 default: 9460 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 9461 tasktype); 9462 break; 9463 } 9464 } 9465 9466 /* 9467 * Clean up hba state, abort all outstanding command and commands in waitq 9468 * reset timeout of all targets. 9469 */ 9470 static void 9471 mptsas_flush_hba(mptsas_t *mpt) 9472 { 9473 mptsas_slots_t *slots = mpt->m_active; 9474 mptsas_cmd_t *cmd; 9475 int slot; 9476 9477 NDBG25(("mptsas_flush_hba")); 9478 9479 /* 9480 * The I/O Controller should have already sent back 9481 * all commands via the scsi I/O reply frame. Make 9482 * sure all commands have been flushed. 9483 * Account for TM request, which use the last SMID. 9484 */ 9485 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9486 if ((cmd = slots->m_slot[slot]) == NULL) 9487 continue; 9488 9489 if (cmd->cmd_flags & CFLAG_CMDIOC) { 9490 /* 9491 * Need to make sure to tell everyone that might be 9492 * waiting on this command that it's going to fail. If 9493 * we get here, this command will never timeout because 9494 * the active command table is going to be re-allocated, 9495 * so there will be nothing to check against a time out. 9496 * Instead, mark the command as failed due to reset. 9497 */ 9498 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 9499 STAT_BUS_RESET); 9500 if ((cmd->cmd_flags & 9501 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 9502 cmd->cmd_flags |= CFLAG_FINISHED; 9503 cv_broadcast(&mpt->m_passthru_cv); 9504 cv_broadcast(&mpt->m_config_cv); 9505 cv_broadcast(&mpt->m_fw_diag_cv); 9506 } 9507 continue; 9508 } 9509 9510 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d", 9511 slot)); 9512 mptsas_dump_cmd(mpt, cmd); 9513 9514 mptsas_remove_cmd(mpt, cmd); 9515 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9516 mptsas_doneq_add(mpt, cmd); 9517 } 9518 9519 /* 9520 * Flush the waitq. 9521 */ 9522 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) { 9523 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9524 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9525 (cmd->cmd_flags & CFLAG_CONFIG) || 9526 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9527 cmd->cmd_flags |= CFLAG_FINISHED; 9528 cv_broadcast(&mpt->m_passthru_cv); 9529 cv_broadcast(&mpt->m_config_cv); 9530 cv_broadcast(&mpt->m_fw_diag_cv); 9531 } else { 9532 mptsas_doneq_add(mpt, cmd); 9533 } 9534 } 9535 9536 /* 9537 * Flush the tx_waitq 9538 */ 9539 mutex_enter(&mpt->m_tx_waitq_mutex); 9540 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) { 9541 mutex_exit(&mpt->m_tx_waitq_mutex); 9542 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9543 mptsas_doneq_add(mpt, cmd); 9544 mutex_enter(&mpt->m_tx_waitq_mutex); 9545 } 9546 mutex_exit(&mpt->m_tx_waitq_mutex); 9547 9548 /* 9549 * Drain the taskqs prior to reallocating resources. The thread 9550 * passing through here could be launched from either (dr) 9551 * or (event) taskqs so only wait on the 'other' queue since 9552 * waiting on 'this' queue is a deadlock condition. 9553 */ 9554 mutex_exit(&mpt->m_mutex); 9555 if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread)) 9556 ddi_taskq_wait(mpt->m_event_taskq); 9557 if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread)) 9558 ddi_taskq_wait(mpt->m_dr_taskq); 9559 9560 mutex_enter(&mpt->m_mutex); 9561 } 9562 9563 /* 9564 * set pkt_reason and OR in pkt_statistics flag 9565 */ 9566 static void 9567 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason, 9568 uint_t stat) 9569 { 9570 #ifndef __lock_lint 9571 _NOTE(ARGUNUSED(mpt)) 9572 #endif 9573 9574 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x", 9575 (void *)cmd, reason, stat)); 9576 9577 if (cmd) { 9578 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) { 9579 cmd->cmd_pkt->pkt_reason = reason; 9580 } 9581 cmd->cmd_pkt->pkt_statistics |= stat; 9582 } 9583 } 9584 9585 static void 9586 mptsas_start_watch_reset_delay() 9587 { 9588 NDBG22(("mptsas_start_watch_reset_delay")); 9589 9590 mutex_enter(&mptsas_global_mutex); 9591 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) { 9592 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL, 9593 drv_usectohz((clock_t) 9594 MPTSAS_WATCH_RESET_DELAY_TICK * 1000)); 9595 ASSERT(mptsas_reset_watch != NULL); 9596 } 9597 mutex_exit(&mptsas_global_mutex); 9598 } 9599 9600 static void 9601 mptsas_setup_bus_reset_delay(mptsas_t *mpt) 9602 { 9603 mptsas_target_t *ptgt = NULL; 9604 9605 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 9606 9607 NDBG22(("mptsas_setup_bus_reset_delay")); 9608 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9609 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9610 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9611 ptgt->m_reset_delay = mpt->m_scsi_reset_delay; 9612 } 9613 9614 mptsas_start_watch_reset_delay(); 9615 } 9616 9617 /* 9618 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every 9619 * mpt instance for active reset delays 9620 */ 9621 static void 9622 mptsas_watch_reset_delay(void *arg) 9623 { 9624 #ifndef __lock_lint 9625 _NOTE(ARGUNUSED(arg)) 9626 #endif 9627 9628 mptsas_t *mpt; 9629 int not_done = 0; 9630 9631 NDBG22(("mptsas_watch_reset_delay")); 9632 9633 mutex_enter(&mptsas_global_mutex); 9634 mptsas_reset_watch = 0; 9635 mutex_exit(&mptsas_global_mutex); 9636 rw_enter(&mptsas_global_rwlock, RW_READER); 9637 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) { 9638 if (mpt->m_tran == 0) { 9639 continue; 9640 } 9641 mutex_enter(&mpt->m_mutex); 9642 not_done += mptsas_watch_reset_delay_subr(mpt); 9643 mutex_exit(&mpt->m_mutex); 9644 } 9645 rw_exit(&mptsas_global_rwlock); 9646 9647 if (not_done) { 9648 mptsas_start_watch_reset_delay(); 9649 } 9650 } 9651 9652 static int 9653 mptsas_watch_reset_delay_subr(mptsas_t *mpt) 9654 { 9655 int done = 0; 9656 int restart = 0; 9657 mptsas_target_t *ptgt = NULL; 9658 9659 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt)); 9660 9661 ASSERT(mutex_owned(&mpt->m_mutex)); 9662 9663 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9664 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9665 if (ptgt->m_reset_delay != 0) { 9666 ptgt->m_reset_delay -= 9667 MPTSAS_WATCH_RESET_DELAY_TICK; 9668 if (ptgt->m_reset_delay <= 0) { 9669 ptgt->m_reset_delay = 0; 9670 mptsas_set_throttle(mpt, ptgt, 9671 MAX_THROTTLE); 9672 restart++; 9673 } else { 9674 done = -1; 9675 } 9676 } 9677 } 9678 9679 if (restart > 0) { 9680 mptsas_restart_hba(mpt); 9681 } 9682 return (done); 9683 } 9684 9685 #ifdef MPTSAS_TEST 9686 static void 9687 mptsas_test_reset(mptsas_t *mpt, int target) 9688 { 9689 mptsas_target_t *ptgt = NULL; 9690 9691 if (mptsas_rtest == target) { 9692 if (mptsas_do_scsi_reset(mpt, target) == TRUE) { 9693 mptsas_rtest = -1; 9694 } 9695 if (mptsas_rtest == -1) { 9696 NDBG22(("mptsas_test_reset success")); 9697 } 9698 } 9699 } 9700 #endif 9701 9702 /* 9703 * abort handling: 9704 * 9705 * Notes: 9706 * - if pkt is not NULL, abort just that command 9707 * - if pkt is NULL, abort all outstanding commands for target 9708 */ 9709 static int 9710 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 9711 { 9712 mptsas_t *mpt = ADDR2MPT(ap); 9713 int rval; 9714 mptsas_tgt_private_t *tgt_private; 9715 int target, lun; 9716 9717 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 9718 tran_tgt_private; 9719 ASSERT(tgt_private != NULL); 9720 target = tgt_private->t_private->m_devhdl; 9721 lun = tgt_private->t_lun; 9722 9723 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun)); 9724 9725 mutex_enter(&mpt->m_mutex); 9726 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt); 9727 mutex_exit(&mpt->m_mutex); 9728 return (rval); 9729 } 9730 9731 static int 9732 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt) 9733 { 9734 mptsas_cmd_t *sp = NULL; 9735 mptsas_slots_t *slots = mpt->m_active; 9736 int rval = FALSE; 9737 9738 ASSERT(mutex_owned(&mpt->m_mutex)); 9739 9740 /* 9741 * Abort the command pkt on the target/lun in ap. If pkt is 9742 * NULL, abort all outstanding commands on that target/lun. 9743 * If you can abort them, return 1, else return 0. 9744 * Each packet that's aborted should be sent back to the target 9745 * driver through the callback routine, with pkt_reason set to 9746 * CMD_ABORTED. 9747 * 9748 * abort cmd pkt on HBA hardware; clean out of outstanding 9749 * command lists, etc. 9750 */ 9751 if (pkt != NULL) { 9752 /* abort the specified packet */ 9753 sp = PKT2CMD(pkt); 9754 9755 if (sp->cmd_queued) { 9756 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted", 9757 (void *)sp)); 9758 mptsas_waitq_delete(mpt, sp); 9759 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED, 9760 STAT_ABORTED); 9761 mptsas_doneq_add(mpt, sp); 9762 rval = TRUE; 9763 goto done; 9764 } 9765 9766 /* 9767 * Have mpt firmware abort this command 9768 */ 9769 9770 if (slots->m_slot[sp->cmd_slot] != NULL) { 9771 rval = mptsas_ioc_task_management(mpt, 9772 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target, 9773 lun, NULL, 0, 0); 9774 9775 /* 9776 * The transport layer expects only TRUE and FALSE. 9777 * Therefore, if mptsas_ioc_task_management returns 9778 * FAILED we will return FALSE. 9779 */ 9780 if (rval == FAILED) 9781 rval = FALSE; 9782 goto done; 9783 } 9784 } 9785 9786 /* 9787 * If pkt is NULL then abort task set 9788 */ 9789 rval = mptsas_ioc_task_management(mpt, 9790 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0); 9791 9792 /* 9793 * The transport layer expects only TRUE and FALSE. 9794 * Therefore, if mptsas_ioc_task_management returns 9795 * FAILED we will return FALSE. 9796 */ 9797 if (rval == FAILED) 9798 rval = FALSE; 9799 9800 #ifdef MPTSAS_TEST 9801 if (rval && mptsas_test_stop) { 9802 debug_enter("mptsas_do_scsi_abort"); 9803 } 9804 #endif 9805 9806 done: 9807 mptsas_doneq_empty(mpt); 9808 return (rval); 9809 } 9810 9811 /* 9812 * capability handling: 9813 * (*tran_getcap). Get the capability named, and return its value. 9814 */ 9815 static int 9816 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly) 9817 { 9818 mptsas_t *mpt = ADDR2MPT(ap); 9819 int ckey; 9820 int rval = FALSE; 9821 9822 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x", 9823 ap->a_target, cap, tgtonly)); 9824 9825 mutex_enter(&mpt->m_mutex); 9826 9827 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9828 mutex_exit(&mpt->m_mutex); 9829 return (UNDEFINED); 9830 } 9831 9832 switch (ckey) { 9833 case SCSI_CAP_DMA_MAX: 9834 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer; 9835 break; 9836 case SCSI_CAP_ARQ: 9837 rval = TRUE; 9838 break; 9839 case SCSI_CAP_MSG_OUT: 9840 case SCSI_CAP_PARITY: 9841 case SCSI_CAP_UNTAGGED_QING: 9842 rval = TRUE; 9843 break; 9844 case SCSI_CAP_TAGGED_QING: 9845 rval = TRUE; 9846 break; 9847 case SCSI_CAP_RESET_NOTIFICATION: 9848 rval = TRUE; 9849 break; 9850 case SCSI_CAP_LINKED_CMDS: 9851 rval = FALSE; 9852 break; 9853 case SCSI_CAP_QFULL_RETRIES: 9854 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran-> 9855 tran_tgt_private))->t_private->m_qfull_retries; 9856 break; 9857 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9858 rval = drv_hztousec(((mptsas_tgt_private_t *) 9859 (ap->a_hba_tran->tran_tgt_private))-> 9860 t_private->m_qfull_retry_interval) / 1000; 9861 break; 9862 case SCSI_CAP_CDB_LEN: 9863 rval = CDB_GROUP4; 9864 break; 9865 case SCSI_CAP_INTERCONNECT_TYPE: 9866 rval = INTERCONNECT_SAS; 9867 break; 9868 case SCSI_CAP_TRAN_LAYER_RETRIES: 9869 if (mpt->m_ioc_capabilities & 9870 MPI2_IOCFACTS_CAPABILITY_TLR) 9871 rval = TRUE; 9872 else 9873 rval = FALSE; 9874 break; 9875 default: 9876 rval = UNDEFINED; 9877 break; 9878 } 9879 9880 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval)); 9881 9882 mutex_exit(&mpt->m_mutex); 9883 return (rval); 9884 } 9885 9886 /* 9887 * (*tran_setcap). Set the capability named to the value given. 9888 */ 9889 static int 9890 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly) 9891 { 9892 mptsas_t *mpt = ADDR2MPT(ap); 9893 int ckey; 9894 int rval = FALSE; 9895 9896 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x", 9897 ap->a_target, cap, value, tgtonly)); 9898 9899 if (!tgtonly) { 9900 return (rval); 9901 } 9902 9903 mutex_enter(&mpt->m_mutex); 9904 9905 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9906 mutex_exit(&mpt->m_mutex); 9907 return (UNDEFINED); 9908 } 9909 9910 switch (ckey) { 9911 case SCSI_CAP_DMA_MAX: 9912 case SCSI_CAP_MSG_OUT: 9913 case SCSI_CAP_PARITY: 9914 case SCSI_CAP_INITIATOR_ID: 9915 case SCSI_CAP_LINKED_CMDS: 9916 case SCSI_CAP_UNTAGGED_QING: 9917 case SCSI_CAP_RESET_NOTIFICATION: 9918 /* 9919 * None of these are settable via 9920 * the capability interface. 9921 */ 9922 break; 9923 case SCSI_CAP_ARQ: 9924 /* 9925 * We cannot turn off arq so return false if asked to 9926 */ 9927 if (value) { 9928 rval = TRUE; 9929 } else { 9930 rval = FALSE; 9931 } 9932 break; 9933 case SCSI_CAP_TAGGED_QING: 9934 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *) 9935 (ap->a_hba_tran->tran_tgt_private))->t_private, 9936 MAX_THROTTLE); 9937 rval = TRUE; 9938 break; 9939 case SCSI_CAP_QFULL_RETRIES: 9940 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9941 t_private->m_qfull_retries = (uchar_t)value; 9942 rval = TRUE; 9943 break; 9944 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9945 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9946 t_private->m_qfull_retry_interval = 9947 drv_usectohz(value * 1000); 9948 rval = TRUE; 9949 break; 9950 default: 9951 rval = UNDEFINED; 9952 break; 9953 } 9954 mutex_exit(&mpt->m_mutex); 9955 return (rval); 9956 } 9957 9958 /* 9959 * Utility routine for mptsas_ifsetcap/ifgetcap 9960 */ 9961 /*ARGSUSED*/ 9962 static int 9963 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp) 9964 { 9965 NDBG24(("mptsas_scsi_capchk: cap=%s", cap)); 9966 9967 if (!cap) 9968 return (FALSE); 9969 9970 *cidxp = scsi_hba_lookup_capstr(cap); 9971 return (TRUE); 9972 } 9973 9974 static int 9975 mptsas_alloc_active_slots(mptsas_t *mpt, int flag) 9976 { 9977 mptsas_slots_t *old_active = mpt->m_active; 9978 mptsas_slots_t *new_active; 9979 size_t size; 9980 9981 /* 9982 * if there are active commands, then we cannot 9983 * change size of active slots array. 9984 */ 9985 ASSERT(mpt->m_ncmds == 0); 9986 9987 size = MPTSAS_SLOTS_SIZE(mpt); 9988 new_active = kmem_zalloc(size, flag); 9989 if (new_active == NULL) { 9990 NDBG1(("new active alloc failed")); 9991 return (-1); 9992 } 9993 /* 9994 * Since SMID 0 is reserved and the TM slot is reserved, the 9995 * number of slots that can be used at any one time is 9996 * m_max_requests - 2. 9997 */ 9998 new_active->m_n_normal = (mpt->m_max_requests - 2); 9999 new_active->m_size = size; 10000 new_active->m_rotor = 1; 10001 if (old_active) 10002 mptsas_free_active_slots(mpt); 10003 mpt->m_active = new_active; 10004 10005 return (0); 10006 } 10007 10008 static void 10009 mptsas_free_active_slots(mptsas_t *mpt) 10010 { 10011 mptsas_slots_t *active = mpt->m_active; 10012 size_t size; 10013 10014 if (active == NULL) 10015 return; 10016 size = active->m_size; 10017 kmem_free(active, size); 10018 mpt->m_active = NULL; 10019 } 10020 10021 /* 10022 * Error logging, printing, and debug print routines. 10023 */ 10024 static char *mptsas_label = "mpt_sas"; 10025 10026 /*PRINTFLIKE3*/ 10027 void 10028 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...) 10029 { 10030 dev_info_t *dev; 10031 va_list ap; 10032 10033 if (mpt) { 10034 dev = mpt->m_dip; 10035 } else { 10036 dev = 0; 10037 } 10038 10039 mutex_enter(&mptsas_log_mutex); 10040 10041 va_start(ap, fmt); 10042 (void) vsprintf(mptsas_log_buf, fmt, ap); 10043 va_end(ap); 10044 10045 if (level == CE_CONT) { 10046 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf); 10047 } else { 10048 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf); 10049 } 10050 10051 mutex_exit(&mptsas_log_mutex); 10052 } 10053 10054 #ifdef MPTSAS_DEBUG 10055 /* 10056 * Use a circular buffer to log messages to private memory. 10057 * Increment idx atomically to minimize risk to miss lines. 10058 * It's fast and does not hold up the proceedings too much. 10059 */ 10060 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT; 10061 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN; 10062 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN]; 10063 static uint32_t mptsas_dbglog_idx = 0; 10064 10065 /*PRINTFLIKE1*/ 10066 void 10067 mptsas_debug_log(char *fmt, ...) 10068 { 10069 va_list ap; 10070 uint32_t idx; 10071 10072 idx = atomic_inc_32_nv(&mptsas_dbglog_idx) & 10073 (mptsas_dbglog_linecnt - 1); 10074 10075 va_start(ap, fmt); 10076 (void) vsnprintf(mptsas_dbglog_bufs[idx], 10077 mptsas_dbglog_linelen, fmt, ap); 10078 va_end(ap); 10079 } 10080 10081 /*PRINTFLIKE1*/ 10082 void 10083 mptsas_printf(char *fmt, ...) 10084 { 10085 dev_info_t *dev = 0; 10086 va_list ap; 10087 10088 mutex_enter(&mptsas_log_mutex); 10089 10090 va_start(ap, fmt); 10091 (void) vsprintf(mptsas_log_buf, fmt, ap); 10092 va_end(ap); 10093 10094 #ifdef PROM_PRINTF 10095 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf); 10096 #else 10097 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf); 10098 #endif 10099 mutex_exit(&mptsas_log_mutex); 10100 } 10101 #endif 10102 10103 /* 10104 * timeout handling 10105 */ 10106 static void 10107 mptsas_watch(void *arg) 10108 { 10109 #ifndef __lock_lint 10110 _NOTE(ARGUNUSED(arg)) 10111 #endif 10112 10113 mptsas_t *mpt; 10114 uint32_t doorbell; 10115 10116 NDBG30(("mptsas_watch")); 10117 10118 rw_enter(&mptsas_global_rwlock, RW_READER); 10119 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) { 10120 10121 mutex_enter(&mpt->m_mutex); 10122 10123 /* Skip device if not powered on */ 10124 if (mpt->m_options & MPTSAS_OPT_PM) { 10125 if (mpt->m_power_level == PM_LEVEL_D0) { 10126 (void) pm_busy_component(mpt->m_dip, 0); 10127 mpt->m_busy = 1; 10128 } else { 10129 mutex_exit(&mpt->m_mutex); 10130 continue; 10131 } 10132 } 10133 10134 /* 10135 * Check if controller is in a FAULT state. If so, reset it. 10136 */ 10137 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell); 10138 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 10139 doorbell &= MPI2_DOORBELL_DATA_MASK; 10140 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, " 10141 "code: %04x", doorbell); 10142 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 10143 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 10144 mptsas_log(mpt, CE_WARN, "Reset failed" 10145 "after fault was detected"); 10146 } 10147 } 10148 10149 /* 10150 * For now, always call mptsas_watchsubr. 10151 */ 10152 mptsas_watchsubr(mpt); 10153 10154 if (mpt->m_options & MPTSAS_OPT_PM) { 10155 mpt->m_busy = 0; 10156 (void) pm_idle_component(mpt->m_dip, 0); 10157 } 10158 10159 mutex_exit(&mpt->m_mutex); 10160 } 10161 rw_exit(&mptsas_global_rwlock); 10162 10163 mutex_enter(&mptsas_global_mutex); 10164 if (mptsas_timeouts_enabled) 10165 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 10166 mutex_exit(&mptsas_global_mutex); 10167 } 10168 10169 static void 10170 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp) 10171 { 10172 mptsas_cmd_t *cmd; 10173 10174 /* 10175 * If we were draining due to a qfull condition, 10176 * go back to full throttle. 10177 */ 10178 if ((ptgt->m_t_throttle < MAX_THROTTLE) && 10179 (ptgt->m_t_throttle > HOLD_THROTTLE) && 10180 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 10181 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10182 mptsas_restart_hba(mpt); 10183 } 10184 10185 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq); 10186 if (cmd == NULL) 10187 return; 10188 10189 if (cmd->cmd_active_expiration <= timestamp) { 10190 /* 10191 * Earliest command timeout expired. Drain throttle. 10192 */ 10193 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10194 10195 /* 10196 * Check for remaining commands. 10197 */ 10198 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq); 10199 if (cmd->cmd_active_expiration > timestamp) { 10200 /* 10201 * Wait for remaining commands to complete or 10202 * time out. 10203 */ 10204 NDBG23(("command timed out, pending drain")); 10205 return; 10206 } 10207 10208 /* 10209 * All command timeouts expired. 10210 */ 10211 mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds " 10212 "expired with %d commands on target %d lun %d.", 10213 cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds, 10214 ptgt->m_devhdl, Lun(cmd)); 10215 10216 mptsas_cmd_timeout(mpt, ptgt); 10217 } else if (cmd->cmd_active_expiration <= 10218 timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) { 10219 NDBG23(("pending timeout")); 10220 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10221 } 10222 } 10223 10224 static void 10225 mptsas_watchsubr(mptsas_t *mpt) 10226 { 10227 int i; 10228 mptsas_cmd_t *cmd; 10229 mptsas_target_t *ptgt = NULL; 10230 hrtime_t timestamp = gethrtime(); 10231 10232 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 10233 10234 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt)); 10235 10236 #ifdef MPTSAS_TEST 10237 if (mptsas_enable_untagged) { 10238 mptsas_test_untagged++; 10239 } 10240 #endif 10241 10242 /* 10243 * Check for commands stuck in active slot 10244 * Account for TM requests, which use the last SMID. 10245 */ 10246 for (i = 0; i <= mpt->m_active->m_n_normal; i++) { 10247 if ((cmd = mpt->m_active->m_slot[i]) != NULL) { 10248 if (cmd->cmd_active_expiration <= timestamp) { 10249 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 10250 /* 10251 * There seems to be a command stuck 10252 * in the active slot. Drain throttle. 10253 */ 10254 mptsas_set_throttle(mpt, 10255 cmd->cmd_tgt_addr, 10256 DRAIN_THROTTLE); 10257 } else if (cmd->cmd_flags & 10258 (CFLAG_PASSTHRU | CFLAG_CONFIG | 10259 CFLAG_FW_DIAG)) { 10260 /* 10261 * passthrough command timeout 10262 */ 10263 cmd->cmd_flags |= (CFLAG_FINISHED | 10264 CFLAG_TIMEOUT); 10265 cv_broadcast(&mpt->m_passthru_cv); 10266 cv_broadcast(&mpt->m_config_cv); 10267 cv_broadcast(&mpt->m_fw_diag_cv); 10268 } 10269 } 10270 } 10271 } 10272 10273 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10274 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10275 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10276 } 10277 10278 for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL; 10279 ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) { 10280 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10281 } 10282 } 10283 10284 /* 10285 * timeout recovery 10286 */ 10287 static void 10288 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt) 10289 { 10290 uint16_t devhdl; 10291 uint64_t sas_wwn; 10292 uint8_t phy; 10293 char wwn_str[MPTSAS_WWN_STRLEN]; 10294 10295 devhdl = ptgt->m_devhdl; 10296 sas_wwn = ptgt->m_addr.mta_wwn; 10297 phy = ptgt->m_phynum; 10298 if (sas_wwn == 0) { 10299 (void) sprintf(wwn_str, "p%x", phy); 10300 } else { 10301 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 10302 } 10303 10304 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl)); 10305 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for " 10306 "target %d %s, enclosure %u", devhdl, wwn_str, 10307 ptgt->m_enclosure); 10308 10309 /* 10310 * Abort all outstanding commands on the device. 10311 */ 10312 NDBG29(("mptsas_cmd_timeout: device reset")); 10313 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) { 10314 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout " 10315 "recovery failed!", devhdl); 10316 } 10317 } 10318 10319 /* 10320 * Device / Hotplug control 10321 */ 10322 static int 10323 mptsas_scsi_quiesce(dev_info_t *dip) 10324 { 10325 mptsas_t *mpt; 10326 scsi_hba_tran_t *tran; 10327 10328 tran = ddi_get_driver_private(dip); 10329 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10330 return (-1); 10331 10332 return (mptsas_quiesce_bus(mpt)); 10333 } 10334 10335 static int 10336 mptsas_scsi_unquiesce(dev_info_t *dip) 10337 { 10338 mptsas_t *mpt; 10339 scsi_hba_tran_t *tran; 10340 10341 tran = ddi_get_driver_private(dip); 10342 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10343 return (-1); 10344 10345 return (mptsas_unquiesce_bus(mpt)); 10346 } 10347 10348 static int 10349 mptsas_quiesce_bus(mptsas_t *mpt) 10350 { 10351 mptsas_target_t *ptgt = NULL; 10352 10353 NDBG28(("mptsas_quiesce_bus")); 10354 mutex_enter(&mpt->m_mutex); 10355 10356 /* Set all the throttles to zero */ 10357 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10358 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10359 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10360 } 10361 10362 /* If there are any outstanding commands in the queue */ 10363 if (mpt->m_ncmds) { 10364 mpt->m_softstate |= MPTSAS_SS_DRAINING; 10365 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10366 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000))); 10367 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) { 10368 /* 10369 * Quiesce has been interrupted 10370 */ 10371 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10372 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10373 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10374 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10375 } 10376 mptsas_restart_hba(mpt); 10377 if (mpt->m_quiesce_timeid != 0) { 10378 timeout_id_t tid = mpt->m_quiesce_timeid; 10379 mpt->m_quiesce_timeid = 0; 10380 mutex_exit(&mpt->m_mutex); 10381 (void) untimeout(tid); 10382 return (-1); 10383 } 10384 mutex_exit(&mpt->m_mutex); 10385 return (-1); 10386 } else { 10387 /* Bus has been quiesced */ 10388 ASSERT(mpt->m_quiesce_timeid == 0); 10389 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10390 mpt->m_softstate |= MPTSAS_SS_QUIESCED; 10391 mutex_exit(&mpt->m_mutex); 10392 return (0); 10393 } 10394 } 10395 /* Bus was not busy - QUIESCED */ 10396 mutex_exit(&mpt->m_mutex); 10397 10398 return (0); 10399 } 10400 10401 static int 10402 mptsas_unquiesce_bus(mptsas_t *mpt) 10403 { 10404 mptsas_target_t *ptgt = NULL; 10405 10406 NDBG28(("mptsas_unquiesce_bus")); 10407 mutex_enter(&mpt->m_mutex); 10408 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED; 10409 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10410 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10411 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10412 } 10413 mptsas_restart_hba(mpt); 10414 mutex_exit(&mpt->m_mutex); 10415 return (0); 10416 } 10417 10418 static void 10419 mptsas_ncmds_checkdrain(void *arg) 10420 { 10421 mptsas_t *mpt = arg; 10422 mptsas_target_t *ptgt = NULL; 10423 10424 mutex_enter(&mpt->m_mutex); 10425 if (mpt->m_softstate & MPTSAS_SS_DRAINING) { 10426 mpt->m_quiesce_timeid = 0; 10427 if (mpt->m_ncmds == 0) { 10428 /* Command queue has been drained */ 10429 cv_signal(&mpt->m_cv); 10430 } else { 10431 /* 10432 * The throttle may have been reset because 10433 * of a SCSI bus reset 10434 */ 10435 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10436 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10437 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10438 } 10439 10440 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10441 mpt, (MPTSAS_QUIESCE_TIMEOUT * 10442 drv_usectohz(1000000))); 10443 } 10444 } 10445 mutex_exit(&mpt->m_mutex); 10446 } 10447 10448 /*ARGSUSED*/ 10449 static void 10450 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 10451 { 10452 int i; 10453 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp; 10454 char buf[128]; 10455 10456 buf[0] = '\0'; 10457 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd, 10458 Tgt(cmd), Lun(cmd))); 10459 (void) sprintf(&buf[0], "\tcdb=["); 10460 for (i = 0; i < (int)cmd->cmd_cdblen; i++) { 10461 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++); 10462 } 10463 (void) sprintf(&buf[strlen(buf)], " ]"); 10464 NDBG25(("?%s\n", buf)); 10465 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n", 10466 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics, 10467 cmd->cmd_pkt->pkt_state)); 10468 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ? 10469 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags)); 10470 } 10471 10472 static void 10473 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10474 pMpi2SGESimple64_t sgep) 10475 { 10476 uint32_t sge_flags; 10477 uint32_t data_size, dataout_size; 10478 ddi_dma_cookie_t data_cookie; 10479 ddi_dma_cookie_t dataout_cookie; 10480 10481 data_size = pt->data_size; 10482 dataout_size = pt->dataout_size; 10483 data_cookie = pt->data_cookie; 10484 dataout_cookie = pt->dataout_cookie; 10485 10486 if (dataout_size) { 10487 sge_flags = dataout_size | 10488 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10489 MPI2_SGE_FLAGS_END_OF_BUFFER | 10490 MPI2_SGE_FLAGS_HOST_TO_IOC | 10491 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10492 MPI2_SGE_FLAGS_SHIFT); 10493 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags); 10494 ddi_put32(acc_hdl, &sgep->Address.Low, 10495 (uint32_t)(dataout_cookie.dmac_laddress & 10496 0xffffffffull)); 10497 ddi_put32(acc_hdl, &sgep->Address.High, 10498 (uint32_t)(dataout_cookie.dmac_laddress 10499 >> 32)); 10500 sgep++; 10501 } 10502 sge_flags = data_size; 10503 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10504 MPI2_SGE_FLAGS_LAST_ELEMENT | 10505 MPI2_SGE_FLAGS_END_OF_BUFFER | 10506 MPI2_SGE_FLAGS_END_OF_LIST | 10507 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10508 MPI2_SGE_FLAGS_SHIFT); 10509 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10510 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 10511 MPI2_SGE_FLAGS_SHIFT); 10512 } else { 10513 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 10514 MPI2_SGE_FLAGS_SHIFT); 10515 } 10516 ddi_put32(acc_hdl, &sgep->FlagsLength, 10517 sge_flags); 10518 ddi_put32(acc_hdl, &sgep->Address.Low, 10519 (uint32_t)(data_cookie.dmac_laddress & 10520 0xffffffffull)); 10521 ddi_put32(acc_hdl, &sgep->Address.High, 10522 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10523 } 10524 10525 static void 10526 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10527 pMpi2IeeeSgeSimple64_t ieeesgep) 10528 { 10529 uint8_t sge_flags; 10530 uint32_t data_size, dataout_size; 10531 ddi_dma_cookie_t data_cookie; 10532 ddi_dma_cookie_t dataout_cookie; 10533 10534 data_size = pt->data_size; 10535 dataout_size = pt->dataout_size; 10536 data_cookie = pt->data_cookie; 10537 dataout_cookie = pt->dataout_cookie; 10538 10539 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 10540 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 10541 if (dataout_size) { 10542 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size); 10543 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10544 (uint32_t)(dataout_cookie.dmac_laddress & 10545 0xffffffffull)); 10546 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10547 (uint32_t)(dataout_cookie.dmac_laddress >> 32)); 10548 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10549 ieeesgep++; 10550 } 10551 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 10552 ddi_put32(acc_hdl, &ieeesgep->Length, data_size); 10553 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10554 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull)); 10555 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10556 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10557 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10558 } 10559 10560 static void 10561 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd) 10562 { 10563 caddr_t memp; 10564 pMPI2RequestHeader_t request_hdrp; 10565 struct scsi_pkt *pkt = cmd->cmd_pkt; 10566 mptsas_pt_request_t *pt = pkt->pkt_ha_private; 10567 uint32_t request_size; 10568 uint32_t i; 10569 uint64_t request_desc = 0; 10570 uint8_t desc_type; 10571 uint16_t SMID; 10572 uint8_t *request, function; 10573 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 10574 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 10575 10576 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 10577 10578 request = pt->request; 10579 request_size = pt->request_size; 10580 10581 SMID = cmd->cmd_slot; 10582 10583 /* 10584 * Store the passthrough message in memory location 10585 * corresponding to our slot number 10586 */ 10587 memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 10588 request_hdrp = (pMPI2RequestHeader_t)memp; 10589 bzero(memp, mpt->m_req_frame_size); 10590 10591 for (i = 0; i < request_size; i++) { 10592 bcopy(request + i, memp + i, 1); 10593 } 10594 10595 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, " 10596 "size=%d, in %d, out %d, SMID %d", request_hdrp->Function, 10597 request_hdrp->MsgFlags, request_size, 10598 pt->data_size, pt->dataout_size, SMID)); 10599 10600 /* 10601 * Add an SGE, even if the length is zero. 10602 */ 10603 if (mpt->m_MPI25 && pt->simple == 0) { 10604 mptsas_passthru_ieee_sge(acc_hdl, pt, 10605 (pMpi2IeeeSgeSimple64_t) 10606 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10607 } else { 10608 mptsas_passthru_sge(acc_hdl, pt, 10609 (pMpi2SGESimple64_t) 10610 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10611 } 10612 10613 function = request_hdrp->Function; 10614 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 10615 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 10616 pMpi2SCSIIORequest_t scsi_io_req; 10617 caddr_t arsbuf; 10618 uint8_t ars_size; 10619 uint32_t ars_dmaaddrlow; 10620 10621 NDBG15(("mptsas_start_passthru: Is SCSI IO Req")); 10622 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp; 10623 10624 if (cmd->cmd_extrqslen != 0) { 10625 /* 10626 * Mapping of the buffer was done in 10627 * mptsas_do_passthru(). 10628 * Calculate the DMA address with the same offset. 10629 */ 10630 arsbuf = cmd->cmd_arq_buf; 10631 ars_size = cmd->cmd_extrqslen; 10632 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10633 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 10634 0xffffffffu; 10635 } else { 10636 arsbuf = mpt->m_req_sense + 10637 (mpt->m_req_sense_size * (SMID-1)); 10638 cmd->cmd_arq_buf = arsbuf; 10639 ars_size = mpt->m_req_sense_size; 10640 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10641 (mpt->m_req_sense_size * (SMID-1))) & 10642 0xffffffffu; 10643 } 10644 bzero(arsbuf, ars_size); 10645 10646 ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size); 10647 ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress, 10648 ars_dmaaddrlow); 10649 10650 /* 10651 * Put SGE for data and data_out buffer at the end of 10652 * scsi_io_request message header.(64 bytes in total) 10653 * Set SGLOffset0 value 10654 */ 10655 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0, 10656 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4); 10657 10658 /* 10659 * Setup descriptor info. RAID passthrough must use the 10660 * default request descriptor which is already set, so if this 10661 * is a SCSI IO request, change the descriptor to SCSI IO. 10662 */ 10663 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 10664 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 10665 request_desc = ((uint64_t)ddi_get16(acc_hdl, 10666 &scsi_io_req->DevHandle) << 48); 10667 } 10668 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 10669 DDI_DMA_SYNC_FORDEV); 10670 } 10671 10672 /* 10673 * We must wait till the message has been completed before 10674 * beginning the next message so we wait for this one to 10675 * finish. 10676 */ 10677 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 10678 request_desc |= (SMID << 16) + desc_type; 10679 cmd->cmd_rfm = NULL; 10680 MPTSAS_START_CMD(mpt, request_desc); 10681 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 10682 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 10683 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10684 } 10685 } 10686 10687 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *); 10688 static mptsas_pre_f mpi_pre_ioc_facts; 10689 static mptsas_pre_f mpi_pre_port_facts; 10690 static mptsas_pre_f mpi_pre_fw_download; 10691 static mptsas_pre_f mpi_pre_fw_25_download; 10692 static mptsas_pre_f mpi_pre_fw_upload; 10693 static mptsas_pre_f mpi_pre_fw_25_upload; 10694 static mptsas_pre_f mpi_pre_sata_passthrough; 10695 static mptsas_pre_f mpi_pre_smp_passthrough; 10696 static mptsas_pre_f mpi_pre_config; 10697 static mptsas_pre_f mpi_pre_sas_io_unit_control; 10698 static mptsas_pre_f mpi_pre_scsi_io_req; 10699 10700 /* 10701 * Prepare the pt for a SAS2 FW_DOWNLOAD request. 10702 */ 10703 static void 10704 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10705 { 10706 pMpi2FWDownloadTCSGE_t tcsge; 10707 pMpi2FWDownloadRequest req; 10708 10709 /* 10710 * If SAS3, call separate function. 10711 */ 10712 if (mpt->m_MPI25) { 10713 mpi_pre_fw_25_download(mpt, pt); 10714 return; 10715 } 10716 10717 /* 10718 * User requests should come in with the Transaction 10719 * context element where the SGL will go. Putting the 10720 * SGL after that seems to work, but don't really know 10721 * why. Other drivers tend to create an extra SGL and 10722 * refer to the TCE through that. 10723 */ 10724 req = (pMpi2FWDownloadRequest)pt->request; 10725 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL; 10726 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10727 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10728 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10729 } 10730 10731 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) + 10732 sizeof (*tcsge); 10733 if (pt->request_size != pt->sgl_offset) { 10734 NDBG15(("mpi_pre_fw_download(): Incorrect req size, " 10735 "0x%x, should be 0x%x, dataoutsz 0x%x", 10736 (int)pt->request_size, (int)pt->sgl_offset, 10737 (int)pt->dataout_size)); 10738 } 10739 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { 10740 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, " 10741 "0x%x, should be 0x%x", pt->data_size, 10742 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY))); 10743 } 10744 } 10745 10746 /* 10747 * Prepare the pt for a SAS3 FW_DOWNLOAD request. 10748 */ 10749 static void 10750 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10751 { 10752 pMpi2FWDownloadTCSGE_t tcsge; 10753 pMpi2FWDownloadRequest req2; 10754 pMpi25FWDownloadRequest req25; 10755 10756 /* 10757 * User requests should come in with the Transaction 10758 * context element where the SGL will go. The new firmware 10759 * Doesn't use TCE and has space in the main request for 10760 * this information. So move to the right place. 10761 */ 10762 req2 = (pMpi2FWDownloadRequest)pt->request; 10763 req25 = (pMpi25FWDownloadRequest)pt->request; 10764 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL; 10765 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10766 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10767 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10768 } 10769 req25->ImageOffset = tcsge->ImageOffset; 10770 req25->ImageSize = tcsge->ImageSize; 10771 10772 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL); 10773 if (pt->request_size != pt->sgl_offset) { 10774 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, " 10775 "0x%x, should be 0x%x, dataoutsz 0x%x", 10776 pt->request_size, pt->sgl_offset, 10777 pt->dataout_size)); 10778 } 10779 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { 10780 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, " 10781 "0x%x, should be 0x%x", pt->data_size, 10782 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10783 } 10784 } 10785 10786 /* 10787 * Prepare the pt for a SAS2 FW_UPLOAD request. 10788 */ 10789 static void 10790 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10791 { 10792 pMpi2FWUploadTCSGE_t tcsge; 10793 pMpi2FWUploadRequest_t req; 10794 10795 /* 10796 * If SAS3, call separate function. 10797 */ 10798 if (mpt->m_MPI25) { 10799 mpi_pre_fw_25_upload(mpt, pt); 10800 return; 10801 } 10802 10803 /* 10804 * User requests should come in with the Transaction 10805 * context element where the SGL will go. Putting the 10806 * SGL after that seems to work, but don't really know 10807 * why. Other drivers tend to create an extra SGL and 10808 * refer to the TCE through that. 10809 */ 10810 req = (pMpi2FWUploadRequest_t)pt->request; 10811 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL; 10812 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10813 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10814 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10815 } 10816 10817 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) + 10818 sizeof (*tcsge); 10819 if (pt->request_size != pt->sgl_offset) { 10820 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, " 10821 "0x%x, should be 0x%x, dataoutsz 0x%x", 10822 pt->request_size, pt->sgl_offset, 10823 pt->dataout_size)); 10824 } 10825 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { 10826 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, " 10827 "0x%x, should be 0x%x", pt->data_size, 10828 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10829 } 10830 } 10831 10832 /* 10833 * Prepare the pt a SAS3 FW_UPLOAD request. 10834 */ 10835 static void 10836 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10837 { 10838 pMpi2FWUploadTCSGE_t tcsge; 10839 pMpi2FWUploadRequest_t req2; 10840 pMpi25FWUploadRequest_t req25; 10841 10842 /* 10843 * User requests should come in with the Transaction 10844 * context element where the SGL will go. The new firmware 10845 * Doesn't use TCE and has space in the main request for 10846 * this information. So move to the right place. 10847 */ 10848 req2 = (pMpi2FWUploadRequest_t)pt->request; 10849 req25 = (pMpi25FWUploadRequest_t)pt->request; 10850 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL; 10851 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10852 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10853 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10854 } 10855 req25->ImageOffset = tcsge->ImageOffset; 10856 req25->ImageSize = tcsge->ImageSize; 10857 10858 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL); 10859 if (pt->request_size != pt->sgl_offset) { 10860 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, " 10861 "0x%x, should be 0x%x, dataoutsz 0x%x", 10862 pt->request_size, pt->sgl_offset, 10863 pt->dataout_size)); 10864 } 10865 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { 10866 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, " 10867 "0x%x, should be 0x%x", pt->data_size, 10868 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10869 } 10870 } 10871 10872 /* 10873 * Prepare the pt for an IOC_FACTS request. 10874 */ 10875 static void 10876 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10877 { 10878 #ifndef __lock_lint 10879 _NOTE(ARGUNUSED(mpt)) 10880 #endif 10881 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) { 10882 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, " 10883 "0x%x, should be 0x%x, dataoutsz 0x%x", 10884 pt->request_size, 10885 (int)sizeof (MPI2_IOC_FACTS_REQUEST), 10886 pt->dataout_size)); 10887 } 10888 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) { 10889 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, " 10890 "0x%x, should be 0x%x", pt->data_size, 10891 (int)sizeof (MPI2_IOC_FACTS_REPLY))); 10892 } 10893 pt->sgl_offset = (uint16_t)pt->request_size; 10894 } 10895 10896 /* 10897 * Prepare the pt for a PORT_FACTS request. 10898 */ 10899 static void 10900 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10901 { 10902 #ifndef __lock_lint 10903 _NOTE(ARGUNUSED(mpt)) 10904 #endif 10905 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) { 10906 NDBG15(("mpi_pre_port_facts(): Incorrect req size, " 10907 "0x%x, should be 0x%x, dataoutsz 0x%x", 10908 pt->request_size, 10909 (int)sizeof (MPI2_PORT_FACTS_REQUEST), 10910 pt->dataout_size)); 10911 } 10912 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) { 10913 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, " 10914 "0x%x, should be 0x%x", pt->data_size, 10915 (int)sizeof (MPI2_PORT_FACTS_REPLY))); 10916 } 10917 pt->sgl_offset = (uint16_t)pt->request_size; 10918 } 10919 10920 /* 10921 * Prepare pt for a SATA_PASSTHROUGH request. 10922 */ 10923 static void 10924 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10925 { 10926 #ifndef __lock_lint 10927 _NOTE(ARGUNUSED(mpt)) 10928 #endif 10929 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL); 10930 if (pt->request_size != pt->sgl_offset) { 10931 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, " 10932 "0x%x, should be 0x%x, dataoutsz 0x%x", 10933 pt->request_size, pt->sgl_offset, 10934 pt->dataout_size)); 10935 } 10936 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) { 10937 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, " 10938 "0x%x, should be 0x%x", pt->data_size, 10939 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY))); 10940 } 10941 } 10942 10943 static void 10944 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10945 { 10946 #ifndef __lock_lint 10947 _NOTE(ARGUNUSED(mpt)) 10948 #endif 10949 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL); 10950 if (pt->request_size != pt->sgl_offset) { 10951 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, " 10952 "0x%x, should be 0x%x, dataoutsz 0x%x", 10953 pt->request_size, pt->sgl_offset, 10954 pt->dataout_size)); 10955 } 10956 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) { 10957 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, " 10958 "0x%x, should be 0x%x", pt->data_size, 10959 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY))); 10960 } 10961 } 10962 10963 /* 10964 * Prepare pt for a CONFIG request. 10965 */ 10966 static void 10967 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt) 10968 { 10969 #ifndef __lock_lint 10970 _NOTE(ARGUNUSED(mpt)) 10971 #endif 10972 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE); 10973 if (pt->request_size != pt->sgl_offset) { 10974 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 10975 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 10976 pt->sgl_offset, pt->dataout_size)); 10977 } 10978 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) { 10979 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 10980 "should be 0x%x", pt->data_size, 10981 (int)sizeof (MPI2_CONFIG_REPLY))); 10982 } 10983 pt->simple = 1; 10984 } 10985 10986 /* 10987 * Prepare pt for a SCSI_IO_REQ request. 10988 */ 10989 static void 10990 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt) 10991 { 10992 #ifndef __lock_lint 10993 _NOTE(ARGUNUSED(mpt)) 10994 #endif 10995 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL); 10996 if (pt->request_size != pt->sgl_offset) { 10997 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 10998 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 10999 pt->sgl_offset, 11000 pt->dataout_size)); 11001 } 11002 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) { 11003 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 11004 "should be 0x%x", pt->data_size, 11005 (int)sizeof (MPI2_SCSI_IO_REPLY))); 11006 } 11007 } 11008 11009 /* 11010 * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request. 11011 */ 11012 static void 11013 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt) 11014 { 11015 #ifndef __lock_lint 11016 _NOTE(ARGUNUSED(mpt)) 11017 #endif 11018 pt->sgl_offset = (uint16_t)pt->request_size; 11019 } 11020 11021 /* 11022 * A set of functions to prepare an mptsas_cmd for the various 11023 * supported requests. 11024 */ 11025 static struct mptsas_func { 11026 U8 Function; 11027 char *Name; 11028 mptsas_pre_f *f_pre; 11029 } mptsas_func_list[] = { 11030 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts }, 11031 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts }, 11032 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download }, 11033 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload }, 11034 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH", 11035 mpi_pre_sata_passthrough }, 11036 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH", 11037 mpi_pre_smp_passthrough}, 11038 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST", 11039 mpi_pre_scsi_io_req}, 11040 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config}, 11041 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL", 11042 mpi_pre_sas_io_unit_control }, 11043 { 0xFF, NULL, NULL } /* list end */ 11044 }; 11045 11046 static void 11047 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt) 11048 { 11049 pMPI2RequestHeader_t hdr; 11050 struct mptsas_func *f; 11051 11052 hdr = (pMPI2RequestHeader_t)pt->request; 11053 11054 for (f = mptsas_func_list; f->f_pre != NULL; f++) { 11055 if (hdr->Function == f->Function) { 11056 f->f_pre(mpt, pt); 11057 NDBG15(("mptsas_prep_sgl_offset: Function %s," 11058 " sgl_offset 0x%x", f->Name, 11059 pt->sgl_offset)); 11060 return; 11061 } 11062 } 11063 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x," 11064 " returning req_size 0x%x for sgl_offset", 11065 hdr->Function, pt->request_size)); 11066 pt->sgl_offset = (uint16_t)pt->request_size; 11067 } 11068 11069 11070 static int 11071 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 11072 uint8_t *data, uint32_t request_size, uint32_t reply_size, 11073 uint32_t data_size, uint32_t direction, uint8_t *dataout, 11074 uint32_t dataout_size, short timeout, int mode) 11075 { 11076 mptsas_pt_request_t pt; 11077 mptsas_dma_alloc_state_t data_dma_state; 11078 mptsas_dma_alloc_state_t dataout_dma_state; 11079 caddr_t memp; 11080 mptsas_cmd_t *cmd = NULL; 11081 struct scsi_pkt *pkt; 11082 uint32_t reply_len = 0, sense_len = 0; 11083 pMPI2RequestHeader_t request_hdrp; 11084 pMPI2RequestHeader_t request_msg; 11085 pMPI2DefaultReply_t reply_msg; 11086 Mpi2SCSIIOReply_t rep_msg; 11087 int rvalue; 11088 int i, status = 0, pt_flags = 0, rv = 0; 11089 uint8_t function; 11090 11091 ASSERT(mutex_owned(&mpt->m_mutex)); 11092 11093 reply_msg = (pMPI2DefaultReply_t)(&rep_msg); 11094 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY)); 11095 request_msg = kmem_zalloc(request_size, KM_SLEEP); 11096 11097 mutex_exit(&mpt->m_mutex); 11098 /* 11099 * copy in the request buffer since it could be used by 11100 * another thread when the pt request into waitq 11101 */ 11102 if (ddi_copyin(request, request_msg, request_size, mode)) { 11103 mutex_enter(&mpt->m_mutex); 11104 status = EFAULT; 11105 mptsas_log(mpt, CE_WARN, "failed to copy request data"); 11106 goto out; 11107 } 11108 NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x", 11109 mode, request_size, request_msg->Function)); 11110 mutex_enter(&mpt->m_mutex); 11111 11112 function = request_msg->Function; 11113 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) { 11114 pMpi2SCSITaskManagementRequest_t task; 11115 task = (pMpi2SCSITaskManagementRequest_t)request_msg; 11116 mptsas_setup_bus_reset_delay(mpt); 11117 rv = mptsas_ioc_task_management(mpt, task->TaskType, 11118 task->DevHandle, (int)task->LUN[1], reply, reply_size, 11119 mode); 11120 11121 if (rv != TRUE) { 11122 status = EIO; 11123 mptsas_log(mpt, CE_WARN, "task management failed"); 11124 } 11125 goto out; 11126 } 11127 11128 if (data_size != 0) { 11129 data_dma_state.size = data_size; 11130 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) { 11131 status = ENOMEM; 11132 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 11133 "resource"); 11134 goto out; 11135 } 11136 pt_flags |= MPTSAS_DATA_ALLOCATED; 11137 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 11138 mutex_exit(&mpt->m_mutex); 11139 for (i = 0; i < data_size; i++) { 11140 if (ddi_copyin(data + i, (uint8_t *) 11141 data_dma_state.memp + i, 1, mode)) { 11142 mutex_enter(&mpt->m_mutex); 11143 status = EFAULT; 11144 mptsas_log(mpt, CE_WARN, "failed to " 11145 "copy read data"); 11146 goto out; 11147 } 11148 } 11149 mutex_enter(&mpt->m_mutex); 11150 } 11151 } else { 11152 bzero(&data_dma_state, sizeof (data_dma_state)); 11153 } 11154 11155 if (dataout_size != 0) { 11156 dataout_dma_state.size = dataout_size; 11157 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) { 11158 status = ENOMEM; 11159 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 11160 "resource"); 11161 goto out; 11162 } 11163 pt_flags |= MPTSAS_DATAOUT_ALLOCATED; 11164 mutex_exit(&mpt->m_mutex); 11165 for (i = 0; i < dataout_size; i++) { 11166 if (ddi_copyin(dataout + i, (uint8_t *) 11167 dataout_dma_state.memp + i, 1, mode)) { 11168 mutex_enter(&mpt->m_mutex); 11169 mptsas_log(mpt, CE_WARN, "failed to copy out" 11170 " data"); 11171 status = EFAULT; 11172 goto out; 11173 } 11174 } 11175 mutex_enter(&mpt->m_mutex); 11176 } else { 11177 bzero(&dataout_dma_state, sizeof (dataout_dma_state)); 11178 } 11179 11180 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11181 status = EAGAIN; 11182 mptsas_log(mpt, CE_NOTE, "event ack command pool is full"); 11183 goto out; 11184 } 11185 pt_flags |= MPTSAS_REQUEST_POOL_CMD; 11186 11187 bzero((caddr_t)cmd, sizeof (*cmd)); 11188 bzero((caddr_t)pkt, scsi_pkt_size()); 11189 bzero((caddr_t)&pt, sizeof (pt)); 11190 11191 cmd->ioc_cmd_slot = (uint32_t)(rvalue); 11192 11193 pt.request = (uint8_t *)request_msg; 11194 pt.direction = direction; 11195 pt.simple = 0; 11196 pt.request_size = request_size; 11197 pt.data_size = data_size; 11198 pt.dataout_size = dataout_size; 11199 pt.data_cookie = data_dma_state.cookie; 11200 pt.dataout_cookie = dataout_dma_state.cookie; 11201 mptsas_prep_sgl_offset(mpt, &pt); 11202 11203 /* 11204 * Form a blank cmd/pkt to store the acknowledgement message 11205 */ 11206 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0]; 11207 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 11208 pkt->pkt_ha_private = (opaque_t)&pt; 11209 pkt->pkt_flags = FLAG_HEAD; 11210 pkt->pkt_time = timeout; 11211 cmd->cmd_pkt = pkt; 11212 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU; 11213 11214 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11215 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11216 uint8_t com, cdb_group_id; 11217 boolean_t ret; 11218 11219 pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32; 11220 com = pkt->pkt_cdbp[0]; 11221 cdb_group_id = CDB_GROUPID(com); 11222 switch (cdb_group_id) { 11223 case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break; 11224 case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break; 11225 case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break; 11226 case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break; 11227 case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break; 11228 default: 11229 NDBG27(("mptsas_do_passthru: SCSI_IO, reserved " 11230 "CDBGROUP 0x%x requested!", cdb_group_id)); 11231 break; 11232 } 11233 11234 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11235 sense_len = reply_size - reply_len; 11236 ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP); 11237 VERIFY(ret == B_TRUE); 11238 } else { 11239 reply_len = reply_size; 11240 sense_len = 0; 11241 } 11242 11243 NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, " 11244 "snslen 0x%x", 11245 (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read", 11246 data_size, dataout_size, reply_len, sense_len)); 11247 11248 /* 11249 * Save the command in a slot 11250 */ 11251 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11252 /* 11253 * Once passthru command get slot, set cmd_flags 11254 * CFLAG_PREPARED. 11255 */ 11256 cmd->cmd_flags |= CFLAG_PREPARED; 11257 mptsas_start_passthru(mpt, cmd); 11258 } else { 11259 mptsas_waitq_add(mpt, cmd); 11260 } 11261 11262 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11263 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex); 11264 } 11265 11266 NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x " 11267 "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm, 11268 pkt->pkt_reason)); 11269 11270 if (cmd->cmd_flags & CFLAG_PREPARED) { 11271 memp = mpt->m_req_frame + (mpt->m_req_frame_size * 11272 cmd->cmd_slot); 11273 request_hdrp = (pMPI2RequestHeader_t)memp; 11274 } 11275 11276 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11277 status = ETIMEDOUT; 11278 mptsas_log(mpt, CE_WARN, "passthrough command timeout"); 11279 pt_flags |= MPTSAS_CMD_TIMEOUT; 11280 goto out; 11281 } 11282 11283 if (cmd->cmd_rfm) { 11284 /* 11285 * cmd_rfm is zero means the command reply is a CONTEXT 11286 * reply and no PCI Write to post the free reply SMFA 11287 * because no reply message frame is used. 11288 * cmd_rfm is non-zero means the reply is a ADDRESS 11289 * reply and reply message frame is used. 11290 */ 11291 pt_flags |= MPTSAS_ADDRESS_REPLY; 11292 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11293 DDI_DMA_SYNC_FORCPU); 11294 reply_msg = (pMPI2DefaultReply_t) 11295 (mpt->m_reply_frame + (cmd->cmd_rfm - 11296 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11297 } 11298 11299 mptsas_fma_check(mpt, cmd); 11300 if (pkt->pkt_reason == CMD_TRAN_ERR) { 11301 status = EAGAIN; 11302 mptsas_log(mpt, CE_WARN, "passthru fma error"); 11303 goto out; 11304 } 11305 if (pkt->pkt_reason == CMD_RESET) { 11306 status = EAGAIN; 11307 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru"); 11308 goto out; 11309 } 11310 11311 if (pkt->pkt_reason == CMD_INCOMPLETE) { 11312 status = EIO; 11313 mptsas_log(mpt, CE_WARN, "passthrough command incomplete"); 11314 goto out; 11315 } 11316 11317 mutex_exit(&mpt->m_mutex); 11318 if (cmd->cmd_flags & CFLAG_PREPARED) { 11319 function = request_hdrp->Function; 11320 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11321 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11322 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11323 sense_len = cmd->cmd_extrqslen ? 11324 min(sense_len, cmd->cmd_extrqslen) : 11325 min(sense_len, cmd->cmd_rqslen); 11326 } else { 11327 reply_len = reply_size; 11328 sense_len = 0; 11329 } 11330 11331 for (i = 0; i < reply_len; i++) { 11332 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1, 11333 mode)) { 11334 mutex_enter(&mpt->m_mutex); 11335 status = EFAULT; 11336 mptsas_log(mpt, CE_WARN, "failed to copy out " 11337 "reply data"); 11338 goto out; 11339 } 11340 } 11341 for (i = 0; i < sense_len; i++) { 11342 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i, 11343 reply + reply_len + i, 1, mode)) { 11344 mutex_enter(&mpt->m_mutex); 11345 status = EFAULT; 11346 mptsas_log(mpt, CE_WARN, "failed to copy out " 11347 "sense data"); 11348 goto out; 11349 } 11350 } 11351 } 11352 11353 if (data_size) { 11354 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) { 11355 (void) ddi_dma_sync(data_dma_state.handle, 0, 0, 11356 DDI_DMA_SYNC_FORCPU); 11357 for (i = 0; i < data_size; i++) { 11358 if (ddi_copyout((uint8_t *)( 11359 data_dma_state.memp + i), data + i, 1, 11360 mode)) { 11361 mutex_enter(&mpt->m_mutex); 11362 status = EFAULT; 11363 mptsas_log(mpt, CE_WARN, "failed to " 11364 "copy out the reply data"); 11365 goto out; 11366 } 11367 } 11368 } 11369 } 11370 mutex_enter(&mpt->m_mutex); 11371 out: 11372 /* 11373 * Put the reply frame back on the free queue, increment the free 11374 * index, and write the new index to the free index register. But only 11375 * if this reply is an ADDRESS reply. 11376 */ 11377 if (pt_flags & MPTSAS_ADDRESS_REPLY) { 11378 ddi_put32(mpt->m_acc_free_queue_hdl, 11379 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11380 cmd->cmd_rfm); 11381 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11382 DDI_DMA_SYNC_FORDEV); 11383 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11384 mpt->m_free_index = 0; 11385 } 11386 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11387 mpt->m_free_index); 11388 } 11389 if (cmd) { 11390 if (cmd->cmd_extrqslen != 0) { 11391 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 11392 cmd->cmd_extrqsidx + 1); 11393 } 11394 if (cmd->cmd_flags & CFLAG_PREPARED) { 11395 mptsas_remove_cmd(mpt, cmd); 11396 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11397 } 11398 } 11399 if (pt_flags & MPTSAS_REQUEST_POOL_CMD) 11400 mptsas_return_to_pool(mpt, cmd); 11401 if (pt_flags & MPTSAS_DATA_ALLOCATED) { 11402 if (mptsas_check_dma_handle(data_dma_state.handle) != 11403 DDI_SUCCESS) { 11404 ddi_fm_service_impact(mpt->m_dip, 11405 DDI_SERVICE_UNAFFECTED); 11406 status = EFAULT; 11407 } 11408 mptsas_dma_free(&data_dma_state); 11409 } 11410 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) { 11411 if (mptsas_check_dma_handle(dataout_dma_state.handle) != 11412 DDI_SUCCESS) { 11413 ddi_fm_service_impact(mpt->m_dip, 11414 DDI_SERVICE_UNAFFECTED); 11415 status = EFAULT; 11416 } 11417 mptsas_dma_free(&dataout_dma_state); 11418 } 11419 if (pt_flags & MPTSAS_CMD_TIMEOUT) { 11420 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 11421 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed"); 11422 } 11423 } 11424 if (request_msg) 11425 kmem_free(request_msg, request_size); 11426 NDBG27(("mptsas_do_passthru: Done status 0x%x", status)); 11427 11428 return (status); 11429 } 11430 11431 static int 11432 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode) 11433 { 11434 /* 11435 * If timeout is 0, set timeout to default of 60 seconds. 11436 */ 11437 if (data->Timeout == 0) { 11438 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT; 11439 } 11440 11441 if (((data->DataSize == 0) && 11442 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) || 11443 ((data->DataSize != 0) && 11444 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) || 11445 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) || 11446 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) && 11447 (data->DataOutSize != 0))))) { 11448 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) { 11449 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ; 11450 } else { 11451 data->DataOutSize = 0; 11452 } 11453 /* 11454 * Send passthru request messages 11455 */ 11456 return (mptsas_do_passthru(mpt, 11457 (uint8_t *)((uintptr_t)data->PtrRequest), 11458 (uint8_t *)((uintptr_t)data->PtrReply), 11459 (uint8_t *)((uintptr_t)data->PtrData), 11460 data->RequestSize, data->ReplySize, 11461 data->DataSize, data->DataDirection, 11462 (uint8_t *)((uintptr_t)data->PtrDataOut), 11463 data->DataOutSize, data->Timeout, mode)); 11464 } else { 11465 return (EINVAL); 11466 } 11467 } 11468 11469 static uint8_t 11470 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id) 11471 { 11472 uint8_t index; 11473 11474 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) { 11475 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) { 11476 return (index); 11477 } 11478 } 11479 11480 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND); 11481 } 11482 11483 static void 11484 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd) 11485 { 11486 pMpi2DiagBufferPostRequest_t pDiag_post_msg; 11487 pMpi2DiagReleaseRequest_t pDiag_release_msg; 11488 struct scsi_pkt *pkt = cmd->cmd_pkt; 11489 mptsas_diag_request_t *diag = pkt->pkt_ha_private; 11490 uint32_t i; 11491 uint64_t request_desc; 11492 11493 ASSERT(mutex_owned(&mpt->m_mutex)); 11494 11495 /* 11496 * Form the diag message depending on the post or release function. 11497 */ 11498 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) { 11499 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t) 11500 (mpt->m_req_frame + (mpt->m_req_frame_size * 11501 cmd->cmd_slot)); 11502 bzero(pDiag_post_msg, mpt->m_req_frame_size); 11503 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function, 11504 diag->function); 11505 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType, 11506 diag->pBuffer->buffer_type); 11507 ddi_put8(mpt->m_acc_req_frame_hdl, 11508 &pDiag_post_msg->ExtendedType, 11509 diag->pBuffer->extended_type); 11510 ddi_put32(mpt->m_acc_req_frame_hdl, 11511 &pDiag_post_msg->BufferLength, 11512 diag->pBuffer->buffer_data.size); 11513 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4); 11514 i++) { 11515 ddi_put32(mpt->m_acc_req_frame_hdl, 11516 &pDiag_post_msg->ProductSpecific[i], 11517 diag->pBuffer->product_specific[i]); 11518 } 11519 ddi_put32(mpt->m_acc_req_frame_hdl, 11520 &pDiag_post_msg->BufferAddress.Low, 11521 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11522 & 0xffffffffull)); 11523 ddi_put32(mpt->m_acc_req_frame_hdl, 11524 &pDiag_post_msg->BufferAddress.High, 11525 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11526 >> 32)); 11527 } else { 11528 pDiag_release_msg = (pMpi2DiagReleaseRequest_t) 11529 (mpt->m_req_frame + (mpt->m_req_frame_size * 11530 cmd->cmd_slot)); 11531 bzero(pDiag_release_msg, mpt->m_req_frame_size); 11532 ddi_put8(mpt->m_acc_req_frame_hdl, 11533 &pDiag_release_msg->Function, diag->function); 11534 ddi_put8(mpt->m_acc_req_frame_hdl, 11535 &pDiag_release_msg->BufferType, 11536 diag->pBuffer->buffer_type); 11537 } 11538 11539 /* 11540 * Send the message 11541 */ 11542 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0, 11543 DDI_DMA_SYNC_FORDEV); 11544 request_desc = (cmd->cmd_slot << 16) + 11545 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 11546 cmd->cmd_rfm = NULL; 11547 MPTSAS_START_CMD(mpt, request_desc); 11548 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 11549 DDI_SUCCESS) || 11550 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 11551 DDI_SUCCESS)) { 11552 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11553 } 11554 } 11555 11556 static int 11557 mptsas_post_fw_diag_buffer(mptsas_t *mpt, 11558 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code) 11559 { 11560 mptsas_diag_request_t diag; 11561 int status, slot_num, post_flags = 0; 11562 mptsas_cmd_t *cmd = NULL; 11563 struct scsi_pkt *pkt; 11564 pMpi2DiagBufferPostReply_t reply; 11565 uint16_t iocstatus; 11566 uint32_t iocloginfo, transfer_length; 11567 11568 /* 11569 * If buffer is not enabled, just leave. 11570 */ 11571 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED; 11572 if (!pBuffer->enabled) { 11573 status = DDI_FAILURE; 11574 goto out; 11575 } 11576 11577 /* 11578 * Clear some flags initially. 11579 */ 11580 pBuffer->force_release = FALSE; 11581 pBuffer->valid_data = FALSE; 11582 pBuffer->owned_by_firmware = FALSE; 11583 11584 /* 11585 * Get a cmd buffer from the cmd buffer pool 11586 */ 11587 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11588 status = DDI_FAILURE; 11589 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag"); 11590 goto out; 11591 } 11592 post_flags |= MPTSAS_REQUEST_POOL_CMD; 11593 11594 bzero((caddr_t)cmd, sizeof (*cmd)); 11595 bzero((caddr_t)pkt, scsi_pkt_size()); 11596 11597 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11598 11599 diag.pBuffer = pBuffer; 11600 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST; 11601 11602 /* 11603 * Form a blank cmd/pkt to store the acknowledgement message 11604 */ 11605 pkt->pkt_ha_private = (opaque_t)&diag; 11606 pkt->pkt_flags = FLAG_HEAD; 11607 pkt->pkt_time = 60; 11608 cmd->cmd_pkt = pkt; 11609 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11610 11611 /* 11612 * Save the command in a slot 11613 */ 11614 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11615 /* 11616 * Once passthru command get slot, set cmd_flags 11617 * CFLAG_PREPARED. 11618 */ 11619 cmd->cmd_flags |= CFLAG_PREPARED; 11620 mptsas_start_diag(mpt, cmd); 11621 } else { 11622 mptsas_waitq_add(mpt, cmd); 11623 } 11624 11625 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11626 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11627 } 11628 11629 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11630 status = DDI_FAILURE; 11631 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout"); 11632 goto out; 11633 } 11634 11635 /* 11636 * cmd_rfm points to the reply message if a reply was given. Check the 11637 * IOCStatus to make sure everything went OK with the FW diag request 11638 * and set buffer flags. 11639 */ 11640 if (cmd->cmd_rfm) { 11641 post_flags |= MPTSAS_ADDRESS_REPLY; 11642 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11643 DDI_DMA_SYNC_FORCPU); 11644 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame + 11645 (cmd->cmd_rfm - 11646 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11647 11648 /* 11649 * Get the reply message data 11650 */ 11651 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11652 &reply->IOCStatus); 11653 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11654 &reply->IOCLogInfo); 11655 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl, 11656 &reply->TransferLength); 11657 11658 /* 11659 * If post failed quit. 11660 */ 11661 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) { 11662 status = DDI_FAILURE; 11663 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, " 11664 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus, 11665 iocloginfo, transfer_length)); 11666 goto out; 11667 } 11668 11669 /* 11670 * Post was successful. 11671 */ 11672 pBuffer->valid_data = TRUE; 11673 pBuffer->owned_by_firmware = TRUE; 11674 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11675 status = DDI_SUCCESS; 11676 } 11677 11678 out: 11679 /* 11680 * Put the reply frame back on the free queue, increment the free 11681 * index, and write the new index to the free index register. But only 11682 * if this reply is an ADDRESS reply. 11683 */ 11684 if (post_flags & MPTSAS_ADDRESS_REPLY) { 11685 ddi_put32(mpt->m_acc_free_queue_hdl, 11686 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11687 cmd->cmd_rfm); 11688 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11689 DDI_DMA_SYNC_FORDEV); 11690 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11691 mpt->m_free_index = 0; 11692 } 11693 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11694 mpt->m_free_index); 11695 } 11696 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11697 mptsas_remove_cmd(mpt, cmd); 11698 post_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11699 } 11700 if (post_flags & MPTSAS_REQUEST_POOL_CMD) { 11701 mptsas_return_to_pool(mpt, cmd); 11702 } 11703 11704 return (status); 11705 } 11706 11707 static int 11708 mptsas_release_fw_diag_buffer(mptsas_t *mpt, 11709 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 11710 uint32_t diag_type) 11711 { 11712 mptsas_diag_request_t diag; 11713 int status, slot_num, rel_flags = 0; 11714 mptsas_cmd_t *cmd = NULL; 11715 struct scsi_pkt *pkt; 11716 pMpi2DiagReleaseReply_t reply; 11717 uint16_t iocstatus; 11718 uint32_t iocloginfo; 11719 11720 /* 11721 * If buffer is not enabled, just leave. 11722 */ 11723 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED; 11724 if (!pBuffer->enabled) { 11725 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported " 11726 "by the IOC"); 11727 status = DDI_FAILURE; 11728 goto out; 11729 } 11730 11731 /* 11732 * Clear some flags initially. 11733 */ 11734 pBuffer->force_release = FALSE; 11735 pBuffer->valid_data = FALSE; 11736 pBuffer->owned_by_firmware = FALSE; 11737 11738 /* 11739 * Get a cmd buffer from the cmd buffer pool 11740 */ 11741 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11742 status = DDI_FAILURE; 11743 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW " 11744 "Diag"); 11745 goto out; 11746 } 11747 rel_flags |= MPTSAS_REQUEST_POOL_CMD; 11748 11749 bzero((caddr_t)cmd, sizeof (*cmd)); 11750 bzero((caddr_t)pkt, scsi_pkt_size()); 11751 11752 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11753 11754 diag.pBuffer = pBuffer; 11755 diag.function = MPI2_FUNCTION_DIAG_RELEASE; 11756 11757 /* 11758 * Form a blank cmd/pkt to store the acknowledgement message 11759 */ 11760 pkt->pkt_ha_private = (opaque_t)&diag; 11761 pkt->pkt_flags = FLAG_HEAD; 11762 pkt->pkt_time = 60; 11763 cmd->cmd_pkt = pkt; 11764 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11765 11766 /* 11767 * Save the command in a slot 11768 */ 11769 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11770 /* 11771 * Once passthru command get slot, set cmd_flags 11772 * CFLAG_PREPARED. 11773 */ 11774 cmd->cmd_flags |= CFLAG_PREPARED; 11775 mptsas_start_diag(mpt, cmd); 11776 } else { 11777 mptsas_waitq_add(mpt, cmd); 11778 } 11779 11780 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11781 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11782 } 11783 11784 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11785 status = DDI_FAILURE; 11786 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout"); 11787 goto out; 11788 } 11789 11790 /* 11791 * cmd_rfm points to the reply message if a reply was given. Check the 11792 * IOCStatus to make sure everything went OK with the FW diag request 11793 * and set buffer flags. 11794 */ 11795 if (cmd->cmd_rfm) { 11796 rel_flags |= MPTSAS_ADDRESS_REPLY; 11797 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11798 DDI_DMA_SYNC_FORCPU); 11799 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame + 11800 (cmd->cmd_rfm - 11801 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11802 11803 /* 11804 * Get the reply message data 11805 */ 11806 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11807 &reply->IOCStatus); 11808 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11809 &reply->IOCLogInfo); 11810 11811 /* 11812 * If release failed quit. 11813 */ 11814 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) || 11815 pBuffer->owned_by_firmware) { 11816 status = DDI_FAILURE; 11817 NDBG13(("release FW Diag Buffer failed: " 11818 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, 11819 iocloginfo)); 11820 goto out; 11821 } 11822 11823 /* 11824 * Release was successful. 11825 */ 11826 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11827 status = DDI_SUCCESS; 11828 11829 /* 11830 * If this was for an UNREGISTER diag type command, clear the 11831 * unique ID. 11832 */ 11833 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) { 11834 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 11835 } 11836 } 11837 11838 out: 11839 /* 11840 * Put the reply frame back on the free queue, increment the free 11841 * index, and write the new index to the free index register. But only 11842 * if this reply is an ADDRESS reply. 11843 */ 11844 if (rel_flags & MPTSAS_ADDRESS_REPLY) { 11845 ddi_put32(mpt->m_acc_free_queue_hdl, 11846 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11847 cmd->cmd_rfm); 11848 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11849 DDI_DMA_SYNC_FORDEV); 11850 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11851 mpt->m_free_index = 0; 11852 } 11853 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11854 mpt->m_free_index); 11855 } 11856 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11857 mptsas_remove_cmd(mpt, cmd); 11858 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11859 } 11860 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) { 11861 mptsas_return_to_pool(mpt, cmd); 11862 } 11863 11864 return (status); 11865 } 11866 11867 static int 11868 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register, 11869 uint32_t *return_code) 11870 { 11871 mptsas_fw_diagnostic_buffer_t *pBuffer; 11872 uint8_t extended_type, buffer_type, i; 11873 uint32_t buffer_size; 11874 uint32_t unique_id; 11875 int status; 11876 11877 ASSERT(mutex_owned(&mpt->m_mutex)); 11878 11879 extended_type = diag_register->ExtendedType; 11880 buffer_type = diag_register->BufferType; 11881 buffer_size = diag_register->RequestedBufferSize; 11882 unique_id = diag_register->UniqueId; 11883 11884 /* 11885 * Check for valid buffer type 11886 */ 11887 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) { 11888 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11889 return (DDI_FAILURE); 11890 } 11891 11892 /* 11893 * Get the current buffer and look up the unique ID. The unique ID 11894 * should not be found. If it is, the ID is already in use. 11895 */ 11896 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11897 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type]; 11898 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11899 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11900 return (DDI_FAILURE); 11901 } 11902 11903 /* 11904 * The buffer's unique ID should not be registered yet, and the given 11905 * unique ID cannot be 0. 11906 */ 11907 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) || 11908 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11909 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11910 return (DDI_FAILURE); 11911 } 11912 11913 /* 11914 * If this buffer is already posted as immediate, just change owner. 11915 */ 11916 if (pBuffer->immediate && pBuffer->owned_by_firmware && 11917 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11918 pBuffer->immediate = FALSE; 11919 pBuffer->unique_id = unique_id; 11920 return (DDI_SUCCESS); 11921 } 11922 11923 /* 11924 * Post a new buffer after checking if it's enabled. The DMA buffer 11925 * that is allocated will be contiguous (sgl_len = 1). 11926 */ 11927 if (!pBuffer->enabled) { 11928 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11929 return (DDI_FAILURE); 11930 } 11931 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t)); 11932 pBuffer->buffer_data.size = buffer_size; 11933 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) { 11934 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for " 11935 "diag buffer: size = %d bytes", buffer_size); 11936 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11937 return (DDI_FAILURE); 11938 } 11939 11940 /* 11941 * Copy the given info to the diag buffer and post the buffer. 11942 */ 11943 pBuffer->buffer_type = buffer_type; 11944 pBuffer->immediate = FALSE; 11945 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) { 11946 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4); 11947 i++) { 11948 pBuffer->product_specific[i] = 11949 diag_register->ProductSpecific[i]; 11950 } 11951 } 11952 pBuffer->extended_type = extended_type; 11953 pBuffer->unique_id = unique_id; 11954 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code); 11955 11956 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 11957 DDI_SUCCESS) { 11958 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in " 11959 "mptsas_diag_register."); 11960 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11961 status = DDI_FAILURE; 11962 } 11963 11964 /* 11965 * In case there was a failure, free the DMA buffer. 11966 */ 11967 if (status == DDI_FAILURE) { 11968 mptsas_dma_free(&pBuffer->buffer_data); 11969 } 11970 11971 return (status); 11972 } 11973 11974 static int 11975 mptsas_diag_unregister(mptsas_t *mpt, 11976 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code) 11977 { 11978 mptsas_fw_diagnostic_buffer_t *pBuffer; 11979 uint8_t i; 11980 uint32_t unique_id; 11981 int status; 11982 11983 ASSERT(mutex_owned(&mpt->m_mutex)); 11984 11985 unique_id = diag_unregister->UniqueId; 11986 11987 /* 11988 * Get the current buffer and look up the unique ID. The unique ID 11989 * should be there. 11990 */ 11991 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11992 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11993 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11994 return (DDI_FAILURE); 11995 } 11996 11997 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11998 11999 /* 12000 * Try to release the buffer from FW before freeing it. If release 12001 * fails, don't free the DMA buffer in case FW tries to access it 12002 * later. If buffer is not owned by firmware, can't release it. 12003 */ 12004 if (!pBuffer->owned_by_firmware) { 12005 status = DDI_SUCCESS; 12006 } else { 12007 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, 12008 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER); 12009 } 12010 12011 /* 12012 * At this point, return the current status no matter what happens with 12013 * the DMA buffer. 12014 */ 12015 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 12016 if (status == DDI_SUCCESS) { 12017 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 12018 DDI_SUCCESS) { 12019 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed " 12020 "in mptsas_diag_unregister."); 12021 ddi_fm_service_impact(mpt->m_dip, 12022 DDI_SERVICE_UNAFFECTED); 12023 } 12024 mptsas_dma_free(&pBuffer->buffer_data); 12025 } 12026 12027 return (status); 12028 } 12029 12030 static int 12031 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 12032 uint32_t *return_code) 12033 { 12034 mptsas_fw_diagnostic_buffer_t *pBuffer; 12035 uint8_t i; 12036 uint32_t unique_id; 12037 12038 ASSERT(mutex_owned(&mpt->m_mutex)); 12039 12040 unique_id = diag_query->UniqueId; 12041 12042 /* 12043 * If ID is valid, query on ID. 12044 * If ID is invalid, query on buffer type. 12045 */ 12046 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) { 12047 i = diag_query->BufferType; 12048 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) { 12049 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12050 return (DDI_FAILURE); 12051 } 12052 } else { 12053 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12054 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12055 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12056 return (DDI_FAILURE); 12057 } 12058 } 12059 12060 /* 12061 * Fill query structure with the diag buffer info. 12062 */ 12063 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12064 diag_query->BufferType = pBuffer->buffer_type; 12065 diag_query->ExtendedType = pBuffer->extended_type; 12066 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) { 12067 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4); 12068 i++) { 12069 diag_query->ProductSpecific[i] = 12070 pBuffer->product_specific[i]; 12071 } 12072 } 12073 diag_query->TotalBufferSize = pBuffer->buffer_data.size; 12074 diag_query->DriverAddedBufferSize = 0; 12075 diag_query->UniqueId = pBuffer->unique_id; 12076 diag_query->ApplicationFlags = 0; 12077 diag_query->DiagnosticFlags = 0; 12078 12079 /* 12080 * Set/Clear application flags 12081 */ 12082 if (pBuffer->immediate) { 12083 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED; 12084 } else { 12085 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED; 12086 } 12087 if (pBuffer->valid_data || pBuffer->owned_by_firmware) { 12088 diag_query->ApplicationFlags |= 12089 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 12090 } else { 12091 diag_query->ApplicationFlags &= 12092 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 12093 } 12094 if (pBuffer->owned_by_firmware) { 12095 diag_query->ApplicationFlags |= 12096 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 12097 } else { 12098 diag_query->ApplicationFlags &= 12099 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 12100 } 12101 12102 return (DDI_SUCCESS); 12103 } 12104 12105 static int 12106 mptsas_diag_read_buffer(mptsas_t *mpt, 12107 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 12108 uint32_t *return_code, int ioctl_mode) 12109 { 12110 mptsas_fw_diagnostic_buffer_t *pBuffer; 12111 uint8_t i, *pData; 12112 uint32_t unique_id, byte; 12113 int status; 12114 12115 ASSERT(mutex_owned(&mpt->m_mutex)); 12116 12117 unique_id = diag_read_buffer->UniqueId; 12118 12119 /* 12120 * Get the current buffer and look up the unique ID. The unique ID 12121 * should be there. 12122 */ 12123 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12124 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12125 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12126 return (DDI_FAILURE); 12127 } 12128 12129 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12130 12131 /* 12132 * Make sure requested read is within limits 12133 */ 12134 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead > 12135 pBuffer->buffer_data.size) { 12136 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12137 return (DDI_FAILURE); 12138 } 12139 12140 /* 12141 * Copy the requested data from DMA to the diag_read_buffer. The DMA 12142 * buffer that was allocated is one contiguous buffer. 12143 */ 12144 pData = (uint8_t *)(pBuffer->buffer_data.memp + 12145 diag_read_buffer->StartingOffset); 12146 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0, 12147 DDI_DMA_SYNC_FORCPU); 12148 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) { 12149 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode) 12150 != 0) { 12151 return (DDI_FAILURE); 12152 } 12153 } 12154 diag_read_buffer->Status = 0; 12155 12156 /* 12157 * Set or clear the Force Release flag. 12158 */ 12159 if (pBuffer->force_release) { 12160 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 12161 } else { 12162 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 12163 } 12164 12165 /* 12166 * If buffer is to be reregistered, make sure it's not already owned by 12167 * firmware first. 12168 */ 12169 status = DDI_SUCCESS; 12170 if (!pBuffer->owned_by_firmware) { 12171 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) { 12172 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, 12173 return_code); 12174 } 12175 } 12176 12177 return (status); 12178 } 12179 12180 static int 12181 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release, 12182 uint32_t *return_code) 12183 { 12184 mptsas_fw_diagnostic_buffer_t *pBuffer; 12185 uint8_t i; 12186 uint32_t unique_id; 12187 int status; 12188 12189 ASSERT(mutex_owned(&mpt->m_mutex)); 12190 12191 unique_id = diag_release->UniqueId; 12192 12193 /* 12194 * Get the current buffer and look up the unique ID. The unique ID 12195 * should be there. 12196 */ 12197 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12198 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12199 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12200 return (DDI_FAILURE); 12201 } 12202 12203 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12204 12205 /* 12206 * If buffer is not owned by firmware, it's already been released. 12207 */ 12208 if (!pBuffer->owned_by_firmware) { 12209 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED; 12210 return (DDI_FAILURE); 12211 } 12212 12213 /* 12214 * Release the buffer. 12215 */ 12216 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code, 12217 MPTSAS_FW_DIAG_TYPE_RELEASE); 12218 return (status); 12219 } 12220 12221 static int 12222 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action, 12223 uint32_t length, uint32_t *return_code, int ioctl_mode) 12224 { 12225 mptsas_fw_diag_register_t diag_register; 12226 mptsas_fw_diag_unregister_t diag_unregister; 12227 mptsas_fw_diag_query_t diag_query; 12228 mptsas_diag_read_buffer_t diag_read_buffer; 12229 mptsas_fw_diag_release_t diag_release; 12230 int status = DDI_SUCCESS; 12231 uint32_t original_return_code, read_buf_len; 12232 12233 ASSERT(mutex_owned(&mpt->m_mutex)); 12234 12235 original_return_code = *return_code; 12236 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 12237 12238 switch (action) { 12239 case MPTSAS_FW_DIAG_TYPE_REGISTER: 12240 if (!length) { 12241 *return_code = 12242 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12243 status = DDI_FAILURE; 12244 break; 12245 } 12246 if (ddi_copyin(diag_action, &diag_register, 12247 sizeof (diag_register), ioctl_mode) != 0) { 12248 return (DDI_FAILURE); 12249 } 12250 status = mptsas_diag_register(mpt, &diag_register, 12251 return_code); 12252 break; 12253 12254 case MPTSAS_FW_DIAG_TYPE_UNREGISTER: 12255 if (length < sizeof (diag_unregister)) { 12256 *return_code = 12257 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12258 status = DDI_FAILURE; 12259 break; 12260 } 12261 if (ddi_copyin(diag_action, &diag_unregister, 12262 sizeof (diag_unregister), ioctl_mode) != 0) { 12263 return (DDI_FAILURE); 12264 } 12265 status = mptsas_diag_unregister(mpt, &diag_unregister, 12266 return_code); 12267 break; 12268 12269 case MPTSAS_FW_DIAG_TYPE_QUERY: 12270 if (length < sizeof (diag_query)) { 12271 *return_code = 12272 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12273 status = DDI_FAILURE; 12274 break; 12275 } 12276 if (ddi_copyin(diag_action, &diag_query, 12277 sizeof (diag_query), ioctl_mode) != 0) { 12278 return (DDI_FAILURE); 12279 } 12280 status = mptsas_diag_query(mpt, &diag_query, 12281 return_code); 12282 if (status == DDI_SUCCESS) { 12283 if (ddi_copyout(&diag_query, diag_action, 12284 sizeof (diag_query), ioctl_mode) != 0) { 12285 return (DDI_FAILURE); 12286 } 12287 } 12288 break; 12289 12290 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER: 12291 if (ddi_copyin(diag_action, &diag_read_buffer, 12292 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) { 12293 return (DDI_FAILURE); 12294 } 12295 read_buf_len = sizeof (diag_read_buffer) - 12296 sizeof (diag_read_buffer.DataBuffer) + 12297 diag_read_buffer.BytesToRead; 12298 if (length < read_buf_len) { 12299 *return_code = 12300 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12301 status = DDI_FAILURE; 12302 break; 12303 } 12304 status = mptsas_diag_read_buffer(mpt, 12305 &diag_read_buffer, diag_action + 12306 sizeof (diag_read_buffer) - 4, return_code, 12307 ioctl_mode); 12308 if (status == DDI_SUCCESS) { 12309 if (ddi_copyout(&diag_read_buffer, diag_action, 12310 sizeof (diag_read_buffer) - 4, ioctl_mode) 12311 != 0) { 12312 return (DDI_FAILURE); 12313 } 12314 } 12315 break; 12316 12317 case MPTSAS_FW_DIAG_TYPE_RELEASE: 12318 if (length < sizeof (diag_release)) { 12319 *return_code = 12320 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12321 status = DDI_FAILURE; 12322 break; 12323 } 12324 if (ddi_copyin(diag_action, &diag_release, 12325 sizeof (diag_release), ioctl_mode) != 0) { 12326 return (DDI_FAILURE); 12327 } 12328 status = mptsas_diag_release(mpt, &diag_release, 12329 return_code); 12330 break; 12331 12332 default: 12333 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12334 status = DDI_FAILURE; 12335 break; 12336 } 12337 12338 if ((status == DDI_FAILURE) && 12339 (original_return_code == MPTSAS_FW_DIAG_NEW) && 12340 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) { 12341 status = DDI_SUCCESS; 12342 } 12343 12344 return (status); 12345 } 12346 12347 static int 12348 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode) 12349 { 12350 int status; 12351 mptsas_diag_action_t driver_data; 12352 12353 ASSERT(mutex_owned(&mpt->m_mutex)); 12354 12355 /* 12356 * Copy the user data to a driver data buffer. 12357 */ 12358 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t), 12359 mode) == 0) { 12360 /* 12361 * Send diag action request if Action is valid 12362 */ 12363 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER || 12364 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER || 12365 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY || 12366 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER || 12367 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) { 12368 status = mptsas_do_diag_action(mpt, driver_data.Action, 12369 (void *)(uintptr_t)driver_data.PtrDiagAction, 12370 driver_data.Length, &driver_data.ReturnCode, 12371 mode); 12372 if (status == DDI_SUCCESS) { 12373 if (ddi_copyout(&driver_data.ReturnCode, 12374 &user_data->ReturnCode, 12375 sizeof (user_data->ReturnCode), mode) 12376 != 0) { 12377 status = EFAULT; 12378 } else { 12379 status = 0; 12380 } 12381 } else { 12382 status = EIO; 12383 } 12384 } else { 12385 status = EINVAL; 12386 } 12387 } else { 12388 status = EFAULT; 12389 } 12390 12391 return (status); 12392 } 12393 12394 /* 12395 * This routine handles the "event query" ioctl. 12396 */ 12397 static int 12398 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode, 12399 int *rval) 12400 { 12401 int status; 12402 mptsas_event_query_t driverdata; 12403 uint8_t i; 12404 12405 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE; 12406 12407 mutex_enter(&mpt->m_mutex); 12408 for (i = 0; i < 4; i++) { 12409 driverdata.Types[i] = mpt->m_event_mask[i]; 12410 } 12411 mutex_exit(&mpt->m_mutex); 12412 12413 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) { 12414 status = EFAULT; 12415 } else { 12416 *rval = MPTIOCTL_STATUS_GOOD; 12417 status = 0; 12418 } 12419 12420 return (status); 12421 } 12422 12423 /* 12424 * This routine handles the "event enable" ioctl. 12425 */ 12426 static int 12427 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode, 12428 int *rval) 12429 { 12430 int status; 12431 mptsas_event_enable_t driverdata; 12432 uint8_t i; 12433 12434 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12435 mutex_enter(&mpt->m_mutex); 12436 for (i = 0; i < 4; i++) { 12437 mpt->m_event_mask[i] = driverdata.Types[i]; 12438 } 12439 mutex_exit(&mpt->m_mutex); 12440 12441 *rval = MPTIOCTL_STATUS_GOOD; 12442 status = 0; 12443 } else { 12444 status = EFAULT; 12445 } 12446 return (status); 12447 } 12448 12449 /* 12450 * This routine handles the "event report" ioctl. 12451 */ 12452 static int 12453 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode, 12454 int *rval) 12455 { 12456 int status; 12457 mptsas_event_report_t driverdata; 12458 12459 mutex_enter(&mpt->m_mutex); 12460 12461 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size), 12462 mode) == 0) { 12463 if (driverdata.Size >= sizeof (mpt->m_events)) { 12464 if (ddi_copyout(mpt->m_events, data->Events, 12465 sizeof (mpt->m_events), mode) != 0) { 12466 status = EFAULT; 12467 } else { 12468 if (driverdata.Size > sizeof (mpt->m_events)) { 12469 driverdata.Size = 12470 sizeof (mpt->m_events); 12471 if (ddi_copyout(&driverdata.Size, 12472 &data->Size, 12473 sizeof (driverdata.Size), 12474 mode) != 0) { 12475 status = EFAULT; 12476 } else { 12477 *rval = MPTIOCTL_STATUS_GOOD; 12478 status = 0; 12479 } 12480 } else { 12481 *rval = MPTIOCTL_STATUS_GOOD; 12482 status = 0; 12483 } 12484 } 12485 } else { 12486 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 12487 status = 0; 12488 } 12489 } else { 12490 status = EFAULT; 12491 } 12492 12493 mutex_exit(&mpt->m_mutex); 12494 return (status); 12495 } 12496 12497 static void 12498 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12499 { 12500 int *reg_data; 12501 uint_t reglen; 12502 12503 /* 12504 * Lookup the 'reg' property and extract the other data 12505 */ 12506 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12507 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12508 DDI_PROP_SUCCESS) { 12509 /* 12510 * Extract the PCI data from the 'reg' property first DWORD. 12511 * The entry looks like the following: 12512 * First DWORD: 12513 * Bits 0 - 7 8-bit Register number 12514 * Bits 8 - 10 3-bit Function number 12515 * Bits 11 - 15 5-bit Device number 12516 * Bits 16 - 23 8-bit Bus number 12517 * Bits 24 - 25 2-bit Address Space type identifier 12518 * 12519 */ 12520 adapter_data->PciInformation.u.bits.BusNumber = 12521 (reg_data[0] & 0x00FF0000) >> 16; 12522 adapter_data->PciInformation.u.bits.DeviceNumber = 12523 (reg_data[0] & 0x0000F800) >> 11; 12524 adapter_data->PciInformation.u.bits.FunctionNumber = 12525 (reg_data[0] & 0x00000700) >> 8; 12526 ddi_prop_free((void *)reg_data); 12527 } else { 12528 /* 12529 * If we can't determine the PCI data then we fill in FF's for 12530 * the data to indicate this. 12531 */ 12532 adapter_data->PCIDeviceHwId = 0xFFFFFFFF; 12533 adapter_data->MpiPortNumber = 0xFFFFFFFF; 12534 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF; 12535 } 12536 12537 /* 12538 * Saved in the mpt->m_fwversion 12539 */ 12540 adapter_data->MpiFirmwareVersion = mpt->m_fwversion; 12541 } 12542 12543 static void 12544 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12545 { 12546 char *driver_verstr = MPTSAS_MOD_STRING; 12547 12548 mptsas_lookup_pci_data(mpt, adapter_data); 12549 adapter_data->AdapterType = mpt->m_MPI25 ? 12550 MPTIOCTL_ADAPTER_TYPE_SAS3 : 12551 MPTIOCTL_ADAPTER_TYPE_SAS2; 12552 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid; 12553 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid; 12554 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid; 12555 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid; 12556 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr); 12557 adapter_data->BiosVersion = 0; 12558 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion); 12559 } 12560 12561 static void 12562 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info) 12563 { 12564 int *reg_data, i; 12565 uint_t reglen; 12566 12567 /* 12568 * Lookup the 'reg' property and extract the other data 12569 */ 12570 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12571 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12572 DDI_PROP_SUCCESS) { 12573 /* 12574 * Extract the PCI data from the 'reg' property first DWORD. 12575 * The entry looks like the following: 12576 * First DWORD: 12577 * Bits 8 - 10 3-bit Function number 12578 * Bits 11 - 15 5-bit Device number 12579 * Bits 16 - 23 8-bit Bus number 12580 */ 12581 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16; 12582 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11; 12583 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8; 12584 ddi_prop_free((void *)reg_data); 12585 } else { 12586 /* 12587 * If we can't determine the PCI info then we fill in FF's for 12588 * the data to indicate this. 12589 */ 12590 pci_info->BusNumber = 0xFFFFFFFF; 12591 pci_info->DeviceNumber = 0xFF; 12592 pci_info->FunctionNumber = 0xFF; 12593 } 12594 12595 /* 12596 * Now get the interrupt vector and the pci header. The vector can 12597 * only be 0 right now. The header is the first 256 bytes of config 12598 * space. 12599 */ 12600 pci_info->InterruptVector = 0; 12601 for (i = 0; i < sizeof (pci_info->PciHeader); i++) { 12602 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle, 12603 i); 12604 } 12605 } 12606 12607 static int 12608 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode) 12609 { 12610 int status = 0; 12611 mptsas_reg_access_t driverdata; 12612 12613 mutex_enter(&mpt->m_mutex); 12614 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12615 switch (driverdata.Command) { 12616 /* 12617 * IO access is not supported. 12618 */ 12619 case REG_IO_READ: 12620 case REG_IO_WRITE: 12621 mptsas_log(mpt, CE_WARN, "IO access is not " 12622 "supported. Use memory access."); 12623 status = EINVAL; 12624 break; 12625 12626 case REG_MEM_READ: 12627 driverdata.RegData = ddi_get32(mpt->m_datap, 12628 (uint32_t *)(void *)mpt->m_reg + 12629 driverdata.RegOffset); 12630 if (ddi_copyout(&driverdata.RegData, 12631 &data->RegData, 12632 sizeof (driverdata.RegData), mode) != 0) { 12633 mptsas_log(mpt, CE_WARN, "Register " 12634 "Read Failed"); 12635 status = EFAULT; 12636 } 12637 break; 12638 12639 case REG_MEM_WRITE: 12640 ddi_put32(mpt->m_datap, 12641 (uint32_t *)(void *)mpt->m_reg + 12642 driverdata.RegOffset, 12643 driverdata.RegData); 12644 break; 12645 12646 default: 12647 status = EINVAL; 12648 break; 12649 } 12650 } else { 12651 status = EFAULT; 12652 } 12653 12654 mutex_exit(&mpt->m_mutex); 12655 return (status); 12656 } 12657 12658 static int 12659 led_control(mptsas_t *mpt, intptr_t data, int mode) 12660 { 12661 int ret = 0; 12662 mptsas_led_control_t lc; 12663 mptsas_target_t *ptgt; 12664 12665 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) { 12666 return (EFAULT); 12667 } 12668 12669 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET && 12670 lc.Command != MPTSAS_LEDCTL_FLAG_GET) || 12671 lc.Led < MPTSAS_LEDCTL_LED_MIN || 12672 lc.Led > MPTSAS_LEDCTL_LED_MAX || 12673 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 && 12674 lc.LedStatus != 1)) { 12675 return (EINVAL); 12676 } 12677 12678 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) || 12679 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0)) 12680 return (EACCES); 12681 12682 /* Locate the target we're interrogating... */ 12683 mutex_enter(&mpt->m_mutex); 12684 ptgt = refhash_linear_search(mpt->m_targets, 12685 mptsas_target_eval_slot, &lc); 12686 if (ptgt == NULL) { 12687 /* We could not find a target for that enclosure/slot. */ 12688 mutex_exit(&mpt->m_mutex); 12689 return (ENOENT); 12690 } 12691 12692 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) { 12693 /* Update our internal LED state. */ 12694 ptgt->m_led_status &= ~(1 << (lc.Led - 1)); 12695 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1); 12696 12697 /* Flush it to the controller. */ 12698 ret = mptsas_flush_led_status(mpt, ptgt); 12699 mutex_exit(&mpt->m_mutex); 12700 return (ret); 12701 } 12702 12703 /* Return our internal LED state. */ 12704 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1; 12705 mutex_exit(&mpt->m_mutex); 12706 12707 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) { 12708 return (EFAULT); 12709 } 12710 12711 return (0); 12712 } 12713 12714 static int 12715 get_disk_info(mptsas_t *mpt, intptr_t data, int mode) 12716 { 12717 uint16_t i = 0; 12718 uint16_t count = 0; 12719 int ret = 0; 12720 mptsas_target_t *ptgt; 12721 mptsas_disk_info_t *di; 12722 STRUCT_DECL(mptsas_get_disk_info, gdi); 12723 12724 if ((mode & FREAD) == 0) 12725 return (EACCES); 12726 12727 STRUCT_INIT(gdi, get_udatamodel()); 12728 12729 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi), 12730 mode) != 0) { 12731 return (EFAULT); 12732 } 12733 12734 /* Find out how many targets there are. */ 12735 mutex_enter(&mpt->m_mutex); 12736 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12737 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12738 count++; 12739 } 12740 mutex_exit(&mpt->m_mutex); 12741 12742 /* 12743 * If we haven't been asked to copy out information on each target, 12744 * then just return the count. 12745 */ 12746 STRUCT_FSET(gdi, DiskCount, count); 12747 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL) 12748 goto copy_out; 12749 12750 /* 12751 * If we haven't been given a large enough buffer to copy out into, 12752 * let the caller know. 12753 */ 12754 if (STRUCT_FGET(gdi, DiskInfoArraySize) < 12755 count * sizeof (mptsas_disk_info_t)) { 12756 ret = ENOSPC; 12757 goto copy_out; 12758 } 12759 12760 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP); 12761 12762 mutex_enter(&mpt->m_mutex); 12763 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12764 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12765 if (i >= count) { 12766 /* 12767 * The number of targets changed while we weren't 12768 * looking, so give up. 12769 */ 12770 refhash_rele(mpt->m_targets, ptgt); 12771 mutex_exit(&mpt->m_mutex); 12772 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12773 return (EAGAIN); 12774 } 12775 di[i].Instance = mpt->m_instance; 12776 di[i].Enclosure = ptgt->m_enclosure; 12777 di[i].Slot = ptgt->m_slot_num; 12778 di[i].SasAddress = ptgt->m_addr.mta_wwn; 12779 i++; 12780 } 12781 mutex_exit(&mpt->m_mutex); 12782 STRUCT_FSET(gdi, DiskCount, i); 12783 12784 /* Copy out the disk information to the caller. */ 12785 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray), 12786 i * sizeof (mptsas_disk_info_t), mode) != 0) { 12787 ret = EFAULT; 12788 } 12789 12790 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12791 12792 copy_out: 12793 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi), 12794 mode) != 0) { 12795 ret = EFAULT; 12796 } 12797 12798 return (ret); 12799 } 12800 12801 static int 12802 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp, 12803 int *rval) 12804 { 12805 int status = 0; 12806 mptsas_t *mpt; 12807 mptsas_update_flash_t flashdata; 12808 mptsas_pass_thru_t passthru_data; 12809 mptsas_adapter_data_t adapter_data; 12810 mptsas_pci_info_t pci_info; 12811 int copylen; 12812 12813 int iport_flag = 0; 12814 dev_info_t *dip = NULL; 12815 mptsas_phymask_t phymask = 0; 12816 struct devctl_iocdata *dcp = NULL; 12817 char *addr = NULL; 12818 mptsas_target_t *ptgt = NULL; 12819 12820 *rval = MPTIOCTL_STATUS_GOOD; 12821 if (secpolicy_sys_config(credp, B_FALSE) != 0) { 12822 return (EPERM); 12823 } 12824 12825 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev))); 12826 if (mpt == NULL) { 12827 /* 12828 * Called from iport node, get the states 12829 */ 12830 iport_flag = 1; 12831 dip = mptsas_get_dip_from_dev(dev, &phymask); 12832 if (dip == NULL) { 12833 return (ENXIO); 12834 } 12835 mpt = DIP2MPT(dip); 12836 } 12837 /* Make sure power level is D0 before accessing registers */ 12838 mutex_enter(&mpt->m_mutex); 12839 if (mpt->m_options & MPTSAS_OPT_PM) { 12840 (void) pm_busy_component(mpt->m_dip, 0); 12841 if (mpt->m_power_level != PM_LEVEL_D0) { 12842 mutex_exit(&mpt->m_mutex); 12843 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) != 12844 DDI_SUCCESS) { 12845 mptsas_log(mpt, CE_WARN, 12846 "mptsas%d: mptsas_ioctl: Raise power " 12847 "request failed.", mpt->m_instance); 12848 (void) pm_idle_component(mpt->m_dip, 0); 12849 return (ENXIO); 12850 } 12851 } else { 12852 mutex_exit(&mpt->m_mutex); 12853 } 12854 } else { 12855 mutex_exit(&mpt->m_mutex); 12856 } 12857 12858 if (iport_flag) { 12859 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval); 12860 if (status != 0) { 12861 goto out; 12862 } 12863 /* 12864 * The following code control the OK2RM LED, it doesn't affect 12865 * the ioctl return status. 12866 */ 12867 if ((cmd == DEVCTL_DEVICE_ONLINE) || 12868 (cmd == DEVCTL_DEVICE_OFFLINE)) { 12869 if (ndi_dc_allochdl((void *)data, &dcp) != 12870 NDI_SUCCESS) { 12871 goto out; 12872 } 12873 addr = ndi_dc_getaddr(dcp); 12874 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask); 12875 if (ptgt == NULL) { 12876 NDBG14(("mptsas_ioctl led control: tgt %s not " 12877 "found", addr)); 12878 ndi_dc_freehdl(dcp); 12879 goto out; 12880 } 12881 mutex_enter(&mpt->m_mutex); 12882 if (cmd == DEVCTL_DEVICE_ONLINE) { 12883 ptgt->m_tgt_unconfigured = 0; 12884 } else if (cmd == DEVCTL_DEVICE_OFFLINE) { 12885 ptgt->m_tgt_unconfigured = 1; 12886 } 12887 if (cmd == DEVCTL_DEVICE_OFFLINE) { 12888 ptgt->m_led_status |= 12889 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)); 12890 } else { 12891 ptgt->m_led_status &= 12892 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)); 12893 } 12894 (void) mptsas_flush_led_status(mpt, ptgt); 12895 mutex_exit(&mpt->m_mutex); 12896 ndi_dc_freehdl(dcp); 12897 } 12898 goto out; 12899 } 12900 switch (cmd) { 12901 case MPTIOCTL_GET_DISK_INFO: 12902 status = get_disk_info(mpt, data, mode); 12903 break; 12904 case MPTIOCTL_LED_CONTROL: 12905 status = led_control(mpt, data, mode); 12906 break; 12907 case MPTIOCTL_UPDATE_FLASH: 12908 if (ddi_copyin((void *)data, &flashdata, 12909 sizeof (struct mptsas_update_flash), mode)) { 12910 status = EFAULT; 12911 break; 12912 } 12913 12914 mutex_enter(&mpt->m_mutex); 12915 if (mptsas_update_flash(mpt, 12916 (caddr_t)(long)flashdata.PtrBuffer, 12917 flashdata.ImageSize, flashdata.ImageType, mode)) { 12918 status = EFAULT; 12919 } 12920 12921 /* 12922 * Reset the chip to start using the new 12923 * firmware. Reset if failed also. 12924 */ 12925 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12926 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 12927 status = EFAULT; 12928 } 12929 mutex_exit(&mpt->m_mutex); 12930 break; 12931 case MPTIOCTL_PASS_THRU: 12932 /* 12933 * The user has requested to pass through a command to 12934 * be executed by the MPT firmware. Call our routine 12935 * which does this. Only allow one passthru IOCTL at 12936 * one time. Other threads will block on 12937 * m_passthru_mutex, which is of adaptive variant. 12938 */ 12939 if (ddi_copyin((void *)data, &passthru_data, 12940 sizeof (mptsas_pass_thru_t), mode)) { 12941 status = EFAULT; 12942 break; 12943 } 12944 mutex_enter(&mpt->m_passthru_mutex); 12945 mutex_enter(&mpt->m_mutex); 12946 status = mptsas_pass_thru(mpt, &passthru_data, mode); 12947 mutex_exit(&mpt->m_mutex); 12948 mutex_exit(&mpt->m_passthru_mutex); 12949 12950 break; 12951 case MPTIOCTL_GET_ADAPTER_DATA: 12952 /* 12953 * The user has requested to read adapter data. Call 12954 * our routine which does this. 12955 */ 12956 bzero(&adapter_data, sizeof (mptsas_adapter_data_t)); 12957 if (ddi_copyin((void *)data, (void *)&adapter_data, 12958 sizeof (mptsas_adapter_data_t), mode)) { 12959 status = EFAULT; 12960 break; 12961 } 12962 if (adapter_data.StructureLength >= 12963 sizeof (mptsas_adapter_data_t)) { 12964 adapter_data.StructureLength = (uint32_t) 12965 sizeof (mptsas_adapter_data_t); 12966 copylen = sizeof (mptsas_adapter_data_t); 12967 mutex_enter(&mpt->m_mutex); 12968 mptsas_read_adapter_data(mpt, &adapter_data); 12969 mutex_exit(&mpt->m_mutex); 12970 } else { 12971 adapter_data.StructureLength = (uint32_t) 12972 sizeof (mptsas_adapter_data_t); 12973 copylen = sizeof (adapter_data.StructureLength); 12974 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 12975 } 12976 if (ddi_copyout((void *)(&adapter_data), (void *)data, 12977 copylen, mode) != 0) { 12978 status = EFAULT; 12979 } 12980 break; 12981 case MPTIOCTL_GET_PCI_INFO: 12982 /* 12983 * The user has requested to read pci info. Call 12984 * our routine which does this. 12985 */ 12986 bzero(&pci_info, sizeof (mptsas_pci_info_t)); 12987 mutex_enter(&mpt->m_mutex); 12988 mptsas_read_pci_info(mpt, &pci_info); 12989 mutex_exit(&mpt->m_mutex); 12990 if (ddi_copyout((void *)(&pci_info), (void *)data, 12991 sizeof (mptsas_pci_info_t), mode) != 0) { 12992 status = EFAULT; 12993 } 12994 break; 12995 case MPTIOCTL_RESET_ADAPTER: 12996 mutex_enter(&mpt->m_mutex); 12997 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12998 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 12999 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL " 13000 "failed"); 13001 status = EFAULT; 13002 } 13003 mutex_exit(&mpt->m_mutex); 13004 break; 13005 case MPTIOCTL_DIAG_ACTION: 13006 /* 13007 * The user has done a diag buffer action. Call our 13008 * routine which does this. Only allow one diag action 13009 * at one time. 13010 */ 13011 mutex_enter(&mpt->m_mutex); 13012 if (mpt->m_diag_action_in_progress) { 13013 mutex_exit(&mpt->m_mutex); 13014 return (EBUSY); 13015 } 13016 mpt->m_diag_action_in_progress = 1; 13017 status = mptsas_diag_action(mpt, 13018 (mptsas_diag_action_t *)data, mode); 13019 mpt->m_diag_action_in_progress = 0; 13020 mutex_exit(&mpt->m_mutex); 13021 break; 13022 case MPTIOCTL_EVENT_QUERY: 13023 /* 13024 * The user has done an event query. Call our routine 13025 * which does this. 13026 */ 13027 status = mptsas_event_query(mpt, 13028 (mptsas_event_query_t *)data, mode, rval); 13029 break; 13030 case MPTIOCTL_EVENT_ENABLE: 13031 /* 13032 * The user has done an event enable. Call our routine 13033 * which does this. 13034 */ 13035 status = mptsas_event_enable(mpt, 13036 (mptsas_event_enable_t *)data, mode, rval); 13037 break; 13038 case MPTIOCTL_EVENT_REPORT: 13039 /* 13040 * The user has done an event report. Call our routine 13041 * which does this. 13042 */ 13043 status = mptsas_event_report(mpt, 13044 (mptsas_event_report_t *)data, mode, rval); 13045 break; 13046 case MPTIOCTL_REG_ACCESS: 13047 /* 13048 * The user has requested register access. Call our 13049 * routine which does this. 13050 */ 13051 status = mptsas_reg_access(mpt, 13052 (mptsas_reg_access_t *)data, mode); 13053 break; 13054 default: 13055 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, 13056 rval); 13057 break; 13058 } 13059 13060 out: 13061 return (status); 13062 } 13063 13064 int 13065 mptsas_restart_ioc(mptsas_t *mpt) 13066 { 13067 int rval = DDI_SUCCESS; 13068 mptsas_target_t *ptgt = NULL; 13069 13070 ASSERT(mutex_owned(&mpt->m_mutex)); 13071 13072 /* 13073 * Set a flag telling I/O path that we're processing a reset. This is 13074 * needed because after the reset is complete, the hash table still 13075 * needs to be rebuilt. If I/Os are started before the hash table is 13076 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked 13077 * so that they can be retried. 13078 */ 13079 mpt->m_in_reset = TRUE; 13080 13081 /* 13082 * Wait until all the allocated sense data buffers for DMA are freed. 13083 */ 13084 while (mpt->m_extreq_sense_refcount > 0) 13085 cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex); 13086 13087 /* 13088 * Set all throttles to HOLD 13089 */ 13090 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 13091 ptgt = refhash_next(mpt->m_targets, ptgt)) { 13092 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 13093 } 13094 13095 /* 13096 * Disable interrupts 13097 */ 13098 MPTSAS_DISABLE_INTR(mpt); 13099 13100 /* 13101 * Abort all commands: outstanding commands, commands in waitq and 13102 * tx_waitq. 13103 */ 13104 mptsas_flush_hba(mpt); 13105 13106 /* 13107 * Reinitialize the chip. 13108 */ 13109 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 13110 rval = DDI_FAILURE; 13111 } 13112 13113 /* 13114 * Enable interrupts again 13115 */ 13116 MPTSAS_ENABLE_INTR(mpt); 13117 13118 /* 13119 * If mptsas_init_chip was successful, update the driver data. 13120 */ 13121 if (rval == DDI_SUCCESS) { 13122 mptsas_update_driver_data(mpt); 13123 } 13124 13125 /* 13126 * Reset the throttles 13127 */ 13128 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 13129 ptgt = refhash_next(mpt->m_targets, ptgt)) { 13130 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 13131 } 13132 13133 mptsas_doneq_empty(mpt); 13134 mptsas_restart_hba(mpt); 13135 13136 if (rval != DDI_SUCCESS) { 13137 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 13138 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 13139 } 13140 13141 /* 13142 * Clear the reset flag so that I/Os can continue. 13143 */ 13144 mpt->m_in_reset = FALSE; 13145 13146 return (rval); 13147 } 13148 13149 static int 13150 mptsas_init_chip(mptsas_t *mpt, int first_time) 13151 { 13152 ddi_dma_cookie_t cookie; 13153 uint32_t i; 13154 int rval; 13155 13156 /* 13157 * Check to see if the firmware image is valid 13158 */ 13159 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) & 13160 MPI2_DIAG_FLASH_BAD_SIG) { 13161 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!"); 13162 goto fail; 13163 } 13164 13165 /* 13166 * Reset the chip 13167 */ 13168 rval = mptsas_ioc_reset(mpt, first_time); 13169 if (rval == MPTSAS_RESET_FAIL) { 13170 mptsas_log(mpt, CE_WARN, "hard reset failed!"); 13171 goto fail; 13172 } 13173 13174 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) { 13175 goto mur; 13176 } 13177 /* 13178 * Setup configuration space 13179 */ 13180 if (mptsas_config_space_init(mpt) == FALSE) { 13181 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init " 13182 "failed!"); 13183 goto fail; 13184 } 13185 13186 /* 13187 * IOC facts can change after a diag reset so all buffers that are 13188 * based on these numbers must be de-allocated and re-allocated. Get 13189 * new IOC facts each time chip is initialized. 13190 */ 13191 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) { 13192 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed"); 13193 goto fail; 13194 } 13195 13196 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) { 13197 goto fail; 13198 } 13199 /* 13200 * Allocate request message frames, reply free queue, reply descriptor 13201 * post queue, and reply message frames using latest IOC facts. 13202 */ 13203 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) { 13204 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed"); 13205 goto fail; 13206 } 13207 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) { 13208 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed"); 13209 goto fail; 13210 } 13211 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) { 13212 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!"); 13213 goto fail; 13214 } 13215 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) { 13216 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!"); 13217 goto fail; 13218 } 13219 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) { 13220 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!"); 13221 goto fail; 13222 } 13223 13224 mur: 13225 /* 13226 * Re-Initialize ioc to operational state 13227 */ 13228 if (mptsas_ioc_init(mpt) == DDI_FAILURE) { 13229 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed"); 13230 goto fail; 13231 } 13232 13233 mptsas_alloc_reply_args(mpt); 13234 13235 /* 13236 * Initialize reply post index. Reply free index is initialized after 13237 * the next loop. 13238 */ 13239 mpt->m_post_index = 0; 13240 13241 /* 13242 * Initialize the Reply Free Queue with the physical addresses of our 13243 * reply frames. 13244 */ 13245 cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu; 13246 for (i = 0; i < mpt->m_max_replies; i++) { 13247 ddi_put32(mpt->m_acc_free_queue_hdl, 13248 &((uint32_t *)(void *)mpt->m_free_queue)[i], 13249 cookie.dmac_address); 13250 cookie.dmac_address += mpt->m_reply_frame_size; 13251 } 13252 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 13253 DDI_DMA_SYNC_FORDEV); 13254 13255 /* 13256 * Initialize the reply free index to one past the last frame on the 13257 * queue. This will signify that the queue is empty to start with. 13258 */ 13259 mpt->m_free_index = i; 13260 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i); 13261 13262 /* 13263 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's. 13264 */ 13265 for (i = 0; i < mpt->m_post_queue_depth; i++) { 13266 ddi_put64(mpt->m_acc_post_queue_hdl, 13267 &((uint64_t *)(void *)mpt->m_post_queue)[i], 13268 0xFFFFFFFFFFFFFFFF); 13269 } 13270 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 13271 DDI_DMA_SYNC_FORDEV); 13272 13273 /* 13274 * Enable ports 13275 */ 13276 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) { 13277 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed"); 13278 goto fail; 13279 } 13280 13281 /* 13282 * enable events 13283 */ 13284 if (mptsas_ioc_enable_event_notification(mpt)) { 13285 mptsas_log(mpt, CE_WARN, 13286 "mptsas_ioc_enable_event_notification failed"); 13287 goto fail; 13288 } 13289 13290 /* 13291 * We need checks in attach and these. 13292 * chip_init is called in mult. places 13293 */ 13294 13295 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 13296 DDI_SUCCESS) || 13297 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 13298 DDI_SUCCESS) || 13299 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 13300 DDI_SUCCESS) || 13301 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 13302 DDI_SUCCESS) || 13303 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 13304 DDI_SUCCESS) || 13305 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 13306 DDI_SUCCESS)) { 13307 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13308 goto fail; 13309 } 13310 13311 /* Check all acc handles */ 13312 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 13313 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 13314 DDI_SUCCESS) || 13315 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 13316 DDI_SUCCESS) || 13317 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 13318 DDI_SUCCESS) || 13319 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 13320 DDI_SUCCESS) || 13321 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 13322 DDI_SUCCESS) || 13323 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 13324 DDI_SUCCESS) || 13325 (mptsas_check_acc_handle(mpt->m_config_handle) != 13326 DDI_SUCCESS)) { 13327 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13328 goto fail; 13329 } 13330 13331 return (DDI_SUCCESS); 13332 13333 fail: 13334 return (DDI_FAILURE); 13335 } 13336 13337 static int 13338 mptsas_get_pci_cap(mptsas_t *mpt) 13339 { 13340 ushort_t caps_ptr, cap, cap_count; 13341 13342 if (mpt->m_config_handle == NULL) 13343 return (FALSE); 13344 /* 13345 * Check if capabilities list is supported and if so, 13346 * get initial capabilities pointer and clear bits 0,1. 13347 */ 13348 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) 13349 & PCI_STAT_CAP) { 13350 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13351 PCI_CONF_CAP_PTR), 4); 13352 } else { 13353 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 13354 } 13355 13356 /* 13357 * Walk capabilities if supported. 13358 */ 13359 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 13360 13361 /* 13362 * Check that we haven't exceeded the maximum number of 13363 * capabilities and that the pointer is in a valid range. 13364 */ 13365 if (++cap_count > 48) { 13366 mptsas_log(mpt, CE_WARN, 13367 "too many device capabilities.\n"); 13368 break; 13369 } 13370 if (caps_ptr < 64) { 13371 mptsas_log(mpt, CE_WARN, 13372 "capabilities pointer 0x%x out of range.\n", 13373 caps_ptr); 13374 break; 13375 } 13376 13377 /* 13378 * Get next capability and check that it is valid. 13379 * For now, we only support power management. 13380 */ 13381 cap = pci_config_get8(mpt->m_config_handle, caps_ptr); 13382 switch (cap) { 13383 case PCI_CAP_ID_PM: 13384 mptsas_log(mpt, CE_NOTE, 13385 "?mptsas%d supports power management.\n", 13386 mpt->m_instance); 13387 mpt->m_options |= MPTSAS_OPT_PM; 13388 13389 /* Save PMCSR offset */ 13390 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR; 13391 break; 13392 /* 13393 * The following capabilities are valid. Any others 13394 * will cause a message to be logged. 13395 */ 13396 case PCI_CAP_ID_VPD: 13397 case PCI_CAP_ID_MSI: 13398 case PCI_CAP_ID_PCIX: 13399 case PCI_CAP_ID_PCI_E: 13400 case PCI_CAP_ID_MSI_X: 13401 break; 13402 default: 13403 mptsas_log(mpt, CE_NOTE, 13404 "?mptsas%d unrecognized capability " 13405 "0x%x.\n", mpt->m_instance, cap); 13406 break; 13407 } 13408 13409 /* 13410 * Get next capabilities pointer and clear bits 0,1. 13411 */ 13412 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13413 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 13414 } 13415 return (TRUE); 13416 } 13417 13418 static int 13419 mptsas_init_pm(mptsas_t *mpt) 13420 { 13421 char pmc_name[16]; 13422 char *pmc[] = { 13423 NULL, 13424 "0=Off (PCI D3 State)", 13425 "3=On (PCI D0 State)", 13426 NULL 13427 }; 13428 uint16_t pmcsr_stat; 13429 13430 if (mptsas_get_pci_cap(mpt) == FALSE) { 13431 return (DDI_FAILURE); 13432 } 13433 /* 13434 * If PCI's capability does not support PM, then don't need 13435 * to registe the pm-components 13436 */ 13437 if (!(mpt->m_options & MPTSAS_OPT_PM)) 13438 return (DDI_SUCCESS); 13439 /* 13440 * If power management is supported by this chip, create 13441 * pm-components property for the power management framework 13442 */ 13443 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance); 13444 pmc[0] = pmc_name; 13445 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip, 13446 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 13447 mpt->m_options &= ~MPTSAS_OPT_PM; 13448 mptsas_log(mpt, CE_WARN, 13449 "mptsas%d: pm-component property creation failed.", 13450 mpt->m_instance); 13451 return (DDI_FAILURE); 13452 } 13453 13454 /* 13455 * Power on device. 13456 */ 13457 (void) pm_busy_component(mpt->m_dip, 0); 13458 pmcsr_stat = pci_config_get16(mpt->m_config_handle, 13459 mpt->m_pmcsr_offset); 13460 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 13461 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device", 13462 mpt->m_instance); 13463 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, 13464 PCI_PMCSR_D0); 13465 } 13466 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 13467 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed"); 13468 return (DDI_FAILURE); 13469 } 13470 mpt->m_power_level = PM_LEVEL_D0; 13471 /* 13472 * Set pm idle delay. 13473 */ 13474 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 13475 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT); 13476 13477 return (DDI_SUCCESS); 13478 } 13479 13480 static int 13481 mptsas_register_intrs(mptsas_t *mpt) 13482 { 13483 dev_info_t *dip; 13484 int intr_types; 13485 13486 dip = mpt->m_dip; 13487 13488 /* Get supported interrupt types */ 13489 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 13490 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types " 13491 "failed\n"); 13492 return (FALSE); 13493 } 13494 13495 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types)); 13496 13497 /* 13498 * Try MSI, but fall back to FIXED 13499 */ 13500 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) { 13501 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) { 13502 NDBG0(("Using MSI interrupt type")); 13503 mpt->m_intr_type = DDI_INTR_TYPE_MSI; 13504 return (TRUE); 13505 } 13506 } 13507 if (intr_types & DDI_INTR_TYPE_FIXED) { 13508 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) { 13509 NDBG0(("Using FIXED interrupt type")); 13510 mpt->m_intr_type = DDI_INTR_TYPE_FIXED; 13511 return (TRUE); 13512 } else { 13513 NDBG0(("FIXED interrupt registration failed")); 13514 return (FALSE); 13515 } 13516 } 13517 13518 return (FALSE); 13519 } 13520 13521 static void 13522 mptsas_unregister_intrs(mptsas_t *mpt) 13523 { 13524 mptsas_rem_intrs(mpt); 13525 } 13526 13527 /* 13528 * mptsas_add_intrs: 13529 * 13530 * Register FIXED or MSI interrupts. 13531 */ 13532 static int 13533 mptsas_add_intrs(mptsas_t *mpt, int intr_type) 13534 { 13535 dev_info_t *dip = mpt->m_dip; 13536 int avail, actual, count = 0; 13537 int i, flag, ret; 13538 13539 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type)); 13540 13541 /* Get number of interrupts */ 13542 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 13543 if ((ret != DDI_SUCCESS) || (count <= 0)) { 13544 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, " 13545 "ret %d count %d\n", ret, count); 13546 13547 return (DDI_FAILURE); 13548 } 13549 13550 /* Get number of available interrupts */ 13551 ret = ddi_intr_get_navail(dip, intr_type, &avail); 13552 if ((ret != DDI_SUCCESS) || (avail == 0)) { 13553 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, " 13554 "ret %d avail %d\n", ret, avail); 13555 13556 return (DDI_FAILURE); 13557 } 13558 13559 if (avail < count) { 13560 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, " 13561 "navail() returned %d", count, avail); 13562 } 13563 13564 /* Mpt only have one interrupt routine */ 13565 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 13566 count = 1; 13567 } 13568 13569 /* Allocate an array of interrupt handles */ 13570 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t); 13571 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP); 13572 13573 flag = DDI_INTR_ALLOC_NORMAL; 13574 13575 /* call ddi_intr_alloc() */ 13576 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0, 13577 count, &actual, flag); 13578 13579 if ((ret != DDI_SUCCESS) || (actual == 0)) { 13580 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n", 13581 ret); 13582 kmem_free(mpt->m_htable, mpt->m_intr_size); 13583 return (DDI_FAILURE); 13584 } 13585 13586 /* use interrupt count returned or abort? */ 13587 if (actual < count) { 13588 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n", 13589 count, actual); 13590 } 13591 13592 mpt->m_intr_cnt = actual; 13593 13594 /* 13595 * Get priority for first msi, assume remaining are all the same 13596 */ 13597 if ((ret = ddi_intr_get_pri(mpt->m_htable[0], 13598 &mpt->m_intr_pri)) != DDI_SUCCESS) { 13599 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret); 13600 13601 /* Free already allocated intr */ 13602 for (i = 0; i < actual; i++) { 13603 (void) ddi_intr_free(mpt->m_htable[i]); 13604 } 13605 13606 kmem_free(mpt->m_htable, mpt->m_intr_size); 13607 return (DDI_FAILURE); 13608 } 13609 13610 /* Test for high level mutex */ 13611 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) { 13612 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: " 13613 "Hi level interrupt not supported\n"); 13614 13615 /* Free already allocated intr */ 13616 for (i = 0; i < actual; i++) { 13617 (void) ddi_intr_free(mpt->m_htable[i]); 13618 } 13619 13620 kmem_free(mpt->m_htable, mpt->m_intr_size); 13621 return (DDI_FAILURE); 13622 } 13623 13624 /* Call ddi_intr_add_handler() */ 13625 for (i = 0; i < actual; i++) { 13626 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr, 13627 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 13628 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() " 13629 "failed %d\n", ret); 13630 13631 /* Free already allocated intr */ 13632 for (i = 0; i < actual; i++) { 13633 (void) ddi_intr_free(mpt->m_htable[i]); 13634 } 13635 13636 kmem_free(mpt->m_htable, mpt->m_intr_size); 13637 return (DDI_FAILURE); 13638 } 13639 } 13640 13641 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap)) 13642 != DDI_SUCCESS) { 13643 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret); 13644 13645 /* Free already allocated intr */ 13646 for (i = 0; i < actual; i++) { 13647 (void) ddi_intr_free(mpt->m_htable[i]); 13648 } 13649 13650 kmem_free(mpt->m_htable, mpt->m_intr_size); 13651 return (DDI_FAILURE); 13652 } 13653 13654 /* 13655 * Enable interrupts 13656 */ 13657 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13658 /* Call ddi_intr_block_enable() for MSI interrupts */ 13659 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt); 13660 } else { 13661 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 13662 for (i = 0; i < mpt->m_intr_cnt; i++) { 13663 (void) ddi_intr_enable(mpt->m_htable[i]); 13664 } 13665 } 13666 return (DDI_SUCCESS); 13667 } 13668 13669 /* 13670 * mptsas_rem_intrs: 13671 * 13672 * Unregister FIXED or MSI interrupts 13673 */ 13674 static void 13675 mptsas_rem_intrs(mptsas_t *mpt) 13676 { 13677 int i; 13678 13679 NDBG6(("mptsas_rem_intrs")); 13680 13681 /* Disable all interrupts */ 13682 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13683 /* Call ddi_intr_block_disable() */ 13684 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt); 13685 } else { 13686 for (i = 0; i < mpt->m_intr_cnt; i++) { 13687 (void) ddi_intr_disable(mpt->m_htable[i]); 13688 } 13689 } 13690 13691 /* Call ddi_intr_remove_handler() */ 13692 for (i = 0; i < mpt->m_intr_cnt; i++) { 13693 (void) ddi_intr_remove_handler(mpt->m_htable[i]); 13694 (void) ddi_intr_free(mpt->m_htable[i]); 13695 } 13696 13697 kmem_free(mpt->m_htable, mpt->m_intr_size); 13698 } 13699 13700 /* 13701 * The IO fault service error handling callback function 13702 */ 13703 /*ARGSUSED*/ 13704 static int 13705 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 13706 { 13707 /* 13708 * as the driver can always deal with an error in any dma or 13709 * access handle, we can just return the fme_status value. 13710 */ 13711 pci_ereport_post(dip, err, NULL); 13712 return (err->fme_status); 13713 } 13714 13715 /* 13716 * mptsas_fm_init - initialize fma capabilities and register with IO 13717 * fault services. 13718 */ 13719 static void 13720 mptsas_fm_init(mptsas_t *mpt) 13721 { 13722 /* 13723 * Need to change iblock to priority for new MSI intr 13724 */ 13725 ddi_iblock_cookie_t fm_ibc; 13726 13727 /* Only register with IO Fault Services if we have some capability */ 13728 if (mpt->m_fm_capabilities) { 13729 /* Adjust access and dma attributes for FMA */ 13730 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 13731 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13732 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13733 13734 /* 13735 * Register capabilities with IO Fault Services. 13736 * mpt->m_fm_capabilities will be updated to indicate 13737 * capabilities actually supported (not requested.) 13738 */ 13739 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc); 13740 13741 /* 13742 * Initialize pci ereport capabilities if ereport 13743 * capable (should always be.) 13744 */ 13745 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13746 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13747 pci_ereport_setup(mpt->m_dip); 13748 } 13749 13750 /* 13751 * Register error callback if error callback capable. 13752 */ 13753 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13754 ddi_fm_handler_register(mpt->m_dip, 13755 mptsas_fm_error_cb, (void *) mpt); 13756 } 13757 } 13758 } 13759 13760 /* 13761 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO 13762 * fault services. 13763 * 13764 */ 13765 static void 13766 mptsas_fm_fini(mptsas_t *mpt) 13767 { 13768 /* Only unregister FMA capabilities if registered */ 13769 if (mpt->m_fm_capabilities) { 13770 13771 /* 13772 * Un-register error callback if error callback capable. 13773 */ 13774 13775 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13776 ddi_fm_handler_unregister(mpt->m_dip); 13777 } 13778 13779 /* 13780 * Release any resources allocated by pci_ereport_setup() 13781 */ 13782 13783 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13784 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13785 pci_ereport_teardown(mpt->m_dip); 13786 } 13787 13788 /* Unregister from IO Fault Services */ 13789 ddi_fm_fini(mpt->m_dip); 13790 13791 /* Adjust access and dma attributes for FMA */ 13792 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 13793 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13794 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13795 13796 } 13797 } 13798 13799 int 13800 mptsas_check_acc_handle(ddi_acc_handle_t handle) 13801 { 13802 ddi_fm_error_t de; 13803 13804 if (handle == NULL) 13805 return (DDI_FAILURE); 13806 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 13807 return (de.fme_status); 13808 } 13809 13810 int 13811 mptsas_check_dma_handle(ddi_dma_handle_t handle) 13812 { 13813 ddi_fm_error_t de; 13814 13815 if (handle == NULL) 13816 return (DDI_FAILURE); 13817 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 13818 return (de.fme_status); 13819 } 13820 13821 void 13822 mptsas_fm_ereport(mptsas_t *mpt, char *detail) 13823 { 13824 uint64_t ena; 13825 char buf[FM_MAX_CLASS]; 13826 13827 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 13828 ena = fm_ena_generate(0, FM_ENA_FMT1); 13829 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) { 13830 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP, 13831 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 13832 } 13833 } 13834 13835 static int 13836 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 13837 uint16_t *dev_handle, mptsas_target_t **pptgt) 13838 { 13839 int rval; 13840 uint32_t dev_info; 13841 uint64_t sas_wwn; 13842 mptsas_phymask_t phymask; 13843 uint8_t physport, phynum, config, disk; 13844 uint64_t devicename; 13845 uint16_t pdev_hdl; 13846 mptsas_target_t *tmp_tgt = NULL; 13847 uint16_t bay_num, enclosure, io_flags; 13848 13849 ASSERT(*pptgt == NULL); 13850 13851 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle, 13852 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl, 13853 &bay_num, &enclosure, &io_flags); 13854 if (rval != DDI_SUCCESS) { 13855 rval = DEV_INFO_FAIL_PAGE0; 13856 return (rval); 13857 } 13858 13859 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET | 13860 MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13861 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) { 13862 rval = DEV_INFO_WRONG_DEVICE_TYPE; 13863 return (rval); 13864 } 13865 13866 /* 13867 * Check if the dev handle is for a Phys Disk. If so, set return value 13868 * and exit. Don't add Phys Disks to hash. 13869 */ 13870 for (config = 0; config < mpt->m_num_raid_configs; config++) { 13871 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 13872 if (*dev_handle == mpt->m_raidconfig[config]. 13873 m_physdisk_devhdl[disk]) { 13874 rval = DEV_INFO_PHYS_DISK; 13875 return (rval); 13876 } 13877 } 13878 } 13879 13880 /* 13881 * Get SATA Device Name from SAS device page0 for 13882 * sata device, if device name doesn't exist, set mta_wwn to 13883 * 0 for direct attached SATA. For the device behind the expander 13884 * we still can use STP address assigned by expander. 13885 */ 13886 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13887 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13888 /* alloc a temporary target to send the cmd to */ 13889 tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle, 13890 0, dev_info, 0, 0); 13891 mutex_exit(&mpt->m_mutex); 13892 13893 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0); 13894 13895 if (devicename == -1) { 13896 mutex_enter(&mpt->m_mutex); 13897 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13898 rval = DEV_INFO_FAIL_GUID; 13899 return (rval); 13900 } 13901 13902 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) { 13903 sas_wwn = devicename; 13904 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) { 13905 sas_wwn = 0; 13906 } 13907 13908 mutex_enter(&mpt->m_mutex); 13909 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13910 } 13911 13912 phymask = mptsas_physport_to_phymask(mpt, physport); 13913 *pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn, 13914 dev_info, phymask, phynum); 13915 if (*pptgt == NULL) { 13916 mptsas_log(mpt, CE_WARN, "Failed to allocated target" 13917 "structure!"); 13918 rval = DEV_INFO_FAIL_ALLOC; 13919 return (rval); 13920 } 13921 (*pptgt)->m_io_flags = io_flags; 13922 (*pptgt)->m_enclosure = enclosure; 13923 (*pptgt)->m_slot_num = bay_num; 13924 return (DEV_INFO_SUCCESS); 13925 } 13926 13927 uint64_t 13928 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun) 13929 { 13930 uint64_t sata_guid = 0, *pwwn = NULL; 13931 int target = ptgt->m_devhdl; 13932 uchar_t *inq83 = NULL; 13933 int inq83_len = 0xFF; 13934 uchar_t *dblk = NULL; 13935 int inq83_retry = 3; 13936 int rval = DDI_FAILURE; 13937 13938 inq83 = kmem_zalloc(inq83_len, KM_SLEEP); 13939 13940 inq83_retry: 13941 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 13942 inq83_len, NULL, 1); 13943 if (rval != DDI_SUCCESS) { 13944 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 13945 "0x83 for target:%x, lun:%x failed!", target, lun); 13946 sata_guid = -1; 13947 goto out; 13948 } 13949 /* According to SAT2, the first descriptor is logic unit name */ 13950 dblk = &inq83[4]; 13951 if ((dblk[1] & 0x30) != 0) { 13952 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated."); 13953 goto out; 13954 } 13955 pwwn = (uint64_t *)(void *)(&dblk[4]); 13956 if ((dblk[4] & 0xf0) == 0x50) { 13957 sata_guid = BE_64(*pwwn); 13958 goto out; 13959 } else if (dblk[4] == 'A') { 13960 NDBG20(("SATA drive has no NAA format GUID.")); 13961 goto out; 13962 } else { 13963 /* The data is not ready, wait and retry */ 13964 inq83_retry--; 13965 if (inq83_retry <= 0) { 13966 goto out; 13967 } 13968 NDBG20(("The GUID is not ready, retry...")); 13969 delay(1 * drv_usectohz(1000000)); 13970 goto inq83_retry; 13971 } 13972 out: 13973 kmem_free(inq83, inq83_len); 13974 return (sata_guid); 13975 } 13976 13977 static int 13978 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page, 13979 unsigned char *buf, int len, int *reallen, uchar_t evpd) 13980 { 13981 uchar_t cdb[CDB_GROUP0]; 13982 struct scsi_address ap; 13983 struct buf *data_bp = NULL; 13984 int resid = 0; 13985 int ret = DDI_FAILURE; 13986 13987 ASSERT(len <= 0xffff); 13988 13989 ap.a_target = MPTSAS_INVALID_DEVHDL; 13990 ap.a_lun = (uchar_t)(lun); 13991 ap.a_hba_tran = mpt->m_tran; 13992 13993 data_bp = scsi_alloc_consistent_buf(&ap, 13994 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL); 13995 if (data_bp == NULL) { 13996 return (ret); 13997 } 13998 bzero(cdb, CDB_GROUP0); 13999 cdb[0] = SCMD_INQUIRY; 14000 cdb[1] = evpd; 14001 cdb[2] = page; 14002 cdb[3] = (len & 0xff00) >> 8; 14003 cdb[4] = (len & 0x00ff); 14004 cdb[5] = 0; 14005 14006 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp, 14007 &resid); 14008 if (ret == DDI_SUCCESS) { 14009 if (reallen) { 14010 *reallen = len - resid; 14011 } 14012 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len); 14013 } 14014 if (data_bp) { 14015 scsi_free_consistent_buf(data_bp); 14016 } 14017 return (ret); 14018 } 14019 14020 static int 14021 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 14022 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 14023 int *resid) 14024 { 14025 struct scsi_pkt *pktp = NULL; 14026 scsi_hba_tran_t *tran_clone = NULL; 14027 mptsas_tgt_private_t *tgt_private = NULL; 14028 int ret = DDI_FAILURE; 14029 14030 /* 14031 * scsi_hba_tran_t->tran_tgt_private is used to pass the address 14032 * information to scsi_init_pkt, allocate a scsi_hba_tran structure 14033 * to simulate the cmds from sd 14034 */ 14035 tran_clone = kmem_alloc( 14036 sizeof (scsi_hba_tran_t), KM_SLEEP); 14037 if (tran_clone == NULL) { 14038 goto out; 14039 } 14040 bcopy((caddr_t)mpt->m_tran, 14041 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t)); 14042 tgt_private = kmem_alloc( 14043 sizeof (mptsas_tgt_private_t), KM_SLEEP); 14044 if (tgt_private == NULL) { 14045 goto out; 14046 } 14047 tgt_private->t_lun = ap->a_lun; 14048 tgt_private->t_private = ptgt; 14049 tran_clone->tran_tgt_private = tgt_private; 14050 ap->a_hba_tran = tran_clone; 14051 14052 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL, 14053 data_bp, cdblen, sizeof (struct scsi_arq_status), 14054 0, PKT_CONSISTENT, NULL, NULL); 14055 if (pktp == NULL) { 14056 goto out; 14057 } 14058 bcopy(cdb, pktp->pkt_cdbp, cdblen); 14059 pktp->pkt_flags = FLAG_NOPARITY; 14060 if (scsi_poll(pktp) < 0) { 14061 goto out; 14062 } 14063 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) { 14064 goto out; 14065 } 14066 if (resid != NULL) { 14067 *resid = pktp->pkt_resid; 14068 } 14069 14070 ret = DDI_SUCCESS; 14071 out: 14072 if (pktp) { 14073 scsi_destroy_pkt(pktp); 14074 } 14075 if (tran_clone) { 14076 kmem_free(tran_clone, sizeof (scsi_hba_tran_t)); 14077 } 14078 if (tgt_private) { 14079 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 14080 } 14081 return (ret); 14082 } 14083 static int 14084 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun) 14085 { 14086 char *cp = NULL; 14087 char *ptr = NULL; 14088 size_t s = 0; 14089 char *wwid_str = NULL; 14090 char *lun_str = NULL; 14091 long lunnum; 14092 long phyid = -1; 14093 int rc = DDI_FAILURE; 14094 14095 ptr = name; 14096 ASSERT(ptr[0] == 'w' || ptr[0] == 'p'); 14097 ptr++; 14098 if ((cp = strchr(ptr, ',')) == NULL) { 14099 return (DDI_FAILURE); 14100 } 14101 14102 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14103 s = (uintptr_t)cp - (uintptr_t)ptr; 14104 14105 bcopy(ptr, wwid_str, s); 14106 wwid_str[s] = '\0'; 14107 14108 ptr = ++cp; 14109 14110 if ((cp = strchr(ptr, '\0')) == NULL) { 14111 goto out; 14112 } 14113 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14114 s = (uintptr_t)cp - (uintptr_t)ptr; 14115 14116 bcopy(ptr, lun_str, s); 14117 lun_str[s] = '\0'; 14118 14119 if (name[0] == 'p') { 14120 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid); 14121 } else { 14122 rc = scsi_wwnstr_to_wwn(wwid_str, wwid); 14123 } 14124 if (rc != DDI_SUCCESS) 14125 goto out; 14126 14127 if (phyid != -1) { 14128 ASSERT(phyid < MPTSAS_MAX_PHYS); 14129 *phy = (uint8_t)phyid; 14130 } 14131 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum); 14132 if (rc != 0) 14133 goto out; 14134 14135 *lun = (int)lunnum; 14136 rc = DDI_SUCCESS; 14137 out: 14138 if (wwid_str) 14139 kmem_free(wwid_str, SCSI_MAXNAMELEN); 14140 if (lun_str) 14141 kmem_free(lun_str, SCSI_MAXNAMELEN); 14142 14143 return (rc); 14144 } 14145 14146 /* 14147 * mptsas_parse_smp_name() is to parse sas wwn string 14148 * which format is "wWWN" 14149 */ 14150 static int 14151 mptsas_parse_smp_name(char *name, uint64_t *wwn) 14152 { 14153 char *ptr = name; 14154 14155 if (*ptr != 'w') { 14156 return (DDI_FAILURE); 14157 } 14158 14159 ptr++; 14160 if (scsi_wwnstr_to_wwn(ptr, wwn)) { 14161 return (DDI_FAILURE); 14162 } 14163 return (DDI_SUCCESS); 14164 } 14165 14166 static int 14167 mptsas_bus_config(dev_info_t *pdip, uint_t flag, 14168 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 14169 { 14170 int ret = NDI_FAILURE; 14171 int circ = 0; 14172 int circ1 = 0; 14173 mptsas_t *mpt; 14174 char *ptr = NULL; 14175 char *devnm = NULL; 14176 uint64_t wwid = 0; 14177 uint8_t phy = 0xFF; 14178 int lun = 0; 14179 uint_t mflags = flag; 14180 int bconfig = TRUE; 14181 14182 if (scsi_hba_iport_unit_address(pdip) == 0) { 14183 return (DDI_FAILURE); 14184 } 14185 14186 mpt = DIP2MPT(pdip); 14187 if (!mpt) { 14188 return (DDI_FAILURE); 14189 } 14190 /* 14191 * Hold the nexus across the bus_config 14192 */ 14193 ndi_devi_enter(scsi_vhci_dip, &circ); 14194 ndi_devi_enter(pdip, &circ1); 14195 switch (op) { 14196 case BUS_CONFIG_ONE: 14197 /* parse wwid/target name out of name given */ 14198 if ((ptr = strchr((char *)arg, '@')) == NULL) { 14199 ret = NDI_FAILURE; 14200 break; 14201 } 14202 ptr++; 14203 if (strncmp((char *)arg, "smp", 3) == 0) { 14204 /* 14205 * This is a SMP target device 14206 */ 14207 ret = mptsas_parse_smp_name(ptr, &wwid); 14208 if (ret != DDI_SUCCESS) { 14209 ret = NDI_FAILURE; 14210 break; 14211 } 14212 ret = mptsas_config_smp(pdip, wwid, childp); 14213 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) { 14214 /* 14215 * OBP could pass down a non-canonical form 14216 * bootpath without LUN part when LUN is 0. 14217 * So driver need adjust the string. 14218 */ 14219 if (strchr(ptr, ',') == NULL) { 14220 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14221 (void) sprintf(devnm, "%s,0", (char *)arg); 14222 ptr = strchr(devnm, '@'); 14223 ptr++; 14224 } 14225 14226 /* 14227 * The device path is wWWID format and the device 14228 * is not SMP target device. 14229 */ 14230 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun); 14231 if (ret != DDI_SUCCESS) { 14232 ret = NDI_FAILURE; 14233 break; 14234 } 14235 *childp = NULL; 14236 if (ptr[0] == 'w') { 14237 ret = mptsas_config_one_addr(pdip, wwid, 14238 lun, childp); 14239 } else if (ptr[0] == 'p') { 14240 ret = mptsas_config_one_phy(pdip, phy, lun, 14241 childp); 14242 } 14243 14244 /* 14245 * If this is CD/DVD device in OBP path, the 14246 * ndi_busop_bus_config can be skipped as config one 14247 * operation is done above. 14248 */ 14249 if ((ret == NDI_SUCCESS) && (*childp != NULL) && 14250 (strcmp(ddi_node_name(*childp), "cdrom") == 0) && 14251 (strncmp((char *)arg, "disk", 4) == 0)) { 14252 bconfig = FALSE; 14253 ndi_hold_devi(*childp); 14254 } 14255 } else { 14256 ret = NDI_FAILURE; 14257 break; 14258 } 14259 14260 /* 14261 * DDI group instructed us to use this flag. 14262 */ 14263 mflags |= NDI_MDI_FALLBACK; 14264 break; 14265 case BUS_CONFIG_DRIVER: 14266 case BUS_CONFIG_ALL: 14267 mptsas_config_all(pdip); 14268 ret = NDI_SUCCESS; 14269 break; 14270 default: 14271 ret = NDI_FAILURE; 14272 break; 14273 } 14274 14275 if ((ret == NDI_SUCCESS) && bconfig) { 14276 ret = ndi_busop_bus_config(pdip, mflags, op, 14277 (devnm == NULL) ? arg : devnm, childp, 0); 14278 } 14279 14280 ndi_devi_exit(pdip, circ1); 14281 ndi_devi_exit(scsi_vhci_dip, circ); 14282 if (devnm != NULL) 14283 kmem_free(devnm, SCSI_MAXNAMELEN); 14284 return (ret); 14285 } 14286 14287 static int 14288 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip, 14289 mptsas_target_t *ptgt) 14290 { 14291 int rval = DDI_FAILURE; 14292 struct scsi_inquiry *sd_inq = NULL; 14293 mptsas_t *mpt = DIP2MPT(pdip); 14294 14295 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14296 14297 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq, 14298 SUN_INQSIZE, 0, (uchar_t)0); 14299 14300 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14301 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun); 14302 } else { 14303 rval = DDI_FAILURE; 14304 } 14305 14306 kmem_free(sd_inq, SUN_INQSIZE); 14307 return (rval); 14308 } 14309 14310 static int 14311 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 14312 dev_info_t **lundip) 14313 { 14314 int rval; 14315 mptsas_t *mpt = DIP2MPT(pdip); 14316 int phymask; 14317 mptsas_target_t *ptgt = NULL; 14318 14319 /* 14320 * Get the physical port associated to the iport 14321 */ 14322 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14323 "phymask", 0); 14324 14325 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr); 14326 if (ptgt == NULL) { 14327 /* 14328 * didn't match any device by searching 14329 */ 14330 return (DDI_FAILURE); 14331 } 14332 /* 14333 * If the LUN already exists and the status is online, 14334 * we just return the pointer to dev_info_t directly. 14335 * For the mdi_pathinfo node, we'll handle it in 14336 * mptsas_create_virt_lun() 14337 * TODO should be also in mptsas_handle_dr 14338 */ 14339 14340 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun); 14341 if (*lundip != NULL) { 14342 /* 14343 * TODO Another senario is, we hotplug the same disk 14344 * on the same slot, the devhdl changed, is this 14345 * possible? 14346 * tgt_private->t_private != ptgt 14347 */ 14348 if (sasaddr != ptgt->m_addr.mta_wwn) { 14349 /* 14350 * The device has changed although the devhdl is the 14351 * same (Enclosure mapping mode, change drive on the 14352 * same slot) 14353 */ 14354 return (DDI_FAILURE); 14355 } 14356 return (DDI_SUCCESS); 14357 } 14358 14359 if (phymask == 0) { 14360 /* 14361 * Configure IR volume 14362 */ 14363 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip); 14364 return (rval); 14365 } 14366 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14367 14368 return (rval); 14369 } 14370 14371 static int 14372 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 14373 dev_info_t **lundip) 14374 { 14375 int rval; 14376 mptsas_t *mpt = DIP2MPT(pdip); 14377 mptsas_phymask_t phymask; 14378 mptsas_target_t *ptgt = NULL; 14379 14380 /* 14381 * Get the physical port associated to the iport 14382 */ 14383 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14384 "phymask", 0); 14385 14386 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy); 14387 if (ptgt == NULL) { 14388 /* 14389 * didn't match any device by searching 14390 */ 14391 return (DDI_FAILURE); 14392 } 14393 14394 /* 14395 * If the LUN already exists and the status is online, 14396 * we just return the pointer to dev_info_t directly. 14397 * For the mdi_pathinfo node, we'll handle it in 14398 * mptsas_create_virt_lun(). 14399 */ 14400 14401 *lundip = mptsas_find_child_phy(pdip, phy); 14402 if (*lundip != NULL) { 14403 return (DDI_SUCCESS); 14404 } 14405 14406 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14407 14408 return (rval); 14409 } 14410 14411 static int 14412 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num, 14413 uint8_t *lun_addr_type) 14414 { 14415 uint32_t lun_idx = 0; 14416 14417 ASSERT(lun_num != NULL); 14418 ASSERT(lun_addr_type != NULL); 14419 14420 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14421 /* determine report luns addressing type */ 14422 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) { 14423 /* 14424 * Vendors in the field have been found to be concatenating 14425 * bus/target/lun to equal the complete lun value instead 14426 * of switching to flat space addressing 14427 */ 14428 /* 00b - peripheral device addressing method */ 14429 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL: 14430 /* FALLTHRU */ 14431 /* 10b - logical unit addressing method */ 14432 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT: 14433 /* FALLTHRU */ 14434 /* 01b - flat space addressing method */ 14435 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE: 14436 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */ 14437 *lun_addr_type = (buf[lun_idx] & 14438 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6; 14439 *lun_num = (buf[lun_idx] & 0x3F) << 8; 14440 *lun_num |= buf[lun_idx + 1]; 14441 return (DDI_SUCCESS); 14442 default: 14443 return (DDI_FAILURE); 14444 } 14445 } 14446 14447 static int 14448 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) 14449 { 14450 struct buf *repluns_bp = NULL; 14451 struct scsi_address ap; 14452 uchar_t cdb[CDB_GROUP5]; 14453 int ret = DDI_FAILURE; 14454 int retry = 0; 14455 int lun_list_len = 0; 14456 uint16_t lun_num = 0; 14457 uint8_t lun_addr_type = 0; 14458 uint32_t lun_cnt = 0; 14459 uint32_t lun_total = 0; 14460 dev_info_t *cdip = NULL; 14461 uint16_t *saved_repluns = NULL; 14462 char *buffer = NULL; 14463 int buf_len = 128; 14464 mptsas_t *mpt = DIP2MPT(pdip); 14465 uint64_t sas_wwn = 0; 14466 uint8_t phy = 0xFF; 14467 uint32_t dev_info = 0; 14468 14469 mutex_enter(&mpt->m_mutex); 14470 sas_wwn = ptgt->m_addr.mta_wwn; 14471 phy = ptgt->m_phynum; 14472 dev_info = ptgt->m_deviceinfo; 14473 mutex_exit(&mpt->m_mutex); 14474 14475 if (sas_wwn == 0) { 14476 /* 14477 * It's a SATA without Device Name 14478 * So don't try multi-LUNs 14479 */ 14480 if (mptsas_find_child_phy(pdip, phy)) { 14481 return (DDI_SUCCESS); 14482 } else { 14483 /* 14484 * need configure and create node 14485 */ 14486 return (DDI_FAILURE); 14487 } 14488 } 14489 14490 /* 14491 * WWN (SAS address or Device Name exist) 14492 */ 14493 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 14494 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 14495 /* 14496 * SATA device with Device Name 14497 * So don't try multi-LUNs 14498 */ 14499 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) { 14500 return (DDI_SUCCESS); 14501 } else { 14502 return (DDI_FAILURE); 14503 } 14504 } 14505 14506 do { 14507 ap.a_target = MPTSAS_INVALID_DEVHDL; 14508 ap.a_lun = 0; 14509 ap.a_hba_tran = mpt->m_tran; 14510 repluns_bp = scsi_alloc_consistent_buf(&ap, 14511 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL); 14512 if (repluns_bp == NULL) { 14513 retry++; 14514 continue; 14515 } 14516 bzero(cdb, CDB_GROUP5); 14517 cdb[0] = SCMD_REPORT_LUNS; 14518 cdb[6] = (buf_len & 0xff000000) >> 24; 14519 cdb[7] = (buf_len & 0x00ff0000) >> 16; 14520 cdb[8] = (buf_len & 0x0000ff00) >> 8; 14521 cdb[9] = (buf_len & 0x000000ff); 14522 14523 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5, 14524 repluns_bp, NULL); 14525 if (ret != DDI_SUCCESS) { 14526 scsi_free_consistent_buf(repluns_bp); 14527 retry++; 14528 continue; 14529 } 14530 lun_list_len = BE_32(*(int *)((void *)( 14531 repluns_bp->b_un.b_addr))); 14532 if (buf_len >= lun_list_len + 8) { 14533 ret = DDI_SUCCESS; 14534 break; 14535 } 14536 scsi_free_consistent_buf(repluns_bp); 14537 buf_len = lun_list_len + 8; 14538 14539 } while (retry < 3); 14540 14541 if (ret != DDI_SUCCESS) 14542 return (ret); 14543 buffer = (char *)repluns_bp->b_un.b_addr; 14544 /* 14545 * find out the number of luns returned by the SCSI ReportLun call 14546 * and allocate buffer space 14547 */ 14548 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14549 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP); 14550 if (saved_repluns == NULL) { 14551 scsi_free_consistent_buf(repluns_bp); 14552 return (DDI_FAILURE); 14553 } 14554 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) { 14555 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer), 14556 &lun_num, &lun_addr_type) != DDI_SUCCESS) { 14557 continue; 14558 } 14559 saved_repluns[lun_cnt] = lun_num; 14560 if ((cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) != 14561 NULL) { 14562 ret = DDI_SUCCESS; 14563 } else { 14564 ret = mptsas_probe_lun(pdip, lun_num, &cdip, 14565 ptgt); 14566 } 14567 if ((ret == DDI_SUCCESS) && (cdip != NULL)) { 14568 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, 14569 MPTSAS_DEV_GONE); 14570 } 14571 } 14572 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt); 14573 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total); 14574 scsi_free_consistent_buf(repluns_bp); 14575 return (DDI_SUCCESS); 14576 } 14577 14578 static int 14579 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip) 14580 { 14581 int rval = DDI_FAILURE; 14582 struct scsi_inquiry *sd_inq = NULL; 14583 mptsas_t *mpt = DIP2MPT(pdip); 14584 mptsas_target_t *ptgt = NULL; 14585 14586 mutex_enter(&mpt->m_mutex); 14587 ptgt = refhash_linear_search(mpt->m_targets, 14588 mptsas_target_eval_devhdl, &target); 14589 mutex_exit(&mpt->m_mutex); 14590 if (ptgt == NULL) { 14591 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x " 14592 "not found.", target); 14593 return (rval); 14594 } 14595 14596 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14597 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq, 14598 SUN_INQSIZE, 0, (uchar_t)0); 14599 14600 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14601 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt, 14602 0); 14603 } else { 14604 rval = DDI_FAILURE; 14605 } 14606 14607 kmem_free(sd_inq, SUN_INQSIZE); 14608 return (rval); 14609 } 14610 14611 /* 14612 * configure all RAID volumes for virtual iport 14613 */ 14614 static void 14615 mptsas_config_all_viport(dev_info_t *pdip) 14616 { 14617 mptsas_t *mpt = DIP2MPT(pdip); 14618 int config, vol; 14619 int target; 14620 dev_info_t *lundip = NULL; 14621 14622 /* 14623 * Get latest RAID info and search for any Volume DevHandles. If any 14624 * are found, configure the volume. 14625 */ 14626 mutex_enter(&mpt->m_mutex); 14627 for (config = 0; config < mpt->m_num_raid_configs; config++) { 14628 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 14629 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid 14630 == 1) { 14631 target = mpt->m_raidconfig[config]. 14632 m_raidvol[vol].m_raidhandle; 14633 mutex_exit(&mpt->m_mutex); 14634 (void) mptsas_config_raid(pdip, target, 14635 &lundip); 14636 mutex_enter(&mpt->m_mutex); 14637 } 14638 } 14639 } 14640 mutex_exit(&mpt->m_mutex); 14641 } 14642 14643 static void 14644 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns, 14645 int lun_cnt, mptsas_target_t *ptgt) 14646 { 14647 dev_info_t *child = NULL, *savechild = NULL; 14648 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 14649 uint64_t sas_wwn, wwid; 14650 uint8_t phy; 14651 int lun; 14652 int i; 14653 int find; 14654 char *addr; 14655 char *nodename; 14656 mptsas_t *mpt = DIP2MPT(pdip); 14657 14658 mutex_enter(&mpt->m_mutex); 14659 wwid = ptgt->m_addr.mta_wwn; 14660 mutex_exit(&mpt->m_mutex); 14661 14662 child = ddi_get_child(pdip); 14663 while (child) { 14664 find = 0; 14665 savechild = child; 14666 child = ddi_get_next_sibling(child); 14667 14668 nodename = ddi_node_name(savechild); 14669 if (strcmp(nodename, "smp") == 0) { 14670 continue; 14671 } 14672 14673 addr = ddi_get_name_addr(savechild); 14674 if (addr == NULL) { 14675 continue; 14676 } 14677 14678 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) != 14679 DDI_SUCCESS) { 14680 continue; 14681 } 14682 14683 if (wwid == sas_wwn) { 14684 for (i = 0; i < lun_cnt; i++) { 14685 if (repluns[i] == lun) { 14686 find = 1; 14687 break; 14688 } 14689 } 14690 } else { 14691 continue; 14692 } 14693 if (find == 0) { 14694 /* 14695 * The lun has not been there already 14696 */ 14697 (void) mptsas_offline_lun(pdip, savechild, NULL, 14698 NDI_DEVI_REMOVE); 14699 } 14700 } 14701 14702 pip = mdi_get_next_client_path(pdip, NULL); 14703 while (pip) { 14704 find = 0; 14705 savepip = pip; 14706 addr = MDI_PI(pip)->pi_addr; 14707 14708 pip = mdi_get_next_client_path(pdip, pip); 14709 14710 if (addr == NULL) { 14711 continue; 14712 } 14713 14714 if (mptsas_parse_address(addr, &sas_wwn, &phy, 14715 &lun) != DDI_SUCCESS) { 14716 continue; 14717 } 14718 14719 if (sas_wwn == wwid) { 14720 for (i = 0; i < lun_cnt; i++) { 14721 if (repluns[i] == lun) { 14722 find = 1; 14723 break; 14724 } 14725 } 14726 } else { 14727 continue; 14728 } 14729 14730 if (find == 0) { 14731 /* 14732 * The lun has not been there already 14733 */ 14734 (void) mptsas_offline_lun(pdip, NULL, savepip, 14735 NDI_DEVI_REMOVE); 14736 } 14737 } 14738 } 14739 14740 /* 14741 * If this enclosure doesn't exist in the enclosure list, add it. If it does, 14742 * update it. 14743 */ 14744 static void 14745 mptsas_enclosure_update(mptsas_t *mpt, mptsas_enclosure_t *mep) 14746 { 14747 mptsas_enclosure_t *m; 14748 14749 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14750 m = mptsas_enc_lookup(mpt, mep->me_enchdl); 14751 if (m != NULL) { 14752 m->me_flags = mep->me_flags; 14753 return; 14754 } 14755 14756 m = kmem_zalloc(sizeof (*m), KM_SLEEP); 14757 m->me_enchdl = mep->me_enchdl; 14758 m->me_flags = mep->me_flags; 14759 list_insert_tail(&mpt->m_enclosures, m); 14760 } 14761 14762 static void 14763 mptsas_update_hashtab(struct mptsas *mpt) 14764 { 14765 uint32_t page_address; 14766 int rval = 0; 14767 uint16_t dev_handle; 14768 mptsas_target_t *ptgt = NULL; 14769 mptsas_smp_t smp_node; 14770 14771 /* 14772 * Get latest RAID info. 14773 */ 14774 (void) mptsas_get_raid_info(mpt); 14775 14776 dev_handle = mpt->m_smp_devhdl; 14777 while (mpt->m_done_traverse_smp == 0) { 14778 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 14779 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14780 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node) 14781 != DDI_SUCCESS) { 14782 break; 14783 } 14784 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl; 14785 (void) mptsas_smp_alloc(mpt, &smp_node); 14786 } 14787 14788 /* 14789 * Loop over enclosures so we can understand what's there. 14790 */ 14791 dev_handle = MPTSAS_INVALID_DEVHDL; 14792 while (mpt->m_done_traverse_enc == 0) { 14793 mptsas_enclosure_t me; 14794 14795 page_address = (MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE & 14796 MPI2_SAS_ENCLOS_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14797 14798 if (mptsas_get_enclosure_page0(mpt, page_address, &me) != 14799 DDI_SUCCESS) { 14800 break; 14801 } 14802 dev_handle = me.me_enchdl; 14803 mptsas_enclosure_update(mpt, &me); 14804 } 14805 14806 /* 14807 * Config target devices 14808 */ 14809 dev_handle = mpt->m_dev_handle; 14810 14811 /* 14812 * Loop to get sas device page 0 by GetNextHandle till the 14813 * the last handle. If the sas device is a SATA/SSP target, 14814 * we try to config it. 14815 */ 14816 while (mpt->m_done_traverse_dev == 0) { 14817 ptgt = NULL; 14818 page_address = 14819 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 14820 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14821 (uint32_t)dev_handle; 14822 rval = mptsas_get_target_device_info(mpt, page_address, 14823 &dev_handle, &ptgt); 14824 if ((rval == DEV_INFO_FAIL_PAGE0) || 14825 (rval == DEV_INFO_FAIL_ALLOC) || 14826 (rval == DEV_INFO_FAIL_GUID)) { 14827 break; 14828 } 14829 14830 mpt->m_dev_handle = dev_handle; 14831 } 14832 14833 } 14834 14835 void 14836 mptsas_update_driver_data(struct mptsas *mpt) 14837 { 14838 mptsas_target_t *tp; 14839 mptsas_smp_t *sp; 14840 14841 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14842 14843 /* 14844 * TODO after hard reset, update the driver data structures 14845 * 1. update port/phymask mapping table mpt->m_phy_info 14846 * 2. invalid all the entries in hash table 14847 * m_devhdl = 0xffff and m_deviceinfo = 0 14848 * 3. call sas_device_page/expander_page to update hash table 14849 */ 14850 mptsas_update_phymask(mpt); 14851 14852 /* 14853 * Remove all the devhdls for existing entries but leave their 14854 * addresses alone. In update_hashtab() below, we'll find all 14855 * targets that are still present and reassociate them with 14856 * their potentially new devhdls. Leaving the targets around in 14857 * this fashion allows them to be used on the tx waitq even 14858 * while IOC reset is occurring. 14859 */ 14860 for (tp = refhash_first(mpt->m_targets); tp != NULL; 14861 tp = refhash_next(mpt->m_targets, tp)) { 14862 tp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14863 tp->m_deviceinfo = 0; 14864 tp->m_dr_flag = MPTSAS_DR_INACTIVE; 14865 } 14866 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 14867 sp = refhash_next(mpt->m_smp_targets, sp)) { 14868 sp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14869 sp->m_deviceinfo = 0; 14870 } 14871 mpt->m_done_traverse_dev = 0; 14872 mpt->m_done_traverse_smp = 0; 14873 mpt->m_done_traverse_enc = 0; 14874 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL; 14875 mptsas_update_hashtab(mpt); 14876 } 14877 14878 static void 14879 mptsas_config_all(dev_info_t *pdip) 14880 { 14881 dev_info_t *smpdip = NULL; 14882 mptsas_t *mpt = DIP2MPT(pdip); 14883 int phymask = 0; 14884 mptsas_phymask_t phy_mask; 14885 mptsas_target_t *ptgt = NULL; 14886 mptsas_smp_t *psmp; 14887 14888 /* 14889 * Get the phymask associated to the iport 14890 */ 14891 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14892 "phymask", 0); 14893 14894 /* 14895 * Enumerate RAID volumes here (phymask == 0). 14896 */ 14897 if (phymask == 0) { 14898 mptsas_config_all_viport(pdip); 14899 return; 14900 } 14901 14902 mutex_enter(&mpt->m_mutex); 14903 14904 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp || 14905 !mpt->m_done_traverse_enc) { 14906 mptsas_update_hashtab(mpt); 14907 } 14908 14909 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL; 14910 psmp = refhash_next(mpt->m_smp_targets, psmp)) { 14911 phy_mask = psmp->m_addr.mta_phymask; 14912 if (phy_mask == phymask) { 14913 smpdip = NULL; 14914 mutex_exit(&mpt->m_mutex); 14915 (void) mptsas_online_smp(pdip, psmp, &smpdip); 14916 mutex_enter(&mpt->m_mutex); 14917 } 14918 } 14919 14920 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 14921 ptgt = refhash_next(mpt->m_targets, ptgt)) { 14922 phy_mask = ptgt->m_addr.mta_phymask; 14923 if (phy_mask == phymask) { 14924 mutex_exit(&mpt->m_mutex); 14925 (void) mptsas_config_target(pdip, ptgt); 14926 mutex_enter(&mpt->m_mutex); 14927 } 14928 } 14929 mutex_exit(&mpt->m_mutex); 14930 } 14931 14932 static int 14933 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt) 14934 { 14935 int rval = DDI_FAILURE; 14936 dev_info_t *tdip; 14937 14938 rval = mptsas_config_luns(pdip, ptgt); 14939 if (rval != DDI_SUCCESS) { 14940 /* 14941 * The return value means the SCMD_REPORT_LUNS 14942 * did not execute successfully. The target maybe 14943 * doesn't support such command. 14944 */ 14945 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt); 14946 } 14947 return (rval); 14948 } 14949 14950 /* 14951 * Return fail if not all the childs/paths are freed. 14952 * if there is any path under the HBA, the return value will be always fail 14953 * because we didn't call mdi_pi_free for path 14954 */ 14955 static int 14956 mptsas_offline_target(dev_info_t *pdip, char *name) 14957 { 14958 dev_info_t *child = NULL, *prechild = NULL; 14959 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 14960 int tmp_rval, rval = DDI_SUCCESS; 14961 char *addr, *cp; 14962 size_t s; 14963 mptsas_t *mpt = DIP2MPT(pdip); 14964 14965 child = ddi_get_child(pdip); 14966 while (child) { 14967 addr = ddi_get_name_addr(child); 14968 prechild = child; 14969 child = ddi_get_next_sibling(child); 14970 14971 if (addr == NULL) { 14972 continue; 14973 } 14974 if ((cp = strchr(addr, ',')) == NULL) { 14975 continue; 14976 } 14977 14978 s = (uintptr_t)cp - (uintptr_t)addr; 14979 14980 if (strncmp(addr, name, s) != 0) { 14981 continue; 14982 } 14983 14984 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL, 14985 NDI_DEVI_REMOVE); 14986 if (tmp_rval != DDI_SUCCESS) { 14987 rval = DDI_FAILURE; 14988 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 14989 prechild, MPTSAS_DEV_GONE) != 14990 DDI_PROP_SUCCESS) { 14991 mptsas_log(mpt, CE_WARN, "mptsas driver " 14992 "unable to create property for " 14993 "SAS %s (MPTSAS_DEV_GONE)", addr); 14994 } 14995 } 14996 } 14997 14998 pip = mdi_get_next_client_path(pdip, NULL); 14999 while (pip) { 15000 addr = MDI_PI(pip)->pi_addr; 15001 savepip = pip; 15002 pip = mdi_get_next_client_path(pdip, pip); 15003 if (addr == NULL) { 15004 continue; 15005 } 15006 15007 if ((cp = strchr(addr, ',')) == NULL) { 15008 continue; 15009 } 15010 15011 s = (uintptr_t)cp - (uintptr_t)addr; 15012 15013 if (strncmp(addr, name, s) != 0) { 15014 continue; 15015 } 15016 15017 (void) mptsas_offline_lun(pdip, NULL, savepip, 15018 NDI_DEVI_REMOVE); 15019 /* 15020 * driver will not invoke mdi_pi_free, so path will not 15021 * be freed forever, return DDI_FAILURE. 15022 */ 15023 rval = DDI_FAILURE; 15024 } 15025 return (rval); 15026 } 15027 15028 static int 15029 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 15030 mdi_pathinfo_t *rpip, uint_t flags) 15031 { 15032 int rval = DDI_FAILURE; 15033 char *devname; 15034 dev_info_t *cdip, *parent; 15035 15036 if (rpip != NULL) { 15037 parent = scsi_vhci_dip; 15038 cdip = mdi_pi_get_client(rpip); 15039 } else if (rdip != NULL) { 15040 parent = pdip; 15041 cdip = rdip; 15042 } else { 15043 return (DDI_FAILURE); 15044 } 15045 15046 /* 15047 * Make sure node is attached otherwise 15048 * it won't have related cache nodes to 15049 * clean up. i_ddi_devi_attached is 15050 * similiar to i_ddi_node_state(cdip) >= 15051 * DS_ATTACHED. 15052 */ 15053 if (i_ddi_devi_attached(cdip)) { 15054 15055 /* Get full devname */ 15056 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 15057 (void) ddi_deviname(cdip, devname); 15058 /* Clean cache */ 15059 (void) devfs_clean(parent, devname + 1, 15060 DV_CLEAN_FORCE); 15061 kmem_free(devname, MAXNAMELEN + 1); 15062 } 15063 if (rpip != NULL) { 15064 if (MDI_PI_IS_OFFLINE(rpip)) { 15065 rval = DDI_SUCCESS; 15066 } else { 15067 rval = mdi_pi_offline(rpip, 0); 15068 } 15069 } else { 15070 rval = ndi_devi_offline(cdip, flags); 15071 } 15072 15073 return (rval); 15074 } 15075 15076 static dev_info_t * 15077 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn) 15078 { 15079 dev_info_t *child = NULL; 15080 char *smp_wwn = NULL; 15081 15082 child = ddi_get_child(parent); 15083 while (child) { 15084 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child, 15085 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn) 15086 != DDI_SUCCESS) { 15087 child = ddi_get_next_sibling(child); 15088 continue; 15089 } 15090 15091 if (strcmp(smp_wwn, str_wwn) == 0) { 15092 ddi_prop_free(smp_wwn); 15093 break; 15094 } 15095 child = ddi_get_next_sibling(child); 15096 ddi_prop_free(smp_wwn); 15097 } 15098 return (child); 15099 } 15100 15101 static int 15102 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags) 15103 { 15104 int rval = DDI_FAILURE; 15105 char *devname; 15106 char wwn_str[MPTSAS_WWN_STRLEN]; 15107 dev_info_t *cdip; 15108 15109 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 15110 15111 cdip = mptsas_find_smp_child(pdip, wwn_str); 15112 15113 if (cdip == NULL) 15114 return (DDI_SUCCESS); 15115 15116 /* 15117 * Make sure node is attached otherwise 15118 * it won't have related cache nodes to 15119 * clean up. i_ddi_devi_attached is 15120 * similiar to i_ddi_node_state(cdip) >= 15121 * DS_ATTACHED. 15122 */ 15123 if (i_ddi_devi_attached(cdip)) { 15124 15125 /* Get full devname */ 15126 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 15127 (void) ddi_deviname(cdip, devname); 15128 /* Clean cache */ 15129 (void) devfs_clean(pdip, devname + 1, 15130 DV_CLEAN_FORCE); 15131 kmem_free(devname, MAXNAMELEN + 1); 15132 } 15133 15134 rval = ndi_devi_offline(cdip, flags); 15135 15136 return (rval); 15137 } 15138 15139 static dev_info_t * 15140 mptsas_find_child(dev_info_t *pdip, char *name) 15141 { 15142 dev_info_t *child = NULL; 15143 char *rname = NULL; 15144 int rval = DDI_FAILURE; 15145 15146 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15147 15148 child = ddi_get_child(pdip); 15149 while (child) { 15150 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN); 15151 if (rval != DDI_SUCCESS) { 15152 child = ddi_get_next_sibling(child); 15153 bzero(rname, SCSI_MAXNAMELEN); 15154 continue; 15155 } 15156 15157 if (strcmp(rname, name) == 0) { 15158 break; 15159 } 15160 child = ddi_get_next_sibling(child); 15161 bzero(rname, SCSI_MAXNAMELEN); 15162 } 15163 15164 kmem_free(rname, SCSI_MAXNAMELEN); 15165 15166 return (child); 15167 } 15168 15169 15170 static dev_info_t * 15171 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun) 15172 { 15173 dev_info_t *child = NULL; 15174 char *name = NULL; 15175 char *addr = NULL; 15176 15177 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15178 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15179 (void) sprintf(name, "%016"PRIx64, sasaddr); 15180 (void) sprintf(addr, "w%s,%x", name, lun); 15181 child = mptsas_find_child(pdip, addr); 15182 kmem_free(name, SCSI_MAXNAMELEN); 15183 kmem_free(addr, SCSI_MAXNAMELEN); 15184 return (child); 15185 } 15186 15187 static dev_info_t * 15188 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy) 15189 { 15190 dev_info_t *child; 15191 char *addr; 15192 15193 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15194 (void) sprintf(addr, "p%x,0", phy); 15195 child = mptsas_find_child(pdip, addr); 15196 kmem_free(addr, SCSI_MAXNAMELEN); 15197 return (child); 15198 } 15199 15200 static mdi_pathinfo_t * 15201 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy) 15202 { 15203 mdi_pathinfo_t *path; 15204 char *addr = NULL; 15205 15206 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15207 (void) sprintf(addr, "p%x,0", phy); 15208 path = mdi_pi_find(pdip, NULL, addr); 15209 kmem_free(addr, SCSI_MAXNAMELEN); 15210 return (path); 15211 } 15212 15213 static mdi_pathinfo_t * 15214 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun) 15215 { 15216 mdi_pathinfo_t *path; 15217 char *name = NULL; 15218 char *addr = NULL; 15219 15220 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15221 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15222 (void) sprintf(name, "%016"PRIx64, sasaddr); 15223 (void) sprintf(addr, "w%s,%x", name, lun); 15224 path = mdi_pi_find(parent, NULL, addr); 15225 kmem_free(name, SCSI_MAXNAMELEN); 15226 kmem_free(addr, SCSI_MAXNAMELEN); 15227 15228 return (path); 15229 } 15230 15231 static int 15232 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 15233 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15234 { 15235 int i = 0; 15236 uchar_t *inq83 = NULL; 15237 int inq83_len1 = 0xFF; 15238 int inq83_len = 0; 15239 int rval = DDI_FAILURE; 15240 ddi_devid_t devid; 15241 char *guid = NULL; 15242 int target = ptgt->m_devhdl; 15243 mdi_pathinfo_t *pip = NULL; 15244 mptsas_t *mpt = DIP2MPT(pdip); 15245 15246 /* 15247 * For DVD/CD ROM and tape devices and optical 15248 * devices, we won't try to enumerate them under 15249 * scsi_vhci, so no need to try page83 15250 */ 15251 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT || 15252 sd_inq->inq_dtype == DTYPE_OPTICAL || 15253 sd_inq->inq_dtype == DTYPE_ESI)) 15254 goto create_lun; 15255 15256 /* 15257 * The LCA returns good SCSI status, but corrupt page 83 data the first 15258 * time it is queried. The solution is to keep trying to request page83 15259 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in 15260 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver 15261 * give up to get VPD page at this stage and fail the enumeration. 15262 */ 15263 15264 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP); 15265 15266 for (i = 0; i < mptsas_inq83_retry_timeout; i++) { 15267 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 15268 inq83_len1, &inq83_len, 1); 15269 if (rval != 0) { 15270 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 15271 "0x83 for target:%x, lun:%x failed!", target, lun); 15272 if (mptsas_physical_bind_failed_page_83 != B_FALSE) 15273 goto create_lun; 15274 goto out; 15275 } 15276 /* 15277 * create DEVID from inquiry data 15278 */ 15279 if ((rval = ddi_devid_scsi_encode( 15280 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq, 15281 sizeof (struct scsi_inquiry), NULL, 0, inq83, 15282 (size_t)inq83_len, &devid)) == DDI_SUCCESS) { 15283 /* 15284 * extract GUID from DEVID 15285 */ 15286 guid = ddi_devid_to_guid(devid); 15287 15288 /* 15289 * Do not enable MPXIO if the strlen(guid) is greater 15290 * than MPTSAS_MAX_GUID_LEN, this constrain would be 15291 * handled by framework later. 15292 */ 15293 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) { 15294 ddi_devid_free_guid(guid); 15295 guid = NULL; 15296 if (mpt->m_mpxio_enable == TRUE) { 15297 mptsas_log(mpt, CE_NOTE, "!Target:%x, " 15298 "lun:%x doesn't have a valid GUID, " 15299 "multipathing for this drive is " 15300 "not enabled", target, lun); 15301 } 15302 } 15303 15304 /* 15305 * devid no longer needed 15306 */ 15307 ddi_devid_free(devid); 15308 break; 15309 } else if (rval == DDI_NOT_WELL_FORMED) { 15310 /* 15311 * return value of ddi_devid_scsi_encode equal to 15312 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth 15313 * to retry inquiry page 0x83 and get GUID. 15314 */ 15315 NDBG20(("Not well formed devid, retry...")); 15316 delay(1 * drv_usectohz(1000000)); 15317 continue; 15318 } else { 15319 mptsas_log(mpt, CE_WARN, "!Encode devid failed for " 15320 "path target:%x, lun:%x", target, lun); 15321 rval = DDI_FAILURE; 15322 goto create_lun; 15323 } 15324 } 15325 15326 if (i == mptsas_inq83_retry_timeout) { 15327 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout " 15328 "for path target:%x, lun:%x", target, lun); 15329 } 15330 15331 rval = DDI_FAILURE; 15332 15333 create_lun: 15334 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) { 15335 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip, 15336 ptgt, lun); 15337 } 15338 if (rval != DDI_SUCCESS) { 15339 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip, 15340 ptgt, lun); 15341 15342 } 15343 out: 15344 if (guid != NULL) { 15345 /* 15346 * guid no longer needed 15347 */ 15348 ddi_devid_free_guid(guid); 15349 } 15350 if (inq83 != NULL) 15351 kmem_free(inq83, inq83_len1); 15352 return (rval); 15353 } 15354 15355 static int 15356 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid, 15357 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun) 15358 { 15359 int target; 15360 char *nodename = NULL; 15361 char **compatible = NULL; 15362 int ncompatible = 0; 15363 int mdi_rtn = MDI_FAILURE; 15364 int rval = DDI_FAILURE; 15365 char *old_guid = NULL; 15366 mptsas_t *mpt = DIP2MPT(pdip); 15367 char *lun_addr = NULL; 15368 char *wwn_str = NULL; 15369 char *attached_wwn_str = NULL; 15370 char *component = NULL; 15371 uint8_t phy = 0xFF; 15372 uint64_t sas_wwn; 15373 int64_t lun64 = 0; 15374 uint32_t devinfo; 15375 uint16_t dev_hdl; 15376 uint16_t pdev_hdl; 15377 uint64_t dev_sas_wwn; 15378 uint64_t pdev_sas_wwn; 15379 uint32_t pdev_info; 15380 uint8_t physport; 15381 uint8_t phy_id; 15382 uint32_t page_address; 15383 uint16_t bay_num, enclosure, io_flags; 15384 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15385 uint32_t dev_info; 15386 15387 mutex_enter(&mpt->m_mutex); 15388 target = ptgt->m_devhdl; 15389 sas_wwn = ptgt->m_addr.mta_wwn; 15390 devinfo = ptgt->m_deviceinfo; 15391 phy = ptgt->m_phynum; 15392 mutex_exit(&mpt->m_mutex); 15393 15394 if (sas_wwn) { 15395 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun); 15396 } else { 15397 *pip = mptsas_find_path_phy(pdip, phy); 15398 } 15399 15400 if (*pip != NULL) { 15401 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15402 ASSERT(*lun_dip != NULL); 15403 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip, 15404 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM), 15405 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) { 15406 if (strncmp(guid, old_guid, strlen(guid)) == 0) { 15407 /* 15408 * Same path back online again. 15409 */ 15410 (void) ddi_prop_free(old_guid); 15411 if ((!MDI_PI_IS_ONLINE(*pip)) && 15412 (!MDI_PI_IS_STANDBY(*pip)) && 15413 (ptgt->m_tgt_unconfigured == 0)) { 15414 rval = mdi_pi_online(*pip, 0); 15415 mutex_enter(&mpt->m_mutex); 15416 ptgt->m_led_status = 0; 15417 (void) mptsas_flush_led_status(mpt, 15418 ptgt); 15419 mutex_exit(&mpt->m_mutex); 15420 } else { 15421 rval = DDI_SUCCESS; 15422 } 15423 if (rval != DDI_SUCCESS) { 15424 mptsas_log(mpt, CE_WARN, "path:target: " 15425 "%x, lun:%x online failed!", target, 15426 lun); 15427 *pip = NULL; 15428 *lun_dip = NULL; 15429 } 15430 return (rval); 15431 } else { 15432 /* 15433 * The GUID of the LUN has changed which maybe 15434 * because customer mapped another volume to the 15435 * same LUN. 15436 */ 15437 mptsas_log(mpt, CE_WARN, "The GUID of the " 15438 "target:%x, lun:%x was changed, maybe " 15439 "because someone mapped another volume " 15440 "to the same LUN", target, lun); 15441 (void) ddi_prop_free(old_guid); 15442 if (!MDI_PI_IS_OFFLINE(*pip)) { 15443 rval = mdi_pi_offline(*pip, 0); 15444 if (rval != MDI_SUCCESS) { 15445 mptsas_log(mpt, CE_WARN, "path:" 15446 "target:%x, lun:%x offline " 15447 "failed!", target, lun); 15448 *pip = NULL; 15449 *lun_dip = NULL; 15450 return (DDI_FAILURE); 15451 } 15452 } 15453 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) { 15454 mptsas_log(mpt, CE_WARN, "path:target:" 15455 "%x, lun:%x free failed!", target, 15456 lun); 15457 *pip = NULL; 15458 *lun_dip = NULL; 15459 return (DDI_FAILURE); 15460 } 15461 } 15462 } else { 15463 mptsas_log(mpt, CE_WARN, "Can't get client-guid " 15464 "property for path:target:%x, lun:%x", target, lun); 15465 *pip = NULL; 15466 *lun_dip = NULL; 15467 return (DDI_FAILURE); 15468 } 15469 } 15470 scsi_hba_nodename_compatible_get(inq, NULL, 15471 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible); 15472 15473 /* 15474 * if nodename can't be determined then print a message and skip it 15475 */ 15476 if (nodename == NULL) { 15477 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible " 15478 "driver for target%d lun %d dtype:0x%02x", target, lun, 15479 inq->inq_dtype); 15480 return (DDI_FAILURE); 15481 } 15482 15483 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15484 /* The property is needed by MPAPI */ 15485 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 15486 15487 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15488 if (guid) { 15489 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun); 15490 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15491 } else { 15492 (void) sprintf(lun_addr, "p%x,%x", phy, lun); 15493 (void) sprintf(wwn_str, "p%x", phy); 15494 } 15495 15496 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename, 15497 guid, lun_addr, compatible, ncompatible, 15498 0, pip); 15499 if (mdi_rtn == MDI_SUCCESS) { 15500 15501 if (mdi_prop_update_string(*pip, MDI_GUID, 15502 guid) != DDI_SUCCESS) { 15503 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15504 "create prop for target %d lun %d (MDI_GUID)", 15505 target, lun); 15506 mdi_rtn = MDI_FAILURE; 15507 goto virt_create_done; 15508 } 15509 15510 if (mdi_prop_update_int(*pip, LUN_PROP, 15511 lun) != DDI_SUCCESS) { 15512 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15513 "create prop for target %d lun %d (LUN_PROP)", 15514 target, lun); 15515 mdi_rtn = MDI_FAILURE; 15516 goto virt_create_done; 15517 } 15518 lun64 = (int64_t)lun; 15519 if (mdi_prop_update_int64(*pip, LUN64_PROP, 15520 lun64) != DDI_SUCCESS) { 15521 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15522 "create prop for target %d (LUN64_PROP)", 15523 target); 15524 mdi_rtn = MDI_FAILURE; 15525 goto virt_create_done; 15526 } 15527 if (mdi_prop_update_string_array(*pip, "compatible", 15528 compatible, ncompatible) != 15529 DDI_PROP_SUCCESS) { 15530 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15531 "create prop for target %d lun %d (COMPATIBLE)", 15532 target, lun); 15533 mdi_rtn = MDI_FAILURE; 15534 goto virt_create_done; 15535 } 15536 if (sas_wwn && (mdi_prop_update_string(*pip, 15537 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) { 15538 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15539 "create prop for target %d lun %d " 15540 "(target-port)", target, lun); 15541 mdi_rtn = MDI_FAILURE; 15542 goto virt_create_done; 15543 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip, 15544 "sata-phy", phy) != DDI_PROP_SUCCESS)) { 15545 /* 15546 * Direct attached SATA device without DeviceName 15547 */ 15548 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15549 "create prop for SAS target %d lun %d " 15550 "(sata-phy)", target, lun); 15551 mdi_rtn = MDI_FAILURE; 15552 goto virt_create_done; 15553 } 15554 mutex_enter(&mpt->m_mutex); 15555 15556 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15557 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15558 (uint32_t)ptgt->m_devhdl; 15559 rval = mptsas_get_sas_device_page0(mpt, page_address, 15560 &dev_hdl, &dev_sas_wwn, &dev_info, &physport, 15561 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15562 if (rval != DDI_SUCCESS) { 15563 mutex_exit(&mpt->m_mutex); 15564 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 15565 "parent device for handle %d", page_address); 15566 mdi_rtn = MDI_FAILURE; 15567 goto virt_create_done; 15568 } 15569 15570 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15571 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15572 rval = mptsas_get_sas_device_page0(mpt, page_address, 15573 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15574 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15575 if (rval != DDI_SUCCESS) { 15576 mutex_exit(&mpt->m_mutex); 15577 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15578 "device info for handle %d", page_address); 15579 mdi_rtn = MDI_FAILURE; 15580 goto virt_create_done; 15581 } 15582 15583 mutex_exit(&mpt->m_mutex); 15584 15585 /* 15586 * If this device direct attached to the controller 15587 * set the attached-port to the base wwid 15588 */ 15589 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15590 != DEVINFO_DIRECT_ATTACHED) { 15591 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15592 pdev_sas_wwn); 15593 } else { 15594 /* 15595 * Update the iport's attached-port to guid 15596 */ 15597 if (sas_wwn == 0) { 15598 (void) sprintf(wwn_str, "p%x", phy); 15599 } else { 15600 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15601 } 15602 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15603 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15604 DDI_PROP_SUCCESS) { 15605 mptsas_log(mpt, CE_WARN, 15606 "mptsas unable to create " 15607 "property for iport target-port" 15608 " %s (sas_wwn)", 15609 wwn_str); 15610 mdi_rtn = MDI_FAILURE; 15611 goto virt_create_done; 15612 } 15613 15614 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15615 mpt->un.m_base_wwid); 15616 } 15617 15618 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) { 15619 char uabuf[SCSI_WWN_BUFLEN]; 15620 15621 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 15622 mptsas_log(mpt, CE_WARN, 15623 "mptsas unable to format SATA bridge WWN"); 15624 mdi_rtn = MDI_FAILURE; 15625 goto virt_create_done; 15626 } 15627 15628 if (mdi_prop_update_string(*pip, 15629 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != 15630 DDI_SUCCESS) { 15631 mptsas_log(mpt, CE_WARN, 15632 "mptsas unable to create SCSI bridge port " 15633 "property for SATA device"); 15634 mdi_rtn = MDI_FAILURE; 15635 goto virt_create_done; 15636 } 15637 } 15638 15639 if (mdi_prop_update_string(*pip, 15640 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 15641 DDI_PROP_SUCCESS) { 15642 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15643 "property for iport attached-port %s (sas_wwn)", 15644 attached_wwn_str); 15645 mdi_rtn = MDI_FAILURE; 15646 goto virt_create_done; 15647 } 15648 15649 15650 if (inq->inq_dtype == 0) { 15651 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 15652 /* 15653 * set obp path for pathinfo 15654 */ 15655 (void) snprintf(component, MAXPATHLEN, 15656 "disk@%s", lun_addr); 15657 15658 if (mdi_pi_pathname_obp_set(*pip, component) != 15659 DDI_SUCCESS) { 15660 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 15661 "unable to set obp-path for object %s", 15662 component); 15663 mdi_rtn = MDI_FAILURE; 15664 goto virt_create_done; 15665 } 15666 } 15667 15668 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15669 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 15670 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 15671 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip, 15672 "pm-capable", 1)) != 15673 DDI_PROP_SUCCESS) { 15674 mptsas_log(mpt, CE_WARN, "mptsas driver" 15675 "failed to create pm-capable " 15676 "property, target %d", target); 15677 mdi_rtn = MDI_FAILURE; 15678 goto virt_create_done; 15679 } 15680 } 15681 /* 15682 * Create the phy-num property 15683 */ 15684 if (mdi_prop_update_int(*pip, "phy-num", 15685 ptgt->m_phynum) != DDI_SUCCESS) { 15686 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15687 "create phy-num property for target %d lun %d", 15688 target, lun); 15689 mdi_rtn = MDI_FAILURE; 15690 goto virt_create_done; 15691 } 15692 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr)); 15693 mdi_rtn = mdi_pi_online(*pip, 0); 15694 if (mdi_rtn == MDI_SUCCESS) { 15695 mutex_enter(&mpt->m_mutex); 15696 ptgt->m_led_status = 0; 15697 (void) mptsas_flush_led_status(mpt, ptgt); 15698 mutex_exit(&mpt->m_mutex); 15699 } 15700 if (mdi_rtn == MDI_NOT_SUPPORTED) { 15701 mdi_rtn = MDI_FAILURE; 15702 } 15703 virt_create_done: 15704 if (*pip && mdi_rtn != MDI_SUCCESS) { 15705 (void) mdi_pi_free(*pip, 0); 15706 *pip = NULL; 15707 *lun_dip = NULL; 15708 } 15709 } 15710 15711 scsi_hba_nodename_compatible_free(nodename, compatible); 15712 if (lun_addr != NULL) { 15713 kmem_free(lun_addr, SCSI_MAXNAMELEN); 15714 } 15715 if (wwn_str != NULL) { 15716 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 15717 } 15718 if (component != NULL) { 15719 kmem_free(component, MAXPATHLEN); 15720 } 15721 15722 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 15723 } 15724 15725 static int 15726 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq, 15727 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15728 { 15729 int target; 15730 int rval; 15731 int ndi_rtn = NDI_FAILURE; 15732 uint64_t be_sas_wwn; 15733 char *nodename = NULL; 15734 char **compatible = NULL; 15735 int ncompatible = 0; 15736 int instance = 0; 15737 mptsas_t *mpt = DIP2MPT(pdip); 15738 char *wwn_str = NULL; 15739 char *component = NULL; 15740 char *attached_wwn_str = NULL; 15741 uint8_t phy = 0xFF; 15742 uint64_t sas_wwn; 15743 uint32_t devinfo; 15744 uint16_t dev_hdl; 15745 uint16_t pdev_hdl; 15746 uint64_t pdev_sas_wwn; 15747 uint64_t dev_sas_wwn; 15748 uint32_t pdev_info; 15749 uint8_t physport; 15750 uint8_t phy_id; 15751 uint32_t page_address; 15752 uint16_t bay_num, enclosure, io_flags; 15753 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15754 uint32_t dev_info; 15755 int64_t lun64 = 0; 15756 15757 mutex_enter(&mpt->m_mutex); 15758 target = ptgt->m_devhdl; 15759 sas_wwn = ptgt->m_addr.mta_wwn; 15760 devinfo = ptgt->m_deviceinfo; 15761 phy = ptgt->m_phynum; 15762 mutex_exit(&mpt->m_mutex); 15763 15764 /* 15765 * generate compatible property with binding-set "mpt" 15766 */ 15767 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL, 15768 &nodename, &compatible, &ncompatible); 15769 15770 /* 15771 * if nodename can't be determined then print a message and skip it 15772 */ 15773 if (nodename == NULL) { 15774 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver " 15775 "for target %d lun %d", target, lun); 15776 return (DDI_FAILURE); 15777 } 15778 15779 ndi_rtn = ndi_devi_alloc(pdip, nodename, 15780 DEVI_SID_NODEID, lun_dip); 15781 15782 /* 15783 * if lun alloc success, set props 15784 */ 15785 if (ndi_rtn == NDI_SUCCESS) { 15786 15787 if (ndi_prop_update_int(DDI_DEV_T_NONE, 15788 *lun_dip, LUN_PROP, lun) != 15789 DDI_PROP_SUCCESS) { 15790 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15791 "property for target %d lun %d (LUN_PROP)", 15792 target, lun); 15793 ndi_rtn = NDI_FAILURE; 15794 goto phys_create_done; 15795 } 15796 15797 lun64 = (int64_t)lun; 15798 if (ndi_prop_update_int64(DDI_DEV_T_NONE, 15799 *lun_dip, LUN64_PROP, lun64) != 15800 DDI_PROP_SUCCESS) { 15801 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15802 "property for target %d lun64 %d (LUN64_PROP)", 15803 target, lun); 15804 ndi_rtn = NDI_FAILURE; 15805 goto phys_create_done; 15806 } 15807 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, 15808 *lun_dip, "compatible", compatible, ncompatible) 15809 != DDI_PROP_SUCCESS) { 15810 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15811 "property for target %d lun %d (COMPATIBLE)", 15812 target, lun); 15813 ndi_rtn = NDI_FAILURE; 15814 goto phys_create_done; 15815 } 15816 15817 /* 15818 * We need the SAS WWN for non-multipath devices, so 15819 * we'll use the same property as that multipathing 15820 * devices need to present for MPAPI. If we don't have 15821 * a WWN (e.g. parallel SCSI), don't create the prop. 15822 */ 15823 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15824 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15825 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE, 15826 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) 15827 != DDI_PROP_SUCCESS) { 15828 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15829 "create property for SAS target %d lun %d " 15830 "(target-port)", target, lun); 15831 ndi_rtn = NDI_FAILURE; 15832 goto phys_create_done; 15833 } 15834 15835 be_sas_wwn = BE_64(sas_wwn); 15836 if (sas_wwn && ndi_prop_update_byte_array( 15837 DDI_DEV_T_NONE, *lun_dip, "port-wwn", 15838 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) { 15839 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15840 "create property for SAS target %d lun %d " 15841 "(port-wwn)", target, lun); 15842 ndi_rtn = NDI_FAILURE; 15843 goto phys_create_done; 15844 } else if ((sas_wwn == 0) && (ndi_prop_update_int( 15845 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) != 15846 DDI_PROP_SUCCESS)) { 15847 /* 15848 * Direct attached SATA device without DeviceName 15849 */ 15850 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15851 "create property for SAS target %d lun %d " 15852 "(sata-phy)", target, lun); 15853 ndi_rtn = NDI_FAILURE; 15854 goto phys_create_done; 15855 } 15856 15857 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 15858 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) { 15859 mptsas_log(mpt, CE_WARN, "mptsas unable to" 15860 "create property for SAS target %d lun %d" 15861 " (SAS_PROP)", target, lun); 15862 ndi_rtn = NDI_FAILURE; 15863 goto phys_create_done; 15864 } 15865 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE, 15866 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) { 15867 mptsas_log(mpt, CE_WARN, "mptsas unable " 15868 "to create guid property for target %d " 15869 "lun %d", target, lun); 15870 ndi_rtn = NDI_FAILURE; 15871 goto phys_create_done; 15872 } 15873 15874 /* 15875 * The following code is to set properties for SM-HBA support, 15876 * it doesn't apply to RAID volumes 15877 */ 15878 if (ptgt->m_addr.mta_phymask == 0) 15879 goto phys_raid_lun; 15880 15881 mutex_enter(&mpt->m_mutex); 15882 15883 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15884 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15885 (uint32_t)ptgt->m_devhdl; 15886 rval = mptsas_get_sas_device_page0(mpt, page_address, 15887 &dev_hdl, &dev_sas_wwn, &dev_info, 15888 &physport, &phy_id, &pdev_hdl, 15889 &bay_num, &enclosure, &io_flags); 15890 if (rval != DDI_SUCCESS) { 15891 mutex_exit(&mpt->m_mutex); 15892 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15893 "parent device for handle %d.", page_address); 15894 ndi_rtn = NDI_FAILURE; 15895 goto phys_create_done; 15896 } 15897 15898 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15899 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15900 rval = mptsas_get_sas_device_page0(mpt, page_address, 15901 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15902 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15903 if (rval != DDI_SUCCESS) { 15904 mutex_exit(&mpt->m_mutex); 15905 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15906 "device for handle %d.", page_address); 15907 ndi_rtn = NDI_FAILURE; 15908 goto phys_create_done; 15909 } 15910 15911 mutex_exit(&mpt->m_mutex); 15912 15913 /* 15914 * If this device direct attached to the controller 15915 * set the attached-port to the base wwid 15916 */ 15917 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15918 != DEVINFO_DIRECT_ATTACHED) { 15919 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15920 pdev_sas_wwn); 15921 } else { 15922 /* 15923 * Update the iport's attached-port to guid 15924 */ 15925 if (sas_wwn == 0) { 15926 (void) sprintf(wwn_str, "p%x", phy); 15927 } else { 15928 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15929 } 15930 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15931 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15932 DDI_PROP_SUCCESS) { 15933 mptsas_log(mpt, CE_WARN, 15934 "mptsas unable to create " 15935 "property for iport target-port" 15936 " %s (sas_wwn)", 15937 wwn_str); 15938 ndi_rtn = NDI_FAILURE; 15939 goto phys_create_done; 15940 } 15941 15942 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15943 mpt->un.m_base_wwid); 15944 } 15945 15946 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15947 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 15948 DDI_PROP_SUCCESS) { 15949 mptsas_log(mpt, CE_WARN, 15950 "mptsas unable to create " 15951 "property for iport attached-port %s (sas_wwn)", 15952 attached_wwn_str); 15953 ndi_rtn = NDI_FAILURE; 15954 goto phys_create_done; 15955 } 15956 15957 if (IS_SATA_DEVICE(dev_info)) { 15958 char uabuf[SCSI_WWN_BUFLEN]; 15959 15960 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15961 *lun_dip, MPTSAS_VARIANT, "sata") != 15962 DDI_PROP_SUCCESS) { 15963 mptsas_log(mpt, CE_WARN, 15964 "mptsas unable to create " 15965 "property for device variant "); 15966 ndi_rtn = NDI_FAILURE; 15967 goto phys_create_done; 15968 } 15969 15970 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 15971 mptsas_log(mpt, CE_WARN, 15972 "mptsas unable to format SATA bridge WWN"); 15973 ndi_rtn = NDI_FAILURE; 15974 goto phys_create_done; 15975 } 15976 15977 if (ndi_prop_update_string(DDI_DEV_T_NONE, *lun_dip, 15978 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != 15979 DDI_PROP_SUCCESS) { 15980 mptsas_log(mpt, CE_WARN, 15981 "mptsas unable to create SCSI bridge port " 15982 "property for SATA device"); 15983 ndi_rtn = NDI_FAILURE; 15984 goto phys_create_done; 15985 } 15986 } 15987 15988 if (IS_ATAPI_DEVICE(dev_info)) { 15989 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15990 *lun_dip, MPTSAS_VARIANT, "atapi") != 15991 DDI_PROP_SUCCESS) { 15992 mptsas_log(mpt, CE_WARN, 15993 "mptsas unable to create " 15994 "property for device variant "); 15995 ndi_rtn = NDI_FAILURE; 15996 goto phys_create_done; 15997 } 15998 } 15999 16000 phys_raid_lun: 16001 /* 16002 * if this is a SAS controller, and the target is a SATA 16003 * drive, set the 'pm-capable' property for sd and if on 16004 * an OPL platform, also check if this is an ATAPI 16005 * device. 16006 */ 16007 instance = ddi_get_instance(mpt->m_dip); 16008 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 16009 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 16010 NDBG2(("mptsas%d: creating pm-capable property, " 16011 "target %d", instance, target)); 16012 16013 if ((ndi_prop_update_int(DDI_DEV_T_NONE, 16014 *lun_dip, "pm-capable", 1)) != 16015 DDI_PROP_SUCCESS) { 16016 mptsas_log(mpt, CE_WARN, "mptsas " 16017 "failed to create pm-capable " 16018 "property, target %d", target); 16019 ndi_rtn = NDI_FAILURE; 16020 goto phys_create_done; 16021 } 16022 16023 } 16024 16025 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) { 16026 /* 16027 * add 'obp-path' properties for devinfo 16028 */ 16029 bzero(wwn_str, sizeof (wwn_str)); 16030 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 16031 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 16032 if (guid) { 16033 (void) snprintf(component, MAXPATHLEN, 16034 "disk@w%s,%x", wwn_str, lun); 16035 } else { 16036 (void) snprintf(component, MAXPATHLEN, 16037 "disk@p%x,%x", phy, lun); 16038 } 16039 if (ddi_pathname_obp_set(*lun_dip, component) 16040 != DDI_SUCCESS) { 16041 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 16042 "unable to set obp-path for SAS " 16043 "object %s", component); 16044 ndi_rtn = NDI_FAILURE; 16045 goto phys_create_done; 16046 } 16047 } 16048 /* 16049 * Create the phy-num property for non-raid disk 16050 */ 16051 if (ptgt->m_addr.mta_phymask != 0) { 16052 if (ndi_prop_update_int(DDI_DEV_T_NONE, 16053 *lun_dip, "phy-num", ptgt->m_phynum) != 16054 DDI_PROP_SUCCESS) { 16055 mptsas_log(mpt, CE_WARN, "mptsas driver " 16056 "failed to create phy-num property for " 16057 "target %d", target); 16058 ndi_rtn = NDI_FAILURE; 16059 goto phys_create_done; 16060 } 16061 } 16062 phys_create_done: 16063 /* 16064 * If props were setup ok, online the lun 16065 */ 16066 if (ndi_rtn == NDI_SUCCESS) { 16067 /* 16068 * Try to online the new node 16069 */ 16070 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH); 16071 } 16072 if (ndi_rtn == NDI_SUCCESS) { 16073 mutex_enter(&mpt->m_mutex); 16074 ptgt->m_led_status = 0; 16075 (void) mptsas_flush_led_status(mpt, ptgt); 16076 mutex_exit(&mpt->m_mutex); 16077 } 16078 16079 /* 16080 * If success set rtn flag, else unwire alloc'd lun 16081 */ 16082 if (ndi_rtn != NDI_SUCCESS) { 16083 NDBG12(("mptsas driver unable to online " 16084 "target %d lun %d", target, lun)); 16085 ndi_prop_remove_all(*lun_dip); 16086 (void) ndi_devi_free(*lun_dip); 16087 *lun_dip = NULL; 16088 } 16089 } 16090 16091 scsi_hba_nodename_compatible_free(nodename, compatible); 16092 16093 if (wwn_str != NULL) { 16094 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 16095 } 16096 if (component != NULL) { 16097 kmem_free(component, MAXPATHLEN); 16098 } 16099 16100 16101 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 16102 } 16103 16104 static int 16105 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn) 16106 { 16107 mptsas_t *mpt = DIP2MPT(pdip); 16108 struct smp_device smp_sd; 16109 16110 /* XXX An HBA driver should not be allocating an smp_device. */ 16111 bzero(&smp_sd, sizeof (struct smp_device)); 16112 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran; 16113 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE); 16114 16115 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS) 16116 return (NDI_FAILURE); 16117 return (NDI_SUCCESS); 16118 } 16119 16120 static int 16121 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip) 16122 { 16123 mptsas_t *mpt = DIP2MPT(pdip); 16124 mptsas_smp_t *psmp = NULL; 16125 int rval; 16126 int phymask; 16127 16128 /* 16129 * Get the physical port associated to the iport 16130 * PHYMASK TODO 16131 */ 16132 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 16133 "phymask", 0); 16134 /* 16135 * Find the smp node in hash table with specified sas address and 16136 * physical port 16137 */ 16138 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn); 16139 if (psmp == NULL) { 16140 return (DDI_FAILURE); 16141 } 16142 16143 rval = mptsas_online_smp(pdip, psmp, smp_dip); 16144 16145 return (rval); 16146 } 16147 16148 static int 16149 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 16150 dev_info_t **smp_dip) 16151 { 16152 char wwn_str[MPTSAS_WWN_STRLEN]; 16153 char attached_wwn_str[MPTSAS_WWN_STRLEN]; 16154 int ndi_rtn = NDI_FAILURE; 16155 int rval = 0; 16156 mptsas_smp_t dev_info; 16157 uint32_t page_address; 16158 mptsas_t *mpt = DIP2MPT(pdip); 16159 uint16_t dev_hdl; 16160 uint64_t sas_wwn; 16161 uint64_t smp_sas_wwn; 16162 uint8_t physport; 16163 uint8_t phy_id; 16164 uint16_t pdev_hdl; 16165 uint8_t numphys = 0; 16166 uint16_t i = 0; 16167 char phymask[MPTSAS_MAX_PHYS]; 16168 char *iport = NULL; 16169 mptsas_phymask_t phy_mask = 0; 16170 uint16_t attached_devhdl; 16171 uint16_t bay_num, enclosure, io_flags; 16172 16173 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 16174 16175 /* 16176 * Probe smp device, prevent the node of removed device from being 16177 * configured succesfully 16178 */ 16179 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) { 16180 return (DDI_FAILURE); 16181 } 16182 16183 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) { 16184 return (DDI_SUCCESS); 16185 } 16186 16187 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip); 16188 16189 /* 16190 * if lun alloc success, set props 16191 */ 16192 if (ndi_rtn == NDI_SUCCESS) { 16193 /* 16194 * Set the flavor of the child to be SMP flavored 16195 */ 16196 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP); 16197 16198 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16199 *smp_dip, SMP_WWN, wwn_str) != 16200 DDI_PROP_SUCCESS) { 16201 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16202 "property for smp device %s (sas_wwn)", 16203 wwn_str); 16204 ndi_rtn = NDI_FAILURE; 16205 goto smp_create_done; 16206 } 16207 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn); 16208 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16209 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != 16210 DDI_PROP_SUCCESS) { 16211 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16212 "property for iport target-port %s (sas_wwn)", 16213 wwn_str); 16214 ndi_rtn = NDI_FAILURE; 16215 goto smp_create_done; 16216 } 16217 16218 mutex_enter(&mpt->m_mutex); 16219 16220 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 16221 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl; 16222 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16223 &dev_info); 16224 if (rval != DDI_SUCCESS) { 16225 mutex_exit(&mpt->m_mutex); 16226 mptsas_log(mpt, CE_WARN, 16227 "mptsas unable to get expander " 16228 "parent device info for %x", page_address); 16229 ndi_rtn = NDI_FAILURE; 16230 goto smp_create_done; 16231 } 16232 16233 smp_node->m_pdevhdl = dev_info.m_pdevhdl; 16234 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16235 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16236 (uint32_t)dev_info.m_pdevhdl; 16237 rval = mptsas_get_sas_device_page0(mpt, page_address, 16238 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport, 16239 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 16240 if (rval != DDI_SUCCESS) { 16241 mutex_exit(&mpt->m_mutex); 16242 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16243 "device info for %x", page_address); 16244 ndi_rtn = NDI_FAILURE; 16245 goto smp_create_done; 16246 } 16247 16248 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16249 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16250 (uint32_t)dev_info.m_devhdl; 16251 rval = mptsas_get_sas_device_page0(mpt, page_address, 16252 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo, 16253 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure, 16254 &io_flags); 16255 if (rval != DDI_SUCCESS) { 16256 mutex_exit(&mpt->m_mutex); 16257 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16258 "device info for %x", page_address); 16259 ndi_rtn = NDI_FAILURE; 16260 goto smp_create_done; 16261 } 16262 mutex_exit(&mpt->m_mutex); 16263 16264 /* 16265 * If this smp direct attached to the controller 16266 * set the attached-port to the base wwid 16267 */ 16268 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16269 != DEVINFO_DIRECT_ATTACHED) { 16270 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16271 sas_wwn); 16272 } else { 16273 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16274 mpt->un.m_base_wwid); 16275 } 16276 16277 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16278 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) != 16279 DDI_PROP_SUCCESS) { 16280 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16281 "property for smp attached-port %s (sas_wwn)", 16282 attached_wwn_str); 16283 ndi_rtn = NDI_FAILURE; 16284 goto smp_create_done; 16285 } 16286 16287 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 16288 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) { 16289 mptsas_log(mpt, CE_WARN, "mptsas unable to " 16290 "create property for SMP %s (SMP_PROP) ", 16291 wwn_str); 16292 ndi_rtn = NDI_FAILURE; 16293 goto smp_create_done; 16294 } 16295 16296 /* 16297 * check the smp to see whether it direct 16298 * attached to the controller 16299 */ 16300 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16301 != DEVINFO_DIRECT_ATTACHED) { 16302 goto smp_create_done; 16303 } 16304 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 16305 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1); 16306 if (numphys > 0) { 16307 goto smp_create_done; 16308 } 16309 /* 16310 * this iport is an old iport, we need to 16311 * reconfig the props for it. 16312 */ 16313 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16314 MPTSAS_VIRTUAL_PORT, 0) != 16315 DDI_PROP_SUCCESS) { 16316 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16317 MPTSAS_VIRTUAL_PORT); 16318 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 16319 "prop update failed"); 16320 goto smp_create_done; 16321 } 16322 16323 mutex_enter(&mpt->m_mutex); 16324 numphys = 0; 16325 iport = ddi_get_name_addr(pdip); 16326 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16327 bzero(phymask, sizeof (phymask)); 16328 (void) sprintf(phymask, 16329 "%x", mpt->m_phy_info[i].phy_mask); 16330 if (strcmp(phymask, iport) == 0) { 16331 phy_mask = mpt->m_phy_info[i].phy_mask; 16332 break; 16333 } 16334 } 16335 16336 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16337 if ((phy_mask >> i) & 0x01) { 16338 numphys++; 16339 } 16340 } 16341 /* 16342 * Update PHY info for smhba 16343 */ 16344 if (mptsas_smhba_phy_init(mpt)) { 16345 mutex_exit(&mpt->m_mutex); 16346 mptsas_log(mpt, CE_WARN, "mptsas phy update " 16347 "failed"); 16348 goto smp_create_done; 16349 } 16350 mutex_exit(&mpt->m_mutex); 16351 16352 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask, 16353 &attached_devhdl); 16354 16355 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16356 MPTSAS_NUM_PHYS, numphys) != 16357 DDI_PROP_SUCCESS) { 16358 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16359 MPTSAS_NUM_PHYS); 16360 mptsas_log(mpt, CE_WARN, "mptsas update " 16361 "num phys props failed"); 16362 goto smp_create_done; 16363 } 16364 /* 16365 * Add parent's props for SMHBA support 16366 */ 16367 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip, 16368 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 16369 DDI_PROP_SUCCESS) { 16370 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16371 SCSI_ADDR_PROP_ATTACHED_PORT); 16372 mptsas_log(mpt, CE_WARN, "mptsas update iport" 16373 "attached-port failed"); 16374 goto smp_create_done; 16375 } 16376 16377 smp_create_done: 16378 /* 16379 * If props were setup ok, online the lun 16380 */ 16381 if (ndi_rtn == NDI_SUCCESS) { 16382 /* 16383 * Try to online the new node 16384 */ 16385 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH); 16386 } 16387 16388 /* 16389 * If success set rtn flag, else unwire alloc'd lun 16390 */ 16391 if (ndi_rtn != NDI_SUCCESS) { 16392 NDBG12(("mptsas unable to online " 16393 "SMP target %s", wwn_str)); 16394 ndi_prop_remove_all(*smp_dip); 16395 (void) ndi_devi_free(*smp_dip); 16396 } 16397 } 16398 16399 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 16400 } 16401 16402 /* smp transport routine */ 16403 static int mptsas_smp_start(struct smp_pkt *smp_pkt) 16404 { 16405 uint64_t wwn; 16406 Mpi2SmpPassthroughRequest_t req; 16407 Mpi2SmpPassthroughReply_t rep; 16408 uint32_t direction = 0; 16409 mptsas_t *mpt; 16410 int ret; 16411 uint64_t tmp64; 16412 16413 mpt = (mptsas_t *)smp_pkt->smp_pkt_address-> 16414 smp_a_hba_tran->smp_tran_hba_private; 16415 16416 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE); 16417 /* 16418 * Need to compose a SMP request message 16419 * and call mptsas_do_passthru() function 16420 */ 16421 bzero(&req, sizeof (req)); 16422 bzero(&rep, sizeof (rep)); 16423 req.PassthroughFlags = 0; 16424 req.PhysicalPort = 0xff; 16425 req.ChainOffset = 0; 16426 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH; 16427 16428 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) { 16429 smp_pkt->smp_pkt_reason = ERANGE; 16430 return (DDI_FAILURE); 16431 } 16432 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4)); 16433 16434 req.MsgFlags = 0; 16435 tmp64 = LE_64(wwn); 16436 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE); 16437 if (smp_pkt->smp_pkt_rspsize > 0) { 16438 direction |= MPTSAS_PASS_THRU_DIRECTION_READ; 16439 } 16440 if (smp_pkt->smp_pkt_reqsize > 0) { 16441 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE; 16442 } 16443 16444 mutex_enter(&mpt->m_mutex); 16445 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, 16446 (uint8_t *)smp_pkt->smp_pkt_rsp, 16447 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep), 16448 smp_pkt->smp_pkt_rspsize - 4, direction, 16449 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4, 16450 smp_pkt->smp_pkt_timeout, FKIOCTL); 16451 mutex_exit(&mpt->m_mutex); 16452 if (ret != 0) { 16453 cmn_err(CE_WARN, "smp_start do passthru error %d", ret); 16454 smp_pkt->smp_pkt_reason = (uchar_t)(ret); 16455 return (DDI_FAILURE); 16456 } 16457 /* do passthrough success, check the smp status */ 16458 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16459 switch (LE_16(rep.IOCStatus)) { 16460 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 16461 smp_pkt->smp_pkt_reason = ENODEV; 16462 break; 16463 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 16464 smp_pkt->smp_pkt_reason = EOVERFLOW; 16465 break; 16466 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 16467 smp_pkt->smp_pkt_reason = EIO; 16468 break; 16469 default: 16470 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc" 16471 "status:%x", LE_16(rep.IOCStatus)); 16472 smp_pkt->smp_pkt_reason = EIO; 16473 break; 16474 } 16475 return (DDI_FAILURE); 16476 } 16477 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) { 16478 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x", 16479 rep.SASStatus); 16480 smp_pkt->smp_pkt_reason = EIO; 16481 return (DDI_FAILURE); 16482 } 16483 16484 return (DDI_SUCCESS); 16485 } 16486 16487 /* 16488 * If we didn't get a match, we need to get sas page0 for each device, and 16489 * untill we get a match. If failed, return NULL 16490 */ 16491 static mptsas_target_t * 16492 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy) 16493 { 16494 int i, j = 0; 16495 int rval = 0; 16496 uint16_t cur_handle; 16497 uint32_t page_address; 16498 mptsas_target_t *ptgt = NULL; 16499 16500 /* 16501 * PHY named device must be direct attached and attaches to 16502 * narrow port, if the iport is not parent of the device which 16503 * we are looking for. 16504 */ 16505 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16506 if ((1 << i) & phymask) 16507 j++; 16508 } 16509 16510 if (j > 1) 16511 return (NULL); 16512 16513 /* 16514 * Must be a narrow port and single device attached to the narrow port 16515 * So the physical port num of device which is equal to the iport's 16516 * port num is the device what we are looking for. 16517 */ 16518 16519 if (mpt->m_phy_info[phy].phy_mask != phymask) 16520 return (NULL); 16521 16522 mutex_enter(&mpt->m_mutex); 16523 16524 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn, 16525 &phy); 16526 if (ptgt != NULL) { 16527 mutex_exit(&mpt->m_mutex); 16528 return (ptgt); 16529 } 16530 16531 if (mpt->m_done_traverse_dev) { 16532 mutex_exit(&mpt->m_mutex); 16533 return (NULL); 16534 } 16535 16536 /* If didn't get a match, come here */ 16537 cur_handle = mpt->m_dev_handle; 16538 for (; ; ) { 16539 ptgt = NULL; 16540 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16541 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16542 rval = mptsas_get_target_device_info(mpt, page_address, 16543 &cur_handle, &ptgt); 16544 if ((rval == DEV_INFO_FAIL_PAGE0) || 16545 (rval == DEV_INFO_FAIL_ALLOC) || 16546 (rval == DEV_INFO_FAIL_GUID)) { 16547 break; 16548 } 16549 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16550 (rval == DEV_INFO_PHYS_DISK)) { 16551 continue; 16552 } 16553 mpt->m_dev_handle = cur_handle; 16554 16555 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) { 16556 break; 16557 } 16558 } 16559 16560 mutex_exit(&mpt->m_mutex); 16561 return (ptgt); 16562 } 16563 16564 /* 16565 * The ptgt->m_addr.mta_wwn contains the wwid for each disk. 16566 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid 16567 * If we didn't get a match, we need to get sas page0 for each device, and 16568 * untill we get a match 16569 * If failed, return NULL 16570 */ 16571 static mptsas_target_t * 16572 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16573 { 16574 int rval = 0; 16575 uint16_t cur_handle; 16576 uint32_t page_address; 16577 mptsas_target_t *tmp_tgt = NULL; 16578 mptsas_target_addr_t addr; 16579 16580 addr.mta_wwn = wwid; 16581 addr.mta_phymask = phymask; 16582 mutex_enter(&mpt->m_mutex); 16583 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16584 if (tmp_tgt != NULL) { 16585 mutex_exit(&mpt->m_mutex); 16586 return (tmp_tgt); 16587 } 16588 16589 if (phymask == 0) { 16590 /* 16591 * It's IR volume 16592 */ 16593 rval = mptsas_get_raid_info(mpt); 16594 if (rval) { 16595 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16596 } 16597 mutex_exit(&mpt->m_mutex); 16598 return (tmp_tgt); 16599 } 16600 16601 if (mpt->m_done_traverse_dev) { 16602 mutex_exit(&mpt->m_mutex); 16603 return (NULL); 16604 } 16605 16606 /* If didn't get a match, come here */ 16607 cur_handle = mpt->m_dev_handle; 16608 for (;;) { 16609 tmp_tgt = NULL; 16610 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16611 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle; 16612 rval = mptsas_get_target_device_info(mpt, page_address, 16613 &cur_handle, &tmp_tgt); 16614 if ((rval == DEV_INFO_FAIL_PAGE0) || 16615 (rval == DEV_INFO_FAIL_ALLOC) || 16616 (rval == DEV_INFO_FAIL_GUID)) { 16617 tmp_tgt = NULL; 16618 break; 16619 } 16620 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16621 (rval == DEV_INFO_PHYS_DISK)) { 16622 continue; 16623 } 16624 mpt->m_dev_handle = cur_handle; 16625 if ((tmp_tgt->m_addr.mta_wwn) && 16626 (tmp_tgt->m_addr.mta_wwn == wwid) && 16627 (tmp_tgt->m_addr.mta_phymask == phymask)) { 16628 break; 16629 } 16630 } 16631 16632 mutex_exit(&mpt->m_mutex); 16633 return (tmp_tgt); 16634 } 16635 16636 static mptsas_smp_t * 16637 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16638 { 16639 int rval = 0; 16640 uint16_t cur_handle; 16641 uint32_t page_address; 16642 mptsas_smp_t smp_node, *psmp = NULL; 16643 mptsas_target_addr_t addr; 16644 16645 addr.mta_wwn = wwid; 16646 addr.mta_phymask = phymask; 16647 mutex_enter(&mpt->m_mutex); 16648 psmp = refhash_lookup(mpt->m_smp_targets, &addr); 16649 if (psmp != NULL) { 16650 mutex_exit(&mpt->m_mutex); 16651 return (psmp); 16652 } 16653 16654 if (mpt->m_done_traverse_smp) { 16655 mutex_exit(&mpt->m_mutex); 16656 return (NULL); 16657 } 16658 16659 /* If didn't get a match, come here */ 16660 cur_handle = mpt->m_smp_devhdl; 16661 for (;;) { 16662 psmp = NULL; 16663 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 16664 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16665 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16666 &smp_node); 16667 if (rval != DDI_SUCCESS) { 16668 break; 16669 } 16670 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl; 16671 psmp = mptsas_smp_alloc(mpt, &smp_node); 16672 ASSERT(psmp); 16673 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) && 16674 (psmp->m_addr.mta_phymask == phymask)) { 16675 break; 16676 } 16677 } 16678 16679 mutex_exit(&mpt->m_mutex); 16680 return (psmp); 16681 } 16682 16683 mptsas_target_t * 16684 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid, 16685 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum) 16686 { 16687 mptsas_target_t *tmp_tgt = NULL; 16688 mptsas_target_addr_t addr; 16689 16690 addr.mta_wwn = wwid; 16691 addr.mta_phymask = phymask; 16692 tmp_tgt = refhash_lookup(refhash, &addr); 16693 if (tmp_tgt != NULL) { 16694 NDBG20(("Hash item already exist")); 16695 tmp_tgt->m_deviceinfo = devinfo; 16696 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */ 16697 return (tmp_tgt); 16698 } 16699 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP); 16700 if (tmp_tgt == NULL) { 16701 cmn_err(CE_WARN, "Fatal, allocated tgt failed"); 16702 return (NULL); 16703 } 16704 tmp_tgt->m_devhdl = devhdl; 16705 tmp_tgt->m_addr.mta_wwn = wwid; 16706 tmp_tgt->m_deviceinfo = devinfo; 16707 tmp_tgt->m_addr.mta_phymask = phymask; 16708 tmp_tgt->m_phynum = phynum; 16709 /* Initialized the tgt structure */ 16710 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 16711 tmp_tgt->m_qfull_retry_interval = 16712 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 16713 tmp_tgt->m_t_throttle = MAX_THROTTLE; 16714 TAILQ_INIT(&tmp_tgt->m_active_cmdq); 16715 16716 refhash_insert(refhash, tmp_tgt); 16717 16718 return (tmp_tgt); 16719 } 16720 16721 static void 16722 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst) 16723 { 16724 dst->m_devhdl = src->m_devhdl; 16725 dst->m_deviceinfo = src->m_deviceinfo; 16726 dst->m_pdevhdl = src->m_pdevhdl; 16727 dst->m_pdevinfo = src->m_pdevinfo; 16728 } 16729 16730 static mptsas_smp_t * 16731 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data) 16732 { 16733 mptsas_target_addr_t addr; 16734 mptsas_smp_t *ret_data; 16735 16736 addr.mta_wwn = data->m_addr.mta_wwn; 16737 addr.mta_phymask = data->m_addr.mta_phymask; 16738 ret_data = refhash_lookup(mpt->m_smp_targets, &addr); 16739 /* 16740 * If there's already a matching SMP target, update its fields 16741 * in place. Since the address is not changing, it's safe to do 16742 * this. We cannot just bcopy() here because the structure we've 16743 * been given has invalid hash links. 16744 */ 16745 if (ret_data != NULL) { 16746 mptsas_smp_target_copy(data, ret_data); 16747 return (ret_data); 16748 } 16749 16750 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP); 16751 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 16752 refhash_insert(mpt->m_smp_targets, ret_data); 16753 return (ret_data); 16754 } 16755 16756 /* 16757 * Functions for SGPIO LED support 16758 */ 16759 static dev_info_t * 16760 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask) 16761 { 16762 dev_info_t *dip; 16763 int prop; 16764 dip = e_ddi_hold_devi_by_dev(dev, 0); 16765 if (dip == NULL) 16766 return (dip); 16767 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 16768 "phymask", 0); 16769 *phymask = (mptsas_phymask_t)prop; 16770 ddi_release_devi(dip); 16771 return (dip); 16772 } 16773 static mptsas_target_t * 16774 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask) 16775 { 16776 uint8_t phynum; 16777 uint64_t wwn; 16778 int lun; 16779 mptsas_target_t *ptgt = NULL; 16780 16781 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) { 16782 return (NULL); 16783 } 16784 if (addr[0] == 'w') { 16785 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn); 16786 } else { 16787 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum); 16788 } 16789 return (ptgt); 16790 } 16791 16792 static int 16793 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt) 16794 { 16795 uint32_t slotstatus = 0; 16796 16797 /* Build an MPI2 Slot Status based on our view of the world */ 16798 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1))) 16799 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST; 16800 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1))) 16801 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT; 16802 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1))) 16803 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE; 16804 16805 /* Write it to the controller */ 16806 NDBG14(("mptsas_ioctl: set LED status %x for slot %x", 16807 slotstatus, ptgt->m_slot_num)); 16808 return (mptsas_send_sep(mpt, ptgt, &slotstatus, 16809 MPI2_SEP_REQ_ACTION_WRITE_STATUS)); 16810 } 16811 16812 /* 16813 * send sep request, use enclosure/slot addressing 16814 */ 16815 static int 16816 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 16817 uint32_t *status, uint8_t act) 16818 { 16819 Mpi2SepRequest_t req; 16820 Mpi2SepReply_t rep; 16821 int ret; 16822 mptsas_enclosure_t *mep; 16823 uint16_t enctype; 16824 16825 ASSERT(mutex_owned(&mpt->m_mutex)); 16826 16827 /* 16828 * We only support SEP control of directly-attached targets, in which 16829 * case the "SEP" we're talking to is a virtual one contained within 16830 * the HBA itself. This is necessary because DA targets typically have 16831 * no other mechanism for LED control. Targets for which a separate 16832 * enclosure service processor exists should be controlled via ses(7d) 16833 * or sgen(7d). Furthermore, since such requests can time out, they 16834 * should be made in user context rather than in response to 16835 * asynchronous fabric changes. 16836 * 16837 * In addition, we do not support this operation for RAID volumes, 16838 * since there is no slot associated with them. 16839 */ 16840 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) || 16841 ptgt->m_addr.mta_phymask == 0) { 16842 return (ENOTTY); 16843 } 16844 16845 /* 16846 * Look through the enclosures and make sure that this enclosure is 16847 * something that is directly attached device. If we didn't find an 16848 * enclosure for this device, don't send the ioctl. 16849 */ 16850 mep = mptsas_enc_lookup(mpt, ptgt->m_enclosure); 16851 if (mep == NULL) 16852 return (ENOTTY); 16853 enctype = mep->me_flags & MPI2_SAS_ENCLS0_FLAGS_MNG_MASK; 16854 if (enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES && 16855 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO && 16856 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO) { 16857 return (ENOTTY); 16858 } 16859 16860 bzero(&req, sizeof (req)); 16861 bzero(&rep, sizeof (rep)); 16862 16863 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR; 16864 req.Action = act; 16865 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS; 16866 req.EnclosureHandle = LE_16(ptgt->m_enclosure); 16867 req.Slot = LE_16(ptgt->m_slot_num); 16868 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16869 req.SlotStatus = LE_32(*status); 16870 } 16871 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 16872 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 16873 if (ret != 0) { 16874 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP " 16875 "Processor Request message error %d", ret); 16876 return (ret); 16877 } 16878 /* do passthrough success, check the ioc status */ 16879 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16880 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc " 16881 "status:%x loginfo %x", act, LE_16(rep.IOCStatus), 16882 LE_32(rep.IOCLogInfo)); 16883 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) { 16884 case MPI2_IOCSTATUS_INVALID_FUNCTION: 16885 case MPI2_IOCSTATUS_INVALID_VPID: 16886 case MPI2_IOCSTATUS_INVALID_FIELD: 16887 case MPI2_IOCSTATUS_INVALID_STATE: 16888 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 16889 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 16890 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 16891 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 16892 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 16893 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 16894 return (EINVAL); 16895 case MPI2_IOCSTATUS_BUSY: 16896 return (EBUSY); 16897 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 16898 return (EAGAIN); 16899 case MPI2_IOCSTATUS_INVALID_SGL: 16900 case MPI2_IOCSTATUS_INTERNAL_ERROR: 16901 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 16902 default: 16903 return (EIO); 16904 } 16905 } 16906 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16907 *status = LE_32(rep.SlotStatus); 16908 } 16909 16910 return (0); 16911 } 16912 16913 int 16914 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 16915 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 16916 uint32_t alloc_size, ddi_dma_cookie_t *cookiep) 16917 { 16918 ddi_dma_cookie_t new_cookie; 16919 size_t alloc_len; 16920 uint_t ncookie; 16921 16922 if (cookiep == NULL) 16923 cookiep = &new_cookie; 16924 16925 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP, 16926 NULL, dma_hdp) != DDI_SUCCESS) { 16927 return (FALSE); 16928 } 16929 16930 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr, 16931 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len, 16932 acc_hdp) != DDI_SUCCESS) { 16933 ddi_dma_free_handle(dma_hdp); 16934 *dma_hdp = NULL; 16935 return (FALSE); 16936 } 16937 16938 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len, 16939 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL, 16940 cookiep, &ncookie) != DDI_DMA_MAPPED) { 16941 (void) ddi_dma_mem_free(acc_hdp); 16942 ddi_dma_free_handle(dma_hdp); 16943 *dma_hdp = NULL; 16944 return (FALSE); 16945 } 16946 16947 return (TRUE); 16948 } 16949 16950 void 16951 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp) 16952 { 16953 if (*dma_hdp == NULL) 16954 return; 16955 16956 (void) ddi_dma_unbind_handle(*dma_hdp); 16957 (void) ddi_dma_mem_free(acc_hdp); 16958 ddi_dma_free_handle(dma_hdp); 16959 *dma_hdp = NULL; 16960 } 16961