1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2019 Joyent, Inc. 26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved. 27 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 28 */ 29 30 /* 31 * Copyright (c) 2000 to 2010, LSI Corporation. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms of all code within 35 * this file that is exclusively owned by LSI, with or without 36 * modification, is permitted provided that, in addition to the CDDL 1.0 37 * License requirements, the following conditions are met: 38 * 39 * Neither the name of the author nor the names of its contributors may be 40 * used to endorse or promote products derived from this software without 41 * specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 54 * DAMAGE. 55 */ 56 57 /* 58 * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface. 59 * 60 */ 61 62 #if defined(lint) || defined(DEBUG) 63 #define MPTSAS_DEBUG 64 #endif 65 66 /* 67 * standard header files. 68 */ 69 #include <sys/note.h> 70 #include <sys/scsi/scsi.h> 71 #include <sys/pci.h> 72 #include <sys/file.h> 73 #include <sys/policy.h> 74 #include <sys/model.h> 75 #include <sys/sysevent.h> 76 #include <sys/sysevent/eventdefs.h> 77 #include <sys/sysevent/dr.h> 78 #include <sys/sata/sata_defs.h> 79 #include <sys/sata/sata_hba.h> 80 #include <sys/scsi/generic/sas.h> 81 #include <sys/scsi/impl/scsi_sas.h> 82 83 #pragma pack(1) 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 92 #pragma pack() 93 94 /* 95 * private header files. 96 * 97 */ 98 #include <sys/scsi/impl/scsi_reset_notify.h> 99 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 100 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 101 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h> 102 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 103 #include <sys/raidioctl.h> 104 105 #include <sys/fs/dv_node.h> /* devfs_clean */ 106 107 /* 108 * FMA header files 109 */ 110 #include <sys/ddifm.h> 111 #include <sys/fm/protocol.h> 112 #include <sys/fm/util.h> 113 #include <sys/fm/io/ddi.h> 114 115 /* 116 * autoconfiguration data and routines. 117 */ 118 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 119 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 120 static int mptsas_power(dev_info_t *dip, int component, int level); 121 122 /* 123 * cb_ops function 124 */ 125 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 126 cred_t *credp, int *rval); 127 #ifdef __sparc 128 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 129 #else /* __sparc */ 130 static int mptsas_quiesce(dev_info_t *devi); 131 #endif /* __sparc */ 132 133 /* 134 * ddi_ufm_ops 135 */ 136 static int mptsas_ufm_fill_image(ddi_ufm_handle_t *ufmh, void *arg, 137 uint_t imgno, ddi_ufm_image_t *img); 138 static int mptsas_ufm_fill_slot(ddi_ufm_handle_t *ufmh, void *arg, 139 uint_t imgno, uint_t slotno, ddi_ufm_slot_t *slot); 140 static int mptsas_ufm_getcaps(ddi_ufm_handle_t *ufmh, void *arg, 141 ddi_ufm_cap_t *caps); 142 143 /* 144 * Resource initialization for hardware 145 */ 146 static void mptsas_setup_cmd_reg(mptsas_t *mpt); 147 static void mptsas_disable_bus_master(mptsas_t *mpt); 148 static void mptsas_hba_fini(mptsas_t *mpt); 149 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 150 static int mptsas_hba_setup(mptsas_t *mpt); 151 static void mptsas_hba_teardown(mptsas_t *mpt); 152 static int mptsas_config_space_init(mptsas_t *mpt); 153 static void mptsas_config_space_fini(mptsas_t *mpt); 154 static void mptsas_iport_register(mptsas_t *mpt); 155 static int mptsas_smp_setup(mptsas_t *mpt); 156 static void mptsas_smp_teardown(mptsas_t *mpt); 157 static int mptsas_enc_setup(mptsas_t *mpt); 158 static void mptsas_enc_teardown(mptsas_t *mpt); 159 static int mptsas_cache_create(mptsas_t *mpt); 160 static void mptsas_cache_destroy(mptsas_t *mpt); 161 static int mptsas_alloc_request_frames(mptsas_t *mpt); 162 static int mptsas_alloc_sense_bufs(mptsas_t *mpt); 163 static int mptsas_alloc_reply_frames(mptsas_t *mpt); 164 static int mptsas_alloc_free_queue(mptsas_t *mpt); 165 static int mptsas_alloc_post_queue(mptsas_t *mpt); 166 static void mptsas_alloc_reply_args(mptsas_t *mpt); 167 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 168 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 169 static int mptsas_init_chip(mptsas_t *mpt, int first_time); 170 static void mptsas_update_hashtab(mptsas_t *mpt); 171 172 /* 173 * SCSA function prototypes 174 */ 175 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 176 static int mptsas_scsi_reset(struct scsi_address *ap, int level); 177 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 178 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 179 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 180 int tgtonly); 181 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 182 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 183 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 184 int tgtlen, int flags, int (*callback)(), caddr_t arg); 185 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 186 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 187 struct scsi_pkt *pkt); 188 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 189 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 190 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 191 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 192 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 193 void (*callback)(caddr_t), caddr_t arg); 194 static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 195 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 196 static int mptsas_scsi_quiesce(dev_info_t *dip); 197 static int mptsas_scsi_unquiesce(dev_info_t *dip); 198 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 199 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 200 201 /* 202 * SMP functions 203 */ 204 static int mptsas_smp_start(struct smp_pkt *smp_pkt); 205 206 /* 207 * internal function prototypes. 208 */ 209 static void mptsas_list_add(mptsas_t *mpt); 210 static void mptsas_list_del(mptsas_t *mpt); 211 212 static int mptsas_quiesce_bus(mptsas_t *mpt); 213 static int mptsas_unquiesce_bus(mptsas_t *mpt); 214 215 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 216 static void mptsas_free_handshake_msg(mptsas_t *mpt); 217 218 static void mptsas_ncmds_checkdrain(void *arg); 219 220 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 221 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 222 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 223 static void mptsas_accept_tx_waitq(mptsas_t *mpt); 224 225 static int mptsas_do_detach(dev_info_t *dev); 226 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 227 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 228 struct scsi_pkt *pkt); 229 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 230 231 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 232 static void mptsas_handle_event(void *args); 233 static int mptsas_handle_event_sync(void *args); 234 static void mptsas_handle_dr(void *args); 235 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 236 dev_info_t *pdip); 237 238 static void mptsas_restart_cmd(void *); 239 240 static void mptsas_flush_hba(mptsas_t *mpt); 241 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 242 uint8_t tasktype); 243 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 244 uchar_t reason, uint_t stat); 245 246 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 247 static void mptsas_process_intr(mptsas_t *mpt, 248 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 249 static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 250 pMpi2ReplyDescriptorsUnion_t reply_desc); 251 static void mptsas_handle_address_reply(mptsas_t *mpt, 252 pMpi2ReplyDescriptorsUnion_t reply_desc); 253 static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 254 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 255 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 256 257 static void mptsas_watch(void *arg); 258 static void mptsas_watchsubr(mptsas_t *mpt); 259 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt); 260 261 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 262 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 263 uint8_t *data, uint32_t request_size, uint32_t reply_size, 264 uint32_t data_size, uint32_t direction, uint8_t *dataout, 265 uint32_t dataout_size, short timeout, int mode); 266 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 267 268 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 269 uint32_t unique_id); 270 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 271 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 272 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 273 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 274 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 275 uint32_t diag_type); 276 static int mptsas_diag_register(mptsas_t *mpt, 277 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 278 static int mptsas_diag_unregister(mptsas_t *mpt, 279 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 280 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 281 uint32_t *return_code); 282 static int mptsas_diag_read_buffer(mptsas_t *mpt, 283 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 284 uint32_t *return_code, int ioctl_mode); 285 static int mptsas_diag_release(mptsas_t *mpt, 286 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 287 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 288 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 289 int ioctl_mode); 290 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 291 int mode); 292 293 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 294 int cmdlen, int tgtlen, int statuslen, int kf); 295 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 296 297 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 298 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 299 300 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 301 int kmflags); 302 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 303 304 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 305 mptsas_cmd_t *cmd); 306 static void mptsas_check_task_mgt(mptsas_t *mpt, 307 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 308 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 309 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 310 int *resid); 311 312 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 313 static void mptsas_free_active_slots(mptsas_t *mpt); 314 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 315 316 static void mptsas_restart_hba(mptsas_t *mpt); 317 static void mptsas_restart_waitq(mptsas_t *mpt); 318 319 static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 320 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 321 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 322 323 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 324 static void mptsas_doneq_empty(mptsas_t *mpt); 325 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 326 327 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 328 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 329 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt); 330 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 331 332 333 static void mptsas_start_watch_reset_delay(); 334 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 335 static void mptsas_watch_reset_delay(void *arg); 336 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 337 338 /* 339 * helper functions 340 */ 341 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 342 343 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 344 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 345 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 346 int lun); 347 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 348 int lun); 349 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 350 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 351 352 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 353 int *lun); 354 static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 355 356 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, 357 mptsas_phymask_t phymask, uint8_t phy); 358 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, 359 mptsas_phymask_t phymask, uint64_t wwid); 360 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, 361 mptsas_phymask_t phymask, uint64_t wwid); 362 363 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 364 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 365 366 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 367 uint16_t *handle, mptsas_target_t **pptgt); 368 static void mptsas_update_phymask(mptsas_t *mpt); 369 370 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep, 371 uint16_t idx); 372 static int mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx, 373 uint32_t *status, uint8_t cmd); 374 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev, 375 mptsas_phymask_t *phymask); 376 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, 377 mptsas_phymask_t phymask); 378 379 380 /* 381 * Enumeration / DR functions 382 */ 383 static void mptsas_config_all(dev_info_t *pdip); 384 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 385 dev_info_t **lundip); 386 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 387 dev_info_t **lundip); 388 389 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 390 static int mptsas_offline_target(dev_info_t *pdip, char *name); 391 392 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 393 dev_info_t **dip); 394 395 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 396 static int mptsas_probe_lun(dev_info_t *pdip, int lun, 397 dev_info_t **dip, mptsas_target_t *ptgt); 398 399 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 400 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 401 402 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 403 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 404 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 405 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 406 int lun); 407 408 static void mptsas_offline_missed_luns(dev_info_t *pdip, 409 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 410 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 411 mdi_pathinfo_t *rpip, uint_t flags); 412 413 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 414 dev_info_t **smp_dip); 415 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 416 uint_t flags); 417 418 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 419 int mode, int *rval); 420 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 421 int mode, int *rval); 422 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 423 int mode, int *rval); 424 static void mptsas_record_event(void *args); 425 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 426 int mode); 427 428 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t, 429 uint32_t, mptsas_phymask_t, uint8_t); 430 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *); 431 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 432 dev_info_t **smp_dip); 433 434 /* 435 * Power management functions 436 */ 437 static int mptsas_get_pci_cap(mptsas_t *mpt); 438 static int mptsas_init_pm(mptsas_t *mpt); 439 440 /* 441 * MPT MSI tunable: 442 * 443 * By default MSI is enabled on all supported platforms. 444 */ 445 boolean_t mptsas_enable_msi = B_TRUE; 446 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE; 447 448 /* 449 * Global switch for use of MPI2.5 FAST PATH. 450 * We don't really know what FAST PATH actually does, so if it is suspected 451 * to cause problems it can be turned off by setting this variable to B_FALSE. 452 */ 453 boolean_t mptsas_use_fastpath = B_TRUE; 454 455 static int mptsas_register_intrs(mptsas_t *); 456 static void mptsas_unregister_intrs(mptsas_t *); 457 static int mptsas_add_intrs(mptsas_t *, int); 458 static void mptsas_rem_intrs(mptsas_t *); 459 460 /* 461 * FMA Prototypes 462 */ 463 static void mptsas_fm_init(mptsas_t *mpt); 464 static void mptsas_fm_fini(mptsas_t *mpt); 465 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 466 467 extern pri_t minclsyspri, maxclsyspri; 468 469 /* 470 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 471 * under this device that the paths to a physical device are created when 472 * MPxIO is used. 473 */ 474 extern dev_info_t *scsi_vhci_dip; 475 476 /* 477 * Tunable timeout value for Inquiry VPD page 0x83 478 * By default the value is 30 seconds. 479 */ 480 int mptsas_inq83_retry_timeout = 30; 481 482 /* 483 * This is used to allocate memory for message frame storage, not for 484 * data I/O DMA. All message frames must be stored in the first 4G of 485 * physical memory. 486 */ 487 ddi_dma_attr_t mptsas_dma_attrs = { 488 DMA_ATTR_V0, /* attribute layout version */ 489 0x0ull, /* address low - should be 0 (longlong) */ 490 0xffffffffull, /* address high - 32-bit max range */ 491 0x00ffffffull, /* count max - max DMA object size */ 492 4, /* allocation alignment requirements */ 493 0x78, /* burstsizes - binary encoded values */ 494 1, /* minxfer - gran. of DMA engine */ 495 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 496 0xffffffffull, /* max segment size (DMA boundary) */ 497 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 498 512, /* granularity - device transfer size */ 499 0 /* flags, set to 0 */ 500 }; 501 502 /* 503 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 504 * physical addresses are supported.) 505 */ 506 ddi_dma_attr_t mptsas_dma_attrs64 = { 507 DMA_ATTR_V0, /* attribute layout version */ 508 0x0ull, /* address low - should be 0 (longlong) */ 509 0xffffffffffffffffull, /* address high - 64-bit max */ 510 0x00ffffffull, /* count max - max DMA object size */ 511 4, /* allocation alignment requirements */ 512 0x78, /* burstsizes - binary encoded values */ 513 1, /* minxfer - gran. of DMA engine */ 514 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 515 0xffffffffull, /* max segment size (DMA boundary) */ 516 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 517 512, /* granularity - device transfer size */ 518 0 /* flags, set to 0 */ 519 }; 520 521 ddi_device_acc_attr_t mptsas_dev_attr = { 522 DDI_DEVICE_ATTR_V1, 523 DDI_STRUCTURE_LE_ACC, 524 DDI_STRICTORDER_ACC, 525 DDI_DEFAULT_ACC 526 }; 527 528 static struct cb_ops mptsas_cb_ops = { 529 scsi_hba_open, /* open */ 530 scsi_hba_close, /* close */ 531 nodev, /* strategy */ 532 nodev, /* print */ 533 nodev, /* dump */ 534 nodev, /* read */ 535 nodev, /* write */ 536 mptsas_ioctl, /* ioctl */ 537 nodev, /* devmap */ 538 nodev, /* mmap */ 539 nodev, /* segmap */ 540 nochpoll, /* chpoll */ 541 ddi_prop_op, /* cb_prop_op */ 542 NULL, /* streamtab */ 543 D_MP, /* cb_flag */ 544 CB_REV, /* rev */ 545 nodev, /* aread */ 546 nodev /* awrite */ 547 }; 548 549 static struct dev_ops mptsas_ops = { 550 DEVO_REV, /* devo_rev, */ 551 0, /* refcnt */ 552 ddi_no_info, /* info */ 553 nulldev, /* identify */ 554 nulldev, /* probe */ 555 mptsas_attach, /* attach */ 556 mptsas_detach, /* detach */ 557 #ifdef __sparc 558 mptsas_reset, 559 #else 560 nodev, /* reset */ 561 #endif /* __sparc */ 562 &mptsas_cb_ops, /* driver operations */ 563 NULL, /* bus operations */ 564 mptsas_power, /* power management */ 565 #ifdef __sparc 566 ddi_quiesce_not_needed 567 #else 568 mptsas_quiesce /* quiesce */ 569 #endif /* __sparc */ 570 }; 571 572 static ddi_ufm_ops_t mptsas_ufm_ops = { 573 NULL, 574 mptsas_ufm_fill_image, 575 mptsas_ufm_fill_slot, 576 mptsas_ufm_getcaps 577 }; 578 579 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24" 580 581 static struct modldrv modldrv = { 582 &mod_driverops, /* Type of module. This one is a driver */ 583 MPTSAS_MOD_STRING, /* Name of the module. */ 584 &mptsas_ops, /* driver ops */ 585 }; 586 587 static struct modlinkage modlinkage = { 588 MODREV_1, &modldrv, NULL 589 }; 590 #define TARGET_PROP "target" 591 #define LUN_PROP "lun" 592 #define LUN64_PROP "lun64" 593 #define SAS_PROP "sas-mpt" 594 #define MDI_GUID "wwn" 595 #define NDI_GUID "guid" 596 #define MPTSAS_DEV_GONE "mptsas_dev_gone" 597 598 /* 599 * Local static data 600 */ 601 #if defined(MPTSAS_DEBUG) 602 /* 603 * Flags to indicate which debug messages are to be printed and which go to the 604 * debug log ring buffer. Default is to not print anything, and to log 605 * everything except the watchsubr() output which normally happens every second. 606 */ 607 uint32_t mptsas_debugprt_flags = 0x0; 608 uint32_t mptsas_debuglog_flags = ~(1U << 30); 609 #endif /* defined(MPTSAS_DEBUG) */ 610 uint32_t mptsas_debug_resets = 0; 611 612 static kmutex_t mptsas_global_mutex; 613 static void *mptsas_state; /* soft state ptr */ 614 static krwlock_t mptsas_global_rwlock; 615 616 static kmutex_t mptsas_log_mutex; 617 static char mptsas_log_buf[256]; 618 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 619 620 static mptsas_t *mptsas_head, *mptsas_tail; 621 static clock_t mptsas_scsi_watchdog_tick; 622 static clock_t mptsas_tick; 623 static timeout_id_t mptsas_reset_watch; 624 static timeout_id_t mptsas_timeout_id; 625 static int mptsas_timeouts_enabled = 0; 626 627 /* 628 * Default length for extended auto request sense buffers. 629 * All sense buffers need to be under the same alloc because there 630 * is only one common top 32bits (of 64bits) address register. 631 * Most requests only require 32 bytes, but some request >256. 632 * We use rmalloc()/rmfree() on this additional memory to manage the 633 * "extended" requests. 634 */ 635 int mptsas_extreq_sense_bufsize = 256*64; 636 637 /* 638 * We believe that all software resrictions of having to run with DMA 639 * attributes to limit allocation to the first 4G are removed. 640 * However, this flag remains to enable quick switchback should suspicious 641 * problems emerge. 642 * Note that scsi_alloc_consistent_buf() does still adhere to allocating 643 * 32 bit addressable memory, but we can cope if that is changed now. 644 */ 645 int mptsas_use_64bit_msgaddr = 1; 646 647 /* 648 * warlock directives 649 */ 650 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 651 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 652 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 653 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 654 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 655 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 656 657 /* 658 * SM - HBA statics 659 */ 660 char *mptsas_driver_rev = MPTSAS_MOD_STRING; 661 662 #ifdef MPTSAS_DEBUG 663 void debug_enter(char *); 664 #endif 665 666 /* 667 * Notes: 668 * - scsi_hba_init(9F) initializes SCSI HBA modules 669 * - must call scsi_hba_fini(9F) if modload() fails 670 */ 671 int 672 _init(void) 673 { 674 int status; 675 /* CONSTCOND */ 676 ASSERT(NO_COMPETING_THREADS); 677 678 NDBG0(("_init")); 679 680 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 681 MPTSAS_INITIAL_SOFT_SPACE); 682 if (status != 0) { 683 return (status); 684 } 685 686 if ((status = scsi_hba_init(&modlinkage)) != 0) { 687 ddi_soft_state_fini(&mptsas_state); 688 return (status); 689 } 690 691 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 692 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 693 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 694 695 if ((status = mod_install(&modlinkage)) != 0) { 696 mutex_destroy(&mptsas_log_mutex); 697 rw_destroy(&mptsas_global_rwlock); 698 mutex_destroy(&mptsas_global_mutex); 699 ddi_soft_state_fini(&mptsas_state); 700 scsi_hba_fini(&modlinkage); 701 } 702 703 return (status); 704 } 705 706 /* 707 * Notes: 708 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 709 */ 710 int 711 _fini(void) 712 { 713 int status; 714 /* CONSTCOND */ 715 ASSERT(NO_COMPETING_THREADS); 716 717 NDBG0(("_fini")); 718 719 if ((status = mod_remove(&modlinkage)) == 0) { 720 ddi_soft_state_fini(&mptsas_state); 721 scsi_hba_fini(&modlinkage); 722 mutex_destroy(&mptsas_global_mutex); 723 rw_destroy(&mptsas_global_rwlock); 724 mutex_destroy(&mptsas_log_mutex); 725 } 726 return (status); 727 } 728 729 /* 730 * The loadable-module _info(9E) entry point 731 */ 732 int 733 _info(struct modinfo *modinfop) 734 { 735 /* CONSTCOND */ 736 ASSERT(NO_COMPETING_THREADS); 737 NDBG0(("mptsas _info")); 738 739 return (mod_info(&modlinkage, modinfop)); 740 } 741 742 static int 743 mptsas_target_eval_devhdl(const void *op, void *arg) 744 { 745 uint16_t dh = *(uint16_t *)arg; 746 const mptsas_target_t *tp = op; 747 748 return ((int)tp->m_devhdl - (int)dh); 749 } 750 751 static int 752 mptsas_target_eval_nowwn(const void *op, void *arg) 753 { 754 uint8_t phy = *(uint8_t *)arg; 755 const mptsas_target_t *tp = op; 756 757 if (tp->m_addr.mta_wwn != 0) 758 return (-1); 759 760 return ((int)tp->m_phynum - (int)phy); 761 } 762 763 static int 764 mptsas_smp_eval_devhdl(const void *op, void *arg) 765 { 766 uint16_t dh = *(uint16_t *)arg; 767 const mptsas_smp_t *sp = op; 768 769 return ((int)sp->m_devhdl - (int)dh); 770 } 771 772 static uint64_t 773 mptsas_target_addr_hash(const void *tp) 774 { 775 const mptsas_target_addr_t *tap = tp; 776 777 return ((tap->mta_wwn & 0xffffffffffffULL) | 778 ((uint64_t)tap->mta_phymask << 48)); 779 } 780 781 static int 782 mptsas_target_addr_cmp(const void *a, const void *b) 783 { 784 const mptsas_target_addr_t *aap = a; 785 const mptsas_target_addr_t *bap = b; 786 787 if (aap->mta_wwn < bap->mta_wwn) 788 return (-1); 789 if (aap->mta_wwn > bap->mta_wwn) 790 return (1); 791 return ((int)bap->mta_phymask - (int)aap->mta_phymask); 792 } 793 794 static uint64_t 795 mptsas_tmp_target_hash(const void *tp) 796 { 797 return ((uint64_t)(uintptr_t)tp); 798 } 799 800 static int 801 mptsas_tmp_target_cmp(const void *a, const void *b) 802 { 803 if (a > b) 804 return (1); 805 if (b < a) 806 return (-1); 807 808 return (0); 809 } 810 811 static void 812 mptsas_target_free(void *op) 813 { 814 kmem_free(op, sizeof (mptsas_target_t)); 815 } 816 817 static void 818 mptsas_smp_free(void *op) 819 { 820 kmem_free(op, sizeof (mptsas_smp_t)); 821 } 822 823 static void 824 mptsas_destroy_hashes(mptsas_t *mpt) 825 { 826 mptsas_target_t *tp; 827 mptsas_smp_t *sp; 828 829 for (tp = refhash_first(mpt->m_targets); tp != NULL; 830 tp = refhash_next(mpt->m_targets, tp)) { 831 refhash_remove(mpt->m_targets, tp); 832 } 833 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 834 sp = refhash_next(mpt->m_smp_targets, sp)) { 835 refhash_remove(mpt->m_smp_targets, sp); 836 } 837 refhash_destroy(mpt->m_tmp_targets); 838 refhash_destroy(mpt->m_targets); 839 refhash_destroy(mpt->m_smp_targets); 840 mpt->m_targets = NULL; 841 mpt->m_smp_targets = NULL; 842 } 843 844 static int 845 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 846 { 847 dev_info_t *pdip; 848 mptsas_t *mpt; 849 scsi_hba_tran_t *hba_tran; 850 char *iport = NULL; 851 char phymask[MPTSAS_MAX_PHYS]; 852 mptsas_phymask_t phy_mask = 0; 853 int dynamic_port = 0; 854 uint32_t page_address; 855 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 856 int rval = DDI_FAILURE; 857 int i = 0; 858 uint8_t numphys = 0; 859 uint8_t phy_id; 860 uint8_t phy_port = 0; 861 uint16_t attached_devhdl = 0; 862 uint32_t dev_info; 863 uint64_t attached_sas_wwn; 864 uint16_t dev_hdl; 865 uint16_t pdev_hdl; 866 uint16_t bay_num, enclosure, io_flags; 867 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 868 869 /* CONSTCOND */ 870 ASSERT(NO_COMPETING_THREADS); 871 872 switch (cmd) { 873 case DDI_ATTACH: 874 break; 875 876 case DDI_RESUME: 877 /* 878 * If this a scsi-iport node, nothing to do here. 879 */ 880 return (DDI_SUCCESS); 881 882 default: 883 return (DDI_FAILURE); 884 } 885 886 pdip = ddi_get_parent(dip); 887 888 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 889 NULL) { 890 cmn_err(CE_WARN, "Failed attach iport because fail to " 891 "get tran vector for the HBA node"); 892 return (DDI_FAILURE); 893 } 894 895 mpt = TRAN2MPT(hba_tran); 896 ASSERT(mpt != NULL); 897 if (mpt == NULL) 898 return (DDI_FAILURE); 899 900 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 901 NULL) { 902 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 903 "get tran vector for the iport node"); 904 return (DDI_FAILURE); 905 } 906 907 /* 908 * Overwrite parent's tran_hba_private to iport's tran vector 909 */ 910 hba_tran->tran_hba_private = mpt; 911 912 ddi_report_dev(dip); 913 914 /* 915 * Get SAS address for initiator port according dev_handle 916 */ 917 iport = ddi_get_name_addr(dip); 918 if (iport && strncmp(iport, "v0", 2) == 0) { 919 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 920 MPTSAS_VIRTUAL_PORT, 1) != 921 DDI_PROP_SUCCESS) { 922 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 923 MPTSAS_VIRTUAL_PORT); 924 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 925 "prop update failed"); 926 return (DDI_FAILURE); 927 } 928 return (DDI_SUCCESS); 929 } 930 931 mutex_enter(&mpt->m_mutex); 932 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 933 bzero(phymask, sizeof (phymask)); 934 (void) sprintf(phymask, 935 "%x", mpt->m_phy_info[i].phy_mask); 936 if (strcmp(phymask, iport) == 0) { 937 break; 938 } 939 } 940 941 if (i == MPTSAS_MAX_PHYS) { 942 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 943 "seems not exist", iport); 944 mutex_exit(&mpt->m_mutex); 945 return (DDI_FAILURE); 946 } 947 948 phy_mask = mpt->m_phy_info[i].phy_mask; 949 950 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 951 dynamic_port = 1; 952 else 953 dynamic_port = 0; 954 955 /* 956 * Update PHY info for smhba 957 */ 958 if (mptsas_smhba_phy_init(mpt)) { 959 mutex_exit(&mpt->m_mutex); 960 mptsas_log(mpt, CE_WARN, "mptsas phy update " 961 "failed"); 962 return (DDI_FAILURE); 963 } 964 965 mutex_exit(&mpt->m_mutex); 966 967 numphys = 0; 968 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 969 if ((phy_mask >> i) & 0x01) { 970 numphys++; 971 } 972 } 973 974 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 975 (void) sprintf(initiator_wwnstr, "w%016"PRIx64, 976 mpt->un.m_base_wwid); 977 978 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 979 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) != 980 DDI_PROP_SUCCESS) { 981 (void) ddi_prop_remove(DDI_DEV_T_NONE, 982 dip, SCSI_ADDR_PROP_INITIATOR_PORT); 983 mptsas_log(mpt, CE_WARN, "mptsas Initiator port " 984 "prop update failed"); 985 return (DDI_FAILURE); 986 } 987 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 988 MPTSAS_NUM_PHYS, numphys) != 989 DDI_PROP_SUCCESS) { 990 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS); 991 return (DDI_FAILURE); 992 } 993 994 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 995 "phymask", phy_mask) != 996 DDI_PROP_SUCCESS) { 997 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 998 mptsas_log(mpt, CE_WARN, "mptsas phy mask " 999 "prop update failed"); 1000 return (DDI_FAILURE); 1001 } 1002 1003 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 1004 "dynamic-port", dynamic_port) != 1005 DDI_PROP_SUCCESS) { 1006 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 1007 mptsas_log(mpt, CE_WARN, "mptsas dynamic port " 1008 "prop update failed"); 1009 return (DDI_FAILURE); 1010 } 1011 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 1012 MPTSAS_VIRTUAL_PORT, 0) != 1013 DDI_PROP_SUCCESS) { 1014 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 1015 MPTSAS_VIRTUAL_PORT); 1016 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 1017 "prop update failed"); 1018 return (DDI_FAILURE); 1019 } 1020 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask, 1021 &attached_devhdl); 1022 1023 mutex_enter(&mpt->m_mutex); 1024 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 1025 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl; 1026 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 1027 &attached_sas_wwn, &dev_info, &phy_port, &phy_id, 1028 &pdev_hdl, &bay_num, &enclosure, &io_flags); 1029 if (rval != DDI_SUCCESS) { 1030 mptsas_log(mpt, CE_WARN, 1031 "Failed to get device page0 for handle:%d", 1032 attached_devhdl); 1033 mutex_exit(&mpt->m_mutex); 1034 return (DDI_FAILURE); 1035 } 1036 1037 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1038 bzero(phymask, sizeof (phymask)); 1039 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 1040 if (strcmp(phymask, iport) == 0) { 1041 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0], 1042 "%x", 1043 mpt->m_phy_info[i].phy_mask); 1044 } 1045 } 1046 mutex_exit(&mpt->m_mutex); 1047 1048 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 1049 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 1050 attached_sas_wwn); 1051 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 1052 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 1053 DDI_PROP_SUCCESS) { 1054 (void) ddi_prop_remove(DDI_DEV_T_NONE, 1055 dip, SCSI_ADDR_PROP_ATTACHED_PORT); 1056 return (DDI_FAILURE); 1057 } 1058 1059 /* Create kstats for each phy on this iport */ 1060 1061 mptsas_create_phy_stats(mpt, iport, dip); 1062 1063 /* 1064 * register sas hba iport with mdi (MPxIO/vhci) 1065 */ 1066 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 1067 dip, 0) == MDI_SUCCESS) { 1068 mpt->m_mpxio_enable = TRUE; 1069 } 1070 return (DDI_SUCCESS); 1071 } 1072 1073 /* 1074 * Notes: 1075 * Set up all device state and allocate data structures, 1076 * mutexes, condition variables, etc. for device operation. 1077 * Add interrupts needed. 1078 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 1079 */ 1080 static int 1081 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1082 { 1083 mptsas_t *mpt = NULL; 1084 int instance, i, j; 1085 int doneq_thread_num; 1086 char intr_added = 0; 1087 char map_setup = 0; 1088 char config_setup = 0; 1089 char hba_attach_setup = 0; 1090 char smp_attach_setup = 0; 1091 char enc_attach_setup = 0; 1092 char mutex_init_done = 0; 1093 char event_taskq_create = 0; 1094 char dr_taskq_create = 0; 1095 char doneq_thread_create = 0; 1096 char added_watchdog = 0; 1097 scsi_hba_tran_t *hba_tran; 1098 uint_t mem_bar = MEM_SPACE; 1099 int rval = DDI_FAILURE; 1100 1101 /* CONSTCOND */ 1102 ASSERT(NO_COMPETING_THREADS); 1103 1104 if (scsi_hba_iport_unit_address(dip)) { 1105 return (mptsas_iport_attach(dip, cmd)); 1106 } 1107 1108 switch (cmd) { 1109 case DDI_ATTACH: 1110 break; 1111 1112 case DDI_RESUME: 1113 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 1114 return (DDI_FAILURE); 1115 1116 mpt = TRAN2MPT(hba_tran); 1117 1118 if (!mpt) { 1119 return (DDI_FAILURE); 1120 } 1121 1122 /* 1123 * Reset hardware and softc to "no outstanding commands" 1124 * Note that a check condition can result on first command 1125 * to a target. 1126 */ 1127 mutex_enter(&mpt->m_mutex); 1128 1129 /* 1130 * raise power. 1131 */ 1132 if (mpt->m_options & MPTSAS_OPT_PM) { 1133 mutex_exit(&mpt->m_mutex); 1134 (void) pm_busy_component(dip, 0); 1135 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0); 1136 if (rval == DDI_SUCCESS) { 1137 mutex_enter(&mpt->m_mutex); 1138 } else { 1139 /* 1140 * The pm_raise_power() call above failed, 1141 * and that can only occur if we were unable 1142 * to reset the hardware. This is probably 1143 * due to unhealty hardware, and because 1144 * important filesystems(such as the root 1145 * filesystem) could be on the attached disks, 1146 * it would not be a good idea to continue, 1147 * as we won't be entirely certain we are 1148 * writing correct data. So we panic() here 1149 * to not only prevent possible data corruption, 1150 * but to give developers or end users a hope 1151 * of identifying and correcting any problems. 1152 */ 1153 fm_panic("mptsas could not reset hardware " 1154 "during resume"); 1155 } 1156 } 1157 1158 mpt->m_suspended = 0; 1159 1160 /* 1161 * Reinitialize ioc 1162 */ 1163 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1164 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 1165 mutex_exit(&mpt->m_mutex); 1166 if (mpt->m_options & MPTSAS_OPT_PM) { 1167 (void) pm_idle_component(dip, 0); 1168 } 1169 fm_panic("mptsas init chip fail during resume"); 1170 } 1171 /* 1172 * mptsas_update_driver_data needs interrupts so enable them 1173 * first. 1174 */ 1175 MPTSAS_ENABLE_INTR(mpt); 1176 mptsas_update_driver_data(mpt); 1177 1178 /* start requests, if possible */ 1179 mptsas_restart_hba(mpt); 1180 1181 mutex_exit(&mpt->m_mutex); 1182 1183 /* 1184 * Restart watch thread 1185 */ 1186 mutex_enter(&mptsas_global_mutex); 1187 if (mptsas_timeout_id == 0) { 1188 mptsas_timeout_id = timeout(mptsas_watch, NULL, 1189 mptsas_tick); 1190 mptsas_timeouts_enabled = 1; 1191 } 1192 mutex_exit(&mptsas_global_mutex); 1193 1194 /* report idle status to pm framework */ 1195 if (mpt->m_options & MPTSAS_OPT_PM) { 1196 (void) pm_idle_component(dip, 0); 1197 } 1198 1199 return (DDI_SUCCESS); 1200 1201 default: 1202 return (DDI_FAILURE); 1203 1204 } 1205 1206 instance = ddi_get_instance(dip); 1207 1208 /* 1209 * Allocate softc information. 1210 */ 1211 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 1212 mptsas_log(NULL, CE_WARN, 1213 "mptsas%d: cannot allocate soft state", instance); 1214 goto fail; 1215 } 1216 1217 mpt = ddi_get_soft_state(mptsas_state, instance); 1218 1219 if (mpt == NULL) { 1220 mptsas_log(NULL, CE_WARN, 1221 "mptsas%d: cannot get soft state", instance); 1222 goto fail; 1223 } 1224 1225 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 1226 scsi_size_clean(dip); 1227 1228 mpt->m_dip = dip; 1229 mpt->m_instance = instance; 1230 1231 /* Make a per-instance copy of the structures */ 1232 mpt->m_io_dma_attr = mptsas_dma_attrs64; 1233 if (mptsas_use_64bit_msgaddr) { 1234 mpt->m_msg_dma_attr = mptsas_dma_attrs64; 1235 } else { 1236 mpt->m_msg_dma_attr = mptsas_dma_attrs; 1237 } 1238 mpt->m_reg_acc_attr = mptsas_dev_attr; 1239 mpt->m_dev_acc_attr = mptsas_dev_attr; 1240 1241 /* 1242 * Size of individual request sense buffer 1243 */ 1244 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE; 1245 1246 /* 1247 * Initialize FMA 1248 */ 1249 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 1250 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 1251 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 1252 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1253 1254 mptsas_fm_init(mpt); 1255 1256 /* 1257 * Initialize us with the UFM subsystem 1258 */ 1259 if (ddi_ufm_init(dip, DDI_UFM_CURRENT_VERSION, &mptsas_ufm_ops, 1260 &mpt->m_ufmh, mpt) != 0) { 1261 mptsas_log(mpt, CE_WARN, "failed to initialize UFM subsystem"); 1262 goto fail; 1263 } 1264 1265 if (mptsas_alloc_handshake_msg(mpt, 1266 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 1267 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 1268 goto fail; 1269 } 1270 1271 /* 1272 * Setup configuration space 1273 */ 1274 if (mptsas_config_space_init(mpt) == FALSE) { 1275 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1276 goto fail; 1277 } 1278 config_setup++; 1279 1280 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1281 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1282 mptsas_log(mpt, CE_WARN, "map setup failed"); 1283 goto fail; 1284 } 1285 map_setup++; 1286 1287 /* 1288 * A taskq is created for dealing with the event handler 1289 */ 1290 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1291 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1292 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1293 goto fail; 1294 } 1295 event_taskq_create++; 1296 1297 /* 1298 * A taskq is created for dealing with dr events 1299 */ 1300 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1301 "mptsas_dr_taskq", 1302 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1303 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1304 "failed"); 1305 goto fail; 1306 } 1307 dr_taskq_create++; 1308 1309 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1310 0, "mptsas_doneq_thread_threshold_prop", 10); 1311 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1312 0, "mptsas_doneq_length_threshold_prop", 8); 1313 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1314 0, "mptsas_doneq_thread_n_prop", 8); 1315 1316 if (mpt->m_doneq_thread_n) { 1317 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1318 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1319 1320 mutex_enter(&mpt->m_doneq_mutex); 1321 mpt->m_doneq_thread_id = 1322 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1323 * mpt->m_doneq_thread_n, KM_SLEEP); 1324 1325 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1326 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1327 CV_DRIVER, NULL); 1328 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1329 MUTEX_DRIVER, NULL); 1330 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1331 mpt->m_doneq_thread_id[j].flag |= 1332 MPTSAS_DONEQ_THREAD_ACTIVE; 1333 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1334 mpt->m_doneq_thread_id[j].arg.t = j; 1335 mpt->m_doneq_thread_id[j].threadp = 1336 thread_create(NULL, 0, mptsas_doneq_thread, 1337 &mpt->m_doneq_thread_id[j].arg, 1338 0, &p0, TS_RUN, minclsyspri); 1339 mpt->m_doneq_thread_id[j].donetail = 1340 &mpt->m_doneq_thread_id[j].doneq; 1341 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1342 } 1343 mutex_exit(&mpt->m_doneq_mutex); 1344 doneq_thread_create++; 1345 } 1346 1347 /* 1348 * Disable hardware interrupt since we're not ready to 1349 * handle it yet. 1350 */ 1351 MPTSAS_DISABLE_INTR(mpt); 1352 if (mptsas_register_intrs(mpt) == FALSE) 1353 goto fail; 1354 intr_added++; 1355 1356 /* Initialize mutex used in interrupt handler */ 1357 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1358 DDI_INTR_PRI(mpt->m_intr_pri)); 1359 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL); 1360 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER, 1361 DDI_INTR_PRI(mpt->m_intr_pri)); 1362 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1363 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex, 1364 NULL, MUTEX_DRIVER, 1365 DDI_INTR_PRI(mpt->m_intr_pri)); 1366 } 1367 1368 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1369 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1370 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1371 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1372 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1373 cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL); 1374 mutex_init_done++; 1375 1376 mutex_enter(&mpt->m_mutex); 1377 /* 1378 * Initialize power management component 1379 */ 1380 if (mpt->m_options & MPTSAS_OPT_PM) { 1381 if (mptsas_init_pm(mpt)) { 1382 mutex_exit(&mpt->m_mutex); 1383 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1384 "failed"); 1385 goto fail; 1386 } 1387 } 1388 1389 /* 1390 * Initialize chip using Message Unit Reset, if allowed 1391 */ 1392 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1393 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1394 mutex_exit(&mpt->m_mutex); 1395 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1396 goto fail; 1397 } 1398 1399 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT, 1400 mptsas_target_addr_hash, mptsas_target_addr_cmp, 1401 mptsas_target_free, sizeof (mptsas_target_t), 1402 offsetof(mptsas_target_t, m_link), 1403 offsetof(mptsas_target_t, m_addr), KM_SLEEP); 1404 1405 /* 1406 * The refhash for temporary targets uses the address of the target 1407 * struct itself as tag, so the tag offset is 0. See the implementation 1408 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp(). 1409 */ 1410 mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT, 1411 mptsas_tmp_target_hash, mptsas_tmp_target_cmp, 1412 mptsas_target_free, sizeof (mptsas_target_t), 1413 offsetof(mptsas_target_t, m_link), 0, KM_SLEEP); 1414 1415 /* 1416 * Fill in the phy_info structure and get the base WWID 1417 */ 1418 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 1419 mptsas_log(mpt, CE_WARN, 1420 "mptsas_get_manufacture_page5 failed!"); 1421 goto fail; 1422 } 1423 1424 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 1425 mptsas_log(mpt, CE_WARN, 1426 "mptsas_get_sas_io_unit_page_hndshk failed!"); 1427 goto fail; 1428 } 1429 1430 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) { 1431 mptsas_log(mpt, CE_WARN, 1432 "mptsas_get_manufacture_page0 failed!"); 1433 goto fail; 1434 } 1435 1436 mutex_exit(&mpt->m_mutex); 1437 1438 /* 1439 * Register the iport for multiple port HBA 1440 */ 1441 mptsas_iport_register(mpt); 1442 1443 /* 1444 * initialize SCSI HBA transport structure 1445 */ 1446 if (mptsas_hba_setup(mpt) == FALSE) 1447 goto fail; 1448 hba_attach_setup++; 1449 1450 if (mptsas_smp_setup(mpt) == FALSE) 1451 goto fail; 1452 smp_attach_setup++; 1453 1454 if (mptsas_enc_setup(mpt) == FALSE) 1455 goto fail; 1456 enc_attach_setup++; 1457 1458 if (mptsas_cache_create(mpt) == FALSE) 1459 goto fail; 1460 1461 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1462 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1463 if (mpt->m_scsi_reset_delay == 0) { 1464 mptsas_log(mpt, CE_NOTE, 1465 "scsi_reset_delay of 0 is not recommended," 1466 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1467 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1468 } 1469 1470 /* 1471 * Initialize the wait and done FIFO queue 1472 */ 1473 mpt->m_donetail = &mpt->m_doneq; 1474 mpt->m_waitqtail = &mpt->m_waitq; 1475 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 1476 mpt->m_tx_draining = 0; 1477 1478 /* 1479 * ioc cmd queue initialize 1480 */ 1481 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1482 mpt->m_dev_handle = 0xFFFF; 1483 1484 MPTSAS_ENABLE_INTR(mpt); 1485 1486 /* 1487 * enable event notification 1488 */ 1489 mutex_enter(&mpt->m_mutex); 1490 if (mptsas_ioc_enable_event_notification(mpt)) { 1491 mutex_exit(&mpt->m_mutex); 1492 goto fail; 1493 } 1494 mutex_exit(&mpt->m_mutex); 1495 1496 /* 1497 * used for mptsas_watch 1498 */ 1499 mptsas_list_add(mpt); 1500 1501 mutex_enter(&mptsas_global_mutex); 1502 if (mptsas_timeouts_enabled == 0) { 1503 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1504 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1505 1506 mptsas_tick = mptsas_scsi_watchdog_tick * 1507 drv_usectohz((clock_t)1000000); 1508 1509 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1510 mptsas_timeouts_enabled = 1; 1511 } 1512 mutex_exit(&mptsas_global_mutex); 1513 added_watchdog++; 1514 1515 /* 1516 * Initialize PHY info for smhba. 1517 * This requires watchdog to be enabled otherwise if interrupts 1518 * don't work the system will hang. 1519 */ 1520 if (mptsas_smhba_setup(mpt)) { 1521 mptsas_log(mpt, CE_WARN, "mptsas phy initialization " 1522 "failed"); 1523 goto fail; 1524 } 1525 1526 /* Check all dma handles allocated in attach */ 1527 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1528 != DDI_SUCCESS) || 1529 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) 1530 != DDI_SUCCESS) || 1531 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1532 != DDI_SUCCESS) || 1533 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1534 != DDI_SUCCESS) || 1535 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1536 != DDI_SUCCESS) || 1537 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1538 != DDI_SUCCESS)) { 1539 goto fail; 1540 } 1541 1542 /* Check all acc handles allocated in attach */ 1543 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1544 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1545 != DDI_SUCCESS) || 1546 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) 1547 != DDI_SUCCESS) || 1548 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1549 != DDI_SUCCESS) || 1550 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1551 != DDI_SUCCESS) || 1552 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1553 != DDI_SUCCESS) || 1554 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1555 != DDI_SUCCESS) || 1556 (mptsas_check_acc_handle(mpt->m_config_handle) 1557 != DDI_SUCCESS)) { 1558 goto fail; 1559 } 1560 1561 /* 1562 * After this point, we are not going to fail the attach. 1563 */ 1564 1565 /* Let the UFM susbsystem know we're ready to receive callbacks */ 1566 ddi_ufm_update(mpt->m_ufmh); 1567 1568 /* Print message of HBA present */ 1569 ddi_report_dev(dip); 1570 1571 /* report idle status to pm framework */ 1572 if (mpt->m_options & MPTSAS_OPT_PM) { 1573 (void) pm_idle_component(dip, 0); 1574 } 1575 1576 return (DDI_SUCCESS); 1577 1578 fail: 1579 mptsas_log(mpt, CE_WARN, "attach failed"); 1580 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1581 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1582 if (mpt) { 1583 /* deallocate in reverse order */ 1584 if (added_watchdog) { 1585 mptsas_list_del(mpt); 1586 mutex_enter(&mptsas_global_mutex); 1587 1588 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1589 timeout_id_t tid = mptsas_timeout_id; 1590 mptsas_timeouts_enabled = 0; 1591 mptsas_timeout_id = 0; 1592 mutex_exit(&mptsas_global_mutex); 1593 (void) untimeout(tid); 1594 mutex_enter(&mptsas_global_mutex); 1595 } 1596 mutex_exit(&mptsas_global_mutex); 1597 } 1598 1599 mptsas_cache_destroy(mpt); 1600 1601 if (smp_attach_setup) { 1602 mptsas_smp_teardown(mpt); 1603 } 1604 if (enc_attach_setup) { 1605 mptsas_enc_teardown(mpt); 1606 } 1607 if (hba_attach_setup) { 1608 mptsas_hba_teardown(mpt); 1609 } 1610 1611 if (mpt->m_tmp_targets) 1612 refhash_destroy(mpt->m_tmp_targets); 1613 if (mpt->m_targets) 1614 refhash_destroy(mpt->m_targets); 1615 if (mpt->m_smp_targets) 1616 refhash_destroy(mpt->m_smp_targets); 1617 1618 if (mpt->m_active) { 1619 mptsas_free_active_slots(mpt); 1620 } 1621 if (intr_added) { 1622 mptsas_unregister_intrs(mpt); 1623 } 1624 1625 if (doneq_thread_create) { 1626 mutex_enter(&mpt->m_doneq_mutex); 1627 doneq_thread_num = mpt->m_doneq_thread_n; 1628 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1629 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1630 mpt->m_doneq_thread_id[j].flag &= 1631 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1632 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1633 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1634 } 1635 while (mpt->m_doneq_thread_n) { 1636 cv_wait(&mpt->m_doneq_thread_cv, 1637 &mpt->m_doneq_mutex); 1638 } 1639 for (j = 0; j < doneq_thread_num; j++) { 1640 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1641 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1642 } 1643 kmem_free(mpt->m_doneq_thread_id, 1644 sizeof (mptsas_doneq_thread_list_t) 1645 * doneq_thread_num); 1646 mutex_exit(&mpt->m_doneq_mutex); 1647 cv_destroy(&mpt->m_doneq_thread_cv); 1648 mutex_destroy(&mpt->m_doneq_mutex); 1649 } 1650 if (event_taskq_create) { 1651 ddi_taskq_destroy(mpt->m_event_taskq); 1652 } 1653 if (dr_taskq_create) { 1654 ddi_taskq_destroy(mpt->m_dr_taskq); 1655 } 1656 if (mutex_init_done) { 1657 mutex_destroy(&mpt->m_tx_waitq_mutex); 1658 mutex_destroy(&mpt->m_passthru_mutex); 1659 mutex_destroy(&mpt->m_mutex); 1660 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1661 mutex_destroy( 1662 &mpt->m_phy_info[i].smhba_info.phy_mutex); 1663 } 1664 cv_destroy(&mpt->m_cv); 1665 cv_destroy(&mpt->m_passthru_cv); 1666 cv_destroy(&mpt->m_fw_cv); 1667 cv_destroy(&mpt->m_config_cv); 1668 cv_destroy(&mpt->m_fw_diag_cv); 1669 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 1670 } 1671 1672 if (map_setup) { 1673 mptsas_cfg_fini(mpt); 1674 } 1675 if (config_setup) { 1676 mptsas_config_space_fini(mpt); 1677 } 1678 mptsas_free_handshake_msg(mpt); 1679 mptsas_hba_fini(mpt); 1680 1681 mptsas_fm_fini(mpt); 1682 ddi_soft_state_free(mptsas_state, instance); 1683 ddi_prop_remove_all(dip); 1684 } 1685 return (DDI_FAILURE); 1686 } 1687 1688 static int 1689 mptsas_suspend(dev_info_t *devi) 1690 { 1691 mptsas_t *mpt, *g; 1692 scsi_hba_tran_t *tran; 1693 1694 if (scsi_hba_iport_unit_address(devi)) { 1695 return (DDI_SUCCESS); 1696 } 1697 1698 if ((tran = ddi_get_driver_private(devi)) == NULL) 1699 return (DDI_SUCCESS); 1700 1701 mpt = TRAN2MPT(tran); 1702 if (!mpt) { 1703 return (DDI_SUCCESS); 1704 } 1705 1706 mutex_enter(&mpt->m_mutex); 1707 1708 if (mpt->m_suspended++) { 1709 mutex_exit(&mpt->m_mutex); 1710 return (DDI_SUCCESS); 1711 } 1712 1713 /* 1714 * Cancel timeout threads for this mpt 1715 */ 1716 if (mpt->m_quiesce_timeid) { 1717 timeout_id_t tid = mpt->m_quiesce_timeid; 1718 mpt->m_quiesce_timeid = 0; 1719 mutex_exit(&mpt->m_mutex); 1720 (void) untimeout(tid); 1721 mutex_enter(&mpt->m_mutex); 1722 } 1723 1724 if (mpt->m_restart_cmd_timeid) { 1725 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1726 mpt->m_restart_cmd_timeid = 0; 1727 mutex_exit(&mpt->m_mutex); 1728 (void) untimeout(tid); 1729 mutex_enter(&mpt->m_mutex); 1730 } 1731 1732 mutex_exit(&mpt->m_mutex); 1733 1734 (void) pm_idle_component(mpt->m_dip, 0); 1735 1736 /* 1737 * Cancel watch threads if all mpts suspended 1738 */ 1739 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1740 for (g = mptsas_head; g != NULL; g = g->m_next) { 1741 if (!g->m_suspended) 1742 break; 1743 } 1744 rw_exit(&mptsas_global_rwlock); 1745 1746 mutex_enter(&mptsas_global_mutex); 1747 if (g == NULL) { 1748 timeout_id_t tid; 1749 1750 mptsas_timeouts_enabled = 0; 1751 if (mptsas_timeout_id) { 1752 tid = mptsas_timeout_id; 1753 mptsas_timeout_id = 0; 1754 mutex_exit(&mptsas_global_mutex); 1755 (void) untimeout(tid); 1756 mutex_enter(&mptsas_global_mutex); 1757 } 1758 if (mptsas_reset_watch) { 1759 tid = mptsas_reset_watch; 1760 mptsas_reset_watch = 0; 1761 mutex_exit(&mptsas_global_mutex); 1762 (void) untimeout(tid); 1763 mutex_enter(&mptsas_global_mutex); 1764 } 1765 } 1766 mutex_exit(&mptsas_global_mutex); 1767 1768 mutex_enter(&mpt->m_mutex); 1769 1770 /* 1771 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1772 */ 1773 if ((mpt->m_options & MPTSAS_OPT_PM) && 1774 (mpt->m_power_level != PM_LEVEL_D0)) { 1775 mutex_exit(&mpt->m_mutex); 1776 return (DDI_SUCCESS); 1777 } 1778 1779 /* Disable HBA interrupts in hardware */ 1780 MPTSAS_DISABLE_INTR(mpt); 1781 /* 1782 * Send RAID action system shutdown to sync IR 1783 */ 1784 mptsas_raid_action_system_shutdown(mpt); 1785 1786 mutex_exit(&mpt->m_mutex); 1787 1788 /* drain the taskq */ 1789 ddi_taskq_wait(mpt->m_event_taskq); 1790 ddi_taskq_wait(mpt->m_dr_taskq); 1791 1792 return (DDI_SUCCESS); 1793 } 1794 1795 #ifdef __sparc 1796 /*ARGSUSED*/ 1797 static int 1798 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1799 { 1800 mptsas_t *mpt; 1801 scsi_hba_tran_t *tran; 1802 1803 /* 1804 * If this call is for iport, just return. 1805 */ 1806 if (scsi_hba_iport_unit_address(devi)) 1807 return (DDI_SUCCESS); 1808 1809 if ((tran = ddi_get_driver_private(devi)) == NULL) 1810 return (DDI_SUCCESS); 1811 1812 if ((mpt = TRAN2MPT(tran)) == NULL) 1813 return (DDI_SUCCESS); 1814 1815 /* 1816 * Send RAID action system shutdown to sync IR. Disable HBA 1817 * interrupts in hardware first. 1818 */ 1819 MPTSAS_DISABLE_INTR(mpt); 1820 mptsas_raid_action_system_shutdown(mpt); 1821 1822 return (DDI_SUCCESS); 1823 } 1824 #else /* __sparc */ 1825 /* 1826 * quiesce(9E) entry point. 1827 * 1828 * This function is called when the system is single-threaded at high 1829 * PIL with preemption disabled. Therefore, this function must not be 1830 * blocked. 1831 * 1832 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1833 * DDI_FAILURE indicates an error condition and should almost never happen. 1834 */ 1835 static int 1836 mptsas_quiesce(dev_info_t *devi) 1837 { 1838 mptsas_t *mpt; 1839 scsi_hba_tran_t *tran; 1840 1841 /* 1842 * If this call is for iport, just return. 1843 */ 1844 if (scsi_hba_iport_unit_address(devi)) 1845 return (DDI_SUCCESS); 1846 1847 if ((tran = ddi_get_driver_private(devi)) == NULL) 1848 return (DDI_SUCCESS); 1849 1850 if ((mpt = TRAN2MPT(tran)) == NULL) 1851 return (DDI_SUCCESS); 1852 1853 /* Disable HBA interrupts in hardware */ 1854 MPTSAS_DISABLE_INTR(mpt); 1855 /* Send RAID action system shutdonw to sync IR */ 1856 mptsas_raid_action_system_shutdown(mpt); 1857 1858 return (DDI_SUCCESS); 1859 } 1860 #endif /* __sparc */ 1861 1862 /* 1863 * detach(9E). Remove all device allocations and system resources; 1864 * disable device interrupts. 1865 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1866 */ 1867 static int 1868 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1869 { 1870 /* CONSTCOND */ 1871 ASSERT(NO_COMPETING_THREADS); 1872 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1873 1874 switch (cmd) { 1875 case DDI_DETACH: 1876 return (mptsas_do_detach(devi)); 1877 1878 case DDI_SUSPEND: 1879 return (mptsas_suspend(devi)); 1880 1881 default: 1882 return (DDI_FAILURE); 1883 } 1884 /* NOTREACHED */ 1885 } 1886 1887 static int 1888 mptsas_do_detach(dev_info_t *dip) 1889 { 1890 mptsas_t *mpt; 1891 scsi_hba_tran_t *tran; 1892 int circ = 0; 1893 int circ1 = 0; 1894 mdi_pathinfo_t *pip = NULL; 1895 int i; 1896 int doneq_thread_num = 0; 1897 1898 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1899 1900 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1901 return (DDI_FAILURE); 1902 1903 mpt = TRAN2MPT(tran); 1904 if (!mpt) { 1905 return (DDI_FAILURE); 1906 } 1907 1908 ddi_ufm_fini(mpt->m_ufmh); 1909 1910 /* 1911 * Still have pathinfo child, should not detach mpt driver 1912 */ 1913 if (scsi_hba_iport_unit_address(dip)) { 1914 if (mpt->m_mpxio_enable) { 1915 /* 1916 * MPxIO enabled for the iport 1917 */ 1918 ndi_devi_enter(scsi_vhci_dip, &circ1); 1919 ndi_devi_enter(dip, &circ); 1920 while ((pip = mdi_get_next_client_path(dip, NULL)) != 1921 NULL) { 1922 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1923 continue; 1924 } 1925 ndi_devi_exit(dip, circ); 1926 ndi_devi_exit(scsi_vhci_dip, circ1); 1927 NDBG12(("detach failed because of " 1928 "outstanding path info")); 1929 return (DDI_FAILURE); 1930 } 1931 ndi_devi_exit(dip, circ); 1932 ndi_devi_exit(scsi_vhci_dip, circ1); 1933 (void) mdi_phci_unregister(dip, 0); 1934 } 1935 1936 ddi_prop_remove_all(dip); 1937 1938 return (DDI_SUCCESS); 1939 } 1940 1941 /* Make sure power level is D0 before accessing registers */ 1942 if (mpt->m_options & MPTSAS_OPT_PM) { 1943 (void) pm_busy_component(dip, 0); 1944 if (mpt->m_power_level != PM_LEVEL_D0) { 1945 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1946 DDI_SUCCESS) { 1947 mptsas_log(mpt, CE_WARN, 1948 "mptsas%d: Raise power request failed.", 1949 mpt->m_instance); 1950 (void) pm_idle_component(dip, 0); 1951 return (DDI_FAILURE); 1952 } 1953 } 1954 } 1955 1956 /* 1957 * Send RAID action system shutdown to sync IR. After action, send a 1958 * Message Unit Reset. Since after that DMA resource will be freed, 1959 * set ioc to READY state will avoid HBA initiated DMA operation. 1960 */ 1961 mutex_enter(&mpt->m_mutex); 1962 MPTSAS_DISABLE_INTR(mpt); 1963 mptsas_raid_action_system_shutdown(mpt); 1964 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1965 (void) mptsas_ioc_reset(mpt, FALSE); 1966 mutex_exit(&mpt->m_mutex); 1967 mptsas_rem_intrs(mpt); 1968 ddi_taskq_destroy(mpt->m_event_taskq); 1969 ddi_taskq_destroy(mpt->m_dr_taskq); 1970 1971 if (mpt->m_doneq_thread_n) { 1972 mutex_enter(&mpt->m_doneq_mutex); 1973 doneq_thread_num = mpt->m_doneq_thread_n; 1974 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1975 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1976 mpt->m_doneq_thread_id[i].flag &= 1977 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1978 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1979 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1980 } 1981 while (mpt->m_doneq_thread_n) { 1982 cv_wait(&mpt->m_doneq_thread_cv, 1983 &mpt->m_doneq_mutex); 1984 } 1985 for (i = 0; i < doneq_thread_num; i++) { 1986 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1987 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1988 } 1989 kmem_free(mpt->m_doneq_thread_id, 1990 sizeof (mptsas_doneq_thread_list_t) 1991 * doneq_thread_num); 1992 mutex_exit(&mpt->m_doneq_mutex); 1993 cv_destroy(&mpt->m_doneq_thread_cv); 1994 mutex_destroy(&mpt->m_doneq_mutex); 1995 } 1996 1997 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1998 1999 mptsas_list_del(mpt); 2000 2001 /* 2002 * Cancel timeout threads for this mpt 2003 */ 2004 mutex_enter(&mpt->m_mutex); 2005 if (mpt->m_quiesce_timeid) { 2006 timeout_id_t tid = mpt->m_quiesce_timeid; 2007 mpt->m_quiesce_timeid = 0; 2008 mutex_exit(&mpt->m_mutex); 2009 (void) untimeout(tid); 2010 mutex_enter(&mpt->m_mutex); 2011 } 2012 2013 if (mpt->m_restart_cmd_timeid) { 2014 timeout_id_t tid = mpt->m_restart_cmd_timeid; 2015 mpt->m_restart_cmd_timeid = 0; 2016 mutex_exit(&mpt->m_mutex); 2017 (void) untimeout(tid); 2018 mutex_enter(&mpt->m_mutex); 2019 } 2020 2021 mutex_exit(&mpt->m_mutex); 2022 2023 /* 2024 * last mpt? ... if active, CANCEL watch threads. 2025 */ 2026 mutex_enter(&mptsas_global_mutex); 2027 if (mptsas_head == NULL) { 2028 timeout_id_t tid; 2029 /* 2030 * Clear mptsas_timeouts_enable so that the watch thread 2031 * gets restarted on DDI_ATTACH 2032 */ 2033 mptsas_timeouts_enabled = 0; 2034 if (mptsas_timeout_id) { 2035 tid = mptsas_timeout_id; 2036 mptsas_timeout_id = 0; 2037 mutex_exit(&mptsas_global_mutex); 2038 (void) untimeout(tid); 2039 mutex_enter(&mptsas_global_mutex); 2040 } 2041 if (mptsas_reset_watch) { 2042 tid = mptsas_reset_watch; 2043 mptsas_reset_watch = 0; 2044 mutex_exit(&mptsas_global_mutex); 2045 (void) untimeout(tid); 2046 mutex_enter(&mptsas_global_mutex); 2047 } 2048 } 2049 mutex_exit(&mptsas_global_mutex); 2050 2051 /* 2052 * Delete Phy stats 2053 */ 2054 mptsas_destroy_phy_stats(mpt); 2055 2056 mptsas_destroy_hashes(mpt); 2057 2058 /* 2059 * Delete nt_active. 2060 */ 2061 mutex_enter(&mpt->m_mutex); 2062 mptsas_free_active_slots(mpt); 2063 mutex_exit(&mpt->m_mutex); 2064 2065 /* deallocate everything that was allocated in mptsas_attach */ 2066 mptsas_cache_destroy(mpt); 2067 2068 mptsas_hba_fini(mpt); 2069 mptsas_cfg_fini(mpt); 2070 2071 /* Lower the power informing PM Framework */ 2072 if (mpt->m_options & MPTSAS_OPT_PM) { 2073 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 2074 mptsas_log(mpt, CE_WARN, 2075 "!mptsas%d: Lower power request failed " 2076 "during detach, ignoring.", 2077 mpt->m_instance); 2078 } 2079 2080 mutex_destroy(&mpt->m_tx_waitq_mutex); 2081 mutex_destroy(&mpt->m_passthru_mutex); 2082 mutex_destroy(&mpt->m_mutex); 2083 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 2084 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex); 2085 } 2086 cv_destroy(&mpt->m_cv); 2087 cv_destroy(&mpt->m_passthru_cv); 2088 cv_destroy(&mpt->m_fw_cv); 2089 cv_destroy(&mpt->m_config_cv); 2090 cv_destroy(&mpt->m_fw_diag_cv); 2091 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 2092 2093 mptsas_smp_teardown(mpt); 2094 mptsas_enc_teardown(mpt); 2095 mptsas_hba_teardown(mpt); 2096 2097 mptsas_config_space_fini(mpt); 2098 2099 mptsas_free_handshake_msg(mpt); 2100 2101 mptsas_fm_fini(mpt); 2102 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 2103 ddi_prop_remove_all(dip); 2104 2105 return (DDI_SUCCESS); 2106 } 2107 2108 static void 2109 mptsas_list_add(mptsas_t *mpt) 2110 { 2111 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2112 2113 if (mptsas_head == NULL) { 2114 mptsas_head = mpt; 2115 } else { 2116 mptsas_tail->m_next = mpt; 2117 } 2118 mptsas_tail = mpt; 2119 rw_exit(&mptsas_global_rwlock); 2120 } 2121 2122 static void 2123 mptsas_list_del(mptsas_t *mpt) 2124 { 2125 mptsas_t *m; 2126 /* 2127 * Remove device instance from the global linked list 2128 */ 2129 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2130 if (mptsas_head == mpt) { 2131 m = mptsas_head = mpt->m_next; 2132 } else { 2133 for (m = mptsas_head; m != NULL; m = m->m_next) { 2134 if (m->m_next == mpt) { 2135 m->m_next = mpt->m_next; 2136 break; 2137 } 2138 } 2139 if (m == NULL) { 2140 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 2141 } 2142 } 2143 2144 if (mptsas_tail == mpt) { 2145 mptsas_tail = m; 2146 } 2147 rw_exit(&mptsas_global_rwlock); 2148 } 2149 2150 static int 2151 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 2152 { 2153 ddi_dma_attr_t task_dma_attrs; 2154 2155 mpt->m_hshk_dma_size = 0; 2156 task_dma_attrs = mpt->m_msg_dma_attr; 2157 task_dma_attrs.dma_attr_sgllen = 1; 2158 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 2159 2160 /* allocate Task Management ddi_dma resources */ 2161 if (mptsas_dma_addr_create(mpt, task_dma_attrs, 2162 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp, 2163 alloc_size, NULL) == FALSE) { 2164 return (DDI_FAILURE); 2165 } 2166 mpt->m_hshk_dma_size = alloc_size; 2167 2168 return (DDI_SUCCESS); 2169 } 2170 2171 static void 2172 mptsas_free_handshake_msg(mptsas_t *mpt) 2173 { 2174 if (mpt->m_hshk_dma_size == 0) 2175 return; 2176 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl); 2177 mpt->m_hshk_dma_size = 0; 2178 } 2179 2180 static int 2181 mptsas_hba_setup(mptsas_t *mpt) 2182 { 2183 scsi_hba_tran_t *hba_tran; 2184 int tran_flags; 2185 2186 /* Allocate a transport structure */ 2187 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip, 2188 SCSI_HBA_CANSLEEP); 2189 ASSERT(mpt->m_tran != NULL); 2190 2191 hba_tran->tran_hba_private = mpt; 2192 hba_tran->tran_tgt_private = NULL; 2193 2194 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 2195 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 2196 2197 hba_tran->tran_start = mptsas_scsi_start; 2198 hba_tran->tran_reset = mptsas_scsi_reset; 2199 hba_tran->tran_abort = mptsas_scsi_abort; 2200 hba_tran->tran_getcap = mptsas_scsi_getcap; 2201 hba_tran->tran_setcap = mptsas_scsi_setcap; 2202 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 2203 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 2204 2205 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 2206 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 2207 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 2208 2209 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 2210 hba_tran->tran_get_name = mptsas_get_name; 2211 2212 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 2213 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 2214 hba_tran->tran_bus_reset = NULL; 2215 2216 hba_tran->tran_add_eventcall = NULL; 2217 hba_tran->tran_get_eventcookie = NULL; 2218 hba_tran->tran_post_event = NULL; 2219 hba_tran->tran_remove_eventcall = NULL; 2220 2221 hba_tran->tran_bus_config = mptsas_bus_config; 2222 2223 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 2224 2225 /* 2226 * All children of the HBA are iports. We need tran was cloned. 2227 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 2228 * inherited to iport's tran vector. 2229 */ 2230 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 2231 2232 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr, 2233 hba_tran, tran_flags) != DDI_SUCCESS) { 2234 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 2235 scsi_hba_tran_free(hba_tran); 2236 mpt->m_tran = NULL; 2237 return (FALSE); 2238 } 2239 return (TRUE); 2240 } 2241 2242 static void 2243 mptsas_hba_teardown(mptsas_t *mpt) 2244 { 2245 (void) scsi_hba_detach(mpt->m_dip); 2246 if (mpt->m_tran != NULL) { 2247 scsi_hba_tran_free(mpt->m_tran); 2248 mpt->m_tran = NULL; 2249 } 2250 } 2251 2252 static void 2253 mptsas_iport_register(mptsas_t *mpt) 2254 { 2255 int i, j; 2256 mptsas_phymask_t mask = 0x0; 2257 /* 2258 * initial value of mask is 0 2259 */ 2260 mutex_enter(&mpt->m_mutex); 2261 for (i = 0; i < mpt->m_num_phys; i++) { 2262 mptsas_phymask_t phy_mask = 0x0; 2263 char phy_mask_name[MPTSAS_MAX_PHYS]; 2264 uint8_t current_port; 2265 2266 if (mpt->m_phy_info[i].attached_devhdl == 0) 2267 continue; 2268 2269 bzero(phy_mask_name, sizeof (phy_mask_name)); 2270 2271 current_port = mpt->m_phy_info[i].port_num; 2272 2273 if ((mask & (1 << i)) != 0) 2274 continue; 2275 2276 for (j = 0; j < mpt->m_num_phys; j++) { 2277 if (mpt->m_phy_info[j].attached_devhdl && 2278 (mpt->m_phy_info[j].port_num == current_port)) { 2279 phy_mask |= (1 << j); 2280 } 2281 } 2282 mask = mask | phy_mask; 2283 2284 for (j = 0; j < mpt->m_num_phys; j++) { 2285 if ((phy_mask >> j) & 0x01) { 2286 mpt->m_phy_info[j].phy_mask = phy_mask; 2287 } 2288 } 2289 2290 (void) sprintf(phy_mask_name, "%x", phy_mask); 2291 2292 mutex_exit(&mpt->m_mutex); 2293 /* 2294 * register a iport 2295 */ 2296 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 2297 mutex_enter(&mpt->m_mutex); 2298 } 2299 mutex_exit(&mpt->m_mutex); 2300 /* 2301 * register a virtual port for RAID volume always 2302 */ 2303 (void) scsi_hba_iport_register(mpt->m_dip, "v0"); 2304 2305 } 2306 2307 static int 2308 mptsas_smp_setup(mptsas_t *mpt) 2309 { 2310 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip); 2311 ASSERT(mpt->m_smptran != NULL); 2312 mpt->m_smptran->smp_tran_hba_private = mpt; 2313 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 2314 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) { 2315 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 2316 smp_hba_tran_free(mpt->m_smptran); 2317 mpt->m_smptran = NULL; 2318 return (FALSE); 2319 } 2320 /* 2321 * Initialize smp hash table 2322 */ 2323 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT, 2324 mptsas_target_addr_hash, mptsas_target_addr_cmp, 2325 mptsas_smp_free, sizeof (mptsas_smp_t), 2326 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr), 2327 KM_SLEEP); 2328 mpt->m_smp_devhdl = 0xFFFF; 2329 2330 return (TRUE); 2331 } 2332 2333 static void 2334 mptsas_smp_teardown(mptsas_t *mpt) 2335 { 2336 (void) smp_hba_detach(mpt->m_dip); 2337 if (mpt->m_smptran != NULL) { 2338 smp_hba_tran_free(mpt->m_smptran); 2339 mpt->m_smptran = NULL; 2340 } 2341 mpt->m_smp_devhdl = 0; 2342 } 2343 2344 static int 2345 mptsas_enc_setup(mptsas_t *mpt) 2346 { 2347 list_create(&mpt->m_enclosures, sizeof (mptsas_enclosure_t), 2348 offsetof(mptsas_enclosure_t, me_link)); 2349 return (TRUE); 2350 } 2351 2352 static void 2353 mptsas_enc_free(mptsas_enclosure_t *mep) 2354 { 2355 if (mep == NULL) 2356 return; 2357 if (mep->me_slotleds != NULL) { 2358 VERIFY3U(mep->me_nslots, >, 0); 2359 kmem_free(mep->me_slotleds, sizeof (uint8_t) * mep->me_nslots); 2360 } 2361 kmem_free(mep, sizeof (mptsas_enclosure_t)); 2362 } 2363 2364 static void 2365 mptsas_enc_teardown(mptsas_t *mpt) 2366 { 2367 mptsas_enclosure_t *mep; 2368 2369 while ((mep = list_remove_head(&mpt->m_enclosures)) != NULL) { 2370 mptsas_enc_free(mep); 2371 } 2372 list_destroy(&mpt->m_enclosures); 2373 } 2374 2375 static mptsas_enclosure_t * 2376 mptsas_enc_lookup(mptsas_t *mpt, uint16_t hdl) 2377 { 2378 mptsas_enclosure_t *mep; 2379 2380 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 2381 2382 for (mep = list_head(&mpt->m_enclosures); mep != NULL; 2383 mep = list_next(&mpt->m_enclosures, mep)) { 2384 if (hdl == mep->me_enchdl) { 2385 return (mep); 2386 } 2387 } 2388 2389 return (NULL); 2390 } 2391 2392 static int 2393 mptsas_cache_create(mptsas_t *mpt) 2394 { 2395 int instance = mpt->m_instance; 2396 char buf[64]; 2397 2398 /* 2399 * create kmem cache for packets 2400 */ 2401 (void) sprintf(buf, "mptsas%d_cache", instance); 2402 mpt->m_kmem_cache = kmem_cache_create(buf, 2403 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 2404 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 2405 NULL, (void *)mpt, NULL, 0); 2406 2407 if (mpt->m_kmem_cache == NULL) { 2408 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 2409 return (FALSE); 2410 } 2411 2412 /* 2413 * create kmem cache for extra SGL frames if SGL cannot 2414 * be accomodated into main request frame. 2415 */ 2416 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 2417 mpt->m_cache_frames = kmem_cache_create(buf, 2418 sizeof (mptsas_cache_frames_t), 8, 2419 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 2420 NULL, (void *)mpt, NULL, 0); 2421 2422 if (mpt->m_cache_frames == NULL) { 2423 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 2424 return (FALSE); 2425 } 2426 2427 return (TRUE); 2428 } 2429 2430 static void 2431 mptsas_cache_destroy(mptsas_t *mpt) 2432 { 2433 /* deallocate in reverse order */ 2434 if (mpt->m_cache_frames) { 2435 kmem_cache_destroy(mpt->m_cache_frames); 2436 mpt->m_cache_frames = NULL; 2437 } 2438 if (mpt->m_kmem_cache) { 2439 kmem_cache_destroy(mpt->m_kmem_cache); 2440 mpt->m_kmem_cache = NULL; 2441 } 2442 } 2443 2444 static int 2445 mptsas_power(dev_info_t *dip, int component, int level) 2446 { 2447 #ifndef __lock_lint 2448 _NOTE(ARGUNUSED(component)) 2449 #endif 2450 mptsas_t *mpt; 2451 int rval = DDI_SUCCESS; 2452 int polls = 0; 2453 uint32_t ioc_status; 2454 2455 if (scsi_hba_iport_unit_address(dip) != 0) 2456 return (DDI_SUCCESS); 2457 2458 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2459 if (mpt == NULL) { 2460 return (DDI_FAILURE); 2461 } 2462 2463 mutex_enter(&mpt->m_mutex); 2464 2465 /* 2466 * If the device is busy, don't lower its power level 2467 */ 2468 if (mpt->m_busy && (mpt->m_power_level > level)) { 2469 mutex_exit(&mpt->m_mutex); 2470 return (DDI_FAILURE); 2471 } 2472 switch (level) { 2473 case PM_LEVEL_D0: 2474 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2475 MPTSAS_POWER_ON(mpt); 2476 /* 2477 * Wait up to 30 seconds for IOC to come out of reset. 2478 */ 2479 while (((ioc_status = ddi_get32(mpt->m_datap, 2480 &mpt->m_reg->Doorbell)) & 2481 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2482 if (polls++ > 3000) { 2483 break; 2484 } 2485 delay(drv_usectohz(10000)); 2486 } 2487 /* 2488 * If IOC is not in operational state, try to hard reset it. 2489 */ 2490 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2491 MPI2_IOC_STATE_OPERATIONAL) { 2492 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 2493 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2494 mptsas_log(mpt, CE_WARN, 2495 "mptsas_power: hard reset failed"); 2496 mutex_exit(&mpt->m_mutex); 2497 return (DDI_FAILURE); 2498 } 2499 } 2500 mpt->m_power_level = PM_LEVEL_D0; 2501 break; 2502 case PM_LEVEL_D3: 2503 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2504 MPTSAS_POWER_OFF(mpt); 2505 break; 2506 default: 2507 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2508 mpt->m_instance, level); 2509 rval = DDI_FAILURE; 2510 break; 2511 } 2512 mutex_exit(&mpt->m_mutex); 2513 return (rval); 2514 } 2515 2516 /* 2517 * Initialize configuration space and figure out which 2518 * chip and revison of the chip the mpt driver is using. 2519 */ 2520 static int 2521 mptsas_config_space_init(mptsas_t *mpt) 2522 { 2523 NDBG0(("mptsas_config_space_init")); 2524 2525 if (mpt->m_config_handle != NULL) 2526 return (TRUE); 2527 2528 if (pci_config_setup(mpt->m_dip, 2529 &mpt->m_config_handle) != DDI_SUCCESS) { 2530 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 2531 return (FALSE); 2532 } 2533 2534 /* 2535 * This is a workaround for a XMITS ASIC bug which does not 2536 * drive the CBE upper bits. 2537 */ 2538 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 2539 PCI_STAT_PERROR) { 2540 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 2541 PCI_STAT_PERROR); 2542 } 2543 2544 mptsas_setup_cmd_reg(mpt); 2545 2546 /* 2547 * Get the chip device id: 2548 */ 2549 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2550 2551 /* 2552 * Save the revision. 2553 */ 2554 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2555 2556 /* 2557 * Save the SubSystem Vendor and Device IDs 2558 */ 2559 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2560 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2561 2562 /* 2563 * Set the latency timer to 0x40 as specified by the upa -> pci 2564 * bridge chip design team. This may be done by the sparc pci 2565 * bus nexus driver, but the driver should make sure the latency 2566 * timer is correct for performance reasons. 2567 */ 2568 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2569 MPTSAS_LATENCY_TIMER); 2570 2571 (void) mptsas_get_pci_cap(mpt); 2572 return (TRUE); 2573 } 2574 2575 static void 2576 mptsas_config_space_fini(mptsas_t *mpt) 2577 { 2578 if (mpt->m_config_handle != NULL) { 2579 mptsas_disable_bus_master(mpt); 2580 pci_config_teardown(&mpt->m_config_handle); 2581 mpt->m_config_handle = NULL; 2582 } 2583 } 2584 2585 static void 2586 mptsas_setup_cmd_reg(mptsas_t *mpt) 2587 { 2588 ushort_t cmdreg; 2589 2590 /* 2591 * Set the command register to the needed values. 2592 */ 2593 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2594 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2595 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2596 cmdreg &= ~PCI_COMM_IO; 2597 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2598 } 2599 2600 static void 2601 mptsas_disable_bus_master(mptsas_t *mpt) 2602 { 2603 ushort_t cmdreg; 2604 2605 /* 2606 * Clear the master enable bit in the PCI command register. 2607 * This prevents any bus mastering activity like DMA. 2608 */ 2609 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2610 cmdreg &= ~PCI_COMM_ME; 2611 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2612 } 2613 2614 int 2615 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2616 { 2617 ddi_dma_attr_t attrs; 2618 2619 attrs = mpt->m_io_dma_attr; 2620 attrs.dma_attr_sgllen = 1; 2621 2622 ASSERT(dma_statep != NULL); 2623 2624 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle, 2625 &dma_statep->accessp, &dma_statep->memp, dma_statep->size, 2626 &dma_statep->cookie) == FALSE) { 2627 return (DDI_FAILURE); 2628 } 2629 2630 return (DDI_SUCCESS); 2631 } 2632 2633 void 2634 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2635 { 2636 ASSERT(dma_statep != NULL); 2637 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp); 2638 dma_statep->size = 0; 2639 } 2640 2641 int 2642 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2643 { 2644 ddi_dma_attr_t attrs; 2645 ddi_dma_handle_t dma_handle; 2646 caddr_t memp; 2647 ddi_acc_handle_t accessp; 2648 int rval; 2649 2650 ASSERT(mutex_owned(&mpt->m_mutex)); 2651 2652 attrs = mpt->m_msg_dma_attr; 2653 attrs.dma_attr_sgllen = 1; 2654 attrs.dma_attr_granular = size; 2655 2656 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle, 2657 &accessp, &memp, size, NULL) == FALSE) { 2658 return (DDI_FAILURE); 2659 } 2660 2661 rval = (*callback) (mpt, memp, var, accessp); 2662 2663 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2664 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2665 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2666 rval = DDI_FAILURE; 2667 } 2668 2669 mptsas_dma_addr_destroy(&dma_handle, &accessp); 2670 return (rval); 2671 2672 } 2673 2674 static int 2675 mptsas_alloc_request_frames(mptsas_t *mpt) 2676 { 2677 ddi_dma_attr_t frame_dma_attrs; 2678 caddr_t memp; 2679 ddi_dma_cookie_t cookie; 2680 size_t mem_size; 2681 2682 /* 2683 * re-alloc when it has already alloced 2684 */ 2685 if (mpt->m_dma_req_frame_hdl) 2686 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2687 &mpt->m_acc_req_frame_hdl); 2688 2689 /* 2690 * The size of the request frame pool is: 2691 * Number of Request Frames * Request Frame Size 2692 */ 2693 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2694 2695 /* 2696 * set the DMA attributes. System Request Message Frames must be 2697 * aligned on a 16-byte boundry. 2698 */ 2699 frame_dma_attrs = mpt->m_msg_dma_attr; 2700 frame_dma_attrs.dma_attr_align = 16; 2701 frame_dma_attrs.dma_attr_sgllen = 1; 2702 2703 /* 2704 * allocate the request frame pool. 2705 */ 2706 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2707 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp, 2708 mem_size, &cookie) == FALSE) { 2709 return (DDI_FAILURE); 2710 } 2711 2712 /* 2713 * Store the request frame memory address. This chip uses this 2714 * address to dma to and from the driver's frame. The second 2715 * address is the address mpt uses to fill in the frame. 2716 */ 2717 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2718 mpt->m_req_frame = memp; 2719 2720 /* 2721 * Clear the request frame pool. 2722 */ 2723 bzero(mpt->m_req_frame, mem_size); 2724 2725 return (DDI_SUCCESS); 2726 } 2727 2728 static int 2729 mptsas_alloc_sense_bufs(mptsas_t *mpt) 2730 { 2731 ddi_dma_attr_t sense_dma_attrs; 2732 caddr_t memp; 2733 ddi_dma_cookie_t cookie; 2734 size_t mem_size; 2735 int num_extrqsense_bufs; 2736 2737 ASSERT(mpt->m_extreq_sense_refcount == 0); 2738 2739 /* 2740 * re-alloc when it has already alloced 2741 */ 2742 if (mpt->m_dma_req_sense_hdl) { 2743 rmfreemap(mpt->m_erqsense_map); 2744 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 2745 &mpt->m_acc_req_sense_hdl); 2746 } 2747 2748 /* 2749 * The size of the request sense pool is: 2750 * (Number of Request Frames - 2 ) * Request Sense Size + 2751 * extra memory for extended sense requests. 2752 */ 2753 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) + 2754 mptsas_extreq_sense_bufsize; 2755 2756 /* 2757 * set the DMA attributes. ARQ buffers 2758 * aligned on a 16-byte boundry. 2759 */ 2760 sense_dma_attrs = mpt->m_msg_dma_attr; 2761 sense_dma_attrs.dma_attr_align = 16; 2762 sense_dma_attrs.dma_attr_sgllen = 1; 2763 2764 /* 2765 * allocate the request sense buffer pool. 2766 */ 2767 if (mptsas_dma_addr_create(mpt, sense_dma_attrs, 2768 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp, 2769 mem_size, &cookie) == FALSE) { 2770 return (DDI_FAILURE); 2771 } 2772 2773 /* 2774 * Store the request sense base memory address. This chip uses this 2775 * address to dma the request sense data. The second 2776 * address is the address mpt uses to access the data. 2777 * The third is the base for the extended rqsense buffers. 2778 */ 2779 mpt->m_req_sense_dma_addr = cookie.dmac_laddress; 2780 mpt->m_req_sense = memp; 2781 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size; 2782 mpt->m_extreq_sense = memp; 2783 2784 /* 2785 * The extra memory is divided up into multiples of the base 2786 * buffer size in order to allocate via rmalloc(). 2787 * Note that the rmallocmap cannot start at zero! 2788 */ 2789 num_extrqsense_bufs = mptsas_extreq_sense_bufsize / 2790 mpt->m_req_sense_size; 2791 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs); 2792 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1); 2793 2794 /* 2795 * Clear the pool. 2796 */ 2797 bzero(mpt->m_req_sense, mem_size); 2798 2799 return (DDI_SUCCESS); 2800 } 2801 2802 static int 2803 mptsas_alloc_reply_frames(mptsas_t *mpt) 2804 { 2805 ddi_dma_attr_t frame_dma_attrs; 2806 caddr_t memp; 2807 ddi_dma_cookie_t cookie; 2808 size_t mem_size; 2809 2810 /* 2811 * re-alloc when it has already alloced 2812 */ 2813 if (mpt->m_dma_reply_frame_hdl) { 2814 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2815 &mpt->m_acc_reply_frame_hdl); 2816 } 2817 2818 /* 2819 * The size of the reply frame pool is: 2820 * Number of Reply Frames * Reply Frame Size 2821 */ 2822 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2823 2824 /* 2825 * set the DMA attributes. System Reply Message Frames must be 2826 * aligned on a 4-byte boundry. This is the default. 2827 */ 2828 frame_dma_attrs = mpt->m_msg_dma_attr; 2829 frame_dma_attrs.dma_attr_sgllen = 1; 2830 2831 /* 2832 * allocate the reply frame pool 2833 */ 2834 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2835 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp, 2836 mem_size, &cookie) == FALSE) { 2837 return (DDI_FAILURE); 2838 } 2839 2840 /* 2841 * Store the reply frame memory address. This chip uses this 2842 * address to dma to and from the driver's frame. The second 2843 * address is the address mpt uses to process the frame. 2844 */ 2845 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2846 mpt->m_reply_frame = memp; 2847 2848 /* 2849 * Clear the reply frame pool. 2850 */ 2851 bzero(mpt->m_reply_frame, mem_size); 2852 2853 return (DDI_SUCCESS); 2854 } 2855 2856 static int 2857 mptsas_alloc_free_queue(mptsas_t *mpt) 2858 { 2859 ddi_dma_attr_t frame_dma_attrs; 2860 caddr_t memp; 2861 ddi_dma_cookie_t cookie; 2862 size_t mem_size; 2863 2864 /* 2865 * re-alloc when it has already alloced 2866 */ 2867 if (mpt->m_dma_free_queue_hdl) { 2868 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2869 &mpt->m_acc_free_queue_hdl); 2870 } 2871 2872 /* 2873 * The reply free queue size is: 2874 * Reply Free Queue Depth * 4 2875 * The "4" is the size of one 32 bit address (low part of 64-bit 2876 * address) 2877 */ 2878 mem_size = mpt->m_free_queue_depth * 4; 2879 2880 /* 2881 * set the DMA attributes The Reply Free Queue must be aligned on a 2882 * 16-byte boundry. 2883 */ 2884 frame_dma_attrs = mpt->m_msg_dma_attr; 2885 frame_dma_attrs.dma_attr_align = 16; 2886 frame_dma_attrs.dma_attr_sgllen = 1; 2887 2888 /* 2889 * allocate the reply free queue 2890 */ 2891 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2892 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp, 2893 mem_size, &cookie) == FALSE) { 2894 return (DDI_FAILURE); 2895 } 2896 2897 /* 2898 * Store the reply free queue memory address. This chip uses this 2899 * address to read from the reply free queue. The second address 2900 * is the address mpt uses to manage the queue. 2901 */ 2902 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2903 mpt->m_free_queue = memp; 2904 2905 /* 2906 * Clear the reply free queue memory. 2907 */ 2908 bzero(mpt->m_free_queue, mem_size); 2909 2910 return (DDI_SUCCESS); 2911 } 2912 2913 static int 2914 mptsas_alloc_post_queue(mptsas_t *mpt) 2915 { 2916 ddi_dma_attr_t frame_dma_attrs; 2917 caddr_t memp; 2918 ddi_dma_cookie_t cookie; 2919 size_t mem_size; 2920 2921 /* 2922 * re-alloc when it has already alloced 2923 */ 2924 if (mpt->m_dma_post_queue_hdl) { 2925 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2926 &mpt->m_acc_post_queue_hdl); 2927 } 2928 2929 /* 2930 * The reply descriptor post queue size is: 2931 * Reply Descriptor Post Queue Depth * 8 2932 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2933 */ 2934 mem_size = mpt->m_post_queue_depth * 8; 2935 2936 /* 2937 * set the DMA attributes. The Reply Descriptor Post Queue must be 2938 * aligned on a 16-byte boundry. 2939 */ 2940 frame_dma_attrs = mpt->m_msg_dma_attr; 2941 frame_dma_attrs.dma_attr_align = 16; 2942 frame_dma_attrs.dma_attr_sgllen = 1; 2943 2944 /* 2945 * allocate the reply post queue 2946 */ 2947 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2948 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp, 2949 mem_size, &cookie) == FALSE) { 2950 return (DDI_FAILURE); 2951 } 2952 2953 /* 2954 * Store the reply descriptor post queue memory address. This chip 2955 * uses this address to write to the reply descriptor post queue. The 2956 * second address is the address mpt uses to manage the queue. 2957 */ 2958 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2959 mpt->m_post_queue = memp; 2960 2961 /* 2962 * Clear the reply post queue memory. 2963 */ 2964 bzero(mpt->m_post_queue, mem_size); 2965 2966 return (DDI_SUCCESS); 2967 } 2968 2969 static void 2970 mptsas_alloc_reply_args(mptsas_t *mpt) 2971 { 2972 if (mpt->m_replyh_args == NULL) { 2973 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 2974 mpt->m_max_replies, KM_SLEEP); 2975 } 2976 } 2977 2978 static int 2979 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2980 { 2981 mptsas_cache_frames_t *frames = NULL; 2982 if (cmd->cmd_extra_frames == NULL) { 2983 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2984 if (frames == NULL) { 2985 return (DDI_FAILURE); 2986 } 2987 cmd->cmd_extra_frames = frames; 2988 } 2989 return (DDI_SUCCESS); 2990 } 2991 2992 static void 2993 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2994 { 2995 if (cmd->cmd_extra_frames) { 2996 kmem_cache_free(mpt->m_cache_frames, 2997 (void *)cmd->cmd_extra_frames); 2998 cmd->cmd_extra_frames = NULL; 2999 } 3000 } 3001 3002 static void 3003 mptsas_cfg_fini(mptsas_t *mpt) 3004 { 3005 NDBG0(("mptsas_cfg_fini")); 3006 ddi_regs_map_free(&mpt->m_datap); 3007 } 3008 3009 static void 3010 mptsas_hba_fini(mptsas_t *mpt) 3011 { 3012 NDBG0(("mptsas_hba_fini")); 3013 3014 /* 3015 * Free up any allocated memory 3016 */ 3017 if (mpt->m_dma_req_frame_hdl) { 3018 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 3019 &mpt->m_acc_req_frame_hdl); 3020 } 3021 3022 if (mpt->m_dma_req_sense_hdl) { 3023 rmfreemap(mpt->m_erqsense_map); 3024 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 3025 &mpt->m_acc_req_sense_hdl); 3026 } 3027 3028 if (mpt->m_dma_reply_frame_hdl) { 3029 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 3030 &mpt->m_acc_reply_frame_hdl); 3031 } 3032 3033 if (mpt->m_dma_free_queue_hdl) { 3034 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 3035 &mpt->m_acc_free_queue_hdl); 3036 } 3037 3038 if (mpt->m_dma_post_queue_hdl) { 3039 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 3040 &mpt->m_acc_post_queue_hdl); 3041 } 3042 3043 if (mpt->m_replyh_args != NULL) { 3044 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 3045 * mpt->m_max_replies); 3046 } 3047 } 3048 3049 static int 3050 mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 3051 { 3052 int lun = 0; 3053 char *sas_wwn = NULL; 3054 int phynum = -1; 3055 int reallen = 0; 3056 3057 /* Get the target num */ 3058 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 3059 LUN_PROP, 0); 3060 3061 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 3062 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 3063 /* 3064 * Stick in the address of form "pPHY,LUN" 3065 */ 3066 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 3067 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, 3068 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) 3069 == DDI_PROP_SUCCESS) { 3070 /* 3071 * Stick in the address of the form "wWWN,LUN" 3072 */ 3073 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun); 3074 ddi_prop_free(sas_wwn); 3075 } else { 3076 return (DDI_FAILURE); 3077 } 3078 3079 ASSERT(reallen < len); 3080 if (reallen >= len) { 3081 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 3082 "length too small, it needs to be %d bytes", reallen + 1); 3083 } 3084 return (DDI_SUCCESS); 3085 } 3086 3087 /* 3088 * tran_tgt_init(9E) - target device instance initialization 3089 */ 3090 static int 3091 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3092 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3093 { 3094 #ifndef __lock_lint 3095 _NOTE(ARGUNUSED(hba_tran)) 3096 #endif 3097 3098 /* 3099 * At this point, the scsi_device structure already exists 3100 * and has been initialized. 3101 * 3102 * Use this function to allocate target-private data structures, 3103 * if needed by this HBA. Add revised flow-control and queue 3104 * properties for child here, if desired and if you can tell they 3105 * support tagged queueing by now. 3106 */ 3107 mptsas_t *mpt; 3108 int lun = sd->sd_address.a_lun; 3109 mdi_pathinfo_t *pip = NULL; 3110 mptsas_tgt_private_t *tgt_private = NULL; 3111 mptsas_target_t *ptgt = NULL; 3112 char *psas_wwn = NULL; 3113 mptsas_phymask_t phymask = 0; 3114 uint64_t sas_wwn = 0; 3115 mptsas_target_addr_t addr; 3116 mpt = SDEV2MPT(sd); 3117 3118 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 3119 3120 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 3121 (void *)hba_dip, (void *)tgt_dip, lun)); 3122 3123 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 3124 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 3125 ddi_set_name_addr(tgt_dip, NULL); 3126 return (DDI_FAILURE); 3127 } 3128 /* 3129 * phymask is 0 means the virtual port for RAID 3130 */ 3131 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 3132 "phymask", 0); 3133 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3134 if ((pip = (void *)(sd->sd_private)) == NULL) { 3135 /* 3136 * Very bad news if this occurs. Somehow scsi_vhci has 3137 * lost the pathinfo node for this target. 3138 */ 3139 return (DDI_NOT_WELL_FORMED); 3140 } 3141 3142 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 3143 DDI_PROP_SUCCESS) { 3144 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 3145 return (DDI_FAILURE); 3146 } 3147 3148 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 3149 &psas_wwn) == MDI_SUCCESS) { 3150 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3151 sas_wwn = 0; 3152 } 3153 (void) mdi_prop_free(psas_wwn); 3154 } 3155 } else { 3156 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 3157 DDI_PROP_DONTPASS, LUN_PROP, 0); 3158 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 3159 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 3160 DDI_PROP_SUCCESS) { 3161 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3162 sas_wwn = 0; 3163 } 3164 ddi_prop_free(psas_wwn); 3165 } else { 3166 sas_wwn = 0; 3167 } 3168 } 3169 3170 ASSERT((sas_wwn != 0) || (phymask != 0)); 3171 addr.mta_wwn = sas_wwn; 3172 addr.mta_phymask = phymask; 3173 mutex_enter(&mpt->m_mutex); 3174 ptgt = refhash_lookup(mpt->m_targets, &addr); 3175 mutex_exit(&mpt->m_mutex); 3176 if (ptgt == NULL) { 3177 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 3178 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 3179 sas_wwn); 3180 return (DDI_FAILURE); 3181 } 3182 if (hba_tran->tran_tgt_private == NULL) { 3183 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 3184 KM_SLEEP); 3185 tgt_private->t_lun = lun; 3186 tgt_private->t_private = ptgt; 3187 hba_tran->tran_tgt_private = tgt_private; 3188 } 3189 3190 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3191 return (DDI_SUCCESS); 3192 } 3193 mutex_enter(&mpt->m_mutex); 3194 3195 if (ptgt->m_deviceinfo & 3196 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 3197 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 3198 uchar_t *inq89 = NULL; 3199 int inq89_len = 0x238; 3200 int reallen = 0; 3201 int rval = 0; 3202 struct sata_id *sid = NULL; 3203 char model[SATA_ID_MODEL_LEN + 1]; 3204 char fw[SATA_ID_FW_LEN + 1]; 3205 char *vid, *pid; 3206 3207 mutex_exit(&mpt->m_mutex); 3208 /* 3209 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 3210 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 3211 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 3212 */ 3213 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 3214 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 3215 inq89, inq89_len, &reallen, 1); 3216 3217 if (rval != 0) { 3218 if (inq89 != NULL) { 3219 kmem_free(inq89, inq89_len); 3220 } 3221 3222 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 3223 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 3224 return (DDI_SUCCESS); 3225 } 3226 sid = (void *)(&inq89[60]); 3227 3228 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 3229 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 3230 3231 model[SATA_ID_MODEL_LEN] = 0; 3232 fw[SATA_ID_FW_LEN] = 0; 3233 3234 sata_split_model(model, &vid, &pid); 3235 3236 /* 3237 * override SCSA "inquiry-*" properties 3238 */ 3239 if (vid) 3240 (void) scsi_device_prop_update_inqstring(sd, 3241 INQUIRY_VENDOR_ID, vid, strlen(vid)); 3242 if (pid) 3243 (void) scsi_device_prop_update_inqstring(sd, 3244 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 3245 (void) scsi_device_prop_update_inqstring(sd, 3246 INQUIRY_REVISION_ID, fw, strlen(fw)); 3247 3248 if (inq89 != NULL) { 3249 kmem_free(inq89, inq89_len); 3250 } 3251 } else { 3252 mutex_exit(&mpt->m_mutex); 3253 } 3254 3255 return (DDI_SUCCESS); 3256 } 3257 /* 3258 * tran_tgt_free(9E) - target device instance deallocation 3259 */ 3260 static void 3261 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3262 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3263 { 3264 #ifndef __lock_lint 3265 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 3266 #endif 3267 3268 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 3269 3270 if (tgt_private != NULL) { 3271 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 3272 hba_tran->tran_tgt_private = NULL; 3273 } 3274 } 3275 3276 /* 3277 * scsi_pkt handling 3278 * 3279 * Visible to the external world via the transport structure. 3280 */ 3281 3282 /* 3283 * Notes: 3284 * - transport the command to the addressed SCSI target/lun device 3285 * - normal operation is to schedule the command to be transported, 3286 * and return TRAN_ACCEPT if this is successful. 3287 * - if NO_INTR, tran_start must poll device for command completion 3288 */ 3289 static int 3290 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 3291 { 3292 #ifndef __lock_lint 3293 _NOTE(ARGUNUSED(ap)) 3294 #endif 3295 mptsas_t *mpt = PKT2MPT(pkt); 3296 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3297 int rval; 3298 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3299 3300 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 3301 ASSERT(ptgt); 3302 if (ptgt == NULL) 3303 return (TRAN_FATAL_ERROR); 3304 3305 /* 3306 * prepare the pkt before taking mutex. 3307 */ 3308 rval = mptsas_prepare_pkt(cmd); 3309 if (rval != TRAN_ACCEPT) { 3310 return (rval); 3311 } 3312 3313 /* 3314 * Send the command to target/lun, however your HBA requires it. 3315 * If busy, return TRAN_BUSY; if there's some other formatting error 3316 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 3317 * return of TRAN_ACCEPT. 3318 * 3319 * Remember that access to shared resources, including the mptsas_t 3320 * data structure and the HBA hardware registers, must be protected 3321 * with mutexes, here and everywhere. 3322 * 3323 * Also remember that at interrupt time, you'll get an argument 3324 * to the interrupt handler which is a pointer to your mptsas_t 3325 * structure; you'll have to remember which commands are outstanding 3326 * and which scsi_pkt is the currently-running command so the 3327 * interrupt handler can refer to the pkt to set completion 3328 * status, call the target driver back through pkt_comp, etc. 3329 * 3330 * If the instance lock is held by other thread, don't spin to wait 3331 * for it. Instead, queue the cmd and next time when the instance lock 3332 * is not held, accept all the queued cmd. A extra tx_waitq is 3333 * introduced to protect the queue. 3334 * 3335 * The polled cmd will not be queud and accepted as usual. 3336 * 3337 * Under the tx_waitq mutex, record whether a thread is draining 3338 * the tx_waitq. An IO requesting thread that finds the instance 3339 * mutex contended appends to the tx_waitq and while holding the 3340 * tx_wait mutex, if the draining flag is not set, sets it and then 3341 * proceeds to spin for the instance mutex. This scheme ensures that 3342 * the last cmd in a burst be processed. 3343 * 3344 * we enable this feature only when the helper threads are enabled, 3345 * at which we think the loads are heavy. 3346 * 3347 * per instance mutex m_tx_waitq_mutex is introduced to protect the 3348 * m_tx_waitqtail, m_tx_waitq, m_tx_draining. 3349 */ 3350 3351 if (mpt->m_doneq_thread_n) { 3352 if (mutex_tryenter(&mpt->m_mutex) != 0) { 3353 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3354 mutex_exit(&mpt->m_mutex); 3355 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3356 mutex_enter(&mpt->m_mutex); 3357 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3358 mutex_exit(&mpt->m_mutex); 3359 } else { 3360 mutex_enter(&mpt->m_tx_waitq_mutex); 3361 /* 3362 * ptgt->m_dr_flag is protected by m_mutex or 3363 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex 3364 * is acquired. 3365 */ 3366 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3367 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3368 /* 3369 * The command should be allowed to 3370 * retry by returning TRAN_BUSY to 3371 * to stall the I/O's which come from 3372 * scsi_vhci since the device/path is 3373 * in unstable state now. 3374 */ 3375 mutex_exit(&mpt->m_tx_waitq_mutex); 3376 return (TRAN_BUSY); 3377 } else { 3378 /* 3379 * The device is offline, just fail the 3380 * command by returning 3381 * TRAN_FATAL_ERROR. 3382 */ 3383 mutex_exit(&mpt->m_tx_waitq_mutex); 3384 return (TRAN_FATAL_ERROR); 3385 } 3386 } 3387 if (mpt->m_tx_draining) { 3388 cmd->cmd_flags |= CFLAG_TXQ; 3389 *mpt->m_tx_waitqtail = cmd; 3390 mpt->m_tx_waitqtail = &cmd->cmd_linkp; 3391 mutex_exit(&mpt->m_tx_waitq_mutex); 3392 } else { /* drain the queue */ 3393 mpt->m_tx_draining = 1; 3394 mutex_exit(&mpt->m_tx_waitq_mutex); 3395 mutex_enter(&mpt->m_mutex); 3396 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3397 mutex_exit(&mpt->m_mutex); 3398 } 3399 } 3400 } else { 3401 mutex_enter(&mpt->m_mutex); 3402 /* 3403 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3404 * in this case, m_mutex is acquired. 3405 */ 3406 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3407 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3408 /* 3409 * commands should be allowed to retry by 3410 * returning TRAN_BUSY to stall the I/O's 3411 * which come from scsi_vhci since the device/ 3412 * path is in unstable state now. 3413 */ 3414 mutex_exit(&mpt->m_mutex); 3415 return (TRAN_BUSY); 3416 } else { 3417 /* 3418 * The device is offline, just fail the 3419 * command by returning TRAN_FATAL_ERROR. 3420 */ 3421 mutex_exit(&mpt->m_mutex); 3422 return (TRAN_FATAL_ERROR); 3423 } 3424 } 3425 rval = mptsas_accept_pkt(mpt, cmd); 3426 mutex_exit(&mpt->m_mutex); 3427 } 3428 3429 return (rval); 3430 } 3431 3432 /* 3433 * Accept all the queued cmds(if any) before accept the current one. 3434 */ 3435 static int 3436 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3437 { 3438 int rval; 3439 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3440 3441 ASSERT(mutex_owned(&mpt->m_mutex)); 3442 /* 3443 * The call to mptsas_accept_tx_waitq() must always be performed 3444 * because that is where mpt->m_tx_draining is cleared. 3445 */ 3446 mutex_enter(&mpt->m_tx_waitq_mutex); 3447 mptsas_accept_tx_waitq(mpt); 3448 mutex_exit(&mpt->m_tx_waitq_mutex); 3449 /* 3450 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3451 * in this case, m_mutex is acquired. 3452 */ 3453 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3454 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3455 /* 3456 * The command should be allowed to retry by returning 3457 * TRAN_BUSY to stall the I/O's which come from 3458 * scsi_vhci since the device/path is in unstable state 3459 * now. 3460 */ 3461 return (TRAN_BUSY); 3462 } else { 3463 /* 3464 * The device is offline, just fail the command by 3465 * return TRAN_FATAL_ERROR. 3466 */ 3467 return (TRAN_FATAL_ERROR); 3468 } 3469 } 3470 rval = mptsas_accept_pkt(mpt, cmd); 3471 3472 return (rval); 3473 } 3474 3475 static int 3476 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3477 { 3478 int rval = TRAN_ACCEPT; 3479 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3480 3481 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3482 3483 ASSERT(mutex_owned(&mpt->m_mutex)); 3484 3485 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3486 rval = mptsas_prepare_pkt(cmd); 3487 if (rval != TRAN_ACCEPT) { 3488 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3489 return (rval); 3490 } 3491 } 3492 3493 /* 3494 * reset the throttle if we were draining 3495 */ 3496 if ((ptgt->m_t_ncmds == 0) && 3497 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3498 NDBG23(("reset throttle")); 3499 ASSERT(ptgt->m_reset_delay == 0); 3500 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3501 } 3502 3503 /* 3504 * If HBA is being reset, the DevHandles are being re-initialized, 3505 * which means that they could be invalid even if the target is still 3506 * attached. Check if being reset and if DevHandle is being 3507 * re-initialized. If this is the case, return BUSY so the I/O can be 3508 * retried later. 3509 */ 3510 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) { 3511 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 3512 if (cmd->cmd_flags & CFLAG_TXQ) { 3513 mptsas_doneq_add(mpt, cmd); 3514 mptsas_doneq_empty(mpt); 3515 return (rval); 3516 } else { 3517 return (TRAN_BUSY); 3518 } 3519 } 3520 3521 /* 3522 * If device handle has already been invalidated, just 3523 * fail the command. In theory, command from scsi_vhci 3524 * client is impossible send down command with invalid 3525 * devhdl since devhdl is set after path offline, target 3526 * driver is not suppose to select a offlined path. 3527 */ 3528 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3529 NDBG3(("rejecting command, it might because invalid devhdl " 3530 "request.")); 3531 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3532 if (cmd->cmd_flags & CFLAG_TXQ) { 3533 mptsas_doneq_add(mpt, cmd); 3534 mptsas_doneq_empty(mpt); 3535 return (rval); 3536 } else { 3537 return (TRAN_FATAL_ERROR); 3538 } 3539 } 3540 /* 3541 * The first case is the normal case. mpt gets a command from the 3542 * target driver and starts it. 3543 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3544 * commands is m_max_requests - 2. 3545 */ 3546 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 3547 (ptgt->m_t_throttle > HOLD_THROTTLE) && 3548 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3549 (ptgt->m_reset_delay == 0) && 3550 (ptgt->m_t_nwait == 0) && 3551 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3552 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3553 (void) mptsas_start_cmd(mpt, cmd); 3554 } else { 3555 mptsas_waitq_add(mpt, cmd); 3556 } 3557 } else { 3558 /* 3559 * Add this pkt to the work queue 3560 */ 3561 mptsas_waitq_add(mpt, cmd); 3562 3563 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3564 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3565 3566 /* 3567 * Only flush the doneq if this is not a TM 3568 * cmd. For TM cmds the flushing of the 3569 * doneq will be done in those routines. 3570 */ 3571 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3572 mptsas_doneq_empty(mpt); 3573 } 3574 } 3575 } 3576 return (rval); 3577 } 3578 3579 int 3580 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3581 { 3582 mptsas_slots_t *slots = mpt->m_active; 3583 uint_t slot, start_rotor; 3584 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3585 3586 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 3587 3588 /* 3589 * Account for reserved TM request slot and reserved SMID of 0. 3590 */ 3591 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2)); 3592 3593 /* 3594 * Find the next available slot, beginning at m_rotor. If no slot is 3595 * available, we'll return FALSE to indicate that. This mechanism 3596 * considers only the normal slots, not the reserved slot 0 nor the 3597 * task management slot m_n_normal + 1. The rotor is left to point to 3598 * the normal slot after the one we select, unless we select the last 3599 * normal slot in which case it returns to slot 1. 3600 */ 3601 start_rotor = slots->m_rotor; 3602 do { 3603 slot = slots->m_rotor++; 3604 if (slots->m_rotor > slots->m_n_normal) 3605 slots->m_rotor = 1; 3606 3607 if (slots->m_rotor == start_rotor) 3608 break; 3609 } while (slots->m_slot[slot] != NULL); 3610 3611 if (slots->m_slot[slot] != NULL) 3612 return (FALSE); 3613 3614 ASSERT(slot != 0 && slot <= slots->m_n_normal); 3615 3616 cmd->cmd_slot = slot; 3617 slots->m_slot[slot] = cmd; 3618 mpt->m_ncmds++; 3619 3620 /* 3621 * only increment per target ncmds if this is not a 3622 * command that has no target associated with it (i.e. a 3623 * event acknoledgment) 3624 */ 3625 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3626 /* 3627 * Expiration time is set in mptsas_start_cmd 3628 */ 3629 ptgt->m_t_ncmds++; 3630 cmd->cmd_active_expiration = 0; 3631 } else { 3632 /* 3633 * Initialize expiration time for passthrough commands, 3634 */ 3635 cmd->cmd_active_expiration = gethrtime() + 3636 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC; 3637 } 3638 return (TRUE); 3639 } 3640 3641 /* 3642 * prepare the pkt: 3643 * the pkt may have been resubmitted or just reused so 3644 * initialize some fields and do some checks. 3645 */ 3646 static int 3647 mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3648 { 3649 struct scsi_pkt *pkt = CMD2PKT(cmd); 3650 3651 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3652 3653 /* 3654 * Reinitialize some fields that need it; the packet may 3655 * have been resubmitted 3656 */ 3657 pkt->pkt_reason = CMD_CMPLT; 3658 pkt->pkt_state = 0; 3659 pkt->pkt_statistics = 0; 3660 pkt->pkt_resid = 0; 3661 cmd->cmd_age = 0; 3662 cmd->cmd_pkt_flags = pkt->pkt_flags; 3663 3664 /* 3665 * zero status byte. 3666 */ 3667 *(pkt->pkt_scbp) = 0; 3668 3669 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3670 pkt->pkt_resid = cmd->cmd_dmacount; 3671 3672 /* 3673 * consistent packets need to be sync'ed first 3674 * (only for data going out) 3675 */ 3676 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3677 (cmd->cmd_flags & CFLAG_DMASEND)) { 3678 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3679 DDI_DMA_SYNC_FORDEV); 3680 } 3681 } 3682 3683 cmd->cmd_flags = 3684 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3685 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3686 3687 return (TRAN_ACCEPT); 3688 } 3689 3690 /* 3691 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3692 * 3693 * One of three possibilities: 3694 * - allocate scsi_pkt 3695 * - allocate scsi_pkt and DMA resources 3696 * - allocate DMA resources to an already-allocated pkt 3697 */ 3698 static struct scsi_pkt * 3699 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3700 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3701 int (*callback)(), caddr_t arg) 3702 { 3703 mptsas_cmd_t *cmd, *new_cmd; 3704 mptsas_t *mpt = ADDR2MPT(ap); 3705 uint_t oldcookiec; 3706 mptsas_target_t *ptgt = NULL; 3707 int rval; 3708 mptsas_tgt_private_t *tgt_private; 3709 int kf; 3710 3711 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3712 3713 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3714 tran_tgt_private; 3715 ASSERT(tgt_private != NULL); 3716 if (tgt_private == NULL) { 3717 return (NULL); 3718 } 3719 ptgt = tgt_private->t_private; 3720 ASSERT(ptgt != NULL); 3721 if (ptgt == NULL) 3722 return (NULL); 3723 ap->a_target = ptgt->m_devhdl; 3724 ap->a_lun = tgt_private->t_lun; 3725 3726 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3727 #ifdef MPTSAS_TEST_EXTRN_ALLOC 3728 statuslen *= 100; tgtlen *= 4; 3729 #endif 3730 NDBG3(("mptsas_scsi_init_pkt:\n" 3731 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3732 ap->a_target, (void *)pkt, (void *)bp, 3733 cmdlen, statuslen, tgtlen, flags)); 3734 3735 /* 3736 * Allocate the new packet. 3737 */ 3738 if (pkt == NULL) { 3739 ddi_dma_handle_t save_dma_handle; 3740 3741 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3742 if (cmd == NULL) 3743 return (NULL); 3744 3745 save_dma_handle = cmd->cmd_dmahandle; 3746 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3747 cmd->cmd_dmahandle = save_dma_handle; 3748 3749 pkt = (void *)((uchar_t *)cmd + 3750 sizeof (struct mptsas_cmd)); 3751 pkt->pkt_ha_private = (opaque_t)cmd; 3752 pkt->pkt_address = *ap; 3753 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3754 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3755 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3756 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3757 cmd->cmd_cdblen = (uchar_t)cmdlen; 3758 cmd->cmd_scblen = statuslen; 3759 cmd->cmd_rqslen = SENSE_LENGTH; 3760 cmd->cmd_tgt_addr = ptgt; 3761 3762 if ((cmdlen > sizeof (cmd->cmd_cdb)) || 3763 (tgtlen > PKT_PRIV_LEN) || 3764 (statuslen > EXTCMDS_STATUS_SIZE)) { 3765 int failure; 3766 3767 /* 3768 * We are going to allocate external packet space which 3769 * might include the sense data buffer for DMA so we 3770 * need to increase the reference counter here. In a 3771 * case the HBA is in reset we just simply free the 3772 * allocated packet and bail out. 3773 */ 3774 mutex_enter(&mpt->m_mutex); 3775 if (mpt->m_in_reset) { 3776 mutex_exit(&mpt->m_mutex); 3777 3778 cmd->cmd_flags = CFLAG_FREE; 3779 kmem_cache_free(mpt->m_kmem_cache, cmd); 3780 return (NULL); 3781 } 3782 mpt->m_extreq_sense_refcount++; 3783 ASSERT(mpt->m_extreq_sense_refcount > 0); 3784 mutex_exit(&mpt->m_mutex); 3785 3786 /* 3787 * if extern alloc fails, all will be 3788 * deallocated, including cmd 3789 */ 3790 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3791 cmdlen, tgtlen, statuslen, kf); 3792 3793 if (failure != 0 || cmd->cmd_extrqslen == 0) { 3794 /* 3795 * If the external packet space allocation 3796 * failed, or we didn't allocate the sense 3797 * data buffer for DMA we need to decrease the 3798 * reference counter. 3799 */ 3800 mutex_enter(&mpt->m_mutex); 3801 ASSERT(mpt->m_extreq_sense_refcount > 0); 3802 mpt->m_extreq_sense_refcount--; 3803 if (mpt->m_extreq_sense_refcount == 0) 3804 cv_broadcast( 3805 &mpt->m_extreq_sense_refcount_cv); 3806 mutex_exit(&mpt->m_mutex); 3807 3808 if (failure != 0) { 3809 /* 3810 * if extern allocation fails, it will 3811 * deallocate the new pkt as well 3812 */ 3813 return (NULL); 3814 } 3815 } 3816 } 3817 new_cmd = cmd; 3818 3819 } else { 3820 cmd = PKT2CMD(pkt); 3821 new_cmd = NULL; 3822 } 3823 3824 3825 /* grab cmd->cmd_cookiec here as oldcookiec */ 3826 3827 oldcookiec = cmd->cmd_cookiec; 3828 3829 /* 3830 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3831 * greater than 0 and we'll need to grab the next dma window 3832 */ 3833 /* 3834 * SLM-not doing extra command frame right now; may add later 3835 */ 3836 3837 if (cmd->cmd_nwin > 0) { 3838 3839 /* 3840 * Make sure we havn't gone past the the total number 3841 * of windows 3842 */ 3843 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3844 return (NULL); 3845 } 3846 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3847 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3848 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3849 return (NULL); 3850 } 3851 goto get_dma_cookies; 3852 } 3853 3854 3855 if (flags & PKT_XARQ) { 3856 cmd->cmd_flags |= CFLAG_XARQ; 3857 } 3858 3859 /* 3860 * DMA resource allocation. This version assumes your 3861 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3862 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3863 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3864 */ 3865 if (bp && (bp->b_bcount != 0) && 3866 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3867 3868 int cnt, dma_flags; 3869 mptti_t *dmap; /* ptr to the S/G list */ 3870 3871 /* 3872 * Set up DMA memory and position to the next DMA segment. 3873 */ 3874 ASSERT(cmd->cmd_dmahandle != NULL); 3875 3876 if (bp->b_flags & B_READ) { 3877 dma_flags = DDI_DMA_READ; 3878 cmd->cmd_flags &= ~CFLAG_DMASEND; 3879 } else { 3880 dma_flags = DDI_DMA_WRITE; 3881 cmd->cmd_flags |= CFLAG_DMASEND; 3882 } 3883 if (flags & PKT_CONSISTENT) { 3884 cmd->cmd_flags |= CFLAG_CMDIOPB; 3885 dma_flags |= DDI_DMA_CONSISTENT; 3886 } 3887 3888 if (flags & PKT_DMA_PARTIAL) { 3889 dma_flags |= DDI_DMA_PARTIAL; 3890 } 3891 3892 /* 3893 * workaround for byte hole issue on psycho and 3894 * schizo pre 2.1 3895 */ 3896 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3897 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3898 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3899 dma_flags |= DDI_DMA_CONSISTENT; 3900 } 3901 3902 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3903 dma_flags, callback, arg, 3904 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3905 if (rval == DDI_DMA_PARTIAL_MAP) { 3906 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3907 &cmd->cmd_nwin); 3908 cmd->cmd_winindex = 0; 3909 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3910 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3911 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3912 &cmd->cmd_cookiec); 3913 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3914 switch (rval) { 3915 case DDI_DMA_NORESOURCES: 3916 bioerror(bp, 0); 3917 break; 3918 case DDI_DMA_BADATTR: 3919 case DDI_DMA_NOMAPPING: 3920 bioerror(bp, EFAULT); 3921 break; 3922 case DDI_DMA_TOOBIG: 3923 default: 3924 bioerror(bp, EINVAL); 3925 break; 3926 } 3927 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3928 if (new_cmd) { 3929 mptsas_scsi_destroy_pkt(ap, pkt); 3930 } 3931 return ((struct scsi_pkt *)NULL); 3932 } 3933 3934 get_dma_cookies: 3935 cmd->cmd_flags |= CFLAG_DMAVALID; 3936 ASSERT(cmd->cmd_cookiec > 0); 3937 3938 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3939 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3940 cmd->cmd_cookiec); 3941 bioerror(bp, EINVAL); 3942 if (new_cmd) { 3943 mptsas_scsi_destroy_pkt(ap, pkt); 3944 } 3945 return ((struct scsi_pkt *)NULL); 3946 } 3947 3948 /* 3949 * Allocate extra SGL buffer if needed. 3950 */ 3951 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3952 (cmd->cmd_extra_frames == NULL)) { 3953 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3954 DDI_FAILURE) { 3955 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3956 "failed"); 3957 bioerror(bp, ENOMEM); 3958 if (new_cmd) { 3959 mptsas_scsi_destroy_pkt(ap, pkt); 3960 } 3961 return ((struct scsi_pkt *)NULL); 3962 } 3963 } 3964 3965 /* 3966 * Always use scatter-gather transfer 3967 * Use the loop below to store physical addresses of 3968 * DMA segments, from the DMA cookies, into your HBA's 3969 * scatter-gather list. 3970 * We need to ensure we have enough kmem alloc'd 3971 * for the sg entries since we are no longer using an 3972 * array inside mptsas_cmd_t. 3973 * 3974 * We check cmd->cmd_cookiec against oldcookiec so 3975 * the scatter-gather list is correctly allocated 3976 */ 3977 3978 if (oldcookiec != cmd->cmd_cookiec) { 3979 if (cmd->cmd_sg != (mptti_t *)NULL) { 3980 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3981 oldcookiec); 3982 cmd->cmd_sg = NULL; 3983 } 3984 } 3985 3986 if (cmd->cmd_sg == (mptti_t *)NULL) { 3987 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3988 cmd->cmd_cookiec), kf); 3989 3990 if (cmd->cmd_sg == (mptti_t *)NULL) { 3991 mptsas_log(mpt, CE_WARN, 3992 "unable to kmem_alloc enough memory " 3993 "for scatter/gather list"); 3994 /* 3995 * if we have an ENOMEM condition we need to behave 3996 * the same way as the rest of this routine 3997 */ 3998 3999 bioerror(bp, ENOMEM); 4000 if (new_cmd) { 4001 mptsas_scsi_destroy_pkt(ap, pkt); 4002 } 4003 return ((struct scsi_pkt *)NULL); 4004 } 4005 } 4006 4007 dmap = cmd->cmd_sg; 4008 4009 ASSERT(cmd->cmd_cookie.dmac_size != 0); 4010 4011 /* 4012 * store the first segment into the S/G list 4013 */ 4014 dmap->count = cmd->cmd_cookie.dmac_size; 4015 dmap->addr.address64.Low = (uint32_t) 4016 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 4017 dmap->addr.address64.High = (uint32_t) 4018 (cmd->cmd_cookie.dmac_laddress >> 32); 4019 4020 /* 4021 * dmacount counts the size of the dma for this window 4022 * (if partial dma is being used). totaldmacount 4023 * keeps track of the total amount of dma we have 4024 * transferred for all the windows (needed to calculate 4025 * the resid value below). 4026 */ 4027 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 4028 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 4029 4030 /* 4031 * We already stored the first DMA scatter gather segment, 4032 * start at 1 if we need to store more. 4033 */ 4034 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 4035 /* 4036 * Get next DMA cookie 4037 */ 4038 ddi_dma_nextcookie(cmd->cmd_dmahandle, 4039 &cmd->cmd_cookie); 4040 dmap++; 4041 4042 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 4043 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 4044 4045 /* 4046 * store the segment parms into the S/G list 4047 */ 4048 dmap->count = cmd->cmd_cookie.dmac_size; 4049 dmap->addr.address64.Low = (uint32_t) 4050 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 4051 dmap->addr.address64.High = (uint32_t) 4052 (cmd->cmd_cookie.dmac_laddress >> 32); 4053 } 4054 4055 /* 4056 * If this was partially allocated we set the resid 4057 * the amount of data NOT transferred in this window 4058 * If there is only one window, the resid will be 0 4059 */ 4060 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 4061 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.", 4062 cmd->cmd_dmacount)); 4063 } 4064 return (pkt); 4065 } 4066 4067 /* 4068 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 4069 * 4070 * Notes: 4071 * - also frees DMA resources if allocated 4072 * - implicit DMA synchonization 4073 */ 4074 static void 4075 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4076 { 4077 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4078 mptsas_t *mpt = ADDR2MPT(ap); 4079 4080 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 4081 ap->a_target, (void *)pkt)); 4082 4083 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4084 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4085 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4086 } 4087 4088 if (cmd->cmd_sg) { 4089 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 4090 cmd->cmd_sg = NULL; 4091 } 4092 4093 mptsas_free_extra_sgl_frame(mpt, cmd); 4094 4095 if ((cmd->cmd_flags & 4096 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 4097 CFLAG_SCBEXTERN)) == 0) { 4098 cmd->cmd_flags = CFLAG_FREE; 4099 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4100 } else { 4101 boolean_t extrqslen = cmd->cmd_extrqslen != 0; 4102 4103 mptsas_pkt_destroy_extern(mpt, cmd); 4104 4105 /* 4106 * If the packet had the sense data buffer for DMA allocated we 4107 * need to decrease the reference counter. 4108 */ 4109 if (extrqslen) { 4110 mutex_enter(&mpt->m_mutex); 4111 ASSERT(mpt->m_extreq_sense_refcount > 0); 4112 mpt->m_extreq_sense_refcount--; 4113 if (mpt->m_extreq_sense_refcount == 0) 4114 cv_broadcast(&mpt->m_extreq_sense_refcount_cv); 4115 mutex_exit(&mpt->m_mutex); 4116 } 4117 } 4118 } 4119 4120 /* 4121 * kmem cache constructor and destructor: 4122 * When constructing, we bzero the cmd and allocate the dma handle 4123 * When destructing, just free the dma handle 4124 */ 4125 static int 4126 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 4127 { 4128 mptsas_cmd_t *cmd = buf; 4129 mptsas_t *mpt = cdrarg; 4130 int (*callback)(caddr_t); 4131 4132 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4133 4134 NDBG4(("mptsas_kmem_cache_constructor")); 4135 4136 /* 4137 * allocate a dma handle 4138 */ 4139 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 4140 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 4141 cmd->cmd_dmahandle = NULL; 4142 return (-1); 4143 } 4144 return (0); 4145 } 4146 4147 static void 4148 mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 4149 { 4150 #ifndef __lock_lint 4151 _NOTE(ARGUNUSED(cdrarg)) 4152 #endif 4153 mptsas_cmd_t *cmd = buf; 4154 4155 NDBG4(("mptsas_kmem_cache_destructor")); 4156 4157 if (cmd->cmd_dmahandle) { 4158 ddi_dma_free_handle(&cmd->cmd_dmahandle); 4159 cmd->cmd_dmahandle = NULL; 4160 } 4161 } 4162 4163 static int 4164 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 4165 { 4166 mptsas_cache_frames_t *p = buf; 4167 mptsas_t *mpt = cdrarg; 4168 ddi_dma_attr_t frame_dma_attr; 4169 size_t mem_size, alloc_len; 4170 ddi_dma_cookie_t cookie; 4171 uint_t ncookie; 4172 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 4173 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4174 4175 frame_dma_attr = mpt->m_msg_dma_attr; 4176 frame_dma_attr.dma_attr_align = 0x10; 4177 frame_dma_attr.dma_attr_sgllen = 1; 4178 4179 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 4180 &p->m_dma_hdl) != DDI_SUCCESS) { 4181 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 4182 " extra SGL."); 4183 return (DDI_FAILURE); 4184 } 4185 4186 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 4187 4188 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 4189 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 4190 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 4191 ddi_dma_free_handle(&p->m_dma_hdl); 4192 p->m_dma_hdl = NULL; 4193 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 4194 " extra SGL."); 4195 return (DDI_FAILURE); 4196 } 4197 4198 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 4199 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 4200 &cookie, &ncookie) != DDI_DMA_MAPPED) { 4201 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4202 ddi_dma_free_handle(&p->m_dma_hdl); 4203 p->m_dma_hdl = NULL; 4204 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 4205 " extra SGL"); 4206 return (DDI_FAILURE); 4207 } 4208 4209 /* 4210 * Store the SGL memory address. This chip uses this 4211 * address to dma to and from the driver. The second 4212 * address is the address mpt uses to fill in the SGL. 4213 */ 4214 p->m_phys_addr = cookie.dmac_laddress; 4215 4216 return (DDI_SUCCESS); 4217 } 4218 4219 static void 4220 mptsas_cache_frames_destructor(void *buf, void *cdrarg) 4221 { 4222 #ifndef __lock_lint 4223 _NOTE(ARGUNUSED(cdrarg)) 4224 #endif 4225 mptsas_cache_frames_t *p = buf; 4226 if (p->m_dma_hdl != NULL) { 4227 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 4228 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4229 ddi_dma_free_handle(&p->m_dma_hdl); 4230 p->m_phys_addr = 0; 4231 p->m_frames_addr = NULL; 4232 p->m_dma_hdl = NULL; 4233 p->m_acc_hdl = NULL; 4234 } 4235 4236 } 4237 4238 /* 4239 * Figure out if we need to use a different method for the request 4240 * sense buffer and allocate from the map if necessary. 4241 */ 4242 static boolean_t 4243 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf) 4244 { 4245 if (senselength > mpt->m_req_sense_size) { 4246 unsigned long i; 4247 4248 /* Sense length is limited to an 8 bit value in MPI Spec. */ 4249 if (senselength > 255) 4250 senselength = 255; 4251 cmd->cmd_extrqschunks = (senselength + 4252 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size; 4253 i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc) 4254 (mpt->m_erqsense_map, cmd->cmd_extrqschunks); 4255 4256 if (i == 0) 4257 return (B_FALSE); 4258 4259 cmd->cmd_extrqslen = (uint16_t)senselength; 4260 cmd->cmd_extrqsidx = i - 1; 4261 cmd->cmd_arq_buf = mpt->m_extreq_sense + 4262 (cmd->cmd_extrqsidx * mpt->m_req_sense_size); 4263 } else { 4264 cmd->cmd_rqslen = (uchar_t)senselength; 4265 } 4266 4267 return (B_TRUE); 4268 } 4269 4270 /* 4271 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 4272 * for non-standard length cdb, pkt_private, status areas 4273 * if allocation fails, then deallocate all external space and the pkt 4274 */ 4275 /* ARGSUSED */ 4276 static int 4277 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 4278 int cmdlen, int tgtlen, int statuslen, int kf) 4279 { 4280 caddr_t cdbp, scbp, tgt; 4281 4282 NDBG3(("mptsas_pkt_alloc_extern: " 4283 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 4284 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 4285 4286 tgt = cdbp = scbp = NULL; 4287 cmd->cmd_scblen = statuslen; 4288 cmd->cmd_privlen = (uchar_t)tgtlen; 4289 4290 if (cmdlen > sizeof (cmd->cmd_cdb)) { 4291 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 4292 goto fail; 4293 } 4294 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 4295 cmd->cmd_flags |= CFLAG_CDBEXTERN; 4296 } 4297 if (tgtlen > PKT_PRIV_LEN) { 4298 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 4299 goto fail; 4300 } 4301 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 4302 cmd->cmd_pkt->pkt_private = tgt; 4303 } 4304 if (statuslen > EXTCMDS_STATUS_SIZE) { 4305 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 4306 goto fail; 4307 } 4308 cmd->cmd_flags |= CFLAG_SCBEXTERN; 4309 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 4310 4311 /* allocate sense data buf for DMA */ 4312 if (mptsas_cmdarqsize(mpt, cmd, statuslen - 4313 MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata), 4314 kf) == B_FALSE) 4315 goto fail; 4316 } 4317 return (0); 4318 fail: 4319 mptsas_pkt_destroy_extern(mpt, cmd); 4320 return (1); 4321 } 4322 4323 /* 4324 * deallocate external pkt space and deallocate the pkt 4325 */ 4326 static void 4327 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 4328 { 4329 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 4330 4331 if (cmd->cmd_flags & CFLAG_FREE) { 4332 mptsas_log(mpt, CE_PANIC, 4333 "mptsas_pkt_destroy_extern: freeing free packet"); 4334 _NOTE(NOT_REACHED) 4335 /* NOTREACHED */ 4336 } 4337 if (cmd->cmd_extrqslen != 0) { 4338 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 4339 cmd->cmd_extrqsidx + 1); 4340 } 4341 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 4342 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 4343 } 4344 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 4345 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4346 } 4347 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4348 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4349 } 4350 cmd->cmd_flags = CFLAG_FREE; 4351 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4352 } 4353 4354 /* 4355 * tran_sync_pkt(9E) - explicit DMA synchronization 4356 */ 4357 /*ARGSUSED*/ 4358 static void 4359 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4360 { 4361 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4362 4363 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4364 ap->a_target, (void *)pkt)); 4365 4366 if (cmd->cmd_dmahandle) { 4367 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4368 (cmd->cmd_flags & CFLAG_DMASEND) ? 4369 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4370 } 4371 } 4372 4373 /* 4374 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4375 */ 4376 /*ARGSUSED*/ 4377 static void 4378 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4379 { 4380 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4381 mptsas_t *mpt = ADDR2MPT(ap); 4382 4383 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4384 ap->a_target, (void *)pkt)); 4385 4386 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4387 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4388 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4389 } 4390 4391 mptsas_free_extra_sgl_frame(mpt, cmd); 4392 } 4393 4394 static void 4395 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4396 { 4397 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4398 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4399 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4400 DDI_DMA_SYNC_FORCPU); 4401 } 4402 (*pkt->pkt_comp)(pkt); 4403 } 4404 4405 static void 4406 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4407 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags) 4408 { 4409 pMpi2SGESimple64_t sge; 4410 mptti_t *dmap; 4411 uint32_t flags; 4412 4413 dmap = cmd->cmd_sg; 4414 4415 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4416 while (cookiec--) { 4417 ddi_put32(acc_hdl, 4418 &sge->Address.Low, dmap->addr.address64.Low); 4419 ddi_put32(acc_hdl, 4420 &sge->Address.High, dmap->addr.address64.High); 4421 ddi_put32(acc_hdl, &sge->FlagsLength, 4422 dmap->count); 4423 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4424 flags |= ((uint32_t) 4425 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4426 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4427 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4428 MPI2_SGE_FLAGS_SHIFT); 4429 4430 /* 4431 * If this is the last cookie, we set the flags 4432 * to indicate so 4433 */ 4434 if (cookiec == 0) { 4435 flags |= end_flags; 4436 } 4437 if (cmd->cmd_flags & CFLAG_DMASEND) { 4438 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4439 MPI2_SGE_FLAGS_SHIFT); 4440 } else { 4441 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4442 MPI2_SGE_FLAGS_SHIFT); 4443 } 4444 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4445 dmap++; 4446 sge++; 4447 } 4448 } 4449 4450 static void 4451 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4452 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4453 { 4454 pMpi2SGESimple64_t sge; 4455 pMpi2SGEChain64_t sgechain; 4456 uint64_t nframe_phys_addr; 4457 uint_t cookiec; 4458 mptti_t *dmap; 4459 uint32_t flags; 4460 4461 /* 4462 * Save the number of entries in the DMA 4463 * Scatter/Gather list 4464 */ 4465 cookiec = cmd->cmd_cookiec; 4466 4467 /* 4468 * Hereby we start to deal with multiple frames. 4469 * The process is as follows: 4470 * 1. Determine how many frames are needed for SGL element 4471 * storage; Note that all frames are stored in contiguous 4472 * memory space and in 64-bit DMA mode each element is 4473 * 3 double-words (12 bytes) long. 4474 * 2. Fill up the main frame. We need to do this separately 4475 * since it contains the SCSI IO request header and needs 4476 * dedicated processing. Note that the last 4 double-words 4477 * of the SCSI IO header is for SGL element storage 4478 * (MPI2_SGE_IO_UNION). 4479 * 3. Fill the chain element in the main frame, so the DMA 4480 * engine can use the following frames. 4481 * 4. Enter a loop to fill the remaining frames. Note that the 4482 * last frame contains no chain element. The remaining 4483 * frames go into the mpt SGL buffer allocated on the fly, 4484 * not immediately following the main message frame, as in 4485 * Gen1. 4486 * Some restrictions: 4487 * 1. For 64-bit DMA, the simple element and chain element 4488 * are both of 3 double-words (12 bytes) in size, even 4489 * though all frames are stored in the first 4G of mem 4490 * range and the higher 32-bits of the address are always 0. 4491 * 2. On some controllers (like the 1064/1068), a frame can 4492 * hold SGL elements with the last 1 or 2 double-words 4493 * (4 or 8 bytes) un-used. On these controllers, we should 4494 * recognize that there's not enough room for another SGL 4495 * element and move the sge pointer to the next frame. 4496 */ 4497 int i, j, k, l, frames, sgemax; 4498 int temp; 4499 uint8_t chainflags; 4500 uint16_t chainlength; 4501 mptsas_cache_frames_t *p; 4502 4503 /* 4504 * Sgemax is the number of SGE's that will fit 4505 * each extra frame and frames is total 4506 * number of frames we'll need. 1 sge entry per 4507 * frame is reseverd for the chain element thus the -1 below. 4508 */ 4509 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4510 - 1); 4511 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4512 4513 /* 4514 * A little check to see if we need to round up the number 4515 * of frames we need 4516 */ 4517 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4518 sgemax) > 1) { 4519 frames = (temp + 1); 4520 } else { 4521 frames = temp; 4522 } 4523 dmap = cmd->cmd_sg; 4524 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4525 4526 /* 4527 * First fill in the main frame 4528 */ 4529 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4530 mptsas_sge_mainframe(cmd, frame, acc_hdl, j, 4531 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) << 4532 MPI2_SGE_FLAGS_SHIFT)); 4533 dmap += j; 4534 sge += j; 4535 j++; 4536 4537 /* 4538 * Fill in the chain element in the main frame. 4539 * About calculation on ChainOffset: 4540 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4541 * in the end reserved for SGL element storage 4542 * (MPI2_SGE_IO_UNION); we should count it in our 4543 * calculation. See its definition in the header file. 4544 * 2. Constant j is the counter of the current SGL element 4545 * that will be processed, and (j - 1) is the number of 4546 * SGL elements that have been processed (stored in the 4547 * main frame). 4548 * 3. ChainOffset value should be in units of double-words (4 4549 * bytes) so the last value should be divided by 4. 4550 */ 4551 ddi_put8(acc_hdl, &frame->ChainOffset, 4552 (sizeof (MPI2_SCSI_IO_REQUEST) - 4553 sizeof (MPI2_SGE_IO_UNION) + 4554 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4555 sgechain = (pMpi2SGEChain64_t)sge; 4556 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4557 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4558 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4559 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4560 4561 /* 4562 * The size of the next frame is the accurate size of space 4563 * (in bytes) used to store the SGL elements. j is the counter 4564 * of SGL elements. (j - 1) is the number of SGL elements that 4565 * have been processed (stored in frames). 4566 */ 4567 if (frames >= 2) { 4568 ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64)); 4569 chainlength = mpt->m_req_frame_size / 4570 sizeof (MPI2_SGE_SIMPLE64) * 4571 sizeof (MPI2_SGE_SIMPLE64); 4572 } else { 4573 chainlength = ((cookiec - (j - 1)) * 4574 sizeof (MPI2_SGE_SIMPLE64)); 4575 } 4576 4577 p = cmd->cmd_extra_frames; 4578 4579 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4580 ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr); 4581 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32); 4582 4583 /* 4584 * If there are more than 2 frames left we have to 4585 * fill in the next chain offset to the location of 4586 * the chain element in the next frame. 4587 * sgemax is the number of simple elements in an extra 4588 * frame. Note that the value NextChainOffset should be 4589 * in double-words (4 bytes). 4590 */ 4591 if (frames >= 2) { 4592 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4593 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4594 } else { 4595 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4596 } 4597 4598 /* 4599 * Jump to next frame; 4600 * Starting here, chain buffers go into the per command SGL. 4601 * This buffer is allocated when chain buffers are needed. 4602 */ 4603 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4604 i = cookiec; 4605 4606 /* 4607 * Start filling in frames with SGE's. If we 4608 * reach the end of frame and still have SGE's 4609 * to fill we need to add a chain element and 4610 * use another frame. j will be our counter 4611 * for what cookie we are at and i will be 4612 * the total cookiec. k is the current frame 4613 */ 4614 for (k = 1; k <= frames; k++) { 4615 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4616 4617 /* 4618 * If we have reached the end of frame 4619 * and we have more SGE's to fill in 4620 * we have to fill the final entry 4621 * with a chain element and then 4622 * continue to the next frame 4623 */ 4624 if ((l == (sgemax + 1)) && (k != frames)) { 4625 sgechain = (pMpi2SGEChain64_t)sge; 4626 j--; 4627 chainflags = ( 4628 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4629 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4630 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4631 ddi_put8(p->m_acc_hdl, 4632 &sgechain->Flags, chainflags); 4633 /* 4634 * k is the frame counter and (k + 1) 4635 * is the number of the next frame. 4636 * Note that frames are in contiguous 4637 * memory space. 4638 */ 4639 nframe_phys_addr = p->m_phys_addr + 4640 (mpt->m_req_frame_size * k); 4641 ddi_put32(p->m_acc_hdl, 4642 &sgechain->Address.Low, 4643 nframe_phys_addr); 4644 ddi_put32(p->m_acc_hdl, 4645 &sgechain->Address.High, 4646 nframe_phys_addr >> 32); 4647 4648 /* 4649 * If there are more than 2 frames left 4650 * we have to next chain offset to 4651 * the location of the chain element 4652 * in the next frame and fill in the 4653 * length of the next chain 4654 */ 4655 if ((frames - k) >= 2) { 4656 ddi_put8(p->m_acc_hdl, 4657 &sgechain->NextChainOffset, 4658 (sgemax * 4659 sizeof (MPI2_SGE_SIMPLE64)) 4660 >> 2); 4661 ddi_put16(p->m_acc_hdl, 4662 &sgechain->Length, 4663 mpt->m_req_frame_size / 4664 sizeof (MPI2_SGE_SIMPLE64) * 4665 sizeof (MPI2_SGE_SIMPLE64)); 4666 } else { 4667 /* 4668 * This is the last frame. Set 4669 * the NextChainOffset to 0 and 4670 * Length is the total size of 4671 * all remaining simple elements 4672 */ 4673 ddi_put8(p->m_acc_hdl, 4674 &sgechain->NextChainOffset, 4675 0); 4676 ddi_put16(p->m_acc_hdl, 4677 &sgechain->Length, 4678 (cookiec - j) * 4679 sizeof (MPI2_SGE_SIMPLE64)); 4680 } 4681 4682 /* Jump to the next frame */ 4683 sge = (pMpi2SGESimple64_t) 4684 ((char *)p->m_frames_addr + 4685 (int)mpt->m_req_frame_size * k); 4686 4687 continue; 4688 } 4689 4690 ddi_put32(p->m_acc_hdl, 4691 &sge->Address.Low, 4692 dmap->addr.address64.Low); 4693 ddi_put32(p->m_acc_hdl, 4694 &sge->Address.High, 4695 dmap->addr.address64.High); 4696 ddi_put32(p->m_acc_hdl, 4697 &sge->FlagsLength, dmap->count); 4698 flags = ddi_get32(p->m_acc_hdl, 4699 &sge->FlagsLength); 4700 flags |= ((uint32_t)( 4701 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4702 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4703 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4704 MPI2_SGE_FLAGS_SHIFT); 4705 4706 /* 4707 * If we are at the end of the frame and 4708 * there is another frame to fill in 4709 * we set the last simple element as last 4710 * element 4711 */ 4712 if ((l == sgemax) && (k != frames)) { 4713 flags |= ((uint32_t) 4714 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4715 MPI2_SGE_FLAGS_SHIFT); 4716 } 4717 4718 /* 4719 * If this is the final cookie we 4720 * indicate it by setting the flags 4721 */ 4722 if (j == i) { 4723 flags |= ((uint32_t) 4724 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4725 MPI2_SGE_FLAGS_END_OF_BUFFER | 4726 MPI2_SGE_FLAGS_END_OF_LIST) << 4727 MPI2_SGE_FLAGS_SHIFT); 4728 } 4729 if (cmd->cmd_flags & CFLAG_DMASEND) { 4730 flags |= 4731 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4732 MPI2_SGE_FLAGS_SHIFT); 4733 } else { 4734 flags |= 4735 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4736 MPI2_SGE_FLAGS_SHIFT); 4737 } 4738 ddi_put32(p->m_acc_hdl, 4739 &sge->FlagsLength, flags); 4740 dmap++; 4741 sge++; 4742 } 4743 } 4744 4745 /* 4746 * Sync DMA with the chain buffers that were just created 4747 */ 4748 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4749 } 4750 4751 static void 4752 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4753 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag) 4754 { 4755 pMpi2IeeeSgeSimple64_t ieeesge; 4756 mptti_t *dmap; 4757 uint8_t flags; 4758 4759 dmap = cmd->cmd_sg; 4760 4761 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec, 4762 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In")); 4763 4764 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4765 while (cookiec--) { 4766 ddi_put32(acc_hdl, 4767 &ieeesge->Address.Low, dmap->addr.address64.Low); 4768 ddi_put32(acc_hdl, 4769 &ieeesge->Address.High, dmap->addr.address64.High); 4770 ddi_put32(acc_hdl, &ieeesge->Length, 4771 dmap->count); 4772 NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count)); 4773 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 4774 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4775 4776 /* 4777 * If this is the last cookie, we set the flags 4778 * to indicate so 4779 */ 4780 if (cookiec == 0) { 4781 flags |= end_flag; 4782 } 4783 4784 ddi_put8(acc_hdl, &ieeesge->Flags, flags); 4785 dmap++; 4786 ieeesge++; 4787 } 4788 } 4789 4790 static void 4791 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4792 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4793 { 4794 pMpi2IeeeSgeSimple64_t ieeesge; 4795 pMpi25IeeeSgeChain64_t ieeesgechain; 4796 uint64_t nframe_phys_addr; 4797 uint_t cookiec; 4798 mptti_t *dmap; 4799 uint8_t flags; 4800 4801 /* 4802 * Save the number of entries in the DMA 4803 * Scatter/Gather list 4804 */ 4805 cookiec = cmd->cmd_cookiec; 4806 4807 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec)); 4808 4809 /* 4810 * Hereby we start to deal with multiple frames. 4811 * The process is as follows: 4812 * 1. Determine how many frames are needed for SGL element 4813 * storage; Note that all frames are stored in contiguous 4814 * memory space and in 64-bit DMA mode each element is 4815 * 4 double-words (16 bytes) long. 4816 * 2. Fill up the main frame. We need to do this separately 4817 * since it contains the SCSI IO request header and needs 4818 * dedicated processing. Note that the last 4 double-words 4819 * of the SCSI IO header is for SGL element storage 4820 * (MPI2_SGE_IO_UNION). 4821 * 3. Fill the chain element in the main frame, so the DMA 4822 * engine can use the following frames. 4823 * 4. Enter a loop to fill the remaining frames. Note that the 4824 * last frame contains no chain element. The remaining 4825 * frames go into the mpt SGL buffer allocated on the fly, 4826 * not immediately following the main message frame, as in 4827 * Gen1. 4828 * Restrictions: 4829 * For 64-bit DMA, the simple element and chain element 4830 * are both of 4 double-words (16 bytes) in size, even 4831 * though all frames are stored in the first 4G of mem 4832 * range and the higher 32-bits of the address are always 0. 4833 */ 4834 int i, j, k, l, frames, sgemax; 4835 int temp; 4836 uint8_t chainflags; 4837 uint32_t chainlength; 4838 mptsas_cache_frames_t *p; 4839 4840 /* 4841 * Sgemax is the number of SGE's that will fit 4842 * each extra frame and frames is total 4843 * number of frames we'll need. 1 sge entry per 4844 * frame is reseverd for the chain element thus the -1 below. 4845 */ 4846 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4847 - 1); 4848 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4849 4850 /* 4851 * A little check to see if we need to round up the number 4852 * of frames we need 4853 */ 4854 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4855 sgemax) > 1) { 4856 frames = (temp + 1); 4857 } else { 4858 frames = temp; 4859 } 4860 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames)); 4861 dmap = cmd->cmd_sg; 4862 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4863 4864 /* 4865 * First fill in the main frame 4866 */ 4867 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4868 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0); 4869 dmap += j; 4870 ieeesge += j; 4871 j++; 4872 4873 /* 4874 * Fill in the chain element in the main frame. 4875 * About calculation on ChainOffset: 4876 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4877 * in the end reserved for SGL element storage 4878 * (MPI2_SGE_IO_UNION); we should count it in our 4879 * calculation. See its definition in the header file. 4880 * 2. Constant j is the counter of the current SGL element 4881 * that will be processed, and (j - 1) is the number of 4882 * SGL elements that have been processed (stored in the 4883 * main frame). 4884 * 3. ChainOffset value should be in units of quad-words (16 4885 * bytes) so the last value should be divided by 16. 4886 */ 4887 ddi_put8(acc_hdl, &frame->ChainOffset, 4888 (sizeof (MPI2_SCSI_IO_REQUEST) - 4889 sizeof (MPI2_SGE_IO_UNION) + 4890 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4891 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4892 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4893 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4894 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags); 4895 4896 /* 4897 * The size of the next frame is the accurate size of space 4898 * (in bytes) used to store the SGL elements. j is the counter 4899 * of SGL elements. (j - 1) is the number of SGL elements that 4900 * have been processed (stored in frames). 4901 */ 4902 if (frames >= 2) { 4903 ASSERT(mpt->m_req_frame_size >= 4904 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4905 chainlength = mpt->m_req_frame_size / 4906 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 4907 sizeof (MPI2_IEEE_SGE_SIMPLE64); 4908 } else { 4909 chainlength = ((cookiec - (j - 1)) * 4910 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4911 } 4912 4913 p = cmd->cmd_extra_frames; 4914 4915 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength); 4916 ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr); 4917 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32); 4918 4919 /* 4920 * If there are more than 2 frames left we have to 4921 * fill in the next chain offset to the location of 4922 * the chain element in the next frame. 4923 * sgemax is the number of simple elements in an extra 4924 * frame. Note that the value NextChainOffset should be 4925 * in double-words (4 bytes). 4926 */ 4927 if (frames >= 2) { 4928 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 4929 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4930 } else { 4931 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0); 4932 } 4933 4934 /* 4935 * Jump to next frame; 4936 * Starting here, chain buffers go into the per command SGL. 4937 * This buffer is allocated when chain buffers are needed. 4938 */ 4939 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr; 4940 i = cookiec; 4941 4942 /* 4943 * Start filling in frames with SGE's. If we 4944 * reach the end of frame and still have SGE's 4945 * to fill we need to add a chain element and 4946 * use another frame. j will be our counter 4947 * for what cookie we are at and i will be 4948 * the total cookiec. k is the current frame 4949 */ 4950 for (k = 1; k <= frames; k++) { 4951 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4952 4953 /* 4954 * If we have reached the end of frame 4955 * and we have more SGE's to fill in 4956 * we have to fill the final entry 4957 * with a chain element and then 4958 * continue to the next frame 4959 */ 4960 if ((l == (sgemax + 1)) && (k != frames)) { 4961 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4962 j--; 4963 chainflags = 4964 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4965 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 4966 ddi_put8(p->m_acc_hdl, 4967 &ieeesgechain->Flags, chainflags); 4968 /* 4969 * k is the frame counter and (k + 1) 4970 * is the number of the next frame. 4971 * Note that frames are in contiguous 4972 * memory space. 4973 */ 4974 nframe_phys_addr = p->m_phys_addr + 4975 (mpt->m_req_frame_size * k); 4976 ddi_put32(p->m_acc_hdl, 4977 &ieeesgechain->Address.Low, 4978 nframe_phys_addr); 4979 ddi_put32(p->m_acc_hdl, 4980 &ieeesgechain->Address.High, 4981 nframe_phys_addr >> 32); 4982 4983 /* 4984 * If there are more than 2 frames left 4985 * we have to next chain offset to 4986 * the location of the chain element 4987 * in the next frame and fill in the 4988 * length of the next chain 4989 */ 4990 if ((frames - k) >= 2) { 4991 ddi_put8(p->m_acc_hdl, 4992 &ieeesgechain->NextChainOffset, 4993 (sgemax * 4994 sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4995 >> 4); 4996 ASSERT(mpt->m_req_frame_size >= 4997 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4998 ddi_put32(p->m_acc_hdl, 4999 &ieeesgechain->Length, 5000 mpt->m_req_frame_size / 5001 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 5002 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 5003 } else { 5004 /* 5005 * This is the last frame. Set 5006 * the NextChainOffset to 0 and 5007 * Length is the total size of 5008 * all remaining simple elements 5009 */ 5010 ddi_put8(p->m_acc_hdl, 5011 &ieeesgechain->NextChainOffset, 5012 0); 5013 ddi_put32(p->m_acc_hdl, 5014 &ieeesgechain->Length, 5015 (cookiec - j) * 5016 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 5017 } 5018 5019 /* Jump to the next frame */ 5020 ieeesge = (pMpi2IeeeSgeSimple64_t) 5021 ((char *)p->m_frames_addr + 5022 (int)mpt->m_req_frame_size * k); 5023 5024 continue; 5025 } 5026 5027 ddi_put32(p->m_acc_hdl, 5028 &ieeesge->Address.Low, 5029 dmap->addr.address64.Low); 5030 ddi_put32(p->m_acc_hdl, 5031 &ieeesge->Address.High, 5032 dmap->addr.address64.High); 5033 ddi_put32(p->m_acc_hdl, 5034 &ieeesge->Length, dmap->count); 5035 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 5036 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 5037 5038 /* 5039 * If we are at the end of the frame and 5040 * there is another frame to fill in 5041 * do we need to do anything? 5042 * if ((l == sgemax) && (k != frames)) { 5043 * } 5044 */ 5045 5046 /* 5047 * If this is the final cookie set end of list. 5048 */ 5049 if (j == i) { 5050 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 5051 } 5052 5053 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags); 5054 dmap++; 5055 ieeesge++; 5056 } 5057 } 5058 5059 /* 5060 * Sync DMA with the chain buffers that were just created 5061 */ 5062 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 5063 } 5064 5065 static void 5066 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 5067 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 5068 { 5069 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 5070 5071 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec)); 5072 5073 /* 5074 * Set read/write bit in control. 5075 */ 5076 if (cmd->cmd_flags & CFLAG_DMASEND) { 5077 *control |= MPI2_SCSIIO_CONTROL_WRITE; 5078 } else { 5079 *control |= MPI2_SCSIIO_CONTROL_READ; 5080 } 5081 5082 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 5083 5084 /* 5085 * We have 4 cases here. First where we can fit all the 5086 * SG elements into the main frame, and the case 5087 * where we can't. The SG element is also different when using 5088 * MPI2.5 interface. 5089 * If we have more cookies than we can attach to a frame 5090 * we will need to use a chain element to point 5091 * a location of memory where the rest of the S/G 5092 * elements reside. 5093 */ 5094 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 5095 if (mpt->m_MPI25) { 5096 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, 5097 cmd->cmd_cookiec, 5098 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 5099 } else { 5100 mptsas_sge_mainframe(cmd, frame, acc_hdl, 5101 cmd->cmd_cookiec, 5102 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 5103 | MPI2_SGE_FLAGS_END_OF_BUFFER 5104 | MPI2_SGE_FLAGS_END_OF_LIST) << 5105 MPI2_SGE_FLAGS_SHIFT)); 5106 } 5107 } else { 5108 if (mpt->m_MPI25) { 5109 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl); 5110 } else { 5111 mptsas_sge_chain(mpt, cmd, frame, acc_hdl); 5112 } 5113 } 5114 } 5115 5116 /* 5117 * Interrupt handling 5118 * Utility routine. Poll for status of a command sent to HBA 5119 * without interrupts (a FLAG_NOINTR command). 5120 */ 5121 int 5122 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 5123 { 5124 int rval = TRUE; 5125 5126 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 5127 5128 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 5129 mptsas_restart_hba(mpt); 5130 } 5131 5132 /* 5133 * Wait, using drv_usecwait(), long enough for the command to 5134 * reasonably return from the target if the target isn't 5135 * "dead". A polled command may well be sent from scsi_poll, and 5136 * there are retries built in to scsi_poll if the transport 5137 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 5138 * and retries the transport up to scsi_poll_busycnt times 5139 * (currently 60) if 5140 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 5141 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 5142 * 5143 * limit the waiting to avoid a hang in the event that the 5144 * cmd never gets started but we are still receiving interrupts 5145 */ 5146 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 5147 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 5148 NDBG5(("mptsas_poll: command incomplete")); 5149 rval = FALSE; 5150 break; 5151 } 5152 } 5153 5154 if (rval == FALSE) { 5155 5156 /* 5157 * this isn't supposed to happen, the hba must be wedged 5158 * Mark this cmd as a timeout. 5159 */ 5160 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 5161 (STAT_TIMEOUT|STAT_ABORTED)); 5162 5163 if (poll_cmd->cmd_queued == FALSE) { 5164 5165 NDBG5(("mptsas_poll: not on waitq")); 5166 5167 poll_cmd->cmd_pkt->pkt_state |= 5168 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 5169 } else { 5170 5171 /* find and remove it from the waitq */ 5172 NDBG5(("mptsas_poll: delete from waitq")); 5173 mptsas_waitq_delete(mpt, poll_cmd); 5174 } 5175 5176 } 5177 mptsas_fma_check(mpt, poll_cmd); 5178 NDBG5(("mptsas_poll: done")); 5179 return (rval); 5180 } 5181 5182 /* 5183 * Used for polling cmds and TM function 5184 */ 5185 static int 5186 mptsas_wait_intr(mptsas_t *mpt, int polltime) 5187 { 5188 int cnt; 5189 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5190 uint32_t int_mask; 5191 5192 NDBG5(("mptsas_wait_intr")); 5193 5194 mpt->m_polled_intr = 1; 5195 5196 /* 5197 * Get the current interrupt mask and disable interrupts. When 5198 * re-enabling ints, set mask to saved value. 5199 */ 5200 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 5201 MPTSAS_DISABLE_INTR(mpt); 5202 5203 /* 5204 * Keep polling for at least (polltime * 1000) seconds 5205 */ 5206 for (cnt = 0; cnt < polltime; cnt++) { 5207 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5208 DDI_DMA_SYNC_FORCPU); 5209 5210 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5211 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5212 5213 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5214 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5215 ddi_get32(mpt->m_acc_post_queue_hdl, 5216 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5217 drv_usecwait(1000); 5218 continue; 5219 } 5220 5221 /* 5222 * The reply is valid, process it according to its 5223 * type. 5224 */ 5225 mptsas_process_intr(mpt, reply_desc_union); 5226 5227 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5228 mpt->m_post_index = 0; 5229 } 5230 5231 /* 5232 * Update the global reply index 5233 */ 5234 ddi_put32(mpt->m_datap, 5235 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5236 mpt->m_polled_intr = 0; 5237 5238 /* 5239 * Re-enable interrupts and quit. 5240 */ 5241 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 5242 int_mask); 5243 return (TRUE); 5244 5245 } 5246 5247 /* 5248 * Clear polling flag, re-enable interrupts and quit. 5249 */ 5250 mpt->m_polled_intr = 0; 5251 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 5252 return (FALSE); 5253 } 5254 5255 static void 5256 mptsas_handle_scsi_io_success(mptsas_t *mpt, 5257 pMpi2ReplyDescriptorsUnion_t reply_desc) 5258 { 5259 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 5260 uint16_t SMID; 5261 mptsas_slots_t *slots = mpt->m_active; 5262 mptsas_cmd_t *cmd = NULL; 5263 struct scsi_pkt *pkt; 5264 5265 ASSERT(mutex_owned(&mpt->m_mutex)); 5266 5267 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 5268 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID); 5269 5270 /* 5271 * This is a success reply so just complete the IO. First, do a sanity 5272 * check on the SMID. The final slot is used for TM requests, which 5273 * would not come into this reply handler. 5274 */ 5275 if ((SMID == 0) || (SMID > slots->m_n_normal)) { 5276 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 5277 SMID); 5278 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5279 return; 5280 } 5281 5282 cmd = slots->m_slot[SMID]; 5283 5284 /* 5285 * print warning and return if the slot is empty 5286 */ 5287 if (cmd == NULL) { 5288 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 5289 "in slot %d", SMID); 5290 return; 5291 } 5292 5293 pkt = CMD2PKT(cmd); 5294 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 5295 STATE_GOT_STATUS); 5296 if (cmd->cmd_flags & CFLAG_DMAVALID) { 5297 pkt->pkt_state |= STATE_XFERRED_DATA; 5298 } 5299 pkt->pkt_resid = 0; 5300 5301 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 5302 cmd->cmd_flags |= CFLAG_FINISHED; 5303 cv_broadcast(&mpt->m_passthru_cv); 5304 return; 5305 } else { 5306 mptsas_remove_cmd(mpt, cmd); 5307 } 5308 5309 if (cmd->cmd_flags & CFLAG_RETRY) { 5310 /* 5311 * The target returned QFULL or busy, do not add tihs 5312 * pkt to the doneq since the hba will retry 5313 * this cmd. 5314 * 5315 * The pkt has already been resubmitted in 5316 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5317 * Remove this cmd_flag here. 5318 */ 5319 cmd->cmd_flags &= ~CFLAG_RETRY; 5320 } else { 5321 mptsas_doneq_add(mpt, cmd); 5322 } 5323 } 5324 5325 static void 5326 mptsas_handle_address_reply(mptsas_t *mpt, 5327 pMpi2ReplyDescriptorsUnion_t reply_desc) 5328 { 5329 pMpi2AddressReplyDescriptor_t address_reply; 5330 pMPI2DefaultReply_t reply; 5331 mptsas_fw_diagnostic_buffer_t *pBuffer; 5332 uint32_t reply_addr, reply_frame_dma_baseaddr; 5333 uint16_t SMID, iocstatus; 5334 mptsas_slots_t *slots = mpt->m_active; 5335 mptsas_cmd_t *cmd = NULL; 5336 uint8_t function, buffer_type; 5337 m_replyh_arg_t *args; 5338 int reply_frame_no; 5339 5340 ASSERT(mutex_owned(&mpt->m_mutex)); 5341 5342 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 5343 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl, 5344 &address_reply->ReplyFrameAddress); 5345 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID); 5346 5347 /* 5348 * If reply frame is not in the proper range we should ignore this 5349 * message and exit the interrupt handler. 5350 */ 5351 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu; 5352 if ((reply_addr < reply_frame_dma_baseaddr) || 5353 (reply_addr >= (reply_frame_dma_baseaddr + 5354 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 5355 ((reply_addr - reply_frame_dma_baseaddr) % 5356 mpt->m_reply_frame_size != 0)) { 5357 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 5358 "address 0x%x\n", reply_addr); 5359 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5360 return; 5361 } 5362 5363 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 5364 DDI_DMA_SYNC_FORCPU); 5365 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 5366 reply_frame_dma_baseaddr)); 5367 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 5368 5369 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x", 5370 function, reply_addr)); 5371 5372 /* 5373 * don't get slot information and command for events since these values 5374 * don't exist 5375 */ 5376 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 5377 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 5378 /* 5379 * This could be a TM reply, which use the last allocated SMID, 5380 * so allow for that. 5381 */ 5382 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) { 5383 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 5384 "%d\n", SMID); 5385 ddi_fm_service_impact(mpt->m_dip, 5386 DDI_SERVICE_UNAFFECTED); 5387 return; 5388 } 5389 5390 cmd = slots->m_slot[SMID]; 5391 5392 /* 5393 * print warning and return if the slot is empty 5394 */ 5395 if (cmd == NULL) { 5396 mptsas_log(mpt, CE_WARN, "?NULL command for address " 5397 "reply in slot %d", SMID); 5398 return; 5399 } 5400 if ((cmd->cmd_flags & 5401 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 5402 cmd->cmd_rfm = reply_addr; 5403 cmd->cmd_flags |= CFLAG_FINISHED; 5404 cv_broadcast(&mpt->m_passthru_cv); 5405 cv_broadcast(&mpt->m_config_cv); 5406 cv_broadcast(&mpt->m_fw_diag_cv); 5407 return; 5408 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 5409 mptsas_remove_cmd(mpt, cmd); 5410 } 5411 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 5412 } 5413 /* 5414 * Depending on the function, we need to handle 5415 * the reply frame (and cmd) differently. 5416 */ 5417 switch (function) { 5418 case MPI2_FUNCTION_SCSI_IO_REQUEST: 5419 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 5420 break; 5421 case MPI2_FUNCTION_SCSI_TASK_MGMT: 5422 cmd->cmd_rfm = reply_addr; 5423 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 5424 cmd); 5425 break; 5426 case MPI2_FUNCTION_FW_DOWNLOAD: 5427 cmd->cmd_flags |= CFLAG_FINISHED; 5428 cv_signal(&mpt->m_fw_cv); 5429 break; 5430 case MPI2_FUNCTION_EVENT_NOTIFICATION: 5431 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) / 5432 mpt->m_reply_frame_size; 5433 args = &mpt->m_replyh_args[reply_frame_no]; 5434 args->mpt = (void *)mpt; 5435 args->rfm = reply_addr; 5436 5437 /* 5438 * Record the event if its type is enabled in 5439 * this mpt instance by ioctl. 5440 */ 5441 mptsas_record_event(args); 5442 5443 /* 5444 * Handle time critical events 5445 * NOT_RESPONDING/ADDED only now 5446 */ 5447 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 5448 /* 5449 * Would not return main process, 5450 * just let taskq resolve ack action 5451 * and ack would be sent in taskq thread 5452 */ 5453 NDBG20(("send mptsas_handle_event_sync success")); 5454 } 5455 5456 if (mpt->m_in_reset) { 5457 NDBG20(("dropping event received during reset")); 5458 return; 5459 } 5460 5461 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 5462 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5463 mptsas_log(mpt, CE_WARN, "No memory available" 5464 "for dispatch taskq"); 5465 /* 5466 * Return the reply frame to the free queue. 5467 */ 5468 ddi_put32(mpt->m_acc_free_queue_hdl, 5469 &((uint32_t *)(void *) 5470 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 5471 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5472 DDI_DMA_SYNC_FORDEV); 5473 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5474 mpt->m_free_index = 0; 5475 } 5476 5477 ddi_put32(mpt->m_datap, 5478 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 5479 } 5480 return; 5481 case MPI2_FUNCTION_DIAG_BUFFER_POST: 5482 /* 5483 * If SMID is 0, this implies that the reply is due to a 5484 * release function with a status that the buffer has been 5485 * released. Set the buffer flags accordingly. 5486 */ 5487 if (SMID == 0) { 5488 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 5489 &reply->IOCStatus); 5490 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 5491 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 5492 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 5493 pBuffer = 5494 &mpt->m_fw_diag_buffer_list[buffer_type]; 5495 pBuffer->valid_data = TRUE; 5496 pBuffer->owned_by_firmware = FALSE; 5497 pBuffer->immediate = FALSE; 5498 } 5499 } else { 5500 /* 5501 * Normal handling of diag post reply with SMID. 5502 */ 5503 cmd = slots->m_slot[SMID]; 5504 5505 /* 5506 * print warning and return if the slot is empty 5507 */ 5508 if (cmd == NULL) { 5509 mptsas_log(mpt, CE_WARN, "?NULL command for " 5510 "address reply in slot %d", SMID); 5511 return; 5512 } 5513 cmd->cmd_rfm = reply_addr; 5514 cmd->cmd_flags |= CFLAG_FINISHED; 5515 cv_broadcast(&mpt->m_fw_diag_cv); 5516 } 5517 return; 5518 default: 5519 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 5520 break; 5521 } 5522 5523 /* 5524 * Return the reply frame to the free queue. 5525 */ 5526 ddi_put32(mpt->m_acc_free_queue_hdl, 5527 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 5528 reply_addr); 5529 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5530 DDI_DMA_SYNC_FORDEV); 5531 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5532 mpt->m_free_index = 0; 5533 } 5534 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 5535 mpt->m_free_index); 5536 5537 if (cmd->cmd_flags & CFLAG_FW_CMD) 5538 return; 5539 5540 if (cmd->cmd_flags & CFLAG_RETRY) { 5541 /* 5542 * The target returned QFULL or busy, do not add this 5543 * pkt to the doneq since the hba will retry 5544 * this cmd. 5545 * 5546 * The pkt has already been resubmitted in 5547 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5548 * Remove this cmd_flag here. 5549 */ 5550 cmd->cmd_flags &= ~CFLAG_RETRY; 5551 } else { 5552 mptsas_doneq_add(mpt, cmd); 5553 } 5554 } 5555 5556 #ifdef MPTSAS_DEBUG 5557 static uint8_t mptsas_last_sense[256]; 5558 #endif 5559 5560 static void 5561 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 5562 mptsas_cmd_t *cmd) 5563 { 5564 uint8_t scsi_status, scsi_state; 5565 uint16_t ioc_status, cmd_rqs_len; 5566 uint32_t xferred, sensecount, responsedata, loginfo = 0; 5567 struct scsi_pkt *pkt; 5568 struct scsi_arq_status *arqstat; 5569 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5570 uint8_t *sensedata = NULL; 5571 uint64_t sas_wwn; 5572 uint8_t phy; 5573 char wwn_str[MPTSAS_WWN_STRLEN]; 5574 5575 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 5576 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5577 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 5578 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 5579 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 5580 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 5581 &reply->ResponseInfo); 5582 5583 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 5584 sas_wwn = ptgt->m_addr.mta_wwn; 5585 phy = ptgt->m_phynum; 5586 if (sas_wwn == 0) { 5587 (void) sprintf(wwn_str, "p%x", phy); 5588 } else { 5589 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 5590 } 5591 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 5592 &reply->IOCLogInfo); 5593 mptsas_log(mpt, CE_NOTE, 5594 "?Log info 0x%x received for target %d %s.\n" 5595 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5596 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status, 5597 scsi_state); 5598 } 5599 5600 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5601 scsi_status, ioc_status, scsi_state)); 5602 5603 pkt = CMD2PKT(cmd); 5604 *(pkt->pkt_scbp) = scsi_status; 5605 5606 if (loginfo == 0x31170000) { 5607 /* 5608 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5609 * 0x31170000 comes, that means the device missing delay 5610 * is in progressing, the command need retry later. 5611 */ 5612 *(pkt->pkt_scbp) = STATUS_BUSY; 5613 return; 5614 } 5615 5616 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5617 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5618 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5619 pkt->pkt_reason = CMD_INCOMPLETE; 5620 pkt->pkt_state |= STATE_GOT_BUS; 5621 if (ptgt->m_reset_delay == 0) { 5622 mptsas_set_throttle(mpt, ptgt, 5623 DRAIN_THROTTLE); 5624 } 5625 return; 5626 } 5627 5628 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5629 responsedata &= 0x000000FF; 5630 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5631 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5632 pkt->pkt_reason = CMD_TLR_OFF; 5633 return; 5634 } 5635 } 5636 5637 5638 switch (scsi_status) { 5639 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5640 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5641 arqstat = (void*)(pkt->pkt_scbp); 5642 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5643 (pkt->pkt_scbp)); 5644 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5645 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5646 if (cmd->cmd_flags & CFLAG_XARQ) { 5647 pkt->pkt_state |= STATE_XARQ_DONE; 5648 } 5649 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5650 pkt->pkt_state |= STATE_XFERRED_DATA; 5651 } 5652 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5653 arqstat->sts_rqpkt_state = pkt->pkt_state; 5654 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5655 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5656 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5657 cmd_rqs_len = cmd->cmd_extrqslen ? 5658 cmd->cmd_extrqslen : cmd->cmd_rqslen; 5659 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 5660 DDI_DMA_SYNC_FORKERNEL); 5661 #ifdef MPTSAS_DEBUG 5662 bcopy(cmd->cmd_arq_buf, mptsas_last_sense, 5663 ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ? 5664 sizeof (mptsas_last_sense):cmd_rqs_len)); 5665 #endif 5666 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata, 5667 ((cmd_rqs_len >= sensecount) ? sensecount : 5668 cmd_rqs_len)); 5669 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount); 5670 cmd->cmd_flags |= CFLAG_CMDARQ; 5671 /* 5672 * Set proper status for pkt if autosense was valid 5673 */ 5674 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5675 struct scsi_status zero_status = { 0 }; 5676 arqstat->sts_rqpkt_status = zero_status; 5677 } 5678 5679 /* 5680 * ASC=0x47 is parity error 5681 * ASC=0x48 is initiator detected error received 5682 */ 5683 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5684 ((scsi_sense_asc(sensedata) == 0x47) || 5685 (scsi_sense_asc(sensedata) == 0x48))) { 5686 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5687 } 5688 5689 /* 5690 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5691 * ASC/ASCQ=0x25/0x00 means invalid lun 5692 */ 5693 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5694 (scsi_sense_asc(sensedata) == 0x3F) && 5695 (scsi_sense_ascq(sensedata) == 0x0E)) || 5696 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5697 (scsi_sense_asc(sensedata) == 0x25) && 5698 (scsi_sense_ascq(sensedata) == 0x00))) { 5699 mptsas_topo_change_list_t *topo_node = NULL; 5700 5701 topo_node = kmem_zalloc( 5702 sizeof (mptsas_topo_change_list_t), 5703 KM_NOSLEEP); 5704 if (topo_node == NULL) { 5705 mptsas_log(mpt, CE_NOTE, "No memory" 5706 "resource for handle SAS dynamic" 5707 "reconfigure.\n"); 5708 break; 5709 } 5710 topo_node->mpt = mpt; 5711 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5712 topo_node->un.phymask = ptgt->m_addr.mta_phymask; 5713 topo_node->devhdl = ptgt->m_devhdl; 5714 topo_node->object = (void *)ptgt; 5715 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5716 5717 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5718 mptsas_handle_dr, 5719 (void *)topo_node, 5720 DDI_NOSLEEP)) != DDI_SUCCESS) { 5721 kmem_free(topo_node, 5722 sizeof (mptsas_topo_change_list_t)); 5723 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5724 "for handle SAS dynamic reconfigure" 5725 "failed. \n"); 5726 } 5727 } 5728 break; 5729 case MPI2_SCSI_STATUS_GOOD: 5730 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5731 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5732 pkt->pkt_reason = CMD_DEV_GONE; 5733 pkt->pkt_state |= STATE_GOT_BUS; 5734 if (ptgt->m_reset_delay == 0) { 5735 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5736 } 5737 NDBG31(("lost disk for target%d, command:%x", 5738 Tgt(cmd), pkt->pkt_cdbp[0])); 5739 break; 5740 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5741 NDBG31(("data overrun: xferred=%d", xferred)); 5742 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5743 pkt->pkt_reason = CMD_DATA_OVR; 5744 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5745 | STATE_SENT_CMD | STATE_GOT_STATUS 5746 | STATE_XFERRED_DATA); 5747 pkt->pkt_resid = 0; 5748 break; 5749 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5750 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5751 NDBG31(("data underrun: xferred=%d", xferred)); 5752 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5753 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5754 | STATE_SENT_CMD | STATE_GOT_STATUS); 5755 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5756 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5757 pkt->pkt_state |= STATE_XFERRED_DATA; 5758 } 5759 break; 5760 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5761 if (cmd->cmd_active_expiration <= gethrtime()) { 5762 /* 5763 * When timeout requested, propagate 5764 * proper reason and statistics to 5765 * target drivers. 5766 */ 5767 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT, 5768 STAT_BUS_RESET | STAT_TIMEOUT); 5769 } else { 5770 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 5771 STAT_BUS_RESET); 5772 } 5773 break; 5774 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5775 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5776 mptsas_set_pkt_reason(mpt, 5777 cmd, CMD_RESET, STAT_DEV_RESET); 5778 break; 5779 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5780 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5781 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5782 mptsas_set_pkt_reason(mpt, 5783 cmd, CMD_TERMINATED, STAT_TERMINATED); 5784 break; 5785 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5786 case MPI2_IOCSTATUS_BUSY: 5787 /* 5788 * set throttles to drain 5789 */ 5790 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 5791 ptgt = refhash_next(mpt->m_targets, ptgt)) { 5792 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5793 } 5794 5795 /* 5796 * retry command 5797 */ 5798 cmd->cmd_flags |= CFLAG_RETRY; 5799 cmd->cmd_pkt_flags |= FLAG_HEAD; 5800 5801 (void) mptsas_accept_pkt(mpt, cmd); 5802 break; 5803 default: 5804 mptsas_log(mpt, CE_WARN, 5805 "unknown ioc_status = %x\n", ioc_status); 5806 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5807 "count = %x, scsi_status = %x", scsi_state, 5808 xferred, scsi_status); 5809 break; 5810 } 5811 break; 5812 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5813 mptsas_handle_qfull(mpt, cmd); 5814 break; 5815 case MPI2_SCSI_STATUS_BUSY: 5816 NDBG31(("scsi_status busy received")); 5817 break; 5818 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5819 NDBG31(("scsi_status reservation conflict received")); 5820 break; 5821 default: 5822 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5823 scsi_status, ioc_status); 5824 mptsas_log(mpt, CE_WARN, 5825 "mptsas_process_intr: invalid scsi status\n"); 5826 break; 5827 } 5828 } 5829 5830 static void 5831 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5832 mptsas_cmd_t *cmd) 5833 { 5834 uint8_t task_type; 5835 uint16_t ioc_status; 5836 uint32_t log_info; 5837 uint16_t dev_handle; 5838 struct scsi_pkt *pkt = CMD2PKT(cmd); 5839 5840 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5841 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5842 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5843 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5844 5845 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5846 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5847 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5848 task_type, ioc_status, log_info, dev_handle); 5849 pkt->pkt_reason = CMD_INCOMPLETE; 5850 return; 5851 } 5852 5853 switch (task_type) { 5854 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5855 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5856 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5857 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5858 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5859 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5860 break; 5861 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5862 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5863 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5864 /* 5865 * Check for invalid DevHandle of 0 in case application 5866 * sends bad command. DevHandle of 0 could cause problems. 5867 */ 5868 if (dev_handle == 0) { 5869 mptsas_log(mpt, CE_WARN, "!Can't flush target with" 5870 " DevHandle of 0."); 5871 } else { 5872 mptsas_flush_target(mpt, dev_handle, Lun(cmd), 5873 task_type); 5874 } 5875 break; 5876 default: 5877 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5878 task_type); 5879 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5880 break; 5881 } 5882 } 5883 5884 static void 5885 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5886 { 5887 mptsas_t *mpt = arg->mpt; 5888 uint64_t t = arg->t; 5889 mptsas_cmd_t *cmd; 5890 struct scsi_pkt *pkt; 5891 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5892 5893 mutex_enter(&item->mutex); 5894 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5895 if (!item->doneq) { 5896 cv_wait(&item->cv, &item->mutex); 5897 } 5898 pkt = NULL; 5899 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5900 cmd->cmd_flags |= CFLAG_COMPLETED; 5901 pkt = CMD2PKT(cmd); 5902 } 5903 mutex_exit(&item->mutex); 5904 if (pkt) { 5905 mptsas_pkt_comp(pkt, cmd); 5906 } 5907 mutex_enter(&item->mutex); 5908 } 5909 mutex_exit(&item->mutex); 5910 mutex_enter(&mpt->m_doneq_mutex); 5911 mpt->m_doneq_thread_n--; 5912 cv_broadcast(&mpt->m_doneq_thread_cv); 5913 mutex_exit(&mpt->m_doneq_mutex); 5914 } 5915 5916 5917 /* 5918 * mpt interrupt handler. 5919 */ 5920 static uint_t 5921 mptsas_intr(caddr_t arg1, caddr_t arg2) 5922 { 5923 mptsas_t *mpt = (void *)arg1; 5924 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5925 uchar_t did_reply = FALSE; 5926 5927 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5928 5929 mutex_enter(&mpt->m_mutex); 5930 5931 /* 5932 * If interrupts are shared by two channels then check whether this 5933 * interrupt is genuinely for this channel by making sure first the 5934 * chip is in high power state. 5935 */ 5936 if ((mpt->m_options & MPTSAS_OPT_PM) && 5937 (mpt->m_power_level != PM_LEVEL_D0)) { 5938 mutex_exit(&mpt->m_mutex); 5939 return (DDI_INTR_UNCLAIMED); 5940 } 5941 5942 /* 5943 * If polling, interrupt was triggered by some shared interrupt because 5944 * IOC interrupts are disabled during polling, so polling routine will 5945 * handle any replies. Considering this, if polling is happening, 5946 * return with interrupt unclaimed. 5947 */ 5948 if (mpt->m_polled_intr) { 5949 mutex_exit(&mpt->m_mutex); 5950 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5951 return (DDI_INTR_UNCLAIMED); 5952 } 5953 5954 /* 5955 * Read the istat register. 5956 */ 5957 if ((INTPENDING(mpt)) != 0) { 5958 /* 5959 * read fifo until empty. 5960 */ 5961 #ifndef __lock_lint 5962 _NOTE(CONSTCOND) 5963 #endif 5964 while (TRUE) { 5965 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5966 DDI_DMA_SYNC_FORCPU); 5967 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5968 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5969 5970 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5971 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5972 ddi_get32(mpt->m_acc_post_queue_hdl, 5973 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5974 break; 5975 } 5976 5977 /* 5978 * The reply is valid, process it according to its 5979 * type. Also, set a flag for updating the reply index 5980 * after they've all been processed. 5981 */ 5982 did_reply = TRUE; 5983 5984 mptsas_process_intr(mpt, reply_desc_union); 5985 5986 /* 5987 * Increment post index and roll over if needed. 5988 */ 5989 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5990 mpt->m_post_index = 0; 5991 } 5992 } 5993 5994 /* 5995 * Update the global reply index if at least one reply was 5996 * processed. 5997 */ 5998 if (did_reply) { 5999 ddi_put32(mpt->m_datap, 6000 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 6001 } 6002 } else { 6003 mutex_exit(&mpt->m_mutex); 6004 return (DDI_INTR_UNCLAIMED); 6005 } 6006 NDBG1(("mptsas_intr complete")); 6007 6008 /* 6009 * If no helper threads are created, process the doneq in ISR. If 6010 * helpers are created, use the doneq length as a metric to measure the 6011 * load on the interrupt CPU. If it is long enough, which indicates the 6012 * load is heavy, then we deliver the IO completions to the helpers. 6013 * This measurement has some limitations, although it is simple and 6014 * straightforward and works well for most of the cases at present. 6015 */ 6016 if (!mpt->m_doneq_thread_n || 6017 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) { 6018 mptsas_doneq_empty(mpt); 6019 } else { 6020 mptsas_deliver_doneq_thread(mpt); 6021 } 6022 6023 /* 6024 * If there are queued cmd, start them now. 6025 */ 6026 if (mpt->m_waitq != NULL) { 6027 mptsas_restart_waitq(mpt); 6028 } 6029 6030 mutex_exit(&mpt->m_mutex); 6031 return (DDI_INTR_CLAIMED); 6032 } 6033 6034 static void 6035 mptsas_process_intr(mptsas_t *mpt, 6036 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 6037 { 6038 uint8_t reply_type; 6039 6040 ASSERT(mutex_owned(&mpt->m_mutex)); 6041 6042 /* 6043 * The reply is valid, process it according to its 6044 * type. Also, set a flag for updated the reply index 6045 * after they've all been processed. 6046 */ 6047 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 6048 &reply_desc_union->Default.ReplyFlags); 6049 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 6050 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || 6051 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) { 6052 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 6053 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 6054 mptsas_handle_address_reply(mpt, reply_desc_union); 6055 } else { 6056 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 6057 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 6058 } 6059 6060 /* 6061 * Clear the reply descriptor for re-use and increment 6062 * index. 6063 */ 6064 ddi_put64(mpt->m_acc_post_queue_hdl, 6065 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 6066 0xFFFFFFFFFFFFFFFF); 6067 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 6068 DDI_DMA_SYNC_FORDEV); 6069 } 6070 6071 /* 6072 * handle qfull condition 6073 */ 6074 static void 6075 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 6076 { 6077 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 6078 6079 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 6080 (ptgt->m_qfull_retries == 0)) { 6081 /* 6082 * We have exhausted the retries on QFULL, or, 6083 * the target driver has indicated that it 6084 * wants to handle QFULL itself by setting 6085 * qfull-retries capability to 0. In either case 6086 * we want the target driver's QFULL handling 6087 * to kick in. We do this by having pkt_reason 6088 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 6089 */ 6090 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 6091 } else { 6092 if (ptgt->m_reset_delay == 0) { 6093 ptgt->m_t_throttle = 6094 max((ptgt->m_t_ncmds - 2), 0); 6095 } 6096 6097 cmd->cmd_pkt_flags |= FLAG_HEAD; 6098 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 6099 cmd->cmd_flags |= CFLAG_RETRY; 6100 6101 (void) mptsas_accept_pkt(mpt, cmd); 6102 6103 /* 6104 * when target gives queue full status with no commands 6105 * outstanding (m_t_ncmds == 0), throttle is set to 0 6106 * (HOLD_THROTTLE), and the queue full handling start 6107 * (see psarc/1994/313); if there are commands outstanding, 6108 * throttle is set to (m_t_ncmds - 2) 6109 */ 6110 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 6111 /* 6112 * By setting throttle to QFULL_THROTTLE, we 6113 * avoid submitting new commands and in 6114 * mptsas_restart_cmd find out slots which need 6115 * their throttles to be cleared. 6116 */ 6117 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 6118 if (mpt->m_restart_cmd_timeid == 0) { 6119 mpt->m_restart_cmd_timeid = 6120 timeout(mptsas_restart_cmd, mpt, 6121 ptgt->m_qfull_retry_interval); 6122 } 6123 } 6124 } 6125 } 6126 6127 mptsas_phymask_t 6128 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 6129 { 6130 mptsas_phymask_t phy_mask = 0; 6131 uint8_t i = 0; 6132 6133 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 6134 6135 ASSERT(mutex_owned(&mpt->m_mutex)); 6136 6137 /* 6138 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 6139 */ 6140 if (physport == 0xFF) { 6141 return (0); 6142 } 6143 6144 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 6145 if (mpt->m_phy_info[i].attached_devhdl && 6146 (mpt->m_phy_info[i].phy_mask != 0) && 6147 (mpt->m_phy_info[i].port_num == physport)) { 6148 phy_mask = mpt->m_phy_info[i].phy_mask; 6149 break; 6150 } 6151 } 6152 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 6153 mpt->m_instance, physport, phy_mask)); 6154 return (phy_mask); 6155 } 6156 6157 /* 6158 * mpt free device handle after device gone, by use of passthrough 6159 */ 6160 static int 6161 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 6162 { 6163 Mpi2SasIoUnitControlRequest_t req; 6164 Mpi2SasIoUnitControlReply_t rep; 6165 int ret; 6166 6167 ASSERT(mutex_owned(&mpt->m_mutex)); 6168 6169 /* 6170 * Need to compose a SAS IO Unit Control request message 6171 * and call mptsas_do_passthru() function 6172 */ 6173 bzero(&req, sizeof (req)); 6174 bzero(&rep, sizeof (rep)); 6175 6176 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 6177 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 6178 req.DevHandle = LE_16(devhdl); 6179 6180 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 6181 sizeof (req), sizeof (rep), 0, MPTSAS_PASS_THRU_DIRECTION_NONE, 6182 NULL, 0, 60, FKIOCTL); 6183 if (ret != 0) { 6184 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6185 "Control error %d", ret); 6186 return (DDI_FAILURE); 6187 } 6188 6189 /* do passthrough success, check the ioc status */ 6190 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 6191 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6192 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 6193 return (DDI_FAILURE); 6194 } 6195 6196 return (DDI_SUCCESS); 6197 } 6198 6199 /* 6200 * We have a SATA target that has changed, which means the "bridge-port" 6201 * property must be updated to reflect the SAS WWN of the new attachment point. 6202 * This may change if a SATA device changes which bay, and therefore phy, it is 6203 * plugged into. This SATA device may be a multipath virtual device or may be a 6204 * physical device. We have to handle both cases. 6205 */ 6206 static boolean_t 6207 mptsas_update_sata_bridge(mptsas_t *mpt, dev_info_t *parent, 6208 mptsas_target_t *ptgt) 6209 { 6210 int rval; 6211 uint16_t dev_hdl; 6212 uint16_t pdev_hdl; 6213 uint64_t dev_sas_wwn; 6214 uint8_t physport; 6215 uint8_t phy_id; 6216 uint32_t page_address; 6217 uint16_t bay_num, enclosure, io_flags; 6218 uint32_t dev_info; 6219 char uabuf[SCSI_WWN_BUFLEN]; 6220 dev_info_t *dip; 6221 mdi_pathinfo_t *pip; 6222 6223 mutex_enter(&mpt->m_mutex); 6224 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6225 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)ptgt->m_devhdl; 6226 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 6227 &dev_sas_wwn, &dev_info, &physport, &phy_id, &pdev_hdl, &bay_num, 6228 &enclosure, &io_flags); 6229 mutex_exit(&mpt->m_mutex); 6230 if (rval != DDI_SUCCESS) { 6231 mptsas_log(mpt, CE_WARN, "unable to get SAS page 0 for " 6232 "handle %d", page_address); 6233 return (B_FALSE); 6234 } 6235 6236 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 6237 mptsas_log(mpt, CE_WARN, 6238 "mptsas unable to format SATA bridge WWN"); 6239 return (B_FALSE); 6240 } 6241 6242 if (mpt->m_mpxio_enable == TRUE && (pip = mptsas_find_path_addr(parent, 6243 ptgt->m_addr.mta_wwn, 0)) != NULL) { 6244 if (mdi_prop_update_string(pip, SCSI_ADDR_PROP_BRIDGE_PORT, 6245 uabuf) != DDI_SUCCESS) { 6246 mptsas_log(mpt, CE_WARN, 6247 "mptsas unable to create SCSI bridge port " 6248 "property for SATA device"); 6249 return (B_FALSE); 6250 } 6251 return (B_TRUE); 6252 } 6253 6254 if ((dip = mptsas_find_child_addr(parent, ptgt->m_addr.mta_wwn, 6255 0)) != NULL) { 6256 if (ndi_prop_update_string(DDI_DEV_T_NONE, dip, 6257 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != DDI_PROP_SUCCESS) { 6258 mptsas_log(mpt, CE_WARN, 6259 "mptsas unable to create SCSI bridge port " 6260 "property for SATA device"); 6261 return (B_FALSE); 6262 } 6263 return (B_TRUE); 6264 } 6265 6266 mptsas_log(mpt, CE_WARN, "mptsas failed to find dev_info_t or " 6267 "mdi_pathinfo_t for target with WWN %016" PRIx64, 6268 ptgt->m_addr.mta_wwn); 6269 6270 return (B_FALSE); 6271 } 6272 6273 static void 6274 mptsas_update_phymask(mptsas_t *mpt) 6275 { 6276 mptsas_phymask_t mask = 0, phy_mask; 6277 char *phy_mask_name; 6278 uint8_t current_port; 6279 int i, j; 6280 6281 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 6282 6283 ASSERT(mutex_owned(&mpt->m_mutex)); 6284 6285 (void) mptsas_get_sas_io_unit_page(mpt); 6286 6287 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6288 6289 for (i = 0; i < mpt->m_num_phys; i++) { 6290 phy_mask = 0x00; 6291 6292 if (mpt->m_phy_info[i].attached_devhdl == 0) 6293 continue; 6294 6295 bzero(phy_mask_name, sizeof (phy_mask_name)); 6296 6297 current_port = mpt->m_phy_info[i].port_num; 6298 6299 if ((mask & (1 << i)) != 0) 6300 continue; 6301 6302 for (j = 0; j < mpt->m_num_phys; j++) { 6303 if (mpt->m_phy_info[j].attached_devhdl && 6304 (mpt->m_phy_info[j].port_num == current_port)) { 6305 phy_mask |= (1 << j); 6306 } 6307 } 6308 mask = mask | phy_mask; 6309 6310 for (j = 0; j < mpt->m_num_phys; j++) { 6311 if ((phy_mask >> j) & 0x01) { 6312 mpt->m_phy_info[j].phy_mask = phy_mask; 6313 } 6314 } 6315 6316 (void) sprintf(phy_mask_name, "%x", phy_mask); 6317 6318 mutex_exit(&mpt->m_mutex); 6319 /* 6320 * register a iport, if the port has already been existed 6321 * SCSA will do nothing and just return. 6322 */ 6323 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 6324 mutex_enter(&mpt->m_mutex); 6325 } 6326 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6327 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 6328 } 6329 6330 /* 6331 * mptsas_handle_dr is a task handler for DR, the DR action includes: 6332 * 1. Directly attched Device Added/Removed. 6333 * 2. Expander Device Added/Removed. 6334 * 3. Indirectly Attached Device Added/Expander. 6335 * 4. LUNs of a existing device status change. 6336 * 5. RAID volume created/deleted. 6337 * 6. Member of RAID volume is released because of RAID deletion. 6338 * 7. Physical disks are removed because of RAID creation. 6339 */ 6340 static void 6341 mptsas_handle_dr(void *args) 6342 { 6343 mptsas_topo_change_list_t *topo_node = NULL; 6344 mptsas_topo_change_list_t *save_node = NULL; 6345 mptsas_t *mpt; 6346 dev_info_t *parent = NULL; 6347 mptsas_phymask_t phymask = 0; 6348 char *phy_mask_name; 6349 uint8_t flags = 0, physport = 0xff; 6350 uint8_t port_update = 0; 6351 uint_t event; 6352 6353 topo_node = (mptsas_topo_change_list_t *)args; 6354 6355 mpt = topo_node->mpt; 6356 event = topo_node->event; 6357 flags = topo_node->flags; 6358 6359 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6360 6361 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 6362 6363 switch (event) { 6364 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6365 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6366 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 6367 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6368 /* 6369 * Direct attached or expander attached device added 6370 * into system or a Phys Disk that is being unhidden. 6371 */ 6372 port_update = 1; 6373 } 6374 break; 6375 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6376 /* 6377 * New expander added into system, it must be the head 6378 * of topo_change_list_t 6379 */ 6380 port_update = 1; 6381 break; 6382 default: 6383 port_update = 0; 6384 break; 6385 } 6386 /* 6387 * All cases port_update == 1 may cause initiator port form change 6388 */ 6389 mutex_enter(&mpt->m_mutex); 6390 if (mpt->m_port_chng && port_update) { 6391 /* 6392 * mpt->m_port_chng flag indicates some PHYs of initiator 6393 * port have changed to online. So when expander added or 6394 * directly attached device online event come, we force to 6395 * update port information by issueing SAS IO Unit Page and 6396 * update PHYMASKs. 6397 */ 6398 (void) mptsas_update_phymask(mpt); 6399 mpt->m_port_chng = 0; 6400 6401 } 6402 mutex_exit(&mpt->m_mutex); 6403 while (topo_node) { 6404 phymask = 0; 6405 if (parent == NULL) { 6406 physport = topo_node->un.physport; 6407 event = topo_node->event; 6408 flags = topo_node->flags; 6409 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 6410 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 6411 /* 6412 * For all offline events, phymask is known 6413 */ 6414 phymask = topo_node->un.phymask; 6415 goto find_parent; 6416 } 6417 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6418 goto handle_topo_change; 6419 } 6420 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 6421 phymask = topo_node->un.phymask; 6422 goto find_parent; 6423 } 6424 6425 if ((flags == 6426 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 6427 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 6428 /* 6429 * There is no any field in IR_CONFIG_CHANGE 6430 * event indicate physport/phynum, let's get 6431 * parent after SAS Device Page0 request. 6432 */ 6433 goto handle_topo_change; 6434 } 6435 6436 mutex_enter(&mpt->m_mutex); 6437 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6438 /* 6439 * If the direct attached device added or a 6440 * phys disk is being unhidden, argument 6441 * physport actually is PHY#, so we have to get 6442 * phymask according PHY#. 6443 */ 6444 physport = mpt->m_phy_info[physport].port_num; 6445 } 6446 6447 /* 6448 * Translate physport to phymask so that we can search 6449 * parent dip. 6450 */ 6451 phymask = mptsas_physport_to_phymask(mpt, 6452 physport); 6453 mutex_exit(&mpt->m_mutex); 6454 6455 find_parent: 6456 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 6457 /* 6458 * For RAID topology change node, write the iport name 6459 * as v0. 6460 */ 6461 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6462 (void) sprintf(phy_mask_name, "v0"); 6463 } else { 6464 /* 6465 * phymask can bo 0 if the drive has been 6466 * pulled by the time an add event is 6467 * processed. If phymask is 0, just skip this 6468 * event and continue. 6469 */ 6470 if (phymask == 0) { 6471 mutex_enter(&mpt->m_mutex); 6472 save_node = topo_node; 6473 topo_node = topo_node->next; 6474 ASSERT(save_node); 6475 kmem_free(save_node, 6476 sizeof (mptsas_topo_change_list_t)); 6477 mutex_exit(&mpt->m_mutex); 6478 6479 parent = NULL; 6480 continue; 6481 } 6482 (void) sprintf(phy_mask_name, "%x", phymask); 6483 } 6484 parent = scsi_hba_iport_find(mpt->m_dip, 6485 phy_mask_name); 6486 if (parent == NULL) { 6487 mptsas_log(mpt, CE_WARN, "Failed to find an " 6488 "iport, should not happen!"); 6489 goto out; 6490 } 6491 6492 } 6493 ASSERT(parent); 6494 handle_topo_change: 6495 6496 mutex_enter(&mpt->m_mutex); 6497 /* 6498 * If HBA is being reset, don't perform operations depending 6499 * on the IOC. We must free the topo list, however. 6500 */ 6501 if (!mpt->m_in_reset) { 6502 mptsas_handle_topo_change(topo_node, parent); 6503 } else { 6504 NDBG20(("skipping topo change received during reset")); 6505 } 6506 save_node = topo_node; 6507 topo_node = topo_node->next; 6508 ASSERT(save_node); 6509 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 6510 mutex_exit(&mpt->m_mutex); 6511 6512 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6513 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 6514 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 6515 /* 6516 * If direct attached device associated, make sure 6517 * reset the parent before start the next one. But 6518 * all devices associated with expander shares the 6519 * parent. Also, reset parent if this is for RAID. 6520 */ 6521 parent = NULL; 6522 } 6523 } 6524 out: 6525 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6526 } 6527 6528 static void 6529 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 6530 dev_info_t *parent) 6531 { 6532 mptsas_target_t *ptgt = NULL; 6533 mptsas_smp_t *psmp = NULL; 6534 mptsas_t *mpt = (void *)topo_node->mpt; 6535 uint16_t devhdl; 6536 uint16_t attached_devhdl; 6537 uint64_t sas_wwn = 0; 6538 int rval = 0; 6539 uint32_t page_address; 6540 uint8_t phy, flags; 6541 char *addr = NULL; 6542 dev_info_t *lundip; 6543 int circ = 0, circ1 = 0; 6544 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 6545 6546 NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x," 6547 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl, 6548 topo_node->event, topo_node->flags)); 6549 6550 ASSERT(mutex_owned(&mpt->m_mutex)); 6551 6552 switch (topo_node->event) { 6553 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6554 { 6555 char *phy_mask_name; 6556 mptsas_phymask_t phymask = 0; 6557 6558 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6559 /* 6560 * Get latest RAID info. 6561 */ 6562 (void) mptsas_get_raid_info(mpt); 6563 ptgt = refhash_linear_search(mpt->m_targets, 6564 mptsas_target_eval_devhdl, &topo_node->devhdl); 6565 if (ptgt == NULL) 6566 break; 6567 } else { 6568 ptgt = (void *)topo_node->object; 6569 } 6570 6571 if (ptgt == NULL) { 6572 /* 6573 * If a Phys Disk was deleted, RAID info needs to be 6574 * updated to reflect the new topology. 6575 */ 6576 (void) mptsas_get_raid_info(mpt); 6577 6578 /* 6579 * Get sas device page 0 by DevHandle to make sure if 6580 * SSP/SATA end device exist. 6581 */ 6582 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6583 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 6584 topo_node->devhdl; 6585 6586 rval = mptsas_get_target_device_info(mpt, page_address, 6587 &devhdl, &ptgt); 6588 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) { 6589 mptsas_log(mpt, CE_NOTE, 6590 "mptsas_handle_topo_change: target %d is " 6591 "not a SAS/SATA device. \n", 6592 topo_node->devhdl); 6593 } else if (rval == DEV_INFO_FAIL_ALLOC) { 6594 mptsas_log(mpt, CE_NOTE, 6595 "mptsas_handle_topo_change: could not " 6596 "allocate memory. \n"); 6597 } else if (rval == DEV_INFO_FAIL_GUID) { 6598 mptsas_log(mpt, CE_NOTE, 6599 "mptsas_handle_topo_change: could not " 6600 "get SATA GUID for target %d. \n", 6601 topo_node->devhdl); 6602 } 6603 /* 6604 * If rval is DEV_INFO_PHYS_DISK or indicates failure 6605 * then there is nothing else to do, just leave. 6606 */ 6607 if (rval != DEV_INFO_SUCCESS) { 6608 return; 6609 } 6610 } 6611 6612 ASSERT(ptgt->m_devhdl == topo_node->devhdl); 6613 6614 mutex_exit(&mpt->m_mutex); 6615 flags = topo_node->flags; 6616 6617 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) { 6618 phymask = ptgt->m_addr.mta_phymask; 6619 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6620 (void) sprintf(phy_mask_name, "%x", phymask); 6621 parent = scsi_hba_iport_find(mpt->m_dip, 6622 phy_mask_name); 6623 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6624 if (parent == NULL) { 6625 mptsas_log(mpt, CE_WARN, "Failed to find a " 6626 "iport for PD, should not happen!"); 6627 mutex_enter(&mpt->m_mutex); 6628 break; 6629 } 6630 } 6631 6632 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6633 ndi_devi_enter(parent, &circ1); 6634 (void) mptsas_config_raid(parent, topo_node->devhdl, 6635 &lundip); 6636 ndi_devi_exit(parent, circ1); 6637 } else { 6638 /* 6639 * hold nexus for bus configure 6640 */ 6641 ndi_devi_enter(scsi_vhci_dip, &circ); 6642 ndi_devi_enter(parent, &circ1); 6643 rval = mptsas_config_target(parent, ptgt); 6644 /* 6645 * release nexus for bus configure 6646 */ 6647 ndi_devi_exit(parent, circ1); 6648 ndi_devi_exit(scsi_vhci_dip, circ); 6649 6650 /* 6651 * If this is a SATA device, make sure that the 6652 * bridge-port (the SAS WWN that the SATA device is 6653 * plugged into) is updated. This may change if a SATA 6654 * device changes which bay, and therefore phy, it is 6655 * plugged into. 6656 */ 6657 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) { 6658 if (!mptsas_update_sata_bridge(mpt, parent, 6659 ptgt)) { 6660 mutex_enter(&mpt->m_mutex); 6661 return; 6662 } 6663 } 6664 6665 /* 6666 * Add parent's props for SMHBA support 6667 */ 6668 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6669 bzero(attached_wwnstr, 6670 sizeof (attached_wwnstr)); 6671 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 6672 ptgt->m_addr.mta_wwn); 6673 if (ddi_prop_update_string(DDI_DEV_T_NONE, 6674 parent, 6675 SCSI_ADDR_PROP_ATTACHED_PORT, 6676 attached_wwnstr) 6677 != DDI_PROP_SUCCESS) { 6678 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6679 parent, 6680 SCSI_ADDR_PROP_ATTACHED_PORT); 6681 mptsas_log(mpt, CE_WARN, "Failed to" 6682 "attached-port props"); 6683 mutex_enter(&mpt->m_mutex); 6684 return; 6685 } 6686 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6687 MPTSAS_NUM_PHYS, 1) != 6688 DDI_PROP_SUCCESS) { 6689 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6690 parent, MPTSAS_NUM_PHYS); 6691 mptsas_log(mpt, CE_WARN, "Failed to" 6692 " create num-phys props"); 6693 mutex_enter(&mpt->m_mutex); 6694 return; 6695 } 6696 6697 /* 6698 * Update PHY info for smhba 6699 */ 6700 mutex_enter(&mpt->m_mutex); 6701 if (mptsas_smhba_phy_init(mpt)) { 6702 mptsas_log(mpt, CE_WARN, "mptsas phy" 6703 " update failed"); 6704 return; 6705 } 6706 mutex_exit(&mpt->m_mutex); 6707 6708 /* 6709 * topo_node->un.physport is really the PHY# 6710 * for direct attached devices 6711 */ 6712 mptsas_smhba_set_one_phy_props(mpt, parent, 6713 topo_node->un.physport, &attached_devhdl); 6714 6715 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6716 MPTSAS_VIRTUAL_PORT, 0) != 6717 DDI_PROP_SUCCESS) { 6718 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6719 parent, MPTSAS_VIRTUAL_PORT); 6720 mptsas_log(mpt, CE_WARN, 6721 "mptsas virtual-port" 6722 "port prop update failed"); 6723 mutex_enter(&mpt->m_mutex); 6724 return; 6725 } 6726 } 6727 } 6728 mutex_enter(&mpt->m_mutex); 6729 6730 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, " 6731 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl, 6732 ptgt->m_addr.mta_phymask)); 6733 break; 6734 } 6735 case MPTSAS_DR_EVENT_OFFLINE_TARGET: 6736 { 6737 devhdl = topo_node->devhdl; 6738 ptgt = refhash_linear_search(mpt->m_targets, 6739 mptsas_target_eval_devhdl, &devhdl); 6740 if (ptgt == NULL) 6741 break; 6742 6743 sas_wwn = ptgt->m_addr.mta_wwn; 6744 phy = ptgt->m_phynum; 6745 6746 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 6747 6748 if (sas_wwn) { 6749 (void) sprintf(addr, "w%016"PRIx64, sas_wwn); 6750 } else { 6751 (void) sprintf(addr, "p%x", phy); 6752 } 6753 ASSERT(ptgt->m_devhdl == devhdl); 6754 6755 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) || 6756 (topo_node->flags == 6757 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6758 /* 6759 * Get latest RAID info if RAID volume status changes 6760 * or Phys Disk status changes 6761 */ 6762 (void) mptsas_get_raid_info(mpt); 6763 } 6764 /* 6765 * Abort all outstanding command on the device 6766 */ 6767 rval = mptsas_do_scsi_reset(mpt, devhdl); 6768 if (rval) { 6769 NDBG20(("mptsas%d handle_topo_change to reset target " 6770 "before offline devhdl:%x, phymask:%x, rval:%x", 6771 mpt->m_instance, ptgt->m_devhdl, 6772 ptgt->m_addr.mta_phymask, rval)); 6773 } 6774 6775 mutex_exit(&mpt->m_mutex); 6776 6777 ndi_devi_enter(scsi_vhci_dip, &circ); 6778 ndi_devi_enter(parent, &circ1); 6779 rval = mptsas_offline_target(parent, addr); 6780 ndi_devi_exit(parent, circ1); 6781 ndi_devi_exit(scsi_vhci_dip, circ); 6782 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, " 6783 "phymask:%x, rval:%x", mpt->m_instance, 6784 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval)); 6785 6786 kmem_free(addr, SCSI_MAXNAMELEN); 6787 6788 /* 6789 * Clear parent's props for SMHBA support 6790 */ 6791 flags = topo_node->flags; 6792 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6793 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6794 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6795 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6796 DDI_PROP_SUCCESS) { 6797 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6798 SCSI_ADDR_PROP_ATTACHED_PORT); 6799 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6800 "prop update failed"); 6801 mutex_enter(&mpt->m_mutex); 6802 break; 6803 } 6804 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6805 MPTSAS_NUM_PHYS, 0) != 6806 DDI_PROP_SUCCESS) { 6807 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6808 MPTSAS_NUM_PHYS); 6809 mptsas_log(mpt, CE_WARN, "mptsas num phys " 6810 "prop update failed"); 6811 mutex_enter(&mpt->m_mutex); 6812 break; 6813 } 6814 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6815 MPTSAS_VIRTUAL_PORT, 1) != 6816 DDI_PROP_SUCCESS) { 6817 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6818 MPTSAS_VIRTUAL_PORT); 6819 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6820 "prop update failed"); 6821 mutex_enter(&mpt->m_mutex); 6822 break; 6823 } 6824 } 6825 6826 mutex_enter(&mpt->m_mutex); 6827 if (rval == DDI_SUCCESS) { 6828 refhash_remove(mpt->m_targets, ptgt); 6829 ptgt = NULL; 6830 } else { 6831 /* 6832 * clean DR_INTRANSITION flag to allow I/O down to 6833 * PHCI driver since failover finished. 6834 * Invalidate the devhdl 6835 */ 6836 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL; 6837 ptgt->m_tgt_unconfigured = 0; 6838 mutex_enter(&mpt->m_tx_waitq_mutex); 6839 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE; 6840 mutex_exit(&mpt->m_tx_waitq_mutex); 6841 } 6842 6843 /* 6844 * Send SAS IO Unit Control to free the dev handle 6845 */ 6846 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6847 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) { 6848 rval = mptsas_free_devhdl(mpt, devhdl); 6849 6850 NDBG20(("mptsas%d handle_topo_change to remove " 6851 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6852 rval)); 6853 } 6854 6855 break; 6856 } 6857 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE: 6858 { 6859 devhdl = topo_node->devhdl; 6860 /* 6861 * If this is the remove handle event, do a reset first. 6862 */ 6863 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6864 rval = mptsas_do_scsi_reset(mpt, devhdl); 6865 if (rval) { 6866 NDBG20(("mpt%d reset target before remove " 6867 "devhdl:%x, rval:%x", mpt->m_instance, 6868 devhdl, rval)); 6869 } 6870 } 6871 6872 /* 6873 * Send SAS IO Unit Control to free the dev handle 6874 */ 6875 rval = mptsas_free_devhdl(mpt, devhdl); 6876 NDBG20(("mptsas%d handle_topo_change to remove " 6877 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6878 rval)); 6879 break; 6880 } 6881 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6882 { 6883 mptsas_smp_t smp; 6884 dev_info_t *smpdip; 6885 6886 devhdl = topo_node->devhdl; 6887 6888 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 6889 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl; 6890 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp); 6891 if (rval != DDI_SUCCESS) { 6892 mptsas_log(mpt, CE_WARN, "failed to online smp, " 6893 "handle %x", devhdl); 6894 return; 6895 } 6896 6897 psmp = mptsas_smp_alloc(mpt, &smp); 6898 if (psmp == NULL) { 6899 return; 6900 } 6901 6902 mutex_exit(&mpt->m_mutex); 6903 ndi_devi_enter(parent, &circ1); 6904 (void) mptsas_online_smp(parent, psmp, &smpdip); 6905 ndi_devi_exit(parent, circ1); 6906 6907 mutex_enter(&mpt->m_mutex); 6908 break; 6909 } 6910 case MPTSAS_DR_EVENT_OFFLINE_SMP: 6911 { 6912 devhdl = topo_node->devhdl; 6913 uint32_t dev_info; 6914 6915 psmp = refhash_linear_search(mpt->m_smp_targets, 6916 mptsas_smp_eval_devhdl, &devhdl); 6917 if (psmp == NULL) 6918 break; 6919 /* 6920 * The mptsas_smp_t data is released only if the dip is offlined 6921 * successfully. 6922 */ 6923 mutex_exit(&mpt->m_mutex); 6924 6925 ndi_devi_enter(parent, &circ1); 6926 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE); 6927 ndi_devi_exit(parent, circ1); 6928 6929 dev_info = psmp->m_deviceinfo; 6930 if ((dev_info & DEVINFO_DIRECT_ATTACHED) == 6931 DEVINFO_DIRECT_ATTACHED) { 6932 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6933 MPTSAS_VIRTUAL_PORT, 1) != 6934 DDI_PROP_SUCCESS) { 6935 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6936 MPTSAS_VIRTUAL_PORT); 6937 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6938 "prop update failed"); 6939 mutex_enter(&mpt->m_mutex); 6940 return; 6941 } 6942 /* 6943 * Check whether the smp connected to the iport, 6944 */ 6945 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6946 MPTSAS_NUM_PHYS, 0) != 6947 DDI_PROP_SUCCESS) { 6948 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6949 MPTSAS_NUM_PHYS); 6950 mptsas_log(mpt, CE_WARN, "mptsas num phys" 6951 "prop update failed"); 6952 mutex_enter(&mpt->m_mutex); 6953 return; 6954 } 6955 /* 6956 * Clear parent's attached-port props 6957 */ 6958 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6959 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6960 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6961 DDI_PROP_SUCCESS) { 6962 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6963 SCSI_ADDR_PROP_ATTACHED_PORT); 6964 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6965 "prop update failed"); 6966 mutex_enter(&mpt->m_mutex); 6967 return; 6968 } 6969 } 6970 6971 mutex_enter(&mpt->m_mutex); 6972 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, " 6973 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval)); 6974 if (rval == DDI_SUCCESS) { 6975 refhash_remove(mpt->m_smp_targets, psmp); 6976 } else { 6977 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL; 6978 } 6979 6980 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6981 6982 break; 6983 } 6984 default: 6985 return; 6986 } 6987 } 6988 6989 /* 6990 * Record the event if its type is enabled in mpt instance by ioctl. 6991 */ 6992 static void 6993 mptsas_record_event(void *args) 6994 { 6995 m_replyh_arg_t *replyh_arg; 6996 pMpi2EventNotificationReply_t eventreply; 6997 uint32_t event, rfm; 6998 mptsas_t *mpt; 6999 int i, j; 7000 uint16_t event_data_len; 7001 boolean_t sendAEN = FALSE; 7002 7003 replyh_arg = (m_replyh_arg_t *)args; 7004 rfm = replyh_arg->rfm; 7005 mpt = replyh_arg->mpt; 7006 7007 eventreply = (pMpi2EventNotificationReply_t) 7008 (mpt->m_reply_frame + (rfm - 7009 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7010 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7011 7012 7013 /* 7014 * Generate a system event to let anyone who cares know that a 7015 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the 7016 * event mask is set to. 7017 */ 7018 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) { 7019 sendAEN = TRUE; 7020 } 7021 7022 /* 7023 * Record the event only if it is not masked. Determine which dword 7024 * and bit of event mask to test. 7025 */ 7026 i = (uint8_t)(event / 32); 7027 j = (uint8_t)(event % 32); 7028 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) { 7029 i = mpt->m_event_index; 7030 mpt->m_events[i].Type = event; 7031 mpt->m_events[i].Number = ++mpt->m_event_number; 7032 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4); 7033 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl, 7034 &eventreply->EventDataLength); 7035 7036 if (event_data_len > 0) { 7037 /* 7038 * Limit data to size in m_event entry 7039 */ 7040 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) { 7041 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH; 7042 } 7043 for (j = 0; j < event_data_len; j++) { 7044 mpt->m_events[i].Data[j] = 7045 ddi_get32(mpt->m_acc_reply_frame_hdl, 7046 &(eventreply->EventData[j])); 7047 } 7048 7049 /* 7050 * check for index wrap-around 7051 */ 7052 if (++i == MPTSAS_EVENT_QUEUE_SIZE) { 7053 i = 0; 7054 } 7055 mpt->m_event_index = (uint8_t)i; 7056 7057 /* 7058 * Set flag to send the event. 7059 */ 7060 sendAEN = TRUE; 7061 } 7062 } 7063 7064 /* 7065 * Generate a system event if flag is set to let anyone who cares know 7066 * that an event has occurred. 7067 */ 7068 if (sendAEN) { 7069 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS", 7070 "SAS", NULL, NULL, DDI_NOSLEEP); 7071 } 7072 } 7073 7074 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS 7075 /* 7076 * handle sync events from ioc in interrupt 7077 * return value: 7078 * DDI_SUCCESS: The event is handled by this func 7079 * DDI_FAILURE: Event is not handled 7080 */ 7081 static int 7082 mptsas_handle_event_sync(void *args) 7083 { 7084 m_replyh_arg_t *replyh_arg; 7085 pMpi2EventNotificationReply_t eventreply; 7086 uint32_t event, rfm; 7087 mptsas_t *mpt; 7088 uint_t iocstatus; 7089 7090 replyh_arg = (m_replyh_arg_t *)args; 7091 rfm = replyh_arg->rfm; 7092 mpt = replyh_arg->mpt; 7093 7094 ASSERT(mutex_owned(&mpt->m_mutex)); 7095 7096 eventreply = (pMpi2EventNotificationReply_t) 7097 (mpt->m_reply_frame + (rfm - 7098 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7099 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7100 7101 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7102 &eventreply->IOCStatus)) != 0) { 7103 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7104 mptsas_log(mpt, CE_WARN, 7105 "!mptsas_handle_event_sync: event 0x%x, " 7106 "IOCStatus=0x%x, " 7107 "IOCLogInfo=0x%x", event, iocstatus, 7108 ddi_get32(mpt->m_acc_reply_frame_hdl, 7109 &eventreply->IOCLogInfo)); 7110 } else { 7111 mptsas_log(mpt, CE_WARN, 7112 "mptsas_handle_event_sync: event 0x%x, " 7113 "IOCStatus=0x%x, " 7114 "(IOCLogInfo=0x%x)", event, iocstatus, 7115 ddi_get32(mpt->m_acc_reply_frame_hdl, 7116 &eventreply->IOCLogInfo)); 7117 } 7118 } 7119 7120 /* 7121 * figure out what kind of event we got and handle accordingly 7122 */ 7123 switch (event) { 7124 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7125 { 7126 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list; 7127 uint8_t num_entries, expstatus, phy; 7128 uint8_t phystatus, physport, state, i; 7129 uint8_t start_phy_num, link_rate; 7130 uint16_t dev_handle, reason_code; 7131 uint16_t enc_handle, expd_handle; 7132 char string[80], curr[80], prev[80]; 7133 mptsas_topo_change_list_t *topo_head = NULL; 7134 mptsas_topo_change_list_t *topo_tail = NULL; 7135 mptsas_topo_change_list_t *topo_node = NULL; 7136 mptsas_target_t *ptgt; 7137 mptsas_smp_t *psmp; 7138 uint8_t flags = 0, exp_flag; 7139 smhba_info_t *pSmhba = NULL; 7140 7141 NDBG20(("mptsas_handle_event_sync: SAS topology change")); 7142 7143 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t) 7144 eventreply->EventData; 7145 7146 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7147 &sas_topo_change_list->EnclosureHandle); 7148 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7149 &sas_topo_change_list->ExpanderDevHandle); 7150 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7151 &sas_topo_change_list->NumEntries); 7152 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 7153 &sas_topo_change_list->StartPhyNum); 7154 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7155 &sas_topo_change_list->ExpStatus); 7156 physport = ddi_get8(mpt->m_acc_reply_frame_hdl, 7157 &sas_topo_change_list->PhysicalPort); 7158 7159 string[0] = 0; 7160 if (expd_handle) { 7161 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED; 7162 switch (expstatus) { 7163 case MPI2_EVENT_SAS_TOPO_ES_ADDED: 7164 (void) sprintf(string, " added"); 7165 /* 7166 * New expander device added 7167 */ 7168 mpt->m_port_chng = 1; 7169 topo_node = kmem_zalloc( 7170 sizeof (mptsas_topo_change_list_t), 7171 KM_SLEEP); 7172 topo_node->mpt = mpt; 7173 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP; 7174 topo_node->un.physport = physport; 7175 topo_node->devhdl = expd_handle; 7176 topo_node->flags = flags; 7177 topo_node->object = NULL; 7178 if (topo_head == NULL) { 7179 topo_head = topo_tail = topo_node; 7180 } else { 7181 topo_tail->next = topo_node; 7182 topo_tail = topo_node; 7183 } 7184 break; 7185 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: 7186 (void) sprintf(string, " not responding, " 7187 "removed"); 7188 psmp = refhash_linear_search(mpt->m_smp_targets, 7189 mptsas_smp_eval_devhdl, &expd_handle); 7190 if (psmp == NULL) 7191 break; 7192 7193 topo_node = kmem_zalloc( 7194 sizeof (mptsas_topo_change_list_t), 7195 KM_SLEEP); 7196 topo_node->mpt = mpt; 7197 topo_node->un.phymask = 7198 psmp->m_addr.mta_phymask; 7199 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP; 7200 topo_node->devhdl = expd_handle; 7201 topo_node->flags = flags; 7202 topo_node->object = NULL; 7203 if (topo_head == NULL) { 7204 topo_head = topo_tail = topo_node; 7205 } else { 7206 topo_tail->next = topo_node; 7207 topo_tail = topo_node; 7208 } 7209 break; 7210 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: 7211 break; 7212 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: 7213 (void) sprintf(string, " not responding, " 7214 "delaying removal"); 7215 break; 7216 default: 7217 break; 7218 } 7219 } else { 7220 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE; 7221 } 7222 7223 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n", 7224 enc_handle, expd_handle, string)); 7225 for (i = 0; i < num_entries; i++) { 7226 phy = i + start_phy_num; 7227 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7228 &sas_topo_change_list->PHY[i].PhyStatus); 7229 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7230 &sas_topo_change_list->PHY[i].AttachedDevHandle); 7231 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK; 7232 /* 7233 * Filter out processing of Phy Vacant Status unless 7234 * the reason code is "Not Responding". Process all 7235 * other combinations of Phy Status and Reason Codes. 7236 */ 7237 if ((phystatus & 7238 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) && 7239 (reason_code != 7240 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) { 7241 continue; 7242 } 7243 curr[0] = 0; 7244 prev[0] = 0; 7245 string[0] = 0; 7246 switch (reason_code) { 7247 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: 7248 { 7249 NDBG20(("mptsas%d phy %d physical_port %d " 7250 "dev_handle %d added", mpt->m_instance, phy, 7251 physport, dev_handle)); 7252 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7253 &sas_topo_change_list->PHY[i].LinkRate); 7254 state = (link_rate & 7255 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7256 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7257 switch (state) { 7258 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7259 (void) sprintf(curr, "is disabled"); 7260 break; 7261 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7262 (void) sprintf(curr, "is offline, " 7263 "failed speed negotiation"); 7264 break; 7265 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7266 (void) sprintf(curr, "SATA OOB " 7267 "complete"); 7268 break; 7269 case SMP_RESET_IN_PROGRESS: 7270 (void) sprintf(curr, "SMP reset in " 7271 "progress"); 7272 break; 7273 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7274 (void) sprintf(curr, "is online at " 7275 "1.5 Gbps"); 7276 break; 7277 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7278 (void) sprintf(curr, "is online at 3.0 " 7279 "Gbps"); 7280 break; 7281 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7282 (void) sprintf(curr, "is online at 6.0 " 7283 "Gbps"); 7284 break; 7285 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7286 (void) sprintf(curr, 7287 "is online at 12.0 Gbps"); 7288 break; 7289 default: 7290 (void) sprintf(curr, "state is " 7291 "unknown"); 7292 break; 7293 } 7294 /* 7295 * New target device added into the system. 7296 * Set association flag according to if an 7297 * expander is used or not. 7298 */ 7299 exp_flag = 7300 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7301 if (flags == 7302 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7303 flags = exp_flag; 7304 } 7305 topo_node = kmem_zalloc( 7306 sizeof (mptsas_topo_change_list_t), 7307 KM_SLEEP); 7308 topo_node->mpt = mpt; 7309 topo_node->event = 7310 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7311 if (expd_handle == 0) { 7312 /* 7313 * Per MPI 2, if expander dev handle 7314 * is 0, it's a directly attached 7315 * device. So driver use PHY to decide 7316 * which iport is associated 7317 */ 7318 physport = phy; 7319 mpt->m_port_chng = 1; 7320 } 7321 topo_node->un.physport = physport; 7322 topo_node->devhdl = dev_handle; 7323 topo_node->flags = flags; 7324 topo_node->object = NULL; 7325 if (topo_head == NULL) { 7326 topo_head = topo_tail = topo_node; 7327 } else { 7328 topo_tail->next = topo_node; 7329 topo_tail = topo_node; 7330 } 7331 break; 7332 } 7333 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: 7334 { 7335 NDBG20(("mptsas%d phy %d physical_port %d " 7336 "dev_handle %d removed", mpt->m_instance, 7337 phy, physport, dev_handle)); 7338 /* 7339 * Set association flag according to if an 7340 * expander is used or not. 7341 */ 7342 exp_flag = 7343 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7344 if (flags == 7345 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7346 flags = exp_flag; 7347 } 7348 /* 7349 * Target device is removed from the system 7350 * Before the device is really offline from 7351 * from system. 7352 */ 7353 ptgt = refhash_linear_search(mpt->m_targets, 7354 mptsas_target_eval_devhdl, &dev_handle); 7355 /* 7356 * If ptgt is NULL here, it means that the 7357 * DevHandle is not in the hash table. This is 7358 * reasonable sometimes. For example, if a 7359 * disk was pulled, then added, then pulled 7360 * again, the disk will not have been put into 7361 * the hash table because the add event will 7362 * have an invalid phymask. BUT, this does not 7363 * mean that the DevHandle is invalid. The 7364 * controller will still have a valid DevHandle 7365 * that must be removed. To do this, use the 7366 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event. 7367 */ 7368 if (ptgt == NULL) { 7369 topo_node = kmem_zalloc( 7370 sizeof (mptsas_topo_change_list_t), 7371 KM_SLEEP); 7372 topo_node->mpt = mpt; 7373 topo_node->un.phymask = 0; 7374 topo_node->event = 7375 MPTSAS_TOPO_FLAG_REMOVE_HANDLE; 7376 topo_node->devhdl = dev_handle; 7377 topo_node->flags = flags; 7378 topo_node->object = NULL; 7379 if (topo_head == NULL) { 7380 topo_head = topo_tail = 7381 topo_node; 7382 } else { 7383 topo_tail->next = topo_node; 7384 topo_tail = topo_node; 7385 } 7386 break; 7387 } 7388 7389 /* 7390 * Update DR flag immediately avoid I/O failure 7391 * before failover finish. Pay attention to the 7392 * mutex protect, we need grab m_tx_waitq_mutex 7393 * during set m_dr_flag because we won't add 7394 * the following command into waitq, instead, 7395 * we need return TRAN_BUSY in the tran_start 7396 * context. 7397 */ 7398 mutex_enter(&mpt->m_tx_waitq_mutex); 7399 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7400 mutex_exit(&mpt->m_tx_waitq_mutex); 7401 7402 topo_node = kmem_zalloc( 7403 sizeof (mptsas_topo_change_list_t), 7404 KM_SLEEP); 7405 topo_node->mpt = mpt; 7406 topo_node->un.phymask = 7407 ptgt->m_addr.mta_phymask; 7408 topo_node->event = 7409 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7410 topo_node->devhdl = dev_handle; 7411 topo_node->flags = flags; 7412 topo_node->object = NULL; 7413 if (topo_head == NULL) { 7414 topo_head = topo_tail = topo_node; 7415 } else { 7416 topo_tail->next = topo_node; 7417 topo_tail = topo_node; 7418 } 7419 break; 7420 } 7421 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: 7422 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7423 &sas_topo_change_list->PHY[i].LinkRate); 7424 state = (link_rate & 7425 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7426 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7427 pSmhba = &mpt->m_phy_info[i].smhba_info; 7428 pSmhba->negotiated_link_rate = state; 7429 switch (state) { 7430 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7431 (void) sprintf(curr, "is disabled"); 7432 mptsas_smhba_log_sysevent(mpt, 7433 ESC_SAS_PHY_EVENT, 7434 SAS_PHY_REMOVE, 7435 &mpt->m_phy_info[i].smhba_info); 7436 mpt->m_phy_info[i].smhba_info. 7437 negotiated_link_rate 7438 = 0x1; 7439 break; 7440 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7441 (void) sprintf(curr, "is offline, " 7442 "failed speed negotiation"); 7443 mptsas_smhba_log_sysevent(mpt, 7444 ESC_SAS_PHY_EVENT, 7445 SAS_PHY_OFFLINE, 7446 &mpt->m_phy_info[i].smhba_info); 7447 break; 7448 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7449 (void) sprintf(curr, "SATA OOB " 7450 "complete"); 7451 break; 7452 case SMP_RESET_IN_PROGRESS: 7453 (void) sprintf(curr, "SMP reset in " 7454 "progress"); 7455 break; 7456 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7457 (void) sprintf(curr, "is online at " 7458 "1.5 Gbps"); 7459 if ((expd_handle == 0) && 7460 (enc_handle == 1)) { 7461 mpt->m_port_chng = 1; 7462 } 7463 mptsas_smhba_log_sysevent(mpt, 7464 ESC_SAS_PHY_EVENT, 7465 SAS_PHY_ONLINE, 7466 &mpt->m_phy_info[i].smhba_info); 7467 break; 7468 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7469 (void) sprintf(curr, "is online at 3.0 " 7470 "Gbps"); 7471 if ((expd_handle == 0) && 7472 (enc_handle == 1)) { 7473 mpt->m_port_chng = 1; 7474 } 7475 mptsas_smhba_log_sysevent(mpt, 7476 ESC_SAS_PHY_EVENT, 7477 SAS_PHY_ONLINE, 7478 &mpt->m_phy_info[i].smhba_info); 7479 break; 7480 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7481 (void) sprintf(curr, "is online at " 7482 "6.0 Gbps"); 7483 if ((expd_handle == 0) && 7484 (enc_handle == 1)) { 7485 mpt->m_port_chng = 1; 7486 } 7487 mptsas_smhba_log_sysevent(mpt, 7488 ESC_SAS_PHY_EVENT, 7489 SAS_PHY_ONLINE, 7490 &mpt->m_phy_info[i].smhba_info); 7491 break; 7492 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7493 (void) sprintf(curr, "is online at " 7494 "12.0 Gbps"); 7495 if ((expd_handle == 0) && 7496 (enc_handle == 1)) { 7497 mpt->m_port_chng = 1; 7498 } 7499 mptsas_smhba_log_sysevent(mpt, 7500 ESC_SAS_PHY_EVENT, 7501 SAS_PHY_ONLINE, 7502 &mpt->m_phy_info[i].smhba_info); 7503 break; 7504 default: 7505 (void) sprintf(curr, "state is " 7506 "unknown"); 7507 break; 7508 } 7509 7510 state = (link_rate & 7511 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >> 7512 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT; 7513 switch (state) { 7514 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7515 (void) sprintf(prev, ", was disabled"); 7516 break; 7517 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7518 (void) sprintf(prev, ", was offline, " 7519 "failed speed negotiation"); 7520 break; 7521 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7522 (void) sprintf(prev, ", was SATA OOB " 7523 "complete"); 7524 break; 7525 case SMP_RESET_IN_PROGRESS: 7526 (void) sprintf(prev, ", was SMP reset " 7527 "in progress"); 7528 break; 7529 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7530 (void) sprintf(prev, ", was online at " 7531 "1.5 Gbps"); 7532 break; 7533 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7534 (void) sprintf(prev, ", was online at " 7535 "3.0 Gbps"); 7536 break; 7537 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7538 (void) sprintf(prev, ", was online at " 7539 "6.0 Gbps"); 7540 break; 7541 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7542 (void) sprintf(prev, ", was online at " 7543 "12.0 Gbps"); 7544 break; 7545 default: 7546 break; 7547 } 7548 (void) sprintf(&string[strlen(string)], "link " 7549 "changed, "); 7550 break; 7551 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: 7552 continue; 7553 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: 7554 (void) sprintf(&string[strlen(string)], 7555 "target not responding, delaying " 7556 "removal"); 7557 break; 7558 } 7559 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n", 7560 mpt->m_instance, phy, dev_handle, string, curr, 7561 prev)); 7562 } 7563 if (topo_head != NULL) { 7564 /* 7565 * Launch DR taskq to handle topology change 7566 */ 7567 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7568 mptsas_handle_dr, (void *)topo_head, 7569 DDI_NOSLEEP)) != DDI_SUCCESS) { 7570 while (topo_head != NULL) { 7571 topo_node = topo_head; 7572 topo_head = topo_head->next; 7573 kmem_free(topo_node, 7574 sizeof (mptsas_topo_change_list_t)); 7575 } 7576 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7577 "for handle SAS DR event failed. \n"); 7578 } 7579 } 7580 break; 7581 } 7582 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7583 { 7584 Mpi2EventDataIrConfigChangeList_t *irChangeList; 7585 mptsas_topo_change_list_t *topo_head = NULL; 7586 mptsas_topo_change_list_t *topo_tail = NULL; 7587 mptsas_topo_change_list_t *topo_node = NULL; 7588 mptsas_target_t *ptgt; 7589 uint8_t num_entries, i, reason; 7590 uint16_t volhandle, diskhandle; 7591 7592 irChangeList = (pMpi2EventDataIrConfigChangeList_t) 7593 eventreply->EventData; 7594 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7595 &irChangeList->NumElements); 7596 7597 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received", 7598 mpt->m_instance)); 7599 7600 for (i = 0; i < num_entries; i++) { 7601 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7602 &irChangeList->ConfigElement[i].ReasonCode); 7603 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7604 &irChangeList->ConfigElement[i].VolDevHandle); 7605 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7606 &irChangeList->ConfigElement[i].PhysDiskDevHandle); 7607 7608 switch (reason) { 7609 case MPI2_EVENT_IR_CHANGE_RC_ADDED: 7610 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: 7611 { 7612 NDBG20(("mptsas %d volume added\n", 7613 mpt->m_instance)); 7614 7615 topo_node = kmem_zalloc( 7616 sizeof (mptsas_topo_change_list_t), 7617 KM_SLEEP); 7618 7619 topo_node->mpt = mpt; 7620 topo_node->event = 7621 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7622 topo_node->un.physport = 0xff; 7623 topo_node->devhdl = volhandle; 7624 topo_node->flags = 7625 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7626 topo_node->object = NULL; 7627 if (topo_head == NULL) { 7628 topo_head = topo_tail = topo_node; 7629 } else { 7630 topo_tail->next = topo_node; 7631 topo_tail = topo_node; 7632 } 7633 break; 7634 } 7635 case MPI2_EVENT_IR_CHANGE_RC_REMOVED: 7636 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: 7637 { 7638 NDBG20(("mptsas %d volume deleted\n", 7639 mpt->m_instance)); 7640 ptgt = refhash_linear_search(mpt->m_targets, 7641 mptsas_target_eval_devhdl, &volhandle); 7642 if (ptgt == NULL) 7643 break; 7644 7645 /* 7646 * Clear any flags related to volume 7647 */ 7648 (void) mptsas_delete_volume(mpt, volhandle); 7649 7650 /* 7651 * Update DR flag immediately avoid I/O failure 7652 */ 7653 mutex_enter(&mpt->m_tx_waitq_mutex); 7654 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7655 mutex_exit(&mpt->m_tx_waitq_mutex); 7656 7657 topo_node = kmem_zalloc( 7658 sizeof (mptsas_topo_change_list_t), 7659 KM_SLEEP); 7660 topo_node->mpt = mpt; 7661 topo_node->un.phymask = 7662 ptgt->m_addr.mta_phymask; 7663 topo_node->event = 7664 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7665 topo_node->devhdl = volhandle; 7666 topo_node->flags = 7667 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7668 topo_node->object = (void *)ptgt; 7669 if (topo_head == NULL) { 7670 topo_head = topo_tail = topo_node; 7671 } else { 7672 topo_tail->next = topo_node; 7673 topo_tail = topo_node; 7674 } 7675 break; 7676 } 7677 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: 7678 case MPI2_EVENT_IR_CHANGE_RC_HIDE: 7679 { 7680 ptgt = refhash_linear_search(mpt->m_targets, 7681 mptsas_target_eval_devhdl, &diskhandle); 7682 if (ptgt == NULL) 7683 break; 7684 7685 /* 7686 * Update DR flag immediately avoid I/O failure 7687 */ 7688 mutex_enter(&mpt->m_tx_waitq_mutex); 7689 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7690 mutex_exit(&mpt->m_tx_waitq_mutex); 7691 7692 topo_node = kmem_zalloc( 7693 sizeof (mptsas_topo_change_list_t), 7694 KM_SLEEP); 7695 topo_node->mpt = mpt; 7696 topo_node->un.phymask = 7697 ptgt->m_addr.mta_phymask; 7698 topo_node->event = 7699 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7700 topo_node->devhdl = diskhandle; 7701 topo_node->flags = 7702 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7703 topo_node->object = (void *)ptgt; 7704 if (topo_head == NULL) { 7705 topo_head = topo_tail = topo_node; 7706 } else { 7707 topo_tail->next = topo_node; 7708 topo_tail = topo_node; 7709 } 7710 break; 7711 } 7712 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: 7713 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: 7714 { 7715 /* 7716 * The physical drive is released by a IR 7717 * volume. But we cannot get the the physport 7718 * or phynum from the event data, so we only 7719 * can get the physport/phynum after SAS 7720 * Device Page0 request for the devhdl. 7721 */ 7722 topo_node = kmem_zalloc( 7723 sizeof (mptsas_topo_change_list_t), 7724 KM_SLEEP); 7725 topo_node->mpt = mpt; 7726 topo_node->un.phymask = 0; 7727 topo_node->event = 7728 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7729 topo_node->devhdl = diskhandle; 7730 topo_node->flags = 7731 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7732 topo_node->object = NULL; 7733 mpt->m_port_chng = 1; 7734 if (topo_head == NULL) { 7735 topo_head = topo_tail = topo_node; 7736 } else { 7737 topo_tail->next = topo_node; 7738 topo_tail = topo_node; 7739 } 7740 break; 7741 } 7742 default: 7743 break; 7744 } 7745 } 7746 7747 if (topo_head != NULL) { 7748 /* 7749 * Launch DR taskq to handle topology change 7750 */ 7751 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7752 mptsas_handle_dr, (void *)topo_head, 7753 DDI_NOSLEEP)) != DDI_SUCCESS) { 7754 while (topo_head != NULL) { 7755 topo_node = topo_head; 7756 topo_head = topo_head->next; 7757 kmem_free(topo_node, 7758 sizeof (mptsas_topo_change_list_t)); 7759 } 7760 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7761 "for handle SAS DR event failed. \n"); 7762 } 7763 } 7764 break; 7765 } 7766 default: 7767 return (DDI_FAILURE); 7768 } 7769 7770 return (DDI_SUCCESS); 7771 } 7772 7773 /* 7774 * handle events from ioc 7775 */ 7776 static void 7777 mptsas_handle_event(void *args) 7778 { 7779 m_replyh_arg_t *replyh_arg; 7780 pMpi2EventNotificationReply_t eventreply; 7781 uint32_t event, iocloginfo, rfm; 7782 uint32_t status; 7783 uint8_t port; 7784 mptsas_t *mpt; 7785 uint_t iocstatus; 7786 7787 replyh_arg = (m_replyh_arg_t *)args; 7788 rfm = replyh_arg->rfm; 7789 mpt = replyh_arg->mpt; 7790 7791 mutex_enter(&mpt->m_mutex); 7792 /* 7793 * If HBA is being reset, drop incoming event. 7794 */ 7795 if (mpt->m_in_reset) { 7796 NDBG20(("dropping event received prior to reset")); 7797 mutex_exit(&mpt->m_mutex); 7798 return; 7799 } 7800 7801 eventreply = (pMpi2EventNotificationReply_t) 7802 (mpt->m_reply_frame + (rfm - 7803 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7804 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7805 7806 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7807 &eventreply->IOCStatus)) != 0) { 7808 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7809 mptsas_log(mpt, CE_WARN, 7810 "!mptsas_handle_event: IOCStatus=0x%x, " 7811 "IOCLogInfo=0x%x", iocstatus, 7812 ddi_get32(mpt->m_acc_reply_frame_hdl, 7813 &eventreply->IOCLogInfo)); 7814 } else { 7815 mptsas_log(mpt, CE_WARN, 7816 "mptsas_handle_event: IOCStatus=0x%x, " 7817 "IOCLogInfo=0x%x", iocstatus, 7818 ddi_get32(mpt->m_acc_reply_frame_hdl, 7819 &eventreply->IOCLogInfo)); 7820 } 7821 } 7822 7823 /* 7824 * figure out what kind of event we got and handle accordingly 7825 */ 7826 switch (event) { 7827 case MPI2_EVENT_LOG_ENTRY_ADDED: 7828 break; 7829 case MPI2_EVENT_LOG_DATA: 7830 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7831 &eventreply->IOCLogInfo); 7832 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance, 7833 iocloginfo)); 7834 break; 7835 case MPI2_EVENT_STATE_CHANGE: 7836 NDBG20(("mptsas%d state change.", mpt->m_instance)); 7837 break; 7838 case MPI2_EVENT_HARD_RESET_RECEIVED: 7839 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7840 break; 7841 case MPI2_EVENT_SAS_DISCOVERY: 7842 { 7843 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery; 7844 char string[80]; 7845 uint8_t rc; 7846 7847 sasdiscovery = 7848 (pMpi2EventDataSasDiscovery_t)eventreply->EventData; 7849 7850 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7851 &sasdiscovery->ReasonCode); 7852 port = ddi_get8(mpt->m_acc_reply_frame_hdl, 7853 &sasdiscovery->PhysicalPort); 7854 status = ddi_get32(mpt->m_acc_reply_frame_hdl, 7855 &sasdiscovery->DiscoveryStatus); 7856 7857 string[0] = 0; 7858 switch (rc) { 7859 case MPI2_EVENT_SAS_DISC_RC_STARTED: 7860 (void) sprintf(string, "STARTING"); 7861 break; 7862 case MPI2_EVENT_SAS_DISC_RC_COMPLETED: 7863 (void) sprintf(string, "COMPLETED"); 7864 break; 7865 default: 7866 (void) sprintf(string, "UNKNOWN"); 7867 break; 7868 } 7869 7870 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string, 7871 port, status)); 7872 7873 break; 7874 } 7875 case MPI2_EVENT_EVENT_CHANGE: 7876 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7877 break; 7878 case MPI2_EVENT_TASK_SET_FULL: 7879 { 7880 pMpi2EventDataTaskSetFull_t taskfull; 7881 7882 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData; 7883 7884 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n", 7885 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7886 &taskfull->CurrentDepth))); 7887 break; 7888 } 7889 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7890 { 7891 /* 7892 * SAS TOPOLOGY CHANGE LIST Event has already been handled 7893 * in mptsas_handle_event_sync() of interrupt context 7894 */ 7895 break; 7896 } 7897 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 7898 { 7899 pMpi2EventDataSasEnclDevStatusChange_t encstatus; 7900 uint8_t rc; 7901 uint16_t enchdl; 7902 char string[80]; 7903 mptsas_enclosure_t *mep; 7904 7905 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t) 7906 eventreply->EventData; 7907 7908 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7909 &encstatus->ReasonCode); 7910 enchdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7911 &encstatus->EnclosureHandle); 7912 7913 switch (rc) { 7914 case MPI2_EVENT_SAS_ENCL_RC_ADDED: 7915 (void) sprintf(string, "added"); 7916 break; 7917 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: 7918 mep = mptsas_enc_lookup(mpt, enchdl); 7919 if (mep != NULL) { 7920 list_remove(&mpt->m_enclosures, mep); 7921 mptsas_enc_free(mep); 7922 mep = NULL; 7923 } 7924 (void) sprintf(string, ", not responding"); 7925 break; 7926 default: 7927 break; 7928 } 7929 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure " 7930 "%x%s\n", mpt->m_instance, 7931 ddi_get16(mpt->m_acc_reply_frame_hdl, 7932 &encstatus->EnclosureHandle), string)); 7933 7934 /* 7935 * No matter what has happened, update all of our device state 7936 * for enclosures, by retriggering an evaluation. 7937 */ 7938 mpt->m_done_traverse_enc = 0; 7939 mptsas_update_hashtab(mpt); 7940 break; 7941 } 7942 7943 /* 7944 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by 7945 * mptsas_handle_event_sync,in here just send ack message. 7946 */ 7947 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 7948 { 7949 pMpi2EventDataSasDeviceStatusChange_t statuschange; 7950 uint8_t rc; 7951 uint16_t devhdl; 7952 uint64_t wwn = 0; 7953 uint32_t wwn_lo, wwn_hi; 7954 7955 statuschange = (pMpi2EventDataSasDeviceStatusChange_t) 7956 eventreply->EventData; 7957 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7958 &statuschange->ReasonCode); 7959 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7960 (uint32_t *)(void *)&statuschange->SASAddress); 7961 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl, 7962 (uint32_t *)(void *)&statuschange->SASAddress + 1); 7963 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo; 7964 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7965 &statuschange->DevHandle); 7966 7967 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64, 7968 wwn)); 7969 7970 switch (rc) { 7971 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7972 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x", 7973 ddi_get8(mpt->m_acc_reply_frame_hdl, 7974 &statuschange->ASC), 7975 ddi_get8(mpt->m_acc_reply_frame_hdl, 7976 &statuschange->ASCQ))); 7977 break; 7978 7979 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7980 NDBG20(("Device not supported")); 7981 break; 7982 7983 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7984 NDBG20(("IOC internally generated the Target Reset " 7985 "for devhdl:%x", devhdl)); 7986 break; 7987 7988 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: 7989 NDBG20(("IOC's internally generated Target Reset " 7990 "completed for devhdl:%x", devhdl)); 7991 break; 7992 7993 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7994 NDBG20(("IOC internally generated Abort Task")); 7995 break; 7996 7997 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: 7998 NDBG20(("IOC's internally generated Abort Task " 7999 "completed")); 8000 break; 8001 8002 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 8003 NDBG20(("IOC internally generated Abort Task Set")); 8004 break; 8005 8006 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 8007 NDBG20(("IOC internally generated Clear Task Set")); 8008 break; 8009 8010 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 8011 NDBG20(("IOC internally generated Query Task")); 8012 break; 8013 8014 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: 8015 NDBG20(("Device sent an Asynchronous Notification")); 8016 break; 8017 8018 default: 8019 break; 8020 } 8021 break; 8022 } 8023 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 8024 { 8025 /* 8026 * IR TOPOLOGY CHANGE LIST Event has already been handled 8027 * in mpt_handle_event_sync() of interrupt context 8028 */ 8029 break; 8030 } 8031 case MPI2_EVENT_IR_OPERATION_STATUS: 8032 { 8033 Mpi2EventDataIrOperationStatus_t *irOpStatus; 8034 char reason_str[80]; 8035 uint8_t rc, percent; 8036 uint16_t handle; 8037 8038 irOpStatus = (pMpi2EventDataIrOperationStatus_t) 8039 eventreply->EventData; 8040 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 8041 &irOpStatus->RAIDOperation); 8042 percent = ddi_get8(mpt->m_acc_reply_frame_hdl, 8043 &irOpStatus->PercentComplete); 8044 handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8045 &irOpStatus->VolDevHandle); 8046 8047 switch (rc) { 8048 case MPI2_EVENT_IR_RAIDOP_RESYNC: 8049 (void) sprintf(reason_str, "resync"); 8050 break; 8051 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: 8052 (void) sprintf(reason_str, "online capacity " 8053 "expansion"); 8054 break; 8055 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: 8056 (void) sprintf(reason_str, "consistency check"); 8057 break; 8058 default: 8059 (void) sprintf(reason_str, "unknown reason %x", 8060 rc); 8061 } 8062 8063 NDBG20(("mptsas%d raid operational status: (%s)" 8064 "\thandle(0x%04x), percent complete(%d)\n", 8065 mpt->m_instance, reason_str, handle, percent)); 8066 break; 8067 } 8068 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 8069 { 8070 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast; 8071 uint8_t phy_num; 8072 uint8_t primitive; 8073 8074 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t) 8075 eventreply->EventData; 8076 8077 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 8078 &sas_broadcast->PhyNum); 8079 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl, 8080 &sas_broadcast->Primitive); 8081 8082 switch (primitive) { 8083 case MPI2_EVENT_PRIMITIVE_CHANGE: 8084 mptsas_smhba_log_sysevent(mpt, 8085 ESC_SAS_HBA_PORT_BROADCAST, 8086 SAS_PORT_BROADCAST_CHANGE, 8087 &mpt->m_phy_info[phy_num].smhba_info); 8088 break; 8089 case MPI2_EVENT_PRIMITIVE_SES: 8090 mptsas_smhba_log_sysevent(mpt, 8091 ESC_SAS_HBA_PORT_BROADCAST, 8092 SAS_PORT_BROADCAST_SES, 8093 &mpt->m_phy_info[phy_num].smhba_info); 8094 break; 8095 case MPI2_EVENT_PRIMITIVE_EXPANDER: 8096 mptsas_smhba_log_sysevent(mpt, 8097 ESC_SAS_HBA_PORT_BROADCAST, 8098 SAS_PORT_BROADCAST_D01_4, 8099 &mpt->m_phy_info[phy_num].smhba_info); 8100 break; 8101 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT: 8102 mptsas_smhba_log_sysevent(mpt, 8103 ESC_SAS_HBA_PORT_BROADCAST, 8104 SAS_PORT_BROADCAST_D04_7, 8105 &mpt->m_phy_info[phy_num].smhba_info); 8106 break; 8107 case MPI2_EVENT_PRIMITIVE_RESERVED3: 8108 mptsas_smhba_log_sysevent(mpt, 8109 ESC_SAS_HBA_PORT_BROADCAST, 8110 SAS_PORT_BROADCAST_D16_7, 8111 &mpt->m_phy_info[phy_num].smhba_info); 8112 break; 8113 case MPI2_EVENT_PRIMITIVE_RESERVED4: 8114 mptsas_smhba_log_sysevent(mpt, 8115 ESC_SAS_HBA_PORT_BROADCAST, 8116 SAS_PORT_BROADCAST_D29_7, 8117 &mpt->m_phy_info[phy_num].smhba_info); 8118 break; 8119 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED: 8120 mptsas_smhba_log_sysevent(mpt, 8121 ESC_SAS_HBA_PORT_BROADCAST, 8122 SAS_PORT_BROADCAST_D24_0, 8123 &mpt->m_phy_info[phy_num].smhba_info); 8124 break; 8125 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED: 8126 mptsas_smhba_log_sysevent(mpt, 8127 ESC_SAS_HBA_PORT_BROADCAST, 8128 SAS_PORT_BROADCAST_D27_4, 8129 &mpt->m_phy_info[phy_num].smhba_info); 8130 break; 8131 default: 8132 NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE" 8133 " %x received", 8134 mpt->m_instance, primitive)); 8135 break; 8136 } 8137 NDBG16(("mptsas%d sas broadcast primitive: " 8138 "\tprimitive(0x%04x), phy(%d) complete\n", 8139 mpt->m_instance, primitive, phy_num)); 8140 break; 8141 } 8142 case MPI2_EVENT_IR_VOLUME: 8143 { 8144 Mpi2EventDataIrVolume_t *irVolume; 8145 uint16_t devhandle; 8146 uint32_t state; 8147 int config, vol; 8148 uint8_t found = FALSE; 8149 8150 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData; 8151 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8152 &irVolume->NewValue); 8153 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8154 &irVolume->VolDevHandle); 8155 8156 NDBG20(("EVENT_IR_VOLUME event is received")); 8157 8158 /* 8159 * Get latest RAID info and then find the DevHandle for this 8160 * event in the configuration. If the DevHandle is not found 8161 * just exit the event. 8162 */ 8163 (void) mptsas_get_raid_info(mpt); 8164 for (config = 0; (config < mpt->m_num_raid_configs) && 8165 (!found); config++) { 8166 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 8167 if (mpt->m_raidconfig[config].m_raidvol[vol]. 8168 m_raidhandle == devhandle) { 8169 found = TRUE; 8170 break; 8171 } 8172 } 8173 } 8174 if (!found) { 8175 break; 8176 } 8177 8178 switch (irVolume->ReasonCode) { 8179 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED: 8180 { 8181 uint32_t i; 8182 mpt->m_raidconfig[config].m_raidvol[vol].m_settings = 8183 state; 8184 8185 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING; 8186 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed" 8187 ", auto-config of hot-swap drives is %s" 8188 ", write caching is %s" 8189 ", hot-spare pool mask is %02x\n", 8190 vol, state & 8191 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE 8192 ? "disabled" : "enabled", 8193 i == MPI2_RAIDVOL0_SETTING_UNCHANGED 8194 ? "controlled by member disks" : 8195 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING 8196 ? "disabled" : 8197 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING 8198 ? "enabled" : 8199 "incorrectly set", 8200 (state >> 16) & 0xff); 8201 break; 8202 } 8203 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED: 8204 { 8205 mpt->m_raidconfig[config].m_raidvol[vol].m_state = 8206 (uint8_t)state; 8207 8208 mptsas_log(mpt, CE_NOTE, 8209 "Volume %d is now %s\n", vol, 8210 state == MPI2_RAID_VOL_STATE_OPTIMAL 8211 ? "optimal" : 8212 state == MPI2_RAID_VOL_STATE_DEGRADED 8213 ? "degraded" : 8214 state == MPI2_RAID_VOL_STATE_ONLINE 8215 ? "online" : 8216 state == MPI2_RAID_VOL_STATE_INITIALIZING 8217 ? "initializing" : 8218 state == MPI2_RAID_VOL_STATE_FAILED 8219 ? "failed" : 8220 state == MPI2_RAID_VOL_STATE_MISSING 8221 ? "missing" : 8222 "state unknown"); 8223 break; 8224 } 8225 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED: 8226 { 8227 mpt->m_raidconfig[config].m_raidvol[vol]. 8228 m_statusflags = state; 8229 8230 mptsas_log(mpt, CE_NOTE, 8231 " Volume %d is now %s%s%s%s%s%s%s%s%s\n", 8232 vol, 8233 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED 8234 ? ", enabled" : ", disabled", 8235 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED 8236 ? ", quiesced" : "", 8237 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 8238 ? ", inactive" : ", active", 8239 state & 8240 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL 8241 ? ", bad block table is full" : "", 8242 state & 8243 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 8244 ? ", resync in progress" : "", 8245 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT 8246 ? ", background initialization in progress" : "", 8247 state & 8248 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION 8249 ? ", capacity expansion in progress" : "", 8250 state & 8251 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK 8252 ? ", consistency check in progress" : "", 8253 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB 8254 ? ", data scrub in progress" : ""); 8255 break; 8256 } 8257 default: 8258 break; 8259 } 8260 break; 8261 } 8262 case MPI2_EVENT_IR_PHYSICAL_DISK: 8263 { 8264 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk; 8265 uint16_t devhandle, enchandle, slot; 8266 uint32_t status, state; 8267 uint8_t physdisknum, reason; 8268 8269 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *) 8270 eventreply->EventData; 8271 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl, 8272 &irPhysDisk->PhysDiskNum); 8273 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8274 &irPhysDisk->PhysDiskDevHandle); 8275 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8276 &irPhysDisk->EnclosureHandle); 8277 slot = ddi_get16(mpt->m_acc_reply_frame_hdl, 8278 &irPhysDisk->Slot); 8279 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8280 &irPhysDisk->NewValue); 8281 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 8282 &irPhysDisk->ReasonCode); 8283 8284 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received")); 8285 8286 switch (reason) { 8287 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED: 8288 mptsas_log(mpt, CE_NOTE, 8289 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8290 "for enclosure with handle 0x%x is now in hot " 8291 "spare pool %d", 8292 physdisknum, devhandle, slot, enchandle, 8293 (state >> 16) & 0xff); 8294 break; 8295 8296 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED: 8297 status = state; 8298 mptsas_log(mpt, CE_NOTE, 8299 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8300 "for enclosure with handle 0x%x is now " 8301 "%s%s%s%s%s\n", physdisknum, devhandle, slot, 8302 enchandle, 8303 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME 8304 ? ", inactive" : ", active", 8305 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 8306 ? ", out of sync" : "", 8307 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED 8308 ? ", quiesced" : "", 8309 status & 8310 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED 8311 ? ", write cache enabled" : "", 8312 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET 8313 ? ", capacity expansion target" : ""); 8314 break; 8315 8316 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED: 8317 mptsas_log(mpt, CE_NOTE, 8318 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8319 "for enclosure with handle 0x%x is now %s\n", 8320 physdisknum, devhandle, slot, enchandle, 8321 state == MPI2_RAID_PD_STATE_OPTIMAL 8322 ? "optimal" : 8323 state == MPI2_RAID_PD_STATE_REBUILDING 8324 ? "rebuilding" : 8325 state == MPI2_RAID_PD_STATE_DEGRADED 8326 ? "degraded" : 8327 state == MPI2_RAID_PD_STATE_HOT_SPARE 8328 ? "a hot spare" : 8329 state == MPI2_RAID_PD_STATE_ONLINE 8330 ? "online" : 8331 state == MPI2_RAID_PD_STATE_OFFLINE 8332 ? "offline" : 8333 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE 8334 ? "not compatible" : 8335 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED 8336 ? "not configured" : 8337 "state unknown"); 8338 break; 8339 } 8340 break; 8341 } 8342 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 8343 { 8344 pMpi26EventDataActiveCableExcept_t actcable; 8345 uint32_t power; 8346 uint8_t reason, id; 8347 8348 actcable = (pMpi26EventDataActiveCableExcept_t) 8349 eventreply->EventData; 8350 power = ddi_get32(mpt->m_acc_reply_frame_hdl, 8351 &actcable->ActiveCablePowerRequirement); 8352 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 8353 &actcable->ReasonCode); 8354 id = ddi_get8(mpt->m_acc_reply_frame_hdl, 8355 &actcable->ReceptacleID); 8356 8357 /* 8358 * It'd be nice if this weren't just logging to the system but 8359 * were telling FMA about the active cable problem and FMA was 8360 * aware of the cable topology and state. 8361 */ 8362 switch (reason) { 8363 case MPI26_EVENT_ACTIVE_CABLE_PRESENT: 8364 /* Don't log anything if it's fine */ 8365 break; 8366 case MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER: 8367 mptsas_log(mpt, CE_WARN, "An active cable (id %u) does " 8368 "not have sufficient power to be enabled. " 8369 "Devices connected to this cable will not be " 8370 "visible to the system.", id); 8371 if (power == UINT32_MAX) { 8372 mptsas_log(mpt, CE_CONT, "The cable's power " 8373 "requirements are unknown.\n"); 8374 } else { 8375 mptsas_log(mpt, CE_CONT, "The cable requires " 8376 "%u mW of power to function.\n", power); 8377 } 8378 break; 8379 case MPI26_EVENT_ACTIVE_CABLE_DEGRADED: 8380 mptsas_log(mpt, CE_WARN, "An active cable (id %u) is " 8381 "degraded and not running at its full speed. " 8382 "Some devices might not appear.", id); 8383 break; 8384 default: 8385 break; 8386 } 8387 break; 8388 } 8389 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: 8390 case MPI2_EVENT_PCIE_ENUMERATION: 8391 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 8392 case MPI2_EVENT_PCIE_LINK_COUNTER: 8393 mptsas_log(mpt, CE_NOTE, "Unhandled mpt_sas PCIe device " 8394 "event received (0x%x)", event); 8395 break; 8396 default: 8397 NDBG20(("mptsas%d: unknown event %x received", 8398 mpt->m_instance, event)); 8399 break; 8400 } 8401 8402 /* 8403 * Return the reply frame to the free queue. 8404 */ 8405 ddi_put32(mpt->m_acc_free_queue_hdl, 8406 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm); 8407 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 8408 DDI_DMA_SYNC_FORDEV); 8409 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 8410 mpt->m_free_index = 0; 8411 } 8412 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 8413 mpt->m_free_index); 8414 mutex_exit(&mpt->m_mutex); 8415 } 8416 8417 /* 8418 * invoked from timeout() to restart qfull cmds with throttle == 0 8419 */ 8420 static void 8421 mptsas_restart_cmd(void *arg) 8422 { 8423 mptsas_t *mpt = arg; 8424 mptsas_target_t *ptgt = NULL; 8425 8426 mutex_enter(&mpt->m_mutex); 8427 8428 mpt->m_restart_cmd_timeid = 0; 8429 8430 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 8431 ptgt = refhash_next(mpt->m_targets, ptgt)) { 8432 if (ptgt->m_reset_delay == 0) { 8433 if (ptgt->m_t_throttle == QFULL_THROTTLE) { 8434 mptsas_set_throttle(mpt, ptgt, 8435 MAX_THROTTLE); 8436 } 8437 } 8438 } 8439 mptsas_restart_hba(mpt); 8440 mutex_exit(&mpt->m_mutex); 8441 } 8442 8443 void 8444 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8445 { 8446 int slot; 8447 mptsas_slots_t *slots = mpt->m_active; 8448 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8449 8450 ASSERT(cmd != NULL); 8451 ASSERT(cmd->cmd_queued == FALSE); 8452 8453 /* 8454 * Task Management cmds are removed in their own routines. Also, 8455 * we don't want to modify timeout based on TM cmds. 8456 */ 8457 if (cmd->cmd_flags & CFLAG_TM_CMD) { 8458 return; 8459 } 8460 8461 slot = cmd->cmd_slot; 8462 8463 /* 8464 * remove the cmd. 8465 */ 8466 if (cmd == slots->m_slot[slot]) { 8467 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags " 8468 "0x%x", (void *)cmd, cmd->cmd_flags)); 8469 slots->m_slot[slot] = NULL; 8470 mpt->m_ncmds--; 8471 8472 /* 8473 * only decrement per target ncmds if command 8474 * has a target associated with it. 8475 */ 8476 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 8477 ptgt->m_t_ncmds--; 8478 /* 8479 * reset throttle if we just ran an untagged command 8480 * to a tagged target 8481 */ 8482 if ((ptgt->m_t_ncmds == 0) && 8483 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) { 8484 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8485 } 8486 8487 /* 8488 * Remove this command from the active queue. 8489 */ 8490 if (cmd->cmd_active_expiration != 0) { 8491 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd, 8492 cmd_active_link); 8493 cmd->cmd_active_expiration = 0; 8494 } 8495 } 8496 } 8497 8498 /* 8499 * This is all we need to do for ioc commands. 8500 */ 8501 if (cmd->cmd_flags & CFLAG_CMDIOC) { 8502 mptsas_return_to_pool(mpt, cmd); 8503 return; 8504 } 8505 8506 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]); 8507 } 8508 8509 /* 8510 * accept all cmds on the tx_waitq if any and then 8511 * start a fresh request from the top of the device queue. 8512 * 8513 * since there are always cmds queued on the tx_waitq, and rare cmds on 8514 * the instance waitq, so this function should not be invoked in the ISR, 8515 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the 8516 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU. 8517 */ 8518 static void 8519 mptsas_restart_hba(mptsas_t *mpt) 8520 { 8521 ASSERT(mutex_owned(&mpt->m_mutex)); 8522 8523 mutex_enter(&mpt->m_tx_waitq_mutex); 8524 if (mpt->m_tx_waitq) { 8525 mptsas_accept_tx_waitq(mpt); 8526 } 8527 mutex_exit(&mpt->m_tx_waitq_mutex); 8528 mptsas_restart_waitq(mpt); 8529 } 8530 8531 /* 8532 * start a fresh request from the top of the device queue 8533 */ 8534 static void 8535 mptsas_restart_waitq(mptsas_t *mpt) 8536 { 8537 mptsas_cmd_t *cmd, *next_cmd; 8538 mptsas_target_t *ptgt = NULL; 8539 8540 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt)); 8541 8542 ASSERT(mutex_owned(&mpt->m_mutex)); 8543 8544 /* 8545 * If there is a reset delay, don't start any cmds. Otherwise, start 8546 * as many cmds as possible. 8547 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 8548 * commands is m_max_requests - 2. 8549 */ 8550 cmd = mpt->m_waitq; 8551 8552 while (cmd != NULL) { 8553 next_cmd = cmd->cmd_linkp; 8554 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 8555 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8556 /* 8557 * passthru command get slot need 8558 * set CFLAG_PREPARED. 8559 */ 8560 cmd->cmd_flags |= CFLAG_PREPARED; 8561 mptsas_waitq_delete(mpt, cmd); 8562 mptsas_start_passthru(mpt, cmd); 8563 } 8564 cmd = next_cmd; 8565 continue; 8566 } 8567 if (cmd->cmd_flags & CFLAG_CONFIG) { 8568 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8569 /* 8570 * Send the config page request and delete it 8571 * from the waitq. 8572 */ 8573 cmd->cmd_flags |= CFLAG_PREPARED; 8574 mptsas_waitq_delete(mpt, cmd); 8575 mptsas_start_config_page_access(mpt, cmd); 8576 } 8577 cmd = next_cmd; 8578 continue; 8579 } 8580 if (cmd->cmd_flags & CFLAG_FW_DIAG) { 8581 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8582 /* 8583 * Send the FW Diag request and delete if from 8584 * the waitq. 8585 */ 8586 cmd->cmd_flags |= CFLAG_PREPARED; 8587 mptsas_waitq_delete(mpt, cmd); 8588 mptsas_start_diag(mpt, cmd); 8589 } 8590 cmd = next_cmd; 8591 continue; 8592 } 8593 8594 ptgt = cmd->cmd_tgt_addr; 8595 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) && 8596 (ptgt->m_t_ncmds == 0)) { 8597 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8598 } 8599 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 8600 (ptgt && (ptgt->m_reset_delay == 0)) && 8601 (ptgt && (ptgt->m_t_ncmds < 8602 ptgt->m_t_throttle))) { 8603 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8604 mptsas_waitq_delete(mpt, cmd); 8605 (void) mptsas_start_cmd(mpt, cmd); 8606 } 8607 } 8608 cmd = next_cmd; 8609 } 8610 } 8611 /* 8612 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait). 8613 * Accept all those queued cmds before new cmd is accept so that the 8614 * cmds are sent in order. 8615 */ 8616 static void 8617 mptsas_accept_tx_waitq(mptsas_t *mpt) 8618 { 8619 mptsas_cmd_t *cmd; 8620 8621 ASSERT(mutex_owned(&mpt->m_mutex)); 8622 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex)); 8623 8624 /* 8625 * A Bus Reset could occur at any time and flush the tx_waitq, 8626 * so we cannot count on the tx_waitq to contain even one cmd. 8627 * And when the m_tx_waitq_mutex is released and run 8628 * mptsas_accept_pkt(), the tx_waitq may be flushed. 8629 */ 8630 cmd = mpt->m_tx_waitq; 8631 for (;;) { 8632 if ((cmd = mpt->m_tx_waitq) == NULL) { 8633 mpt->m_tx_draining = 0; 8634 break; 8635 } 8636 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) { 8637 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 8638 } 8639 cmd->cmd_linkp = NULL; 8640 mutex_exit(&mpt->m_tx_waitq_mutex); 8641 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT) 8642 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed " 8643 "to accept cmd on queue\n"); 8644 mutex_enter(&mpt->m_tx_waitq_mutex); 8645 } 8646 } 8647 8648 8649 /* 8650 * mpt tag type lookup 8651 */ 8652 static char mptsas_tag_lookup[] = 8653 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG}; 8654 8655 static int 8656 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8657 { 8658 struct scsi_pkt *pkt = CMD2PKT(cmd); 8659 uint32_t control = 0; 8660 caddr_t mem, arsbuf; 8661 pMpi2SCSIIORequest_t io_request; 8662 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 8663 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 8664 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8665 uint16_t SMID, io_flags = 0; 8666 uint8_t ars_size; 8667 uint64_t request_desc; 8668 uint32_t ars_dmaaddrlow; 8669 mptsas_cmd_t *c; 8670 8671 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd, 8672 cmd->cmd_flags)); 8673 8674 /* 8675 * Set SMID and increment index. Rollover to 1 instead of 0 if index 8676 * is at the max. 0 is an invalid SMID, so we call the first index 1. 8677 */ 8678 SMID = cmd->cmd_slot; 8679 8680 /* 8681 * It is possible for back to back device reset to 8682 * happen before the reset delay has expired. That's 8683 * ok, just let the device reset go out on the bus. 8684 */ 8685 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8686 ASSERT(ptgt->m_reset_delay == 0); 8687 } 8688 8689 /* 8690 * if a non-tagged cmd is submitted to an active tagged target 8691 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 8692 * to be untagged 8693 */ 8694 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 8695 (ptgt->m_t_ncmds > 1) && 8696 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 8697 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 8698 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8699 NDBG23(("target=%d, untagged cmd, start draining\n", 8700 ptgt->m_devhdl)); 8701 8702 if (ptgt->m_reset_delay == 0) { 8703 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 8704 } 8705 8706 mptsas_remove_cmd(mpt, cmd); 8707 cmd->cmd_pkt_flags |= FLAG_HEAD; 8708 mptsas_waitq_add(mpt, cmd); 8709 } 8710 return (DDI_FAILURE); 8711 } 8712 8713 /* 8714 * Set correct tag bits. 8715 */ 8716 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 8717 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 8718 FLAG_TAGMASK) >> 12)]) { 8719 case MSG_SIMPLE_QTAG: 8720 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8721 break; 8722 case MSG_HEAD_QTAG: 8723 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 8724 break; 8725 case MSG_ORDERED_QTAG: 8726 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 8727 break; 8728 default: 8729 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 8730 break; 8731 } 8732 } else { 8733 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 8734 ptgt->m_t_throttle = 1; 8735 } 8736 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8737 } 8738 8739 if (cmd->cmd_pkt_flags & FLAG_TLR) { 8740 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 8741 } 8742 8743 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 8744 io_request = (pMpi2SCSIIORequest_t)mem; 8745 if (cmd->cmd_extrqslen != 0) { 8746 /* 8747 * Mapping of the buffer was done in mptsas_pkt_alloc_extern(). 8748 * Calculate the DMA address with the same offset. 8749 */ 8750 arsbuf = cmd->cmd_arq_buf; 8751 ars_size = cmd->cmd_extrqslen; 8752 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8753 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 8754 0xffffffffu; 8755 } else { 8756 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1)); 8757 cmd->cmd_arq_buf = arsbuf; 8758 ars_size = mpt->m_req_sense_size; 8759 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8760 (mpt->m_req_sense_size * (SMID-1))) & 8761 0xffffffffu; 8762 } 8763 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 8764 bzero(arsbuf, ars_size); 8765 8766 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 8767 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 8768 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 8769 MPI2_FUNCTION_SCSI_IO_REQUEST); 8770 8771 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 8772 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 8773 8774 io_flags = cmd->cmd_cdblen; 8775 if (mptsas_use_fastpath && 8776 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) { 8777 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH; 8778 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 8779 } else { 8780 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 8781 } 8782 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 8783 /* 8784 * setup the Scatter/Gather DMA list for this request 8785 */ 8786 if (cmd->cmd_cookiec > 0) { 8787 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 8788 } else { 8789 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 8790 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 8791 MPI2_SGE_FLAGS_END_OF_BUFFER | 8792 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 8793 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 8794 } 8795 8796 /* 8797 * save ARQ information 8798 */ 8799 ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size); 8800 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow); 8801 8802 ddi_put32(acc_hdl, &io_request->Control, control); 8803 8804 NDBG31(("starting message=%d(0x%p), with cmd=0x%p", 8805 SMID, (void *)io_request, (void *)cmd)); 8806 8807 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 8808 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 8809 DDI_DMA_SYNC_FORDEV); 8810 8811 /* 8812 * Build request descriptor and write it to the request desc post reg. 8813 */ 8814 request_desc |= (SMID << 16); 8815 request_desc |= (uint64_t)ptgt->m_devhdl << 48; 8816 MPTSAS_START_CMD(mpt, request_desc); 8817 8818 /* 8819 * Start timeout. 8820 */ 8821 cmd->cmd_active_expiration = 8822 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC; 8823 #ifdef MPTSAS_TEST 8824 /* 8825 * Force timeouts to happen immediately. 8826 */ 8827 if (mptsas_test_timeouts) 8828 cmd->cmd_active_expiration = gethrtime(); 8829 #endif 8830 c = TAILQ_FIRST(&ptgt->m_active_cmdq); 8831 if (c == NULL || 8832 c->cmd_active_expiration < cmd->cmd_active_expiration) { 8833 /* 8834 * Common case is that this is the last pending expiration 8835 * (or queue is empty). Insert at head of the queue. 8836 */ 8837 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link); 8838 } else { 8839 /* 8840 * Queue is not empty and first element expires later than 8841 * this command. Search for element expiring sooner. 8842 */ 8843 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) { 8844 if (c->cmd_active_expiration < 8845 cmd->cmd_active_expiration) { 8846 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link); 8847 break; 8848 } 8849 } 8850 if (c == NULL) { 8851 /* 8852 * No element found expiring sooner, append to 8853 * non-empty queue. 8854 */ 8855 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd, 8856 cmd_active_link); 8857 } 8858 } 8859 8860 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 8861 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 8862 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8863 return (DDI_FAILURE); 8864 } 8865 return (DDI_SUCCESS); 8866 } 8867 8868 /* 8869 * Select a helper thread to handle current doneq 8870 */ 8871 static void 8872 mptsas_deliver_doneq_thread(mptsas_t *mpt) 8873 { 8874 uint64_t t, i; 8875 uint32_t min = 0xffffffff; 8876 mptsas_doneq_thread_list_t *item; 8877 8878 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 8879 item = &mpt->m_doneq_thread_id[i]; 8880 /* 8881 * If the completed command on help thread[i] less than 8882 * doneq_thread_threshold, then pick the thread[i]. Otherwise 8883 * pick a thread which has least completed command. 8884 */ 8885 8886 mutex_enter(&item->mutex); 8887 if (item->len < mpt->m_doneq_thread_threshold) { 8888 t = i; 8889 mutex_exit(&item->mutex); 8890 break; 8891 } 8892 if (item->len < min) { 8893 min = item->len; 8894 t = i; 8895 } 8896 mutex_exit(&item->mutex); 8897 } 8898 mutex_enter(&mpt->m_doneq_thread_id[t].mutex); 8899 mptsas_doneq_mv(mpt, t); 8900 cv_signal(&mpt->m_doneq_thread_id[t].cv); 8901 mutex_exit(&mpt->m_doneq_thread_id[t].mutex); 8902 } 8903 8904 /* 8905 * move the current global doneq to the doneq of thead[t] 8906 */ 8907 static void 8908 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t) 8909 { 8910 mptsas_cmd_t *cmd; 8911 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8912 8913 ASSERT(mutex_owned(&item->mutex)); 8914 while ((cmd = mpt->m_doneq) != NULL) { 8915 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) { 8916 mpt->m_donetail = &mpt->m_doneq; 8917 } 8918 cmd->cmd_linkp = NULL; 8919 *item->donetail = cmd; 8920 item->donetail = &cmd->cmd_linkp; 8921 mpt->m_doneq_len--; 8922 item->len++; 8923 } 8924 } 8925 8926 void 8927 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd) 8928 { 8929 struct scsi_pkt *pkt = CMD2PKT(cmd); 8930 8931 /* Check all acc and dma handles */ 8932 if ((mptsas_check_acc_handle(mpt->m_datap) != 8933 DDI_SUCCESS) || 8934 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 8935 DDI_SUCCESS) || 8936 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 8937 DDI_SUCCESS) || 8938 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 8939 DDI_SUCCESS) || 8940 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 8941 DDI_SUCCESS) || 8942 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 8943 DDI_SUCCESS) || 8944 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 8945 DDI_SUCCESS) || 8946 (mptsas_check_acc_handle(mpt->m_config_handle) != 8947 DDI_SUCCESS)) { 8948 ddi_fm_service_impact(mpt->m_dip, 8949 DDI_SERVICE_UNAFFECTED); 8950 ddi_fm_acc_err_clear(mpt->m_config_handle, 8951 DDI_FME_VER0); 8952 pkt->pkt_reason = CMD_TRAN_ERR; 8953 pkt->pkt_statistics = 0; 8954 } 8955 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 8956 DDI_SUCCESS) || 8957 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 8958 DDI_SUCCESS) || 8959 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 8960 DDI_SUCCESS) || 8961 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 8962 DDI_SUCCESS) || 8963 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 8964 DDI_SUCCESS) || 8965 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 8966 DDI_SUCCESS)) { 8967 ddi_fm_service_impact(mpt->m_dip, 8968 DDI_SERVICE_UNAFFECTED); 8969 pkt->pkt_reason = CMD_TRAN_ERR; 8970 pkt->pkt_statistics = 0; 8971 } 8972 if (cmd->cmd_dmahandle && 8973 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 8974 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8975 pkt->pkt_reason = CMD_TRAN_ERR; 8976 pkt->pkt_statistics = 0; 8977 } 8978 if ((cmd->cmd_extra_frames && 8979 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 8980 DDI_SUCCESS) || 8981 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 8982 DDI_SUCCESS)))) { 8983 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8984 pkt->pkt_reason = CMD_TRAN_ERR; 8985 pkt->pkt_statistics = 0; 8986 } 8987 } 8988 8989 /* 8990 * These routines manipulate the queue of commands that 8991 * are waiting for their completion routines to be called. 8992 * The queue is usually in FIFO order but on an MP system 8993 * it's possible for the completion routines to get out 8994 * of order. If that's a problem you need to add a global 8995 * mutex around the code that calls the completion routine 8996 * in the interrupt handler. 8997 */ 8998 static void 8999 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 9000 { 9001 struct scsi_pkt *pkt = CMD2PKT(cmd); 9002 9003 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd)); 9004 9005 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0); 9006 cmd->cmd_linkp = NULL; 9007 cmd->cmd_flags |= CFLAG_FINISHED; 9008 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT; 9009 9010 mptsas_fma_check(mpt, cmd); 9011 9012 /* 9013 * only add scsi pkts that have completion routines to 9014 * the doneq. no intr cmds do not have callbacks. 9015 */ 9016 if (pkt && (pkt->pkt_comp)) { 9017 *mpt->m_donetail = cmd; 9018 mpt->m_donetail = &cmd->cmd_linkp; 9019 mpt->m_doneq_len++; 9020 } 9021 } 9022 9023 static mptsas_cmd_t * 9024 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t) 9025 { 9026 mptsas_cmd_t *cmd; 9027 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 9028 9029 /* pop one off the done queue */ 9030 if ((cmd = item->doneq) != NULL) { 9031 /* if the queue is now empty fix the tail pointer */ 9032 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd)); 9033 if ((item->doneq = cmd->cmd_linkp) == NULL) { 9034 item->donetail = &item->doneq; 9035 } 9036 cmd->cmd_linkp = NULL; 9037 item->len--; 9038 } 9039 return (cmd); 9040 } 9041 9042 static void 9043 mptsas_doneq_empty(mptsas_t *mpt) 9044 { 9045 if (mpt->m_doneq && !mpt->m_in_callback) { 9046 mptsas_cmd_t *cmd, *next; 9047 struct scsi_pkt *pkt; 9048 9049 mpt->m_in_callback = 1; 9050 cmd = mpt->m_doneq; 9051 mpt->m_doneq = NULL; 9052 mpt->m_donetail = &mpt->m_doneq; 9053 mpt->m_doneq_len = 0; 9054 9055 mutex_exit(&mpt->m_mutex); 9056 /* 9057 * run the completion routines of all the 9058 * completed commands 9059 */ 9060 while (cmd != NULL) { 9061 next = cmd->cmd_linkp; 9062 cmd->cmd_linkp = NULL; 9063 /* run this command's completion routine */ 9064 cmd->cmd_flags |= CFLAG_COMPLETED; 9065 pkt = CMD2PKT(cmd); 9066 mptsas_pkt_comp(pkt, cmd); 9067 cmd = next; 9068 } 9069 mutex_enter(&mpt->m_mutex); 9070 mpt->m_in_callback = 0; 9071 } 9072 } 9073 9074 /* 9075 * These routines manipulate the target's queue of pending requests 9076 */ 9077 void 9078 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 9079 { 9080 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd)); 9081 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 9082 cmd->cmd_queued = TRUE; 9083 if (ptgt) 9084 ptgt->m_t_nwait++; 9085 if (cmd->cmd_pkt_flags & FLAG_HEAD) { 9086 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) { 9087 mpt->m_waitqtail = &cmd->cmd_linkp; 9088 } 9089 mpt->m_waitq = cmd; 9090 } else { 9091 cmd->cmd_linkp = NULL; 9092 *(mpt->m_waitqtail) = cmd; 9093 mpt->m_waitqtail = &cmd->cmd_linkp; 9094 } 9095 } 9096 9097 static mptsas_cmd_t * 9098 mptsas_waitq_rm(mptsas_t *mpt) 9099 { 9100 mptsas_cmd_t *cmd; 9101 mptsas_target_t *ptgt; 9102 NDBG7(("mptsas_waitq_rm")); 9103 9104 MPTSAS_WAITQ_RM(mpt, cmd); 9105 9106 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd)); 9107 if (cmd) { 9108 ptgt = cmd->cmd_tgt_addr; 9109 if (ptgt) { 9110 ptgt->m_t_nwait--; 9111 ASSERT(ptgt->m_t_nwait >= 0); 9112 } 9113 } 9114 return (cmd); 9115 } 9116 9117 /* 9118 * remove specified cmd from the middle of the wait queue. 9119 */ 9120 static void 9121 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 9122 { 9123 mptsas_cmd_t *prevp = mpt->m_waitq; 9124 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 9125 9126 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9127 (void *)mpt, (void *)cmd)); 9128 if (ptgt) { 9129 ptgt->m_t_nwait--; 9130 ASSERT(ptgt->m_t_nwait >= 0); 9131 } 9132 9133 if (prevp == cmd) { 9134 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL) 9135 mpt->m_waitqtail = &mpt->m_waitq; 9136 9137 cmd->cmd_linkp = NULL; 9138 cmd->cmd_queued = FALSE; 9139 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9140 (void *)mpt, (void *)cmd)); 9141 return; 9142 } 9143 9144 while (prevp != NULL) { 9145 if (prevp->cmd_linkp == cmd) { 9146 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 9147 mpt->m_waitqtail = &prevp->cmd_linkp; 9148 9149 cmd->cmd_linkp = NULL; 9150 cmd->cmd_queued = FALSE; 9151 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9152 (void *)mpt, (void *)cmd)); 9153 return; 9154 } 9155 prevp = prevp->cmd_linkp; 9156 } 9157 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch"); 9158 } 9159 9160 static mptsas_cmd_t * 9161 mptsas_tx_waitq_rm(mptsas_t *mpt) 9162 { 9163 mptsas_cmd_t *cmd; 9164 NDBG7(("mptsas_tx_waitq_rm")); 9165 9166 MPTSAS_TX_WAITQ_RM(mpt, cmd); 9167 9168 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd)); 9169 9170 return (cmd); 9171 } 9172 9173 /* 9174 * remove specified cmd from the middle of the tx_waitq. 9175 */ 9176 static void 9177 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 9178 { 9179 mptsas_cmd_t *prevp = mpt->m_tx_waitq; 9180 9181 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9182 (void *)mpt, (void *)cmd)); 9183 9184 if (prevp == cmd) { 9185 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) 9186 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 9187 9188 cmd->cmd_linkp = NULL; 9189 cmd->cmd_queued = FALSE; 9190 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9191 (void *)mpt, (void *)cmd)); 9192 return; 9193 } 9194 9195 while (prevp != NULL) { 9196 if (prevp->cmd_linkp == cmd) { 9197 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 9198 mpt->m_tx_waitqtail = &prevp->cmd_linkp; 9199 9200 cmd->cmd_linkp = NULL; 9201 cmd->cmd_queued = FALSE; 9202 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9203 (void *)mpt, (void *)cmd)); 9204 return; 9205 } 9206 prevp = prevp->cmd_linkp; 9207 } 9208 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch"); 9209 } 9210 9211 /* 9212 * device and bus reset handling 9213 * 9214 * Notes: 9215 * - RESET_ALL: reset the controller 9216 * - RESET_TARGET: reset the target specified in scsi_address 9217 */ 9218 static int 9219 mptsas_scsi_reset(struct scsi_address *ap, int level) 9220 { 9221 mptsas_t *mpt = ADDR2MPT(ap); 9222 int rval; 9223 mptsas_tgt_private_t *tgt_private; 9224 mptsas_target_t *ptgt = NULL; 9225 9226 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private; 9227 ptgt = tgt_private->t_private; 9228 if (ptgt == NULL) { 9229 return (FALSE); 9230 } 9231 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl, 9232 level)); 9233 9234 mutex_enter(&mpt->m_mutex); 9235 /* 9236 * if we are not in panic set up a reset delay for this target 9237 */ 9238 if (!ddi_in_panic()) { 9239 mptsas_setup_bus_reset_delay(mpt); 9240 } else { 9241 drv_usecwait(mpt->m_scsi_reset_delay * 1000); 9242 } 9243 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl); 9244 mutex_exit(&mpt->m_mutex); 9245 9246 /* 9247 * The transport layer expect to only see TRUE and 9248 * FALSE. Therefore, we will adjust the return value 9249 * if mptsas_do_scsi_reset returns FAILED. 9250 */ 9251 if (rval == FAILED) 9252 rval = FALSE; 9253 return (rval); 9254 } 9255 9256 static int 9257 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl) 9258 { 9259 int rval = FALSE; 9260 uint8_t config, disk; 9261 9262 ASSERT(mutex_owned(&mpt->m_mutex)); 9263 9264 if (mptsas_debug_resets) { 9265 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d", 9266 devhdl); 9267 } 9268 9269 /* 9270 * Issue a Target Reset message to the target specified but not to a 9271 * disk making up a raid volume. Just look through the RAID config 9272 * Phys Disk list of DevHandles. If the target's DevHandle is in this 9273 * list, then don't reset this target. 9274 */ 9275 for (config = 0; config < mpt->m_num_raid_configs; config++) { 9276 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 9277 if (devhdl == mpt->m_raidconfig[config]. 9278 m_physdisk_devhdl[disk]) { 9279 return (TRUE); 9280 } 9281 } 9282 } 9283 9284 rval = mptsas_ioc_task_management(mpt, 9285 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0); 9286 9287 mptsas_doneq_empty(mpt); 9288 return (rval); 9289 } 9290 9291 static int 9292 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 9293 void (*callback)(caddr_t), caddr_t arg) 9294 { 9295 mptsas_t *mpt = ADDR2MPT(ap); 9296 9297 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target)); 9298 9299 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg, 9300 &mpt->m_mutex, &mpt->m_reset_notify_listf)); 9301 } 9302 9303 static int 9304 mptsas_get_name(struct scsi_device *sd, char *name, int len) 9305 { 9306 dev_info_t *lun_dip = NULL; 9307 9308 ASSERT(sd != NULL); 9309 ASSERT(name != NULL); 9310 lun_dip = sd->sd_dev; 9311 ASSERT(lun_dip != NULL); 9312 9313 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) { 9314 return (1); 9315 } else { 9316 return (0); 9317 } 9318 } 9319 9320 static int 9321 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len) 9322 { 9323 return (mptsas_get_name(sd, name, len)); 9324 } 9325 9326 void 9327 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what) 9328 { 9329 9330 NDBG25(("mptsas_set_throttle: throttle=%x", what)); 9331 9332 /* 9333 * if the bus is draining/quiesced, no changes to the throttles 9334 * are allowed. Not allowing change of throttles during draining 9335 * limits error recovery but will reduce draining time 9336 * 9337 * all throttles should have been set to HOLD_THROTTLE 9338 */ 9339 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) { 9340 return; 9341 } 9342 9343 if (what == HOLD_THROTTLE) { 9344 ptgt->m_t_throttle = HOLD_THROTTLE; 9345 } else if (ptgt->m_reset_delay == 0) { 9346 ptgt->m_t_throttle = what; 9347 } 9348 } 9349 9350 /* 9351 * Clean up from a device reset. 9352 * For the case of target reset, this function clears the waitq of all 9353 * commands for a particular target. For the case of abort task set, this 9354 * function clears the waitq of all commonds for a particular target/lun. 9355 */ 9356 static void 9357 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype) 9358 { 9359 mptsas_slots_t *slots = mpt->m_active; 9360 mptsas_cmd_t *cmd, *next_cmd; 9361 int slot; 9362 uchar_t reason; 9363 uint_t stat; 9364 hrtime_t timestamp; 9365 9366 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun)); 9367 9368 timestamp = gethrtime(); 9369 9370 /* 9371 * Make sure the I/O Controller has flushed all cmds 9372 * that are associated with this target for a target reset 9373 * and target/lun for abort task set. 9374 * Account for TM requests, which use the last SMID. 9375 */ 9376 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9377 if ((cmd = slots->m_slot[slot]) == NULL) 9378 continue; 9379 reason = CMD_RESET; 9380 stat = STAT_DEV_RESET; 9381 switch (tasktype) { 9382 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9383 if (Tgt(cmd) == target) { 9384 if (cmd->cmd_active_expiration <= timestamp) { 9385 /* 9386 * When timeout requested, propagate 9387 * proper reason and statistics to 9388 * target drivers. 9389 */ 9390 reason = CMD_TIMEOUT; 9391 stat |= STAT_TIMEOUT; 9392 } 9393 NDBG25(("mptsas_flush_target discovered non-" 9394 "NULL cmd in slot %d, tasktype 0x%x", slot, 9395 tasktype)); 9396 mptsas_dump_cmd(mpt, cmd); 9397 mptsas_remove_cmd(mpt, cmd); 9398 mptsas_set_pkt_reason(mpt, cmd, reason, stat); 9399 mptsas_doneq_add(mpt, cmd); 9400 } 9401 break; 9402 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9403 reason = CMD_ABORTED; 9404 stat = STAT_ABORTED; 9405 /*FALLTHROUGH*/ 9406 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9407 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9408 9409 NDBG25(("mptsas_flush_target discovered non-" 9410 "NULL cmd in slot %d, tasktype 0x%x", slot, 9411 tasktype)); 9412 mptsas_dump_cmd(mpt, cmd); 9413 mptsas_remove_cmd(mpt, cmd); 9414 mptsas_set_pkt_reason(mpt, cmd, reason, 9415 stat); 9416 mptsas_doneq_add(mpt, cmd); 9417 } 9418 break; 9419 default: 9420 break; 9421 } 9422 } 9423 9424 /* 9425 * Flush the waitq and tx_waitq of this target's cmds 9426 */ 9427 cmd = mpt->m_waitq; 9428 9429 reason = CMD_RESET; 9430 stat = STAT_DEV_RESET; 9431 9432 switch (tasktype) { 9433 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9434 while (cmd != NULL) { 9435 next_cmd = cmd->cmd_linkp; 9436 if (Tgt(cmd) == target) { 9437 mptsas_waitq_delete(mpt, cmd); 9438 mptsas_set_pkt_reason(mpt, cmd, 9439 reason, stat); 9440 mptsas_doneq_add(mpt, cmd); 9441 } 9442 cmd = next_cmd; 9443 } 9444 mutex_enter(&mpt->m_tx_waitq_mutex); 9445 cmd = mpt->m_tx_waitq; 9446 while (cmd != NULL) { 9447 next_cmd = cmd->cmd_linkp; 9448 if (Tgt(cmd) == target) { 9449 mptsas_tx_waitq_delete(mpt, cmd); 9450 mutex_exit(&mpt->m_tx_waitq_mutex); 9451 mptsas_set_pkt_reason(mpt, cmd, 9452 reason, stat); 9453 mptsas_doneq_add(mpt, cmd); 9454 mutex_enter(&mpt->m_tx_waitq_mutex); 9455 } 9456 cmd = next_cmd; 9457 } 9458 mutex_exit(&mpt->m_tx_waitq_mutex); 9459 break; 9460 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9461 reason = CMD_ABORTED; 9462 stat = STAT_ABORTED; 9463 /*FALLTHROUGH*/ 9464 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9465 while (cmd != NULL) { 9466 next_cmd = cmd->cmd_linkp; 9467 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9468 mptsas_waitq_delete(mpt, cmd); 9469 mptsas_set_pkt_reason(mpt, cmd, 9470 reason, stat); 9471 mptsas_doneq_add(mpt, cmd); 9472 } 9473 cmd = next_cmd; 9474 } 9475 mutex_enter(&mpt->m_tx_waitq_mutex); 9476 cmd = mpt->m_tx_waitq; 9477 while (cmd != NULL) { 9478 next_cmd = cmd->cmd_linkp; 9479 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9480 mptsas_tx_waitq_delete(mpt, cmd); 9481 mutex_exit(&mpt->m_tx_waitq_mutex); 9482 mptsas_set_pkt_reason(mpt, cmd, 9483 reason, stat); 9484 mptsas_doneq_add(mpt, cmd); 9485 mutex_enter(&mpt->m_tx_waitq_mutex); 9486 } 9487 cmd = next_cmd; 9488 } 9489 mutex_exit(&mpt->m_tx_waitq_mutex); 9490 break; 9491 default: 9492 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 9493 tasktype); 9494 break; 9495 } 9496 } 9497 9498 /* 9499 * Clean up hba state, abort all outstanding command and commands in waitq 9500 * reset timeout of all targets. 9501 */ 9502 static void 9503 mptsas_flush_hba(mptsas_t *mpt) 9504 { 9505 mptsas_slots_t *slots = mpt->m_active; 9506 mptsas_cmd_t *cmd; 9507 int slot; 9508 9509 NDBG25(("mptsas_flush_hba")); 9510 9511 /* 9512 * The I/O Controller should have already sent back 9513 * all commands via the scsi I/O reply frame. Make 9514 * sure all commands have been flushed. 9515 * Account for TM request, which use the last SMID. 9516 */ 9517 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9518 if ((cmd = slots->m_slot[slot]) == NULL) 9519 continue; 9520 9521 if (cmd->cmd_flags & CFLAG_CMDIOC) { 9522 /* 9523 * Need to make sure to tell everyone that might be 9524 * waiting on this command that it's going to fail. If 9525 * we get here, this command will never timeout because 9526 * the active command table is going to be re-allocated, 9527 * so there will be nothing to check against a time out. 9528 * Instead, mark the command as failed due to reset. 9529 */ 9530 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 9531 STAT_BUS_RESET); 9532 if ((cmd->cmd_flags & 9533 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 9534 cmd->cmd_flags |= CFLAG_FINISHED; 9535 cv_broadcast(&mpt->m_passthru_cv); 9536 cv_broadcast(&mpt->m_config_cv); 9537 cv_broadcast(&mpt->m_fw_diag_cv); 9538 } 9539 continue; 9540 } 9541 9542 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d", 9543 slot)); 9544 mptsas_dump_cmd(mpt, cmd); 9545 9546 mptsas_remove_cmd(mpt, cmd); 9547 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9548 mptsas_doneq_add(mpt, cmd); 9549 } 9550 9551 /* 9552 * Flush the waitq. 9553 */ 9554 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) { 9555 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9556 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9557 (cmd->cmd_flags & CFLAG_CONFIG) || 9558 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9559 cmd->cmd_flags |= CFLAG_FINISHED; 9560 cv_broadcast(&mpt->m_passthru_cv); 9561 cv_broadcast(&mpt->m_config_cv); 9562 cv_broadcast(&mpt->m_fw_diag_cv); 9563 } else { 9564 mptsas_doneq_add(mpt, cmd); 9565 } 9566 } 9567 9568 /* 9569 * Flush the tx_waitq 9570 */ 9571 mutex_enter(&mpt->m_tx_waitq_mutex); 9572 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) { 9573 mutex_exit(&mpt->m_tx_waitq_mutex); 9574 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9575 mptsas_doneq_add(mpt, cmd); 9576 mutex_enter(&mpt->m_tx_waitq_mutex); 9577 } 9578 mutex_exit(&mpt->m_tx_waitq_mutex); 9579 9580 /* 9581 * Drain the taskqs prior to reallocating resources. The thread 9582 * passing through here could be launched from either (dr) 9583 * or (event) taskqs so only wait on the 'other' queue since 9584 * waiting on 'this' queue is a deadlock condition. 9585 */ 9586 mutex_exit(&mpt->m_mutex); 9587 if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread)) 9588 ddi_taskq_wait(mpt->m_event_taskq); 9589 if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread)) 9590 ddi_taskq_wait(mpt->m_dr_taskq); 9591 9592 mutex_enter(&mpt->m_mutex); 9593 } 9594 9595 /* 9596 * set pkt_reason and OR in pkt_statistics flag 9597 */ 9598 static void 9599 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason, 9600 uint_t stat) 9601 { 9602 #ifndef __lock_lint 9603 _NOTE(ARGUNUSED(mpt)) 9604 #endif 9605 9606 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x", 9607 (void *)cmd, reason, stat)); 9608 9609 if (cmd) { 9610 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) { 9611 cmd->cmd_pkt->pkt_reason = reason; 9612 } 9613 cmd->cmd_pkt->pkt_statistics |= stat; 9614 } 9615 } 9616 9617 static void 9618 mptsas_start_watch_reset_delay() 9619 { 9620 NDBG22(("mptsas_start_watch_reset_delay")); 9621 9622 mutex_enter(&mptsas_global_mutex); 9623 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) { 9624 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL, 9625 drv_usectohz((clock_t) 9626 MPTSAS_WATCH_RESET_DELAY_TICK * 1000)); 9627 ASSERT(mptsas_reset_watch != NULL); 9628 } 9629 mutex_exit(&mptsas_global_mutex); 9630 } 9631 9632 static void 9633 mptsas_setup_bus_reset_delay(mptsas_t *mpt) 9634 { 9635 mptsas_target_t *ptgt = NULL; 9636 9637 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 9638 9639 NDBG22(("mptsas_setup_bus_reset_delay")); 9640 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9641 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9642 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9643 ptgt->m_reset_delay = mpt->m_scsi_reset_delay; 9644 } 9645 9646 mptsas_start_watch_reset_delay(); 9647 } 9648 9649 /* 9650 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every 9651 * mpt instance for active reset delays 9652 */ 9653 static void 9654 mptsas_watch_reset_delay(void *arg) 9655 { 9656 #ifndef __lock_lint 9657 _NOTE(ARGUNUSED(arg)) 9658 #endif 9659 9660 mptsas_t *mpt; 9661 int not_done = 0; 9662 9663 NDBG22(("mptsas_watch_reset_delay")); 9664 9665 mutex_enter(&mptsas_global_mutex); 9666 mptsas_reset_watch = 0; 9667 mutex_exit(&mptsas_global_mutex); 9668 rw_enter(&mptsas_global_rwlock, RW_READER); 9669 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) { 9670 if (mpt->m_tran == 0) { 9671 continue; 9672 } 9673 mutex_enter(&mpt->m_mutex); 9674 not_done += mptsas_watch_reset_delay_subr(mpt); 9675 mutex_exit(&mpt->m_mutex); 9676 } 9677 rw_exit(&mptsas_global_rwlock); 9678 9679 if (not_done) { 9680 mptsas_start_watch_reset_delay(); 9681 } 9682 } 9683 9684 static int 9685 mptsas_watch_reset_delay_subr(mptsas_t *mpt) 9686 { 9687 int done = 0; 9688 int restart = 0; 9689 mptsas_target_t *ptgt = NULL; 9690 9691 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt)); 9692 9693 ASSERT(mutex_owned(&mpt->m_mutex)); 9694 9695 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9696 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9697 if (ptgt->m_reset_delay != 0) { 9698 ptgt->m_reset_delay -= 9699 MPTSAS_WATCH_RESET_DELAY_TICK; 9700 if (ptgt->m_reset_delay <= 0) { 9701 ptgt->m_reset_delay = 0; 9702 mptsas_set_throttle(mpt, ptgt, 9703 MAX_THROTTLE); 9704 restart++; 9705 } else { 9706 done = -1; 9707 } 9708 } 9709 } 9710 9711 if (restart > 0) { 9712 mptsas_restart_hba(mpt); 9713 } 9714 return (done); 9715 } 9716 9717 #ifdef MPTSAS_TEST 9718 static void 9719 mptsas_test_reset(mptsas_t *mpt, int target) 9720 { 9721 mptsas_target_t *ptgt = NULL; 9722 9723 if (mptsas_rtest == target) { 9724 if (mptsas_do_scsi_reset(mpt, target) == TRUE) { 9725 mptsas_rtest = -1; 9726 } 9727 if (mptsas_rtest == -1) { 9728 NDBG22(("mptsas_test_reset success")); 9729 } 9730 } 9731 } 9732 #endif 9733 9734 /* 9735 * abort handling: 9736 * 9737 * Notes: 9738 * - if pkt is not NULL, abort just that command 9739 * - if pkt is NULL, abort all outstanding commands for target 9740 */ 9741 static int 9742 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 9743 { 9744 mptsas_t *mpt = ADDR2MPT(ap); 9745 int rval; 9746 mptsas_tgt_private_t *tgt_private; 9747 int target, lun; 9748 9749 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 9750 tran_tgt_private; 9751 ASSERT(tgt_private != NULL); 9752 target = tgt_private->t_private->m_devhdl; 9753 lun = tgt_private->t_lun; 9754 9755 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun)); 9756 9757 mutex_enter(&mpt->m_mutex); 9758 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt); 9759 mutex_exit(&mpt->m_mutex); 9760 return (rval); 9761 } 9762 9763 static int 9764 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt) 9765 { 9766 mptsas_cmd_t *sp = NULL; 9767 mptsas_slots_t *slots = mpt->m_active; 9768 int rval = FALSE; 9769 9770 ASSERT(mutex_owned(&mpt->m_mutex)); 9771 9772 /* 9773 * Abort the command pkt on the target/lun in ap. If pkt is 9774 * NULL, abort all outstanding commands on that target/lun. 9775 * If you can abort them, return 1, else return 0. 9776 * Each packet that's aborted should be sent back to the target 9777 * driver through the callback routine, with pkt_reason set to 9778 * CMD_ABORTED. 9779 * 9780 * abort cmd pkt on HBA hardware; clean out of outstanding 9781 * command lists, etc. 9782 */ 9783 if (pkt != NULL) { 9784 /* abort the specified packet */ 9785 sp = PKT2CMD(pkt); 9786 9787 if (sp->cmd_queued) { 9788 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted", 9789 (void *)sp)); 9790 mptsas_waitq_delete(mpt, sp); 9791 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED, 9792 STAT_ABORTED); 9793 mptsas_doneq_add(mpt, sp); 9794 rval = TRUE; 9795 goto done; 9796 } 9797 9798 /* 9799 * Have mpt firmware abort this command 9800 */ 9801 9802 if (slots->m_slot[sp->cmd_slot] != NULL) { 9803 rval = mptsas_ioc_task_management(mpt, 9804 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target, 9805 lun, NULL, 0, 0); 9806 9807 /* 9808 * The transport layer expects only TRUE and FALSE. 9809 * Therefore, if mptsas_ioc_task_management returns 9810 * FAILED we will return FALSE. 9811 */ 9812 if (rval == FAILED) 9813 rval = FALSE; 9814 goto done; 9815 } 9816 } 9817 9818 /* 9819 * If pkt is NULL then abort task set 9820 */ 9821 rval = mptsas_ioc_task_management(mpt, 9822 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0); 9823 9824 /* 9825 * The transport layer expects only TRUE and FALSE. 9826 * Therefore, if mptsas_ioc_task_management returns 9827 * FAILED we will return FALSE. 9828 */ 9829 if (rval == FAILED) 9830 rval = FALSE; 9831 9832 #ifdef MPTSAS_TEST 9833 if (rval && mptsas_test_stop) { 9834 debug_enter("mptsas_do_scsi_abort"); 9835 } 9836 #endif 9837 9838 done: 9839 mptsas_doneq_empty(mpt); 9840 return (rval); 9841 } 9842 9843 /* 9844 * capability handling: 9845 * (*tran_getcap). Get the capability named, and return its value. 9846 */ 9847 static int 9848 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly) 9849 { 9850 mptsas_t *mpt = ADDR2MPT(ap); 9851 int ckey; 9852 int rval = FALSE; 9853 9854 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x", 9855 ap->a_target, cap, tgtonly)); 9856 9857 mutex_enter(&mpt->m_mutex); 9858 9859 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9860 mutex_exit(&mpt->m_mutex); 9861 return (UNDEFINED); 9862 } 9863 9864 switch (ckey) { 9865 case SCSI_CAP_DMA_MAX: 9866 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer; 9867 break; 9868 case SCSI_CAP_ARQ: 9869 rval = TRUE; 9870 break; 9871 case SCSI_CAP_MSG_OUT: 9872 case SCSI_CAP_PARITY: 9873 case SCSI_CAP_UNTAGGED_QING: 9874 rval = TRUE; 9875 break; 9876 case SCSI_CAP_TAGGED_QING: 9877 rval = TRUE; 9878 break; 9879 case SCSI_CAP_RESET_NOTIFICATION: 9880 rval = TRUE; 9881 break; 9882 case SCSI_CAP_LINKED_CMDS: 9883 rval = FALSE; 9884 break; 9885 case SCSI_CAP_QFULL_RETRIES: 9886 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran-> 9887 tran_tgt_private))->t_private->m_qfull_retries; 9888 break; 9889 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9890 rval = drv_hztousec(((mptsas_tgt_private_t *) 9891 (ap->a_hba_tran->tran_tgt_private))-> 9892 t_private->m_qfull_retry_interval) / 1000; 9893 break; 9894 case SCSI_CAP_CDB_LEN: 9895 rval = CDB_GROUP4; 9896 break; 9897 case SCSI_CAP_INTERCONNECT_TYPE: 9898 rval = INTERCONNECT_SAS; 9899 break; 9900 case SCSI_CAP_TRAN_LAYER_RETRIES: 9901 if (mpt->m_ioc_capabilities & 9902 MPI2_IOCFACTS_CAPABILITY_TLR) 9903 rval = TRUE; 9904 else 9905 rval = FALSE; 9906 break; 9907 default: 9908 rval = UNDEFINED; 9909 break; 9910 } 9911 9912 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval)); 9913 9914 mutex_exit(&mpt->m_mutex); 9915 return (rval); 9916 } 9917 9918 /* 9919 * (*tran_setcap). Set the capability named to the value given. 9920 */ 9921 static int 9922 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly) 9923 { 9924 mptsas_t *mpt = ADDR2MPT(ap); 9925 int ckey; 9926 int rval = FALSE; 9927 9928 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x", 9929 ap->a_target, cap, value, tgtonly)); 9930 9931 if (!tgtonly) { 9932 return (rval); 9933 } 9934 9935 mutex_enter(&mpt->m_mutex); 9936 9937 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9938 mutex_exit(&mpt->m_mutex); 9939 return (UNDEFINED); 9940 } 9941 9942 switch (ckey) { 9943 case SCSI_CAP_DMA_MAX: 9944 case SCSI_CAP_MSG_OUT: 9945 case SCSI_CAP_PARITY: 9946 case SCSI_CAP_INITIATOR_ID: 9947 case SCSI_CAP_LINKED_CMDS: 9948 case SCSI_CAP_UNTAGGED_QING: 9949 case SCSI_CAP_RESET_NOTIFICATION: 9950 /* 9951 * None of these are settable via 9952 * the capability interface. 9953 */ 9954 break; 9955 case SCSI_CAP_ARQ: 9956 /* 9957 * We cannot turn off arq so return false if asked to 9958 */ 9959 if (value) { 9960 rval = TRUE; 9961 } else { 9962 rval = FALSE; 9963 } 9964 break; 9965 case SCSI_CAP_TAGGED_QING: 9966 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *) 9967 (ap->a_hba_tran->tran_tgt_private))->t_private, 9968 MAX_THROTTLE); 9969 rval = TRUE; 9970 break; 9971 case SCSI_CAP_QFULL_RETRIES: 9972 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9973 t_private->m_qfull_retries = (uchar_t)value; 9974 rval = TRUE; 9975 break; 9976 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9977 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9978 t_private->m_qfull_retry_interval = 9979 drv_usectohz(value * 1000); 9980 rval = TRUE; 9981 break; 9982 default: 9983 rval = UNDEFINED; 9984 break; 9985 } 9986 mutex_exit(&mpt->m_mutex); 9987 return (rval); 9988 } 9989 9990 /* 9991 * Utility routine for mptsas_ifsetcap/ifgetcap 9992 */ 9993 /*ARGSUSED*/ 9994 static int 9995 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp) 9996 { 9997 NDBG24(("mptsas_scsi_capchk: cap=%s", cap)); 9998 9999 if (!cap) 10000 return (FALSE); 10001 10002 *cidxp = scsi_hba_lookup_capstr(cap); 10003 return (TRUE); 10004 } 10005 10006 static int 10007 mptsas_alloc_active_slots(mptsas_t *mpt, int flag) 10008 { 10009 mptsas_slots_t *old_active = mpt->m_active; 10010 mptsas_slots_t *new_active; 10011 size_t size; 10012 10013 /* 10014 * if there are active commands, then we cannot 10015 * change size of active slots array. 10016 */ 10017 ASSERT(mpt->m_ncmds == 0); 10018 10019 size = MPTSAS_SLOTS_SIZE(mpt); 10020 new_active = kmem_zalloc(size, flag); 10021 if (new_active == NULL) { 10022 NDBG1(("new active alloc failed")); 10023 return (-1); 10024 } 10025 /* 10026 * Since SMID 0 is reserved and the TM slot is reserved, the 10027 * number of slots that can be used at any one time is 10028 * m_max_requests - 2. 10029 */ 10030 new_active->m_n_normal = (mpt->m_max_requests - 2); 10031 new_active->m_size = size; 10032 new_active->m_rotor = 1; 10033 if (old_active) 10034 mptsas_free_active_slots(mpt); 10035 mpt->m_active = new_active; 10036 10037 return (0); 10038 } 10039 10040 static void 10041 mptsas_free_active_slots(mptsas_t *mpt) 10042 { 10043 mptsas_slots_t *active = mpt->m_active; 10044 size_t size; 10045 10046 if (active == NULL) 10047 return; 10048 size = active->m_size; 10049 kmem_free(active, size); 10050 mpt->m_active = NULL; 10051 } 10052 10053 /* 10054 * Error logging, printing, and debug print routines. 10055 */ 10056 static char *mptsas_label = "mpt_sas"; 10057 10058 /*PRINTFLIKE3*/ 10059 void 10060 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...) 10061 { 10062 dev_info_t *dev; 10063 va_list ap; 10064 10065 if (mpt) { 10066 dev = mpt->m_dip; 10067 } else { 10068 dev = 0; 10069 } 10070 10071 mutex_enter(&mptsas_log_mutex); 10072 10073 va_start(ap, fmt); 10074 (void) vsprintf(mptsas_log_buf, fmt, ap); 10075 va_end(ap); 10076 10077 if (level == CE_CONT) { 10078 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf); 10079 } else { 10080 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf); 10081 } 10082 10083 mutex_exit(&mptsas_log_mutex); 10084 } 10085 10086 #ifdef MPTSAS_DEBUG 10087 /* 10088 * Use a circular buffer to log messages to private memory. 10089 * Increment idx atomically to minimize risk to miss lines. 10090 * It's fast and does not hold up the proceedings too much. 10091 */ 10092 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT; 10093 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN; 10094 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN]; 10095 static uint32_t mptsas_dbglog_idx = 0; 10096 10097 /*PRINTFLIKE1*/ 10098 void 10099 mptsas_debug_log(char *fmt, ...) 10100 { 10101 va_list ap; 10102 uint32_t idx; 10103 10104 idx = atomic_inc_32_nv(&mptsas_dbglog_idx) & 10105 (mptsas_dbglog_linecnt - 1); 10106 10107 va_start(ap, fmt); 10108 (void) vsnprintf(mptsas_dbglog_bufs[idx], 10109 mptsas_dbglog_linelen, fmt, ap); 10110 va_end(ap); 10111 } 10112 10113 /*PRINTFLIKE1*/ 10114 void 10115 mptsas_printf(char *fmt, ...) 10116 { 10117 dev_info_t *dev = 0; 10118 va_list ap; 10119 10120 mutex_enter(&mptsas_log_mutex); 10121 10122 va_start(ap, fmt); 10123 (void) vsprintf(mptsas_log_buf, fmt, ap); 10124 va_end(ap); 10125 10126 #ifdef PROM_PRINTF 10127 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf); 10128 #else 10129 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf); 10130 #endif 10131 mutex_exit(&mptsas_log_mutex); 10132 } 10133 #endif 10134 10135 /* 10136 * timeout handling 10137 */ 10138 static void 10139 mptsas_watch(void *arg) 10140 { 10141 #ifndef __lock_lint 10142 _NOTE(ARGUNUSED(arg)) 10143 #endif 10144 10145 mptsas_t *mpt; 10146 uint32_t doorbell; 10147 10148 NDBG30(("mptsas_watch")); 10149 10150 rw_enter(&mptsas_global_rwlock, RW_READER); 10151 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) { 10152 10153 mutex_enter(&mpt->m_mutex); 10154 10155 /* Skip device if not powered on */ 10156 if (mpt->m_options & MPTSAS_OPT_PM) { 10157 if (mpt->m_power_level == PM_LEVEL_D0) { 10158 (void) pm_busy_component(mpt->m_dip, 0); 10159 mpt->m_busy = 1; 10160 } else { 10161 mutex_exit(&mpt->m_mutex); 10162 continue; 10163 } 10164 } 10165 10166 /* 10167 * Check if controller is in a FAULT state. If so, reset it. 10168 */ 10169 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell); 10170 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 10171 doorbell &= MPI2_DOORBELL_DATA_MASK; 10172 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, " 10173 "code: %04x", doorbell); 10174 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 10175 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 10176 mptsas_log(mpt, CE_WARN, "Reset failed" 10177 "after fault was detected"); 10178 } 10179 } 10180 10181 /* 10182 * For now, always call mptsas_watchsubr. 10183 */ 10184 mptsas_watchsubr(mpt); 10185 10186 if (mpt->m_options & MPTSAS_OPT_PM) { 10187 mpt->m_busy = 0; 10188 (void) pm_idle_component(mpt->m_dip, 0); 10189 } 10190 10191 mutex_exit(&mpt->m_mutex); 10192 } 10193 rw_exit(&mptsas_global_rwlock); 10194 10195 mutex_enter(&mptsas_global_mutex); 10196 if (mptsas_timeouts_enabled) 10197 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 10198 mutex_exit(&mptsas_global_mutex); 10199 } 10200 10201 static void 10202 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp) 10203 { 10204 mptsas_cmd_t *cmd; 10205 10206 /* 10207 * If we were draining due to a qfull condition, 10208 * go back to full throttle. 10209 */ 10210 if ((ptgt->m_t_throttle < MAX_THROTTLE) && 10211 (ptgt->m_t_throttle > HOLD_THROTTLE) && 10212 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 10213 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10214 mptsas_restart_hba(mpt); 10215 } 10216 10217 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq); 10218 if (cmd == NULL) 10219 return; 10220 10221 if (cmd->cmd_active_expiration <= timestamp) { 10222 /* 10223 * Earliest command timeout expired. Drain throttle. 10224 */ 10225 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10226 10227 /* 10228 * Check for remaining commands. 10229 */ 10230 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq); 10231 if (cmd->cmd_active_expiration > timestamp) { 10232 /* 10233 * Wait for remaining commands to complete or 10234 * time out. 10235 */ 10236 NDBG23(("command timed out, pending drain")); 10237 return; 10238 } 10239 10240 /* 10241 * All command timeouts expired. 10242 */ 10243 mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds " 10244 "expired with %d commands on target %d lun %d.", 10245 cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds, 10246 ptgt->m_devhdl, Lun(cmd)); 10247 10248 mptsas_cmd_timeout(mpt, ptgt); 10249 } else if (cmd->cmd_active_expiration <= 10250 timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) { 10251 NDBG23(("pending timeout")); 10252 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10253 } 10254 } 10255 10256 static void 10257 mptsas_watchsubr(mptsas_t *mpt) 10258 { 10259 int i; 10260 mptsas_cmd_t *cmd; 10261 mptsas_target_t *ptgt = NULL; 10262 hrtime_t timestamp = gethrtime(); 10263 10264 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 10265 10266 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt)); 10267 10268 #ifdef MPTSAS_TEST 10269 if (mptsas_enable_untagged) { 10270 mptsas_test_untagged++; 10271 } 10272 #endif 10273 10274 /* 10275 * Check for commands stuck in active slot 10276 * Account for TM requests, which use the last SMID. 10277 */ 10278 for (i = 0; i <= mpt->m_active->m_n_normal; i++) { 10279 if ((cmd = mpt->m_active->m_slot[i]) != NULL) { 10280 if (cmd->cmd_active_expiration <= timestamp) { 10281 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 10282 /* 10283 * There seems to be a command stuck 10284 * in the active slot. Drain throttle. 10285 */ 10286 mptsas_set_throttle(mpt, 10287 cmd->cmd_tgt_addr, 10288 DRAIN_THROTTLE); 10289 } else if (cmd->cmd_flags & 10290 (CFLAG_PASSTHRU | CFLAG_CONFIG | 10291 CFLAG_FW_DIAG)) { 10292 /* 10293 * passthrough command timeout 10294 */ 10295 cmd->cmd_flags |= (CFLAG_FINISHED | 10296 CFLAG_TIMEOUT); 10297 cv_broadcast(&mpt->m_passthru_cv); 10298 cv_broadcast(&mpt->m_config_cv); 10299 cv_broadcast(&mpt->m_fw_diag_cv); 10300 } 10301 } 10302 } 10303 } 10304 10305 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10306 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10307 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10308 } 10309 10310 for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL; 10311 ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) { 10312 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10313 } 10314 } 10315 10316 /* 10317 * timeout recovery 10318 */ 10319 static void 10320 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt) 10321 { 10322 uint16_t devhdl; 10323 uint64_t sas_wwn; 10324 uint8_t phy; 10325 char wwn_str[MPTSAS_WWN_STRLEN]; 10326 10327 devhdl = ptgt->m_devhdl; 10328 sas_wwn = ptgt->m_addr.mta_wwn; 10329 phy = ptgt->m_phynum; 10330 if (sas_wwn == 0) { 10331 (void) sprintf(wwn_str, "p%x", phy); 10332 } else { 10333 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 10334 } 10335 10336 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl)); 10337 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for " 10338 "target %d %s, enclosure %u", devhdl, wwn_str, 10339 ptgt->m_enclosure); 10340 10341 /* 10342 * Abort all outstanding commands on the device. 10343 */ 10344 NDBG29(("mptsas_cmd_timeout: device reset")); 10345 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) { 10346 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout " 10347 "recovery failed!", devhdl); 10348 } 10349 } 10350 10351 /* 10352 * Device / Hotplug control 10353 */ 10354 static int 10355 mptsas_scsi_quiesce(dev_info_t *dip) 10356 { 10357 mptsas_t *mpt; 10358 scsi_hba_tran_t *tran; 10359 10360 tran = ddi_get_driver_private(dip); 10361 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10362 return (-1); 10363 10364 return (mptsas_quiesce_bus(mpt)); 10365 } 10366 10367 static int 10368 mptsas_scsi_unquiesce(dev_info_t *dip) 10369 { 10370 mptsas_t *mpt; 10371 scsi_hba_tran_t *tran; 10372 10373 tran = ddi_get_driver_private(dip); 10374 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10375 return (-1); 10376 10377 return (mptsas_unquiesce_bus(mpt)); 10378 } 10379 10380 static int 10381 mptsas_quiesce_bus(mptsas_t *mpt) 10382 { 10383 mptsas_target_t *ptgt = NULL; 10384 10385 NDBG28(("mptsas_quiesce_bus")); 10386 mutex_enter(&mpt->m_mutex); 10387 10388 /* Set all the throttles to zero */ 10389 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10390 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10391 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10392 } 10393 10394 /* If there are any outstanding commands in the queue */ 10395 if (mpt->m_ncmds) { 10396 mpt->m_softstate |= MPTSAS_SS_DRAINING; 10397 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10398 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000))); 10399 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) { 10400 /* 10401 * Quiesce has been interrupted 10402 */ 10403 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10404 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10405 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10406 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10407 } 10408 mptsas_restart_hba(mpt); 10409 if (mpt->m_quiesce_timeid != 0) { 10410 timeout_id_t tid = mpt->m_quiesce_timeid; 10411 mpt->m_quiesce_timeid = 0; 10412 mutex_exit(&mpt->m_mutex); 10413 (void) untimeout(tid); 10414 return (-1); 10415 } 10416 mutex_exit(&mpt->m_mutex); 10417 return (-1); 10418 } else { 10419 /* Bus has been quiesced */ 10420 ASSERT(mpt->m_quiesce_timeid == 0); 10421 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10422 mpt->m_softstate |= MPTSAS_SS_QUIESCED; 10423 mutex_exit(&mpt->m_mutex); 10424 return (0); 10425 } 10426 } 10427 /* Bus was not busy - QUIESCED */ 10428 mutex_exit(&mpt->m_mutex); 10429 10430 return (0); 10431 } 10432 10433 static int 10434 mptsas_unquiesce_bus(mptsas_t *mpt) 10435 { 10436 mptsas_target_t *ptgt = NULL; 10437 10438 NDBG28(("mptsas_unquiesce_bus")); 10439 mutex_enter(&mpt->m_mutex); 10440 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED; 10441 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10442 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10443 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10444 } 10445 mptsas_restart_hba(mpt); 10446 mutex_exit(&mpt->m_mutex); 10447 return (0); 10448 } 10449 10450 static void 10451 mptsas_ncmds_checkdrain(void *arg) 10452 { 10453 mptsas_t *mpt = arg; 10454 mptsas_target_t *ptgt = NULL; 10455 10456 mutex_enter(&mpt->m_mutex); 10457 if (mpt->m_softstate & MPTSAS_SS_DRAINING) { 10458 mpt->m_quiesce_timeid = 0; 10459 if (mpt->m_ncmds == 0) { 10460 /* Command queue has been drained */ 10461 cv_signal(&mpt->m_cv); 10462 } else { 10463 /* 10464 * The throttle may have been reset because 10465 * of a SCSI bus reset 10466 */ 10467 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10468 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10469 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10470 } 10471 10472 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10473 mpt, (MPTSAS_QUIESCE_TIMEOUT * 10474 drv_usectohz(1000000))); 10475 } 10476 } 10477 mutex_exit(&mpt->m_mutex); 10478 } 10479 10480 /*ARGSUSED*/ 10481 static void 10482 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 10483 { 10484 int i; 10485 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp; 10486 char buf[128]; 10487 10488 buf[0] = '\0'; 10489 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd, 10490 Tgt(cmd), Lun(cmd))); 10491 (void) sprintf(&buf[0], "\tcdb=["); 10492 for (i = 0; i < (int)cmd->cmd_cdblen; i++) { 10493 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++); 10494 } 10495 (void) sprintf(&buf[strlen(buf)], " ]"); 10496 NDBG25(("?%s\n", buf)); 10497 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n", 10498 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics, 10499 cmd->cmd_pkt->pkt_state)); 10500 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ? 10501 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags)); 10502 } 10503 10504 static void 10505 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10506 pMpi2SGESimple64_t sgep) 10507 { 10508 uint32_t sge_flags; 10509 uint32_t data_size, dataout_size; 10510 ddi_dma_cookie_t data_cookie; 10511 ddi_dma_cookie_t dataout_cookie; 10512 10513 data_size = pt->data_size; 10514 dataout_size = pt->dataout_size; 10515 data_cookie = pt->data_cookie; 10516 dataout_cookie = pt->dataout_cookie; 10517 10518 if (dataout_size) { 10519 sge_flags = dataout_size | 10520 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10521 MPI2_SGE_FLAGS_END_OF_BUFFER | 10522 MPI2_SGE_FLAGS_HOST_TO_IOC | 10523 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10524 MPI2_SGE_FLAGS_SHIFT); 10525 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags); 10526 ddi_put32(acc_hdl, &sgep->Address.Low, 10527 (uint32_t)(dataout_cookie.dmac_laddress & 10528 0xffffffffull)); 10529 ddi_put32(acc_hdl, &sgep->Address.High, 10530 (uint32_t)(dataout_cookie.dmac_laddress 10531 >> 32)); 10532 sgep++; 10533 } 10534 sge_flags = data_size; 10535 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10536 MPI2_SGE_FLAGS_LAST_ELEMENT | 10537 MPI2_SGE_FLAGS_END_OF_BUFFER | 10538 MPI2_SGE_FLAGS_END_OF_LIST | 10539 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10540 MPI2_SGE_FLAGS_SHIFT); 10541 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10542 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 10543 MPI2_SGE_FLAGS_SHIFT); 10544 } else { 10545 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 10546 MPI2_SGE_FLAGS_SHIFT); 10547 } 10548 ddi_put32(acc_hdl, &sgep->FlagsLength, 10549 sge_flags); 10550 ddi_put32(acc_hdl, &sgep->Address.Low, 10551 (uint32_t)(data_cookie.dmac_laddress & 10552 0xffffffffull)); 10553 ddi_put32(acc_hdl, &sgep->Address.High, 10554 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10555 } 10556 10557 static void 10558 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10559 pMpi2IeeeSgeSimple64_t ieeesgep) 10560 { 10561 uint8_t sge_flags; 10562 uint32_t data_size, dataout_size; 10563 ddi_dma_cookie_t data_cookie; 10564 ddi_dma_cookie_t dataout_cookie; 10565 10566 data_size = pt->data_size; 10567 dataout_size = pt->dataout_size; 10568 data_cookie = pt->data_cookie; 10569 dataout_cookie = pt->dataout_cookie; 10570 10571 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 10572 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 10573 if (dataout_size) { 10574 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size); 10575 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10576 (uint32_t)(dataout_cookie.dmac_laddress & 10577 0xffffffffull)); 10578 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10579 (uint32_t)(dataout_cookie.dmac_laddress >> 32)); 10580 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10581 ieeesgep++; 10582 } 10583 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 10584 ddi_put32(acc_hdl, &ieeesgep->Length, data_size); 10585 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10586 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull)); 10587 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10588 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10589 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10590 } 10591 10592 static void 10593 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd) 10594 { 10595 caddr_t memp; 10596 pMPI2RequestHeader_t request_hdrp; 10597 struct scsi_pkt *pkt = cmd->cmd_pkt; 10598 mptsas_pt_request_t *pt = pkt->pkt_ha_private; 10599 uint32_t request_size; 10600 uint32_t i; 10601 uint64_t request_desc = 0; 10602 uint8_t desc_type; 10603 uint16_t SMID; 10604 uint8_t *request, function; 10605 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 10606 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 10607 10608 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 10609 10610 request = pt->request; 10611 request_size = pt->request_size; 10612 10613 SMID = cmd->cmd_slot; 10614 10615 /* 10616 * Store the passthrough message in memory location 10617 * corresponding to our slot number 10618 */ 10619 memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 10620 request_hdrp = (pMPI2RequestHeader_t)memp; 10621 bzero(memp, mpt->m_req_frame_size); 10622 10623 for (i = 0; i < request_size; i++) { 10624 bcopy(request + i, memp + i, 1); 10625 } 10626 10627 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, " 10628 "size=%d, in %d, out %d, SMID %d", request_hdrp->Function, 10629 request_hdrp->MsgFlags, request_size, 10630 pt->data_size, pt->dataout_size, SMID)); 10631 10632 /* 10633 * Add an SGE, even if the length is zero. 10634 */ 10635 if (mpt->m_MPI25 && pt->simple == 0) { 10636 mptsas_passthru_ieee_sge(acc_hdl, pt, 10637 (pMpi2IeeeSgeSimple64_t) 10638 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10639 } else { 10640 mptsas_passthru_sge(acc_hdl, pt, 10641 (pMpi2SGESimple64_t) 10642 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10643 } 10644 10645 function = request_hdrp->Function; 10646 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 10647 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 10648 pMpi2SCSIIORequest_t scsi_io_req; 10649 caddr_t arsbuf; 10650 uint8_t ars_size; 10651 uint32_t ars_dmaaddrlow; 10652 10653 NDBG15(("mptsas_start_passthru: Is SCSI IO Req")); 10654 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp; 10655 10656 if (cmd->cmd_extrqslen != 0) { 10657 /* 10658 * Mapping of the buffer was done in 10659 * mptsas_do_passthru(). 10660 * Calculate the DMA address with the same offset. 10661 */ 10662 arsbuf = cmd->cmd_arq_buf; 10663 ars_size = cmd->cmd_extrqslen; 10664 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10665 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 10666 0xffffffffu; 10667 } else { 10668 arsbuf = mpt->m_req_sense + 10669 (mpt->m_req_sense_size * (SMID-1)); 10670 cmd->cmd_arq_buf = arsbuf; 10671 ars_size = mpt->m_req_sense_size; 10672 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10673 (mpt->m_req_sense_size * (SMID-1))) & 10674 0xffffffffu; 10675 } 10676 bzero(arsbuf, ars_size); 10677 10678 ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size); 10679 ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress, 10680 ars_dmaaddrlow); 10681 10682 /* 10683 * Put SGE for data and data_out buffer at the end of 10684 * scsi_io_request message header.(64 bytes in total) 10685 * Set SGLOffset0 value 10686 */ 10687 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0, 10688 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4); 10689 10690 /* 10691 * Setup descriptor info. RAID passthrough must use the 10692 * default request descriptor which is already set, so if this 10693 * is a SCSI IO request, change the descriptor to SCSI IO. 10694 */ 10695 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 10696 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 10697 request_desc = ((uint64_t)ddi_get16(acc_hdl, 10698 &scsi_io_req->DevHandle) << 48); 10699 } 10700 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 10701 DDI_DMA_SYNC_FORDEV); 10702 } 10703 10704 /* 10705 * We must wait till the message has been completed before 10706 * beginning the next message so we wait for this one to 10707 * finish. 10708 */ 10709 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 10710 request_desc |= (SMID << 16) + desc_type; 10711 cmd->cmd_rfm = 0; 10712 MPTSAS_START_CMD(mpt, request_desc); 10713 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 10714 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 10715 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10716 } 10717 } 10718 10719 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *); 10720 static mptsas_pre_f mpi_pre_ioc_facts; 10721 static mptsas_pre_f mpi_pre_port_facts; 10722 static mptsas_pre_f mpi_pre_fw_download; 10723 static mptsas_pre_f mpi_pre_fw_25_download; 10724 static mptsas_pre_f mpi_pre_fw_upload; 10725 static mptsas_pre_f mpi_pre_fw_25_upload; 10726 static mptsas_pre_f mpi_pre_sata_passthrough; 10727 static mptsas_pre_f mpi_pre_smp_passthrough; 10728 static mptsas_pre_f mpi_pre_config; 10729 static mptsas_pre_f mpi_pre_sas_io_unit_control; 10730 static mptsas_pre_f mpi_pre_scsi_io_req; 10731 10732 /* 10733 * Prepare the pt for a SAS2 FW_DOWNLOAD request. 10734 */ 10735 static void 10736 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10737 { 10738 pMpi2FWDownloadTCSGE_t tcsge; 10739 pMpi2FWDownloadRequest req; 10740 10741 /* 10742 * If SAS3, call separate function. 10743 */ 10744 if (mpt->m_MPI25) { 10745 mpi_pre_fw_25_download(mpt, pt); 10746 return; 10747 } 10748 10749 /* 10750 * User requests should come in with the Transaction 10751 * context element where the SGL will go. Putting the 10752 * SGL after that seems to work, but don't really know 10753 * why. Other drivers tend to create an extra SGL and 10754 * refer to the TCE through that. 10755 */ 10756 req = (pMpi2FWDownloadRequest)pt->request; 10757 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL; 10758 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10759 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10760 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10761 } 10762 10763 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) + 10764 sizeof (*tcsge); 10765 if (pt->request_size != pt->sgl_offset) { 10766 NDBG15(("mpi_pre_fw_download(): Incorrect req size, " 10767 "0x%x, should be 0x%x, dataoutsz 0x%x", 10768 (int)pt->request_size, (int)pt->sgl_offset, 10769 (int)pt->dataout_size)); 10770 } 10771 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { 10772 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, " 10773 "0x%x, should be 0x%x", pt->data_size, 10774 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY))); 10775 } 10776 } 10777 10778 /* 10779 * Prepare the pt for a SAS3 FW_DOWNLOAD request. 10780 */ 10781 static void 10782 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10783 { 10784 pMpi2FWDownloadTCSGE_t tcsge; 10785 pMpi2FWDownloadRequest req2; 10786 pMpi25FWDownloadRequest req25; 10787 10788 /* 10789 * User requests should come in with the Transaction 10790 * context element where the SGL will go. The new firmware 10791 * Doesn't use TCE and has space in the main request for 10792 * this information. So move to the right place. 10793 */ 10794 req2 = (pMpi2FWDownloadRequest)pt->request; 10795 req25 = (pMpi25FWDownloadRequest)pt->request; 10796 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL; 10797 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10798 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10799 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10800 } 10801 req25->ImageOffset = tcsge->ImageOffset; 10802 req25->ImageSize = tcsge->ImageSize; 10803 10804 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL); 10805 if (pt->request_size != pt->sgl_offset) { 10806 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, " 10807 "0x%x, should be 0x%x, dataoutsz 0x%x", 10808 pt->request_size, pt->sgl_offset, 10809 pt->dataout_size)); 10810 } 10811 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { 10812 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, " 10813 "0x%x, should be 0x%x", pt->data_size, 10814 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10815 } 10816 } 10817 10818 /* 10819 * Prepare the pt for a SAS2 FW_UPLOAD request. 10820 */ 10821 static void 10822 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10823 { 10824 pMpi2FWUploadTCSGE_t tcsge; 10825 pMpi2FWUploadRequest_t req; 10826 10827 /* 10828 * If SAS3, call separate function. 10829 */ 10830 if (mpt->m_MPI25) { 10831 mpi_pre_fw_25_upload(mpt, pt); 10832 return; 10833 } 10834 10835 /* 10836 * User requests should come in with the Transaction 10837 * context element where the SGL will go. Putting the 10838 * SGL after that seems to work, but don't really know 10839 * why. Other drivers tend to create an extra SGL and 10840 * refer to the TCE through that. 10841 */ 10842 req = (pMpi2FWUploadRequest_t)pt->request; 10843 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL; 10844 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10845 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10846 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10847 } 10848 10849 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) + 10850 sizeof (*tcsge); 10851 if (pt->request_size != pt->sgl_offset) { 10852 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, " 10853 "0x%x, should be 0x%x, dataoutsz 0x%x", 10854 pt->request_size, pt->sgl_offset, 10855 pt->dataout_size)); 10856 } 10857 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { 10858 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, " 10859 "0x%x, should be 0x%x", pt->data_size, 10860 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10861 } 10862 } 10863 10864 /* 10865 * Prepare the pt a SAS3 FW_UPLOAD request. 10866 */ 10867 static void 10868 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10869 { 10870 pMpi2FWUploadTCSGE_t tcsge; 10871 pMpi2FWUploadRequest_t req2; 10872 pMpi25FWUploadRequest_t req25; 10873 10874 /* 10875 * User requests should come in with the Transaction 10876 * context element where the SGL will go. The new firmware 10877 * Doesn't use TCE and has space in the main request for 10878 * this information. So move to the right place. 10879 */ 10880 req2 = (pMpi2FWUploadRequest_t)pt->request; 10881 req25 = (pMpi25FWUploadRequest_t)pt->request; 10882 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL; 10883 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10884 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10885 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10886 } 10887 req25->ImageOffset = tcsge->ImageOffset; 10888 req25->ImageSize = tcsge->ImageSize; 10889 10890 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL); 10891 if (pt->request_size != pt->sgl_offset) { 10892 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, " 10893 "0x%x, should be 0x%x, dataoutsz 0x%x", 10894 pt->request_size, pt->sgl_offset, 10895 pt->dataout_size)); 10896 } 10897 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { 10898 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, " 10899 "0x%x, should be 0x%x", pt->data_size, 10900 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10901 } 10902 } 10903 10904 /* 10905 * Prepare the pt for an IOC_FACTS request. 10906 */ 10907 static void 10908 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10909 { 10910 #ifndef __lock_lint 10911 _NOTE(ARGUNUSED(mpt)) 10912 #endif 10913 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) { 10914 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, " 10915 "0x%x, should be 0x%x, dataoutsz 0x%x", 10916 pt->request_size, 10917 (int)sizeof (MPI2_IOC_FACTS_REQUEST), 10918 pt->dataout_size)); 10919 } 10920 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) { 10921 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, " 10922 "0x%x, should be 0x%x", pt->data_size, 10923 (int)sizeof (MPI2_IOC_FACTS_REPLY))); 10924 } 10925 pt->sgl_offset = (uint16_t)pt->request_size; 10926 } 10927 10928 /* 10929 * Prepare the pt for a PORT_FACTS request. 10930 */ 10931 static void 10932 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10933 { 10934 #ifndef __lock_lint 10935 _NOTE(ARGUNUSED(mpt)) 10936 #endif 10937 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) { 10938 NDBG15(("mpi_pre_port_facts(): Incorrect req size, " 10939 "0x%x, should be 0x%x, dataoutsz 0x%x", 10940 pt->request_size, 10941 (int)sizeof (MPI2_PORT_FACTS_REQUEST), 10942 pt->dataout_size)); 10943 } 10944 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) { 10945 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, " 10946 "0x%x, should be 0x%x", pt->data_size, 10947 (int)sizeof (MPI2_PORT_FACTS_REPLY))); 10948 } 10949 pt->sgl_offset = (uint16_t)pt->request_size; 10950 } 10951 10952 /* 10953 * Prepare pt for a SATA_PASSTHROUGH request. 10954 */ 10955 static void 10956 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10957 { 10958 #ifndef __lock_lint 10959 _NOTE(ARGUNUSED(mpt)) 10960 #endif 10961 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL); 10962 if (pt->request_size != pt->sgl_offset) { 10963 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, " 10964 "0x%x, should be 0x%x, dataoutsz 0x%x", 10965 pt->request_size, pt->sgl_offset, 10966 pt->dataout_size)); 10967 } 10968 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) { 10969 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, " 10970 "0x%x, should be 0x%x", pt->data_size, 10971 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY))); 10972 } 10973 } 10974 10975 static void 10976 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10977 { 10978 #ifndef __lock_lint 10979 _NOTE(ARGUNUSED(mpt)) 10980 #endif 10981 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL); 10982 if (pt->request_size != pt->sgl_offset) { 10983 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, " 10984 "0x%x, should be 0x%x, dataoutsz 0x%x", 10985 pt->request_size, pt->sgl_offset, 10986 pt->dataout_size)); 10987 } 10988 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) { 10989 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, " 10990 "0x%x, should be 0x%x", pt->data_size, 10991 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY))); 10992 } 10993 } 10994 10995 /* 10996 * Prepare pt for a CONFIG request. 10997 */ 10998 static void 10999 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt) 11000 { 11001 #ifndef __lock_lint 11002 _NOTE(ARGUNUSED(mpt)) 11003 #endif 11004 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE); 11005 if (pt->request_size != pt->sgl_offset) { 11006 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 11007 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 11008 pt->sgl_offset, pt->dataout_size)); 11009 } 11010 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) { 11011 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 11012 "should be 0x%x", pt->data_size, 11013 (int)sizeof (MPI2_CONFIG_REPLY))); 11014 } 11015 pt->simple = 1; 11016 } 11017 11018 /* 11019 * Prepare pt for a SCSI_IO_REQ request. 11020 */ 11021 static void 11022 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt) 11023 { 11024 #ifndef __lock_lint 11025 _NOTE(ARGUNUSED(mpt)) 11026 #endif 11027 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL); 11028 if (pt->request_size != pt->sgl_offset) { 11029 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 11030 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 11031 pt->sgl_offset, 11032 pt->dataout_size)); 11033 } 11034 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) { 11035 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 11036 "should be 0x%x", pt->data_size, 11037 (int)sizeof (MPI2_SCSI_IO_REPLY))); 11038 } 11039 } 11040 11041 /* 11042 * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request. 11043 */ 11044 static void 11045 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt) 11046 { 11047 #ifndef __lock_lint 11048 _NOTE(ARGUNUSED(mpt)) 11049 #endif 11050 pt->sgl_offset = (uint16_t)pt->request_size; 11051 } 11052 11053 /* 11054 * A set of functions to prepare an mptsas_cmd for the various 11055 * supported requests. 11056 */ 11057 static struct mptsas_func { 11058 U8 Function; 11059 char *Name; 11060 mptsas_pre_f *f_pre; 11061 } mptsas_func_list[] = { 11062 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts }, 11063 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts }, 11064 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download }, 11065 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload }, 11066 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH", 11067 mpi_pre_sata_passthrough }, 11068 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH", 11069 mpi_pre_smp_passthrough}, 11070 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST", 11071 mpi_pre_scsi_io_req}, 11072 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config}, 11073 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL", 11074 mpi_pre_sas_io_unit_control }, 11075 { 0xFF, NULL, NULL } /* list end */ 11076 }; 11077 11078 static void 11079 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt) 11080 { 11081 pMPI2RequestHeader_t hdr; 11082 struct mptsas_func *f; 11083 11084 hdr = (pMPI2RequestHeader_t)pt->request; 11085 11086 for (f = mptsas_func_list; f->f_pre != NULL; f++) { 11087 if (hdr->Function == f->Function) { 11088 f->f_pre(mpt, pt); 11089 NDBG15(("mptsas_prep_sgl_offset: Function %s," 11090 " sgl_offset 0x%x", f->Name, 11091 pt->sgl_offset)); 11092 return; 11093 } 11094 } 11095 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x," 11096 " returning req_size 0x%x for sgl_offset", 11097 hdr->Function, pt->request_size)); 11098 pt->sgl_offset = (uint16_t)pt->request_size; 11099 } 11100 11101 11102 static int 11103 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 11104 uint8_t *data, uint32_t request_size, uint32_t reply_size, 11105 uint32_t data_size, uint32_t direction, uint8_t *dataout, 11106 uint32_t dataout_size, short timeout, int mode) 11107 { 11108 mptsas_pt_request_t pt; 11109 mptsas_dma_alloc_state_t data_dma_state; 11110 mptsas_dma_alloc_state_t dataout_dma_state; 11111 caddr_t memp; 11112 mptsas_cmd_t *cmd = NULL; 11113 struct scsi_pkt *pkt; 11114 uint32_t reply_len = 0, sense_len = 0; 11115 pMPI2RequestHeader_t request_hdrp; 11116 pMPI2RequestHeader_t request_msg; 11117 pMPI2DefaultReply_t reply_msg; 11118 Mpi2SCSIIOReply_t rep_msg; 11119 int rvalue; 11120 int i, status = 0, pt_flags = 0, rv = 0; 11121 uint8_t function; 11122 11123 ASSERT(mutex_owned(&mpt->m_mutex)); 11124 11125 reply_msg = (pMPI2DefaultReply_t)(&rep_msg); 11126 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY)); 11127 request_msg = kmem_zalloc(request_size, KM_SLEEP); 11128 11129 mutex_exit(&mpt->m_mutex); 11130 /* 11131 * copy in the request buffer since it could be used by 11132 * another thread when the pt request into waitq 11133 */ 11134 if (ddi_copyin(request, request_msg, request_size, mode)) { 11135 mutex_enter(&mpt->m_mutex); 11136 status = EFAULT; 11137 mptsas_log(mpt, CE_WARN, "failed to copy request data"); 11138 goto out; 11139 } 11140 NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x", 11141 mode, request_size, request_msg->Function)); 11142 mutex_enter(&mpt->m_mutex); 11143 11144 function = request_msg->Function; 11145 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) { 11146 pMpi2SCSITaskManagementRequest_t task; 11147 task = (pMpi2SCSITaskManagementRequest_t)request_msg; 11148 mptsas_setup_bus_reset_delay(mpt); 11149 rv = mptsas_ioc_task_management(mpt, task->TaskType, 11150 task->DevHandle, (int)task->LUN[1], reply, reply_size, 11151 mode); 11152 11153 if (rv != TRUE) { 11154 status = EIO; 11155 mptsas_log(mpt, CE_WARN, "task management failed"); 11156 } 11157 goto out; 11158 } 11159 11160 if (data_size != 0) { 11161 data_dma_state.size = data_size; 11162 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) { 11163 status = ENOMEM; 11164 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 11165 "resource"); 11166 goto out; 11167 } 11168 pt_flags |= MPTSAS_DATA_ALLOCATED; 11169 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 11170 mutex_exit(&mpt->m_mutex); 11171 for (i = 0; i < data_size; i++) { 11172 if (ddi_copyin(data + i, (uint8_t *) 11173 data_dma_state.memp + i, 1, mode)) { 11174 mutex_enter(&mpt->m_mutex); 11175 status = EFAULT; 11176 mptsas_log(mpt, CE_WARN, "failed to " 11177 "copy read data"); 11178 goto out; 11179 } 11180 } 11181 mutex_enter(&mpt->m_mutex); 11182 } 11183 } else { 11184 bzero(&data_dma_state, sizeof (data_dma_state)); 11185 } 11186 11187 if (dataout_size != 0) { 11188 dataout_dma_state.size = dataout_size; 11189 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) { 11190 status = ENOMEM; 11191 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 11192 "resource"); 11193 goto out; 11194 } 11195 pt_flags |= MPTSAS_DATAOUT_ALLOCATED; 11196 mutex_exit(&mpt->m_mutex); 11197 for (i = 0; i < dataout_size; i++) { 11198 if (ddi_copyin(dataout + i, (uint8_t *) 11199 dataout_dma_state.memp + i, 1, mode)) { 11200 mutex_enter(&mpt->m_mutex); 11201 mptsas_log(mpt, CE_WARN, "failed to copy out" 11202 " data"); 11203 status = EFAULT; 11204 goto out; 11205 } 11206 } 11207 mutex_enter(&mpt->m_mutex); 11208 } else { 11209 bzero(&dataout_dma_state, sizeof (dataout_dma_state)); 11210 } 11211 11212 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11213 status = EAGAIN; 11214 mptsas_log(mpt, CE_NOTE, "event ack command pool is full"); 11215 goto out; 11216 } 11217 pt_flags |= MPTSAS_REQUEST_POOL_CMD; 11218 11219 bzero((caddr_t)cmd, sizeof (*cmd)); 11220 bzero((caddr_t)pkt, scsi_pkt_size()); 11221 bzero((caddr_t)&pt, sizeof (pt)); 11222 11223 cmd->ioc_cmd_slot = (uint32_t)(rvalue); 11224 11225 pt.request = (uint8_t *)request_msg; 11226 pt.direction = direction; 11227 pt.simple = 0; 11228 pt.request_size = request_size; 11229 pt.data_size = data_size; 11230 pt.dataout_size = dataout_size; 11231 pt.data_cookie = data_dma_state.cookie; 11232 pt.dataout_cookie = dataout_dma_state.cookie; 11233 mptsas_prep_sgl_offset(mpt, &pt); 11234 11235 /* 11236 * Form a blank cmd/pkt to store the acknowledgement message 11237 */ 11238 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0]; 11239 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 11240 pkt->pkt_ha_private = (opaque_t)&pt; 11241 pkt->pkt_flags = FLAG_HEAD; 11242 pkt->pkt_time = timeout; 11243 cmd->cmd_pkt = pkt; 11244 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU; 11245 11246 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11247 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11248 uint8_t com, cdb_group_id; 11249 boolean_t ret; 11250 11251 pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32; 11252 com = pkt->pkt_cdbp[0]; 11253 cdb_group_id = CDB_GROUPID(com); 11254 switch (cdb_group_id) { 11255 case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break; 11256 case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break; 11257 case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break; 11258 case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break; 11259 case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break; 11260 default: 11261 NDBG27(("mptsas_do_passthru: SCSI_IO, reserved " 11262 "CDBGROUP 0x%x requested!", cdb_group_id)); 11263 break; 11264 } 11265 11266 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11267 sense_len = reply_size - reply_len; 11268 ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP); 11269 VERIFY(ret == B_TRUE); 11270 } else { 11271 reply_len = reply_size; 11272 sense_len = 0; 11273 } 11274 11275 NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, " 11276 "snslen 0x%x", 11277 (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read", 11278 data_size, dataout_size, reply_len, sense_len)); 11279 11280 /* 11281 * Save the command in a slot 11282 */ 11283 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11284 /* 11285 * Once passthru command get slot, set cmd_flags 11286 * CFLAG_PREPARED. 11287 */ 11288 cmd->cmd_flags |= CFLAG_PREPARED; 11289 mptsas_start_passthru(mpt, cmd); 11290 } else { 11291 mptsas_waitq_add(mpt, cmd); 11292 } 11293 11294 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11295 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex); 11296 } 11297 11298 NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x " 11299 "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm, 11300 pkt->pkt_reason)); 11301 11302 if (cmd->cmd_flags & CFLAG_PREPARED) { 11303 memp = mpt->m_req_frame + (mpt->m_req_frame_size * 11304 cmd->cmd_slot); 11305 request_hdrp = (pMPI2RequestHeader_t)memp; 11306 } 11307 11308 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11309 status = ETIMEDOUT; 11310 mptsas_log(mpt, CE_WARN, "passthrough command timeout"); 11311 pt_flags |= MPTSAS_CMD_TIMEOUT; 11312 goto out; 11313 } 11314 11315 if (cmd->cmd_rfm) { 11316 /* 11317 * cmd_rfm is zero means the command reply is a CONTEXT 11318 * reply and no PCI Write to post the free reply SMFA 11319 * because no reply message frame is used. 11320 * cmd_rfm is non-zero means the reply is a ADDRESS 11321 * reply and reply message frame is used. 11322 */ 11323 pt_flags |= MPTSAS_ADDRESS_REPLY; 11324 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11325 DDI_DMA_SYNC_FORCPU); 11326 reply_msg = (pMPI2DefaultReply_t) 11327 (mpt->m_reply_frame + (cmd->cmd_rfm - 11328 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11329 } 11330 11331 mptsas_fma_check(mpt, cmd); 11332 if (pkt->pkt_reason == CMD_TRAN_ERR) { 11333 status = EAGAIN; 11334 mptsas_log(mpt, CE_WARN, "passthru fma error"); 11335 goto out; 11336 } 11337 if (pkt->pkt_reason == CMD_RESET) { 11338 status = EAGAIN; 11339 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru"); 11340 goto out; 11341 } 11342 11343 if (pkt->pkt_reason == CMD_INCOMPLETE) { 11344 status = EIO; 11345 mptsas_log(mpt, CE_WARN, "passthrough command incomplete"); 11346 goto out; 11347 } 11348 11349 mutex_exit(&mpt->m_mutex); 11350 if (cmd->cmd_flags & CFLAG_PREPARED) { 11351 function = request_hdrp->Function; 11352 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11353 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11354 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11355 sense_len = cmd->cmd_extrqslen ? 11356 min(sense_len, cmd->cmd_extrqslen) : 11357 min(sense_len, cmd->cmd_rqslen); 11358 } else { 11359 reply_len = reply_size; 11360 sense_len = 0; 11361 } 11362 11363 for (i = 0; i < reply_len; i++) { 11364 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1, 11365 mode)) { 11366 mutex_enter(&mpt->m_mutex); 11367 status = EFAULT; 11368 mptsas_log(mpt, CE_WARN, "failed to copy out " 11369 "reply data"); 11370 goto out; 11371 } 11372 } 11373 for (i = 0; i < sense_len; i++) { 11374 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i, 11375 reply + reply_len + i, 1, mode)) { 11376 mutex_enter(&mpt->m_mutex); 11377 status = EFAULT; 11378 mptsas_log(mpt, CE_WARN, "failed to copy out " 11379 "sense data"); 11380 goto out; 11381 } 11382 } 11383 } 11384 11385 if (data_size) { 11386 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) { 11387 (void) ddi_dma_sync(data_dma_state.handle, 0, 0, 11388 DDI_DMA_SYNC_FORCPU); 11389 for (i = 0; i < data_size; i++) { 11390 if (ddi_copyout((uint8_t *)( 11391 data_dma_state.memp + i), data + i, 1, 11392 mode)) { 11393 mutex_enter(&mpt->m_mutex); 11394 status = EFAULT; 11395 mptsas_log(mpt, CE_WARN, "failed to " 11396 "copy out the reply data"); 11397 goto out; 11398 } 11399 } 11400 } 11401 } 11402 mutex_enter(&mpt->m_mutex); 11403 out: 11404 /* 11405 * Put the reply frame back on the free queue, increment the free 11406 * index, and write the new index to the free index register. But only 11407 * if this reply is an ADDRESS reply. 11408 */ 11409 if (pt_flags & MPTSAS_ADDRESS_REPLY) { 11410 ddi_put32(mpt->m_acc_free_queue_hdl, 11411 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11412 cmd->cmd_rfm); 11413 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11414 DDI_DMA_SYNC_FORDEV); 11415 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11416 mpt->m_free_index = 0; 11417 } 11418 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11419 mpt->m_free_index); 11420 } 11421 if (cmd) { 11422 if (cmd->cmd_extrqslen != 0) { 11423 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 11424 cmd->cmd_extrqsidx + 1); 11425 } 11426 if (cmd->cmd_flags & CFLAG_PREPARED) { 11427 mptsas_remove_cmd(mpt, cmd); 11428 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11429 } 11430 } 11431 if (pt_flags & MPTSAS_REQUEST_POOL_CMD) 11432 mptsas_return_to_pool(mpt, cmd); 11433 if (pt_flags & MPTSAS_DATA_ALLOCATED) { 11434 if (mptsas_check_dma_handle(data_dma_state.handle) != 11435 DDI_SUCCESS) { 11436 ddi_fm_service_impact(mpt->m_dip, 11437 DDI_SERVICE_UNAFFECTED); 11438 status = EFAULT; 11439 } 11440 mptsas_dma_free(&data_dma_state); 11441 } 11442 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) { 11443 if (mptsas_check_dma_handle(dataout_dma_state.handle) != 11444 DDI_SUCCESS) { 11445 ddi_fm_service_impact(mpt->m_dip, 11446 DDI_SERVICE_UNAFFECTED); 11447 status = EFAULT; 11448 } 11449 mptsas_dma_free(&dataout_dma_state); 11450 } 11451 if (pt_flags & MPTSAS_CMD_TIMEOUT) { 11452 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 11453 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed"); 11454 } 11455 } 11456 if (request_msg) 11457 kmem_free(request_msg, request_size); 11458 NDBG27(("mptsas_do_passthru: Done status 0x%x", status)); 11459 11460 return (status); 11461 } 11462 11463 static int 11464 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode) 11465 { 11466 /* 11467 * If timeout is 0, set timeout to default of 60 seconds. 11468 */ 11469 if (data->Timeout == 0) { 11470 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT; 11471 } 11472 11473 if (((data->DataSize == 0) && 11474 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) || 11475 ((data->DataSize != 0) && 11476 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) || 11477 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) || 11478 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) && 11479 (data->DataOutSize != 0))))) { 11480 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) { 11481 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ; 11482 } else { 11483 data->DataOutSize = 0; 11484 } 11485 /* 11486 * Send passthru request messages 11487 */ 11488 return (mptsas_do_passthru(mpt, 11489 (uint8_t *)((uintptr_t)data->PtrRequest), 11490 (uint8_t *)((uintptr_t)data->PtrReply), 11491 (uint8_t *)((uintptr_t)data->PtrData), 11492 data->RequestSize, data->ReplySize, 11493 data->DataSize, data->DataDirection, 11494 (uint8_t *)((uintptr_t)data->PtrDataOut), 11495 data->DataOutSize, data->Timeout, mode)); 11496 } else { 11497 return (EINVAL); 11498 } 11499 } 11500 11501 static uint8_t 11502 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id) 11503 { 11504 uint8_t index; 11505 11506 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) { 11507 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) { 11508 return (index); 11509 } 11510 } 11511 11512 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND); 11513 } 11514 11515 static void 11516 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd) 11517 { 11518 pMpi2DiagBufferPostRequest_t pDiag_post_msg; 11519 pMpi2DiagReleaseRequest_t pDiag_release_msg; 11520 struct scsi_pkt *pkt = cmd->cmd_pkt; 11521 mptsas_diag_request_t *diag = pkt->pkt_ha_private; 11522 uint32_t i; 11523 uint64_t request_desc; 11524 11525 ASSERT(mutex_owned(&mpt->m_mutex)); 11526 11527 /* 11528 * Form the diag message depending on the post or release function. 11529 */ 11530 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) { 11531 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t) 11532 (mpt->m_req_frame + (mpt->m_req_frame_size * 11533 cmd->cmd_slot)); 11534 bzero(pDiag_post_msg, mpt->m_req_frame_size); 11535 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function, 11536 diag->function); 11537 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType, 11538 diag->pBuffer->buffer_type); 11539 ddi_put8(mpt->m_acc_req_frame_hdl, 11540 &pDiag_post_msg->ExtendedType, 11541 diag->pBuffer->extended_type); 11542 ddi_put32(mpt->m_acc_req_frame_hdl, 11543 &pDiag_post_msg->BufferLength, 11544 diag->pBuffer->buffer_data.size); 11545 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4); 11546 i++) { 11547 ddi_put32(mpt->m_acc_req_frame_hdl, 11548 &pDiag_post_msg->ProductSpecific[i], 11549 diag->pBuffer->product_specific[i]); 11550 } 11551 ddi_put32(mpt->m_acc_req_frame_hdl, 11552 &pDiag_post_msg->BufferAddress.Low, 11553 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11554 & 0xffffffffull)); 11555 ddi_put32(mpt->m_acc_req_frame_hdl, 11556 &pDiag_post_msg->BufferAddress.High, 11557 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11558 >> 32)); 11559 } else { 11560 pDiag_release_msg = (pMpi2DiagReleaseRequest_t) 11561 (mpt->m_req_frame + (mpt->m_req_frame_size * 11562 cmd->cmd_slot)); 11563 bzero(pDiag_release_msg, mpt->m_req_frame_size); 11564 ddi_put8(mpt->m_acc_req_frame_hdl, 11565 &pDiag_release_msg->Function, diag->function); 11566 ddi_put8(mpt->m_acc_req_frame_hdl, 11567 &pDiag_release_msg->BufferType, 11568 diag->pBuffer->buffer_type); 11569 } 11570 11571 /* 11572 * Send the message 11573 */ 11574 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0, 11575 DDI_DMA_SYNC_FORDEV); 11576 request_desc = (cmd->cmd_slot << 16) + 11577 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 11578 cmd->cmd_rfm = 0; 11579 MPTSAS_START_CMD(mpt, request_desc); 11580 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 11581 DDI_SUCCESS) || 11582 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 11583 DDI_SUCCESS)) { 11584 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11585 } 11586 } 11587 11588 static int 11589 mptsas_post_fw_diag_buffer(mptsas_t *mpt, 11590 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code) 11591 { 11592 mptsas_diag_request_t diag; 11593 int status, slot_num, post_flags = 0; 11594 mptsas_cmd_t *cmd = NULL; 11595 struct scsi_pkt *pkt; 11596 pMpi2DiagBufferPostReply_t reply; 11597 uint16_t iocstatus; 11598 uint32_t iocloginfo, transfer_length; 11599 11600 /* 11601 * If buffer is not enabled, just leave. 11602 */ 11603 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED; 11604 if (!pBuffer->enabled) { 11605 status = DDI_FAILURE; 11606 goto out; 11607 } 11608 11609 /* 11610 * Clear some flags initially. 11611 */ 11612 pBuffer->force_release = FALSE; 11613 pBuffer->valid_data = FALSE; 11614 pBuffer->owned_by_firmware = FALSE; 11615 11616 /* 11617 * Get a cmd buffer from the cmd buffer pool 11618 */ 11619 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11620 status = DDI_FAILURE; 11621 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag"); 11622 goto out; 11623 } 11624 post_flags |= MPTSAS_REQUEST_POOL_CMD; 11625 11626 bzero((caddr_t)cmd, sizeof (*cmd)); 11627 bzero((caddr_t)pkt, scsi_pkt_size()); 11628 11629 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11630 11631 diag.pBuffer = pBuffer; 11632 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST; 11633 11634 /* 11635 * Form a blank cmd/pkt to store the acknowledgement message 11636 */ 11637 pkt->pkt_ha_private = (opaque_t)&diag; 11638 pkt->pkt_flags = FLAG_HEAD; 11639 pkt->pkt_time = 60; 11640 cmd->cmd_pkt = pkt; 11641 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11642 11643 /* 11644 * Save the command in a slot 11645 */ 11646 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11647 /* 11648 * Once passthru command get slot, set cmd_flags 11649 * CFLAG_PREPARED. 11650 */ 11651 cmd->cmd_flags |= CFLAG_PREPARED; 11652 mptsas_start_diag(mpt, cmd); 11653 } else { 11654 mptsas_waitq_add(mpt, cmd); 11655 } 11656 11657 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11658 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11659 } 11660 11661 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11662 status = DDI_FAILURE; 11663 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout"); 11664 goto out; 11665 } 11666 11667 /* 11668 * cmd_rfm points to the reply message if a reply was given. Check the 11669 * IOCStatus to make sure everything went OK with the FW diag request 11670 * and set buffer flags. 11671 */ 11672 if (cmd->cmd_rfm) { 11673 post_flags |= MPTSAS_ADDRESS_REPLY; 11674 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11675 DDI_DMA_SYNC_FORCPU); 11676 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame + 11677 (cmd->cmd_rfm - 11678 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11679 11680 /* 11681 * Get the reply message data 11682 */ 11683 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11684 &reply->IOCStatus); 11685 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11686 &reply->IOCLogInfo); 11687 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl, 11688 &reply->TransferLength); 11689 11690 /* 11691 * If post failed quit. 11692 */ 11693 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) { 11694 status = DDI_FAILURE; 11695 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, " 11696 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus, 11697 iocloginfo, transfer_length)); 11698 goto out; 11699 } 11700 11701 /* 11702 * Post was successful. 11703 */ 11704 pBuffer->valid_data = TRUE; 11705 pBuffer->owned_by_firmware = TRUE; 11706 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11707 status = DDI_SUCCESS; 11708 } 11709 11710 out: 11711 /* 11712 * Put the reply frame back on the free queue, increment the free 11713 * index, and write the new index to the free index register. But only 11714 * if this reply is an ADDRESS reply. 11715 */ 11716 if (post_flags & MPTSAS_ADDRESS_REPLY) { 11717 ddi_put32(mpt->m_acc_free_queue_hdl, 11718 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11719 cmd->cmd_rfm); 11720 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11721 DDI_DMA_SYNC_FORDEV); 11722 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11723 mpt->m_free_index = 0; 11724 } 11725 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11726 mpt->m_free_index); 11727 } 11728 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11729 mptsas_remove_cmd(mpt, cmd); 11730 post_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11731 } 11732 if (post_flags & MPTSAS_REQUEST_POOL_CMD) { 11733 mptsas_return_to_pool(mpt, cmd); 11734 } 11735 11736 return (status); 11737 } 11738 11739 static int 11740 mptsas_release_fw_diag_buffer(mptsas_t *mpt, 11741 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 11742 uint32_t diag_type) 11743 { 11744 mptsas_diag_request_t diag; 11745 int status, slot_num, rel_flags = 0; 11746 mptsas_cmd_t *cmd = NULL; 11747 struct scsi_pkt *pkt; 11748 pMpi2DiagReleaseReply_t reply; 11749 uint16_t iocstatus; 11750 uint32_t iocloginfo; 11751 11752 /* 11753 * If buffer is not enabled, just leave. 11754 */ 11755 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED; 11756 if (!pBuffer->enabled) { 11757 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported " 11758 "by the IOC"); 11759 status = DDI_FAILURE; 11760 goto out; 11761 } 11762 11763 /* 11764 * Clear some flags initially. 11765 */ 11766 pBuffer->force_release = FALSE; 11767 pBuffer->valid_data = FALSE; 11768 pBuffer->owned_by_firmware = FALSE; 11769 11770 /* 11771 * Get a cmd buffer from the cmd buffer pool 11772 */ 11773 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11774 status = DDI_FAILURE; 11775 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW " 11776 "Diag"); 11777 goto out; 11778 } 11779 rel_flags |= MPTSAS_REQUEST_POOL_CMD; 11780 11781 bzero((caddr_t)cmd, sizeof (*cmd)); 11782 bzero((caddr_t)pkt, scsi_pkt_size()); 11783 11784 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11785 11786 diag.pBuffer = pBuffer; 11787 diag.function = MPI2_FUNCTION_DIAG_RELEASE; 11788 11789 /* 11790 * Form a blank cmd/pkt to store the acknowledgement message 11791 */ 11792 pkt->pkt_ha_private = (opaque_t)&diag; 11793 pkt->pkt_flags = FLAG_HEAD; 11794 pkt->pkt_time = 60; 11795 cmd->cmd_pkt = pkt; 11796 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11797 11798 /* 11799 * Save the command in a slot 11800 */ 11801 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11802 /* 11803 * Once passthru command get slot, set cmd_flags 11804 * CFLAG_PREPARED. 11805 */ 11806 cmd->cmd_flags |= CFLAG_PREPARED; 11807 mptsas_start_diag(mpt, cmd); 11808 } else { 11809 mptsas_waitq_add(mpt, cmd); 11810 } 11811 11812 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11813 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11814 } 11815 11816 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11817 status = DDI_FAILURE; 11818 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout"); 11819 goto out; 11820 } 11821 11822 /* 11823 * cmd_rfm points to the reply message if a reply was given. Check the 11824 * IOCStatus to make sure everything went OK with the FW diag request 11825 * and set buffer flags. 11826 */ 11827 if (cmd->cmd_rfm) { 11828 rel_flags |= MPTSAS_ADDRESS_REPLY; 11829 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11830 DDI_DMA_SYNC_FORCPU); 11831 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame + 11832 (cmd->cmd_rfm - 11833 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11834 11835 /* 11836 * Get the reply message data 11837 */ 11838 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11839 &reply->IOCStatus); 11840 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11841 &reply->IOCLogInfo); 11842 11843 /* 11844 * If release failed quit. 11845 */ 11846 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) || 11847 pBuffer->owned_by_firmware) { 11848 status = DDI_FAILURE; 11849 NDBG13(("release FW Diag Buffer failed: " 11850 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, 11851 iocloginfo)); 11852 goto out; 11853 } 11854 11855 /* 11856 * Release was successful. 11857 */ 11858 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11859 status = DDI_SUCCESS; 11860 11861 /* 11862 * If this was for an UNREGISTER diag type command, clear the 11863 * unique ID. 11864 */ 11865 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) { 11866 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 11867 } 11868 } 11869 11870 out: 11871 /* 11872 * Put the reply frame back on the free queue, increment the free 11873 * index, and write the new index to the free index register. But only 11874 * if this reply is an ADDRESS reply. 11875 */ 11876 if (rel_flags & MPTSAS_ADDRESS_REPLY) { 11877 ddi_put32(mpt->m_acc_free_queue_hdl, 11878 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11879 cmd->cmd_rfm); 11880 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11881 DDI_DMA_SYNC_FORDEV); 11882 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11883 mpt->m_free_index = 0; 11884 } 11885 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11886 mpt->m_free_index); 11887 } 11888 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11889 mptsas_remove_cmd(mpt, cmd); 11890 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11891 } 11892 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) { 11893 mptsas_return_to_pool(mpt, cmd); 11894 } 11895 11896 return (status); 11897 } 11898 11899 static int 11900 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register, 11901 uint32_t *return_code) 11902 { 11903 mptsas_fw_diagnostic_buffer_t *pBuffer; 11904 uint8_t extended_type, buffer_type, i; 11905 uint32_t buffer_size; 11906 uint32_t unique_id; 11907 int status; 11908 11909 ASSERT(mutex_owned(&mpt->m_mutex)); 11910 11911 extended_type = diag_register->ExtendedType; 11912 buffer_type = diag_register->BufferType; 11913 buffer_size = diag_register->RequestedBufferSize; 11914 unique_id = diag_register->UniqueId; 11915 11916 /* 11917 * Check for valid buffer type 11918 */ 11919 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) { 11920 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11921 return (DDI_FAILURE); 11922 } 11923 11924 /* 11925 * Get the current buffer and look up the unique ID. The unique ID 11926 * should not be found. If it is, the ID is already in use. 11927 */ 11928 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11929 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type]; 11930 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11931 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11932 return (DDI_FAILURE); 11933 } 11934 11935 /* 11936 * The buffer's unique ID should not be registered yet, and the given 11937 * unique ID cannot be 0. 11938 */ 11939 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) || 11940 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11941 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11942 return (DDI_FAILURE); 11943 } 11944 11945 /* 11946 * If this buffer is already posted as immediate, just change owner. 11947 */ 11948 if (pBuffer->immediate && pBuffer->owned_by_firmware && 11949 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11950 pBuffer->immediate = FALSE; 11951 pBuffer->unique_id = unique_id; 11952 return (DDI_SUCCESS); 11953 } 11954 11955 /* 11956 * Post a new buffer after checking if it's enabled. The DMA buffer 11957 * that is allocated will be contiguous (sgl_len = 1). 11958 */ 11959 if (!pBuffer->enabled) { 11960 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11961 return (DDI_FAILURE); 11962 } 11963 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t)); 11964 pBuffer->buffer_data.size = buffer_size; 11965 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) { 11966 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for " 11967 "diag buffer: size = %d bytes", buffer_size); 11968 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11969 return (DDI_FAILURE); 11970 } 11971 11972 /* 11973 * Copy the given info to the diag buffer and post the buffer. 11974 */ 11975 pBuffer->buffer_type = buffer_type; 11976 pBuffer->immediate = FALSE; 11977 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) { 11978 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4); 11979 i++) { 11980 pBuffer->product_specific[i] = 11981 diag_register->ProductSpecific[i]; 11982 } 11983 } 11984 pBuffer->extended_type = extended_type; 11985 pBuffer->unique_id = unique_id; 11986 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code); 11987 11988 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 11989 DDI_SUCCESS) { 11990 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in " 11991 "mptsas_diag_register."); 11992 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11993 status = DDI_FAILURE; 11994 } 11995 11996 /* 11997 * In case there was a failure, free the DMA buffer. 11998 */ 11999 if (status == DDI_FAILURE) { 12000 mptsas_dma_free(&pBuffer->buffer_data); 12001 } 12002 12003 return (status); 12004 } 12005 12006 static int 12007 mptsas_diag_unregister(mptsas_t *mpt, 12008 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code) 12009 { 12010 mptsas_fw_diagnostic_buffer_t *pBuffer; 12011 uint8_t i; 12012 uint32_t unique_id; 12013 int status; 12014 12015 ASSERT(mutex_owned(&mpt->m_mutex)); 12016 12017 unique_id = diag_unregister->UniqueId; 12018 12019 /* 12020 * Get the current buffer and look up the unique ID. The unique ID 12021 * should be there. 12022 */ 12023 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12024 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12025 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12026 return (DDI_FAILURE); 12027 } 12028 12029 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12030 12031 /* 12032 * Try to release the buffer from FW before freeing it. If release 12033 * fails, don't free the DMA buffer in case FW tries to access it 12034 * later. If buffer is not owned by firmware, can't release it. 12035 */ 12036 if (!pBuffer->owned_by_firmware) { 12037 status = DDI_SUCCESS; 12038 } else { 12039 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, 12040 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER); 12041 } 12042 12043 /* 12044 * At this point, return the current status no matter what happens with 12045 * the DMA buffer. 12046 */ 12047 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 12048 if (status == DDI_SUCCESS) { 12049 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 12050 DDI_SUCCESS) { 12051 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed " 12052 "in mptsas_diag_unregister."); 12053 ddi_fm_service_impact(mpt->m_dip, 12054 DDI_SERVICE_UNAFFECTED); 12055 } 12056 mptsas_dma_free(&pBuffer->buffer_data); 12057 } 12058 12059 return (status); 12060 } 12061 12062 static int 12063 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 12064 uint32_t *return_code) 12065 { 12066 mptsas_fw_diagnostic_buffer_t *pBuffer; 12067 uint8_t i; 12068 uint32_t unique_id; 12069 12070 ASSERT(mutex_owned(&mpt->m_mutex)); 12071 12072 unique_id = diag_query->UniqueId; 12073 12074 /* 12075 * If ID is valid, query on ID. 12076 * If ID is invalid, query on buffer type. 12077 */ 12078 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) { 12079 i = diag_query->BufferType; 12080 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) { 12081 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12082 return (DDI_FAILURE); 12083 } 12084 } else { 12085 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12086 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12087 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12088 return (DDI_FAILURE); 12089 } 12090 } 12091 12092 /* 12093 * Fill query structure with the diag buffer info. 12094 */ 12095 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12096 diag_query->BufferType = pBuffer->buffer_type; 12097 diag_query->ExtendedType = pBuffer->extended_type; 12098 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) { 12099 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4); 12100 i++) { 12101 diag_query->ProductSpecific[i] = 12102 pBuffer->product_specific[i]; 12103 } 12104 } 12105 diag_query->TotalBufferSize = pBuffer->buffer_data.size; 12106 diag_query->DriverAddedBufferSize = 0; 12107 diag_query->UniqueId = pBuffer->unique_id; 12108 diag_query->ApplicationFlags = 0; 12109 diag_query->DiagnosticFlags = 0; 12110 12111 /* 12112 * Set/Clear application flags 12113 */ 12114 if (pBuffer->immediate) { 12115 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED; 12116 } else { 12117 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED; 12118 } 12119 if (pBuffer->valid_data || pBuffer->owned_by_firmware) { 12120 diag_query->ApplicationFlags |= 12121 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 12122 } else { 12123 diag_query->ApplicationFlags &= 12124 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 12125 } 12126 if (pBuffer->owned_by_firmware) { 12127 diag_query->ApplicationFlags |= 12128 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 12129 } else { 12130 diag_query->ApplicationFlags &= 12131 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 12132 } 12133 12134 return (DDI_SUCCESS); 12135 } 12136 12137 static int 12138 mptsas_diag_read_buffer(mptsas_t *mpt, 12139 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 12140 uint32_t *return_code, int ioctl_mode) 12141 { 12142 mptsas_fw_diagnostic_buffer_t *pBuffer; 12143 uint8_t i, *pData; 12144 uint32_t unique_id, byte; 12145 int status; 12146 12147 ASSERT(mutex_owned(&mpt->m_mutex)); 12148 12149 unique_id = diag_read_buffer->UniqueId; 12150 12151 /* 12152 * Get the current buffer and look up the unique ID. The unique ID 12153 * should be there. 12154 */ 12155 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12156 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12157 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12158 return (DDI_FAILURE); 12159 } 12160 12161 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12162 12163 /* 12164 * Make sure requested read is within limits 12165 */ 12166 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead > 12167 pBuffer->buffer_data.size) { 12168 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12169 return (DDI_FAILURE); 12170 } 12171 12172 /* 12173 * Copy the requested data from DMA to the diag_read_buffer. The DMA 12174 * buffer that was allocated is one contiguous buffer. 12175 */ 12176 pData = (uint8_t *)(pBuffer->buffer_data.memp + 12177 diag_read_buffer->StartingOffset); 12178 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0, 12179 DDI_DMA_SYNC_FORCPU); 12180 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) { 12181 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode) 12182 != 0) { 12183 return (DDI_FAILURE); 12184 } 12185 } 12186 diag_read_buffer->Status = 0; 12187 12188 /* 12189 * Set or clear the Force Release flag. 12190 */ 12191 if (pBuffer->force_release) { 12192 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 12193 } else { 12194 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 12195 } 12196 12197 /* 12198 * If buffer is to be reregistered, make sure it's not already owned by 12199 * firmware first. 12200 */ 12201 status = DDI_SUCCESS; 12202 if (!pBuffer->owned_by_firmware) { 12203 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) { 12204 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, 12205 return_code); 12206 } 12207 } 12208 12209 return (status); 12210 } 12211 12212 static int 12213 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release, 12214 uint32_t *return_code) 12215 { 12216 mptsas_fw_diagnostic_buffer_t *pBuffer; 12217 uint8_t i; 12218 uint32_t unique_id; 12219 int status; 12220 12221 ASSERT(mutex_owned(&mpt->m_mutex)); 12222 12223 unique_id = diag_release->UniqueId; 12224 12225 /* 12226 * Get the current buffer and look up the unique ID. The unique ID 12227 * should be there. 12228 */ 12229 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12230 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12231 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12232 return (DDI_FAILURE); 12233 } 12234 12235 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12236 12237 /* 12238 * If buffer is not owned by firmware, it's already been released. 12239 */ 12240 if (!pBuffer->owned_by_firmware) { 12241 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED; 12242 return (DDI_FAILURE); 12243 } 12244 12245 /* 12246 * Release the buffer. 12247 */ 12248 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code, 12249 MPTSAS_FW_DIAG_TYPE_RELEASE); 12250 return (status); 12251 } 12252 12253 static int 12254 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action, 12255 uint32_t length, uint32_t *return_code, int ioctl_mode) 12256 { 12257 mptsas_fw_diag_register_t diag_register; 12258 mptsas_fw_diag_unregister_t diag_unregister; 12259 mptsas_fw_diag_query_t diag_query; 12260 mptsas_diag_read_buffer_t diag_read_buffer; 12261 mptsas_fw_diag_release_t diag_release; 12262 int status = DDI_SUCCESS; 12263 uint32_t original_return_code, read_buf_len; 12264 12265 ASSERT(mutex_owned(&mpt->m_mutex)); 12266 12267 original_return_code = *return_code; 12268 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 12269 12270 switch (action) { 12271 case MPTSAS_FW_DIAG_TYPE_REGISTER: 12272 if (!length) { 12273 *return_code = 12274 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12275 status = DDI_FAILURE; 12276 break; 12277 } 12278 if (ddi_copyin(diag_action, &diag_register, 12279 sizeof (diag_register), ioctl_mode) != 0) { 12280 return (DDI_FAILURE); 12281 } 12282 status = mptsas_diag_register(mpt, &diag_register, 12283 return_code); 12284 break; 12285 12286 case MPTSAS_FW_DIAG_TYPE_UNREGISTER: 12287 if (length < sizeof (diag_unregister)) { 12288 *return_code = 12289 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12290 status = DDI_FAILURE; 12291 break; 12292 } 12293 if (ddi_copyin(diag_action, &diag_unregister, 12294 sizeof (diag_unregister), ioctl_mode) != 0) { 12295 return (DDI_FAILURE); 12296 } 12297 status = mptsas_diag_unregister(mpt, &diag_unregister, 12298 return_code); 12299 break; 12300 12301 case MPTSAS_FW_DIAG_TYPE_QUERY: 12302 if (length < sizeof (diag_query)) { 12303 *return_code = 12304 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12305 status = DDI_FAILURE; 12306 break; 12307 } 12308 if (ddi_copyin(diag_action, &diag_query, 12309 sizeof (diag_query), ioctl_mode) != 0) { 12310 return (DDI_FAILURE); 12311 } 12312 status = mptsas_diag_query(mpt, &diag_query, 12313 return_code); 12314 if (status == DDI_SUCCESS) { 12315 if (ddi_copyout(&diag_query, diag_action, 12316 sizeof (diag_query), ioctl_mode) != 0) { 12317 return (DDI_FAILURE); 12318 } 12319 } 12320 break; 12321 12322 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER: 12323 if (ddi_copyin(diag_action, &diag_read_buffer, 12324 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) { 12325 return (DDI_FAILURE); 12326 } 12327 read_buf_len = sizeof (diag_read_buffer) - 12328 sizeof (diag_read_buffer.DataBuffer) + 12329 diag_read_buffer.BytesToRead; 12330 if (length < read_buf_len) { 12331 *return_code = 12332 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12333 status = DDI_FAILURE; 12334 break; 12335 } 12336 status = mptsas_diag_read_buffer(mpt, 12337 &diag_read_buffer, diag_action + 12338 sizeof (diag_read_buffer) - 4, return_code, 12339 ioctl_mode); 12340 if (status == DDI_SUCCESS) { 12341 if (ddi_copyout(&diag_read_buffer, diag_action, 12342 sizeof (diag_read_buffer) - 4, ioctl_mode) 12343 != 0) { 12344 return (DDI_FAILURE); 12345 } 12346 } 12347 break; 12348 12349 case MPTSAS_FW_DIAG_TYPE_RELEASE: 12350 if (length < sizeof (diag_release)) { 12351 *return_code = 12352 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12353 status = DDI_FAILURE; 12354 break; 12355 } 12356 if (ddi_copyin(diag_action, &diag_release, 12357 sizeof (diag_release), ioctl_mode) != 0) { 12358 return (DDI_FAILURE); 12359 } 12360 status = mptsas_diag_release(mpt, &diag_release, 12361 return_code); 12362 break; 12363 12364 default: 12365 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12366 status = DDI_FAILURE; 12367 break; 12368 } 12369 12370 if ((status == DDI_FAILURE) && 12371 (original_return_code == MPTSAS_FW_DIAG_NEW) && 12372 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) { 12373 status = DDI_SUCCESS; 12374 } 12375 12376 return (status); 12377 } 12378 12379 static int 12380 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode) 12381 { 12382 int status; 12383 mptsas_diag_action_t driver_data; 12384 12385 ASSERT(mutex_owned(&mpt->m_mutex)); 12386 12387 /* 12388 * Copy the user data to a driver data buffer. 12389 */ 12390 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t), 12391 mode) == 0) { 12392 /* 12393 * Send diag action request if Action is valid 12394 */ 12395 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER || 12396 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER || 12397 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY || 12398 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER || 12399 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) { 12400 status = mptsas_do_diag_action(mpt, driver_data.Action, 12401 (void *)(uintptr_t)driver_data.PtrDiagAction, 12402 driver_data.Length, &driver_data.ReturnCode, 12403 mode); 12404 if (status == DDI_SUCCESS) { 12405 if (ddi_copyout(&driver_data.ReturnCode, 12406 &user_data->ReturnCode, 12407 sizeof (user_data->ReturnCode), mode) 12408 != 0) { 12409 status = EFAULT; 12410 } else { 12411 status = 0; 12412 } 12413 } else { 12414 status = EIO; 12415 } 12416 } else { 12417 status = EINVAL; 12418 } 12419 } else { 12420 status = EFAULT; 12421 } 12422 12423 return (status); 12424 } 12425 12426 /* 12427 * This routine handles the "event query" ioctl. 12428 */ 12429 static int 12430 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode, 12431 int *rval) 12432 { 12433 int status; 12434 mptsas_event_query_t driverdata; 12435 uint8_t i; 12436 12437 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE; 12438 12439 mutex_enter(&mpt->m_mutex); 12440 for (i = 0; i < 4; i++) { 12441 driverdata.Types[i] = mpt->m_event_mask[i]; 12442 } 12443 mutex_exit(&mpt->m_mutex); 12444 12445 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) { 12446 status = EFAULT; 12447 } else { 12448 *rval = MPTIOCTL_STATUS_GOOD; 12449 status = 0; 12450 } 12451 12452 return (status); 12453 } 12454 12455 /* 12456 * This routine handles the "event enable" ioctl. 12457 */ 12458 static int 12459 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode, 12460 int *rval) 12461 { 12462 int status; 12463 mptsas_event_enable_t driverdata; 12464 uint8_t i; 12465 12466 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12467 mutex_enter(&mpt->m_mutex); 12468 for (i = 0; i < 4; i++) { 12469 mpt->m_event_mask[i] = driverdata.Types[i]; 12470 } 12471 mutex_exit(&mpt->m_mutex); 12472 12473 *rval = MPTIOCTL_STATUS_GOOD; 12474 status = 0; 12475 } else { 12476 status = EFAULT; 12477 } 12478 return (status); 12479 } 12480 12481 /* 12482 * This routine handles the "event report" ioctl. 12483 */ 12484 static int 12485 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode, 12486 int *rval) 12487 { 12488 int status; 12489 mptsas_event_report_t driverdata; 12490 12491 mutex_enter(&mpt->m_mutex); 12492 12493 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size), 12494 mode) == 0) { 12495 if (driverdata.Size >= sizeof (mpt->m_events)) { 12496 if (ddi_copyout(mpt->m_events, data->Events, 12497 sizeof (mpt->m_events), mode) != 0) { 12498 status = EFAULT; 12499 } else { 12500 if (driverdata.Size > sizeof (mpt->m_events)) { 12501 driverdata.Size = 12502 sizeof (mpt->m_events); 12503 if (ddi_copyout(&driverdata.Size, 12504 &data->Size, 12505 sizeof (driverdata.Size), 12506 mode) != 0) { 12507 status = EFAULT; 12508 } else { 12509 *rval = MPTIOCTL_STATUS_GOOD; 12510 status = 0; 12511 } 12512 } else { 12513 *rval = MPTIOCTL_STATUS_GOOD; 12514 status = 0; 12515 } 12516 } 12517 } else { 12518 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 12519 status = 0; 12520 } 12521 } else { 12522 status = EFAULT; 12523 } 12524 12525 mutex_exit(&mpt->m_mutex); 12526 return (status); 12527 } 12528 12529 static void 12530 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12531 { 12532 int *reg_data; 12533 uint_t reglen; 12534 12535 /* 12536 * Lookup the 'reg' property and extract the other data 12537 */ 12538 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12539 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12540 DDI_PROP_SUCCESS) { 12541 /* 12542 * Extract the PCI data from the 'reg' property first DWORD. 12543 * The entry looks like the following: 12544 * First DWORD: 12545 * Bits 0 - 7 8-bit Register number 12546 * Bits 8 - 10 3-bit Function number 12547 * Bits 11 - 15 5-bit Device number 12548 * Bits 16 - 23 8-bit Bus number 12549 * Bits 24 - 25 2-bit Address Space type identifier 12550 * 12551 */ 12552 adapter_data->PciInformation.u.bits.BusNumber = 12553 (reg_data[0] & 0x00FF0000) >> 16; 12554 adapter_data->PciInformation.u.bits.DeviceNumber = 12555 (reg_data[0] & 0x0000F800) >> 11; 12556 adapter_data->PciInformation.u.bits.FunctionNumber = 12557 (reg_data[0] & 0x00000700) >> 8; 12558 ddi_prop_free((void *)reg_data); 12559 } else { 12560 /* 12561 * If we can't determine the PCI data then we fill in FF's for 12562 * the data to indicate this. 12563 */ 12564 adapter_data->PCIDeviceHwId = 0xFFFFFFFF; 12565 adapter_data->MpiPortNumber = 0xFFFFFFFF; 12566 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF; 12567 } 12568 12569 /* 12570 * Saved in the mpt->m_fwversion 12571 */ 12572 adapter_data->MpiFirmwareVersion = mpt->m_fwversion; 12573 } 12574 12575 static void 12576 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12577 { 12578 char *driver_verstr = MPTSAS_MOD_STRING; 12579 12580 mptsas_lookup_pci_data(mpt, adapter_data); 12581 adapter_data->AdapterType = mpt->m_MPI25 ? 12582 MPTIOCTL_ADAPTER_TYPE_SAS3 : 12583 MPTIOCTL_ADAPTER_TYPE_SAS2; 12584 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid; 12585 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid; 12586 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid; 12587 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid; 12588 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr); 12589 adapter_data->BiosVersion = 0; 12590 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion); 12591 } 12592 12593 static void 12594 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info) 12595 { 12596 int *reg_data, i; 12597 uint_t reglen; 12598 12599 /* 12600 * Lookup the 'reg' property and extract the other data 12601 */ 12602 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12603 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12604 DDI_PROP_SUCCESS) { 12605 /* 12606 * Extract the PCI data from the 'reg' property first DWORD. 12607 * The entry looks like the following: 12608 * First DWORD: 12609 * Bits 8 - 10 3-bit Function number 12610 * Bits 11 - 15 5-bit Device number 12611 * Bits 16 - 23 8-bit Bus number 12612 */ 12613 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16; 12614 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11; 12615 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8; 12616 ddi_prop_free((void *)reg_data); 12617 } else { 12618 /* 12619 * If we can't determine the PCI info then we fill in FF's for 12620 * the data to indicate this. 12621 */ 12622 pci_info->BusNumber = 0xFFFFFFFF; 12623 pci_info->DeviceNumber = 0xFF; 12624 pci_info->FunctionNumber = 0xFF; 12625 } 12626 12627 /* 12628 * Now get the interrupt vector and the pci header. The vector can 12629 * only be 0 right now. The header is the first 256 bytes of config 12630 * space. 12631 */ 12632 pci_info->InterruptVector = 0; 12633 for (i = 0; i < sizeof (pci_info->PciHeader); i++) { 12634 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle, 12635 i); 12636 } 12637 } 12638 12639 static int 12640 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode) 12641 { 12642 int status = 0; 12643 mptsas_reg_access_t driverdata; 12644 12645 mutex_enter(&mpt->m_mutex); 12646 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12647 switch (driverdata.Command) { 12648 /* 12649 * IO access is not supported. 12650 */ 12651 case REG_IO_READ: 12652 case REG_IO_WRITE: 12653 mptsas_log(mpt, CE_WARN, "IO access is not " 12654 "supported. Use memory access."); 12655 status = EINVAL; 12656 break; 12657 12658 case REG_MEM_READ: 12659 driverdata.RegData = ddi_get32(mpt->m_datap, 12660 (uint32_t *)(void *)mpt->m_reg + 12661 driverdata.RegOffset); 12662 if (ddi_copyout(&driverdata.RegData, 12663 &data->RegData, 12664 sizeof (driverdata.RegData), mode) != 0) { 12665 mptsas_log(mpt, CE_WARN, "Register " 12666 "Read Failed"); 12667 status = EFAULT; 12668 } 12669 break; 12670 12671 case REG_MEM_WRITE: 12672 ddi_put32(mpt->m_datap, 12673 (uint32_t *)(void *)mpt->m_reg + 12674 driverdata.RegOffset, 12675 driverdata.RegData); 12676 break; 12677 12678 default: 12679 status = EINVAL; 12680 break; 12681 } 12682 } else { 12683 status = EFAULT; 12684 } 12685 12686 mutex_exit(&mpt->m_mutex); 12687 return (status); 12688 } 12689 12690 static int 12691 led_control(mptsas_t *mpt, intptr_t data, int mode) 12692 { 12693 int ret = 0; 12694 mptsas_led_control_t lc; 12695 mptsas_enclosure_t *mep; 12696 uint16_t slotidx; 12697 12698 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) { 12699 return (EFAULT); 12700 } 12701 12702 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET && 12703 lc.Command != MPTSAS_LEDCTL_FLAG_GET) || 12704 lc.Led < MPTSAS_LEDCTL_LED_MIN || 12705 lc.Led > MPTSAS_LEDCTL_LED_MAX || 12706 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 && 12707 lc.LedStatus != 1)) { 12708 return (EINVAL); 12709 } 12710 12711 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) || 12712 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0)) 12713 return (EACCES); 12714 12715 /* Locate the required enclosure */ 12716 mutex_enter(&mpt->m_mutex); 12717 mep = mptsas_enc_lookup(mpt, lc.Enclosure); 12718 if (mep == NULL) { 12719 mutex_exit(&mpt->m_mutex); 12720 return (ENOENT); 12721 } 12722 12723 if (lc.Slot < mep->me_fslot) { 12724 mutex_exit(&mpt->m_mutex); 12725 return (ENOENT); 12726 } 12727 12728 /* 12729 * Slots on the enclosure are maintained in array where me_fslot is 12730 * entry zero. We normalize the requested slot. 12731 */ 12732 slotidx = lc.Slot - mep->me_fslot; 12733 if (slotidx >= mep->me_nslots) { 12734 mutex_exit(&mpt->m_mutex); 12735 return (ENOENT); 12736 } 12737 12738 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) { 12739 /* Update our internal LED state. */ 12740 mep->me_slotleds[slotidx] &= ~(1 << (lc.Led - 1)); 12741 mep->me_slotleds[slotidx] |= lc.LedStatus << (lc.Led - 1); 12742 12743 /* Flush it to the controller. */ 12744 ret = mptsas_flush_led_status(mpt, mep, slotidx); 12745 mutex_exit(&mpt->m_mutex); 12746 return (ret); 12747 } 12748 12749 /* Return our internal LED state. */ 12750 lc.LedStatus = (mep->me_slotleds[slotidx] >> (lc.Led - 1)) & 1; 12751 mutex_exit(&mpt->m_mutex); 12752 12753 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) { 12754 return (EFAULT); 12755 } 12756 12757 return (0); 12758 } 12759 12760 static int 12761 get_disk_info(mptsas_t *mpt, intptr_t data, int mode) 12762 { 12763 uint16_t i = 0; 12764 uint16_t count = 0; 12765 int ret = 0; 12766 mptsas_target_t *ptgt; 12767 mptsas_disk_info_t *di; 12768 STRUCT_DECL(mptsas_get_disk_info, gdi); 12769 12770 if ((mode & FREAD) == 0) 12771 return (EACCES); 12772 12773 STRUCT_INIT(gdi, get_udatamodel()); 12774 12775 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi), 12776 mode) != 0) { 12777 return (EFAULT); 12778 } 12779 12780 /* Find out how many targets there are. */ 12781 mutex_enter(&mpt->m_mutex); 12782 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12783 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12784 count++; 12785 } 12786 mutex_exit(&mpt->m_mutex); 12787 12788 /* 12789 * If we haven't been asked to copy out information on each target, 12790 * then just return the count. 12791 */ 12792 STRUCT_FSET(gdi, DiskCount, count); 12793 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL) 12794 goto copy_out; 12795 12796 /* 12797 * If we haven't been given a large enough buffer to copy out into, 12798 * let the caller know. 12799 */ 12800 if (STRUCT_FGET(gdi, DiskInfoArraySize) < 12801 count * sizeof (mptsas_disk_info_t)) { 12802 ret = ENOSPC; 12803 goto copy_out; 12804 } 12805 12806 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP); 12807 12808 mutex_enter(&mpt->m_mutex); 12809 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12810 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12811 if (i >= count) { 12812 /* 12813 * The number of targets changed while we weren't 12814 * looking, so give up. 12815 */ 12816 refhash_rele(mpt->m_targets, ptgt); 12817 mutex_exit(&mpt->m_mutex); 12818 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12819 return (EAGAIN); 12820 } 12821 di[i].Instance = mpt->m_instance; 12822 di[i].Enclosure = ptgt->m_enclosure; 12823 di[i].Slot = ptgt->m_slot_num; 12824 di[i].SasAddress = ptgt->m_addr.mta_wwn; 12825 i++; 12826 } 12827 mutex_exit(&mpt->m_mutex); 12828 STRUCT_FSET(gdi, DiskCount, i); 12829 12830 /* Copy out the disk information to the caller. */ 12831 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray), 12832 i * sizeof (mptsas_disk_info_t), mode) != 0) { 12833 ret = EFAULT; 12834 } 12835 12836 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12837 12838 copy_out: 12839 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi), 12840 mode) != 0) { 12841 ret = EFAULT; 12842 } 12843 12844 return (ret); 12845 } 12846 12847 static int 12848 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp, 12849 int *rval) 12850 { 12851 int status = 0; 12852 mptsas_t *mpt; 12853 mptsas_update_flash_t flashdata; 12854 mptsas_pass_thru_t passthru_data; 12855 mptsas_adapter_data_t adapter_data; 12856 mptsas_pci_info_t pci_info; 12857 int copylen; 12858 12859 int iport_flag = 0; 12860 dev_info_t *dip = NULL; 12861 mptsas_phymask_t phymask = 0; 12862 struct devctl_iocdata *dcp = NULL; 12863 char *addr = NULL; 12864 mptsas_target_t *ptgt = NULL; 12865 12866 *rval = MPTIOCTL_STATUS_GOOD; 12867 if (secpolicy_sys_config(credp, B_FALSE) != 0) { 12868 return (EPERM); 12869 } 12870 12871 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev))); 12872 if (mpt == NULL) { 12873 /* 12874 * Called from iport node, get the states 12875 */ 12876 iport_flag = 1; 12877 dip = mptsas_get_dip_from_dev(dev, &phymask); 12878 if (dip == NULL) { 12879 return (ENXIO); 12880 } 12881 mpt = DIP2MPT(dip); 12882 } 12883 /* Make sure power level is D0 before accessing registers */ 12884 mutex_enter(&mpt->m_mutex); 12885 if (mpt->m_options & MPTSAS_OPT_PM) { 12886 (void) pm_busy_component(mpt->m_dip, 0); 12887 if (mpt->m_power_level != PM_LEVEL_D0) { 12888 mutex_exit(&mpt->m_mutex); 12889 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) != 12890 DDI_SUCCESS) { 12891 mptsas_log(mpt, CE_WARN, 12892 "mptsas%d: mptsas_ioctl: Raise power " 12893 "request failed.", mpt->m_instance); 12894 (void) pm_idle_component(mpt->m_dip, 0); 12895 return (ENXIO); 12896 } 12897 } else { 12898 mutex_exit(&mpt->m_mutex); 12899 } 12900 } else { 12901 mutex_exit(&mpt->m_mutex); 12902 } 12903 12904 if (iport_flag) { 12905 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval); 12906 if (status != 0) { 12907 goto out; 12908 } 12909 /* 12910 * The following code control the OK2RM LED, it doesn't affect 12911 * the ioctl return status. 12912 */ 12913 if ((cmd == DEVCTL_DEVICE_ONLINE) || 12914 (cmd == DEVCTL_DEVICE_OFFLINE)) { 12915 if (ndi_dc_allochdl((void *)data, &dcp) != 12916 NDI_SUCCESS) { 12917 goto out; 12918 } 12919 addr = ndi_dc_getaddr(dcp); 12920 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask); 12921 if (ptgt == NULL) { 12922 NDBG14(("mptsas_ioctl led control: tgt %s not " 12923 "found", addr)); 12924 ndi_dc_freehdl(dcp); 12925 goto out; 12926 } 12927 ndi_dc_freehdl(dcp); 12928 } 12929 goto out; 12930 } 12931 switch (cmd) { 12932 case MPTIOCTL_GET_DISK_INFO: 12933 status = get_disk_info(mpt, data, mode); 12934 break; 12935 case MPTIOCTL_LED_CONTROL: 12936 status = led_control(mpt, data, mode); 12937 break; 12938 case MPTIOCTL_UPDATE_FLASH: 12939 if (ddi_copyin((void *)data, &flashdata, 12940 sizeof (struct mptsas_update_flash), mode)) { 12941 status = EFAULT; 12942 break; 12943 } 12944 12945 mutex_enter(&mpt->m_mutex); 12946 if (mptsas_update_flash(mpt, 12947 (caddr_t)(long)flashdata.PtrBuffer, 12948 flashdata.ImageSize, flashdata.ImageType, mode)) { 12949 status = EFAULT; 12950 } 12951 12952 /* 12953 * Reset the chip to start using the new 12954 * firmware. Reset if failed also. 12955 */ 12956 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12957 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 12958 status = EFAULT; 12959 } 12960 mutex_exit(&mpt->m_mutex); 12961 break; 12962 case MPTIOCTL_PASS_THRU: 12963 /* 12964 * The user has requested to pass through a command to 12965 * be executed by the MPT firmware. Call our routine 12966 * which does this. Only allow one passthru IOCTL at 12967 * one time. Other threads will block on 12968 * m_passthru_mutex, which is of adaptive variant. 12969 */ 12970 if (ddi_copyin((void *)data, &passthru_data, 12971 sizeof (mptsas_pass_thru_t), mode)) { 12972 status = EFAULT; 12973 break; 12974 } 12975 mutex_enter(&mpt->m_passthru_mutex); 12976 mutex_enter(&mpt->m_mutex); 12977 status = mptsas_pass_thru(mpt, &passthru_data, mode); 12978 mutex_exit(&mpt->m_mutex); 12979 mutex_exit(&mpt->m_passthru_mutex); 12980 12981 break; 12982 case MPTIOCTL_GET_ADAPTER_DATA: 12983 /* 12984 * The user has requested to read adapter data. Call 12985 * our routine which does this. 12986 */ 12987 bzero(&adapter_data, sizeof (mptsas_adapter_data_t)); 12988 if (ddi_copyin((void *)data, (void *)&adapter_data, 12989 sizeof (mptsas_adapter_data_t), mode)) { 12990 status = EFAULT; 12991 break; 12992 } 12993 if (adapter_data.StructureLength >= 12994 sizeof (mptsas_adapter_data_t)) { 12995 adapter_data.StructureLength = (uint32_t) 12996 sizeof (mptsas_adapter_data_t); 12997 copylen = sizeof (mptsas_adapter_data_t); 12998 mutex_enter(&mpt->m_mutex); 12999 mptsas_read_adapter_data(mpt, &adapter_data); 13000 mutex_exit(&mpt->m_mutex); 13001 } else { 13002 adapter_data.StructureLength = (uint32_t) 13003 sizeof (mptsas_adapter_data_t); 13004 copylen = sizeof (adapter_data.StructureLength); 13005 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 13006 } 13007 if (ddi_copyout((void *)(&adapter_data), (void *)data, 13008 copylen, mode) != 0) { 13009 status = EFAULT; 13010 } 13011 break; 13012 case MPTIOCTL_GET_PCI_INFO: 13013 /* 13014 * The user has requested to read pci info. Call 13015 * our routine which does this. 13016 */ 13017 bzero(&pci_info, sizeof (mptsas_pci_info_t)); 13018 mutex_enter(&mpt->m_mutex); 13019 mptsas_read_pci_info(mpt, &pci_info); 13020 mutex_exit(&mpt->m_mutex); 13021 if (ddi_copyout((void *)(&pci_info), (void *)data, 13022 sizeof (mptsas_pci_info_t), mode) != 0) { 13023 status = EFAULT; 13024 } 13025 break; 13026 case MPTIOCTL_RESET_ADAPTER: 13027 mutex_enter(&mpt->m_mutex); 13028 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 13029 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 13030 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL " 13031 "failed"); 13032 status = EFAULT; 13033 } 13034 mutex_exit(&mpt->m_mutex); 13035 break; 13036 case MPTIOCTL_DIAG_ACTION: 13037 /* 13038 * The user has done a diag buffer action. Call our 13039 * routine which does this. Only allow one diag action 13040 * at one time. 13041 */ 13042 mutex_enter(&mpt->m_mutex); 13043 if (mpt->m_diag_action_in_progress) { 13044 mutex_exit(&mpt->m_mutex); 13045 return (EBUSY); 13046 } 13047 mpt->m_diag_action_in_progress = 1; 13048 status = mptsas_diag_action(mpt, 13049 (mptsas_diag_action_t *)data, mode); 13050 mpt->m_diag_action_in_progress = 0; 13051 mutex_exit(&mpt->m_mutex); 13052 break; 13053 case MPTIOCTL_EVENT_QUERY: 13054 /* 13055 * The user has done an event query. Call our routine 13056 * which does this. 13057 */ 13058 status = mptsas_event_query(mpt, 13059 (mptsas_event_query_t *)data, mode, rval); 13060 break; 13061 case MPTIOCTL_EVENT_ENABLE: 13062 /* 13063 * The user has done an event enable. Call our routine 13064 * which does this. 13065 */ 13066 status = mptsas_event_enable(mpt, 13067 (mptsas_event_enable_t *)data, mode, rval); 13068 break; 13069 case MPTIOCTL_EVENT_REPORT: 13070 /* 13071 * The user has done an event report. Call our routine 13072 * which does this. 13073 */ 13074 status = mptsas_event_report(mpt, 13075 (mptsas_event_report_t *)data, mode, rval); 13076 break; 13077 case MPTIOCTL_REG_ACCESS: 13078 /* 13079 * The user has requested register access. Call our 13080 * routine which does this. 13081 */ 13082 status = mptsas_reg_access(mpt, 13083 (mptsas_reg_access_t *)data, mode); 13084 break; 13085 default: 13086 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, 13087 rval); 13088 break; 13089 } 13090 13091 out: 13092 return (status); 13093 } 13094 13095 int 13096 mptsas_restart_ioc(mptsas_t *mpt) 13097 { 13098 int rval = DDI_SUCCESS; 13099 mptsas_target_t *ptgt = NULL; 13100 13101 ASSERT(mutex_owned(&mpt->m_mutex)); 13102 13103 /* 13104 * Set a flag telling I/O path that we're processing a reset. This is 13105 * needed because after the reset is complete, the hash table still 13106 * needs to be rebuilt. If I/Os are started before the hash table is 13107 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked 13108 * so that they can be retried. 13109 */ 13110 mpt->m_in_reset = TRUE; 13111 13112 /* 13113 * Wait until all the allocated sense data buffers for DMA are freed. 13114 */ 13115 while (mpt->m_extreq_sense_refcount > 0) 13116 cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex); 13117 13118 /* 13119 * Set all throttles to HOLD 13120 */ 13121 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 13122 ptgt = refhash_next(mpt->m_targets, ptgt)) { 13123 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 13124 } 13125 13126 /* 13127 * Disable interrupts 13128 */ 13129 MPTSAS_DISABLE_INTR(mpt); 13130 13131 /* 13132 * Abort all commands: outstanding commands, commands in waitq and 13133 * tx_waitq. 13134 */ 13135 mptsas_flush_hba(mpt); 13136 13137 /* 13138 * Reinitialize the chip. 13139 */ 13140 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 13141 rval = DDI_FAILURE; 13142 } 13143 13144 /* 13145 * Enable interrupts again 13146 */ 13147 MPTSAS_ENABLE_INTR(mpt); 13148 13149 /* 13150 * If mptsas_init_chip was successful, update the driver data. 13151 */ 13152 if (rval == DDI_SUCCESS) { 13153 mptsas_update_driver_data(mpt); 13154 } 13155 13156 /* 13157 * Reset the throttles 13158 */ 13159 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 13160 ptgt = refhash_next(mpt->m_targets, ptgt)) { 13161 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 13162 } 13163 13164 mptsas_doneq_empty(mpt); 13165 mptsas_restart_hba(mpt); 13166 13167 if (rval != DDI_SUCCESS) { 13168 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 13169 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 13170 } 13171 13172 /* 13173 * Clear the reset flag so that I/Os can continue. 13174 */ 13175 mpt->m_in_reset = FALSE; 13176 13177 return (rval); 13178 } 13179 13180 static int 13181 mptsas_init_chip(mptsas_t *mpt, int first_time) 13182 { 13183 ddi_dma_cookie_t cookie; 13184 uint32_t i; 13185 int rval; 13186 13187 /* 13188 * Check to see if the firmware image is valid 13189 */ 13190 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) & 13191 MPI2_DIAG_FLASH_BAD_SIG) { 13192 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!"); 13193 goto fail; 13194 } 13195 13196 /* 13197 * Reset the chip 13198 */ 13199 rval = mptsas_ioc_reset(mpt, first_time); 13200 if (rval == MPTSAS_RESET_FAIL) { 13201 mptsas_log(mpt, CE_WARN, "hard reset failed!"); 13202 goto fail; 13203 } 13204 13205 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) { 13206 goto mur; 13207 } 13208 /* 13209 * Setup configuration space 13210 */ 13211 if (mptsas_config_space_init(mpt) == FALSE) { 13212 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init " 13213 "failed!"); 13214 goto fail; 13215 } 13216 13217 /* 13218 * IOC facts can change after a diag reset so all buffers that are 13219 * based on these numbers must be de-allocated and re-allocated. Get 13220 * new IOC facts each time chip is initialized. 13221 */ 13222 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) { 13223 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed"); 13224 goto fail; 13225 } 13226 13227 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) { 13228 goto fail; 13229 } 13230 /* 13231 * Allocate request message frames, reply free queue, reply descriptor 13232 * post queue, and reply message frames using latest IOC facts. 13233 */ 13234 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) { 13235 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed"); 13236 goto fail; 13237 } 13238 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) { 13239 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed"); 13240 goto fail; 13241 } 13242 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) { 13243 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!"); 13244 goto fail; 13245 } 13246 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) { 13247 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!"); 13248 goto fail; 13249 } 13250 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) { 13251 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!"); 13252 goto fail; 13253 } 13254 13255 mur: 13256 /* 13257 * Re-Initialize ioc to operational state 13258 */ 13259 if (mptsas_ioc_init(mpt) == DDI_FAILURE) { 13260 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed"); 13261 goto fail; 13262 } 13263 13264 mptsas_alloc_reply_args(mpt); 13265 13266 /* 13267 * Initialize reply post index. Reply free index is initialized after 13268 * the next loop. 13269 */ 13270 mpt->m_post_index = 0; 13271 13272 /* 13273 * Initialize the Reply Free Queue with the physical addresses of our 13274 * reply frames. 13275 */ 13276 cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu; 13277 for (i = 0; i < mpt->m_max_replies; i++) { 13278 ddi_put32(mpt->m_acc_free_queue_hdl, 13279 &((uint32_t *)(void *)mpt->m_free_queue)[i], 13280 cookie.dmac_address); 13281 cookie.dmac_address += mpt->m_reply_frame_size; 13282 } 13283 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 13284 DDI_DMA_SYNC_FORDEV); 13285 13286 /* 13287 * Initialize the reply free index to one past the last frame on the 13288 * queue. This will signify that the queue is empty to start with. 13289 */ 13290 mpt->m_free_index = i; 13291 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i); 13292 13293 /* 13294 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's. 13295 */ 13296 for (i = 0; i < mpt->m_post_queue_depth; i++) { 13297 ddi_put64(mpt->m_acc_post_queue_hdl, 13298 &((uint64_t *)(void *)mpt->m_post_queue)[i], 13299 0xFFFFFFFFFFFFFFFF); 13300 } 13301 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 13302 DDI_DMA_SYNC_FORDEV); 13303 13304 /* 13305 * Enable ports 13306 */ 13307 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) { 13308 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed"); 13309 goto fail; 13310 } 13311 13312 /* 13313 * enable events 13314 */ 13315 if (mptsas_ioc_enable_event_notification(mpt)) { 13316 mptsas_log(mpt, CE_WARN, 13317 "mptsas_ioc_enable_event_notification failed"); 13318 goto fail; 13319 } 13320 13321 /* 13322 * We need checks in attach and these. 13323 * chip_init is called in mult. places 13324 */ 13325 13326 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 13327 DDI_SUCCESS) || 13328 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 13329 DDI_SUCCESS) || 13330 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 13331 DDI_SUCCESS) || 13332 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 13333 DDI_SUCCESS) || 13334 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 13335 DDI_SUCCESS) || 13336 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 13337 DDI_SUCCESS)) { 13338 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13339 goto fail; 13340 } 13341 13342 /* Check all acc handles */ 13343 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 13344 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 13345 DDI_SUCCESS) || 13346 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 13347 DDI_SUCCESS) || 13348 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 13349 DDI_SUCCESS) || 13350 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 13351 DDI_SUCCESS) || 13352 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 13353 DDI_SUCCESS) || 13354 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 13355 DDI_SUCCESS) || 13356 (mptsas_check_acc_handle(mpt->m_config_handle) != 13357 DDI_SUCCESS)) { 13358 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13359 goto fail; 13360 } 13361 13362 return (DDI_SUCCESS); 13363 13364 fail: 13365 return (DDI_FAILURE); 13366 } 13367 13368 static int 13369 mptsas_get_pci_cap(mptsas_t *mpt) 13370 { 13371 ushort_t caps_ptr, cap, cap_count; 13372 13373 if (mpt->m_config_handle == NULL) 13374 return (FALSE); 13375 /* 13376 * Check if capabilities list is supported and if so, 13377 * get initial capabilities pointer and clear bits 0,1. 13378 */ 13379 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) 13380 & PCI_STAT_CAP) { 13381 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13382 PCI_CONF_CAP_PTR), 4); 13383 } else { 13384 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 13385 } 13386 13387 /* 13388 * Walk capabilities if supported. 13389 */ 13390 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 13391 13392 /* 13393 * Check that we haven't exceeded the maximum number of 13394 * capabilities and that the pointer is in a valid range. 13395 */ 13396 if (++cap_count > 48) { 13397 mptsas_log(mpt, CE_WARN, 13398 "too many device capabilities.\n"); 13399 break; 13400 } 13401 if (caps_ptr < 64) { 13402 mptsas_log(mpt, CE_WARN, 13403 "capabilities pointer 0x%x out of range.\n", 13404 caps_ptr); 13405 break; 13406 } 13407 13408 /* 13409 * Get next capability and check that it is valid. 13410 * For now, we only support power management. 13411 */ 13412 cap = pci_config_get8(mpt->m_config_handle, caps_ptr); 13413 switch (cap) { 13414 case PCI_CAP_ID_PM: 13415 mptsas_log(mpt, CE_NOTE, 13416 "?mptsas%d supports power management.\n", 13417 mpt->m_instance); 13418 mpt->m_options |= MPTSAS_OPT_PM; 13419 13420 /* Save PMCSR offset */ 13421 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR; 13422 break; 13423 /* 13424 * The following capabilities are valid. Any others 13425 * will cause a message to be logged. 13426 */ 13427 case PCI_CAP_ID_VPD: 13428 case PCI_CAP_ID_MSI: 13429 case PCI_CAP_ID_PCIX: 13430 case PCI_CAP_ID_PCI_E: 13431 case PCI_CAP_ID_MSI_X: 13432 break; 13433 default: 13434 mptsas_log(mpt, CE_NOTE, 13435 "?mptsas%d unrecognized capability " 13436 "0x%x.\n", mpt->m_instance, cap); 13437 break; 13438 } 13439 13440 /* 13441 * Get next capabilities pointer and clear bits 0,1. 13442 */ 13443 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13444 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 13445 } 13446 return (TRUE); 13447 } 13448 13449 static int 13450 mptsas_init_pm(mptsas_t *mpt) 13451 { 13452 char pmc_name[16]; 13453 char *pmc[] = { 13454 NULL, 13455 "0=Off (PCI D3 State)", 13456 "3=On (PCI D0 State)", 13457 NULL 13458 }; 13459 uint16_t pmcsr_stat; 13460 13461 if (mptsas_get_pci_cap(mpt) == FALSE) { 13462 return (DDI_FAILURE); 13463 } 13464 /* 13465 * If PCI's capability does not support PM, then don't need 13466 * to registe the pm-components 13467 */ 13468 if (!(mpt->m_options & MPTSAS_OPT_PM)) 13469 return (DDI_SUCCESS); 13470 /* 13471 * If power management is supported by this chip, create 13472 * pm-components property for the power management framework 13473 */ 13474 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance); 13475 pmc[0] = pmc_name; 13476 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip, 13477 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 13478 mpt->m_options &= ~MPTSAS_OPT_PM; 13479 mptsas_log(mpt, CE_WARN, 13480 "mptsas%d: pm-component property creation failed.", 13481 mpt->m_instance); 13482 return (DDI_FAILURE); 13483 } 13484 13485 /* 13486 * Power on device. 13487 */ 13488 (void) pm_busy_component(mpt->m_dip, 0); 13489 pmcsr_stat = pci_config_get16(mpt->m_config_handle, 13490 mpt->m_pmcsr_offset); 13491 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 13492 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device", 13493 mpt->m_instance); 13494 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, 13495 PCI_PMCSR_D0); 13496 } 13497 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 13498 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed"); 13499 return (DDI_FAILURE); 13500 } 13501 mpt->m_power_level = PM_LEVEL_D0; 13502 /* 13503 * Set pm idle delay. 13504 */ 13505 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 13506 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT); 13507 13508 return (DDI_SUCCESS); 13509 } 13510 13511 static int 13512 mptsas_register_intrs(mptsas_t *mpt) 13513 { 13514 dev_info_t *dip; 13515 int intr_types; 13516 13517 dip = mpt->m_dip; 13518 13519 /* Get supported interrupt types */ 13520 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 13521 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types " 13522 "failed\n"); 13523 return (FALSE); 13524 } 13525 13526 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types)); 13527 13528 /* 13529 * Try MSI, but fall back to FIXED 13530 */ 13531 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) { 13532 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) { 13533 NDBG0(("Using MSI interrupt type")); 13534 mpt->m_intr_type = DDI_INTR_TYPE_MSI; 13535 return (TRUE); 13536 } 13537 } 13538 if (intr_types & DDI_INTR_TYPE_FIXED) { 13539 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) { 13540 NDBG0(("Using FIXED interrupt type")); 13541 mpt->m_intr_type = DDI_INTR_TYPE_FIXED; 13542 return (TRUE); 13543 } else { 13544 NDBG0(("FIXED interrupt registration failed")); 13545 return (FALSE); 13546 } 13547 } 13548 13549 return (FALSE); 13550 } 13551 13552 static void 13553 mptsas_unregister_intrs(mptsas_t *mpt) 13554 { 13555 mptsas_rem_intrs(mpt); 13556 } 13557 13558 /* 13559 * mptsas_add_intrs: 13560 * 13561 * Register FIXED or MSI interrupts. 13562 */ 13563 static int 13564 mptsas_add_intrs(mptsas_t *mpt, int intr_type) 13565 { 13566 dev_info_t *dip = mpt->m_dip; 13567 int avail, actual, count = 0; 13568 int i, flag, ret; 13569 13570 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type)); 13571 13572 /* Get number of interrupts */ 13573 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 13574 if ((ret != DDI_SUCCESS) || (count <= 0)) { 13575 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, " 13576 "ret %d count %d\n", ret, count); 13577 13578 return (DDI_FAILURE); 13579 } 13580 13581 /* Get number of available interrupts */ 13582 ret = ddi_intr_get_navail(dip, intr_type, &avail); 13583 if ((ret != DDI_SUCCESS) || (avail == 0)) { 13584 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, " 13585 "ret %d avail %d\n", ret, avail); 13586 13587 return (DDI_FAILURE); 13588 } 13589 13590 if (avail < count) { 13591 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, " 13592 "navail() returned %d", count, avail); 13593 } 13594 13595 /* Mpt only have one interrupt routine */ 13596 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 13597 count = 1; 13598 } 13599 13600 /* Allocate an array of interrupt handles */ 13601 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t); 13602 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP); 13603 13604 flag = DDI_INTR_ALLOC_NORMAL; 13605 13606 /* call ddi_intr_alloc() */ 13607 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0, 13608 count, &actual, flag); 13609 13610 if ((ret != DDI_SUCCESS) || (actual == 0)) { 13611 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n", 13612 ret); 13613 kmem_free(mpt->m_htable, mpt->m_intr_size); 13614 return (DDI_FAILURE); 13615 } 13616 13617 /* use interrupt count returned or abort? */ 13618 if (actual < count) { 13619 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n", 13620 count, actual); 13621 } 13622 13623 mpt->m_intr_cnt = actual; 13624 13625 /* 13626 * Get priority for first msi, assume remaining are all the same 13627 */ 13628 if ((ret = ddi_intr_get_pri(mpt->m_htable[0], 13629 &mpt->m_intr_pri)) != DDI_SUCCESS) { 13630 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret); 13631 13632 /* Free already allocated intr */ 13633 for (i = 0; i < actual; i++) { 13634 (void) ddi_intr_free(mpt->m_htable[i]); 13635 } 13636 13637 kmem_free(mpt->m_htable, mpt->m_intr_size); 13638 return (DDI_FAILURE); 13639 } 13640 13641 /* Test for high level mutex */ 13642 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) { 13643 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: " 13644 "Hi level interrupt not supported\n"); 13645 13646 /* Free already allocated intr */ 13647 for (i = 0; i < actual; i++) { 13648 (void) ddi_intr_free(mpt->m_htable[i]); 13649 } 13650 13651 kmem_free(mpt->m_htable, mpt->m_intr_size); 13652 return (DDI_FAILURE); 13653 } 13654 13655 /* Call ddi_intr_add_handler() */ 13656 for (i = 0; i < actual; i++) { 13657 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr, 13658 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 13659 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() " 13660 "failed %d\n", ret); 13661 13662 /* Free already allocated intr */ 13663 for (i = 0; i < actual; i++) { 13664 (void) ddi_intr_free(mpt->m_htable[i]); 13665 } 13666 13667 kmem_free(mpt->m_htable, mpt->m_intr_size); 13668 return (DDI_FAILURE); 13669 } 13670 } 13671 13672 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap)) 13673 != DDI_SUCCESS) { 13674 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret); 13675 13676 /* Free already allocated intr */ 13677 for (i = 0; i < actual; i++) { 13678 (void) ddi_intr_free(mpt->m_htable[i]); 13679 } 13680 13681 kmem_free(mpt->m_htable, mpt->m_intr_size); 13682 return (DDI_FAILURE); 13683 } 13684 13685 /* 13686 * Enable interrupts 13687 */ 13688 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13689 /* Call ddi_intr_block_enable() for MSI interrupts */ 13690 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt); 13691 } else { 13692 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 13693 for (i = 0; i < mpt->m_intr_cnt; i++) { 13694 (void) ddi_intr_enable(mpt->m_htable[i]); 13695 } 13696 } 13697 return (DDI_SUCCESS); 13698 } 13699 13700 /* 13701 * mptsas_rem_intrs: 13702 * 13703 * Unregister FIXED or MSI interrupts 13704 */ 13705 static void 13706 mptsas_rem_intrs(mptsas_t *mpt) 13707 { 13708 int i; 13709 13710 NDBG6(("mptsas_rem_intrs")); 13711 13712 /* Disable all interrupts */ 13713 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13714 /* Call ddi_intr_block_disable() */ 13715 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt); 13716 } else { 13717 for (i = 0; i < mpt->m_intr_cnt; i++) { 13718 (void) ddi_intr_disable(mpt->m_htable[i]); 13719 } 13720 } 13721 13722 /* Call ddi_intr_remove_handler() */ 13723 for (i = 0; i < mpt->m_intr_cnt; i++) { 13724 (void) ddi_intr_remove_handler(mpt->m_htable[i]); 13725 (void) ddi_intr_free(mpt->m_htable[i]); 13726 } 13727 13728 kmem_free(mpt->m_htable, mpt->m_intr_size); 13729 } 13730 13731 /* 13732 * The IO fault service error handling callback function 13733 */ 13734 /*ARGSUSED*/ 13735 static int 13736 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 13737 { 13738 /* 13739 * as the driver can always deal with an error in any dma or 13740 * access handle, we can just return the fme_status value. 13741 */ 13742 pci_ereport_post(dip, err, NULL); 13743 return (err->fme_status); 13744 } 13745 13746 /* 13747 * mptsas_fm_init - initialize fma capabilities and register with IO 13748 * fault services. 13749 */ 13750 static void 13751 mptsas_fm_init(mptsas_t *mpt) 13752 { 13753 /* 13754 * Need to change iblock to priority for new MSI intr 13755 */ 13756 ddi_iblock_cookie_t fm_ibc; 13757 13758 /* Only register with IO Fault Services if we have some capability */ 13759 if (mpt->m_fm_capabilities) { 13760 /* Adjust access and dma attributes for FMA */ 13761 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 13762 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13763 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13764 13765 /* 13766 * Register capabilities with IO Fault Services. 13767 * mpt->m_fm_capabilities will be updated to indicate 13768 * capabilities actually supported (not requested.) 13769 */ 13770 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc); 13771 13772 /* 13773 * Initialize pci ereport capabilities if ereport 13774 * capable (should always be.) 13775 */ 13776 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13777 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13778 pci_ereport_setup(mpt->m_dip); 13779 } 13780 13781 /* 13782 * Register error callback if error callback capable. 13783 */ 13784 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13785 ddi_fm_handler_register(mpt->m_dip, 13786 mptsas_fm_error_cb, (void *) mpt); 13787 } 13788 } 13789 } 13790 13791 /* 13792 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO 13793 * fault services. 13794 * 13795 */ 13796 static void 13797 mptsas_fm_fini(mptsas_t *mpt) 13798 { 13799 /* Only unregister FMA capabilities if registered */ 13800 if (mpt->m_fm_capabilities) { 13801 13802 /* 13803 * Un-register error callback if error callback capable. 13804 */ 13805 13806 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13807 ddi_fm_handler_unregister(mpt->m_dip); 13808 } 13809 13810 /* 13811 * Release any resources allocated by pci_ereport_setup() 13812 */ 13813 13814 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13815 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13816 pci_ereport_teardown(mpt->m_dip); 13817 } 13818 13819 /* Unregister from IO Fault Services */ 13820 ddi_fm_fini(mpt->m_dip); 13821 13822 /* Adjust access and dma attributes for FMA */ 13823 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 13824 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13825 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13826 13827 } 13828 } 13829 13830 int 13831 mptsas_check_acc_handle(ddi_acc_handle_t handle) 13832 { 13833 ddi_fm_error_t de; 13834 13835 if (handle == NULL) 13836 return (DDI_FAILURE); 13837 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 13838 return (de.fme_status); 13839 } 13840 13841 int 13842 mptsas_check_dma_handle(ddi_dma_handle_t handle) 13843 { 13844 ddi_fm_error_t de; 13845 13846 if (handle == NULL) 13847 return (DDI_FAILURE); 13848 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 13849 return (de.fme_status); 13850 } 13851 13852 void 13853 mptsas_fm_ereport(mptsas_t *mpt, char *detail) 13854 { 13855 uint64_t ena; 13856 char buf[FM_MAX_CLASS]; 13857 13858 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 13859 ena = fm_ena_generate(0, FM_ENA_FMT1); 13860 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) { 13861 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP, 13862 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 13863 } 13864 } 13865 13866 static int 13867 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 13868 uint16_t *dev_handle, mptsas_target_t **pptgt) 13869 { 13870 int rval; 13871 uint32_t dev_info; 13872 uint64_t sas_wwn; 13873 mptsas_phymask_t phymask; 13874 uint8_t physport, phynum, config, disk; 13875 uint64_t devicename; 13876 uint16_t pdev_hdl; 13877 mptsas_target_t *tmp_tgt = NULL; 13878 uint16_t bay_num, enclosure, io_flags; 13879 13880 ASSERT(*pptgt == NULL); 13881 13882 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle, 13883 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl, 13884 &bay_num, &enclosure, &io_flags); 13885 if (rval != DDI_SUCCESS) { 13886 rval = DEV_INFO_FAIL_PAGE0; 13887 return (rval); 13888 } 13889 13890 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET | 13891 MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13892 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == 0) { 13893 rval = DEV_INFO_WRONG_DEVICE_TYPE; 13894 return (rval); 13895 } 13896 13897 /* 13898 * Check if the dev handle is for a Phys Disk. If so, set return value 13899 * and exit. Don't add Phys Disks to hash. 13900 */ 13901 for (config = 0; config < mpt->m_num_raid_configs; config++) { 13902 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 13903 if (*dev_handle == mpt->m_raidconfig[config]. 13904 m_physdisk_devhdl[disk]) { 13905 rval = DEV_INFO_PHYS_DISK; 13906 return (rval); 13907 } 13908 } 13909 } 13910 13911 /* 13912 * Get SATA Device Name from SAS device page0 for 13913 * sata device, if device name doesn't exist, set mta_wwn to 13914 * 0 for direct attached SATA. For the device behind the expander 13915 * we still can use STP address assigned by expander. 13916 */ 13917 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13918 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13919 /* alloc a temporary target to send the cmd to */ 13920 tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle, 13921 0, dev_info, 0, 0); 13922 mutex_exit(&mpt->m_mutex); 13923 13924 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0); 13925 13926 if (devicename == -1) { 13927 mutex_enter(&mpt->m_mutex); 13928 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13929 rval = DEV_INFO_FAIL_GUID; 13930 return (rval); 13931 } 13932 13933 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) { 13934 sas_wwn = devicename; 13935 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) { 13936 sas_wwn = 0; 13937 } 13938 13939 mutex_enter(&mpt->m_mutex); 13940 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13941 } 13942 13943 phymask = mptsas_physport_to_phymask(mpt, physport); 13944 *pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn, 13945 dev_info, phymask, phynum); 13946 if (*pptgt == NULL) { 13947 mptsas_log(mpt, CE_WARN, "Failed to allocated target" 13948 "structure!"); 13949 rval = DEV_INFO_FAIL_ALLOC; 13950 return (rval); 13951 } 13952 (*pptgt)->m_io_flags = io_flags; 13953 (*pptgt)->m_enclosure = enclosure; 13954 (*pptgt)->m_slot_num = bay_num; 13955 return (DEV_INFO_SUCCESS); 13956 } 13957 13958 uint64_t 13959 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun) 13960 { 13961 uint64_t sata_guid = 0, *pwwn = NULL; 13962 int target = ptgt->m_devhdl; 13963 uchar_t *inq83 = NULL; 13964 int inq83_len = 0xFF; 13965 uchar_t *dblk = NULL; 13966 int inq83_retry = 3; 13967 int rval = DDI_FAILURE; 13968 13969 inq83 = kmem_zalloc(inq83_len, KM_SLEEP); 13970 13971 inq83_retry: 13972 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 13973 inq83_len, NULL, 1); 13974 if (rval != DDI_SUCCESS) { 13975 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 13976 "0x83 for target:%x, lun:%x failed!", target, lun); 13977 sata_guid = -1; 13978 goto out; 13979 } 13980 /* According to SAT2, the first descriptor is logic unit name */ 13981 dblk = &inq83[4]; 13982 if ((dblk[1] & 0x30) != 0) { 13983 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated."); 13984 goto out; 13985 } 13986 pwwn = (uint64_t *)(void *)(&dblk[4]); 13987 if ((dblk[4] & 0xf0) == 0x50) { 13988 sata_guid = BE_64(*pwwn); 13989 goto out; 13990 } else if (dblk[4] == 'A') { 13991 NDBG20(("SATA drive has no NAA format GUID.")); 13992 goto out; 13993 } else { 13994 /* The data is not ready, wait and retry */ 13995 inq83_retry--; 13996 if (inq83_retry <= 0) { 13997 goto out; 13998 } 13999 NDBG20(("The GUID is not ready, retry...")); 14000 delay(1 * drv_usectohz(1000000)); 14001 goto inq83_retry; 14002 } 14003 out: 14004 kmem_free(inq83, inq83_len); 14005 return (sata_guid); 14006 } 14007 14008 static int 14009 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page, 14010 unsigned char *buf, int len, int *reallen, uchar_t evpd) 14011 { 14012 uchar_t cdb[CDB_GROUP0]; 14013 struct scsi_address ap; 14014 struct buf *data_bp = NULL; 14015 int resid = 0; 14016 int ret = DDI_FAILURE; 14017 14018 ASSERT(len <= 0xffff); 14019 14020 ap.a_target = MPTSAS_INVALID_DEVHDL; 14021 ap.a_lun = (uchar_t)(lun); 14022 ap.a_hba_tran = mpt->m_tran; 14023 14024 data_bp = scsi_alloc_consistent_buf(&ap, 14025 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL); 14026 if (data_bp == NULL) { 14027 return (ret); 14028 } 14029 bzero(cdb, CDB_GROUP0); 14030 cdb[0] = SCMD_INQUIRY; 14031 cdb[1] = evpd; 14032 cdb[2] = page; 14033 cdb[3] = (len & 0xff00) >> 8; 14034 cdb[4] = (len & 0x00ff); 14035 cdb[5] = 0; 14036 14037 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp, 14038 &resid); 14039 if (ret == DDI_SUCCESS) { 14040 if (reallen) { 14041 *reallen = len - resid; 14042 } 14043 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len); 14044 } 14045 if (data_bp) { 14046 scsi_free_consistent_buf(data_bp); 14047 } 14048 return (ret); 14049 } 14050 14051 static int 14052 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 14053 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 14054 int *resid) 14055 { 14056 struct scsi_pkt *pktp = NULL; 14057 scsi_hba_tran_t *tran_clone = NULL; 14058 mptsas_tgt_private_t *tgt_private = NULL; 14059 int ret = DDI_FAILURE; 14060 14061 /* 14062 * scsi_hba_tran_t->tran_tgt_private is used to pass the address 14063 * information to scsi_init_pkt, allocate a scsi_hba_tran structure 14064 * to simulate the cmds from sd 14065 */ 14066 tran_clone = kmem_alloc( 14067 sizeof (scsi_hba_tran_t), KM_SLEEP); 14068 if (tran_clone == NULL) { 14069 goto out; 14070 } 14071 bcopy((caddr_t)mpt->m_tran, 14072 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t)); 14073 tgt_private = kmem_alloc( 14074 sizeof (mptsas_tgt_private_t), KM_SLEEP); 14075 if (tgt_private == NULL) { 14076 goto out; 14077 } 14078 tgt_private->t_lun = ap->a_lun; 14079 tgt_private->t_private = ptgt; 14080 tran_clone->tran_tgt_private = tgt_private; 14081 ap->a_hba_tran = tran_clone; 14082 14083 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL, 14084 data_bp, cdblen, sizeof (struct scsi_arq_status), 14085 0, PKT_CONSISTENT, NULL, NULL); 14086 if (pktp == NULL) { 14087 goto out; 14088 } 14089 bcopy(cdb, pktp->pkt_cdbp, cdblen); 14090 pktp->pkt_flags = FLAG_NOPARITY; 14091 if (scsi_poll(pktp) < 0) { 14092 goto out; 14093 } 14094 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) { 14095 goto out; 14096 } 14097 if (resid != NULL) { 14098 *resid = pktp->pkt_resid; 14099 } 14100 14101 ret = DDI_SUCCESS; 14102 out: 14103 if (pktp) { 14104 scsi_destroy_pkt(pktp); 14105 } 14106 if (tran_clone) { 14107 kmem_free(tran_clone, sizeof (scsi_hba_tran_t)); 14108 } 14109 if (tgt_private) { 14110 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 14111 } 14112 return (ret); 14113 } 14114 static int 14115 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun) 14116 { 14117 char *cp = NULL; 14118 char *ptr = NULL; 14119 size_t s = 0; 14120 char *wwid_str = NULL; 14121 char *lun_str = NULL; 14122 long lunnum; 14123 long phyid = -1; 14124 int rc = DDI_FAILURE; 14125 14126 ptr = name; 14127 ASSERT(ptr[0] == 'w' || ptr[0] == 'p'); 14128 ptr++; 14129 if ((cp = strchr(ptr, ',')) == NULL) { 14130 return (DDI_FAILURE); 14131 } 14132 14133 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14134 s = (uintptr_t)cp - (uintptr_t)ptr; 14135 14136 bcopy(ptr, wwid_str, s); 14137 wwid_str[s] = '\0'; 14138 14139 ptr = ++cp; 14140 14141 if ((cp = strchr(ptr, '\0')) == NULL) { 14142 goto out; 14143 } 14144 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14145 s = (uintptr_t)cp - (uintptr_t)ptr; 14146 14147 bcopy(ptr, lun_str, s); 14148 lun_str[s] = '\0'; 14149 14150 if (name[0] == 'p') { 14151 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid); 14152 } else { 14153 rc = scsi_wwnstr_to_wwn(wwid_str, wwid); 14154 } 14155 if (rc != DDI_SUCCESS) 14156 goto out; 14157 14158 if (phyid != -1) { 14159 ASSERT(phyid < MPTSAS_MAX_PHYS); 14160 *phy = (uint8_t)phyid; 14161 } 14162 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum); 14163 if (rc != 0) 14164 goto out; 14165 14166 *lun = (int)lunnum; 14167 rc = DDI_SUCCESS; 14168 out: 14169 if (wwid_str) 14170 kmem_free(wwid_str, SCSI_MAXNAMELEN); 14171 if (lun_str) 14172 kmem_free(lun_str, SCSI_MAXNAMELEN); 14173 14174 return (rc); 14175 } 14176 14177 /* 14178 * mptsas_parse_smp_name() is to parse sas wwn string 14179 * which format is "wWWN" 14180 */ 14181 static int 14182 mptsas_parse_smp_name(char *name, uint64_t *wwn) 14183 { 14184 char *ptr = name; 14185 14186 if (*ptr != 'w') { 14187 return (DDI_FAILURE); 14188 } 14189 14190 ptr++; 14191 if (scsi_wwnstr_to_wwn(ptr, wwn)) { 14192 return (DDI_FAILURE); 14193 } 14194 return (DDI_SUCCESS); 14195 } 14196 14197 static int 14198 mptsas_bus_config(dev_info_t *pdip, uint_t flag, 14199 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 14200 { 14201 int ret = NDI_FAILURE; 14202 int circ = 0; 14203 int circ1 = 0; 14204 mptsas_t *mpt; 14205 char *ptr = NULL; 14206 char *devnm = NULL; 14207 uint64_t wwid = 0; 14208 uint8_t phy = 0xFF; 14209 int lun = 0; 14210 uint_t mflags = flag; 14211 int bconfig = TRUE; 14212 14213 if (scsi_hba_iport_unit_address(pdip) == 0) { 14214 return (DDI_FAILURE); 14215 } 14216 14217 mpt = DIP2MPT(pdip); 14218 if (!mpt) { 14219 return (DDI_FAILURE); 14220 } 14221 /* 14222 * Hold the nexus across the bus_config 14223 */ 14224 ndi_devi_enter(scsi_vhci_dip, &circ); 14225 ndi_devi_enter(pdip, &circ1); 14226 switch (op) { 14227 case BUS_CONFIG_ONE: 14228 /* parse wwid/target name out of name given */ 14229 if ((ptr = strchr((char *)arg, '@')) == NULL) { 14230 ret = NDI_FAILURE; 14231 break; 14232 } 14233 ptr++; 14234 if (strncmp((char *)arg, "smp", 3) == 0) { 14235 /* 14236 * This is a SMP target device 14237 */ 14238 ret = mptsas_parse_smp_name(ptr, &wwid); 14239 if (ret != DDI_SUCCESS) { 14240 ret = NDI_FAILURE; 14241 break; 14242 } 14243 ret = mptsas_config_smp(pdip, wwid, childp); 14244 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) { 14245 /* 14246 * OBP could pass down a non-canonical form 14247 * bootpath without LUN part when LUN is 0. 14248 * So driver need adjust the string. 14249 */ 14250 if (strchr(ptr, ',') == NULL) { 14251 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14252 (void) sprintf(devnm, "%s,0", (char *)arg); 14253 ptr = strchr(devnm, '@'); 14254 ptr++; 14255 } 14256 14257 /* 14258 * The device path is wWWID format and the device 14259 * is not SMP target device. 14260 */ 14261 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun); 14262 if (ret != DDI_SUCCESS) { 14263 ret = NDI_FAILURE; 14264 break; 14265 } 14266 *childp = NULL; 14267 if (ptr[0] == 'w') { 14268 ret = mptsas_config_one_addr(pdip, wwid, 14269 lun, childp); 14270 } else if (ptr[0] == 'p') { 14271 ret = mptsas_config_one_phy(pdip, phy, lun, 14272 childp); 14273 } 14274 14275 /* 14276 * If this is CD/DVD device in OBP path, the 14277 * ndi_busop_bus_config can be skipped as config one 14278 * operation is done above. 14279 */ 14280 if ((ret == NDI_SUCCESS) && (*childp != NULL) && 14281 (strcmp(ddi_node_name(*childp), "cdrom") == 0) && 14282 (strncmp((char *)arg, "disk", 4) == 0)) { 14283 bconfig = FALSE; 14284 ndi_hold_devi(*childp); 14285 } 14286 } else { 14287 ret = NDI_FAILURE; 14288 break; 14289 } 14290 14291 /* 14292 * DDI group instructed us to use this flag. 14293 */ 14294 mflags |= NDI_MDI_FALLBACK; 14295 break; 14296 case BUS_CONFIG_DRIVER: 14297 case BUS_CONFIG_ALL: 14298 mptsas_config_all(pdip); 14299 ret = NDI_SUCCESS; 14300 break; 14301 default: 14302 ret = NDI_FAILURE; 14303 break; 14304 } 14305 14306 if ((ret == NDI_SUCCESS) && bconfig) { 14307 ret = ndi_busop_bus_config(pdip, mflags, op, 14308 (devnm == NULL) ? arg : devnm, childp, 0); 14309 } 14310 14311 ndi_devi_exit(pdip, circ1); 14312 ndi_devi_exit(scsi_vhci_dip, circ); 14313 if (devnm != NULL) 14314 kmem_free(devnm, SCSI_MAXNAMELEN); 14315 return (ret); 14316 } 14317 14318 static int 14319 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip, 14320 mptsas_target_t *ptgt) 14321 { 14322 int rval = DDI_FAILURE; 14323 struct scsi_inquiry *sd_inq = NULL; 14324 mptsas_t *mpt = DIP2MPT(pdip); 14325 14326 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14327 14328 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq, 14329 SUN_INQSIZE, 0, (uchar_t)0); 14330 14331 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14332 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun); 14333 } else { 14334 rval = DDI_FAILURE; 14335 } 14336 14337 kmem_free(sd_inq, SUN_INQSIZE); 14338 return (rval); 14339 } 14340 14341 static int 14342 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 14343 dev_info_t **lundip) 14344 { 14345 int rval; 14346 mptsas_t *mpt = DIP2MPT(pdip); 14347 int phymask; 14348 mptsas_target_t *ptgt = NULL; 14349 14350 /* 14351 * Get the physical port associated to the iport 14352 */ 14353 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14354 "phymask", 0); 14355 14356 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr); 14357 if (ptgt == NULL) { 14358 /* 14359 * didn't match any device by searching 14360 */ 14361 return (DDI_FAILURE); 14362 } 14363 /* 14364 * If the LUN already exists and the status is online, 14365 * we just return the pointer to dev_info_t directly. 14366 * For the mdi_pathinfo node, we'll handle it in 14367 * mptsas_create_virt_lun() 14368 * TODO should be also in mptsas_handle_dr 14369 */ 14370 14371 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun); 14372 if (*lundip != NULL) { 14373 /* 14374 * TODO Another senario is, we hotplug the same disk 14375 * on the same slot, the devhdl changed, is this 14376 * possible? 14377 * tgt_private->t_private != ptgt 14378 */ 14379 if (sasaddr != ptgt->m_addr.mta_wwn) { 14380 /* 14381 * The device has changed although the devhdl is the 14382 * same (Enclosure mapping mode, change drive on the 14383 * same slot) 14384 */ 14385 return (DDI_FAILURE); 14386 } 14387 return (DDI_SUCCESS); 14388 } 14389 14390 if (phymask == 0) { 14391 /* 14392 * Configure IR volume 14393 */ 14394 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip); 14395 return (rval); 14396 } 14397 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14398 14399 return (rval); 14400 } 14401 14402 static int 14403 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 14404 dev_info_t **lundip) 14405 { 14406 int rval; 14407 mptsas_t *mpt = DIP2MPT(pdip); 14408 mptsas_phymask_t phymask; 14409 mptsas_target_t *ptgt = NULL; 14410 14411 /* 14412 * Get the physical port associated to the iport 14413 */ 14414 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14415 "phymask", 0); 14416 14417 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy); 14418 if (ptgt == NULL) { 14419 /* 14420 * didn't match any device by searching 14421 */ 14422 return (DDI_FAILURE); 14423 } 14424 14425 /* 14426 * If the LUN already exists and the status is online, 14427 * we just return the pointer to dev_info_t directly. 14428 * For the mdi_pathinfo node, we'll handle it in 14429 * mptsas_create_virt_lun(). 14430 */ 14431 14432 *lundip = mptsas_find_child_phy(pdip, phy); 14433 if (*lundip != NULL) { 14434 return (DDI_SUCCESS); 14435 } 14436 14437 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14438 14439 return (rval); 14440 } 14441 14442 static int 14443 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num, 14444 uint8_t *lun_addr_type) 14445 { 14446 uint32_t lun_idx = 0; 14447 14448 ASSERT(lun_num != NULL); 14449 ASSERT(lun_addr_type != NULL); 14450 14451 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14452 /* determine report luns addressing type */ 14453 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) { 14454 /* 14455 * Vendors in the field have been found to be concatenating 14456 * bus/target/lun to equal the complete lun value instead 14457 * of switching to flat space addressing 14458 */ 14459 /* 00b - peripheral device addressing method */ 14460 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL: 14461 /* FALLTHRU */ 14462 /* 10b - logical unit addressing method */ 14463 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT: 14464 /* FALLTHRU */ 14465 /* 01b - flat space addressing method */ 14466 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE: 14467 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */ 14468 *lun_addr_type = (buf[lun_idx] & 14469 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6; 14470 *lun_num = (buf[lun_idx] & 0x3F) << 8; 14471 *lun_num |= buf[lun_idx + 1]; 14472 return (DDI_SUCCESS); 14473 default: 14474 return (DDI_FAILURE); 14475 } 14476 } 14477 14478 static int 14479 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) 14480 { 14481 struct buf *repluns_bp = NULL; 14482 struct scsi_address ap; 14483 uchar_t cdb[CDB_GROUP5]; 14484 int ret = DDI_FAILURE; 14485 int retry = 0; 14486 int lun_list_len = 0; 14487 uint16_t lun_num = 0; 14488 uint8_t lun_addr_type = 0; 14489 uint32_t lun_cnt = 0; 14490 uint32_t lun_total = 0; 14491 dev_info_t *cdip = NULL; 14492 uint16_t *saved_repluns = NULL; 14493 char *buffer = NULL; 14494 int buf_len = 128; 14495 mptsas_t *mpt = DIP2MPT(pdip); 14496 uint64_t sas_wwn = 0; 14497 uint8_t phy = 0xFF; 14498 uint32_t dev_info = 0; 14499 14500 mutex_enter(&mpt->m_mutex); 14501 sas_wwn = ptgt->m_addr.mta_wwn; 14502 phy = ptgt->m_phynum; 14503 dev_info = ptgt->m_deviceinfo; 14504 mutex_exit(&mpt->m_mutex); 14505 14506 if (sas_wwn == 0) { 14507 /* 14508 * It's a SATA without Device Name 14509 * So don't try multi-LUNs 14510 */ 14511 if (mptsas_find_child_phy(pdip, phy)) { 14512 return (DDI_SUCCESS); 14513 } else { 14514 /* 14515 * need configure and create node 14516 */ 14517 return (DDI_FAILURE); 14518 } 14519 } 14520 14521 /* 14522 * WWN (SAS address or Device Name exist) 14523 */ 14524 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 14525 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 14526 /* 14527 * SATA device with Device Name 14528 * So don't try multi-LUNs 14529 */ 14530 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) { 14531 return (DDI_SUCCESS); 14532 } else { 14533 return (DDI_FAILURE); 14534 } 14535 } 14536 14537 do { 14538 ap.a_target = MPTSAS_INVALID_DEVHDL; 14539 ap.a_lun = 0; 14540 ap.a_hba_tran = mpt->m_tran; 14541 repluns_bp = scsi_alloc_consistent_buf(&ap, 14542 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL); 14543 if (repluns_bp == NULL) { 14544 retry++; 14545 continue; 14546 } 14547 bzero(cdb, CDB_GROUP5); 14548 cdb[0] = SCMD_REPORT_LUNS; 14549 cdb[6] = (buf_len & 0xff000000) >> 24; 14550 cdb[7] = (buf_len & 0x00ff0000) >> 16; 14551 cdb[8] = (buf_len & 0x0000ff00) >> 8; 14552 cdb[9] = (buf_len & 0x000000ff); 14553 14554 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5, 14555 repluns_bp, NULL); 14556 if (ret != DDI_SUCCESS) { 14557 scsi_free_consistent_buf(repluns_bp); 14558 retry++; 14559 continue; 14560 } 14561 lun_list_len = BE_32(*(int *)((void *)( 14562 repluns_bp->b_un.b_addr))); 14563 if (buf_len >= lun_list_len + 8) { 14564 ret = DDI_SUCCESS; 14565 break; 14566 } 14567 scsi_free_consistent_buf(repluns_bp); 14568 buf_len = lun_list_len + 8; 14569 14570 } while (retry < 3); 14571 14572 if (ret != DDI_SUCCESS) 14573 return (ret); 14574 buffer = (char *)repluns_bp->b_un.b_addr; 14575 /* 14576 * find out the number of luns returned by the SCSI ReportLun call 14577 * and allocate buffer space 14578 */ 14579 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14580 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP); 14581 if (saved_repluns == NULL) { 14582 scsi_free_consistent_buf(repluns_bp); 14583 return (DDI_FAILURE); 14584 } 14585 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) { 14586 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer), 14587 &lun_num, &lun_addr_type) != DDI_SUCCESS) { 14588 continue; 14589 } 14590 saved_repluns[lun_cnt] = lun_num; 14591 if ((cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) != 14592 NULL) { 14593 ret = DDI_SUCCESS; 14594 } else { 14595 ret = mptsas_probe_lun(pdip, lun_num, &cdip, 14596 ptgt); 14597 } 14598 if ((ret == DDI_SUCCESS) && (cdip != NULL)) { 14599 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, 14600 MPTSAS_DEV_GONE); 14601 } 14602 } 14603 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt); 14604 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total); 14605 scsi_free_consistent_buf(repluns_bp); 14606 return (DDI_SUCCESS); 14607 } 14608 14609 static int 14610 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip) 14611 { 14612 int rval = DDI_FAILURE; 14613 struct scsi_inquiry *sd_inq = NULL; 14614 mptsas_t *mpt = DIP2MPT(pdip); 14615 mptsas_target_t *ptgt = NULL; 14616 14617 mutex_enter(&mpt->m_mutex); 14618 ptgt = refhash_linear_search(mpt->m_targets, 14619 mptsas_target_eval_devhdl, &target); 14620 mutex_exit(&mpt->m_mutex); 14621 if (ptgt == NULL) { 14622 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x " 14623 "not found.", target); 14624 return (rval); 14625 } 14626 14627 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14628 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq, 14629 SUN_INQSIZE, 0, (uchar_t)0); 14630 14631 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14632 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt, 14633 0); 14634 } else { 14635 rval = DDI_FAILURE; 14636 } 14637 14638 kmem_free(sd_inq, SUN_INQSIZE); 14639 return (rval); 14640 } 14641 14642 /* 14643 * configure all RAID volumes for virtual iport 14644 */ 14645 static void 14646 mptsas_config_all_viport(dev_info_t *pdip) 14647 { 14648 mptsas_t *mpt = DIP2MPT(pdip); 14649 int config, vol; 14650 int target; 14651 dev_info_t *lundip = NULL; 14652 14653 /* 14654 * Get latest RAID info and search for any Volume DevHandles. If any 14655 * are found, configure the volume. 14656 */ 14657 mutex_enter(&mpt->m_mutex); 14658 for (config = 0; config < mpt->m_num_raid_configs; config++) { 14659 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 14660 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid 14661 == 1) { 14662 target = mpt->m_raidconfig[config]. 14663 m_raidvol[vol].m_raidhandle; 14664 mutex_exit(&mpt->m_mutex); 14665 (void) mptsas_config_raid(pdip, target, 14666 &lundip); 14667 mutex_enter(&mpt->m_mutex); 14668 } 14669 } 14670 } 14671 mutex_exit(&mpt->m_mutex); 14672 } 14673 14674 static void 14675 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns, 14676 int lun_cnt, mptsas_target_t *ptgt) 14677 { 14678 dev_info_t *child = NULL, *savechild = NULL; 14679 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 14680 uint64_t sas_wwn, wwid; 14681 uint8_t phy; 14682 int lun; 14683 int i; 14684 int find; 14685 char *addr; 14686 char *nodename; 14687 mptsas_t *mpt = DIP2MPT(pdip); 14688 14689 mutex_enter(&mpt->m_mutex); 14690 wwid = ptgt->m_addr.mta_wwn; 14691 mutex_exit(&mpt->m_mutex); 14692 14693 child = ddi_get_child(pdip); 14694 while (child) { 14695 find = 0; 14696 savechild = child; 14697 child = ddi_get_next_sibling(child); 14698 14699 nodename = ddi_node_name(savechild); 14700 if (strcmp(nodename, "smp") == 0) { 14701 continue; 14702 } 14703 14704 addr = ddi_get_name_addr(savechild); 14705 if (addr == NULL) { 14706 continue; 14707 } 14708 14709 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) != 14710 DDI_SUCCESS) { 14711 continue; 14712 } 14713 14714 if (wwid == sas_wwn) { 14715 for (i = 0; i < lun_cnt; i++) { 14716 if (repluns[i] == lun) { 14717 find = 1; 14718 break; 14719 } 14720 } 14721 } else { 14722 continue; 14723 } 14724 if (find == 0) { 14725 /* 14726 * The lun has not been there already 14727 */ 14728 (void) mptsas_offline_lun(pdip, savechild, NULL, 14729 NDI_DEVI_REMOVE); 14730 } 14731 } 14732 14733 pip = mdi_get_next_client_path(pdip, NULL); 14734 while (pip) { 14735 find = 0; 14736 savepip = pip; 14737 addr = MDI_PI(pip)->pi_addr; 14738 14739 pip = mdi_get_next_client_path(pdip, pip); 14740 14741 if (addr == NULL) { 14742 continue; 14743 } 14744 14745 if (mptsas_parse_address(addr, &sas_wwn, &phy, 14746 &lun) != DDI_SUCCESS) { 14747 continue; 14748 } 14749 14750 if (sas_wwn == wwid) { 14751 for (i = 0; i < lun_cnt; i++) { 14752 if (repluns[i] == lun) { 14753 find = 1; 14754 break; 14755 } 14756 } 14757 } else { 14758 continue; 14759 } 14760 14761 if (find == 0) { 14762 /* 14763 * The lun has not been there already 14764 */ 14765 (void) mptsas_offline_lun(pdip, NULL, savepip, 14766 NDI_DEVI_REMOVE); 14767 } 14768 } 14769 } 14770 14771 /* 14772 * If this enclosure doesn't exist in the enclosure list, add it. If it does, 14773 * update it. 14774 */ 14775 static void 14776 mptsas_enclosure_update(mptsas_t *mpt, mptsas_enclosure_t *mep) 14777 { 14778 mptsas_enclosure_t *m; 14779 14780 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14781 m = mptsas_enc_lookup(mpt, mep->me_enchdl); 14782 if (m != NULL) { 14783 uint8_t *ledp; 14784 m->me_flags = mep->me_flags; 14785 14786 14787 /* 14788 * If the number of slots and the first slot entry in the 14789 * enclosure has not changed, then we don't need to do anything 14790 * here. Otherwise, we need to allocate a new array for the LED 14791 * status of the slot. 14792 */ 14793 if (m->me_fslot == mep->me_fslot && 14794 m->me_nslots == mep->me_nslots) 14795 return; 14796 14797 /* 14798 * If the number of slots or the first slot has changed, it's 14799 * not clear that we're really in a place that we can continue 14800 * to honor the existing flags. 14801 */ 14802 if (mep->me_nslots > 0) { 14803 ledp = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots, 14804 KM_SLEEP); 14805 } else { 14806 ledp = NULL; 14807 } 14808 14809 if (m->me_slotleds != NULL) { 14810 kmem_free(m->me_slotleds, sizeof (uint8_t) * 14811 m->me_nslots); 14812 } 14813 m->me_slotleds = ledp; 14814 m->me_fslot = mep->me_fslot; 14815 m->me_nslots = mep->me_nslots; 14816 return; 14817 } 14818 14819 m = kmem_zalloc(sizeof (*m), KM_SLEEP); 14820 m->me_enchdl = mep->me_enchdl; 14821 m->me_flags = mep->me_flags; 14822 m->me_nslots = mep->me_nslots; 14823 m->me_fslot = mep->me_fslot; 14824 if (m->me_nslots > 0) { 14825 m->me_slotleds = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots, 14826 KM_SLEEP); 14827 /* 14828 * It may make sense to optionally flush all of the slots and/or 14829 * read the slot status flag here to synchronize between 14830 * ourselves and the card. So far, that hasn't been needed 14831 * annecdotally when enumerating something new. If we do, we 14832 * should kick that off in a taskq potentially. 14833 */ 14834 } 14835 list_insert_tail(&mpt->m_enclosures, m); 14836 } 14837 14838 static void 14839 mptsas_update_hashtab(struct mptsas *mpt) 14840 { 14841 uint32_t page_address; 14842 int rval = 0; 14843 uint16_t dev_handle; 14844 mptsas_target_t *ptgt = NULL; 14845 mptsas_smp_t smp_node; 14846 14847 /* 14848 * Get latest RAID info. 14849 */ 14850 (void) mptsas_get_raid_info(mpt); 14851 14852 dev_handle = mpt->m_smp_devhdl; 14853 while (mpt->m_done_traverse_smp == 0) { 14854 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 14855 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14856 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node) 14857 != DDI_SUCCESS) { 14858 break; 14859 } 14860 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl; 14861 (void) mptsas_smp_alloc(mpt, &smp_node); 14862 } 14863 14864 /* 14865 * Loop over enclosures so we can understand what's there. 14866 */ 14867 dev_handle = MPTSAS_INVALID_DEVHDL; 14868 while (mpt->m_done_traverse_enc == 0) { 14869 mptsas_enclosure_t me; 14870 14871 page_address = (MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE & 14872 MPI2_SAS_ENCLOS_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14873 14874 if (mptsas_get_enclosure_page0(mpt, page_address, &me) != 14875 DDI_SUCCESS) { 14876 break; 14877 } 14878 dev_handle = me.me_enchdl; 14879 mptsas_enclosure_update(mpt, &me); 14880 } 14881 14882 /* 14883 * Config target devices 14884 */ 14885 dev_handle = mpt->m_dev_handle; 14886 14887 /* 14888 * Loop to get sas device page 0 by GetNextHandle till the 14889 * the last handle. If the sas device is a SATA/SSP target, 14890 * we try to config it. 14891 */ 14892 while (mpt->m_done_traverse_dev == 0) { 14893 ptgt = NULL; 14894 page_address = 14895 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 14896 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14897 (uint32_t)dev_handle; 14898 rval = mptsas_get_target_device_info(mpt, page_address, 14899 &dev_handle, &ptgt); 14900 if ((rval == DEV_INFO_FAIL_PAGE0) || 14901 (rval == DEV_INFO_FAIL_ALLOC) || 14902 (rval == DEV_INFO_FAIL_GUID)) { 14903 break; 14904 } 14905 14906 mpt->m_dev_handle = dev_handle; 14907 } 14908 14909 } 14910 14911 void 14912 mptsas_update_driver_data(struct mptsas *mpt) 14913 { 14914 mptsas_target_t *tp; 14915 mptsas_smp_t *sp; 14916 14917 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14918 14919 /* 14920 * TODO after hard reset, update the driver data structures 14921 * 1. update port/phymask mapping table mpt->m_phy_info 14922 * 2. invalid all the entries in hash table 14923 * m_devhdl = 0xffff and m_deviceinfo = 0 14924 * 3. call sas_device_page/expander_page to update hash table 14925 */ 14926 mptsas_update_phymask(mpt); 14927 14928 /* 14929 * Remove all the devhdls for existing entries but leave their 14930 * addresses alone. In update_hashtab() below, we'll find all 14931 * targets that are still present and reassociate them with 14932 * their potentially new devhdls. Leaving the targets around in 14933 * this fashion allows them to be used on the tx waitq even 14934 * while IOC reset is occurring. 14935 */ 14936 for (tp = refhash_first(mpt->m_targets); tp != NULL; 14937 tp = refhash_next(mpt->m_targets, tp)) { 14938 tp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14939 tp->m_deviceinfo = 0; 14940 tp->m_dr_flag = MPTSAS_DR_INACTIVE; 14941 } 14942 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 14943 sp = refhash_next(mpt->m_smp_targets, sp)) { 14944 sp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14945 sp->m_deviceinfo = 0; 14946 } 14947 mpt->m_done_traverse_dev = 0; 14948 mpt->m_done_traverse_smp = 0; 14949 mpt->m_done_traverse_enc = 0; 14950 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL; 14951 mptsas_update_hashtab(mpt); 14952 } 14953 14954 static void 14955 mptsas_config_all(dev_info_t *pdip) 14956 { 14957 dev_info_t *smpdip = NULL; 14958 mptsas_t *mpt = DIP2MPT(pdip); 14959 int phymask = 0; 14960 mptsas_phymask_t phy_mask; 14961 mptsas_target_t *ptgt = NULL; 14962 mptsas_smp_t *psmp; 14963 14964 /* 14965 * Get the phymask associated to the iport 14966 */ 14967 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14968 "phymask", 0); 14969 14970 /* 14971 * Enumerate RAID volumes here (phymask == 0). 14972 */ 14973 if (phymask == 0) { 14974 mptsas_config_all_viport(pdip); 14975 return; 14976 } 14977 14978 mutex_enter(&mpt->m_mutex); 14979 14980 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp || 14981 !mpt->m_done_traverse_enc) { 14982 mptsas_update_hashtab(mpt); 14983 } 14984 14985 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL; 14986 psmp = refhash_next(mpt->m_smp_targets, psmp)) { 14987 phy_mask = psmp->m_addr.mta_phymask; 14988 if (phy_mask == phymask) { 14989 smpdip = NULL; 14990 mutex_exit(&mpt->m_mutex); 14991 (void) mptsas_online_smp(pdip, psmp, &smpdip); 14992 mutex_enter(&mpt->m_mutex); 14993 } 14994 } 14995 14996 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 14997 ptgt = refhash_next(mpt->m_targets, ptgt)) { 14998 phy_mask = ptgt->m_addr.mta_phymask; 14999 if (phy_mask == phymask) { 15000 mutex_exit(&mpt->m_mutex); 15001 (void) mptsas_config_target(pdip, ptgt); 15002 mutex_enter(&mpt->m_mutex); 15003 } 15004 } 15005 mutex_exit(&mpt->m_mutex); 15006 } 15007 15008 static int 15009 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt) 15010 { 15011 int rval = DDI_FAILURE; 15012 dev_info_t *tdip; 15013 15014 rval = mptsas_config_luns(pdip, ptgt); 15015 if (rval != DDI_SUCCESS) { 15016 /* 15017 * The return value means the SCMD_REPORT_LUNS 15018 * did not execute successfully. The target maybe 15019 * doesn't support such command. 15020 */ 15021 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt); 15022 } 15023 return (rval); 15024 } 15025 15026 /* 15027 * Return fail if not all the childs/paths are freed. 15028 * if there is any path under the HBA, the return value will be always fail 15029 * because we didn't call mdi_pi_free for path 15030 */ 15031 static int 15032 mptsas_offline_target(dev_info_t *pdip, char *name) 15033 { 15034 dev_info_t *child = NULL, *prechild = NULL; 15035 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 15036 int tmp_rval, rval = DDI_SUCCESS; 15037 char *addr, *cp; 15038 size_t s; 15039 mptsas_t *mpt = DIP2MPT(pdip); 15040 15041 child = ddi_get_child(pdip); 15042 while (child) { 15043 addr = ddi_get_name_addr(child); 15044 prechild = child; 15045 child = ddi_get_next_sibling(child); 15046 15047 if (addr == NULL) { 15048 continue; 15049 } 15050 if ((cp = strchr(addr, ',')) == NULL) { 15051 continue; 15052 } 15053 15054 s = (uintptr_t)cp - (uintptr_t)addr; 15055 15056 if (strncmp(addr, name, s) != 0) { 15057 continue; 15058 } 15059 15060 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL, 15061 NDI_DEVI_REMOVE); 15062 if (tmp_rval != DDI_SUCCESS) { 15063 rval = DDI_FAILURE; 15064 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 15065 prechild, MPTSAS_DEV_GONE) != 15066 DDI_PROP_SUCCESS) { 15067 mptsas_log(mpt, CE_WARN, "mptsas driver " 15068 "unable to create property for " 15069 "SAS %s (MPTSAS_DEV_GONE)", addr); 15070 } 15071 } 15072 } 15073 15074 pip = mdi_get_next_client_path(pdip, NULL); 15075 while (pip) { 15076 addr = MDI_PI(pip)->pi_addr; 15077 savepip = pip; 15078 pip = mdi_get_next_client_path(pdip, pip); 15079 if (addr == NULL) { 15080 continue; 15081 } 15082 15083 if ((cp = strchr(addr, ',')) == NULL) { 15084 continue; 15085 } 15086 15087 s = (uintptr_t)cp - (uintptr_t)addr; 15088 15089 if (strncmp(addr, name, s) != 0) { 15090 continue; 15091 } 15092 15093 (void) mptsas_offline_lun(pdip, NULL, savepip, 15094 NDI_DEVI_REMOVE); 15095 /* 15096 * driver will not invoke mdi_pi_free, so path will not 15097 * be freed forever, return DDI_FAILURE. 15098 */ 15099 rval = DDI_FAILURE; 15100 } 15101 return (rval); 15102 } 15103 15104 static int 15105 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 15106 mdi_pathinfo_t *rpip, uint_t flags) 15107 { 15108 int rval = DDI_FAILURE; 15109 char *devname; 15110 dev_info_t *cdip, *parent; 15111 15112 if (rpip != NULL) { 15113 parent = scsi_vhci_dip; 15114 cdip = mdi_pi_get_client(rpip); 15115 } else if (rdip != NULL) { 15116 parent = pdip; 15117 cdip = rdip; 15118 } else { 15119 return (DDI_FAILURE); 15120 } 15121 15122 /* 15123 * Make sure node is attached otherwise 15124 * it won't have related cache nodes to 15125 * clean up. i_ddi_devi_attached is 15126 * similiar to i_ddi_node_state(cdip) >= 15127 * DS_ATTACHED. 15128 */ 15129 if (i_ddi_devi_attached(cdip)) { 15130 15131 /* Get full devname */ 15132 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 15133 (void) ddi_deviname(cdip, devname); 15134 /* Clean cache */ 15135 (void) devfs_clean(parent, devname + 1, 15136 DV_CLEAN_FORCE); 15137 kmem_free(devname, MAXNAMELEN + 1); 15138 } 15139 if (rpip != NULL) { 15140 if (MDI_PI_IS_OFFLINE(rpip)) { 15141 rval = DDI_SUCCESS; 15142 } else { 15143 rval = mdi_pi_offline(rpip, 0); 15144 } 15145 } else { 15146 rval = ndi_devi_offline(cdip, flags); 15147 } 15148 15149 return (rval); 15150 } 15151 15152 static dev_info_t * 15153 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn) 15154 { 15155 dev_info_t *child = NULL; 15156 char *smp_wwn = NULL; 15157 15158 child = ddi_get_child(parent); 15159 while (child) { 15160 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child, 15161 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn) 15162 != DDI_SUCCESS) { 15163 child = ddi_get_next_sibling(child); 15164 continue; 15165 } 15166 15167 if (strcmp(smp_wwn, str_wwn) == 0) { 15168 ddi_prop_free(smp_wwn); 15169 break; 15170 } 15171 child = ddi_get_next_sibling(child); 15172 ddi_prop_free(smp_wwn); 15173 } 15174 return (child); 15175 } 15176 15177 static int 15178 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags) 15179 { 15180 int rval = DDI_FAILURE; 15181 char *devname; 15182 char wwn_str[MPTSAS_WWN_STRLEN]; 15183 dev_info_t *cdip; 15184 15185 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 15186 15187 cdip = mptsas_find_smp_child(pdip, wwn_str); 15188 15189 if (cdip == NULL) 15190 return (DDI_SUCCESS); 15191 15192 /* 15193 * Make sure node is attached otherwise 15194 * it won't have related cache nodes to 15195 * clean up. i_ddi_devi_attached is 15196 * similiar to i_ddi_node_state(cdip) >= 15197 * DS_ATTACHED. 15198 */ 15199 if (i_ddi_devi_attached(cdip)) { 15200 15201 /* Get full devname */ 15202 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 15203 (void) ddi_deviname(cdip, devname); 15204 /* Clean cache */ 15205 (void) devfs_clean(pdip, devname + 1, 15206 DV_CLEAN_FORCE); 15207 kmem_free(devname, MAXNAMELEN + 1); 15208 } 15209 15210 rval = ndi_devi_offline(cdip, flags); 15211 15212 return (rval); 15213 } 15214 15215 static dev_info_t * 15216 mptsas_find_child(dev_info_t *pdip, char *name) 15217 { 15218 dev_info_t *child = NULL; 15219 char *rname = NULL; 15220 int rval = DDI_FAILURE; 15221 15222 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15223 15224 child = ddi_get_child(pdip); 15225 while (child) { 15226 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN); 15227 if (rval != DDI_SUCCESS) { 15228 child = ddi_get_next_sibling(child); 15229 bzero(rname, SCSI_MAXNAMELEN); 15230 continue; 15231 } 15232 15233 if (strcmp(rname, name) == 0) { 15234 break; 15235 } 15236 child = ddi_get_next_sibling(child); 15237 bzero(rname, SCSI_MAXNAMELEN); 15238 } 15239 15240 kmem_free(rname, SCSI_MAXNAMELEN); 15241 15242 return (child); 15243 } 15244 15245 15246 static dev_info_t * 15247 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun) 15248 { 15249 dev_info_t *child = NULL; 15250 char *name = NULL; 15251 char *addr = NULL; 15252 15253 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15254 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15255 (void) sprintf(name, "%016"PRIx64, sasaddr); 15256 (void) sprintf(addr, "w%s,%x", name, lun); 15257 child = mptsas_find_child(pdip, addr); 15258 kmem_free(name, SCSI_MAXNAMELEN); 15259 kmem_free(addr, SCSI_MAXNAMELEN); 15260 return (child); 15261 } 15262 15263 static dev_info_t * 15264 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy) 15265 { 15266 dev_info_t *child; 15267 char *addr; 15268 15269 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15270 (void) sprintf(addr, "p%x,0", phy); 15271 child = mptsas_find_child(pdip, addr); 15272 kmem_free(addr, SCSI_MAXNAMELEN); 15273 return (child); 15274 } 15275 15276 static mdi_pathinfo_t * 15277 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy) 15278 { 15279 mdi_pathinfo_t *path; 15280 char *addr = NULL; 15281 15282 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15283 (void) sprintf(addr, "p%x,0", phy); 15284 path = mdi_pi_find(pdip, NULL, addr); 15285 kmem_free(addr, SCSI_MAXNAMELEN); 15286 return (path); 15287 } 15288 15289 static mdi_pathinfo_t * 15290 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun) 15291 { 15292 mdi_pathinfo_t *path; 15293 char *name = NULL; 15294 char *addr = NULL; 15295 15296 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15297 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15298 (void) sprintf(name, "%016"PRIx64, sasaddr); 15299 (void) sprintf(addr, "w%s,%x", name, lun); 15300 path = mdi_pi_find(parent, NULL, addr); 15301 kmem_free(name, SCSI_MAXNAMELEN); 15302 kmem_free(addr, SCSI_MAXNAMELEN); 15303 15304 return (path); 15305 } 15306 15307 static int 15308 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 15309 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15310 { 15311 int i = 0; 15312 uchar_t *inq83 = NULL; 15313 int inq83_len1 = 0xFF; 15314 int inq83_len = 0; 15315 int rval = DDI_FAILURE; 15316 ddi_devid_t devid; 15317 char *guid = NULL; 15318 int target = ptgt->m_devhdl; 15319 mdi_pathinfo_t *pip = NULL; 15320 mptsas_t *mpt = DIP2MPT(pdip); 15321 15322 /* 15323 * For DVD/CD ROM and tape devices and optical 15324 * devices, we won't try to enumerate them under 15325 * scsi_vhci, so no need to try page83 15326 */ 15327 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT || 15328 sd_inq->inq_dtype == DTYPE_OPTICAL || 15329 sd_inq->inq_dtype == DTYPE_ESI)) 15330 goto create_lun; 15331 15332 /* 15333 * The LCA returns good SCSI status, but corrupt page 83 data the first 15334 * time it is queried. The solution is to keep trying to request page83 15335 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in 15336 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver 15337 * give up to get VPD page at this stage and fail the enumeration. 15338 */ 15339 15340 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP); 15341 15342 for (i = 0; i < mptsas_inq83_retry_timeout; i++) { 15343 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 15344 inq83_len1, &inq83_len, 1); 15345 if (rval != 0) { 15346 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 15347 "0x83 for target:%x, lun:%x failed!", target, lun); 15348 if (mptsas_physical_bind_failed_page_83 != B_FALSE) 15349 goto create_lun; 15350 goto out; 15351 } 15352 /* 15353 * create DEVID from inquiry data 15354 */ 15355 if ((rval = ddi_devid_scsi_encode( 15356 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq, 15357 sizeof (struct scsi_inquiry), NULL, 0, inq83, 15358 (size_t)inq83_len, &devid)) == DDI_SUCCESS) { 15359 /* 15360 * extract GUID from DEVID 15361 */ 15362 guid = ddi_devid_to_guid(devid); 15363 15364 /* 15365 * Do not enable MPXIO if the strlen(guid) is greater 15366 * than MPTSAS_MAX_GUID_LEN, this constrain would be 15367 * handled by framework later. 15368 */ 15369 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) { 15370 ddi_devid_free_guid(guid); 15371 guid = NULL; 15372 if (mpt->m_mpxio_enable == TRUE) { 15373 mptsas_log(mpt, CE_NOTE, "!Target:%x, " 15374 "lun:%x doesn't have a valid GUID, " 15375 "multipathing for this drive is " 15376 "not enabled", target, lun); 15377 } 15378 } 15379 15380 /* 15381 * devid no longer needed 15382 */ 15383 ddi_devid_free(devid); 15384 break; 15385 } else if (rval == DDI_NOT_WELL_FORMED) { 15386 /* 15387 * return value of ddi_devid_scsi_encode equal to 15388 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth 15389 * to retry inquiry page 0x83 and get GUID. 15390 */ 15391 NDBG20(("Not well formed devid, retry...")); 15392 delay(1 * drv_usectohz(1000000)); 15393 continue; 15394 } else { 15395 mptsas_log(mpt, CE_WARN, "!Encode devid failed for " 15396 "path target:%x, lun:%x", target, lun); 15397 rval = DDI_FAILURE; 15398 goto create_lun; 15399 } 15400 } 15401 15402 if (i == mptsas_inq83_retry_timeout) { 15403 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout " 15404 "for path target:%x, lun:%x", target, lun); 15405 } 15406 15407 rval = DDI_FAILURE; 15408 15409 create_lun: 15410 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) { 15411 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip, 15412 ptgt, lun); 15413 } 15414 if (rval != DDI_SUCCESS) { 15415 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip, 15416 ptgt, lun); 15417 15418 } 15419 out: 15420 if (guid != NULL) { 15421 /* 15422 * guid no longer needed 15423 */ 15424 ddi_devid_free_guid(guid); 15425 } 15426 if (inq83 != NULL) 15427 kmem_free(inq83, inq83_len1); 15428 return (rval); 15429 } 15430 15431 static int 15432 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid, 15433 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun) 15434 { 15435 int target; 15436 char *nodename = NULL; 15437 char **compatible = NULL; 15438 int ncompatible = 0; 15439 int mdi_rtn = MDI_FAILURE; 15440 int rval = DDI_FAILURE; 15441 char *old_guid = NULL; 15442 mptsas_t *mpt = DIP2MPT(pdip); 15443 char *lun_addr = NULL; 15444 char *wwn_str = NULL; 15445 char *attached_wwn_str = NULL; 15446 char *component = NULL; 15447 uint8_t phy = 0xFF; 15448 uint64_t sas_wwn; 15449 int64_t lun64 = 0; 15450 uint32_t devinfo; 15451 uint16_t dev_hdl; 15452 uint16_t pdev_hdl; 15453 uint64_t dev_sas_wwn; 15454 uint64_t pdev_sas_wwn; 15455 uint32_t pdev_info; 15456 uint8_t physport; 15457 uint8_t phy_id; 15458 uint32_t page_address; 15459 uint16_t bay_num, enclosure, io_flags; 15460 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15461 uint32_t dev_info; 15462 15463 mutex_enter(&mpt->m_mutex); 15464 target = ptgt->m_devhdl; 15465 sas_wwn = ptgt->m_addr.mta_wwn; 15466 devinfo = ptgt->m_deviceinfo; 15467 phy = ptgt->m_phynum; 15468 mutex_exit(&mpt->m_mutex); 15469 15470 if (sas_wwn) { 15471 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun); 15472 } else { 15473 *pip = mptsas_find_path_phy(pdip, phy); 15474 } 15475 15476 if (*pip != NULL) { 15477 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15478 ASSERT(*lun_dip != NULL); 15479 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip, 15480 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM), 15481 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) { 15482 if (strncmp(guid, old_guid, strlen(guid)) == 0) { 15483 /* 15484 * Same path back online again. 15485 */ 15486 (void) ddi_prop_free(old_guid); 15487 if ((!MDI_PI_IS_ONLINE(*pip)) && 15488 (!MDI_PI_IS_STANDBY(*pip)) && 15489 (ptgt->m_tgt_unconfigured == 0)) { 15490 rval = mdi_pi_online(*pip, 0); 15491 } else { 15492 rval = DDI_SUCCESS; 15493 } 15494 if (rval != DDI_SUCCESS) { 15495 mptsas_log(mpt, CE_WARN, "path:target: " 15496 "%x, lun:%x online failed!", target, 15497 lun); 15498 *pip = NULL; 15499 *lun_dip = NULL; 15500 } 15501 return (rval); 15502 } else { 15503 /* 15504 * The GUID of the LUN has changed which maybe 15505 * because customer mapped another volume to the 15506 * same LUN. 15507 */ 15508 mptsas_log(mpt, CE_WARN, "The GUID of the " 15509 "target:%x, lun:%x was changed, maybe " 15510 "because someone mapped another volume " 15511 "to the same LUN", target, lun); 15512 (void) ddi_prop_free(old_guid); 15513 if (!MDI_PI_IS_OFFLINE(*pip)) { 15514 rval = mdi_pi_offline(*pip, 0); 15515 if (rval != MDI_SUCCESS) { 15516 mptsas_log(mpt, CE_WARN, "path:" 15517 "target:%x, lun:%x offline " 15518 "failed!", target, lun); 15519 *pip = NULL; 15520 *lun_dip = NULL; 15521 return (DDI_FAILURE); 15522 } 15523 } 15524 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) { 15525 mptsas_log(mpt, CE_WARN, "path:target:" 15526 "%x, lun:%x free failed!", target, 15527 lun); 15528 *pip = NULL; 15529 *lun_dip = NULL; 15530 return (DDI_FAILURE); 15531 } 15532 } 15533 } else { 15534 mptsas_log(mpt, CE_WARN, "Can't get client-guid " 15535 "property for path:target:%x, lun:%x", target, lun); 15536 *pip = NULL; 15537 *lun_dip = NULL; 15538 return (DDI_FAILURE); 15539 } 15540 } 15541 scsi_hba_nodename_compatible_get(inq, NULL, 15542 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible); 15543 15544 /* 15545 * if nodename can't be determined then print a message and skip it 15546 */ 15547 if (nodename == NULL) { 15548 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible " 15549 "driver for target%d lun %d dtype:0x%02x", target, lun, 15550 inq->inq_dtype); 15551 return (DDI_FAILURE); 15552 } 15553 15554 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15555 /* The property is needed by MPAPI */ 15556 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 15557 15558 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15559 if (guid) { 15560 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun); 15561 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15562 } else { 15563 (void) sprintf(lun_addr, "p%x,%x", phy, lun); 15564 (void) sprintf(wwn_str, "p%x", phy); 15565 } 15566 15567 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename, 15568 guid, lun_addr, compatible, ncompatible, 15569 0, pip); 15570 if (mdi_rtn == MDI_SUCCESS) { 15571 15572 if (mdi_prop_update_string(*pip, MDI_GUID, 15573 guid) != DDI_SUCCESS) { 15574 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15575 "create prop for target %d lun %d (MDI_GUID)", 15576 target, lun); 15577 mdi_rtn = MDI_FAILURE; 15578 goto virt_create_done; 15579 } 15580 15581 if (mdi_prop_update_int(*pip, LUN_PROP, 15582 lun) != DDI_SUCCESS) { 15583 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15584 "create prop for target %d lun %d (LUN_PROP)", 15585 target, lun); 15586 mdi_rtn = MDI_FAILURE; 15587 goto virt_create_done; 15588 } 15589 lun64 = (int64_t)lun; 15590 if (mdi_prop_update_int64(*pip, LUN64_PROP, 15591 lun64) != DDI_SUCCESS) { 15592 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15593 "create prop for target %d (LUN64_PROP)", 15594 target); 15595 mdi_rtn = MDI_FAILURE; 15596 goto virt_create_done; 15597 } 15598 if (mdi_prop_update_string_array(*pip, "compatible", 15599 compatible, ncompatible) != 15600 DDI_PROP_SUCCESS) { 15601 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15602 "create prop for target %d lun %d (COMPATIBLE)", 15603 target, lun); 15604 mdi_rtn = MDI_FAILURE; 15605 goto virt_create_done; 15606 } 15607 if (sas_wwn && (mdi_prop_update_string(*pip, 15608 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) { 15609 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15610 "create prop for target %d lun %d " 15611 "(target-port)", target, lun); 15612 mdi_rtn = MDI_FAILURE; 15613 goto virt_create_done; 15614 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip, 15615 "sata-phy", phy) != DDI_PROP_SUCCESS)) { 15616 /* 15617 * Direct attached SATA device without DeviceName 15618 */ 15619 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15620 "create prop for SAS target %d lun %d " 15621 "(sata-phy)", target, lun); 15622 mdi_rtn = MDI_FAILURE; 15623 goto virt_create_done; 15624 } 15625 mutex_enter(&mpt->m_mutex); 15626 15627 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15628 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15629 (uint32_t)ptgt->m_devhdl; 15630 rval = mptsas_get_sas_device_page0(mpt, page_address, 15631 &dev_hdl, &dev_sas_wwn, &dev_info, &physport, 15632 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15633 if (rval != DDI_SUCCESS) { 15634 mutex_exit(&mpt->m_mutex); 15635 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 15636 "parent device for handle %d", page_address); 15637 mdi_rtn = MDI_FAILURE; 15638 goto virt_create_done; 15639 } 15640 15641 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15642 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15643 rval = mptsas_get_sas_device_page0(mpt, page_address, 15644 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15645 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15646 if (rval != DDI_SUCCESS) { 15647 mutex_exit(&mpt->m_mutex); 15648 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15649 "device info for handle %d", page_address); 15650 mdi_rtn = MDI_FAILURE; 15651 goto virt_create_done; 15652 } 15653 15654 mutex_exit(&mpt->m_mutex); 15655 15656 /* 15657 * If this device direct attached to the controller 15658 * set the attached-port to the base wwid 15659 */ 15660 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15661 != DEVINFO_DIRECT_ATTACHED) { 15662 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15663 pdev_sas_wwn); 15664 } else { 15665 /* 15666 * Update the iport's attached-port to guid 15667 */ 15668 if (sas_wwn == 0) { 15669 (void) sprintf(wwn_str, "p%x", phy); 15670 } else { 15671 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15672 } 15673 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15674 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15675 DDI_PROP_SUCCESS) { 15676 mptsas_log(mpt, CE_WARN, 15677 "mptsas unable to create " 15678 "property for iport target-port" 15679 " %s (sas_wwn)", 15680 wwn_str); 15681 mdi_rtn = MDI_FAILURE; 15682 goto virt_create_done; 15683 } 15684 15685 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15686 mpt->un.m_base_wwid); 15687 } 15688 15689 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) { 15690 char uabuf[SCSI_WWN_BUFLEN]; 15691 15692 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 15693 mptsas_log(mpt, CE_WARN, 15694 "mptsas unable to format SATA bridge WWN"); 15695 mdi_rtn = MDI_FAILURE; 15696 goto virt_create_done; 15697 } 15698 15699 if (mdi_prop_update_string(*pip, 15700 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != 15701 DDI_SUCCESS) { 15702 mptsas_log(mpt, CE_WARN, 15703 "mptsas unable to create SCSI bridge port " 15704 "property for SATA device"); 15705 mdi_rtn = MDI_FAILURE; 15706 goto virt_create_done; 15707 } 15708 } 15709 15710 if (mdi_prop_update_string(*pip, 15711 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 15712 DDI_PROP_SUCCESS) { 15713 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15714 "property for iport attached-port %s (sas_wwn)", 15715 attached_wwn_str); 15716 mdi_rtn = MDI_FAILURE; 15717 goto virt_create_done; 15718 } 15719 15720 15721 if (inq->inq_dtype == 0) { 15722 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 15723 /* 15724 * set obp path for pathinfo 15725 */ 15726 (void) snprintf(component, MAXPATHLEN, 15727 "disk@%s", lun_addr); 15728 15729 if (mdi_pi_pathname_obp_set(*pip, component) != 15730 DDI_SUCCESS) { 15731 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 15732 "unable to set obp-path for object %s", 15733 component); 15734 mdi_rtn = MDI_FAILURE; 15735 goto virt_create_done; 15736 } 15737 } 15738 15739 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15740 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 15741 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 15742 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip, 15743 "pm-capable", 1)) != 15744 DDI_PROP_SUCCESS) { 15745 mptsas_log(mpt, CE_WARN, "mptsas driver" 15746 "failed to create pm-capable " 15747 "property, target %d", target); 15748 mdi_rtn = MDI_FAILURE; 15749 goto virt_create_done; 15750 } 15751 } 15752 /* 15753 * Create the phy-num property 15754 */ 15755 if (mdi_prop_update_int(*pip, "phy-num", 15756 ptgt->m_phynum) != DDI_SUCCESS) { 15757 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15758 "create phy-num property for target %d lun %d", 15759 target, lun); 15760 mdi_rtn = MDI_FAILURE; 15761 goto virt_create_done; 15762 } 15763 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr)); 15764 mdi_rtn = mdi_pi_online(*pip, 0); 15765 if (mdi_rtn == MDI_NOT_SUPPORTED) { 15766 mdi_rtn = MDI_FAILURE; 15767 } 15768 virt_create_done: 15769 if (*pip && mdi_rtn != MDI_SUCCESS) { 15770 (void) mdi_pi_free(*pip, 0); 15771 *pip = NULL; 15772 *lun_dip = NULL; 15773 } 15774 } 15775 15776 scsi_hba_nodename_compatible_free(nodename, compatible); 15777 if (lun_addr != NULL) { 15778 kmem_free(lun_addr, SCSI_MAXNAMELEN); 15779 } 15780 if (wwn_str != NULL) { 15781 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 15782 } 15783 if (component != NULL) { 15784 kmem_free(component, MAXPATHLEN); 15785 } 15786 15787 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 15788 } 15789 15790 static int 15791 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq, 15792 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15793 { 15794 int target; 15795 int rval; 15796 int ndi_rtn = NDI_FAILURE; 15797 uint64_t be_sas_wwn; 15798 char *nodename = NULL; 15799 char **compatible = NULL; 15800 int ncompatible = 0; 15801 int instance = 0; 15802 mptsas_t *mpt = DIP2MPT(pdip); 15803 char *wwn_str = NULL; 15804 char *component = NULL; 15805 char *attached_wwn_str = NULL; 15806 uint8_t phy = 0xFF; 15807 uint64_t sas_wwn; 15808 uint32_t devinfo; 15809 uint16_t dev_hdl; 15810 uint16_t pdev_hdl; 15811 uint64_t pdev_sas_wwn; 15812 uint64_t dev_sas_wwn; 15813 uint32_t pdev_info; 15814 uint8_t physport; 15815 uint8_t phy_id; 15816 uint32_t page_address; 15817 uint16_t bay_num, enclosure, io_flags; 15818 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15819 uint32_t dev_info; 15820 int64_t lun64 = 0; 15821 15822 mutex_enter(&mpt->m_mutex); 15823 target = ptgt->m_devhdl; 15824 sas_wwn = ptgt->m_addr.mta_wwn; 15825 devinfo = ptgt->m_deviceinfo; 15826 phy = ptgt->m_phynum; 15827 mutex_exit(&mpt->m_mutex); 15828 15829 /* 15830 * generate compatible property with binding-set "mpt" 15831 */ 15832 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL, 15833 &nodename, &compatible, &ncompatible); 15834 15835 /* 15836 * if nodename can't be determined then print a message and skip it 15837 */ 15838 if (nodename == NULL) { 15839 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver " 15840 "for target %d lun %d", target, lun); 15841 return (DDI_FAILURE); 15842 } 15843 15844 ndi_rtn = ndi_devi_alloc(pdip, nodename, 15845 DEVI_SID_NODEID, lun_dip); 15846 15847 /* 15848 * if lun alloc success, set props 15849 */ 15850 if (ndi_rtn == NDI_SUCCESS) { 15851 15852 if (ndi_prop_update_int(DDI_DEV_T_NONE, 15853 *lun_dip, LUN_PROP, lun) != 15854 DDI_PROP_SUCCESS) { 15855 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15856 "property for target %d lun %d (LUN_PROP)", 15857 target, lun); 15858 ndi_rtn = NDI_FAILURE; 15859 goto phys_create_done; 15860 } 15861 15862 lun64 = (int64_t)lun; 15863 if (ndi_prop_update_int64(DDI_DEV_T_NONE, 15864 *lun_dip, LUN64_PROP, lun64) != 15865 DDI_PROP_SUCCESS) { 15866 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15867 "property for target %d lun64 %d (LUN64_PROP)", 15868 target, lun); 15869 ndi_rtn = NDI_FAILURE; 15870 goto phys_create_done; 15871 } 15872 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, 15873 *lun_dip, "compatible", compatible, ncompatible) 15874 != DDI_PROP_SUCCESS) { 15875 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15876 "property for target %d lun %d (COMPATIBLE)", 15877 target, lun); 15878 ndi_rtn = NDI_FAILURE; 15879 goto phys_create_done; 15880 } 15881 15882 /* 15883 * We need the SAS WWN for non-multipath devices, so 15884 * we'll use the same property as that multipathing 15885 * devices need to present for MPAPI. If we don't have 15886 * a WWN (e.g. parallel SCSI), don't create the prop. 15887 */ 15888 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15889 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15890 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE, 15891 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) 15892 != DDI_PROP_SUCCESS) { 15893 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15894 "create property for SAS target %d lun %d " 15895 "(target-port)", target, lun); 15896 ndi_rtn = NDI_FAILURE; 15897 goto phys_create_done; 15898 } 15899 15900 be_sas_wwn = BE_64(sas_wwn); 15901 if (sas_wwn && ndi_prop_update_byte_array( 15902 DDI_DEV_T_NONE, *lun_dip, "port-wwn", 15903 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) { 15904 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15905 "create property for SAS target %d lun %d " 15906 "(port-wwn)", target, lun); 15907 ndi_rtn = NDI_FAILURE; 15908 goto phys_create_done; 15909 } else if ((sas_wwn == 0) && (ndi_prop_update_int( 15910 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) != 15911 DDI_PROP_SUCCESS)) { 15912 /* 15913 * Direct attached SATA device without DeviceName 15914 */ 15915 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15916 "create property for SAS target %d lun %d " 15917 "(sata-phy)", target, lun); 15918 ndi_rtn = NDI_FAILURE; 15919 goto phys_create_done; 15920 } 15921 15922 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 15923 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) { 15924 mptsas_log(mpt, CE_WARN, "mptsas unable to" 15925 "create property for SAS target %d lun %d" 15926 " (SAS_PROP)", target, lun); 15927 ndi_rtn = NDI_FAILURE; 15928 goto phys_create_done; 15929 } 15930 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE, 15931 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) { 15932 mptsas_log(mpt, CE_WARN, "mptsas unable " 15933 "to create guid property for target %d " 15934 "lun %d", target, lun); 15935 ndi_rtn = NDI_FAILURE; 15936 goto phys_create_done; 15937 } 15938 15939 /* 15940 * The following code is to set properties for SM-HBA support, 15941 * it doesn't apply to RAID volumes 15942 */ 15943 if (ptgt->m_addr.mta_phymask == 0) 15944 goto phys_raid_lun; 15945 15946 mutex_enter(&mpt->m_mutex); 15947 15948 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15949 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15950 (uint32_t)ptgt->m_devhdl; 15951 rval = mptsas_get_sas_device_page0(mpt, page_address, 15952 &dev_hdl, &dev_sas_wwn, &dev_info, 15953 &physport, &phy_id, &pdev_hdl, 15954 &bay_num, &enclosure, &io_flags); 15955 if (rval != DDI_SUCCESS) { 15956 mutex_exit(&mpt->m_mutex); 15957 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15958 "parent device for handle %d.", page_address); 15959 ndi_rtn = NDI_FAILURE; 15960 goto phys_create_done; 15961 } 15962 15963 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15964 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15965 rval = mptsas_get_sas_device_page0(mpt, page_address, 15966 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15967 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15968 if (rval != DDI_SUCCESS) { 15969 mutex_exit(&mpt->m_mutex); 15970 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15971 "device for handle %d.", page_address); 15972 ndi_rtn = NDI_FAILURE; 15973 goto phys_create_done; 15974 } 15975 15976 mutex_exit(&mpt->m_mutex); 15977 15978 /* 15979 * If this device direct attached to the controller 15980 * set the attached-port to the base wwid 15981 */ 15982 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15983 != DEVINFO_DIRECT_ATTACHED) { 15984 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15985 pdev_sas_wwn); 15986 } else { 15987 /* 15988 * Update the iport's attached-port to guid 15989 */ 15990 if (sas_wwn == 0) { 15991 (void) sprintf(wwn_str, "p%x", phy); 15992 } else { 15993 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15994 } 15995 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15996 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15997 DDI_PROP_SUCCESS) { 15998 mptsas_log(mpt, CE_WARN, 15999 "mptsas unable to create " 16000 "property for iport target-port" 16001 " %s (sas_wwn)", 16002 wwn_str); 16003 ndi_rtn = NDI_FAILURE; 16004 goto phys_create_done; 16005 } 16006 16007 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 16008 mpt->un.m_base_wwid); 16009 } 16010 16011 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16012 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 16013 DDI_PROP_SUCCESS) { 16014 mptsas_log(mpt, CE_WARN, 16015 "mptsas unable to create " 16016 "property for iport attached-port %s (sas_wwn)", 16017 attached_wwn_str); 16018 ndi_rtn = NDI_FAILURE; 16019 goto phys_create_done; 16020 } 16021 16022 if (IS_SATA_DEVICE(dev_info)) { 16023 char uabuf[SCSI_WWN_BUFLEN]; 16024 16025 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16026 *lun_dip, MPTSAS_VARIANT, "sata") != 16027 DDI_PROP_SUCCESS) { 16028 mptsas_log(mpt, CE_WARN, 16029 "mptsas unable to create " 16030 "property for device variant "); 16031 ndi_rtn = NDI_FAILURE; 16032 goto phys_create_done; 16033 } 16034 16035 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 16036 mptsas_log(mpt, CE_WARN, 16037 "mptsas unable to format SATA bridge WWN"); 16038 ndi_rtn = NDI_FAILURE; 16039 goto phys_create_done; 16040 } 16041 16042 if (ndi_prop_update_string(DDI_DEV_T_NONE, *lun_dip, 16043 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != 16044 DDI_PROP_SUCCESS) { 16045 mptsas_log(mpt, CE_WARN, 16046 "mptsas unable to create SCSI bridge port " 16047 "property for SATA device"); 16048 ndi_rtn = NDI_FAILURE; 16049 goto phys_create_done; 16050 } 16051 } 16052 16053 if (IS_ATAPI_DEVICE(dev_info)) { 16054 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16055 *lun_dip, MPTSAS_VARIANT, "atapi") != 16056 DDI_PROP_SUCCESS) { 16057 mptsas_log(mpt, CE_WARN, 16058 "mptsas unable to create " 16059 "property for device variant "); 16060 ndi_rtn = NDI_FAILURE; 16061 goto phys_create_done; 16062 } 16063 } 16064 16065 phys_raid_lun: 16066 /* 16067 * if this is a SAS controller, and the target is a SATA 16068 * drive, set the 'pm-capable' property for sd and if on 16069 * an OPL platform, also check if this is an ATAPI 16070 * device. 16071 */ 16072 instance = ddi_get_instance(mpt->m_dip); 16073 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 16074 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 16075 NDBG2(("mptsas%d: creating pm-capable property, " 16076 "target %d", instance, target)); 16077 16078 if ((ndi_prop_update_int(DDI_DEV_T_NONE, 16079 *lun_dip, "pm-capable", 1)) != 16080 DDI_PROP_SUCCESS) { 16081 mptsas_log(mpt, CE_WARN, "mptsas " 16082 "failed to create pm-capable " 16083 "property, target %d", target); 16084 ndi_rtn = NDI_FAILURE; 16085 goto phys_create_done; 16086 } 16087 16088 } 16089 16090 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) { 16091 /* 16092 * add 'obp-path' properties for devinfo 16093 */ 16094 bzero(wwn_str, sizeof (wwn_str)); 16095 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 16096 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 16097 if (guid) { 16098 (void) snprintf(component, MAXPATHLEN, 16099 "disk@w%s,%x", wwn_str, lun); 16100 } else { 16101 (void) snprintf(component, MAXPATHLEN, 16102 "disk@p%x,%x", phy, lun); 16103 } 16104 if (ddi_pathname_obp_set(*lun_dip, component) 16105 != DDI_SUCCESS) { 16106 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 16107 "unable to set obp-path for SAS " 16108 "object %s", component); 16109 ndi_rtn = NDI_FAILURE; 16110 goto phys_create_done; 16111 } 16112 } 16113 /* 16114 * Create the phy-num property for non-raid disk 16115 */ 16116 if (ptgt->m_addr.mta_phymask != 0) { 16117 if (ndi_prop_update_int(DDI_DEV_T_NONE, 16118 *lun_dip, "phy-num", ptgt->m_phynum) != 16119 DDI_PROP_SUCCESS) { 16120 mptsas_log(mpt, CE_WARN, "mptsas driver " 16121 "failed to create phy-num property for " 16122 "target %d", target); 16123 ndi_rtn = NDI_FAILURE; 16124 goto phys_create_done; 16125 } 16126 } 16127 phys_create_done: 16128 /* 16129 * If props were setup ok, online the lun 16130 */ 16131 if (ndi_rtn == NDI_SUCCESS) { 16132 /* 16133 * Try to online the new node 16134 */ 16135 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH); 16136 } 16137 16138 /* 16139 * If success set rtn flag, else unwire alloc'd lun 16140 */ 16141 if (ndi_rtn != NDI_SUCCESS) { 16142 NDBG12(("mptsas driver unable to online " 16143 "target %d lun %d", target, lun)); 16144 ndi_prop_remove_all(*lun_dip); 16145 (void) ndi_devi_free(*lun_dip); 16146 *lun_dip = NULL; 16147 } 16148 } 16149 16150 scsi_hba_nodename_compatible_free(nodename, compatible); 16151 16152 if (wwn_str != NULL) { 16153 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 16154 } 16155 if (component != NULL) { 16156 kmem_free(component, MAXPATHLEN); 16157 } 16158 16159 16160 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 16161 } 16162 16163 static int 16164 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn) 16165 { 16166 mptsas_t *mpt = DIP2MPT(pdip); 16167 struct smp_device smp_sd; 16168 16169 /* XXX An HBA driver should not be allocating an smp_device. */ 16170 bzero(&smp_sd, sizeof (struct smp_device)); 16171 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran; 16172 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE); 16173 16174 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS) 16175 return (NDI_FAILURE); 16176 return (NDI_SUCCESS); 16177 } 16178 16179 static int 16180 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip) 16181 { 16182 mptsas_t *mpt = DIP2MPT(pdip); 16183 mptsas_smp_t *psmp = NULL; 16184 int rval; 16185 int phymask; 16186 16187 /* 16188 * Get the physical port associated to the iport 16189 * PHYMASK TODO 16190 */ 16191 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 16192 "phymask", 0); 16193 /* 16194 * Find the smp node in hash table with specified sas address and 16195 * physical port 16196 */ 16197 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn); 16198 if (psmp == NULL) { 16199 return (DDI_FAILURE); 16200 } 16201 16202 rval = mptsas_online_smp(pdip, psmp, smp_dip); 16203 16204 return (rval); 16205 } 16206 16207 static int 16208 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 16209 dev_info_t **smp_dip) 16210 { 16211 char wwn_str[MPTSAS_WWN_STRLEN]; 16212 char attached_wwn_str[MPTSAS_WWN_STRLEN]; 16213 int ndi_rtn = NDI_FAILURE; 16214 int rval = 0; 16215 mptsas_smp_t dev_info; 16216 uint32_t page_address; 16217 mptsas_t *mpt = DIP2MPT(pdip); 16218 uint16_t dev_hdl; 16219 uint64_t sas_wwn; 16220 uint64_t smp_sas_wwn; 16221 uint8_t physport; 16222 uint8_t phy_id; 16223 uint16_t pdev_hdl; 16224 uint8_t numphys = 0; 16225 uint16_t i = 0; 16226 char phymask[MPTSAS_MAX_PHYS]; 16227 char *iport = NULL; 16228 mptsas_phymask_t phy_mask = 0; 16229 uint16_t attached_devhdl; 16230 uint16_t bay_num, enclosure, io_flags; 16231 16232 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 16233 16234 /* 16235 * Probe smp device, prevent the node of removed device from being 16236 * configured succesfully 16237 */ 16238 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) { 16239 return (DDI_FAILURE); 16240 } 16241 16242 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) { 16243 return (DDI_SUCCESS); 16244 } 16245 16246 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip); 16247 16248 /* 16249 * if lun alloc success, set props 16250 */ 16251 if (ndi_rtn == NDI_SUCCESS) { 16252 /* 16253 * Set the flavor of the child to be SMP flavored 16254 */ 16255 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP); 16256 16257 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16258 *smp_dip, SMP_WWN, wwn_str) != 16259 DDI_PROP_SUCCESS) { 16260 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16261 "property for smp device %s (sas_wwn)", 16262 wwn_str); 16263 ndi_rtn = NDI_FAILURE; 16264 goto smp_create_done; 16265 } 16266 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn); 16267 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16268 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != 16269 DDI_PROP_SUCCESS) { 16270 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16271 "property for iport target-port %s (sas_wwn)", 16272 wwn_str); 16273 ndi_rtn = NDI_FAILURE; 16274 goto smp_create_done; 16275 } 16276 16277 mutex_enter(&mpt->m_mutex); 16278 16279 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 16280 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl; 16281 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16282 &dev_info); 16283 if (rval != DDI_SUCCESS) { 16284 mutex_exit(&mpt->m_mutex); 16285 mptsas_log(mpt, CE_WARN, 16286 "mptsas unable to get expander " 16287 "parent device info for %x", page_address); 16288 ndi_rtn = NDI_FAILURE; 16289 goto smp_create_done; 16290 } 16291 16292 smp_node->m_pdevhdl = dev_info.m_pdevhdl; 16293 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16294 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16295 (uint32_t)dev_info.m_pdevhdl; 16296 rval = mptsas_get_sas_device_page0(mpt, page_address, 16297 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport, 16298 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 16299 if (rval != DDI_SUCCESS) { 16300 mutex_exit(&mpt->m_mutex); 16301 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16302 "device info for %x", page_address); 16303 ndi_rtn = NDI_FAILURE; 16304 goto smp_create_done; 16305 } 16306 16307 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16308 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16309 (uint32_t)dev_info.m_devhdl; 16310 rval = mptsas_get_sas_device_page0(mpt, page_address, 16311 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo, 16312 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure, 16313 &io_flags); 16314 if (rval != DDI_SUCCESS) { 16315 mutex_exit(&mpt->m_mutex); 16316 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16317 "device info for %x", page_address); 16318 ndi_rtn = NDI_FAILURE; 16319 goto smp_create_done; 16320 } 16321 mutex_exit(&mpt->m_mutex); 16322 16323 /* 16324 * If this smp direct attached to the controller 16325 * set the attached-port to the base wwid 16326 */ 16327 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16328 != DEVINFO_DIRECT_ATTACHED) { 16329 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16330 sas_wwn); 16331 } else { 16332 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16333 mpt->un.m_base_wwid); 16334 } 16335 16336 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16337 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) != 16338 DDI_PROP_SUCCESS) { 16339 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16340 "property for smp attached-port %s (sas_wwn)", 16341 attached_wwn_str); 16342 ndi_rtn = NDI_FAILURE; 16343 goto smp_create_done; 16344 } 16345 16346 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 16347 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) { 16348 mptsas_log(mpt, CE_WARN, "mptsas unable to " 16349 "create property for SMP %s (SMP_PROP) ", 16350 wwn_str); 16351 ndi_rtn = NDI_FAILURE; 16352 goto smp_create_done; 16353 } 16354 16355 /* 16356 * check the smp to see whether it direct 16357 * attached to the controller 16358 */ 16359 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16360 != DEVINFO_DIRECT_ATTACHED) { 16361 goto smp_create_done; 16362 } 16363 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 16364 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1); 16365 if (numphys > 0) { 16366 goto smp_create_done; 16367 } 16368 /* 16369 * this iport is an old iport, we need to 16370 * reconfig the props for it. 16371 */ 16372 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16373 MPTSAS_VIRTUAL_PORT, 0) != 16374 DDI_PROP_SUCCESS) { 16375 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16376 MPTSAS_VIRTUAL_PORT); 16377 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 16378 "prop update failed"); 16379 goto smp_create_done; 16380 } 16381 16382 mutex_enter(&mpt->m_mutex); 16383 numphys = 0; 16384 iport = ddi_get_name_addr(pdip); 16385 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16386 bzero(phymask, sizeof (phymask)); 16387 (void) sprintf(phymask, 16388 "%x", mpt->m_phy_info[i].phy_mask); 16389 if (strcmp(phymask, iport) == 0) { 16390 phy_mask = mpt->m_phy_info[i].phy_mask; 16391 break; 16392 } 16393 } 16394 16395 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16396 if ((phy_mask >> i) & 0x01) { 16397 numphys++; 16398 } 16399 } 16400 /* 16401 * Update PHY info for smhba 16402 */ 16403 if (mptsas_smhba_phy_init(mpt)) { 16404 mutex_exit(&mpt->m_mutex); 16405 mptsas_log(mpt, CE_WARN, "mptsas phy update " 16406 "failed"); 16407 goto smp_create_done; 16408 } 16409 mutex_exit(&mpt->m_mutex); 16410 16411 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask, 16412 &attached_devhdl); 16413 16414 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16415 MPTSAS_NUM_PHYS, numphys) != 16416 DDI_PROP_SUCCESS) { 16417 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16418 MPTSAS_NUM_PHYS); 16419 mptsas_log(mpt, CE_WARN, "mptsas update " 16420 "num phys props failed"); 16421 goto smp_create_done; 16422 } 16423 /* 16424 * Add parent's props for SMHBA support 16425 */ 16426 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip, 16427 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 16428 DDI_PROP_SUCCESS) { 16429 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16430 SCSI_ADDR_PROP_ATTACHED_PORT); 16431 mptsas_log(mpt, CE_WARN, "mptsas update iport" 16432 "attached-port failed"); 16433 goto smp_create_done; 16434 } 16435 16436 smp_create_done: 16437 /* 16438 * If props were setup ok, online the lun 16439 */ 16440 if (ndi_rtn == NDI_SUCCESS) { 16441 /* 16442 * Try to online the new node 16443 */ 16444 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH); 16445 } 16446 16447 /* 16448 * If success set rtn flag, else unwire alloc'd lun 16449 */ 16450 if (ndi_rtn != NDI_SUCCESS) { 16451 NDBG12(("mptsas unable to online " 16452 "SMP target %s", wwn_str)); 16453 ndi_prop_remove_all(*smp_dip); 16454 (void) ndi_devi_free(*smp_dip); 16455 } 16456 } 16457 16458 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 16459 } 16460 16461 /* smp transport routine */ 16462 static int mptsas_smp_start(struct smp_pkt *smp_pkt) 16463 { 16464 uint64_t wwn; 16465 Mpi2SmpPassthroughRequest_t req; 16466 Mpi2SmpPassthroughReply_t rep; 16467 uint32_t direction = 0; 16468 mptsas_t *mpt; 16469 int ret; 16470 uint64_t tmp64; 16471 16472 mpt = (mptsas_t *)smp_pkt->smp_pkt_address-> 16473 smp_a_hba_tran->smp_tran_hba_private; 16474 16475 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE); 16476 /* 16477 * Need to compose a SMP request message 16478 * and call mptsas_do_passthru() function 16479 */ 16480 bzero(&req, sizeof (req)); 16481 bzero(&rep, sizeof (rep)); 16482 req.PassthroughFlags = 0; 16483 req.PhysicalPort = 0xff; 16484 req.ChainOffset = 0; 16485 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH; 16486 16487 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) { 16488 smp_pkt->smp_pkt_reason = ERANGE; 16489 return (DDI_FAILURE); 16490 } 16491 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4)); 16492 16493 req.MsgFlags = 0; 16494 tmp64 = LE_64(wwn); 16495 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE); 16496 if (smp_pkt->smp_pkt_rspsize > 0) { 16497 direction |= MPTSAS_PASS_THRU_DIRECTION_READ; 16498 } 16499 if (smp_pkt->smp_pkt_reqsize > 0) { 16500 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE; 16501 } 16502 16503 mutex_enter(&mpt->m_mutex); 16504 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, 16505 (uint8_t *)smp_pkt->smp_pkt_rsp, 16506 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep), 16507 smp_pkt->smp_pkt_rspsize - 4, direction, 16508 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4, 16509 smp_pkt->smp_pkt_timeout, FKIOCTL); 16510 mutex_exit(&mpt->m_mutex); 16511 if (ret != 0) { 16512 cmn_err(CE_WARN, "smp_start do passthru error %d", ret); 16513 smp_pkt->smp_pkt_reason = (uchar_t)(ret); 16514 return (DDI_FAILURE); 16515 } 16516 /* do passthrough success, check the smp status */ 16517 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16518 switch (LE_16(rep.IOCStatus)) { 16519 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 16520 smp_pkt->smp_pkt_reason = ENODEV; 16521 break; 16522 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 16523 smp_pkt->smp_pkt_reason = EOVERFLOW; 16524 break; 16525 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 16526 smp_pkt->smp_pkt_reason = EIO; 16527 break; 16528 default: 16529 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc" 16530 "status:%x", LE_16(rep.IOCStatus)); 16531 smp_pkt->smp_pkt_reason = EIO; 16532 break; 16533 } 16534 return (DDI_FAILURE); 16535 } 16536 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) { 16537 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x", 16538 rep.SASStatus); 16539 smp_pkt->smp_pkt_reason = EIO; 16540 return (DDI_FAILURE); 16541 } 16542 16543 return (DDI_SUCCESS); 16544 } 16545 16546 /* 16547 * If we didn't get a match, we need to get sas page0 for each device, and 16548 * untill we get a match. If failed, return NULL 16549 */ 16550 static mptsas_target_t * 16551 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy) 16552 { 16553 int i, j = 0; 16554 int rval = 0; 16555 uint16_t cur_handle; 16556 uint32_t page_address; 16557 mptsas_target_t *ptgt = NULL; 16558 16559 /* 16560 * PHY named device must be direct attached and attaches to 16561 * narrow port, if the iport is not parent of the device which 16562 * we are looking for. 16563 */ 16564 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16565 if ((1 << i) & phymask) 16566 j++; 16567 } 16568 16569 if (j > 1) 16570 return (NULL); 16571 16572 /* 16573 * Must be a narrow port and single device attached to the narrow port 16574 * So the physical port num of device which is equal to the iport's 16575 * port num is the device what we are looking for. 16576 */ 16577 16578 if (mpt->m_phy_info[phy].phy_mask != phymask) 16579 return (NULL); 16580 16581 mutex_enter(&mpt->m_mutex); 16582 16583 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn, 16584 &phy); 16585 if (ptgt != NULL) { 16586 mutex_exit(&mpt->m_mutex); 16587 return (ptgt); 16588 } 16589 16590 if (mpt->m_done_traverse_dev) { 16591 mutex_exit(&mpt->m_mutex); 16592 return (NULL); 16593 } 16594 16595 /* If didn't get a match, come here */ 16596 cur_handle = mpt->m_dev_handle; 16597 for (; ; ) { 16598 ptgt = NULL; 16599 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16600 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16601 rval = mptsas_get_target_device_info(mpt, page_address, 16602 &cur_handle, &ptgt); 16603 if ((rval == DEV_INFO_FAIL_PAGE0) || 16604 (rval == DEV_INFO_FAIL_ALLOC) || 16605 (rval == DEV_INFO_FAIL_GUID)) { 16606 break; 16607 } 16608 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16609 (rval == DEV_INFO_PHYS_DISK)) { 16610 continue; 16611 } 16612 mpt->m_dev_handle = cur_handle; 16613 16614 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) { 16615 break; 16616 } 16617 } 16618 16619 mutex_exit(&mpt->m_mutex); 16620 return (ptgt); 16621 } 16622 16623 /* 16624 * The ptgt->m_addr.mta_wwn contains the wwid for each disk. 16625 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid 16626 * If we didn't get a match, we need to get sas page0 for each device, and 16627 * untill we get a match 16628 * If failed, return NULL 16629 */ 16630 static mptsas_target_t * 16631 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16632 { 16633 int rval = 0; 16634 uint16_t cur_handle; 16635 uint32_t page_address; 16636 mptsas_target_t *tmp_tgt = NULL; 16637 mptsas_target_addr_t addr; 16638 16639 addr.mta_wwn = wwid; 16640 addr.mta_phymask = phymask; 16641 mutex_enter(&mpt->m_mutex); 16642 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16643 if (tmp_tgt != NULL) { 16644 mutex_exit(&mpt->m_mutex); 16645 return (tmp_tgt); 16646 } 16647 16648 if (phymask == 0) { 16649 /* 16650 * It's IR volume 16651 */ 16652 rval = mptsas_get_raid_info(mpt); 16653 if (rval) { 16654 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16655 } 16656 mutex_exit(&mpt->m_mutex); 16657 return (tmp_tgt); 16658 } 16659 16660 if (mpt->m_done_traverse_dev) { 16661 mutex_exit(&mpt->m_mutex); 16662 return (NULL); 16663 } 16664 16665 /* If didn't get a match, come here */ 16666 cur_handle = mpt->m_dev_handle; 16667 for (;;) { 16668 tmp_tgt = NULL; 16669 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16670 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle; 16671 rval = mptsas_get_target_device_info(mpt, page_address, 16672 &cur_handle, &tmp_tgt); 16673 if ((rval == DEV_INFO_FAIL_PAGE0) || 16674 (rval == DEV_INFO_FAIL_ALLOC) || 16675 (rval == DEV_INFO_FAIL_GUID)) { 16676 tmp_tgt = NULL; 16677 break; 16678 } 16679 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16680 (rval == DEV_INFO_PHYS_DISK)) { 16681 continue; 16682 } 16683 mpt->m_dev_handle = cur_handle; 16684 if ((tmp_tgt->m_addr.mta_wwn) && 16685 (tmp_tgt->m_addr.mta_wwn == wwid) && 16686 (tmp_tgt->m_addr.mta_phymask == phymask)) { 16687 break; 16688 } 16689 } 16690 16691 mutex_exit(&mpt->m_mutex); 16692 return (tmp_tgt); 16693 } 16694 16695 static mptsas_smp_t * 16696 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16697 { 16698 int rval = 0; 16699 uint16_t cur_handle; 16700 uint32_t page_address; 16701 mptsas_smp_t smp_node, *psmp = NULL; 16702 mptsas_target_addr_t addr; 16703 16704 addr.mta_wwn = wwid; 16705 addr.mta_phymask = phymask; 16706 mutex_enter(&mpt->m_mutex); 16707 psmp = refhash_lookup(mpt->m_smp_targets, &addr); 16708 if (psmp != NULL) { 16709 mutex_exit(&mpt->m_mutex); 16710 return (psmp); 16711 } 16712 16713 if (mpt->m_done_traverse_smp) { 16714 mutex_exit(&mpt->m_mutex); 16715 return (NULL); 16716 } 16717 16718 /* If didn't get a match, come here */ 16719 cur_handle = mpt->m_smp_devhdl; 16720 for (;;) { 16721 psmp = NULL; 16722 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 16723 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16724 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16725 &smp_node); 16726 if (rval != DDI_SUCCESS) { 16727 break; 16728 } 16729 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl; 16730 psmp = mptsas_smp_alloc(mpt, &smp_node); 16731 ASSERT(psmp); 16732 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) && 16733 (psmp->m_addr.mta_phymask == phymask)) { 16734 break; 16735 } 16736 } 16737 16738 mutex_exit(&mpt->m_mutex); 16739 return (psmp); 16740 } 16741 16742 mptsas_target_t * 16743 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid, 16744 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum) 16745 { 16746 mptsas_target_t *tmp_tgt = NULL; 16747 mptsas_target_addr_t addr; 16748 16749 addr.mta_wwn = wwid; 16750 addr.mta_phymask = phymask; 16751 tmp_tgt = refhash_lookup(refhash, &addr); 16752 if (tmp_tgt != NULL) { 16753 NDBG20(("Hash item already exist")); 16754 tmp_tgt->m_deviceinfo = devinfo; 16755 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */ 16756 return (tmp_tgt); 16757 } 16758 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP); 16759 if (tmp_tgt == NULL) { 16760 cmn_err(CE_WARN, "Fatal, allocated tgt failed"); 16761 return (NULL); 16762 } 16763 tmp_tgt->m_devhdl = devhdl; 16764 tmp_tgt->m_addr.mta_wwn = wwid; 16765 tmp_tgt->m_deviceinfo = devinfo; 16766 tmp_tgt->m_addr.mta_phymask = phymask; 16767 tmp_tgt->m_phynum = phynum; 16768 /* Initialized the tgt structure */ 16769 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 16770 tmp_tgt->m_qfull_retry_interval = 16771 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 16772 tmp_tgt->m_t_throttle = MAX_THROTTLE; 16773 TAILQ_INIT(&tmp_tgt->m_active_cmdq); 16774 16775 refhash_insert(refhash, tmp_tgt); 16776 16777 return (tmp_tgt); 16778 } 16779 16780 static void 16781 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst) 16782 { 16783 dst->m_devhdl = src->m_devhdl; 16784 dst->m_deviceinfo = src->m_deviceinfo; 16785 dst->m_pdevhdl = src->m_pdevhdl; 16786 dst->m_pdevinfo = src->m_pdevinfo; 16787 } 16788 16789 static mptsas_smp_t * 16790 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data) 16791 { 16792 mptsas_target_addr_t addr; 16793 mptsas_smp_t *ret_data; 16794 16795 addr.mta_wwn = data->m_addr.mta_wwn; 16796 addr.mta_phymask = data->m_addr.mta_phymask; 16797 ret_data = refhash_lookup(mpt->m_smp_targets, &addr); 16798 /* 16799 * If there's already a matching SMP target, update its fields 16800 * in place. Since the address is not changing, it's safe to do 16801 * this. We cannot just bcopy() here because the structure we've 16802 * been given has invalid hash links. 16803 */ 16804 if (ret_data != NULL) { 16805 mptsas_smp_target_copy(data, ret_data); 16806 return (ret_data); 16807 } 16808 16809 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP); 16810 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 16811 refhash_insert(mpt->m_smp_targets, ret_data); 16812 return (ret_data); 16813 } 16814 16815 /* 16816 * Functions for SGPIO LED support 16817 */ 16818 static dev_info_t * 16819 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask) 16820 { 16821 dev_info_t *dip; 16822 int prop; 16823 dip = e_ddi_hold_devi_by_dev(dev, 0); 16824 if (dip == NULL) 16825 return (dip); 16826 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 16827 "phymask", 0); 16828 *phymask = (mptsas_phymask_t)prop; 16829 ddi_release_devi(dip); 16830 return (dip); 16831 } 16832 static mptsas_target_t * 16833 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask) 16834 { 16835 uint8_t phynum; 16836 uint64_t wwn; 16837 int lun; 16838 mptsas_target_t *ptgt = NULL; 16839 16840 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) { 16841 return (NULL); 16842 } 16843 if (addr[0] == 'w') { 16844 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn); 16845 } else { 16846 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum); 16847 } 16848 return (ptgt); 16849 } 16850 16851 static int 16852 mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx) 16853 { 16854 uint32_t slotstatus = 0; 16855 16856 ASSERT3U(idx, <, mep->me_nslots); 16857 16858 /* Build an MPI2 Slot Status based on our view of the world */ 16859 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1))) 16860 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST; 16861 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1))) 16862 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT; 16863 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1))) 16864 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE; 16865 16866 /* Write it to the controller */ 16867 NDBG14(("mptsas_ioctl: set LED status %x for slot %x", 16868 slotstatus, idx + mep->me_fslot)); 16869 return (mptsas_send_sep(mpt, mep, idx, &slotstatus, 16870 MPI2_SEP_REQ_ACTION_WRITE_STATUS)); 16871 } 16872 16873 /* 16874 * send sep request, use enclosure/slot addressing 16875 */ 16876 static int 16877 mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx, 16878 uint32_t *status, uint8_t act) 16879 { 16880 Mpi2SepRequest_t req; 16881 Mpi2SepReply_t rep; 16882 int ret; 16883 uint16_t enctype; 16884 uint16_t slot; 16885 16886 ASSERT(mutex_owned(&mpt->m_mutex)); 16887 16888 /* 16889 * Look through the enclosures and make sure that this enclosure is 16890 * something that is directly attached device. If we didn't find an 16891 * enclosure for this device, don't send the ioctl. 16892 */ 16893 enctype = mep->me_flags & MPI2_SAS_ENCLS0_FLAGS_MNG_MASK; 16894 if (enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES && 16895 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO && 16896 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO) { 16897 return (ENOTTY); 16898 } 16899 slot = idx + mep->me_fslot; 16900 16901 bzero(&req, sizeof (req)); 16902 bzero(&rep, sizeof (rep)); 16903 16904 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR; 16905 req.Action = act; 16906 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS; 16907 req.EnclosureHandle = LE_16(mep->me_enchdl); 16908 req.Slot = LE_16(slot); 16909 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16910 req.SlotStatus = LE_32(*status); 16911 } 16912 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 16913 sizeof (req), sizeof (rep), 0, MPTSAS_PASS_THRU_DIRECTION_NONE, 16914 NULL, 0, 60, FKIOCTL); 16915 if (ret != 0) { 16916 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP " 16917 "Processor Request message error %d", ret); 16918 return (ret); 16919 } 16920 /* do passthrough success, check the ioc status */ 16921 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16922 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc " 16923 "status:%x loginfo %x", act, LE_16(rep.IOCStatus), 16924 LE_32(rep.IOCLogInfo)); 16925 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) { 16926 case MPI2_IOCSTATUS_INVALID_FUNCTION: 16927 case MPI2_IOCSTATUS_INVALID_VPID: 16928 case MPI2_IOCSTATUS_INVALID_FIELD: 16929 case MPI2_IOCSTATUS_INVALID_STATE: 16930 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 16931 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 16932 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 16933 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 16934 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 16935 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 16936 return (EINVAL); 16937 case MPI2_IOCSTATUS_BUSY: 16938 return (EBUSY); 16939 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 16940 return (EAGAIN); 16941 case MPI2_IOCSTATUS_INVALID_SGL: 16942 case MPI2_IOCSTATUS_INTERNAL_ERROR: 16943 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 16944 default: 16945 return (EIO); 16946 } 16947 } 16948 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16949 *status = LE_32(rep.SlotStatus); 16950 } 16951 16952 return (0); 16953 } 16954 16955 int 16956 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 16957 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 16958 uint32_t alloc_size, ddi_dma_cookie_t *cookiep) 16959 { 16960 ddi_dma_cookie_t new_cookie; 16961 size_t alloc_len; 16962 uint_t ncookie; 16963 16964 if (cookiep == NULL) 16965 cookiep = &new_cookie; 16966 16967 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP, 16968 NULL, dma_hdp) != DDI_SUCCESS) { 16969 return (FALSE); 16970 } 16971 16972 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr, 16973 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len, 16974 acc_hdp) != DDI_SUCCESS) { 16975 ddi_dma_free_handle(dma_hdp); 16976 *dma_hdp = NULL; 16977 return (FALSE); 16978 } 16979 16980 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len, 16981 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL, 16982 cookiep, &ncookie) != DDI_DMA_MAPPED) { 16983 (void) ddi_dma_mem_free(acc_hdp); 16984 ddi_dma_free_handle(dma_hdp); 16985 *dma_hdp = NULL; 16986 return (FALSE); 16987 } 16988 16989 return (TRUE); 16990 } 16991 16992 void 16993 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp) 16994 { 16995 if (*dma_hdp == NULL) 16996 return; 16997 16998 (void) ddi_dma_unbind_handle(*dma_hdp); 16999 (void) ddi_dma_mem_free(acc_hdp); 17000 ddi_dma_free_handle(dma_hdp); 17001 *dma_hdp = NULL; 17002 } 17003 17004 /* 17005 * DDI UFM Callbacks 17006 */ 17007 static int 17008 mptsas_ufm_fill_image(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, 17009 ddi_ufm_image_t *img) 17010 { 17011 if (imgno != 0) 17012 return (EINVAL); 17013 17014 ddi_ufm_image_set_desc(img, "IOC Firmware"); 17015 ddi_ufm_image_set_nslots(img, 1); 17016 17017 return (0); 17018 } 17019 17020 static int 17021 mptsas_ufm_fill_slot(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, 17022 uint_t slotno, ddi_ufm_slot_t *slot) 17023 { 17024 mptsas_t *mpt = (mptsas_t *)arg; 17025 char *buf; 17026 17027 if (imgno != 0 || slotno != 0 || 17028 ddi_prop_lookup_string(DDI_DEV_T_ANY, mpt->m_dip, 17029 DDI_PROP_DONTPASS, "firmware-version", &buf) != DDI_PROP_SUCCESS) 17030 return (EINVAL); 17031 17032 ddi_ufm_slot_set_attrs(slot, DDI_UFM_ATTR_ACTIVE); 17033 ddi_ufm_slot_set_version(slot, buf); 17034 17035 ddi_prop_free(buf); 17036 17037 return (0); 17038 } 17039 17040 static int 17041 mptsas_ufm_getcaps(ddi_ufm_handle_t *ufmh, void *arg, ddi_ufm_cap_t *caps) 17042 { 17043 *caps = DDI_UFM_CAP_REPORT; 17044 17045 return (0); 17046 } 17047