xref: /illumos-gate/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c (revision 15c07adc1c7b828006b5e3c4d528b92229d6bd23) 
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24  * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
25  * Copyright (c) 2018, Joyent, Inc.
26  * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved.
27  * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
28  */
29 
30 /*
31  * Copyright (c) 2000 to 2010, LSI Corporation.
32  * All rights reserved.
33  *
34  * Redistribution and use in source and binary forms of all code within
35  * this file that is exclusively owned by LSI, with or without
36  * modification, is permitted provided that, in addition to the CDDL 1.0
37  * License requirements, the following conditions are met:
38  *
39  *    Neither the name of the author nor the names of its contributors may be
40  *    used to endorse or promote products derived from this software without
41  *    specific prior written permission.
42  *
43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
46  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
47  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
48  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
49  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
50  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
51  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
52  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54  * DAMAGE.
55  */
56 
57 /*
58  * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface.
59  *
60  */
61 
62 #if defined(lint) || defined(DEBUG)
63 #define	MPTSAS_DEBUG
64 #endif
65 
66 /*
67  * standard header files.
68  */
69 #include <sys/note.h>
70 #include <sys/scsi/scsi.h>
71 #include <sys/pci.h>
72 #include <sys/file.h>
73 #include <sys/policy.h>
74 #include <sys/model.h>
75 #include <sys/sysevent.h>
76 #include <sys/sysevent/eventdefs.h>
77 #include <sys/sysevent/dr.h>
78 #include <sys/sata/sata_defs.h>
79 #include <sys/sata/sata_hba.h>
80 #include <sys/scsi/generic/sas.h>
81 #include <sys/scsi/impl/scsi_sas.h>
82 
83 #pragma pack(1)
84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
92 #pragma pack()
93 
94 /*
95  * private header files.
96  *
97  */
98 #include <sys/scsi/impl/scsi_reset_notify.h>
99 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
100 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
101 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
102 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
103 #include <sys/raidioctl.h>
104 
105 #include <sys/fs/dv_node.h>	/* devfs_clean */
106 
107 /*
108  * FMA header files
109  */
110 #include <sys/ddifm.h>
111 #include <sys/fm/protocol.h>
112 #include <sys/fm/util.h>
113 #include <sys/fm/io/ddi.h>
114 
115 /*
116  * autoconfiguration data and routines.
117  */
118 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
119 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
120 static int mptsas_power(dev_info_t *dip, int component, int level);
121 
122 /*
123  * cb_ops function
124  */
125 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
126 	cred_t *credp, int *rval);
127 #ifdef __sparc
128 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
129 #else  /* __sparc */
130 static int mptsas_quiesce(dev_info_t *devi);
131 #endif	/* __sparc */
132 
133 /*
134  * Resource initilaization for hardware
135  */
136 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
137 static void mptsas_disable_bus_master(mptsas_t *mpt);
138 static void mptsas_hba_fini(mptsas_t *mpt);
139 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
140 static int mptsas_hba_setup(mptsas_t *mpt);
141 static void mptsas_hba_teardown(mptsas_t *mpt);
142 static int mptsas_config_space_init(mptsas_t *mpt);
143 static void mptsas_config_space_fini(mptsas_t *mpt);
144 static void mptsas_iport_register(mptsas_t *mpt);
145 static int mptsas_smp_setup(mptsas_t *mpt);
146 static void mptsas_smp_teardown(mptsas_t *mpt);
147 static int mptsas_enc_setup(mptsas_t *mpt);
148 static void mptsas_enc_teardown(mptsas_t *mpt);
149 static int mptsas_cache_create(mptsas_t *mpt);
150 static void mptsas_cache_destroy(mptsas_t *mpt);
151 static int mptsas_alloc_request_frames(mptsas_t *mpt);
152 static int mptsas_alloc_sense_bufs(mptsas_t *mpt);
153 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
154 static int mptsas_alloc_free_queue(mptsas_t *mpt);
155 static int mptsas_alloc_post_queue(mptsas_t *mpt);
156 static void mptsas_alloc_reply_args(mptsas_t *mpt);
157 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
158 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
159 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
160 static void mptsas_update_hashtab(mptsas_t *mpt);
161 
162 /*
163  * SCSA function prototypes
164  */
165 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
166 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
167 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
168 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
169 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
170     int tgtonly);
171 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
172 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
173     struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
174 	int tgtlen, int flags, int (*callback)(), caddr_t arg);
175 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
176 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
177     struct scsi_pkt *pkt);
178 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
179     scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
180 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
181     scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
182 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
183     void (*callback)(caddr_t), caddr_t arg);
184 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
185 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
186 static int mptsas_scsi_quiesce(dev_info_t *dip);
187 static int mptsas_scsi_unquiesce(dev_info_t *dip);
188 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
189     ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
190 
191 /*
192  * SMP functions
193  */
194 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
195 
196 /*
197  * internal function prototypes.
198  */
199 static void mptsas_list_add(mptsas_t *mpt);
200 static void mptsas_list_del(mptsas_t *mpt);
201 
202 static int mptsas_quiesce_bus(mptsas_t *mpt);
203 static int mptsas_unquiesce_bus(mptsas_t *mpt);
204 
205 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
206 static void mptsas_free_handshake_msg(mptsas_t *mpt);
207 
208 static void mptsas_ncmds_checkdrain(void *arg);
209 
210 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
211 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
212 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
213 static void mptsas_accept_tx_waitq(mptsas_t *mpt);
214 
215 static int mptsas_do_detach(dev_info_t *dev);
216 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
217 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
218     struct scsi_pkt *pkt);
219 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
220 
221 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
222 static void mptsas_handle_event(void *args);
223 static int mptsas_handle_event_sync(void *args);
224 static void mptsas_handle_dr(void *args);
225 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
226     dev_info_t *pdip);
227 
228 static void mptsas_restart_cmd(void *);
229 
230 static void mptsas_flush_hba(mptsas_t *mpt);
231 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
232 	uint8_t tasktype);
233 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
234     uchar_t reason, uint_t stat);
235 
236 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
237 static void mptsas_process_intr(mptsas_t *mpt,
238     pMpi2ReplyDescriptorsUnion_t reply_desc_union);
239 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
240     pMpi2ReplyDescriptorsUnion_t reply_desc);
241 static void mptsas_handle_address_reply(mptsas_t *mpt,
242     pMpi2ReplyDescriptorsUnion_t reply_desc);
243 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
244 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
245     uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
246 
247 static void mptsas_watch(void *arg);
248 static void mptsas_watchsubr(mptsas_t *mpt);
249 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt);
250 
251 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
252 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
253     uint8_t *data, uint32_t request_size, uint32_t reply_size,
254     uint32_t data_size, uint32_t direction, uint8_t *dataout,
255     uint32_t dataout_size, short timeout, int mode);
256 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
257 
258 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
259     uint32_t unique_id);
260 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
261 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
262     mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
263 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
264     mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
265     uint32_t diag_type);
266 static int mptsas_diag_register(mptsas_t *mpt,
267     mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
268 static int mptsas_diag_unregister(mptsas_t *mpt,
269     mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
270 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
271     uint32_t *return_code);
272 static int mptsas_diag_read_buffer(mptsas_t *mpt,
273     mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
274     uint32_t *return_code, int ioctl_mode);
275 static int mptsas_diag_release(mptsas_t *mpt,
276     mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
277 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
278     uint8_t *diag_action, uint32_t length, uint32_t *return_code,
279     int ioctl_mode);
280 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
281     int mode);
282 
283 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
284     int cmdlen, int tgtlen, int statuslen, int kf);
285 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
286 
287 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
288 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
289 
290 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
291     int kmflags);
292 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
293 
294 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
295     mptsas_cmd_t *cmd);
296 static void mptsas_check_task_mgt(mptsas_t *mpt,
297     pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
298 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
299     mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
300     int *resid);
301 
302 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
303 static void mptsas_free_active_slots(mptsas_t *mpt);
304 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
305 
306 static void mptsas_restart_hba(mptsas_t *mpt);
307 static void mptsas_restart_waitq(mptsas_t *mpt);
308 
309 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
310 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
311 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
312 
313 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
314 static void mptsas_doneq_empty(mptsas_t *mpt);
315 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
316 
317 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
318 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
319 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
320 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
321 
322 
323 static void mptsas_start_watch_reset_delay();
324 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
325 static void mptsas_watch_reset_delay(void *arg);
326 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
327 
328 /*
329  * helper functions
330  */
331 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
332 
333 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
334 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
335 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
336     int lun);
337 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
338     int lun);
339 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
340 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
341 
342 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
343     int *lun);
344 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
345 
346 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt,
347     mptsas_phymask_t phymask, uint8_t phy);
348 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt,
349     mptsas_phymask_t phymask, uint64_t wwid);
350 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt,
351     mptsas_phymask_t phymask, uint64_t wwid);
352 
353 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
354     uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
355 
356 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
357     uint16_t *handle, mptsas_target_t **pptgt);
358 static void mptsas_update_phymask(mptsas_t *mpt);
359 
360 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep,
361     uint16_t idx);
362 static int mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx,
363     uint32_t *status, uint8_t cmd);
364 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
365     mptsas_phymask_t *phymask);
366 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
367     mptsas_phymask_t phymask);
368 
369 
370 /*
371  * Enumeration / DR functions
372  */
373 static void mptsas_config_all(dev_info_t *pdip);
374 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
375     dev_info_t **lundip);
376 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
377     dev_info_t **lundip);
378 
379 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
380 static int mptsas_offline_target(dev_info_t *pdip, char *name);
381 
382 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
383     dev_info_t **dip);
384 
385 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
386 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
387     dev_info_t **dip, mptsas_target_t *ptgt);
388 
389 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
390     dev_info_t **dip, mptsas_target_t *ptgt, int lun);
391 
392 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
393     char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
394 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
395     char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
396     int lun);
397 
398 static void mptsas_offline_missed_luns(dev_info_t *pdip,
399     uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
400 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
401     mdi_pathinfo_t *rpip, uint_t flags);
402 
403 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
404     dev_info_t **smp_dip);
405 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
406     uint_t flags);
407 
408 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
409     int mode, int *rval);
410 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
411     int mode, int *rval);
412 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
413     int mode, int *rval);
414 static void mptsas_record_event(void *args);
415 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
416     int mode);
417 
418 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t,
419     uint32_t, mptsas_phymask_t, uint8_t);
420 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *);
421 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
422     dev_info_t **smp_dip);
423 
424 /*
425  * Power management functions
426  */
427 static int mptsas_get_pci_cap(mptsas_t *mpt);
428 static int mptsas_init_pm(mptsas_t *mpt);
429 
430 /*
431  * MPT MSI tunable:
432  *
433  * By default MSI is enabled on all supported platforms.
434  */
435 boolean_t mptsas_enable_msi = B_TRUE;
436 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
437 
438 /*
439  * Global switch for use of MPI2.5 FAST PATH.
440  * We don't really know what FAST PATH actually does, so if it is suspected
441  * to cause problems it can be turned off by setting this variable to B_FALSE.
442  */
443 boolean_t mptsas_use_fastpath = B_TRUE;
444 
445 static int mptsas_register_intrs(mptsas_t *);
446 static void mptsas_unregister_intrs(mptsas_t *);
447 static int mptsas_add_intrs(mptsas_t *, int);
448 static void mptsas_rem_intrs(mptsas_t *);
449 
450 /*
451  * FMA Prototypes
452  */
453 static void mptsas_fm_init(mptsas_t *mpt);
454 static void mptsas_fm_fini(mptsas_t *mpt);
455 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
456 
457 extern pri_t minclsyspri, maxclsyspri;
458 
459 /*
460  * This device is created by the SCSI pseudo nexus driver (SCSI vHCI).  It is
461  * under this device that the paths to a physical device are created when
462  * MPxIO is used.
463  */
464 extern dev_info_t	*scsi_vhci_dip;
465 
466 /*
467  * Tunable timeout value for Inquiry VPD page 0x83
468  * By default the value is 30 seconds.
469  */
470 int mptsas_inq83_retry_timeout = 30;
471 
472 /*
473  * This is used to allocate memory for message frame storage, not for
474  * data I/O DMA. All message frames must be stored in the first 4G of
475  * physical memory.
476  */
477 ddi_dma_attr_t mptsas_dma_attrs = {
478 	DMA_ATTR_V0,	/* attribute layout version		*/
479 	0x0ull,		/* address low - should be 0 (longlong)	*/
480 	0xffffffffull,	/* address high - 32-bit max range	*/
481 	0x00ffffffull,	/* count max - max DMA object size	*/
482 	4,		/* allocation alignment requirements	*/
483 	0x78,		/* burstsizes - binary encoded values	*/
484 	1,		/* minxfer - gran. of DMA engine	*/
485 	0x00ffffffull,	/* maxxfer - gran. of DMA engine	*/
486 	0xffffffffull,	/* max segment size (DMA boundary)	*/
487 	MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length	*/
488 	512,		/* granularity - device transfer size	*/
489 	0		/* flags, set to 0			*/
490 };
491 
492 /*
493  * This is used for data I/O DMA memory allocation. (full 64-bit DMA
494  * physical addresses are supported.)
495  */
496 ddi_dma_attr_t mptsas_dma_attrs64 = {
497 	DMA_ATTR_V0,	/* attribute layout version		*/
498 	0x0ull,		/* address low - should be 0 (longlong)	*/
499 	0xffffffffffffffffull,	/* address high - 64-bit max	*/
500 	0x00ffffffull,	/* count max - max DMA object size	*/
501 	4,		/* allocation alignment requirements	*/
502 	0x78,		/* burstsizes - binary encoded values	*/
503 	1,		/* minxfer - gran. of DMA engine	*/
504 	0x00ffffffull,	/* maxxfer - gran. of DMA engine	*/
505 	0xffffffffull,	/* max segment size (DMA boundary)	*/
506 	MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length	*/
507 	512,		/* granularity - device transfer size	*/
508 	0		/* flags, set to 0 */
509 };
510 
511 ddi_device_acc_attr_t mptsas_dev_attr = {
512 	DDI_DEVICE_ATTR_V1,
513 	DDI_STRUCTURE_LE_ACC,
514 	DDI_STRICTORDER_ACC,
515 	DDI_DEFAULT_ACC
516 };
517 
518 static struct cb_ops mptsas_cb_ops = {
519 	scsi_hba_open,		/* open */
520 	scsi_hba_close,		/* close */
521 	nodev,			/* strategy */
522 	nodev,			/* print */
523 	nodev,			/* dump */
524 	nodev,			/* read */
525 	nodev,			/* write */
526 	mptsas_ioctl,		/* ioctl */
527 	nodev,			/* devmap */
528 	nodev,			/* mmap */
529 	nodev,			/* segmap */
530 	nochpoll,		/* chpoll */
531 	ddi_prop_op,		/* cb_prop_op */
532 	NULL,			/* streamtab */
533 	D_MP,			/* cb_flag */
534 	CB_REV,			/* rev */
535 	nodev,			/* aread */
536 	nodev			/* awrite */
537 };
538 
539 static struct dev_ops mptsas_ops = {
540 	DEVO_REV,		/* devo_rev, */
541 	0,			/* refcnt  */
542 	ddi_no_info,		/* info */
543 	nulldev,		/* identify */
544 	nulldev,		/* probe */
545 	mptsas_attach,		/* attach */
546 	mptsas_detach,		/* detach */
547 #ifdef  __sparc
548 	mptsas_reset,
549 #else
550 	nodev,			/* reset */
551 #endif  /* __sparc */
552 	&mptsas_cb_ops,		/* driver operations */
553 	NULL,			/* bus operations */
554 	mptsas_power,		/* power management */
555 #ifdef	__sparc
556 	ddi_quiesce_not_needed
557 #else
558 	mptsas_quiesce		/* quiesce */
559 #endif	/* __sparc */
560 };
561 
562 
563 #define	MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
564 
565 static struct modldrv modldrv = {
566 	&mod_driverops,	/* Type of module. This one is a driver */
567 	MPTSAS_MOD_STRING, /* Name of the module. */
568 	&mptsas_ops,	/* driver ops */
569 };
570 
571 static struct modlinkage modlinkage = {
572 	MODREV_1, &modldrv, NULL
573 };
574 #define	TARGET_PROP	"target"
575 #define	LUN_PROP	"lun"
576 #define	LUN64_PROP	"lun64"
577 #define	SAS_PROP	"sas-mpt"
578 #define	MDI_GUID	"wwn"
579 #define	NDI_GUID	"guid"
580 #define	MPTSAS_DEV_GONE	"mptsas_dev_gone"
581 
582 /*
583  * Local static data
584  */
585 #if defined(MPTSAS_DEBUG)
586 /*
587  * Flags to indicate which debug messages are to be printed and which go to the
588  * debug log ring buffer. Default is to not print anything, and to log
589  * everything except the watchsubr() output which normally happens every second.
590  */
591 uint32_t mptsas_debugprt_flags = 0x0;
592 uint32_t mptsas_debuglog_flags = ~(1U << 30);
593 #endif	/* defined(MPTSAS_DEBUG) */
594 uint32_t mptsas_debug_resets = 0;
595 
596 static kmutex_t		mptsas_global_mutex;
597 static void		*mptsas_state;		/* soft	state ptr */
598 static krwlock_t	mptsas_global_rwlock;
599 
600 static kmutex_t		mptsas_log_mutex;
601 static char		mptsas_log_buf[256];
602 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
603 
604 static mptsas_t *mptsas_head, *mptsas_tail;
605 static clock_t mptsas_scsi_watchdog_tick;
606 static clock_t mptsas_tick;
607 static timeout_id_t mptsas_reset_watch;
608 static timeout_id_t mptsas_timeout_id;
609 static int mptsas_timeouts_enabled = 0;
610 
611 /*
612  * Default length for extended auto request sense buffers.
613  * All sense buffers need to be under the same alloc because there
614  * is only one common top 32bits (of 64bits) address register.
615  * Most requests only require 32 bytes, but some request >256.
616  * We use rmalloc()/rmfree() on this additional memory to manage the
617  * "extended" requests.
618  */
619 int mptsas_extreq_sense_bufsize = 256*64;
620 
621 /*
622  * We believe that all software resrictions of having to run with DMA
623  * attributes to limit allocation to the first 4G are removed.
624  * However, this flag remains to enable quick switchback should suspicious
625  * problems emerge.
626  * Note that scsi_alloc_consistent_buf() does still adhere to allocating
627  * 32 bit addressable memory, but we can cope if that is changed now.
628  */
629 int mptsas_use_64bit_msgaddr = 1;
630 
631 /*
632  * warlock directives
633  */
634 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
635 	mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
636 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
637 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
638 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
639 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
640 
641 /*
642  * SM - HBA statics
643  */
644 char	*mptsas_driver_rev = MPTSAS_MOD_STRING;
645 
646 #ifdef MPTSAS_DEBUG
647 void debug_enter(char *);
648 #endif
649 
650 /*
651  * Notes:
652  *	- scsi_hba_init(9F) initializes SCSI HBA modules
653  *	- must call scsi_hba_fini(9F) if modload() fails
654  */
655 int
656 _init(void)
657 {
658 	int status;
659 	/* CONSTCOND */
660 	ASSERT(NO_COMPETING_THREADS);
661 
662 	NDBG0(("_init"));
663 
664 	status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
665 	    MPTSAS_INITIAL_SOFT_SPACE);
666 	if (status != 0) {
667 		return (status);
668 	}
669 
670 	if ((status = scsi_hba_init(&modlinkage)) != 0) {
671 		ddi_soft_state_fini(&mptsas_state);
672 		return (status);
673 	}
674 
675 	mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
676 	rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
677 	mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
678 
679 	if ((status = mod_install(&modlinkage)) != 0) {
680 		mutex_destroy(&mptsas_log_mutex);
681 		rw_destroy(&mptsas_global_rwlock);
682 		mutex_destroy(&mptsas_global_mutex);
683 		ddi_soft_state_fini(&mptsas_state);
684 		scsi_hba_fini(&modlinkage);
685 	}
686 
687 	return (status);
688 }
689 
690 /*
691  * Notes:
692  *	- scsi_hba_fini(9F) uninitializes SCSI HBA modules
693  */
694 int
695 _fini(void)
696 {
697 	int	status;
698 	/* CONSTCOND */
699 	ASSERT(NO_COMPETING_THREADS);
700 
701 	NDBG0(("_fini"));
702 
703 	if ((status = mod_remove(&modlinkage)) == 0) {
704 		ddi_soft_state_fini(&mptsas_state);
705 		scsi_hba_fini(&modlinkage);
706 		mutex_destroy(&mptsas_global_mutex);
707 		rw_destroy(&mptsas_global_rwlock);
708 		mutex_destroy(&mptsas_log_mutex);
709 	}
710 	return (status);
711 }
712 
713 /*
714  * The loadable-module _info(9E) entry point
715  */
716 int
717 _info(struct modinfo *modinfop)
718 {
719 	/* CONSTCOND */
720 	ASSERT(NO_COMPETING_THREADS);
721 	NDBG0(("mptsas _info"));
722 
723 	return (mod_info(&modlinkage, modinfop));
724 }
725 
726 static int
727 mptsas_target_eval_devhdl(const void *op, void *arg)
728 {
729 	uint16_t dh = *(uint16_t *)arg;
730 	const mptsas_target_t *tp = op;
731 
732 	return ((int)tp->m_devhdl - (int)dh);
733 }
734 
735 static int
736 mptsas_target_eval_nowwn(const void *op, void *arg)
737 {
738 	uint8_t phy = *(uint8_t *)arg;
739 	const mptsas_target_t *tp = op;
740 
741 	if (tp->m_addr.mta_wwn != 0)
742 		return (-1);
743 
744 	return ((int)tp->m_phynum - (int)phy);
745 }
746 
747 static int
748 mptsas_smp_eval_devhdl(const void *op, void *arg)
749 {
750 	uint16_t dh = *(uint16_t *)arg;
751 	const mptsas_smp_t *sp = op;
752 
753 	return ((int)sp->m_devhdl - (int)dh);
754 }
755 
756 static uint64_t
757 mptsas_target_addr_hash(const void *tp)
758 {
759 	const mptsas_target_addr_t *tap = tp;
760 
761 	return ((tap->mta_wwn & 0xffffffffffffULL) |
762 	    ((uint64_t)tap->mta_phymask << 48));
763 }
764 
765 static int
766 mptsas_target_addr_cmp(const void *a, const void *b)
767 {
768 	const mptsas_target_addr_t *aap = a;
769 	const mptsas_target_addr_t *bap = b;
770 
771 	if (aap->mta_wwn < bap->mta_wwn)
772 		return (-1);
773 	if (aap->mta_wwn > bap->mta_wwn)
774 		return (1);
775 	return ((int)bap->mta_phymask - (int)aap->mta_phymask);
776 }
777 
778 static uint64_t
779 mptsas_tmp_target_hash(const void *tp)
780 {
781 	return ((uint64_t)(uintptr_t)tp);
782 }
783 
784 static int
785 mptsas_tmp_target_cmp(const void *a, const void *b)
786 {
787 	if (a > b)
788 		return (1);
789 	if (b < a)
790 		return (-1);
791 
792 	return (0);
793 }
794 
795 static void
796 mptsas_target_free(void *op)
797 {
798 	kmem_free(op, sizeof (mptsas_target_t));
799 }
800 
801 static void
802 mptsas_smp_free(void *op)
803 {
804 	kmem_free(op, sizeof (mptsas_smp_t));
805 }
806 
807 static void
808 mptsas_destroy_hashes(mptsas_t *mpt)
809 {
810 	mptsas_target_t *tp;
811 	mptsas_smp_t *sp;
812 
813 	for (tp = refhash_first(mpt->m_targets); tp != NULL;
814 	    tp = refhash_next(mpt->m_targets, tp)) {
815 		refhash_remove(mpt->m_targets, tp);
816 	}
817 	for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
818 	    sp = refhash_next(mpt->m_smp_targets, sp)) {
819 		refhash_remove(mpt->m_smp_targets, sp);
820 	}
821 	refhash_destroy(mpt->m_tmp_targets);
822 	refhash_destroy(mpt->m_targets);
823 	refhash_destroy(mpt->m_smp_targets);
824 	mpt->m_targets = NULL;
825 	mpt->m_smp_targets = NULL;
826 }
827 
828 static int
829 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
830 {
831 	dev_info_t		*pdip;
832 	mptsas_t		*mpt;
833 	scsi_hba_tran_t		*hba_tran;
834 	char			*iport = NULL;
835 	char			phymask[MPTSAS_MAX_PHYS];
836 	mptsas_phymask_t	phy_mask = 0;
837 	int			dynamic_port = 0;
838 	uint32_t		page_address;
839 	char			initiator_wwnstr[MPTSAS_WWN_STRLEN];
840 	int			rval = DDI_FAILURE;
841 	int			i = 0;
842 	uint8_t			numphys = 0;
843 	uint8_t			phy_id;
844 	uint8_t			phy_port = 0;
845 	uint16_t		attached_devhdl = 0;
846 	uint32_t		dev_info;
847 	uint64_t		attached_sas_wwn;
848 	uint16_t		dev_hdl;
849 	uint16_t		pdev_hdl;
850 	uint16_t		bay_num, enclosure, io_flags;
851 	char			attached_wwnstr[MPTSAS_WWN_STRLEN];
852 
853 	/* CONSTCOND */
854 	ASSERT(NO_COMPETING_THREADS);
855 
856 	switch (cmd) {
857 	case DDI_ATTACH:
858 		break;
859 
860 	case DDI_RESUME:
861 		/*
862 		 * If this a scsi-iport node, nothing to do here.
863 		 */
864 		return (DDI_SUCCESS);
865 
866 	default:
867 		return (DDI_FAILURE);
868 	}
869 
870 	pdip = ddi_get_parent(dip);
871 
872 	if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
873 	    NULL) {
874 		cmn_err(CE_WARN, "Failed attach iport because fail to "
875 		    "get tran vector for the HBA node");
876 		return (DDI_FAILURE);
877 	}
878 
879 	mpt = TRAN2MPT(hba_tran);
880 	ASSERT(mpt != NULL);
881 	if (mpt == NULL)
882 		return (DDI_FAILURE);
883 
884 	if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
885 	    NULL) {
886 		mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
887 		    "get tran vector for the iport node");
888 		return (DDI_FAILURE);
889 	}
890 
891 	/*
892 	 * Overwrite parent's tran_hba_private to iport's tran vector
893 	 */
894 	hba_tran->tran_hba_private = mpt;
895 
896 	ddi_report_dev(dip);
897 
898 	/*
899 	 * Get SAS address for initiator port according dev_handle
900 	 */
901 	iport = ddi_get_name_addr(dip);
902 	if (iport && strncmp(iport, "v0", 2) == 0) {
903 		if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
904 		    MPTSAS_VIRTUAL_PORT, 1) !=
905 		    DDI_PROP_SUCCESS) {
906 			(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
907 			    MPTSAS_VIRTUAL_PORT);
908 			mptsas_log(mpt, CE_WARN, "mptsas virtual port "
909 			    "prop update failed");
910 			return (DDI_FAILURE);
911 		}
912 		return (DDI_SUCCESS);
913 	}
914 
915 	mutex_enter(&mpt->m_mutex);
916 	for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
917 		bzero(phymask, sizeof (phymask));
918 		(void) sprintf(phymask,
919 		    "%x", mpt->m_phy_info[i].phy_mask);
920 		if (strcmp(phymask, iport) == 0) {
921 			break;
922 		}
923 	}
924 
925 	if (i == MPTSAS_MAX_PHYS) {
926 		mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
927 		    "seems not exist", iport);
928 		mutex_exit(&mpt->m_mutex);
929 		return (DDI_FAILURE);
930 	}
931 
932 	phy_mask = mpt->m_phy_info[i].phy_mask;
933 
934 	if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
935 		dynamic_port = 1;
936 	else
937 		dynamic_port = 0;
938 
939 	/*
940 	 * Update PHY info for smhba
941 	 */
942 	if (mptsas_smhba_phy_init(mpt)) {
943 		mutex_exit(&mpt->m_mutex);
944 		mptsas_log(mpt, CE_WARN, "mptsas phy update "
945 		    "failed");
946 		return (DDI_FAILURE);
947 	}
948 
949 	mutex_exit(&mpt->m_mutex);
950 
951 	numphys = 0;
952 	for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
953 		if ((phy_mask >> i) & 0x01) {
954 			numphys++;
955 		}
956 	}
957 
958 	bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
959 	(void) sprintf(initiator_wwnstr, "w%016"PRIx64,
960 	    mpt->un.m_base_wwid);
961 
962 	if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
963 	    SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
964 	    DDI_PROP_SUCCESS) {
965 		(void) ddi_prop_remove(DDI_DEV_T_NONE,
966 		    dip, SCSI_ADDR_PROP_INITIATOR_PORT);
967 		mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
968 		    "prop update failed");
969 		return (DDI_FAILURE);
970 	}
971 	if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
972 	    MPTSAS_NUM_PHYS, numphys) !=
973 	    DDI_PROP_SUCCESS) {
974 		(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
975 		return (DDI_FAILURE);
976 	}
977 
978 	if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
979 	    "phymask", phy_mask) !=
980 	    DDI_PROP_SUCCESS) {
981 		(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
982 		mptsas_log(mpt, CE_WARN, "mptsas phy mask "
983 		    "prop update failed");
984 		return (DDI_FAILURE);
985 	}
986 
987 	if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
988 	    "dynamic-port", dynamic_port) !=
989 	    DDI_PROP_SUCCESS) {
990 		(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
991 		mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
992 		    "prop update failed");
993 		return (DDI_FAILURE);
994 	}
995 	if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
996 	    MPTSAS_VIRTUAL_PORT, 0) !=
997 	    DDI_PROP_SUCCESS) {
998 		(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
999 		    MPTSAS_VIRTUAL_PORT);
1000 		mptsas_log(mpt, CE_WARN, "mptsas virtual port "
1001 		    "prop update failed");
1002 		return (DDI_FAILURE);
1003 	}
1004 	mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
1005 	    &attached_devhdl);
1006 
1007 	mutex_enter(&mpt->m_mutex);
1008 	page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
1009 	    MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
1010 	rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
1011 	    &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
1012 	    &pdev_hdl, &bay_num, &enclosure, &io_flags);
1013 	if (rval != DDI_SUCCESS) {
1014 		mptsas_log(mpt, CE_WARN,
1015 		    "Failed to get device page0 for handle:%d",
1016 		    attached_devhdl);
1017 		mutex_exit(&mpt->m_mutex);
1018 		return (DDI_FAILURE);
1019 	}
1020 
1021 	for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1022 		bzero(phymask, sizeof (phymask));
1023 		(void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
1024 		if (strcmp(phymask, iport) == 0) {
1025 			(void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
1026 			    "%x",
1027 			    mpt->m_phy_info[i].phy_mask);
1028 		}
1029 	}
1030 	mutex_exit(&mpt->m_mutex);
1031 
1032 	bzero(attached_wwnstr, sizeof (attached_wwnstr));
1033 	(void) sprintf(attached_wwnstr, "w%016"PRIx64,
1034 	    attached_sas_wwn);
1035 	if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
1036 	    SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
1037 	    DDI_PROP_SUCCESS) {
1038 		(void) ddi_prop_remove(DDI_DEV_T_NONE,
1039 		    dip, SCSI_ADDR_PROP_ATTACHED_PORT);
1040 		return (DDI_FAILURE);
1041 	}
1042 
1043 	/* Create kstats for each phy on this iport */
1044 
1045 	mptsas_create_phy_stats(mpt, iport, dip);
1046 
1047 	/*
1048 	 * register sas hba iport with mdi (MPxIO/vhci)
1049 	 */
1050 	if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
1051 	    dip, 0) == MDI_SUCCESS) {
1052 		mpt->m_mpxio_enable = TRUE;
1053 	}
1054 	return (DDI_SUCCESS);
1055 }
1056 
1057 /*
1058  * Notes:
1059  *	Set up all device state and allocate data structures,
1060  *	mutexes, condition variables, etc. for device operation.
1061  *	Add interrupts needed.
1062  *	Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
1063  */
1064 static int
1065 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1066 {
1067 	mptsas_t		*mpt = NULL;
1068 	int			instance, i, j;
1069 	int			doneq_thread_num;
1070 	char			intr_added = 0;
1071 	char			map_setup = 0;
1072 	char			config_setup = 0;
1073 	char			hba_attach_setup = 0;
1074 	char			smp_attach_setup = 0;
1075 	char			enc_attach_setup = 0;
1076 	char			mutex_init_done = 0;
1077 	char			event_taskq_create = 0;
1078 	char			dr_taskq_create = 0;
1079 	char			doneq_thread_create = 0;
1080 	char			added_watchdog = 0;
1081 	scsi_hba_tran_t		*hba_tran;
1082 	uint_t			mem_bar = MEM_SPACE;
1083 	int			rval = DDI_FAILURE;
1084 
1085 	/* CONSTCOND */
1086 	ASSERT(NO_COMPETING_THREADS);
1087 
1088 	if (scsi_hba_iport_unit_address(dip)) {
1089 		return (mptsas_iport_attach(dip, cmd));
1090 	}
1091 
1092 	switch (cmd) {
1093 	case DDI_ATTACH:
1094 		break;
1095 
1096 	case DDI_RESUME:
1097 		if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
1098 			return (DDI_FAILURE);
1099 
1100 		mpt = TRAN2MPT(hba_tran);
1101 
1102 		if (!mpt) {
1103 			return (DDI_FAILURE);
1104 		}
1105 
1106 		/*
1107 		 * Reset hardware and softc to "no outstanding commands"
1108 		 * Note	that a check condition can result on first command
1109 		 * to a	target.
1110 		 */
1111 		mutex_enter(&mpt->m_mutex);
1112 
1113 		/*
1114 		 * raise power.
1115 		 */
1116 		if (mpt->m_options & MPTSAS_OPT_PM) {
1117 			mutex_exit(&mpt->m_mutex);
1118 			(void) pm_busy_component(dip, 0);
1119 			rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1120 			if (rval == DDI_SUCCESS) {
1121 				mutex_enter(&mpt->m_mutex);
1122 			} else {
1123 				/*
1124 				 * The pm_raise_power() call above failed,
1125 				 * and that can only occur if we were unable
1126 				 * to reset the hardware.  This is probably
1127 				 * due to unhealty hardware, and because
1128 				 * important filesystems(such as the root
1129 				 * filesystem) could be on the attached disks,
1130 				 * it would not be a good idea to continue,
1131 				 * as we won't be entirely certain we are
1132 				 * writing correct data.  So we panic() here
1133 				 * to not only prevent possible data corruption,
1134 				 * but to give developers or end users a hope
1135 				 * of identifying and correcting any problems.
1136 				 */
1137 				fm_panic("mptsas could not reset hardware "
1138 				    "during resume");
1139 			}
1140 		}
1141 
1142 		mpt->m_suspended = 0;
1143 
1144 		/*
1145 		 * Reinitialize ioc
1146 		 */
1147 		mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1148 		if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1149 			mutex_exit(&mpt->m_mutex);
1150 			if (mpt->m_options & MPTSAS_OPT_PM) {
1151 				(void) pm_idle_component(dip, 0);
1152 			}
1153 			fm_panic("mptsas init chip fail during resume");
1154 		}
1155 		/*
1156 		 * mptsas_update_driver_data needs interrupts so enable them
1157 		 * first.
1158 		 */
1159 		MPTSAS_ENABLE_INTR(mpt);
1160 		mptsas_update_driver_data(mpt);
1161 
1162 		/* start requests, if possible */
1163 		mptsas_restart_hba(mpt);
1164 
1165 		mutex_exit(&mpt->m_mutex);
1166 
1167 		/*
1168 		 * Restart watch thread
1169 		 */
1170 		mutex_enter(&mptsas_global_mutex);
1171 		if (mptsas_timeout_id == 0) {
1172 			mptsas_timeout_id = timeout(mptsas_watch, NULL,
1173 			    mptsas_tick);
1174 			mptsas_timeouts_enabled = 1;
1175 		}
1176 		mutex_exit(&mptsas_global_mutex);
1177 
1178 		/* report idle status to pm framework */
1179 		if (mpt->m_options & MPTSAS_OPT_PM) {
1180 			(void) pm_idle_component(dip, 0);
1181 		}
1182 
1183 		return (DDI_SUCCESS);
1184 
1185 	default:
1186 		return (DDI_FAILURE);
1187 
1188 	}
1189 
1190 	instance = ddi_get_instance(dip);
1191 
1192 	/*
1193 	 * Allocate softc information.
1194 	 */
1195 	if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1196 		mptsas_log(NULL, CE_WARN,
1197 		    "mptsas%d: cannot allocate soft state", instance);
1198 		goto fail;
1199 	}
1200 
1201 	mpt = ddi_get_soft_state(mptsas_state, instance);
1202 
1203 	if (mpt == NULL) {
1204 		mptsas_log(NULL, CE_WARN,
1205 		    "mptsas%d: cannot get soft state", instance);
1206 		goto fail;
1207 	}
1208 
1209 	/* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1210 	scsi_size_clean(dip);
1211 
1212 	mpt->m_dip = dip;
1213 	mpt->m_instance = instance;
1214 
1215 	/* Make a per-instance copy of the structures */
1216 	mpt->m_io_dma_attr = mptsas_dma_attrs64;
1217 	if (mptsas_use_64bit_msgaddr) {
1218 		mpt->m_msg_dma_attr = mptsas_dma_attrs64;
1219 	} else {
1220 		mpt->m_msg_dma_attr = mptsas_dma_attrs;
1221 	}
1222 	mpt->m_reg_acc_attr = mptsas_dev_attr;
1223 	mpt->m_dev_acc_attr = mptsas_dev_attr;
1224 
1225 	/*
1226 	 * Size of individual request sense buffer
1227 	 */
1228 	mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE;
1229 
1230 	/*
1231 	 * Initialize FMA
1232 	 */
1233 	mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1234 	    DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1235 	    DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1236 	    DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1237 
1238 	mptsas_fm_init(mpt);
1239 
1240 	if (mptsas_alloc_handshake_msg(mpt,
1241 	    sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1242 		mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1243 		goto fail;
1244 	}
1245 
1246 	/*
1247 	 * Setup configuration space
1248 	 */
1249 	if (mptsas_config_space_init(mpt) == FALSE) {
1250 		mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1251 		goto fail;
1252 	}
1253 	config_setup++;
1254 
1255 	if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1256 	    0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1257 		mptsas_log(mpt, CE_WARN, "map setup failed");
1258 		goto fail;
1259 	}
1260 	map_setup++;
1261 
1262 	/*
1263 	 * A taskq is created for dealing with the event handler
1264 	 */
1265 	if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1266 	    1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1267 		mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1268 		goto fail;
1269 	}
1270 	event_taskq_create++;
1271 
1272 	/*
1273 	 * A taskq is created for dealing with dr events
1274 	 */
1275 	if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1276 	    "mptsas_dr_taskq",
1277 	    1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1278 		mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1279 		    "failed");
1280 		goto fail;
1281 	}
1282 	dr_taskq_create++;
1283 
1284 	mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1285 	    0, "mptsas_doneq_thread_threshold_prop", 10);
1286 	mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1287 	    0, "mptsas_doneq_length_threshold_prop", 8);
1288 	mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1289 	    0, "mptsas_doneq_thread_n_prop", 8);
1290 
1291 	if (mpt->m_doneq_thread_n) {
1292 		cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1293 		mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1294 
1295 		mutex_enter(&mpt->m_doneq_mutex);
1296 		mpt->m_doneq_thread_id =
1297 		    kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1298 		    * mpt->m_doneq_thread_n, KM_SLEEP);
1299 
1300 		for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1301 			cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1302 			    CV_DRIVER, NULL);
1303 			mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1304 			    MUTEX_DRIVER, NULL);
1305 			mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1306 			mpt->m_doneq_thread_id[j].flag |=
1307 			    MPTSAS_DONEQ_THREAD_ACTIVE;
1308 			mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1309 			mpt->m_doneq_thread_id[j].arg.t = j;
1310 			mpt->m_doneq_thread_id[j].threadp =
1311 			    thread_create(NULL, 0, mptsas_doneq_thread,
1312 			    &mpt->m_doneq_thread_id[j].arg,
1313 			    0, &p0, TS_RUN, minclsyspri);
1314 			mpt->m_doneq_thread_id[j].donetail =
1315 			    &mpt->m_doneq_thread_id[j].doneq;
1316 			mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1317 		}
1318 		mutex_exit(&mpt->m_doneq_mutex);
1319 		doneq_thread_create++;
1320 	}
1321 
1322 	/*
1323 	 * Disable hardware interrupt since we're not ready to
1324 	 * handle it yet.
1325 	 */
1326 	MPTSAS_DISABLE_INTR(mpt);
1327 	if (mptsas_register_intrs(mpt) == FALSE)
1328 		goto fail;
1329 	intr_added++;
1330 
1331 	/* Initialize mutex used in interrupt handler */
1332 	mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1333 	    DDI_INTR_PRI(mpt->m_intr_pri));
1334 	mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1335 	mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1336 	    DDI_INTR_PRI(mpt->m_intr_pri));
1337 	for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1338 		mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1339 		    NULL, MUTEX_DRIVER,
1340 		    DDI_INTR_PRI(mpt->m_intr_pri));
1341 	}
1342 
1343 	cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1344 	cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1345 	cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1346 	cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1347 	cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1348 	cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL);
1349 	mutex_init_done++;
1350 
1351 	mutex_enter(&mpt->m_mutex);
1352 	/*
1353 	 * Initialize power management component
1354 	 */
1355 	if (mpt->m_options & MPTSAS_OPT_PM) {
1356 		if (mptsas_init_pm(mpt)) {
1357 			mutex_exit(&mpt->m_mutex);
1358 			mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1359 			    "failed");
1360 			goto fail;
1361 		}
1362 	}
1363 
1364 	/*
1365 	 * Initialize chip using Message Unit Reset, if allowed
1366 	 */
1367 	mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1368 	if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1369 		mutex_exit(&mpt->m_mutex);
1370 		mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1371 		goto fail;
1372 	}
1373 
1374 	mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT,
1375 	    mptsas_target_addr_hash, mptsas_target_addr_cmp,
1376 	    mptsas_target_free, sizeof (mptsas_target_t),
1377 	    offsetof(mptsas_target_t, m_link),
1378 	    offsetof(mptsas_target_t, m_addr), KM_SLEEP);
1379 
1380 	/*
1381 	 * The refhash for temporary targets uses the address of the target
1382 	 * struct itself as tag, so the tag offset is 0. See the implementation
1383 	 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp().
1384 	 */
1385 	mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT,
1386 	    mptsas_tmp_target_hash, mptsas_tmp_target_cmp,
1387 	    mptsas_target_free, sizeof (mptsas_target_t),
1388 	    offsetof(mptsas_target_t, m_link), 0, KM_SLEEP);
1389 
1390 	/*
1391 	 * Fill in the phy_info structure and get the base WWID
1392 	 */
1393 	if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1394 		mptsas_log(mpt, CE_WARN,
1395 		    "mptsas_get_manufacture_page5 failed!");
1396 		goto fail;
1397 	}
1398 
1399 	if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1400 		mptsas_log(mpt, CE_WARN,
1401 		    "mptsas_get_sas_io_unit_page_hndshk failed!");
1402 		goto fail;
1403 	}
1404 
1405 	if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1406 		mptsas_log(mpt, CE_WARN,
1407 		    "mptsas_get_manufacture_page0 failed!");
1408 		goto fail;
1409 	}
1410 
1411 	mutex_exit(&mpt->m_mutex);
1412 
1413 	/*
1414 	 * Register the iport for multiple port HBA
1415 	 */
1416 	mptsas_iport_register(mpt);
1417 
1418 	/*
1419 	 * initialize SCSI HBA transport structure
1420 	 */
1421 	if (mptsas_hba_setup(mpt) == FALSE)
1422 		goto fail;
1423 	hba_attach_setup++;
1424 
1425 	if (mptsas_smp_setup(mpt) == FALSE)
1426 		goto fail;
1427 	smp_attach_setup++;
1428 
1429 	if (mptsas_enc_setup(mpt) == FALSE)
1430 		goto fail;
1431 	enc_attach_setup++;
1432 
1433 	if (mptsas_cache_create(mpt) == FALSE)
1434 		goto fail;
1435 
1436 	mpt->m_scsi_reset_delay	= ddi_prop_get_int(DDI_DEV_T_ANY,
1437 	    dip, 0, "scsi-reset-delay",	SCSI_DEFAULT_RESET_DELAY);
1438 	if (mpt->m_scsi_reset_delay == 0) {
1439 		mptsas_log(mpt, CE_NOTE,
1440 		    "scsi_reset_delay of 0 is not recommended,"
1441 		    " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1442 		mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1443 	}
1444 
1445 	/*
1446 	 * Initialize the wait and done FIFO queue
1447 	 */
1448 	mpt->m_donetail = &mpt->m_doneq;
1449 	mpt->m_waitqtail = &mpt->m_waitq;
1450 	mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1451 	mpt->m_tx_draining = 0;
1452 
1453 	/*
1454 	 * ioc cmd queue initialize
1455 	 */
1456 	mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1457 	mpt->m_dev_handle = 0xFFFF;
1458 
1459 	MPTSAS_ENABLE_INTR(mpt);
1460 
1461 	/*
1462 	 * enable event notification
1463 	 */
1464 	mutex_enter(&mpt->m_mutex);
1465 	if (mptsas_ioc_enable_event_notification(mpt)) {
1466 		mutex_exit(&mpt->m_mutex);
1467 		goto fail;
1468 	}
1469 	mutex_exit(&mpt->m_mutex);
1470 
1471 	/*
1472 	 * used for mptsas_watch
1473 	 */
1474 	mptsas_list_add(mpt);
1475 
1476 	mutex_enter(&mptsas_global_mutex);
1477 	if (mptsas_timeouts_enabled == 0) {
1478 		mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1479 		    dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1480 
1481 		mptsas_tick = mptsas_scsi_watchdog_tick *
1482 		    drv_usectohz((clock_t)1000000);
1483 
1484 		mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1485 		mptsas_timeouts_enabled = 1;
1486 	}
1487 	mutex_exit(&mptsas_global_mutex);
1488 	added_watchdog++;
1489 
1490 	/*
1491 	 * Initialize PHY info for smhba.
1492 	 * This requires watchdog to be enabled otherwise if interrupts
1493 	 * don't work the system will hang.
1494 	 */
1495 	if (mptsas_smhba_setup(mpt)) {
1496 		mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1497 		    "failed");
1498 		goto fail;
1499 	}
1500 
1501 	/* Check all dma handles allocated in attach */
1502 	if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1503 	    != DDI_SUCCESS) ||
1504 	    (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl)
1505 	    != DDI_SUCCESS) ||
1506 	    (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1507 	    != DDI_SUCCESS) ||
1508 	    (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1509 	    != DDI_SUCCESS) ||
1510 	    (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1511 	    != DDI_SUCCESS) ||
1512 	    (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1513 	    != DDI_SUCCESS)) {
1514 		goto fail;
1515 	}
1516 
1517 	/* Check all acc handles allocated in attach */
1518 	if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1519 	    (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1520 	    != DDI_SUCCESS) ||
1521 	    (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl)
1522 	    != DDI_SUCCESS) ||
1523 	    (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1524 	    != DDI_SUCCESS) ||
1525 	    (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1526 	    != DDI_SUCCESS) ||
1527 	    (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1528 	    != DDI_SUCCESS) ||
1529 	    (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1530 	    != DDI_SUCCESS) ||
1531 	    (mptsas_check_acc_handle(mpt->m_config_handle)
1532 	    != DDI_SUCCESS)) {
1533 		goto fail;
1534 	}
1535 
1536 	/*
1537 	 * After this point, we are not going to fail the attach.
1538 	 */
1539 
1540 	/* Print message of HBA present */
1541 	ddi_report_dev(dip);
1542 
1543 	/* report idle status to pm framework */
1544 	if (mpt->m_options & MPTSAS_OPT_PM) {
1545 		(void) pm_idle_component(dip, 0);
1546 	}
1547 
1548 	return (DDI_SUCCESS);
1549 
1550 fail:
1551 	mptsas_log(mpt, CE_WARN, "attach failed");
1552 	mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1553 	ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1554 	if (mpt) {
1555 		/* deallocate in reverse order */
1556 		if (added_watchdog) {
1557 			mptsas_list_del(mpt);
1558 			mutex_enter(&mptsas_global_mutex);
1559 
1560 			if (mptsas_timeout_id && (mptsas_head == NULL)) {
1561 				timeout_id_t tid = mptsas_timeout_id;
1562 				mptsas_timeouts_enabled = 0;
1563 				mptsas_timeout_id = 0;
1564 				mutex_exit(&mptsas_global_mutex);
1565 				(void) untimeout(tid);
1566 				mutex_enter(&mptsas_global_mutex);
1567 			}
1568 			mutex_exit(&mptsas_global_mutex);
1569 		}
1570 
1571 		mptsas_cache_destroy(mpt);
1572 
1573 		if (smp_attach_setup) {
1574 			mptsas_smp_teardown(mpt);
1575 		}
1576 		if (enc_attach_setup) {
1577 			mptsas_enc_teardown(mpt);
1578 		}
1579 		if (hba_attach_setup) {
1580 			mptsas_hba_teardown(mpt);
1581 		}
1582 
1583 		if (mpt->m_tmp_targets)
1584 			refhash_destroy(mpt->m_tmp_targets);
1585 		if (mpt->m_targets)
1586 			refhash_destroy(mpt->m_targets);
1587 		if (mpt->m_smp_targets)
1588 			refhash_destroy(mpt->m_smp_targets);
1589 
1590 		if (mpt->m_active) {
1591 			mptsas_free_active_slots(mpt);
1592 		}
1593 		if (intr_added) {
1594 			mptsas_unregister_intrs(mpt);
1595 		}
1596 
1597 		if (doneq_thread_create) {
1598 			mutex_enter(&mpt->m_doneq_mutex);
1599 			doneq_thread_num = mpt->m_doneq_thread_n;
1600 			for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1601 				mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1602 				mpt->m_doneq_thread_id[j].flag &=
1603 				    (~MPTSAS_DONEQ_THREAD_ACTIVE);
1604 				cv_signal(&mpt->m_doneq_thread_id[j].cv);
1605 				mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1606 			}
1607 			while (mpt->m_doneq_thread_n) {
1608 				cv_wait(&mpt->m_doneq_thread_cv,
1609 				    &mpt->m_doneq_mutex);
1610 			}
1611 			for (j = 0; j < doneq_thread_num; j++) {
1612 				cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1613 				mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1614 			}
1615 			kmem_free(mpt->m_doneq_thread_id,
1616 			    sizeof (mptsas_doneq_thread_list_t)
1617 			    * doneq_thread_num);
1618 			mutex_exit(&mpt->m_doneq_mutex);
1619 			cv_destroy(&mpt->m_doneq_thread_cv);
1620 			mutex_destroy(&mpt->m_doneq_mutex);
1621 		}
1622 		if (event_taskq_create) {
1623 			ddi_taskq_destroy(mpt->m_event_taskq);
1624 		}
1625 		if (dr_taskq_create) {
1626 			ddi_taskq_destroy(mpt->m_dr_taskq);
1627 		}
1628 		if (mutex_init_done) {
1629 			mutex_destroy(&mpt->m_tx_waitq_mutex);
1630 			mutex_destroy(&mpt->m_passthru_mutex);
1631 			mutex_destroy(&mpt->m_mutex);
1632 			for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1633 				mutex_destroy(
1634 				    &mpt->m_phy_info[i].smhba_info.phy_mutex);
1635 			}
1636 			cv_destroy(&mpt->m_cv);
1637 			cv_destroy(&mpt->m_passthru_cv);
1638 			cv_destroy(&mpt->m_fw_cv);
1639 			cv_destroy(&mpt->m_config_cv);
1640 			cv_destroy(&mpt->m_fw_diag_cv);
1641 			cv_destroy(&mpt->m_extreq_sense_refcount_cv);
1642 		}
1643 
1644 		if (map_setup) {
1645 			mptsas_cfg_fini(mpt);
1646 		}
1647 		if (config_setup) {
1648 			mptsas_config_space_fini(mpt);
1649 		}
1650 		mptsas_free_handshake_msg(mpt);
1651 		mptsas_hba_fini(mpt);
1652 
1653 		mptsas_fm_fini(mpt);
1654 		ddi_soft_state_free(mptsas_state, instance);
1655 		ddi_prop_remove_all(dip);
1656 	}
1657 	return (DDI_FAILURE);
1658 }
1659 
1660 static int
1661 mptsas_suspend(dev_info_t *devi)
1662 {
1663 	mptsas_t	*mpt, *g;
1664 	scsi_hba_tran_t	*tran;
1665 
1666 	if (scsi_hba_iport_unit_address(devi)) {
1667 		return (DDI_SUCCESS);
1668 	}
1669 
1670 	if ((tran = ddi_get_driver_private(devi)) == NULL)
1671 		return (DDI_SUCCESS);
1672 
1673 	mpt = TRAN2MPT(tran);
1674 	if (!mpt) {
1675 		return (DDI_SUCCESS);
1676 	}
1677 
1678 	mutex_enter(&mpt->m_mutex);
1679 
1680 	if (mpt->m_suspended++) {
1681 		mutex_exit(&mpt->m_mutex);
1682 		return (DDI_SUCCESS);
1683 	}
1684 
1685 	/*
1686 	 * Cancel timeout threads for this mpt
1687 	 */
1688 	if (mpt->m_quiesce_timeid) {
1689 		timeout_id_t tid = mpt->m_quiesce_timeid;
1690 		mpt->m_quiesce_timeid = 0;
1691 		mutex_exit(&mpt->m_mutex);
1692 		(void) untimeout(tid);
1693 		mutex_enter(&mpt->m_mutex);
1694 	}
1695 
1696 	if (mpt->m_restart_cmd_timeid) {
1697 		timeout_id_t tid = mpt->m_restart_cmd_timeid;
1698 		mpt->m_restart_cmd_timeid = 0;
1699 		mutex_exit(&mpt->m_mutex);
1700 		(void) untimeout(tid);
1701 		mutex_enter(&mpt->m_mutex);
1702 	}
1703 
1704 	mutex_exit(&mpt->m_mutex);
1705 
1706 	(void) pm_idle_component(mpt->m_dip, 0);
1707 
1708 	/*
1709 	 * Cancel watch threads if all mpts suspended
1710 	 */
1711 	rw_enter(&mptsas_global_rwlock, RW_WRITER);
1712 	for (g = mptsas_head; g != NULL; g = g->m_next) {
1713 		if (!g->m_suspended)
1714 			break;
1715 	}
1716 	rw_exit(&mptsas_global_rwlock);
1717 
1718 	mutex_enter(&mptsas_global_mutex);
1719 	if (g == NULL) {
1720 		timeout_id_t tid;
1721 
1722 		mptsas_timeouts_enabled = 0;
1723 		if (mptsas_timeout_id) {
1724 			tid = mptsas_timeout_id;
1725 			mptsas_timeout_id = 0;
1726 			mutex_exit(&mptsas_global_mutex);
1727 			(void) untimeout(tid);
1728 			mutex_enter(&mptsas_global_mutex);
1729 		}
1730 		if (mptsas_reset_watch) {
1731 			tid = mptsas_reset_watch;
1732 			mptsas_reset_watch = 0;
1733 			mutex_exit(&mptsas_global_mutex);
1734 			(void) untimeout(tid);
1735 			mutex_enter(&mptsas_global_mutex);
1736 		}
1737 	}
1738 	mutex_exit(&mptsas_global_mutex);
1739 
1740 	mutex_enter(&mpt->m_mutex);
1741 
1742 	/*
1743 	 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1744 	 */
1745 	if ((mpt->m_options & MPTSAS_OPT_PM) &&
1746 	    (mpt->m_power_level != PM_LEVEL_D0)) {
1747 		mutex_exit(&mpt->m_mutex);
1748 		return (DDI_SUCCESS);
1749 	}
1750 
1751 	/* Disable HBA interrupts in hardware */
1752 	MPTSAS_DISABLE_INTR(mpt);
1753 	/*
1754 	 * Send RAID action system shutdown to sync IR
1755 	 */
1756 	mptsas_raid_action_system_shutdown(mpt);
1757 
1758 	mutex_exit(&mpt->m_mutex);
1759 
1760 	/* drain the taskq */
1761 	ddi_taskq_wait(mpt->m_event_taskq);
1762 	ddi_taskq_wait(mpt->m_dr_taskq);
1763 
1764 	return (DDI_SUCCESS);
1765 }
1766 
1767 #ifdef	__sparc
1768 /*ARGSUSED*/
1769 static int
1770 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1771 {
1772 	mptsas_t	*mpt;
1773 	scsi_hba_tran_t *tran;
1774 
1775 	/*
1776 	 * If this call is for iport, just return.
1777 	 */
1778 	if (scsi_hba_iport_unit_address(devi))
1779 		return (DDI_SUCCESS);
1780 
1781 	if ((tran = ddi_get_driver_private(devi)) == NULL)
1782 		return (DDI_SUCCESS);
1783 
1784 	if ((mpt = TRAN2MPT(tran)) == NULL)
1785 		return (DDI_SUCCESS);
1786 
1787 	/*
1788 	 * Send RAID action system shutdown to sync IR.  Disable HBA
1789 	 * interrupts in hardware first.
1790 	 */
1791 	MPTSAS_DISABLE_INTR(mpt);
1792 	mptsas_raid_action_system_shutdown(mpt);
1793 
1794 	return (DDI_SUCCESS);
1795 }
1796 #else /* __sparc */
1797 /*
1798  * quiesce(9E) entry point.
1799  *
1800  * This function is called when the system is single-threaded at high
1801  * PIL with preemption disabled. Therefore, this function must not be
1802  * blocked.
1803  *
1804  * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1805  * DDI_FAILURE indicates an error condition and should almost never happen.
1806  */
1807 static int
1808 mptsas_quiesce(dev_info_t *devi)
1809 {
1810 	mptsas_t	*mpt;
1811 	scsi_hba_tran_t *tran;
1812 
1813 	/*
1814 	 * If this call is for iport, just return.
1815 	 */
1816 	if (scsi_hba_iport_unit_address(devi))
1817 		return (DDI_SUCCESS);
1818 
1819 	if ((tran = ddi_get_driver_private(devi)) == NULL)
1820 		return (DDI_SUCCESS);
1821 
1822 	if ((mpt = TRAN2MPT(tran)) == NULL)
1823 		return (DDI_SUCCESS);
1824 
1825 	/* Disable HBA interrupts in hardware */
1826 	MPTSAS_DISABLE_INTR(mpt);
1827 	/* Send RAID action system shutdonw to sync IR */
1828 	mptsas_raid_action_system_shutdown(mpt);
1829 
1830 	return (DDI_SUCCESS);
1831 }
1832 #endif	/* __sparc */
1833 
1834 /*
1835  * detach(9E).	Remove all device allocations and system resources;
1836  * disable device interrupts.
1837  * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1838  */
1839 static int
1840 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1841 {
1842 	/* CONSTCOND */
1843 	ASSERT(NO_COMPETING_THREADS);
1844 	NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1845 
1846 	switch (cmd) {
1847 	case DDI_DETACH:
1848 		return (mptsas_do_detach(devi));
1849 
1850 	case DDI_SUSPEND:
1851 		return (mptsas_suspend(devi));
1852 
1853 	default:
1854 		return (DDI_FAILURE);
1855 	}
1856 	/* NOTREACHED */
1857 }
1858 
1859 static int
1860 mptsas_do_detach(dev_info_t *dip)
1861 {
1862 	mptsas_t	*mpt;
1863 	scsi_hba_tran_t	*tran;
1864 	int		circ = 0;
1865 	int		circ1 = 0;
1866 	mdi_pathinfo_t	*pip = NULL;
1867 	int		i;
1868 	int		doneq_thread_num = 0;
1869 
1870 	NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1871 
1872 	if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1873 		return (DDI_FAILURE);
1874 
1875 	mpt = TRAN2MPT(tran);
1876 	if (!mpt) {
1877 		return (DDI_FAILURE);
1878 	}
1879 	/*
1880 	 * Still have pathinfo child, should not detach mpt driver
1881 	 */
1882 	if (scsi_hba_iport_unit_address(dip)) {
1883 		if (mpt->m_mpxio_enable) {
1884 			/*
1885 			 * MPxIO enabled for the iport
1886 			 */
1887 			ndi_devi_enter(scsi_vhci_dip, &circ1);
1888 			ndi_devi_enter(dip, &circ);
1889 			while ((pip = mdi_get_next_client_path(dip, NULL)) !=
1890 			    NULL) {
1891 				if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1892 					continue;
1893 				}
1894 				ndi_devi_exit(dip, circ);
1895 				ndi_devi_exit(scsi_vhci_dip, circ1);
1896 				NDBG12(("detach failed because of "
1897 				    "outstanding path info"));
1898 				return (DDI_FAILURE);
1899 			}
1900 			ndi_devi_exit(dip, circ);
1901 			ndi_devi_exit(scsi_vhci_dip, circ1);
1902 			(void) mdi_phci_unregister(dip, 0);
1903 		}
1904 
1905 		ddi_prop_remove_all(dip);
1906 
1907 		return (DDI_SUCCESS);
1908 	}
1909 
1910 	/* Make sure power level is D0 before accessing registers */
1911 	if (mpt->m_options & MPTSAS_OPT_PM) {
1912 		(void) pm_busy_component(dip, 0);
1913 		if (mpt->m_power_level != PM_LEVEL_D0) {
1914 			if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1915 			    DDI_SUCCESS) {
1916 				mptsas_log(mpt, CE_WARN,
1917 				    "mptsas%d: Raise power request failed.",
1918 				    mpt->m_instance);
1919 				(void) pm_idle_component(dip, 0);
1920 				return (DDI_FAILURE);
1921 			}
1922 		}
1923 	}
1924 
1925 	/*
1926 	 * Send RAID action system shutdown to sync IR.  After action, send a
1927 	 * Message Unit Reset. Since after that DMA resource will be freed,
1928 	 * set ioc to READY state will avoid HBA initiated DMA operation.
1929 	 */
1930 	mutex_enter(&mpt->m_mutex);
1931 	MPTSAS_DISABLE_INTR(mpt);
1932 	mptsas_raid_action_system_shutdown(mpt);
1933 	mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1934 	(void) mptsas_ioc_reset(mpt, FALSE);
1935 	mutex_exit(&mpt->m_mutex);
1936 	mptsas_rem_intrs(mpt);
1937 	ddi_taskq_destroy(mpt->m_event_taskq);
1938 	ddi_taskq_destroy(mpt->m_dr_taskq);
1939 
1940 	if (mpt->m_doneq_thread_n) {
1941 		mutex_enter(&mpt->m_doneq_mutex);
1942 		doneq_thread_num = mpt->m_doneq_thread_n;
1943 		for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1944 			mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1945 			mpt->m_doneq_thread_id[i].flag &=
1946 			    (~MPTSAS_DONEQ_THREAD_ACTIVE);
1947 			cv_signal(&mpt->m_doneq_thread_id[i].cv);
1948 			mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1949 		}
1950 		while (mpt->m_doneq_thread_n) {
1951 			cv_wait(&mpt->m_doneq_thread_cv,
1952 			    &mpt->m_doneq_mutex);
1953 		}
1954 		for (i = 0;  i < doneq_thread_num; i++) {
1955 			cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1956 			mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1957 		}
1958 		kmem_free(mpt->m_doneq_thread_id,
1959 		    sizeof (mptsas_doneq_thread_list_t)
1960 		    * doneq_thread_num);
1961 		mutex_exit(&mpt->m_doneq_mutex);
1962 		cv_destroy(&mpt->m_doneq_thread_cv);
1963 		mutex_destroy(&mpt->m_doneq_mutex);
1964 	}
1965 
1966 	scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1967 
1968 	mptsas_list_del(mpt);
1969 
1970 	/*
1971 	 * Cancel timeout threads for this mpt
1972 	 */
1973 	mutex_enter(&mpt->m_mutex);
1974 	if (mpt->m_quiesce_timeid) {
1975 		timeout_id_t tid = mpt->m_quiesce_timeid;
1976 		mpt->m_quiesce_timeid = 0;
1977 		mutex_exit(&mpt->m_mutex);
1978 		(void) untimeout(tid);
1979 		mutex_enter(&mpt->m_mutex);
1980 	}
1981 
1982 	if (mpt->m_restart_cmd_timeid) {
1983 		timeout_id_t tid = mpt->m_restart_cmd_timeid;
1984 		mpt->m_restart_cmd_timeid = 0;
1985 		mutex_exit(&mpt->m_mutex);
1986 		(void) untimeout(tid);
1987 		mutex_enter(&mpt->m_mutex);
1988 	}
1989 
1990 	mutex_exit(&mpt->m_mutex);
1991 
1992 	/*
1993 	 * last mpt? ... if active, CANCEL watch threads.
1994 	 */
1995 	mutex_enter(&mptsas_global_mutex);
1996 	if (mptsas_head == NULL) {
1997 		timeout_id_t tid;
1998 		/*
1999 		 * Clear mptsas_timeouts_enable so that the watch thread
2000 		 * gets restarted on DDI_ATTACH
2001 		 */
2002 		mptsas_timeouts_enabled = 0;
2003 		if (mptsas_timeout_id) {
2004 			tid = mptsas_timeout_id;
2005 			mptsas_timeout_id = 0;
2006 			mutex_exit(&mptsas_global_mutex);
2007 			(void) untimeout(tid);
2008 			mutex_enter(&mptsas_global_mutex);
2009 		}
2010 		if (mptsas_reset_watch) {
2011 			tid = mptsas_reset_watch;
2012 			mptsas_reset_watch = 0;
2013 			mutex_exit(&mptsas_global_mutex);
2014 			(void) untimeout(tid);
2015 			mutex_enter(&mptsas_global_mutex);
2016 		}
2017 	}
2018 	mutex_exit(&mptsas_global_mutex);
2019 
2020 	/*
2021 	 * Delete Phy stats
2022 	 */
2023 	mptsas_destroy_phy_stats(mpt);
2024 
2025 	mptsas_destroy_hashes(mpt);
2026 
2027 	/*
2028 	 * Delete nt_active.
2029 	 */
2030 	mutex_enter(&mpt->m_mutex);
2031 	mptsas_free_active_slots(mpt);
2032 	mutex_exit(&mpt->m_mutex);
2033 
2034 	/* deallocate everything that was allocated in mptsas_attach */
2035 	mptsas_cache_destroy(mpt);
2036 
2037 	mptsas_hba_fini(mpt);
2038 	mptsas_cfg_fini(mpt);
2039 
2040 	/* Lower the power informing PM Framework */
2041 	if (mpt->m_options & MPTSAS_OPT_PM) {
2042 		if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
2043 			mptsas_log(mpt, CE_WARN,
2044 			    "!mptsas%d: Lower power request failed "
2045 			    "during detach, ignoring.",
2046 			    mpt->m_instance);
2047 	}
2048 
2049 	mutex_destroy(&mpt->m_tx_waitq_mutex);
2050 	mutex_destroy(&mpt->m_passthru_mutex);
2051 	mutex_destroy(&mpt->m_mutex);
2052 	for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
2053 		mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
2054 	}
2055 	cv_destroy(&mpt->m_cv);
2056 	cv_destroy(&mpt->m_passthru_cv);
2057 	cv_destroy(&mpt->m_fw_cv);
2058 	cv_destroy(&mpt->m_config_cv);
2059 	cv_destroy(&mpt->m_fw_diag_cv);
2060 	cv_destroy(&mpt->m_extreq_sense_refcount_cv);
2061 
2062 	mptsas_smp_teardown(mpt);
2063 	mptsas_enc_teardown(mpt);
2064 	mptsas_hba_teardown(mpt);
2065 
2066 	mptsas_config_space_fini(mpt);
2067 
2068 	mptsas_free_handshake_msg(mpt);
2069 
2070 	mptsas_fm_fini(mpt);
2071 	ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
2072 	ddi_prop_remove_all(dip);
2073 
2074 	return (DDI_SUCCESS);
2075 }
2076 
2077 static void
2078 mptsas_list_add(mptsas_t *mpt)
2079 {
2080 	rw_enter(&mptsas_global_rwlock, RW_WRITER);
2081 
2082 	if (mptsas_head == NULL) {
2083 		mptsas_head = mpt;
2084 	} else {
2085 		mptsas_tail->m_next = mpt;
2086 	}
2087 	mptsas_tail = mpt;
2088 	rw_exit(&mptsas_global_rwlock);
2089 }
2090 
2091 static void
2092 mptsas_list_del(mptsas_t *mpt)
2093 {
2094 	mptsas_t *m;
2095 	/*
2096 	 * Remove device instance from the global linked list
2097 	 */
2098 	rw_enter(&mptsas_global_rwlock, RW_WRITER);
2099 	if (mptsas_head == mpt) {
2100 		m = mptsas_head = mpt->m_next;
2101 	} else {
2102 		for (m = mptsas_head; m != NULL; m = m->m_next) {
2103 			if (m->m_next == mpt) {
2104 				m->m_next = mpt->m_next;
2105 				break;
2106 			}
2107 		}
2108 		if (m == NULL) {
2109 			mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2110 		}
2111 	}
2112 
2113 	if (mptsas_tail == mpt) {
2114 		mptsas_tail = m;
2115 	}
2116 	rw_exit(&mptsas_global_rwlock);
2117 }
2118 
2119 static int
2120 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2121 {
2122 	ddi_dma_attr_t	task_dma_attrs;
2123 
2124 	mpt->m_hshk_dma_size = 0;
2125 	task_dma_attrs = mpt->m_msg_dma_attr;
2126 	task_dma_attrs.dma_attr_sgllen = 1;
2127 	task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2128 
2129 	/* allocate Task Management ddi_dma resources */
2130 	if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2131 	    &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2132 	    alloc_size, NULL) == FALSE) {
2133 		return (DDI_FAILURE);
2134 	}
2135 	mpt->m_hshk_dma_size = alloc_size;
2136 
2137 	return (DDI_SUCCESS);
2138 }
2139 
2140 static void
2141 mptsas_free_handshake_msg(mptsas_t *mpt)
2142 {
2143 	if (mpt->m_hshk_dma_size == 0)
2144 		return;
2145 	mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2146 	mpt->m_hshk_dma_size = 0;
2147 }
2148 
2149 static int
2150 mptsas_hba_setup(mptsas_t *mpt)
2151 {
2152 	scsi_hba_tran_t		*hba_tran;
2153 	int			tran_flags;
2154 
2155 	/* Allocate a transport structure */
2156 	hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2157 	    SCSI_HBA_CANSLEEP);
2158 	ASSERT(mpt->m_tran != NULL);
2159 
2160 	hba_tran->tran_hba_private	= mpt;
2161 	hba_tran->tran_tgt_private	= NULL;
2162 
2163 	hba_tran->tran_tgt_init		= mptsas_scsi_tgt_init;
2164 	hba_tran->tran_tgt_free		= mptsas_scsi_tgt_free;
2165 
2166 	hba_tran->tran_start		= mptsas_scsi_start;
2167 	hba_tran->tran_reset		= mptsas_scsi_reset;
2168 	hba_tran->tran_abort		= mptsas_scsi_abort;
2169 	hba_tran->tran_getcap		= mptsas_scsi_getcap;
2170 	hba_tran->tran_setcap		= mptsas_scsi_setcap;
2171 	hba_tran->tran_init_pkt		= mptsas_scsi_init_pkt;
2172 	hba_tran->tran_destroy_pkt	= mptsas_scsi_destroy_pkt;
2173 
2174 	hba_tran->tran_dmafree		= mptsas_scsi_dmafree;
2175 	hba_tran->tran_sync_pkt		= mptsas_scsi_sync_pkt;
2176 	hba_tran->tran_reset_notify	= mptsas_scsi_reset_notify;
2177 
2178 	hba_tran->tran_get_bus_addr	= mptsas_get_bus_addr;
2179 	hba_tran->tran_get_name		= mptsas_get_name;
2180 
2181 	hba_tran->tran_quiesce		= mptsas_scsi_quiesce;
2182 	hba_tran->tran_unquiesce	= mptsas_scsi_unquiesce;
2183 	hba_tran->tran_bus_reset	= NULL;
2184 
2185 	hba_tran->tran_add_eventcall	= NULL;
2186 	hba_tran->tran_get_eventcookie	= NULL;
2187 	hba_tran->tran_post_event	= NULL;
2188 	hba_tran->tran_remove_eventcall	= NULL;
2189 
2190 	hba_tran->tran_bus_config	= mptsas_bus_config;
2191 
2192 	hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2193 
2194 	/*
2195 	 * All children of the HBA are iports. We need tran was cloned.
2196 	 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2197 	 * inherited to iport's tran vector.
2198 	 */
2199 	tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2200 
2201 	if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2202 	    hba_tran, tran_flags) != DDI_SUCCESS) {
2203 		mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2204 		scsi_hba_tran_free(hba_tran);
2205 		mpt->m_tran = NULL;
2206 		return (FALSE);
2207 	}
2208 	return (TRUE);
2209 }
2210 
2211 static void
2212 mptsas_hba_teardown(mptsas_t *mpt)
2213 {
2214 	(void) scsi_hba_detach(mpt->m_dip);
2215 	if (mpt->m_tran != NULL) {
2216 		scsi_hba_tran_free(mpt->m_tran);
2217 		mpt->m_tran = NULL;
2218 	}
2219 }
2220 
2221 static void
2222 mptsas_iport_register(mptsas_t *mpt)
2223 {
2224 	int i, j;
2225 	mptsas_phymask_t	mask = 0x0;
2226 	/*
2227 	 * initial value of mask is 0
2228 	 */
2229 	mutex_enter(&mpt->m_mutex);
2230 	for (i = 0; i < mpt->m_num_phys; i++) {
2231 		mptsas_phymask_t phy_mask = 0x0;
2232 		char phy_mask_name[MPTSAS_MAX_PHYS];
2233 		uint8_t current_port;
2234 
2235 		if (mpt->m_phy_info[i].attached_devhdl == 0)
2236 			continue;
2237 
2238 		bzero(phy_mask_name, sizeof (phy_mask_name));
2239 
2240 		current_port = mpt->m_phy_info[i].port_num;
2241 
2242 		if ((mask & (1 << i)) != 0)
2243 			continue;
2244 
2245 		for (j = 0; j < mpt->m_num_phys; j++) {
2246 			if (mpt->m_phy_info[j].attached_devhdl &&
2247 			    (mpt->m_phy_info[j].port_num == current_port)) {
2248 				phy_mask |= (1 << j);
2249 			}
2250 		}
2251 		mask = mask | phy_mask;
2252 
2253 		for (j = 0; j < mpt->m_num_phys; j++) {
2254 			if ((phy_mask >> j) & 0x01) {
2255 				mpt->m_phy_info[j].phy_mask = phy_mask;
2256 			}
2257 		}
2258 
2259 		(void) sprintf(phy_mask_name, "%x", phy_mask);
2260 
2261 		mutex_exit(&mpt->m_mutex);
2262 		/*
2263 		 * register a iport
2264 		 */
2265 		(void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2266 		mutex_enter(&mpt->m_mutex);
2267 	}
2268 	mutex_exit(&mpt->m_mutex);
2269 	/*
2270 	 * register a virtual port for RAID volume always
2271 	 */
2272 	(void) scsi_hba_iport_register(mpt->m_dip, "v0");
2273 
2274 }
2275 
2276 static int
2277 mptsas_smp_setup(mptsas_t *mpt)
2278 {
2279 	mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2280 	ASSERT(mpt->m_smptran != NULL);
2281 	mpt->m_smptran->smp_tran_hba_private = mpt;
2282 	mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2283 	if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2284 		mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2285 		smp_hba_tran_free(mpt->m_smptran);
2286 		mpt->m_smptran = NULL;
2287 		return (FALSE);
2288 	}
2289 	/*
2290 	 * Initialize smp hash table
2291 	 */
2292 	mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT,
2293 	    mptsas_target_addr_hash, mptsas_target_addr_cmp,
2294 	    mptsas_smp_free, sizeof (mptsas_smp_t),
2295 	    offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr),
2296 	    KM_SLEEP);
2297 	mpt->m_smp_devhdl = 0xFFFF;
2298 
2299 	return (TRUE);
2300 }
2301 
2302 static void
2303 mptsas_smp_teardown(mptsas_t *mpt)
2304 {
2305 	(void) smp_hba_detach(mpt->m_dip);
2306 	if (mpt->m_smptran != NULL) {
2307 		smp_hba_tran_free(mpt->m_smptran);
2308 		mpt->m_smptran = NULL;
2309 	}
2310 	mpt->m_smp_devhdl = 0;
2311 }
2312 
2313 static int
2314 mptsas_enc_setup(mptsas_t *mpt)
2315 {
2316 	list_create(&mpt->m_enclosures, sizeof (mptsas_enclosure_t),
2317 	    offsetof(mptsas_enclosure_t, me_link));
2318 	return (TRUE);
2319 }
2320 
2321 static void
2322 mptsas_enc_free(mptsas_enclosure_t *mep)
2323 {
2324 	if (mep == NULL)
2325 		return;
2326 	if (mep->me_slotleds != NULL) {
2327 		VERIFY3U(mep->me_nslots, >, 0);
2328 		kmem_free(mep->me_slotleds, sizeof (uint8_t) * mep->me_nslots);
2329 	}
2330 	kmem_free(mep, sizeof (mptsas_enclosure_t));
2331 }
2332 
2333 static void
2334 mptsas_enc_teardown(mptsas_t *mpt)
2335 {
2336 	mptsas_enclosure_t *mep;
2337 
2338 	while ((mep = list_remove_head(&mpt->m_enclosures)) != NULL) {
2339 		mptsas_enc_free(mep);
2340 	}
2341 	list_destroy(&mpt->m_enclosures);
2342 }
2343 
2344 static mptsas_enclosure_t *
2345 mptsas_enc_lookup(mptsas_t *mpt, uint16_t hdl)
2346 {
2347 	mptsas_enclosure_t *mep;
2348 
2349 	ASSERT(MUTEX_HELD(&mpt->m_mutex));
2350 
2351 	for (mep = list_head(&mpt->m_enclosures); mep != NULL;
2352 	    mep = list_next(&mpt->m_enclosures, mep)) {
2353 		if (hdl == mep->me_enchdl) {
2354 			return (mep);
2355 		}
2356 	}
2357 
2358 	return (NULL);
2359 }
2360 
2361 static int
2362 mptsas_cache_create(mptsas_t *mpt)
2363 {
2364 	int instance = mpt->m_instance;
2365 	char buf[64];
2366 
2367 	/*
2368 	 * create kmem cache for packets
2369 	 */
2370 	(void) sprintf(buf, "mptsas%d_cache", instance);
2371 	mpt->m_kmem_cache = kmem_cache_create(buf,
2372 	    sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2373 	    mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2374 	    NULL, (void *)mpt, NULL, 0);
2375 
2376 	if (mpt->m_kmem_cache == NULL) {
2377 		mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2378 		return (FALSE);
2379 	}
2380 
2381 	/*
2382 	 * create kmem cache for extra SGL frames if SGL cannot
2383 	 * be accomodated into main request frame.
2384 	 */
2385 	(void) sprintf(buf, "mptsas%d_cache_frames", instance);
2386 	mpt->m_cache_frames = kmem_cache_create(buf,
2387 	    sizeof (mptsas_cache_frames_t), 8,
2388 	    mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2389 	    NULL, (void *)mpt, NULL, 0);
2390 
2391 	if (mpt->m_cache_frames == NULL) {
2392 		mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2393 		return (FALSE);
2394 	}
2395 
2396 	return (TRUE);
2397 }
2398 
2399 static void
2400 mptsas_cache_destroy(mptsas_t *mpt)
2401 {
2402 	/* deallocate in reverse order */
2403 	if (mpt->m_cache_frames) {
2404 		kmem_cache_destroy(mpt->m_cache_frames);
2405 		mpt->m_cache_frames = NULL;
2406 	}
2407 	if (mpt->m_kmem_cache) {
2408 		kmem_cache_destroy(mpt->m_kmem_cache);
2409 		mpt->m_kmem_cache = NULL;
2410 	}
2411 }
2412 
2413 static int
2414 mptsas_power(dev_info_t *dip, int component, int level)
2415 {
2416 #ifndef __lock_lint
2417 	_NOTE(ARGUNUSED(component))
2418 #endif
2419 	mptsas_t	*mpt;
2420 	int		rval = DDI_SUCCESS;
2421 	int		polls = 0;
2422 	uint32_t	ioc_status;
2423 
2424 	if (scsi_hba_iport_unit_address(dip) != 0)
2425 		return (DDI_SUCCESS);
2426 
2427 	mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2428 	if (mpt == NULL) {
2429 		return (DDI_FAILURE);
2430 	}
2431 
2432 	mutex_enter(&mpt->m_mutex);
2433 
2434 	/*
2435 	 * If the device is busy, don't lower its power level
2436 	 */
2437 	if (mpt->m_busy && (mpt->m_power_level > level)) {
2438 		mutex_exit(&mpt->m_mutex);
2439 		return (DDI_FAILURE);
2440 	}
2441 	switch (level) {
2442 	case PM_LEVEL_D0:
2443 		NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2444 		MPTSAS_POWER_ON(mpt);
2445 		/*
2446 		 * Wait up to 30 seconds for IOC to come out of reset.
2447 		 */
2448 		while (((ioc_status = ddi_get32(mpt->m_datap,
2449 		    &mpt->m_reg->Doorbell)) &
2450 		    MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2451 			if (polls++ > 3000) {
2452 				break;
2453 			}
2454 			delay(drv_usectohz(10000));
2455 		}
2456 		/*
2457 		 * If IOC is not in operational state, try to hard reset it.
2458 		 */
2459 		if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2460 		    MPI2_IOC_STATE_OPERATIONAL) {
2461 			mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2462 			if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2463 				mptsas_log(mpt, CE_WARN,
2464 				    "mptsas_power: hard reset failed");
2465 				mutex_exit(&mpt->m_mutex);
2466 				return (DDI_FAILURE);
2467 			}
2468 		}
2469 		mpt->m_power_level = PM_LEVEL_D0;
2470 		break;
2471 	case PM_LEVEL_D3:
2472 		NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2473 		MPTSAS_POWER_OFF(mpt);
2474 		break;
2475 	default:
2476 		mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2477 		    mpt->m_instance, level);
2478 		rval = DDI_FAILURE;
2479 		break;
2480 	}
2481 	mutex_exit(&mpt->m_mutex);
2482 	return (rval);
2483 }
2484 
2485 /*
2486  * Initialize configuration space and figure out which
2487  * chip and revison of the chip the mpt driver is using.
2488  */
2489 static int
2490 mptsas_config_space_init(mptsas_t *mpt)
2491 {
2492 	NDBG0(("mptsas_config_space_init"));
2493 
2494 	if (mpt->m_config_handle != NULL)
2495 		return (TRUE);
2496 
2497 	if (pci_config_setup(mpt->m_dip,
2498 	    &mpt->m_config_handle) != DDI_SUCCESS) {
2499 		mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2500 		return (FALSE);
2501 	}
2502 
2503 	/*
2504 	 * This is a workaround for a XMITS ASIC bug which does not
2505 	 * drive the CBE upper bits.
2506 	 */
2507 	if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2508 	    PCI_STAT_PERROR) {
2509 		pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2510 		    PCI_STAT_PERROR);
2511 	}
2512 
2513 	mptsas_setup_cmd_reg(mpt);
2514 
2515 	/*
2516 	 * Get the chip device id:
2517 	 */
2518 	mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2519 
2520 	/*
2521 	 * Save the revision.
2522 	 */
2523 	mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2524 
2525 	/*
2526 	 * Save the SubSystem Vendor and Device IDs
2527 	 */
2528 	mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2529 	mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2530 
2531 	/*
2532 	 * Set the latency timer to 0x40 as specified by the upa -> pci
2533 	 * bridge chip design team.  This may be done by the sparc pci
2534 	 * bus nexus driver, but the driver should make sure the latency
2535 	 * timer is correct for performance reasons.
2536 	 */
2537 	pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2538 	    MPTSAS_LATENCY_TIMER);
2539 
2540 	(void) mptsas_get_pci_cap(mpt);
2541 	return (TRUE);
2542 }
2543 
2544 static void
2545 mptsas_config_space_fini(mptsas_t *mpt)
2546 {
2547 	if (mpt->m_config_handle != NULL) {
2548 		mptsas_disable_bus_master(mpt);
2549 		pci_config_teardown(&mpt->m_config_handle);
2550 		mpt->m_config_handle = NULL;
2551 	}
2552 }
2553 
2554 static void
2555 mptsas_setup_cmd_reg(mptsas_t *mpt)
2556 {
2557 	ushort_t	cmdreg;
2558 
2559 	/*
2560 	 * Set the command register to the needed values.
2561 	 */
2562 	cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2563 	cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2564 	    PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2565 	cmdreg &= ~PCI_COMM_IO;
2566 	pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2567 }
2568 
2569 static void
2570 mptsas_disable_bus_master(mptsas_t *mpt)
2571 {
2572 	ushort_t	cmdreg;
2573 
2574 	/*
2575 	 * Clear the master enable bit in the PCI command register.
2576 	 * This prevents any bus mastering activity like DMA.
2577 	 */
2578 	cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2579 	cmdreg &= ~PCI_COMM_ME;
2580 	pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2581 }
2582 
2583 int
2584 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2585 {
2586 	ddi_dma_attr_t	attrs;
2587 
2588 	attrs = mpt->m_io_dma_attr;
2589 	attrs.dma_attr_sgllen = 1;
2590 
2591 	ASSERT(dma_statep != NULL);
2592 
2593 	if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2594 	    &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2595 	    &dma_statep->cookie) == FALSE) {
2596 		return (DDI_FAILURE);
2597 	}
2598 
2599 	return (DDI_SUCCESS);
2600 }
2601 
2602 void
2603 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2604 {
2605 	ASSERT(dma_statep != NULL);
2606 	mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2607 	dma_statep->size = 0;
2608 }
2609 
2610 int
2611 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2612 {
2613 	ddi_dma_attr_t		attrs;
2614 	ddi_dma_handle_t	dma_handle;
2615 	caddr_t			memp;
2616 	ddi_acc_handle_t	accessp;
2617 	int			rval;
2618 
2619 	ASSERT(mutex_owned(&mpt->m_mutex));
2620 
2621 	attrs = mpt->m_msg_dma_attr;
2622 	attrs.dma_attr_sgllen = 1;
2623 	attrs.dma_attr_granular = size;
2624 
2625 	if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2626 	    &accessp, &memp, size, NULL) == FALSE) {
2627 		return (DDI_FAILURE);
2628 	}
2629 
2630 	rval = (*callback) (mpt, memp, var, accessp);
2631 
2632 	if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2633 	    (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2634 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2635 		rval = DDI_FAILURE;
2636 	}
2637 
2638 	mptsas_dma_addr_destroy(&dma_handle, &accessp);
2639 	return (rval);
2640 
2641 }
2642 
2643 static int
2644 mptsas_alloc_request_frames(mptsas_t *mpt)
2645 {
2646 	ddi_dma_attr_t		frame_dma_attrs;
2647 	caddr_t			memp;
2648 	ddi_dma_cookie_t	cookie;
2649 	size_t			mem_size;
2650 
2651 	/*
2652 	 * re-alloc when it has already alloced
2653 	 */
2654 	if (mpt->m_dma_req_frame_hdl)
2655 		mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2656 		    &mpt->m_acc_req_frame_hdl);
2657 
2658 	/*
2659 	 * The size of the request frame pool is:
2660 	 *   Number of Request Frames * Request Frame Size
2661 	 */
2662 	mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2663 
2664 	/*
2665 	 * set the DMA attributes.  System Request Message Frames must be
2666 	 * aligned on a 16-byte boundry.
2667 	 */
2668 	frame_dma_attrs = mpt->m_msg_dma_attr;
2669 	frame_dma_attrs.dma_attr_align = 16;
2670 	frame_dma_attrs.dma_attr_sgllen = 1;
2671 
2672 	/*
2673 	 * allocate the request frame pool.
2674 	 */
2675 	if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2676 	    &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2677 	    mem_size, &cookie) == FALSE) {
2678 		return (DDI_FAILURE);
2679 	}
2680 
2681 	/*
2682 	 * Store the request frame memory address.  This chip uses this
2683 	 * address to dma to and from the driver's frame.  The second
2684 	 * address is the address mpt uses to fill in the frame.
2685 	 */
2686 	mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2687 	mpt->m_req_frame = memp;
2688 
2689 	/*
2690 	 * Clear the request frame pool.
2691 	 */
2692 	bzero(mpt->m_req_frame, mem_size);
2693 
2694 	return (DDI_SUCCESS);
2695 }
2696 
2697 static int
2698 mptsas_alloc_sense_bufs(mptsas_t *mpt)
2699 {
2700 	ddi_dma_attr_t		sense_dma_attrs;
2701 	caddr_t			memp;
2702 	ddi_dma_cookie_t	cookie;
2703 	size_t			mem_size;
2704 	int			num_extrqsense_bufs;
2705 
2706 	ASSERT(mpt->m_extreq_sense_refcount == 0);
2707 
2708 	/*
2709 	 * re-alloc when it has already alloced
2710 	 */
2711 	if (mpt->m_dma_req_sense_hdl) {
2712 		rmfreemap(mpt->m_erqsense_map);
2713 		mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2714 		    &mpt->m_acc_req_sense_hdl);
2715 	}
2716 
2717 	/*
2718 	 * The size of the request sense pool is:
2719 	 *   (Number of Request Frames - 2 ) * Request Sense Size +
2720 	 *   extra memory for extended sense requests.
2721 	 */
2722 	mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) +
2723 	    mptsas_extreq_sense_bufsize;
2724 
2725 	/*
2726 	 * set the DMA attributes.  ARQ buffers
2727 	 * aligned on a 16-byte boundry.
2728 	 */
2729 	sense_dma_attrs = mpt->m_msg_dma_attr;
2730 	sense_dma_attrs.dma_attr_align = 16;
2731 	sense_dma_attrs.dma_attr_sgllen = 1;
2732 
2733 	/*
2734 	 * allocate the request sense buffer pool.
2735 	 */
2736 	if (mptsas_dma_addr_create(mpt, sense_dma_attrs,
2737 	    &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp,
2738 	    mem_size, &cookie) == FALSE) {
2739 		return (DDI_FAILURE);
2740 	}
2741 
2742 	/*
2743 	 * Store the request sense base memory address.  This chip uses this
2744 	 * address to dma the request sense data.  The second
2745 	 * address is the address mpt uses to access the data.
2746 	 * The third is the base for the extended rqsense buffers.
2747 	 */
2748 	mpt->m_req_sense_dma_addr = cookie.dmac_laddress;
2749 	mpt->m_req_sense = memp;
2750 	memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size;
2751 	mpt->m_extreq_sense = memp;
2752 
2753 	/*
2754 	 * The extra memory is divided up into multiples of the base
2755 	 * buffer size in order to allocate via rmalloc().
2756 	 * Note that the rmallocmap cannot start at zero!
2757 	 */
2758 	num_extrqsense_bufs = mptsas_extreq_sense_bufsize /
2759 	    mpt->m_req_sense_size;
2760 	mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs);
2761 	rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1);
2762 
2763 	/*
2764 	 * Clear the pool.
2765 	 */
2766 	bzero(mpt->m_req_sense, mem_size);
2767 
2768 	return (DDI_SUCCESS);
2769 }
2770 
2771 static int
2772 mptsas_alloc_reply_frames(mptsas_t *mpt)
2773 {
2774 	ddi_dma_attr_t		frame_dma_attrs;
2775 	caddr_t			memp;
2776 	ddi_dma_cookie_t	cookie;
2777 	size_t			mem_size;
2778 
2779 	/*
2780 	 * re-alloc when it has already alloced
2781 	 */
2782 	if (mpt->m_dma_reply_frame_hdl) {
2783 		mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2784 		    &mpt->m_acc_reply_frame_hdl);
2785 	}
2786 
2787 	/*
2788 	 * The size of the reply frame pool is:
2789 	 *   Number of Reply Frames * Reply Frame Size
2790 	 */
2791 	mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2792 
2793 	/*
2794 	 * set the DMA attributes.   System Reply Message Frames must be
2795 	 * aligned on a 4-byte boundry.  This is the default.
2796 	 */
2797 	frame_dma_attrs = mpt->m_msg_dma_attr;
2798 	frame_dma_attrs.dma_attr_sgllen = 1;
2799 
2800 	/*
2801 	 * allocate the reply frame pool
2802 	 */
2803 	if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2804 	    &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2805 	    mem_size, &cookie) == FALSE) {
2806 		return (DDI_FAILURE);
2807 	}
2808 
2809 	/*
2810 	 * Store the reply frame memory address.  This chip uses this
2811 	 * address to dma to and from the driver's frame.  The second
2812 	 * address is the address mpt uses to process the frame.
2813 	 */
2814 	mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2815 	mpt->m_reply_frame = memp;
2816 
2817 	/*
2818 	 * Clear the reply frame pool.
2819 	 */
2820 	bzero(mpt->m_reply_frame, mem_size);
2821 
2822 	return (DDI_SUCCESS);
2823 }
2824 
2825 static int
2826 mptsas_alloc_free_queue(mptsas_t *mpt)
2827 {
2828 	ddi_dma_attr_t		frame_dma_attrs;
2829 	caddr_t			memp;
2830 	ddi_dma_cookie_t	cookie;
2831 	size_t			mem_size;
2832 
2833 	/*
2834 	 * re-alloc when it has already alloced
2835 	 */
2836 	if (mpt->m_dma_free_queue_hdl) {
2837 		mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2838 		    &mpt->m_acc_free_queue_hdl);
2839 	}
2840 
2841 	/*
2842 	 * The reply free queue size is:
2843 	 *   Reply Free Queue Depth * 4
2844 	 * The "4" is the size of one 32 bit address (low part of 64-bit
2845 	 *   address)
2846 	 */
2847 	mem_size = mpt->m_free_queue_depth * 4;
2848 
2849 	/*
2850 	 * set the DMA attributes  The Reply Free Queue must be aligned on a
2851 	 * 16-byte boundry.
2852 	 */
2853 	frame_dma_attrs = mpt->m_msg_dma_attr;
2854 	frame_dma_attrs.dma_attr_align = 16;
2855 	frame_dma_attrs.dma_attr_sgllen = 1;
2856 
2857 	/*
2858 	 * allocate the reply free queue
2859 	 */
2860 	if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2861 	    &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2862 	    mem_size, &cookie) == FALSE) {
2863 		return (DDI_FAILURE);
2864 	}
2865 
2866 	/*
2867 	 * Store the reply free queue memory address.  This chip uses this
2868 	 * address to read from the reply free queue.  The second address
2869 	 * is the address mpt uses to manage the queue.
2870 	 */
2871 	mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2872 	mpt->m_free_queue = memp;
2873 
2874 	/*
2875 	 * Clear the reply free queue memory.
2876 	 */
2877 	bzero(mpt->m_free_queue, mem_size);
2878 
2879 	return (DDI_SUCCESS);
2880 }
2881 
2882 static int
2883 mptsas_alloc_post_queue(mptsas_t *mpt)
2884 {
2885 	ddi_dma_attr_t		frame_dma_attrs;
2886 	caddr_t			memp;
2887 	ddi_dma_cookie_t	cookie;
2888 	size_t			mem_size;
2889 
2890 	/*
2891 	 * re-alloc when it has already alloced
2892 	 */
2893 	if (mpt->m_dma_post_queue_hdl) {
2894 		mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2895 		    &mpt->m_acc_post_queue_hdl);
2896 	}
2897 
2898 	/*
2899 	 * The reply descriptor post queue size is:
2900 	 *   Reply Descriptor Post Queue Depth * 8
2901 	 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2902 	 */
2903 	mem_size = mpt->m_post_queue_depth * 8;
2904 
2905 	/*
2906 	 * set the DMA attributes.  The Reply Descriptor Post Queue must be
2907 	 * aligned on a 16-byte boundry.
2908 	 */
2909 	frame_dma_attrs = mpt->m_msg_dma_attr;
2910 	frame_dma_attrs.dma_attr_align = 16;
2911 	frame_dma_attrs.dma_attr_sgllen = 1;
2912 
2913 	/*
2914 	 * allocate the reply post queue
2915 	 */
2916 	if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2917 	    &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2918 	    mem_size, &cookie) == FALSE) {
2919 		return (DDI_FAILURE);
2920 	}
2921 
2922 	/*
2923 	 * Store the reply descriptor post queue memory address.  This chip
2924 	 * uses this address to write to the reply descriptor post queue.  The
2925 	 * second address is the address mpt uses to manage the queue.
2926 	 */
2927 	mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2928 	mpt->m_post_queue = memp;
2929 
2930 	/*
2931 	 * Clear the reply post queue memory.
2932 	 */
2933 	bzero(mpt->m_post_queue, mem_size);
2934 
2935 	return (DDI_SUCCESS);
2936 }
2937 
2938 static void
2939 mptsas_alloc_reply_args(mptsas_t *mpt)
2940 {
2941 	if (mpt->m_replyh_args == NULL) {
2942 		mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2943 		    mpt->m_max_replies, KM_SLEEP);
2944 	}
2945 }
2946 
2947 static int
2948 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2949 {
2950 	mptsas_cache_frames_t	*frames = NULL;
2951 	if (cmd->cmd_extra_frames == NULL) {
2952 		frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2953 		if (frames == NULL) {
2954 			return (DDI_FAILURE);
2955 		}
2956 		cmd->cmd_extra_frames = frames;
2957 	}
2958 	return (DDI_SUCCESS);
2959 }
2960 
2961 static void
2962 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2963 {
2964 	if (cmd->cmd_extra_frames) {
2965 		kmem_cache_free(mpt->m_cache_frames,
2966 		    (void *)cmd->cmd_extra_frames);
2967 		cmd->cmd_extra_frames = NULL;
2968 	}
2969 }
2970 
2971 static void
2972 mptsas_cfg_fini(mptsas_t *mpt)
2973 {
2974 	NDBG0(("mptsas_cfg_fini"));
2975 	ddi_regs_map_free(&mpt->m_datap);
2976 }
2977 
2978 static void
2979 mptsas_hba_fini(mptsas_t *mpt)
2980 {
2981 	NDBG0(("mptsas_hba_fini"));
2982 
2983 	/*
2984 	 * Free up any allocated memory
2985 	 */
2986 	if (mpt->m_dma_req_frame_hdl) {
2987 		mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2988 		    &mpt->m_acc_req_frame_hdl);
2989 	}
2990 
2991 	if (mpt->m_dma_req_sense_hdl) {
2992 		rmfreemap(mpt->m_erqsense_map);
2993 		mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2994 		    &mpt->m_acc_req_sense_hdl);
2995 	}
2996 
2997 	if (mpt->m_dma_reply_frame_hdl) {
2998 		mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2999 		    &mpt->m_acc_reply_frame_hdl);
3000 	}
3001 
3002 	if (mpt->m_dma_free_queue_hdl) {
3003 		mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
3004 		    &mpt->m_acc_free_queue_hdl);
3005 	}
3006 
3007 	if (mpt->m_dma_post_queue_hdl) {
3008 		mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
3009 		    &mpt->m_acc_post_queue_hdl);
3010 	}
3011 
3012 	if (mpt->m_replyh_args != NULL) {
3013 		kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
3014 		    * mpt->m_max_replies);
3015 	}
3016 }
3017 
3018 static int
3019 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
3020 {
3021 	int		lun = 0;
3022 	char		*sas_wwn = NULL;
3023 	int		phynum = -1;
3024 	int		reallen = 0;
3025 
3026 	/* Get the target num */
3027 	lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
3028 	    LUN_PROP, 0);
3029 
3030 	if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
3031 	    DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
3032 		/*
3033 		 * Stick in the address of form "pPHY,LUN"
3034 		 */
3035 		reallen = snprintf(name, len, "p%x,%x", phynum, lun);
3036 	} else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
3037 	    DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
3038 	    == DDI_PROP_SUCCESS) {
3039 		/*
3040 		 * Stick in the address of the form "wWWN,LUN"
3041 		 */
3042 		reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
3043 		ddi_prop_free(sas_wwn);
3044 	} else {
3045 		return (DDI_FAILURE);
3046 	}
3047 
3048 	ASSERT(reallen < len);
3049 	if (reallen >= len) {
3050 		mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
3051 		    "length too small, it needs to be %d bytes", reallen + 1);
3052 	}
3053 	return (DDI_SUCCESS);
3054 }
3055 
3056 /*
3057  * tran_tgt_init(9E) - target device instance initialization
3058  */
3059 static int
3060 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3061     scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3062 {
3063 #ifndef __lock_lint
3064 	_NOTE(ARGUNUSED(hba_tran))
3065 #endif
3066 
3067 	/*
3068 	 * At this point, the scsi_device structure already exists
3069 	 * and has been initialized.
3070 	 *
3071 	 * Use this function to allocate target-private data structures,
3072 	 * if needed by this HBA.  Add revised flow-control and queue
3073 	 * properties for child here, if desired and if you can tell they
3074 	 * support tagged queueing by now.
3075 	 */
3076 	mptsas_t		*mpt;
3077 	int			lun = sd->sd_address.a_lun;
3078 	mdi_pathinfo_t		*pip = NULL;
3079 	mptsas_tgt_private_t	*tgt_private = NULL;
3080 	mptsas_target_t		*ptgt = NULL;
3081 	char			*psas_wwn = NULL;
3082 	mptsas_phymask_t	phymask = 0;
3083 	uint64_t		sas_wwn = 0;
3084 	mptsas_target_addr_t	addr;
3085 	mpt = SDEV2MPT(sd);
3086 
3087 	ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
3088 
3089 	NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
3090 	    (void *)hba_dip, (void *)tgt_dip, lun));
3091 
3092 	if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
3093 		(void) ndi_merge_node(tgt_dip, mptsas_name_child);
3094 		ddi_set_name_addr(tgt_dip, NULL);
3095 		return (DDI_FAILURE);
3096 	}
3097 	/*
3098 	 * phymask is 0 means the virtual port for RAID
3099 	 */
3100 	phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
3101 	    "phymask", 0);
3102 	if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3103 		if ((pip = (void *)(sd->sd_private)) == NULL) {
3104 			/*
3105 			 * Very bad news if this occurs. Somehow scsi_vhci has
3106 			 * lost the pathinfo node for this target.
3107 			 */
3108 			return (DDI_NOT_WELL_FORMED);
3109 		}
3110 
3111 		if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
3112 		    DDI_PROP_SUCCESS) {
3113 			mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
3114 			return (DDI_FAILURE);
3115 		}
3116 
3117 		if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
3118 		    &psas_wwn) == MDI_SUCCESS) {
3119 			if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3120 				sas_wwn = 0;
3121 			}
3122 			(void) mdi_prop_free(psas_wwn);
3123 		}
3124 	} else {
3125 		lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
3126 		    DDI_PROP_DONTPASS, LUN_PROP, 0);
3127 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
3128 		    DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
3129 		    DDI_PROP_SUCCESS) {
3130 			if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3131 				sas_wwn = 0;
3132 			}
3133 			ddi_prop_free(psas_wwn);
3134 		} else {
3135 			sas_wwn = 0;
3136 		}
3137 	}
3138 
3139 	ASSERT((sas_wwn != 0) || (phymask != 0));
3140 	addr.mta_wwn = sas_wwn;
3141 	addr.mta_phymask = phymask;
3142 	mutex_enter(&mpt->m_mutex);
3143 	ptgt = refhash_lookup(mpt->m_targets, &addr);
3144 	mutex_exit(&mpt->m_mutex);
3145 	if (ptgt == NULL) {
3146 		mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
3147 		    "gone already! phymask:%x, saswwn %"PRIx64, phymask,
3148 		    sas_wwn);
3149 		return (DDI_FAILURE);
3150 	}
3151 	if (hba_tran->tran_tgt_private == NULL) {
3152 		tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
3153 		    KM_SLEEP);
3154 		tgt_private->t_lun = lun;
3155 		tgt_private->t_private = ptgt;
3156 		hba_tran->tran_tgt_private = tgt_private;
3157 	}
3158 
3159 	if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3160 		return (DDI_SUCCESS);
3161 	}
3162 	mutex_enter(&mpt->m_mutex);
3163 
3164 	if (ptgt->m_deviceinfo &
3165 	    (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
3166 	    MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
3167 		uchar_t *inq89 = NULL;
3168 		int inq89_len = 0x238;
3169 		int reallen = 0;
3170 		int rval = 0;
3171 		struct sata_id *sid = NULL;
3172 		char model[SATA_ID_MODEL_LEN + 1];
3173 		char fw[SATA_ID_FW_LEN + 1];
3174 		char *vid, *pid;
3175 
3176 		mutex_exit(&mpt->m_mutex);
3177 		/*
3178 		 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
3179 		 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
3180 		 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
3181 		 */
3182 		inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
3183 		rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
3184 		    inq89, inq89_len, &reallen, 1);
3185 
3186 		if (rval != 0) {
3187 			if (inq89 != NULL) {
3188 				kmem_free(inq89, inq89_len);
3189 			}
3190 
3191 			mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
3192 			    "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
3193 			return (DDI_SUCCESS);
3194 		}
3195 		sid = (void *)(&inq89[60]);
3196 
3197 		swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
3198 		swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
3199 
3200 		model[SATA_ID_MODEL_LEN] = 0;
3201 		fw[SATA_ID_FW_LEN] = 0;
3202 
3203 		sata_split_model(model, &vid, &pid);
3204 
3205 		/*
3206 		 * override SCSA "inquiry-*" properties
3207 		 */
3208 		if (vid)
3209 			(void) scsi_device_prop_update_inqstring(sd,
3210 			    INQUIRY_VENDOR_ID, vid, strlen(vid));
3211 		if (pid)
3212 			(void) scsi_device_prop_update_inqstring(sd,
3213 			    INQUIRY_PRODUCT_ID, pid, strlen(pid));
3214 		(void) scsi_device_prop_update_inqstring(sd,
3215 		    INQUIRY_REVISION_ID, fw, strlen(fw));
3216 
3217 		if (inq89 != NULL) {
3218 			kmem_free(inq89, inq89_len);
3219 		}
3220 	} else {
3221 		mutex_exit(&mpt->m_mutex);
3222 	}
3223 
3224 	return (DDI_SUCCESS);
3225 }
3226 /*
3227  * tran_tgt_free(9E) - target device instance deallocation
3228  */
3229 static void
3230 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3231     scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3232 {
3233 #ifndef __lock_lint
3234 	_NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
3235 #endif
3236 
3237 	mptsas_tgt_private_t	*tgt_private = hba_tran->tran_tgt_private;
3238 
3239 	if (tgt_private != NULL) {
3240 		kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
3241 		hba_tran->tran_tgt_private = NULL;
3242 	}
3243 }
3244 
3245 /*
3246  * scsi_pkt handling
3247  *
3248  * Visible to the external world via the transport structure.
3249  */
3250 
3251 /*
3252  * Notes:
3253  *	- transport the command to the addressed SCSI target/lun device
3254  *	- normal operation is to schedule the command to be transported,
3255  *	  and return TRAN_ACCEPT if this is successful.
3256  *	- if NO_INTR, tran_start must poll device for command completion
3257  */
3258 static int
3259 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
3260 {
3261 #ifndef __lock_lint
3262 	_NOTE(ARGUNUSED(ap))
3263 #endif
3264 	mptsas_t	*mpt = PKT2MPT(pkt);
3265 	mptsas_cmd_t	*cmd = PKT2CMD(pkt);
3266 	int		rval;
3267 	mptsas_target_t	*ptgt = cmd->cmd_tgt_addr;
3268 
3269 	NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
3270 	ASSERT(ptgt);
3271 	if (ptgt == NULL)
3272 		return (TRAN_FATAL_ERROR);
3273 
3274 	/*
3275 	 * prepare the pkt before taking mutex.
3276 	 */
3277 	rval = mptsas_prepare_pkt(cmd);
3278 	if (rval != TRAN_ACCEPT) {
3279 		return (rval);
3280 	}
3281 
3282 	/*
3283 	 * Send the command to target/lun, however your HBA requires it.
3284 	 * If busy, return TRAN_BUSY; if there's some other formatting error
3285 	 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
3286 	 * return of TRAN_ACCEPT.
3287 	 *
3288 	 * Remember that access to shared resources, including the mptsas_t
3289 	 * data structure and the HBA hardware registers, must be protected
3290 	 * with mutexes, here and everywhere.
3291 	 *
3292 	 * Also remember that at interrupt time, you'll get an argument
3293 	 * to the interrupt handler which is a pointer to your mptsas_t
3294 	 * structure; you'll have to remember which commands are outstanding
3295 	 * and which scsi_pkt is the currently-running command so the
3296 	 * interrupt handler can refer to the pkt to set completion
3297 	 * status, call the target driver back through pkt_comp, etc.
3298 	 *
3299 	 * If the instance lock is held by other thread, don't spin to wait
3300 	 * for it. Instead, queue the cmd and next time when the instance lock
3301 	 * is not held, accept all the queued cmd. A extra tx_waitq is
3302 	 * introduced to protect the queue.
3303 	 *
3304 	 * The polled cmd will not be queud and accepted as usual.
3305 	 *
3306 	 * Under the tx_waitq mutex, record whether a thread is draining
3307 	 * the tx_waitq.  An IO requesting thread that finds the instance
3308 	 * mutex contended appends to the tx_waitq and while holding the
3309 	 * tx_wait mutex, if the draining flag is not set, sets it and then
3310 	 * proceeds to spin for the instance mutex. This scheme ensures that
3311 	 * the last cmd in a burst be processed.
3312 	 *
3313 	 * we enable this feature only when the helper threads are enabled,
3314 	 * at which we think the loads are heavy.
3315 	 *
3316 	 * per instance mutex m_tx_waitq_mutex is introduced to protect the
3317 	 * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3318 	 */
3319 
3320 	if (mpt->m_doneq_thread_n) {
3321 		if (mutex_tryenter(&mpt->m_mutex) != 0) {
3322 			rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3323 			mutex_exit(&mpt->m_mutex);
3324 		} else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3325 			mutex_enter(&mpt->m_mutex);
3326 			rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3327 			mutex_exit(&mpt->m_mutex);
3328 		} else {
3329 			mutex_enter(&mpt->m_tx_waitq_mutex);
3330 			/*
3331 			 * ptgt->m_dr_flag is protected by m_mutex or
3332 			 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3333 			 * is acquired.
3334 			 */
3335 			if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3336 				if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3337 					/*
3338 					 * The command should be allowed to
3339 					 * retry by returning TRAN_BUSY to
3340 					 * to stall the I/O's which come from
3341 					 * scsi_vhci since the device/path is
3342 					 * in unstable state now.
3343 					 */
3344 					mutex_exit(&mpt->m_tx_waitq_mutex);
3345 					return (TRAN_BUSY);
3346 				} else {
3347 					/*
3348 					 * The device is offline, just fail the
3349 					 * command by returning
3350 					 * TRAN_FATAL_ERROR.
3351 					 */
3352 					mutex_exit(&mpt->m_tx_waitq_mutex);
3353 					return (TRAN_FATAL_ERROR);
3354 				}
3355 			}
3356 			if (mpt->m_tx_draining) {
3357 				cmd->cmd_flags |= CFLAG_TXQ;
3358 				*mpt->m_tx_waitqtail = cmd;
3359 				mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3360 				mutex_exit(&mpt->m_tx_waitq_mutex);
3361 			} else { /* drain the queue */
3362 				mpt->m_tx_draining = 1;
3363 				mutex_exit(&mpt->m_tx_waitq_mutex);
3364 				mutex_enter(&mpt->m_mutex);
3365 				rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3366 				mutex_exit(&mpt->m_mutex);
3367 			}
3368 		}
3369 	} else {
3370 		mutex_enter(&mpt->m_mutex);
3371 		/*
3372 		 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3373 		 * in this case, m_mutex is acquired.
3374 		 */
3375 		if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3376 			if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3377 				/*
3378 				 * commands should be allowed to retry by
3379 				 * returning TRAN_BUSY to stall the I/O's
3380 				 * which come from scsi_vhci since the device/
3381 				 * path is in unstable state now.
3382 				 */
3383 				mutex_exit(&mpt->m_mutex);
3384 				return (TRAN_BUSY);
3385 			} else {
3386 				/*
3387 				 * The device is offline, just fail the
3388 				 * command by returning TRAN_FATAL_ERROR.
3389 				 */
3390 				mutex_exit(&mpt->m_mutex);
3391 				return (TRAN_FATAL_ERROR);
3392 			}
3393 		}
3394 		rval = mptsas_accept_pkt(mpt, cmd);
3395 		mutex_exit(&mpt->m_mutex);
3396 	}
3397 
3398 	return (rval);
3399 }
3400 
3401 /*
3402  * Accept all the queued cmds(if any) before accept the current one.
3403  */
3404 static int
3405 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3406 {
3407 	int rval;
3408 	mptsas_target_t	*ptgt = cmd->cmd_tgt_addr;
3409 
3410 	ASSERT(mutex_owned(&mpt->m_mutex));
3411 	/*
3412 	 * The call to mptsas_accept_tx_waitq() must always be performed
3413 	 * because that is where mpt->m_tx_draining is cleared.
3414 	 */
3415 	mutex_enter(&mpt->m_tx_waitq_mutex);
3416 	mptsas_accept_tx_waitq(mpt);
3417 	mutex_exit(&mpt->m_tx_waitq_mutex);
3418 	/*
3419 	 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3420 	 * in this case, m_mutex is acquired.
3421 	 */
3422 	if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3423 		if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3424 			/*
3425 			 * The command should be allowed to retry by returning
3426 			 * TRAN_BUSY to stall the I/O's which come from
3427 			 * scsi_vhci since the device/path is in unstable state
3428 			 * now.
3429 			 */
3430 			return (TRAN_BUSY);
3431 		} else {
3432 			/*
3433 			 * The device is offline, just fail the command by
3434 			 * return TRAN_FATAL_ERROR.
3435 			 */
3436 			return (TRAN_FATAL_ERROR);
3437 		}
3438 	}
3439 	rval = mptsas_accept_pkt(mpt, cmd);
3440 
3441 	return (rval);
3442 }
3443 
3444 static int
3445 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3446 {
3447 	int		rval = TRAN_ACCEPT;
3448 	mptsas_target_t	*ptgt = cmd->cmd_tgt_addr;
3449 
3450 	NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3451 
3452 	ASSERT(mutex_owned(&mpt->m_mutex));
3453 
3454 	if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3455 		rval = mptsas_prepare_pkt(cmd);
3456 		if (rval != TRAN_ACCEPT) {
3457 			cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3458 			return (rval);
3459 		}
3460 	}
3461 
3462 	/*
3463 	 * reset the throttle if we were draining
3464 	 */
3465 	if ((ptgt->m_t_ncmds == 0) &&
3466 	    (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3467 		NDBG23(("reset throttle"));
3468 		ASSERT(ptgt->m_reset_delay == 0);
3469 		mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3470 	}
3471 
3472 	/*
3473 	 * If HBA is being reset, the DevHandles are being re-initialized,
3474 	 * which means that they could be invalid even if the target is still
3475 	 * attached.  Check if being reset and if DevHandle is being
3476 	 * re-initialized.  If this is the case, return BUSY so the I/O can be
3477 	 * retried later.
3478 	 */
3479 	if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3480 		mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3481 		if (cmd->cmd_flags & CFLAG_TXQ) {
3482 			mptsas_doneq_add(mpt, cmd);
3483 			mptsas_doneq_empty(mpt);
3484 			return (rval);
3485 		} else {
3486 			return (TRAN_BUSY);
3487 		}
3488 	}
3489 
3490 	/*
3491 	 * If device handle has already been invalidated, just
3492 	 * fail the command. In theory, command from scsi_vhci
3493 	 * client is impossible send down command with invalid
3494 	 * devhdl since devhdl is set after path offline, target
3495 	 * driver is not suppose to select a offlined path.
3496 	 */
3497 	if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3498 		NDBG3(("rejecting command, it might because invalid devhdl "
3499 		    "request."));
3500 		mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3501 		if (cmd->cmd_flags & CFLAG_TXQ) {
3502 			mptsas_doneq_add(mpt, cmd);
3503 			mptsas_doneq_empty(mpt);
3504 			return (rval);
3505 		} else {
3506 			return (TRAN_FATAL_ERROR);
3507 		}
3508 	}
3509 	/*
3510 	 * The first case is the normal case.  mpt gets a command from the
3511 	 * target driver and starts it.
3512 	 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3513 	 * commands is m_max_requests - 2.
3514 	 */
3515 	if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3516 	    (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3517 	    (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3518 	    (ptgt->m_reset_delay == 0) &&
3519 	    (ptgt->m_t_nwait == 0) &&
3520 	    ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3521 		if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3522 			(void) mptsas_start_cmd(mpt, cmd);
3523 		} else {
3524 			mptsas_waitq_add(mpt, cmd);
3525 		}
3526 	} else {
3527 		/*
3528 		 * Add this pkt to the work queue
3529 		 */
3530 		mptsas_waitq_add(mpt, cmd);
3531 
3532 		if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3533 			(void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3534 
3535 			/*
3536 			 * Only flush the doneq if this is not a TM
3537 			 * cmd.  For TM cmds the flushing of the
3538 			 * doneq will be done in those routines.
3539 			 */
3540 			if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3541 				mptsas_doneq_empty(mpt);
3542 			}
3543 		}
3544 	}
3545 	return (rval);
3546 }
3547 
3548 int
3549 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3550 {
3551 	mptsas_slots_t *slots = mpt->m_active;
3552 	uint_t slot, start_rotor;
3553 	mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3554 
3555 	ASSERT(MUTEX_HELD(&mpt->m_mutex));
3556 
3557 	/*
3558 	 * Account for reserved TM request slot and reserved SMID of 0.
3559 	 */
3560 	ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2));
3561 
3562 	/*
3563 	 * Find the next available slot, beginning at m_rotor.  If no slot is
3564 	 * available, we'll return FALSE to indicate that.  This mechanism
3565 	 * considers only the normal slots, not the reserved slot 0 nor the
3566 	 * task management slot m_n_normal + 1.  The rotor is left to point to
3567 	 * the normal slot after the one we select, unless we select the last
3568 	 * normal slot in which case it returns to slot 1.
3569 	 */
3570 	start_rotor = slots->m_rotor;
3571 	do {
3572 		slot = slots->m_rotor++;
3573 		if (slots->m_rotor > slots->m_n_normal)
3574 			slots->m_rotor = 1;
3575 
3576 		if (slots->m_rotor == start_rotor)
3577 			break;
3578 	} while (slots->m_slot[slot] != NULL);
3579 
3580 	if (slots->m_slot[slot] != NULL)
3581 		return (FALSE);
3582 
3583 	ASSERT(slot != 0 && slot <= slots->m_n_normal);
3584 
3585 	cmd->cmd_slot = slot;
3586 	slots->m_slot[slot] = cmd;
3587 	mpt->m_ncmds++;
3588 
3589 	/*
3590 	 * only increment per target ncmds if this is not a
3591 	 * command that has no target associated with it (i.e. a
3592 	 * event acknoledgment)
3593 	 */
3594 	if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3595 		/*
3596 		 * Expiration time is set in mptsas_start_cmd
3597 		 */
3598 		ptgt->m_t_ncmds++;
3599 		cmd->cmd_active_expiration = 0;
3600 	} else {
3601 		/*
3602 		 * Initialize expiration time for passthrough commands,
3603 		 */
3604 		cmd->cmd_active_expiration = gethrtime() +
3605 		    (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC;
3606 	}
3607 	return (TRUE);
3608 }
3609 
3610 /*
3611  * prepare the pkt:
3612  * the pkt may have been resubmitted or just reused so
3613  * initialize some fields and do some checks.
3614  */
3615 static int
3616 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3617 {
3618 	struct scsi_pkt	*pkt = CMD2PKT(cmd);
3619 
3620 	NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3621 
3622 	/*
3623 	 * Reinitialize some fields that need it; the packet may
3624 	 * have been resubmitted
3625 	 */
3626 	pkt->pkt_reason = CMD_CMPLT;
3627 	pkt->pkt_state = 0;
3628 	pkt->pkt_statistics = 0;
3629 	pkt->pkt_resid = 0;
3630 	cmd->cmd_age = 0;
3631 	cmd->cmd_pkt_flags = pkt->pkt_flags;
3632 
3633 	/*
3634 	 * zero status byte.
3635 	 */
3636 	*(pkt->pkt_scbp) = 0;
3637 
3638 	if (cmd->cmd_flags & CFLAG_DMAVALID) {
3639 		pkt->pkt_resid = cmd->cmd_dmacount;
3640 
3641 		/*
3642 		 * consistent packets need to be sync'ed first
3643 		 * (only for data going out)
3644 		 */
3645 		if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3646 		    (cmd->cmd_flags & CFLAG_DMASEND)) {
3647 			(void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3648 			    DDI_DMA_SYNC_FORDEV);
3649 		}
3650 	}
3651 
3652 	cmd->cmd_flags =
3653 	    (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3654 	    CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3655 
3656 	return (TRAN_ACCEPT);
3657 }
3658 
3659 /*
3660  * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3661  *
3662  * One of three possibilities:
3663  *	- allocate scsi_pkt
3664  *	- allocate scsi_pkt and DMA resources
3665  *	- allocate DMA resources to an already-allocated pkt
3666  */
3667 static struct scsi_pkt *
3668 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3669     struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3670     int (*callback)(), caddr_t arg)
3671 {
3672 	mptsas_cmd_t		*cmd, *new_cmd;
3673 	mptsas_t		*mpt = ADDR2MPT(ap);
3674 	uint_t			oldcookiec;
3675 	mptsas_target_t		*ptgt = NULL;
3676 	int			rval;
3677 	mptsas_tgt_private_t	*tgt_private;
3678 	int			kf;
3679 
3680 	kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3681 
3682 	tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3683 	    tran_tgt_private;
3684 	ASSERT(tgt_private != NULL);
3685 	if (tgt_private == NULL) {
3686 		return (NULL);
3687 	}
3688 	ptgt = tgt_private->t_private;
3689 	ASSERT(ptgt != NULL);
3690 	if (ptgt == NULL)
3691 		return (NULL);
3692 	ap->a_target = ptgt->m_devhdl;
3693 	ap->a_lun = tgt_private->t_lun;
3694 
3695 	ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3696 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3697 	statuslen *= 100; tgtlen *= 4;
3698 #endif
3699 	NDBG3(("mptsas_scsi_init_pkt:\n"
3700 	    "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3701 	    ap->a_target, (void *)pkt, (void *)bp,
3702 	    cmdlen, statuslen, tgtlen, flags));
3703 
3704 	/*
3705 	 * Allocate the new packet.
3706 	 */
3707 	if (pkt == NULL) {
3708 		ddi_dma_handle_t	save_dma_handle;
3709 
3710 		cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3711 		if (cmd == NULL)
3712 			return (NULL);
3713 
3714 		save_dma_handle = cmd->cmd_dmahandle;
3715 		bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3716 		cmd->cmd_dmahandle = save_dma_handle;
3717 
3718 		pkt = (void *)((uchar_t *)cmd +
3719 		    sizeof (struct mptsas_cmd));
3720 		pkt->pkt_ha_private = (opaque_t)cmd;
3721 		pkt->pkt_address = *ap;
3722 		pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3723 		pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3724 		pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3725 		cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3726 		cmd->cmd_cdblen = (uchar_t)cmdlen;
3727 		cmd->cmd_scblen = statuslen;
3728 		cmd->cmd_rqslen = SENSE_LENGTH;
3729 		cmd->cmd_tgt_addr = ptgt;
3730 
3731 		if ((cmdlen > sizeof (cmd->cmd_cdb)) ||
3732 		    (tgtlen > PKT_PRIV_LEN) ||
3733 		    (statuslen > EXTCMDS_STATUS_SIZE)) {
3734 			int failure;
3735 
3736 			/*
3737 			 * We are going to allocate external packet space which
3738 			 * might include the sense data buffer for DMA so we
3739 			 * need to increase the reference counter here.  In a
3740 			 * case the HBA is in reset we just simply free the
3741 			 * allocated packet and bail out.
3742 			 */
3743 			mutex_enter(&mpt->m_mutex);
3744 			if (mpt->m_in_reset) {
3745 				mutex_exit(&mpt->m_mutex);
3746 
3747 				cmd->cmd_flags = CFLAG_FREE;
3748 				kmem_cache_free(mpt->m_kmem_cache, cmd);
3749 				return (NULL);
3750 			}
3751 			mpt->m_extreq_sense_refcount++;
3752 			ASSERT(mpt->m_extreq_sense_refcount > 0);
3753 			mutex_exit(&mpt->m_mutex);
3754 
3755 			/*
3756 			 * if extern alloc fails, all will be
3757 			 * deallocated, including cmd
3758 			 */
3759 			failure = mptsas_pkt_alloc_extern(mpt, cmd,
3760 			    cmdlen, tgtlen, statuslen, kf);
3761 
3762 			if (failure != 0 || cmd->cmd_extrqslen == 0) {
3763 				/*
3764 				 * If the external packet space allocation
3765 				 * failed, or we didn't allocate the sense
3766 				 * data buffer for DMA we need to decrease the
3767 				 * reference counter.
3768 				 */
3769 				mutex_enter(&mpt->m_mutex);
3770 				ASSERT(mpt->m_extreq_sense_refcount > 0);
3771 				mpt->m_extreq_sense_refcount--;
3772 				if (mpt->m_extreq_sense_refcount == 0)
3773 					cv_broadcast(
3774 					    &mpt->m_extreq_sense_refcount_cv);
3775 				mutex_exit(&mpt->m_mutex);
3776 
3777 				if (failure != 0) {
3778 					/*
3779 					 * if extern allocation fails, it will
3780 					 * deallocate the new pkt as well
3781 					 */
3782 					return (NULL);
3783 				}
3784 			}
3785 		}
3786 		new_cmd = cmd;
3787 
3788 	} else {
3789 		cmd = PKT2CMD(pkt);
3790 		new_cmd = NULL;
3791 	}
3792 
3793 
3794 	/* grab cmd->cmd_cookiec here as oldcookiec */
3795 
3796 	oldcookiec = cmd->cmd_cookiec;
3797 
3798 	/*
3799 	 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3800 	 * greater than 0 and we'll need to grab the next dma window
3801 	 */
3802 	/*
3803 	 * SLM-not doing extra command frame right now; may add later
3804 	 */
3805 
3806 	if (cmd->cmd_nwin > 0) {
3807 
3808 		/*
3809 		 * Make sure we havn't gone past the the total number
3810 		 * of windows
3811 		 */
3812 		if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3813 			return (NULL);
3814 		}
3815 		if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3816 		    &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3817 		    &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3818 			return (NULL);
3819 		}
3820 		goto get_dma_cookies;
3821 	}
3822 
3823 
3824 	if (flags & PKT_XARQ) {
3825 		cmd->cmd_flags |= CFLAG_XARQ;
3826 	}
3827 
3828 	/*
3829 	 * DMA resource allocation.  This version assumes your
3830 	 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3831 	 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3832 	 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3833 	 */
3834 	if (bp && (bp->b_bcount != 0) &&
3835 	    (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3836 
3837 		int	cnt, dma_flags;
3838 		mptti_t	*dmap;		/* ptr to the S/G list */
3839 
3840 		/*
3841 		 * Set up DMA memory and position to the next DMA segment.
3842 		 */
3843 		ASSERT(cmd->cmd_dmahandle != NULL);
3844 
3845 		if (bp->b_flags & B_READ) {
3846 			dma_flags = DDI_DMA_READ;
3847 			cmd->cmd_flags &= ~CFLAG_DMASEND;
3848 		} else {
3849 			dma_flags = DDI_DMA_WRITE;
3850 			cmd->cmd_flags |= CFLAG_DMASEND;
3851 		}
3852 		if (flags & PKT_CONSISTENT) {
3853 			cmd->cmd_flags |= CFLAG_CMDIOPB;
3854 			dma_flags |= DDI_DMA_CONSISTENT;
3855 		}
3856 
3857 		if (flags & PKT_DMA_PARTIAL) {
3858 			dma_flags |= DDI_DMA_PARTIAL;
3859 		}
3860 
3861 		/*
3862 		 * workaround for byte hole issue on psycho and
3863 		 * schizo pre 2.1
3864 		 */
3865 		if ((bp->b_flags & B_READ) && ((bp->b_flags &
3866 		    (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3867 		    ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3868 			dma_flags |= DDI_DMA_CONSISTENT;
3869 		}
3870 
3871 		rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3872 		    dma_flags, callback, arg,
3873 		    &cmd->cmd_cookie, &cmd->cmd_cookiec);
3874 		if (rval == DDI_DMA_PARTIAL_MAP) {
3875 			(void) ddi_dma_numwin(cmd->cmd_dmahandle,
3876 			    &cmd->cmd_nwin);
3877 			cmd->cmd_winindex = 0;
3878 			(void) ddi_dma_getwin(cmd->cmd_dmahandle,
3879 			    cmd->cmd_winindex, &cmd->cmd_dma_offset,
3880 			    &cmd->cmd_dma_len, &cmd->cmd_cookie,
3881 			    &cmd->cmd_cookiec);
3882 		} else if (rval && (rval != DDI_DMA_MAPPED)) {
3883 			switch (rval) {
3884 			case DDI_DMA_NORESOURCES:
3885 				bioerror(bp, 0);
3886 				break;
3887 			case DDI_DMA_BADATTR:
3888 			case DDI_DMA_NOMAPPING:
3889 				bioerror(bp, EFAULT);
3890 				break;
3891 			case DDI_DMA_TOOBIG:
3892 			default:
3893 				bioerror(bp, EINVAL);
3894 				break;
3895 			}
3896 			cmd->cmd_flags &= ~CFLAG_DMAVALID;
3897 			if (new_cmd) {
3898 				mptsas_scsi_destroy_pkt(ap, pkt);
3899 			}
3900 			return ((struct scsi_pkt *)NULL);
3901 		}
3902 
3903 get_dma_cookies:
3904 		cmd->cmd_flags |= CFLAG_DMAVALID;
3905 		ASSERT(cmd->cmd_cookiec > 0);
3906 
3907 		if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3908 			mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3909 			    cmd->cmd_cookiec);
3910 			bioerror(bp, EINVAL);
3911 			if (new_cmd) {
3912 				mptsas_scsi_destroy_pkt(ap, pkt);
3913 			}
3914 			return ((struct scsi_pkt *)NULL);
3915 		}
3916 
3917 		/*
3918 		 * Allocate extra SGL buffer if needed.
3919 		 */
3920 		if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3921 		    (cmd->cmd_extra_frames == NULL)) {
3922 			if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3923 			    DDI_FAILURE) {
3924 				mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3925 				    "failed");
3926 				bioerror(bp, ENOMEM);
3927 				if (new_cmd) {
3928 					mptsas_scsi_destroy_pkt(ap, pkt);
3929 				}
3930 				return ((struct scsi_pkt *)NULL);
3931 			}
3932 		}
3933 
3934 		/*
3935 		 * Always use scatter-gather transfer
3936 		 * Use the loop below to store physical addresses of
3937 		 * DMA segments, from the DMA cookies, into your HBA's
3938 		 * scatter-gather list.
3939 		 * We need to ensure we have enough kmem alloc'd
3940 		 * for the sg entries since we are no longer using an
3941 		 * array inside mptsas_cmd_t.
3942 		 *
3943 		 * We check cmd->cmd_cookiec against oldcookiec so
3944 		 * the scatter-gather list is correctly allocated
3945 		 */
3946 
3947 		if (oldcookiec != cmd->cmd_cookiec) {
3948 			if (cmd->cmd_sg != (mptti_t *)NULL) {
3949 				kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3950 				    oldcookiec);
3951 				cmd->cmd_sg = NULL;
3952 			}
3953 		}
3954 
3955 		if (cmd->cmd_sg == (mptti_t *)NULL) {
3956 			cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3957 			    cmd->cmd_cookiec), kf);
3958 
3959 			if (cmd->cmd_sg == (mptti_t *)NULL) {
3960 				mptsas_log(mpt, CE_WARN,
3961 				    "unable to kmem_alloc enough memory "
3962 				    "for scatter/gather list");
3963 		/*
3964 		 * if we have an ENOMEM condition we need to behave
3965 		 * the same way as the rest of this routine
3966 		 */
3967 
3968 				bioerror(bp, ENOMEM);
3969 				if (new_cmd) {
3970 					mptsas_scsi_destroy_pkt(ap, pkt);
3971 				}
3972 				return ((struct scsi_pkt *)NULL);
3973 			}
3974 		}
3975 
3976 		dmap = cmd->cmd_sg;
3977 
3978 		ASSERT(cmd->cmd_cookie.dmac_size != 0);
3979 
3980 		/*
3981 		 * store the first segment into the S/G list
3982 		 */
3983 		dmap->count = cmd->cmd_cookie.dmac_size;
3984 		dmap->addr.address64.Low = (uint32_t)
3985 		    (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3986 		dmap->addr.address64.High = (uint32_t)
3987 		    (cmd->cmd_cookie.dmac_laddress >> 32);
3988 
3989 		/*
3990 		 * dmacount counts the size of the dma for this window
3991 		 * (if partial dma is being used).  totaldmacount
3992 		 * keeps track of the total amount of dma we have
3993 		 * transferred for all the windows (needed to calculate
3994 		 * the resid value below).
3995 		 */
3996 		cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3997 		cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3998 
3999 		/*
4000 		 * We already stored the first DMA scatter gather segment,
4001 		 * start at 1 if we need to store more.
4002 		 */
4003 		for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
4004 			/*
4005 			 * Get next DMA cookie
4006 			 */
4007 			ddi_dma_nextcookie(cmd->cmd_dmahandle,
4008 			    &cmd->cmd_cookie);
4009 			dmap++;
4010 
4011 			cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
4012 			cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
4013 
4014 			/*
4015 			 * store the segment parms into the S/G list
4016 			 */
4017 			dmap->count = cmd->cmd_cookie.dmac_size;
4018 			dmap->addr.address64.Low = (uint32_t)
4019 			    (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
4020 			dmap->addr.address64.High = (uint32_t)
4021 			    (cmd->cmd_cookie.dmac_laddress >> 32);
4022 		}
4023 
4024 		/*
4025 		 * If this was partially allocated we set the resid
4026 		 * the amount of data NOT transferred in this window
4027 		 * If there is only one window, the resid will be 0
4028 		 */
4029 		pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
4030 		NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.",
4031 		    cmd->cmd_dmacount));
4032 	}
4033 	return (pkt);
4034 }
4035 
4036 /*
4037  * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
4038  *
4039  * Notes:
4040  *	- also frees DMA resources if allocated
4041  *	- implicit DMA synchonization
4042  */
4043 static void
4044 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4045 {
4046 	mptsas_cmd_t	*cmd = PKT2CMD(pkt);
4047 	mptsas_t	*mpt = ADDR2MPT(ap);
4048 
4049 	NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
4050 	    ap->a_target, (void *)pkt));
4051 
4052 	if (cmd->cmd_flags & CFLAG_DMAVALID) {
4053 		(void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4054 		cmd->cmd_flags &= ~CFLAG_DMAVALID;
4055 	}
4056 
4057 	if (cmd->cmd_sg) {
4058 		kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
4059 		cmd->cmd_sg = NULL;
4060 	}
4061 
4062 	mptsas_free_extra_sgl_frame(mpt, cmd);
4063 
4064 	if ((cmd->cmd_flags &
4065 	    (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
4066 	    CFLAG_SCBEXTERN)) == 0) {
4067 		cmd->cmd_flags = CFLAG_FREE;
4068 		kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4069 	} else {
4070 		boolean_t extrqslen = cmd->cmd_extrqslen != 0;
4071 
4072 		mptsas_pkt_destroy_extern(mpt, cmd);
4073 
4074 		/*
4075 		 * If the packet had the sense data buffer for DMA allocated we
4076 		 * need to decrease the reference counter.
4077 		 */
4078 		if (extrqslen) {
4079 			mutex_enter(&mpt->m_mutex);
4080 			ASSERT(mpt->m_extreq_sense_refcount > 0);
4081 			mpt->m_extreq_sense_refcount--;
4082 			if (mpt->m_extreq_sense_refcount == 0)
4083 				cv_broadcast(&mpt->m_extreq_sense_refcount_cv);
4084 			mutex_exit(&mpt->m_mutex);
4085 		}
4086 	}
4087 }
4088 
4089 /*
4090  * kmem cache constructor and destructor:
4091  * When constructing, we bzero the cmd and allocate the dma handle
4092  * When destructing, just free the dma handle
4093  */
4094 static int
4095 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
4096 {
4097 	mptsas_cmd_t		*cmd = buf;
4098 	mptsas_t		*mpt  = cdrarg;
4099 	int			(*callback)(caddr_t);
4100 
4101 	callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4102 
4103 	NDBG4(("mptsas_kmem_cache_constructor"));
4104 
4105 	/*
4106 	 * allocate a dma handle
4107 	 */
4108 	if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
4109 	    NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
4110 		cmd->cmd_dmahandle = NULL;
4111 		return (-1);
4112 	}
4113 	return (0);
4114 }
4115 
4116 static void
4117 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
4118 {
4119 #ifndef __lock_lint
4120 	_NOTE(ARGUNUSED(cdrarg))
4121 #endif
4122 	mptsas_cmd_t	*cmd = buf;
4123 
4124 	NDBG4(("mptsas_kmem_cache_destructor"));
4125 
4126 	if (cmd->cmd_dmahandle) {
4127 		ddi_dma_free_handle(&cmd->cmd_dmahandle);
4128 		cmd->cmd_dmahandle = NULL;
4129 	}
4130 }
4131 
4132 static int
4133 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
4134 {
4135 	mptsas_cache_frames_t	*p = buf;
4136 	mptsas_t		*mpt = cdrarg;
4137 	ddi_dma_attr_t		frame_dma_attr;
4138 	size_t			mem_size, alloc_len;
4139 	ddi_dma_cookie_t	cookie;
4140 	uint_t			ncookie;
4141 	int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
4142 	    ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4143 
4144 	frame_dma_attr = mpt->m_msg_dma_attr;
4145 	frame_dma_attr.dma_attr_align = 0x10;
4146 	frame_dma_attr.dma_attr_sgllen = 1;
4147 
4148 	if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
4149 	    &p->m_dma_hdl) != DDI_SUCCESS) {
4150 		mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
4151 		    " extra SGL.");
4152 		return (DDI_FAILURE);
4153 	}
4154 
4155 	mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
4156 
4157 	if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
4158 	    DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
4159 	    &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
4160 		ddi_dma_free_handle(&p->m_dma_hdl);
4161 		p->m_dma_hdl = NULL;
4162 		mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
4163 		    " extra SGL.");
4164 		return (DDI_FAILURE);
4165 	}
4166 
4167 	if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
4168 	    alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
4169 	    &cookie, &ncookie) != DDI_DMA_MAPPED) {
4170 		(void) ddi_dma_mem_free(&p->m_acc_hdl);
4171 		ddi_dma_free_handle(&p->m_dma_hdl);
4172 		p->m_dma_hdl = NULL;
4173 		mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
4174 		    " extra SGL");
4175 		return (DDI_FAILURE);
4176 	}
4177 
4178 	/*
4179 	 * Store the SGL memory address.  This chip uses this
4180 	 * address to dma to and from the driver.  The second
4181 	 * address is the address mpt uses to fill in the SGL.
4182 	 */
4183 	p->m_phys_addr = cookie.dmac_laddress;
4184 
4185 	return (DDI_SUCCESS);
4186 }
4187 
4188 static void
4189 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
4190 {
4191 #ifndef __lock_lint
4192 	_NOTE(ARGUNUSED(cdrarg))
4193 #endif
4194 	mptsas_cache_frames_t	*p = buf;
4195 	if (p->m_dma_hdl != NULL) {
4196 		(void) ddi_dma_unbind_handle(p->m_dma_hdl);
4197 		(void) ddi_dma_mem_free(&p->m_acc_hdl);
4198 		ddi_dma_free_handle(&p->m_dma_hdl);
4199 		p->m_phys_addr = NULL;
4200 		p->m_frames_addr = NULL;
4201 		p->m_dma_hdl = NULL;
4202 		p->m_acc_hdl = NULL;
4203 	}
4204 
4205 }
4206 
4207 /*
4208  * Figure out if we need to use a different method for the request
4209  * sense buffer and allocate from the map if necessary.
4210  */
4211 static boolean_t
4212 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf)
4213 {
4214 	if (senselength > mpt->m_req_sense_size) {
4215 		unsigned long i;
4216 
4217 		/* Sense length is limited to an 8 bit value in MPI Spec. */
4218 		if (senselength > 255)
4219 			senselength = 255;
4220 		cmd->cmd_extrqschunks = (senselength +
4221 		    (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size;
4222 		i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc)
4223 		    (mpt->m_erqsense_map, cmd->cmd_extrqschunks);
4224 
4225 		if (i == 0)
4226 			return (B_FALSE);
4227 
4228 		cmd->cmd_extrqslen = (uint16_t)senselength;
4229 		cmd->cmd_extrqsidx = i - 1;
4230 		cmd->cmd_arq_buf = mpt->m_extreq_sense +
4231 		    (cmd->cmd_extrqsidx * mpt->m_req_sense_size);
4232 	} else {
4233 		cmd->cmd_rqslen = (uchar_t)senselength;
4234 	}
4235 
4236 	return (B_TRUE);
4237 }
4238 
4239 /*
4240  * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
4241  * for non-standard length cdb, pkt_private, status areas
4242  * if allocation fails, then deallocate all external space and the pkt
4243  */
4244 /* ARGSUSED */
4245 static int
4246 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
4247     int cmdlen, int tgtlen, int statuslen, int kf)
4248 {
4249 	caddr_t			cdbp, scbp, tgt;
4250 
4251 	NDBG3(("mptsas_pkt_alloc_extern: "
4252 	    "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
4253 	    (void *)cmd, cmdlen, tgtlen, statuslen, kf));
4254 
4255 	tgt = cdbp = scbp = NULL;
4256 	cmd->cmd_scblen		= statuslen;
4257 	cmd->cmd_privlen	= (uchar_t)tgtlen;
4258 
4259 	if (cmdlen > sizeof (cmd->cmd_cdb)) {
4260 		if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
4261 			goto fail;
4262 		}
4263 		cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
4264 		cmd->cmd_flags |= CFLAG_CDBEXTERN;
4265 	}
4266 	if (tgtlen > PKT_PRIV_LEN) {
4267 		if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
4268 			goto fail;
4269 		}
4270 		cmd->cmd_flags |= CFLAG_PRIVEXTERN;
4271 		cmd->cmd_pkt->pkt_private = tgt;
4272 	}
4273 	if (statuslen > EXTCMDS_STATUS_SIZE) {
4274 		if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
4275 			goto fail;
4276 		}
4277 		cmd->cmd_flags |= CFLAG_SCBEXTERN;
4278 		cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
4279 
4280 		/* allocate sense data buf for DMA */
4281 		if (mptsas_cmdarqsize(mpt, cmd, statuslen -
4282 		    MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata),
4283 		    kf) == B_FALSE)
4284 			goto fail;
4285 	}
4286 	return (0);
4287 fail:
4288 	mptsas_pkt_destroy_extern(mpt, cmd);
4289 	return (1);
4290 }
4291 
4292 /*
4293  * deallocate external pkt space and deallocate the pkt
4294  */
4295 static void
4296 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4297 {
4298 	NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4299 
4300 	if (cmd->cmd_flags & CFLAG_FREE) {
4301 		mptsas_log(mpt, CE_PANIC,
4302 		    "mptsas_pkt_destroy_extern: freeing free packet");
4303 		_NOTE(NOT_REACHED)
4304 		/* NOTREACHED */
4305 	}
4306 	if (cmd->cmd_extrqslen != 0) {
4307 		rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
4308 		    cmd->cmd_extrqsidx + 1);
4309 	}
4310 	if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4311 		kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4312 	}
4313 	if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4314 		kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4315 	}
4316 	if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4317 		kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4318 	}
4319 	cmd->cmd_flags = CFLAG_FREE;
4320 	kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4321 }
4322 
4323 /*
4324  * tran_sync_pkt(9E) - explicit DMA synchronization
4325  */
4326 /*ARGSUSED*/
4327 static void
4328 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4329 {
4330 	mptsas_cmd_t	*cmd = PKT2CMD(pkt);
4331 
4332 	NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4333 	    ap->a_target, (void *)pkt));
4334 
4335 	if (cmd->cmd_dmahandle) {
4336 		(void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4337 		    (cmd->cmd_flags & CFLAG_DMASEND) ?
4338 		    DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4339 	}
4340 }
4341 
4342 /*
4343  * tran_dmafree(9E) - deallocate DMA resources allocated for command
4344  */
4345 /*ARGSUSED*/
4346 static void
4347 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4348 {
4349 	mptsas_cmd_t	*cmd = PKT2CMD(pkt);
4350 	mptsas_t	*mpt = ADDR2MPT(ap);
4351 
4352 	NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4353 	    ap->a_target, (void *)pkt));
4354 
4355 	if (cmd->cmd_flags & CFLAG_DMAVALID) {
4356 		(void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4357 		cmd->cmd_flags &= ~CFLAG_DMAVALID;
4358 	}
4359 
4360 	mptsas_free_extra_sgl_frame(mpt, cmd);
4361 }
4362 
4363 static void
4364 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4365 {
4366 	if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4367 	    (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4368 		(void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4369 		    DDI_DMA_SYNC_FORCPU);
4370 	}
4371 	(*pkt->pkt_comp)(pkt);
4372 }
4373 
4374 static void
4375 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4376     ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags)
4377 {
4378 	pMpi2SGESimple64_t	sge;
4379 	mptti_t			*dmap;
4380 	uint32_t		flags;
4381 
4382 	dmap = cmd->cmd_sg;
4383 
4384 	sge = (pMpi2SGESimple64_t)(&frame->SGL);
4385 	while (cookiec--) {
4386 		ddi_put32(acc_hdl,
4387 		    &sge->Address.Low, dmap->addr.address64.Low);
4388 		ddi_put32(acc_hdl,
4389 		    &sge->Address.High, dmap->addr.address64.High);
4390 		ddi_put32(acc_hdl, &sge->FlagsLength,
4391 		    dmap->count);
4392 		flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4393 		flags |= ((uint32_t)
4394 		    (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4395 		    MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4396 		    MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4397 		    MPI2_SGE_FLAGS_SHIFT);
4398 
4399 		/*
4400 		 * If this is the last cookie, we set the flags
4401 		 * to indicate so
4402 		 */
4403 		if (cookiec == 0) {
4404 			flags |= end_flags;
4405 		}
4406 		if (cmd->cmd_flags & CFLAG_DMASEND) {
4407 			flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4408 			    MPI2_SGE_FLAGS_SHIFT);
4409 		} else {
4410 			flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4411 			    MPI2_SGE_FLAGS_SHIFT);
4412 		}
4413 		ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4414 		dmap++;
4415 		sge++;
4416 	}
4417 }
4418 
4419 static void
4420 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4421     pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4422 {
4423 	pMpi2SGESimple64_t	sge;
4424 	pMpi2SGEChain64_t	sgechain;
4425 	uint64_t		nframe_phys_addr;
4426 	uint_t			cookiec;
4427 	mptti_t			*dmap;
4428 	uint32_t		flags;
4429 
4430 	/*
4431 	 * Save the number of entries in the DMA
4432 	 * Scatter/Gather list
4433 	 */
4434 	cookiec = cmd->cmd_cookiec;
4435 
4436 	/*
4437 	 * Hereby we start to deal with multiple frames.
4438 	 * The process is as follows:
4439 	 * 1. Determine how many frames are needed for SGL element
4440 	 *    storage; Note that all frames are stored in contiguous
4441 	 *    memory space and in 64-bit DMA mode each element is
4442 	 *    3 double-words (12 bytes) long.
4443 	 * 2. Fill up the main frame. We need to do this separately
4444 	 *    since it contains the SCSI IO request header and needs
4445 	 *    dedicated processing. Note that the last 4 double-words
4446 	 *    of the SCSI IO header is for SGL element storage
4447 	 *    (MPI2_SGE_IO_UNION).
4448 	 * 3. Fill the chain element in the main frame, so the DMA
4449 	 *    engine can use the following frames.
4450 	 * 4. Enter a loop to fill the remaining frames. Note that the
4451 	 *    last frame contains no chain element.  The remaining
4452 	 *    frames go into the mpt SGL buffer allocated on the fly,
4453 	 *    not immediately following the main message frame, as in
4454 	 *    Gen1.
4455 	 * Some restrictions:
4456 	 * 1. For 64-bit DMA, the simple element and chain element
4457 	 *    are both of 3 double-words (12 bytes) in size, even
4458 	 *    though all frames are stored in the first 4G of mem
4459 	 *    range and the higher 32-bits of the address are always 0.
4460 	 * 2. On some controllers (like the 1064/1068), a frame can
4461 	 *    hold SGL elements with the last 1 or 2 double-words
4462 	 *    (4 or 8 bytes) un-used. On these controllers, we should
4463 	 *    recognize that there's not enough room for another SGL
4464 	 *    element and move the sge pointer to the next frame.
4465 	 */
4466 	int			i, j, k, l, frames, sgemax;
4467 	int			temp;
4468 	uint8_t			chainflags;
4469 	uint16_t		chainlength;
4470 	mptsas_cache_frames_t	*p;
4471 
4472 	/*
4473 	 * Sgemax is the number of SGE's that will fit
4474 	 * each extra frame and frames is total
4475 	 * number of frames we'll need.  1 sge entry per
4476 	 * frame is reseverd for the chain element thus the -1 below.
4477 	 */
4478 	sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4479 	    - 1);
4480 	temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4481 
4482 	/*
4483 	 * A little check to see if we need to round up the number
4484 	 * of frames we need
4485 	 */
4486 	if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4487 	    sgemax) > 1) {
4488 		frames = (temp + 1);
4489 	} else {
4490 		frames = temp;
4491 	}
4492 	dmap = cmd->cmd_sg;
4493 	sge = (pMpi2SGESimple64_t)(&frame->SGL);
4494 
4495 	/*
4496 	 * First fill in the main frame
4497 	 */
4498 	j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4499 	mptsas_sge_mainframe(cmd, frame, acc_hdl, j,
4500 	    ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4501 	    MPI2_SGE_FLAGS_SHIFT));
4502 	dmap += j;
4503 	sge += j;
4504 	j++;
4505 
4506 	/*
4507 	 * Fill in the chain element in the main frame.
4508 	 * About calculation on ChainOffset:
4509 	 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4510 	 *    in the end reserved for SGL element storage
4511 	 *    (MPI2_SGE_IO_UNION); we should count it in our
4512 	 *    calculation.  See its definition in the header file.
4513 	 * 2. Constant j is the counter of the current SGL element
4514 	 *    that will be processed, and (j - 1) is the number of
4515 	 *    SGL elements that have been processed (stored in the
4516 	 *    main frame).
4517 	 * 3. ChainOffset value should be in units of double-words (4
4518 	 *    bytes) so the last value should be divided by 4.
4519 	 */
4520 	ddi_put8(acc_hdl, &frame->ChainOffset,
4521 	    (sizeof (MPI2_SCSI_IO_REQUEST) -
4522 	    sizeof (MPI2_SGE_IO_UNION) +
4523 	    (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4524 	sgechain = (pMpi2SGEChain64_t)sge;
4525 	chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4526 	    MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4527 	    MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4528 	ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4529 
4530 	/*
4531 	 * The size of the next frame is the accurate size of space
4532 	 * (in bytes) used to store the SGL elements. j is the counter
4533 	 * of SGL elements. (j - 1) is the number of SGL elements that
4534 	 * have been processed (stored in frames).
4535 	 */
4536 	if (frames >= 2) {
4537 		ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64));
4538 		chainlength = mpt->m_req_frame_size /
4539 		    sizeof (MPI2_SGE_SIMPLE64) *
4540 		    sizeof (MPI2_SGE_SIMPLE64);
4541 	} else {
4542 		chainlength = ((cookiec - (j - 1)) *
4543 		    sizeof (MPI2_SGE_SIMPLE64));
4544 	}
4545 
4546 	p = cmd->cmd_extra_frames;
4547 
4548 	ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4549 	ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr);
4550 	ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32);
4551 
4552 	/*
4553 	 * If there are more than 2 frames left we have to
4554 	 * fill in the next chain offset to the location of
4555 	 * the chain element in the next frame.
4556 	 * sgemax is the number of simple elements in an extra
4557 	 * frame. Note that the value NextChainOffset should be
4558 	 * in double-words (4 bytes).
4559 	 */
4560 	if (frames >= 2) {
4561 		ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4562 		    (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4563 	} else {
4564 		ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4565 	}
4566 
4567 	/*
4568 	 * Jump to next frame;
4569 	 * Starting here, chain buffers go into the per command SGL.
4570 	 * This buffer is allocated when chain buffers are needed.
4571 	 */
4572 	sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4573 	i = cookiec;
4574 
4575 	/*
4576 	 * Start filling in frames with SGE's.  If we
4577 	 * reach the end of frame and still have SGE's
4578 	 * to fill we need to add a chain element and
4579 	 * use another frame.  j will be our counter
4580 	 * for what cookie we are at and i will be
4581 	 * the total cookiec. k is the current frame
4582 	 */
4583 	for (k = 1; k <= frames; k++) {
4584 		for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4585 
4586 			/*
4587 			 * If we have reached the end of frame
4588 			 * and we have more SGE's to fill in
4589 			 * we have to fill the final entry
4590 			 * with a chain element and then
4591 			 * continue to the next frame
4592 			 */
4593 			if ((l == (sgemax + 1)) && (k != frames)) {
4594 				sgechain = (pMpi2SGEChain64_t)sge;
4595 				j--;
4596 				chainflags = (
4597 				    MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4598 				    MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4599 				    MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4600 				ddi_put8(p->m_acc_hdl,
4601 				    &sgechain->Flags, chainflags);
4602 				/*
4603 				 * k is the frame counter and (k + 1)
4604 				 * is the number of the next frame.
4605 				 * Note that frames are in contiguous
4606 				 * memory space.
4607 				 */
4608 				nframe_phys_addr = p->m_phys_addr +
4609 				    (mpt->m_req_frame_size * k);
4610 				ddi_put32(p->m_acc_hdl,
4611 				    &sgechain->Address.Low,
4612 				    nframe_phys_addr);
4613 				ddi_put32(p->m_acc_hdl,
4614 				    &sgechain->Address.High,
4615 				    nframe_phys_addr >> 32);
4616 
4617 				/*
4618 				 * If there are more than 2 frames left
4619 				 * we have to next chain offset to
4620 				 * the location of the chain element
4621 				 * in the next frame and fill in the
4622 				 * length of the next chain
4623 				 */
4624 				if ((frames - k) >= 2) {
4625 					ddi_put8(p->m_acc_hdl,
4626 					    &sgechain->NextChainOffset,
4627 					    (sgemax *
4628 					    sizeof (MPI2_SGE_SIMPLE64))
4629 					    >> 2);
4630 					ddi_put16(p->m_acc_hdl,
4631 					    &sgechain->Length,
4632 					    mpt->m_req_frame_size /
4633 					    sizeof (MPI2_SGE_SIMPLE64) *
4634 					    sizeof (MPI2_SGE_SIMPLE64));
4635 				} else {
4636 					/*
4637 					 * This is the last frame. Set
4638 					 * the NextChainOffset to 0 and
4639 					 * Length is the total size of
4640 					 * all remaining simple elements
4641 					 */
4642 					ddi_put8(p->m_acc_hdl,
4643 					    &sgechain->NextChainOffset,
4644 					    0);
4645 					ddi_put16(p->m_acc_hdl,
4646 					    &sgechain->Length,
4647 					    (cookiec - j) *
4648 					    sizeof (MPI2_SGE_SIMPLE64));
4649 				}
4650 
4651 				/* Jump to the next frame */
4652 				sge = (pMpi2SGESimple64_t)
4653 				    ((char *)p->m_frames_addr +
4654 				    (int)mpt->m_req_frame_size * k);
4655 
4656 				continue;
4657 			}
4658 
4659 			ddi_put32(p->m_acc_hdl,
4660 			    &sge->Address.Low,
4661 			    dmap->addr.address64.Low);
4662 			ddi_put32(p->m_acc_hdl,
4663 			    &sge->Address.High,
4664 			    dmap->addr.address64.High);
4665 			ddi_put32(p->m_acc_hdl,
4666 			    &sge->FlagsLength, dmap->count);
4667 			flags = ddi_get32(p->m_acc_hdl,
4668 			    &sge->FlagsLength);
4669 			flags |= ((uint32_t)(
4670 			    MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4671 			    MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4672 			    MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4673 			    MPI2_SGE_FLAGS_SHIFT);
4674 
4675 			/*
4676 			 * If we are at the end of the frame and
4677 			 * there is another frame to fill in
4678 			 * we set the last simple element as last
4679 			 * element
4680 			 */
4681 			if ((l == sgemax) && (k != frames)) {
4682 				flags |= ((uint32_t)
4683 				    (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4684 				    MPI2_SGE_FLAGS_SHIFT);
4685 			}
4686 
4687 			/*
4688 			 * If this is the final cookie we
4689 			 * indicate it by setting the flags
4690 			 */
4691 			if (j == i) {
4692 				flags |= ((uint32_t)
4693 				    (MPI2_SGE_FLAGS_LAST_ELEMENT |
4694 				    MPI2_SGE_FLAGS_END_OF_BUFFER |
4695 				    MPI2_SGE_FLAGS_END_OF_LIST) <<
4696 				    MPI2_SGE_FLAGS_SHIFT);
4697 			}
4698 			if (cmd->cmd_flags & CFLAG_DMASEND) {
4699 				flags |=
4700 				    (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4701 				    MPI2_SGE_FLAGS_SHIFT);
4702 			} else {
4703 				flags |=
4704 				    (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4705 				    MPI2_SGE_FLAGS_SHIFT);
4706 			}
4707 			ddi_put32(p->m_acc_hdl,
4708 			    &sge->FlagsLength, flags);
4709 			dmap++;
4710 			sge++;
4711 		}
4712 	}
4713 
4714 	/*
4715 	 * Sync DMA with the chain buffers that were just created
4716 	 */
4717 	(void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4718 }
4719 
4720 static void
4721 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4722     ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag)
4723 {
4724 	pMpi2IeeeSgeSimple64_t	ieeesge;
4725 	mptti_t			*dmap;
4726 	uint8_t			flags;
4727 
4728 	dmap = cmd->cmd_sg;
4729 
4730 	NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec,
4731 	    cmd->cmd_flags & CFLAG_DMASEND?"Out":"In"));
4732 
4733 	ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4734 	while (cookiec--) {
4735 		ddi_put32(acc_hdl,
4736 		    &ieeesge->Address.Low, dmap->addr.address64.Low);
4737 		ddi_put32(acc_hdl,
4738 		    &ieeesge->Address.High, dmap->addr.address64.High);
4739 		ddi_put32(acc_hdl, &ieeesge->Length,
4740 		    dmap->count);
4741 		NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count));
4742 		flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4743 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4744 
4745 		/*
4746 		 * If this is the last cookie, we set the flags
4747 		 * to indicate so
4748 		 */
4749 		if (cookiec == 0) {
4750 			flags |= end_flag;
4751 		}
4752 
4753 		ddi_put8(acc_hdl, &ieeesge->Flags, flags);
4754 		dmap++;
4755 		ieeesge++;
4756 	}
4757 }
4758 
4759 static void
4760 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4761     pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4762 {
4763 	pMpi2IeeeSgeSimple64_t	ieeesge;
4764 	pMpi25IeeeSgeChain64_t	ieeesgechain;
4765 	uint64_t		nframe_phys_addr;
4766 	uint_t			cookiec;
4767 	mptti_t			*dmap;
4768 	uint8_t			flags;
4769 
4770 	/*
4771 	 * Save the number of entries in the DMA
4772 	 * Scatter/Gather list
4773 	 */
4774 	cookiec = cmd->cmd_cookiec;
4775 
4776 	NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec));
4777 
4778 	/*
4779 	 * Hereby we start to deal with multiple frames.
4780 	 * The process is as follows:
4781 	 * 1. Determine how many frames are needed for SGL element
4782 	 *    storage; Note that all frames are stored in contiguous
4783 	 *    memory space and in 64-bit DMA mode each element is
4784 	 *    4 double-words (16 bytes) long.
4785 	 * 2. Fill up the main frame. We need to do this separately
4786 	 *    since it contains the SCSI IO request header and needs
4787 	 *    dedicated processing. Note that the last 4 double-words
4788 	 *    of the SCSI IO header is for SGL element storage
4789 	 *    (MPI2_SGE_IO_UNION).
4790 	 * 3. Fill the chain element in the main frame, so the DMA
4791 	 *    engine can use the following frames.
4792 	 * 4. Enter a loop to fill the remaining frames. Note that the
4793 	 *    last frame contains no chain element.  The remaining
4794 	 *    frames go into the mpt SGL buffer allocated on the fly,
4795 	 *    not immediately following the main message frame, as in
4796 	 *    Gen1.
4797 	 * Restrictions:
4798 	 *    For 64-bit DMA, the simple element and chain element
4799 	 *    are both of 4 double-words (16 bytes) in size, even
4800 	 *    though all frames are stored in the first 4G of mem
4801 	 *    range and the higher 32-bits of the address are always 0.
4802 	 */
4803 	int			i, j, k, l, frames, sgemax;
4804 	int			temp;
4805 	uint8_t			chainflags;
4806 	uint32_t		chainlength;
4807 	mptsas_cache_frames_t	*p;
4808 
4809 	/*
4810 	 * Sgemax is the number of SGE's that will fit
4811 	 * each extra frame and frames is total
4812 	 * number of frames we'll need.  1 sge entry per
4813 	 * frame is reseverd for the chain element thus the -1 below.
4814 	 */
4815 	sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64))
4816 	    - 1);
4817 	temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4818 
4819 	/*
4820 	 * A little check to see if we need to round up the number
4821 	 * of frames we need
4822 	 */
4823 	if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4824 	    sgemax) > 1) {
4825 		frames = (temp + 1);
4826 	} else {
4827 		frames = temp;
4828 	}
4829 	NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames));
4830 	dmap = cmd->cmd_sg;
4831 	ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4832 
4833 	/*
4834 	 * First fill in the main frame
4835 	 */
4836 	j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4837 	mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0);
4838 	dmap += j;
4839 	ieeesge += j;
4840 	j++;
4841 
4842 	/*
4843 	 * Fill in the chain element in the main frame.
4844 	 * About calculation on ChainOffset:
4845 	 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4846 	 *    in the end reserved for SGL element storage
4847 	 *    (MPI2_SGE_IO_UNION); we should count it in our
4848 	 *    calculation.  See its definition in the header file.
4849 	 * 2. Constant j is the counter of the current SGL element
4850 	 *    that will be processed, and (j - 1) is the number of
4851 	 *    SGL elements that have been processed (stored in the
4852 	 *    main frame).
4853 	 * 3. ChainOffset value should be in units of quad-words (16
4854 	 *    bytes) so the last value should be divided by 16.
4855 	 */
4856 	ddi_put8(acc_hdl, &frame->ChainOffset,
4857 	    (sizeof (MPI2_SCSI_IO_REQUEST) -
4858 	    sizeof (MPI2_SGE_IO_UNION) +
4859 	    (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4860 	ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4861 	chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4862 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4863 	ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags);
4864 
4865 	/*
4866 	 * The size of the next frame is the accurate size of space
4867 	 * (in bytes) used to store the SGL elements. j is the counter
4868 	 * of SGL elements. (j - 1) is the number of SGL elements that
4869 	 * have been processed (stored in frames).
4870 	 */
4871 	if (frames >= 2) {
4872 		ASSERT(mpt->m_req_frame_size >=
4873 		    sizeof (MPI2_IEEE_SGE_SIMPLE64));
4874 		chainlength = mpt->m_req_frame_size /
4875 		    sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4876 		    sizeof (MPI2_IEEE_SGE_SIMPLE64);
4877 	} else {
4878 		chainlength = ((cookiec - (j - 1)) *
4879 		    sizeof (MPI2_IEEE_SGE_SIMPLE64));
4880 	}
4881 
4882 	p = cmd->cmd_extra_frames;
4883 
4884 	ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength);
4885 	ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr);
4886 	ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32);
4887 
4888 	/*
4889 	 * If there are more than 2 frames left we have to
4890 	 * fill in the next chain offset to the location of
4891 	 * the chain element in the next frame.
4892 	 * sgemax is the number of simple elements in an extra
4893 	 * frame. Note that the value NextChainOffset should be
4894 	 * in double-words (4 bytes).
4895 	 */
4896 	if (frames >= 2) {
4897 		ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset,
4898 		    (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4899 	} else {
4900 		ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0);
4901 	}
4902 
4903 	/*
4904 	 * Jump to next frame;
4905 	 * Starting here, chain buffers go into the per command SGL.
4906 	 * This buffer is allocated when chain buffers are needed.
4907 	 */
4908 	ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr;
4909 	i = cookiec;
4910 
4911 	/*
4912 	 * Start filling in frames with SGE's.  If we
4913 	 * reach the end of frame and still have SGE's
4914 	 * to fill we need to add a chain element and
4915 	 * use another frame.  j will be our counter
4916 	 * for what cookie we are at and i will be
4917 	 * the total cookiec. k is the current frame
4918 	 */
4919 	for (k = 1; k <= frames; k++) {
4920 		for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4921 
4922 			/*
4923 			 * If we have reached the end of frame
4924 			 * and we have more SGE's to fill in
4925 			 * we have to fill the final entry
4926 			 * with a chain element and then
4927 			 * continue to the next frame
4928 			 */
4929 			if ((l == (sgemax + 1)) && (k != frames)) {
4930 				ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4931 				j--;
4932 				chainflags =
4933 				    MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4934 				    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
4935 				ddi_put8(p->m_acc_hdl,
4936 				    &ieeesgechain->Flags, chainflags);
4937 				/*
4938 				 * k is the frame counter and (k + 1)
4939 				 * is the number of the next frame.
4940 				 * Note that frames are in contiguous
4941 				 * memory space.
4942 				 */
4943 				nframe_phys_addr = p->m_phys_addr +
4944 				    (mpt->m_req_frame_size * k);
4945 				ddi_put32(p->m_acc_hdl,
4946 				    &ieeesgechain->Address.Low,
4947 				    nframe_phys_addr);
4948 				ddi_put32(p->m_acc_hdl,
4949 				    &ieeesgechain->Address.High,
4950 				    nframe_phys_addr >> 32);
4951 
4952 				/*
4953 				 * If there are more than 2 frames left
4954 				 * we have to next chain offset to
4955 				 * the location of the chain element
4956 				 * in the next frame and fill in the
4957 				 * length of the next chain
4958 				 */
4959 				if ((frames - k) >= 2) {
4960 					ddi_put8(p->m_acc_hdl,
4961 					    &ieeesgechain->NextChainOffset,
4962 					    (sgemax *
4963 					    sizeof (MPI2_IEEE_SGE_SIMPLE64))
4964 					    >> 4);
4965 					ASSERT(mpt->m_req_frame_size >=
4966 					    sizeof (MPI2_IEEE_SGE_SIMPLE64));
4967 					ddi_put32(p->m_acc_hdl,
4968 					    &ieeesgechain->Length,
4969 					    mpt->m_req_frame_size /
4970 					    sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4971 					    sizeof (MPI2_IEEE_SGE_SIMPLE64));
4972 				} else {
4973 					/*
4974 					 * This is the last frame. Set
4975 					 * the NextChainOffset to 0 and
4976 					 * Length is the total size of
4977 					 * all remaining simple elements
4978 					 */
4979 					ddi_put8(p->m_acc_hdl,
4980 					    &ieeesgechain->NextChainOffset,
4981 					    0);
4982 					ddi_put32(p->m_acc_hdl,
4983 					    &ieeesgechain->Length,
4984 					    (cookiec - j) *
4985 					    sizeof (MPI2_IEEE_SGE_SIMPLE64));
4986 				}
4987 
4988 				/* Jump to the next frame */
4989 				ieeesge = (pMpi2IeeeSgeSimple64_t)
4990 				    ((char *)p->m_frames_addr +
4991 				    (int)mpt->m_req_frame_size * k);
4992 
4993 				continue;
4994 			}
4995 
4996 			ddi_put32(p->m_acc_hdl,
4997 			    &ieeesge->Address.Low,
4998 			    dmap->addr.address64.Low);
4999 			ddi_put32(p->m_acc_hdl,
5000 			    &ieeesge->Address.High,
5001 			    dmap->addr.address64.High);
5002 			ddi_put32(p->m_acc_hdl,
5003 			    &ieeesge->Length, dmap->count);
5004 			flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
5005 			    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
5006 
5007 			/*
5008 			 * If we are at the end of the frame and
5009 			 * there is another frame to fill in
5010 			 * do we need to do anything?
5011 			 * if ((l == sgemax) && (k != frames)) {
5012 			 * }
5013 			 */
5014 
5015 			/*
5016 			 * If this is the final cookie set end of list.
5017 			 */
5018 			if (j == i) {
5019 				flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
5020 			}
5021 
5022 			ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags);
5023 			dmap++;
5024 			ieeesge++;
5025 		}
5026 	}
5027 
5028 	/*
5029 	 * Sync DMA with the chain buffers that were just created
5030 	 */
5031 	(void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
5032 }
5033 
5034 static void
5035 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
5036     pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
5037 {
5038 	ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
5039 
5040 	NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec));
5041 
5042 	/*
5043 	 * Set read/write bit in control.
5044 	 */
5045 	if (cmd->cmd_flags & CFLAG_DMASEND) {
5046 		*control |= MPI2_SCSIIO_CONTROL_WRITE;
5047 	} else {
5048 		*control |= MPI2_SCSIIO_CONTROL_READ;
5049 	}
5050 
5051 	ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
5052 
5053 	/*
5054 	 * We have 4 cases here.  First where we can fit all the
5055 	 * SG elements into the main frame, and the case
5056 	 * where we can't. The SG element is also different when using
5057 	 * MPI2.5 interface.
5058 	 * If we have more cookies than we can attach to a frame
5059 	 * we will need to use a chain element to point
5060 	 * a location of memory where the rest of the S/G
5061 	 * elements reside.
5062 	 */
5063 	if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
5064 		if (mpt->m_MPI25) {
5065 			mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl,
5066 			    cmd->cmd_cookiec,
5067 			    MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
5068 		} else {
5069 			mptsas_sge_mainframe(cmd, frame, acc_hdl,
5070 			    cmd->cmd_cookiec,
5071 			    ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
5072 			    | MPI2_SGE_FLAGS_END_OF_BUFFER
5073 			    | MPI2_SGE_FLAGS_END_OF_LIST) <<
5074 			    MPI2_SGE_FLAGS_SHIFT));
5075 		}
5076 	} else {
5077 		if (mpt->m_MPI25) {
5078 			mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl);
5079 		} else {
5080 			mptsas_sge_chain(mpt, cmd, frame, acc_hdl);
5081 		}
5082 	}
5083 }
5084 
5085 /*
5086  * Interrupt handling
5087  * Utility routine.  Poll for status of a command sent to HBA
5088  * without interrupts (a FLAG_NOINTR command).
5089  */
5090 int
5091 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
5092 {
5093 	int	rval = TRUE;
5094 
5095 	NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
5096 
5097 	if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
5098 		mptsas_restart_hba(mpt);
5099 	}
5100 
5101 	/*
5102 	 * Wait, using drv_usecwait(), long enough for the command to
5103 	 * reasonably return from the target if the target isn't
5104 	 * "dead".  A polled command may well be sent from scsi_poll, and
5105 	 * there are retries built in to scsi_poll if the transport
5106 	 * accepted the packet (TRAN_ACCEPT).  scsi_poll waits 1 second
5107 	 * and retries the transport up to scsi_poll_busycnt times
5108 	 * (currently 60) if
5109 	 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
5110 	 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
5111 	 *
5112 	 * limit the waiting to avoid a hang in the event that the
5113 	 * cmd never gets started but we are still receiving interrupts
5114 	 */
5115 	while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
5116 		if (mptsas_wait_intr(mpt, polltime) == FALSE) {
5117 			NDBG5(("mptsas_poll: command incomplete"));
5118 			rval = FALSE;
5119 			break;
5120 		}
5121 	}
5122 
5123 	if (rval == FALSE) {
5124 
5125 		/*
5126 		 * this isn't supposed to happen, the hba must be wedged
5127 		 * Mark this cmd as a timeout.
5128 		 */
5129 		mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
5130 		    (STAT_TIMEOUT|STAT_ABORTED));
5131 
5132 		if (poll_cmd->cmd_queued == FALSE) {
5133 
5134 			NDBG5(("mptsas_poll: not on waitq"));
5135 
5136 			poll_cmd->cmd_pkt->pkt_state |=
5137 			    (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
5138 		} else {
5139 
5140 			/* find and remove it from the waitq */
5141 			NDBG5(("mptsas_poll: delete from waitq"));
5142 			mptsas_waitq_delete(mpt, poll_cmd);
5143 		}
5144 
5145 	}
5146 	mptsas_fma_check(mpt, poll_cmd);
5147 	NDBG5(("mptsas_poll: done"));
5148 	return (rval);
5149 }
5150 
5151 /*
5152  * Used for polling cmds and TM function
5153  */
5154 static int
5155 mptsas_wait_intr(mptsas_t *mpt, int polltime)
5156 {
5157 	int				cnt;
5158 	pMpi2ReplyDescriptorsUnion_t	reply_desc_union;
5159 	uint32_t			int_mask;
5160 
5161 	NDBG5(("mptsas_wait_intr"));
5162 
5163 	mpt->m_polled_intr = 1;
5164 
5165 	/*
5166 	 * Get the current interrupt mask and disable interrupts.  When
5167 	 * re-enabling ints, set mask to saved value.
5168 	 */
5169 	int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
5170 	MPTSAS_DISABLE_INTR(mpt);
5171 
5172 	/*
5173 	 * Keep polling for at least (polltime * 1000) seconds
5174 	 */
5175 	for (cnt = 0; cnt < polltime; cnt++) {
5176 		(void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5177 		    DDI_DMA_SYNC_FORCPU);
5178 
5179 		reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5180 		    MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5181 
5182 		if (ddi_get32(mpt->m_acc_post_queue_hdl,
5183 		    &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5184 		    ddi_get32(mpt->m_acc_post_queue_hdl,
5185 		    &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5186 			drv_usecwait(1000);
5187 			continue;
5188 		}
5189 
5190 		/*
5191 		 * The reply is valid, process it according to its
5192 		 * type.
5193 		 */
5194 		mptsas_process_intr(mpt, reply_desc_union);
5195 
5196 		if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5197 			mpt->m_post_index = 0;
5198 		}
5199 
5200 		/*
5201 		 * Update the global reply index
5202 		 */
5203 		ddi_put32(mpt->m_datap,
5204 		    &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5205 		mpt->m_polled_intr = 0;
5206 
5207 		/*
5208 		 * Re-enable interrupts and quit.
5209 		 */
5210 		ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
5211 		    int_mask);
5212 		return (TRUE);
5213 
5214 	}
5215 
5216 	/*
5217 	 * Clear polling flag, re-enable interrupts and quit.
5218 	 */
5219 	mpt->m_polled_intr = 0;
5220 	ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
5221 	return (FALSE);
5222 }
5223 
5224 static void
5225 mptsas_handle_scsi_io_success(mptsas_t *mpt,
5226     pMpi2ReplyDescriptorsUnion_t reply_desc)
5227 {
5228 	pMpi2SCSIIOSuccessReplyDescriptor_t	scsi_io_success;
5229 	uint16_t				SMID;
5230 	mptsas_slots_t				*slots = mpt->m_active;
5231 	mptsas_cmd_t				*cmd = NULL;
5232 	struct scsi_pkt				*pkt;
5233 
5234 	ASSERT(mutex_owned(&mpt->m_mutex));
5235 
5236 	scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
5237 	SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
5238 
5239 	/*
5240 	 * This is a success reply so just complete the IO.  First, do a sanity
5241 	 * check on the SMID.  The final slot is used for TM requests, which
5242 	 * would not come into this reply handler.
5243 	 */
5244 	if ((SMID == 0) || (SMID > slots->m_n_normal)) {
5245 		mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
5246 		    SMID);
5247 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5248 		return;
5249 	}
5250 
5251 	cmd = slots->m_slot[SMID];
5252 
5253 	/*
5254 	 * print warning and return if the slot is empty
5255 	 */
5256 	if (cmd == NULL) {
5257 		mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
5258 		    "in slot %d", SMID);
5259 		return;
5260 	}
5261 
5262 	pkt = CMD2PKT(cmd);
5263 	pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
5264 	    STATE_GOT_STATUS);
5265 	if (cmd->cmd_flags & CFLAG_DMAVALID) {
5266 		pkt->pkt_state |= STATE_XFERRED_DATA;
5267 	}
5268 	pkt->pkt_resid = 0;
5269 
5270 	if (cmd->cmd_flags & CFLAG_PASSTHRU) {
5271 		cmd->cmd_flags |= CFLAG_FINISHED;
5272 		cv_broadcast(&mpt->m_passthru_cv);
5273 		return;
5274 	} else {
5275 		mptsas_remove_cmd(mpt, cmd);
5276 	}
5277 
5278 	if (cmd->cmd_flags & CFLAG_RETRY) {
5279 		/*
5280 		 * The target returned QFULL or busy, do not add tihs
5281 		 * pkt to the doneq since the hba will retry
5282 		 * this cmd.
5283 		 *
5284 		 * The pkt has already been resubmitted in
5285 		 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5286 		 * Remove this cmd_flag here.
5287 		 */
5288 		cmd->cmd_flags &= ~CFLAG_RETRY;
5289 	} else {
5290 		mptsas_doneq_add(mpt, cmd);
5291 	}
5292 }
5293 
5294 static void
5295 mptsas_handle_address_reply(mptsas_t *mpt,
5296     pMpi2ReplyDescriptorsUnion_t reply_desc)
5297 {
5298 	pMpi2AddressReplyDescriptor_t	address_reply;
5299 	pMPI2DefaultReply_t		reply;
5300 	mptsas_fw_diagnostic_buffer_t	*pBuffer;
5301 	uint32_t			reply_addr, reply_frame_dma_baseaddr;
5302 	uint16_t			SMID, iocstatus;
5303 	mptsas_slots_t			*slots = mpt->m_active;
5304 	mptsas_cmd_t			*cmd = NULL;
5305 	uint8_t				function, buffer_type;
5306 	m_replyh_arg_t			*args;
5307 	int				reply_frame_no;
5308 
5309 	ASSERT(mutex_owned(&mpt->m_mutex));
5310 
5311 	address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
5312 	reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
5313 	    &address_reply->ReplyFrameAddress);
5314 	SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
5315 
5316 	/*
5317 	 * If reply frame is not in the proper range we should ignore this
5318 	 * message and exit the interrupt handler.
5319 	 */
5320 	reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu;
5321 	if ((reply_addr < reply_frame_dma_baseaddr) ||
5322 	    (reply_addr >= (reply_frame_dma_baseaddr +
5323 	    (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
5324 	    ((reply_addr - reply_frame_dma_baseaddr) %
5325 	    mpt->m_reply_frame_size != 0)) {
5326 		mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
5327 		    "address 0x%x\n", reply_addr);
5328 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5329 		return;
5330 	}
5331 
5332 	(void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
5333 	    DDI_DMA_SYNC_FORCPU);
5334 	reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
5335 	    reply_frame_dma_baseaddr));
5336 	function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
5337 
5338 	NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x",
5339 	    function, reply_addr));
5340 
5341 	/*
5342 	 * don't get slot information and command for events since these values
5343 	 * don't exist
5344 	 */
5345 	if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
5346 	    (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
5347 		/*
5348 		 * This could be a TM reply, which use the last allocated SMID,
5349 		 * so allow for that.
5350 		 */
5351 		if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) {
5352 			mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
5353 			    "%d\n", SMID);
5354 			ddi_fm_service_impact(mpt->m_dip,
5355 			    DDI_SERVICE_UNAFFECTED);
5356 			return;
5357 		}
5358 
5359 		cmd = slots->m_slot[SMID];
5360 
5361 		/*
5362 		 * print warning and return if the slot is empty
5363 		 */
5364 		if (cmd == NULL) {
5365 			mptsas_log(mpt, CE_WARN, "?NULL command for address "
5366 			    "reply in slot %d", SMID);
5367 			return;
5368 		}
5369 		if ((cmd->cmd_flags &
5370 		    (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
5371 			cmd->cmd_rfm = reply_addr;
5372 			cmd->cmd_flags |= CFLAG_FINISHED;
5373 			cv_broadcast(&mpt->m_passthru_cv);
5374 			cv_broadcast(&mpt->m_config_cv);
5375 			cv_broadcast(&mpt->m_fw_diag_cv);
5376 			return;
5377 		} else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
5378 			mptsas_remove_cmd(mpt, cmd);
5379 		}
5380 		NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
5381 	}
5382 	/*
5383 	 * Depending on the function, we need to handle
5384 	 * the reply frame (and cmd) differently.
5385 	 */
5386 	switch (function) {
5387 	case MPI2_FUNCTION_SCSI_IO_REQUEST:
5388 		mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
5389 		break;
5390 	case MPI2_FUNCTION_SCSI_TASK_MGMT:
5391 		cmd->cmd_rfm = reply_addr;
5392 		mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
5393 		    cmd);
5394 		break;
5395 	case MPI2_FUNCTION_FW_DOWNLOAD:
5396 		cmd->cmd_flags |= CFLAG_FINISHED;
5397 		cv_signal(&mpt->m_fw_cv);
5398 		break;
5399 	case MPI2_FUNCTION_EVENT_NOTIFICATION:
5400 		reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) /
5401 		    mpt->m_reply_frame_size;
5402 		args = &mpt->m_replyh_args[reply_frame_no];
5403 		args->mpt = (void *)mpt;
5404 		args->rfm = reply_addr;
5405 
5406 		/*
5407 		 * Record the event if its type is enabled in
5408 		 * this mpt instance by ioctl.
5409 		 */
5410 		mptsas_record_event(args);
5411 
5412 		/*
5413 		 * Handle time critical events
5414 		 * NOT_RESPONDING/ADDED only now
5415 		 */
5416 		if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
5417 			/*
5418 			 * Would not return main process,
5419 			 * just let taskq resolve ack action
5420 			 * and ack would be sent in taskq thread
5421 			 */
5422 			NDBG20(("send mptsas_handle_event_sync success"));
5423 		}
5424 
5425 		if (mpt->m_in_reset) {
5426 			NDBG20(("dropping event received during reset"));
5427 			return;
5428 		}
5429 
5430 		if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
5431 		    (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
5432 			mptsas_log(mpt, CE_WARN, "No memory available"
5433 			"for dispatch taskq");
5434 			/*
5435 			 * Return the reply frame to the free queue.
5436 			 */
5437 			ddi_put32(mpt->m_acc_free_queue_hdl,
5438 			    &((uint32_t *)(void *)
5439 			    mpt->m_free_queue)[mpt->m_free_index], reply_addr);
5440 			(void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5441 			    DDI_DMA_SYNC_FORDEV);
5442 			if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5443 				mpt->m_free_index = 0;
5444 			}
5445 
5446 			ddi_put32(mpt->m_datap,
5447 			    &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
5448 		}
5449 		return;
5450 	case MPI2_FUNCTION_DIAG_BUFFER_POST:
5451 		/*
5452 		 * If SMID is 0, this implies that the reply is due to a
5453 		 * release function with a status that the buffer has been
5454 		 * released.  Set the buffer flags accordingly.
5455 		 */
5456 		if (SMID == 0) {
5457 			iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
5458 			    &reply->IOCStatus);
5459 			buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
5460 			    &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
5461 			if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
5462 				pBuffer =
5463 				    &mpt->m_fw_diag_buffer_list[buffer_type];
5464 				pBuffer->valid_data = TRUE;
5465 				pBuffer->owned_by_firmware = FALSE;
5466 				pBuffer->immediate = FALSE;
5467 			}
5468 		} else {
5469 			/*
5470 			 * Normal handling of diag post reply with SMID.
5471 			 */
5472 			cmd = slots->m_slot[SMID];
5473 
5474 			/*
5475 			 * print warning and return if the slot is empty
5476 			 */
5477 			if (cmd == NULL) {
5478 				mptsas_log(mpt, CE_WARN, "?NULL command for "
5479 				    "address reply in slot %d", SMID);
5480 				return;
5481 			}
5482 			cmd->cmd_rfm = reply_addr;
5483 			cmd->cmd_flags |= CFLAG_FINISHED;
5484 			cv_broadcast(&mpt->m_fw_diag_cv);
5485 		}
5486 		return;
5487 	default:
5488 		mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
5489 		break;
5490 	}
5491 
5492 	/*
5493 	 * Return the reply frame to the free queue.
5494 	 */
5495 	ddi_put32(mpt->m_acc_free_queue_hdl,
5496 	    &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
5497 	    reply_addr);
5498 	(void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5499 	    DDI_DMA_SYNC_FORDEV);
5500 	if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5501 		mpt->m_free_index = 0;
5502 	}
5503 	ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
5504 	    mpt->m_free_index);
5505 
5506 	if (cmd->cmd_flags & CFLAG_FW_CMD)
5507 		return;
5508 
5509 	if (cmd->cmd_flags & CFLAG_RETRY) {
5510 		/*
5511 		 * The target returned QFULL or busy, do not add this
5512 		 * pkt to the doneq since the hba will retry
5513 		 * this cmd.
5514 		 *
5515 		 * The pkt has already been resubmitted in
5516 		 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5517 		 * Remove this cmd_flag here.
5518 		 */
5519 		cmd->cmd_flags &= ~CFLAG_RETRY;
5520 	} else {
5521 		mptsas_doneq_add(mpt, cmd);
5522 	}
5523 }
5524 
5525 #ifdef MPTSAS_DEBUG
5526 static uint8_t mptsas_last_sense[256];
5527 #endif
5528 
5529 static void
5530 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5531     mptsas_cmd_t *cmd)
5532 {
5533 	uint8_t			scsi_status, scsi_state;
5534 	uint16_t		ioc_status, cmd_rqs_len;
5535 	uint32_t		xferred, sensecount, responsedata, loginfo = 0;
5536 	struct scsi_pkt		*pkt;
5537 	struct scsi_arq_status	*arqstat;
5538 	mptsas_target_t		*ptgt = cmd->cmd_tgt_addr;
5539 	uint8_t			*sensedata = NULL;
5540 	uint64_t		sas_wwn;
5541 	uint8_t			phy;
5542 	char			wwn_str[MPTSAS_WWN_STRLEN];
5543 
5544 	scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5545 	ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5546 	scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5547 	xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5548 	sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5549 	responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5550 	    &reply->ResponseInfo);
5551 
5552 	if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5553 		sas_wwn = ptgt->m_addr.mta_wwn;
5554 		phy = ptgt->m_phynum;
5555 		if (sas_wwn == 0) {
5556 			(void) sprintf(wwn_str, "p%x", phy);
5557 		} else {
5558 			(void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
5559 		}
5560 		loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5561 		    &reply->IOCLogInfo);
5562 		mptsas_log(mpt, CE_NOTE,
5563 		    "?Log info 0x%x received for target %d %s.\n"
5564 		    "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5565 		    loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status,
5566 		    scsi_state);
5567 	}
5568 
5569 	NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5570 	    scsi_status, ioc_status, scsi_state));
5571 
5572 	pkt = CMD2PKT(cmd);
5573 	*(pkt->pkt_scbp) = scsi_status;
5574 
5575 	if (loginfo == 0x31170000) {
5576 		/*
5577 		 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5578 		 * 0x31170000 comes, that means the device missing delay
5579 		 * is in progressing, the command need retry later.
5580 		 */
5581 		*(pkt->pkt_scbp) = STATUS_BUSY;
5582 		return;
5583 	}
5584 
5585 	if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5586 	    ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5587 	    MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5588 		pkt->pkt_reason = CMD_INCOMPLETE;
5589 		pkt->pkt_state |= STATE_GOT_BUS;
5590 		if (ptgt->m_reset_delay == 0) {
5591 			mptsas_set_throttle(mpt, ptgt,
5592 			    DRAIN_THROTTLE);
5593 		}
5594 		return;
5595 	}
5596 
5597 	if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5598 		responsedata &= 0x000000FF;
5599 		if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5600 			mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5601 			pkt->pkt_reason = CMD_TLR_OFF;
5602 			return;
5603 		}
5604 	}
5605 
5606 
5607 	switch (scsi_status) {
5608 	case MPI2_SCSI_STATUS_CHECK_CONDITION:
5609 		pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5610 		arqstat = (void*)(pkt->pkt_scbp);
5611 		arqstat->sts_rqpkt_status = *((struct scsi_status *)
5612 		    (pkt->pkt_scbp));
5613 		pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5614 		    STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5615 		if (cmd->cmd_flags & CFLAG_XARQ) {
5616 			pkt->pkt_state |= STATE_XARQ_DONE;
5617 		}
5618 		if (pkt->pkt_resid != cmd->cmd_dmacount) {
5619 			pkt->pkt_state |= STATE_XFERRED_DATA;
5620 		}
5621 		arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5622 		arqstat->sts_rqpkt_state  = pkt->pkt_state;
5623 		arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5624 		arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5625 		sensedata = (uint8_t *)&arqstat->sts_sensedata;
5626 		cmd_rqs_len = cmd->cmd_extrqslen ?
5627 		    cmd->cmd_extrqslen : cmd->cmd_rqslen;
5628 		(void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
5629 		    DDI_DMA_SYNC_FORKERNEL);
5630 #ifdef MPTSAS_DEBUG
5631 		bcopy(cmd->cmd_arq_buf, mptsas_last_sense,
5632 		    ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ?
5633 		    sizeof (mptsas_last_sense):cmd_rqs_len));
5634 #endif
5635 		bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata,
5636 		    ((cmd_rqs_len >= sensecount) ? sensecount :
5637 		    cmd_rqs_len));
5638 		arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount);
5639 		cmd->cmd_flags |= CFLAG_CMDARQ;
5640 		/*
5641 		 * Set proper status for pkt if autosense was valid
5642 		 */
5643 		if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5644 			struct scsi_status zero_status = { 0 };
5645 			arqstat->sts_rqpkt_status = zero_status;
5646 		}
5647 
5648 		/*
5649 		 * ASC=0x47 is parity error
5650 		 * ASC=0x48 is initiator detected error received
5651 		 */
5652 		if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5653 		    ((scsi_sense_asc(sensedata) == 0x47) ||
5654 		    (scsi_sense_asc(sensedata) == 0x48))) {
5655 			mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5656 		}
5657 
5658 		/*
5659 		 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5660 		 * ASC/ASCQ=0x25/0x00 means invalid lun
5661 		 */
5662 		if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5663 		    (scsi_sense_asc(sensedata) == 0x3F) &&
5664 		    (scsi_sense_ascq(sensedata) == 0x0E)) ||
5665 		    ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5666 		    (scsi_sense_asc(sensedata) == 0x25) &&
5667 		    (scsi_sense_ascq(sensedata) == 0x00))) {
5668 			mptsas_topo_change_list_t *topo_node = NULL;
5669 
5670 			topo_node = kmem_zalloc(
5671 			    sizeof (mptsas_topo_change_list_t),
5672 			    KM_NOSLEEP);
5673 			if (topo_node == NULL) {
5674 				mptsas_log(mpt, CE_NOTE, "No memory"
5675 				    "resource for handle SAS dynamic"
5676 				    "reconfigure.\n");
5677 				break;
5678 			}
5679 			topo_node->mpt = mpt;
5680 			topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5681 			topo_node->un.phymask = ptgt->m_addr.mta_phymask;
5682 			topo_node->devhdl = ptgt->m_devhdl;
5683 			topo_node->object = (void *)ptgt;
5684 			topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5685 
5686 			if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5687 			    mptsas_handle_dr,
5688 			    (void *)topo_node,
5689 			    DDI_NOSLEEP)) != DDI_SUCCESS) {
5690 				kmem_free(topo_node,
5691 				    sizeof (mptsas_topo_change_list_t));
5692 				mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5693 				    "for handle SAS dynamic reconfigure"
5694 				    "failed. \n");
5695 			}
5696 		}
5697 		break;
5698 	case MPI2_SCSI_STATUS_GOOD:
5699 		switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5700 		case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5701 			pkt->pkt_reason = CMD_DEV_GONE;
5702 			pkt->pkt_state |= STATE_GOT_BUS;
5703 			if (ptgt->m_reset_delay == 0) {
5704 				mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5705 			}
5706 			NDBG31(("lost disk for target%d, command:%x",
5707 			    Tgt(cmd), pkt->pkt_cdbp[0]));
5708 			break;
5709 		case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5710 			NDBG31(("data overrun: xferred=%d", xferred));
5711 			NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5712 			pkt->pkt_reason = CMD_DATA_OVR;
5713 			pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5714 			    | STATE_SENT_CMD | STATE_GOT_STATUS
5715 			    | STATE_XFERRED_DATA);
5716 			pkt->pkt_resid = 0;
5717 			break;
5718 		case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5719 		case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5720 			NDBG31(("data underrun: xferred=%d", xferred));
5721 			NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5722 			pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5723 			    | STATE_SENT_CMD | STATE_GOT_STATUS);
5724 			pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5725 			if (pkt->pkt_resid != cmd->cmd_dmacount) {
5726 				pkt->pkt_state |= STATE_XFERRED_DATA;
5727 			}
5728 			break;
5729 		case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5730 			if (cmd->cmd_active_expiration <= gethrtime()) {
5731 				/*
5732 				 * When timeout requested, propagate
5733 				 * proper reason and statistics to
5734 				 * target drivers.
5735 				 */
5736 				mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT,
5737 				    STAT_BUS_RESET | STAT_TIMEOUT);
5738 			} else {
5739 				mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
5740 				    STAT_BUS_RESET);
5741 			}
5742 			break;
5743 		case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5744 		case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5745 			mptsas_set_pkt_reason(mpt,
5746 			    cmd, CMD_RESET, STAT_DEV_RESET);
5747 			break;
5748 		case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5749 		case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5750 			pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5751 			mptsas_set_pkt_reason(mpt,
5752 			    cmd, CMD_TERMINATED, STAT_TERMINATED);
5753 			break;
5754 		case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5755 		case MPI2_IOCSTATUS_BUSY:
5756 			/*
5757 			 * set throttles to drain
5758 			 */
5759 			for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
5760 			    ptgt = refhash_next(mpt->m_targets, ptgt)) {
5761 				mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5762 			}
5763 
5764 			/*
5765 			 * retry command
5766 			 */
5767 			cmd->cmd_flags |= CFLAG_RETRY;
5768 			cmd->cmd_pkt_flags |= FLAG_HEAD;
5769 
5770 			(void) mptsas_accept_pkt(mpt, cmd);
5771 			break;
5772 		default:
5773 			mptsas_log(mpt, CE_WARN,
5774 			    "unknown ioc_status = %x\n", ioc_status);
5775 			mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5776 			    "count = %x, scsi_status = %x", scsi_state,
5777 			    xferred, scsi_status);
5778 			break;
5779 		}
5780 		break;
5781 	case MPI2_SCSI_STATUS_TASK_SET_FULL:
5782 		mptsas_handle_qfull(mpt, cmd);
5783 		break;
5784 	case MPI2_SCSI_STATUS_BUSY:
5785 		NDBG31(("scsi_status busy received"));
5786 		break;
5787 	case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5788 		NDBG31(("scsi_status reservation conflict received"));
5789 		break;
5790 	default:
5791 		mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5792 		    scsi_status, ioc_status);
5793 		mptsas_log(mpt, CE_WARN,
5794 		    "mptsas_process_intr: invalid scsi status\n");
5795 		break;
5796 	}
5797 }
5798 
5799 static void
5800 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5801     mptsas_cmd_t *cmd)
5802 {
5803 	uint8_t		task_type;
5804 	uint16_t	ioc_status;
5805 	uint32_t	log_info;
5806 	uint16_t	dev_handle;
5807 	struct scsi_pkt *pkt = CMD2PKT(cmd);
5808 
5809 	task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5810 	ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5811 	log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5812 	dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5813 
5814 	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5815 		mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5816 		    "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5817 		    task_type, ioc_status, log_info, dev_handle);
5818 		pkt->pkt_reason = CMD_INCOMPLETE;
5819 		return;
5820 	}
5821 
5822 	switch (task_type) {
5823 	case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5824 	case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5825 	case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5826 	case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5827 	case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5828 	case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5829 		break;
5830 	case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5831 	case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5832 	case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5833 		/*
5834 		 * Check for invalid DevHandle of 0 in case application
5835 		 * sends bad command.  DevHandle of 0 could cause problems.
5836 		 */
5837 		if (dev_handle == 0) {
5838 			mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5839 			    " DevHandle of 0.");
5840 		} else {
5841 			mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5842 			    task_type);
5843 		}
5844 		break;
5845 	default:
5846 		mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5847 		    task_type);
5848 		mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5849 		break;
5850 	}
5851 }
5852 
5853 static void
5854 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5855 {
5856 	mptsas_t			*mpt = arg->mpt;
5857 	uint64_t			t = arg->t;
5858 	mptsas_cmd_t			*cmd;
5859 	struct scsi_pkt			*pkt;
5860 	mptsas_doneq_thread_list_t	*item = &mpt->m_doneq_thread_id[t];
5861 
5862 	mutex_enter(&item->mutex);
5863 	while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5864 		if (!item->doneq) {
5865 			cv_wait(&item->cv, &item->mutex);
5866 		}
5867 		pkt = NULL;
5868 		if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5869 			cmd->cmd_flags |= CFLAG_COMPLETED;
5870 			pkt = CMD2PKT(cmd);
5871 		}
5872 		mutex_exit(&item->mutex);
5873 		if (pkt) {
5874 			mptsas_pkt_comp(pkt, cmd);
5875 		}
5876 		mutex_enter(&item->mutex);
5877 	}
5878 	mutex_exit(&item->mutex);
5879 	mutex_enter(&mpt->m_doneq_mutex);
5880 	mpt->m_doneq_thread_n--;
5881 	cv_broadcast(&mpt->m_doneq_thread_cv);
5882 	mutex_exit(&mpt->m_doneq_mutex);
5883 }
5884 
5885 
5886 /*
5887  * mpt interrupt handler.
5888  */
5889 static uint_t
5890 mptsas_intr(caddr_t arg1, caddr_t arg2)
5891 {
5892 	mptsas_t			*mpt = (void *)arg1;
5893 	pMpi2ReplyDescriptorsUnion_t	reply_desc_union;
5894 	uchar_t				did_reply = FALSE;
5895 
5896 	NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5897 
5898 	mutex_enter(&mpt->m_mutex);
5899 
5900 	/*
5901 	 * If interrupts are shared by two channels then check whether this
5902 	 * interrupt is genuinely for this channel by making sure first the
5903 	 * chip is in high power state.
5904 	 */
5905 	if ((mpt->m_options & MPTSAS_OPT_PM) &&
5906 	    (mpt->m_power_level != PM_LEVEL_D0)) {
5907 		mutex_exit(&mpt->m_mutex);
5908 		return (DDI_INTR_UNCLAIMED);
5909 	}
5910 
5911 	/*
5912 	 * If polling, interrupt was triggered by some shared interrupt because
5913 	 * IOC interrupts are disabled during polling, so polling routine will
5914 	 * handle any replies.  Considering this, if polling is happening,
5915 	 * return with interrupt unclaimed.
5916 	 */
5917 	if (mpt->m_polled_intr) {
5918 		mutex_exit(&mpt->m_mutex);
5919 		mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5920 		return (DDI_INTR_UNCLAIMED);
5921 	}
5922 
5923 	/*
5924 	 * Read the istat register.
5925 	 */
5926 	if ((INTPENDING(mpt)) != 0) {
5927 		/*
5928 		 * read fifo until empty.
5929 		 */
5930 #ifndef __lock_lint
5931 		_NOTE(CONSTCOND)
5932 #endif
5933 		while (TRUE) {
5934 			(void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5935 			    DDI_DMA_SYNC_FORCPU);
5936 			reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5937 			    MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5938 
5939 			if (ddi_get32(mpt->m_acc_post_queue_hdl,
5940 			    &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5941 			    ddi_get32(mpt->m_acc_post_queue_hdl,
5942 			    &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5943 				break;
5944 			}
5945 
5946 			/*
5947 			 * The reply is valid, process it according to its
5948 			 * type.  Also, set a flag for updating the reply index
5949 			 * after they've all been processed.
5950 			 */
5951 			did_reply = TRUE;
5952 
5953 			mptsas_process_intr(mpt, reply_desc_union);
5954 
5955 			/*
5956 			 * Increment post index and roll over if needed.
5957 			 */
5958 			if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5959 				mpt->m_post_index = 0;
5960 			}
5961 		}
5962 
5963 		/*
5964 		 * Update the global reply index if at least one reply was
5965 		 * processed.
5966 		 */
5967 		if (did_reply) {
5968 			ddi_put32(mpt->m_datap,
5969 			    &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5970 		}
5971 	} else {
5972 		mutex_exit(&mpt->m_mutex);
5973 		return (DDI_INTR_UNCLAIMED);
5974 	}
5975 	NDBG1(("mptsas_intr complete"));
5976 
5977 	/*
5978 	 * If no helper threads are created, process the doneq in ISR. If
5979 	 * helpers are created, use the doneq length as a metric to measure the
5980 	 * load on the interrupt CPU. If it is long enough, which indicates the
5981 	 * load is heavy, then we deliver the IO completions to the helpers.
5982 	 * This measurement has some limitations, although it is simple and
5983 	 * straightforward and works well for most of the cases at present.
5984 	 */
5985 	if (!mpt->m_doneq_thread_n ||
5986 	    (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5987 		mptsas_doneq_empty(mpt);
5988 	} else {
5989 		mptsas_deliver_doneq_thread(mpt);
5990 	}
5991 
5992 	/*
5993 	 * If there are queued cmd, start them now.
5994 	 */
5995 	if (mpt->m_waitq != NULL) {
5996 		mptsas_restart_waitq(mpt);
5997 	}
5998 
5999 	mutex_exit(&mpt->m_mutex);
6000 	return (DDI_INTR_CLAIMED);
6001 }
6002 
6003 static void
6004 mptsas_process_intr(mptsas_t *mpt,
6005     pMpi2ReplyDescriptorsUnion_t reply_desc_union)
6006 {
6007 	uint8_t	reply_type;
6008 
6009 	ASSERT(mutex_owned(&mpt->m_mutex));
6010 
6011 	/*
6012 	 * The reply is valid, process it according to its
6013 	 * type.  Also, set a flag for updated the reply index
6014 	 * after they've all been processed.
6015 	 */
6016 	reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
6017 	    &reply_desc_union->Default.ReplyFlags);
6018 	reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
6019 	if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
6020 	    reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) {
6021 		mptsas_handle_scsi_io_success(mpt, reply_desc_union);
6022 	} else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
6023 		mptsas_handle_address_reply(mpt, reply_desc_union);
6024 	} else {
6025 		mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
6026 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
6027 	}
6028 
6029 	/*
6030 	 * Clear the reply descriptor for re-use and increment
6031 	 * index.
6032 	 */
6033 	ddi_put64(mpt->m_acc_post_queue_hdl,
6034 	    &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
6035 	    0xFFFFFFFFFFFFFFFF);
6036 	(void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
6037 	    DDI_DMA_SYNC_FORDEV);
6038 }
6039 
6040 /*
6041  * handle qfull condition
6042  */
6043 static void
6044 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
6045 {
6046 	mptsas_target_t	*ptgt = cmd->cmd_tgt_addr;
6047 
6048 	if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
6049 	    (ptgt->m_qfull_retries == 0)) {
6050 		/*
6051 		 * We have exhausted the retries on QFULL, or,
6052 		 * the target driver has indicated that it
6053 		 * wants to handle QFULL itself by setting
6054 		 * qfull-retries capability to 0. In either case
6055 		 * we want the target driver's QFULL handling
6056 		 * to kick in. We do this by having pkt_reason
6057 		 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
6058 		 */
6059 		mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
6060 	} else {
6061 		if (ptgt->m_reset_delay == 0) {
6062 			ptgt->m_t_throttle =
6063 			    max((ptgt->m_t_ncmds - 2), 0);
6064 		}
6065 
6066 		cmd->cmd_pkt_flags |= FLAG_HEAD;
6067 		cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
6068 		cmd->cmd_flags |= CFLAG_RETRY;
6069 
6070 		(void) mptsas_accept_pkt(mpt, cmd);
6071 
6072 		/*
6073 		 * when target gives queue full status with no commands
6074 		 * outstanding (m_t_ncmds == 0), throttle is set to 0
6075 		 * (HOLD_THROTTLE), and the queue full handling start
6076 		 * (see psarc/1994/313); if there are commands outstanding,
6077 		 * throttle is set to (m_t_ncmds - 2)
6078 		 */
6079 		if (ptgt->m_t_throttle == HOLD_THROTTLE) {
6080 			/*
6081 			 * By setting throttle to QFULL_THROTTLE, we
6082 			 * avoid submitting new commands and in
6083 			 * mptsas_restart_cmd find out slots which need
6084 			 * their throttles to be cleared.
6085 			 */
6086 			mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
6087 			if (mpt->m_restart_cmd_timeid == 0) {
6088 				mpt->m_restart_cmd_timeid =
6089 				    timeout(mptsas_restart_cmd, mpt,
6090 				    ptgt->m_qfull_retry_interval);
6091 			}
6092 		}
6093 	}
6094 }
6095 
6096 mptsas_phymask_t
6097 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
6098 {
6099 	mptsas_phymask_t	phy_mask = 0;
6100 	uint8_t			i = 0;
6101 
6102 	NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
6103 
6104 	ASSERT(mutex_owned(&mpt->m_mutex));
6105 
6106 	/*
6107 	 * If physport is 0xFF, this is a RAID volume.  Use phymask of 0.
6108 	 */
6109 	if (physport == 0xFF) {
6110 		return (0);
6111 	}
6112 
6113 	for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
6114 		if (mpt->m_phy_info[i].attached_devhdl &&
6115 		    (mpt->m_phy_info[i].phy_mask != 0) &&
6116 		    (mpt->m_phy_info[i].port_num == physport)) {
6117 			phy_mask = mpt->m_phy_info[i].phy_mask;
6118 			break;
6119 		}
6120 	}
6121 	NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
6122 	    mpt->m_instance, physport, phy_mask));
6123 	return (phy_mask);
6124 }
6125 
6126 /*
6127  * mpt free device handle after device gone, by use of passthrough
6128  */
6129 static int
6130 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
6131 {
6132 	Mpi2SasIoUnitControlRequest_t	req;
6133 	Mpi2SasIoUnitControlReply_t	rep;
6134 	int				ret;
6135 
6136 	ASSERT(mutex_owned(&mpt->m_mutex));
6137 
6138 	/*
6139 	 * Need to compose a SAS IO Unit Control request message
6140 	 * and call mptsas_do_passthru() function
6141 	 */
6142 	bzero(&req, sizeof (req));
6143 	bzero(&rep, sizeof (rep));
6144 
6145 	req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
6146 	req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
6147 	req.DevHandle = LE_16(devhdl);
6148 
6149 	ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
6150 	    sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
6151 	if (ret != 0) {
6152 		cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6153 		    "Control error %d", ret);
6154 		return (DDI_FAILURE);
6155 	}
6156 
6157 	/* do passthrough success, check the ioc status */
6158 	if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
6159 		cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6160 		    "Control IOCStatus %d", LE_16(rep.IOCStatus));
6161 		return (DDI_FAILURE);
6162 	}
6163 
6164 	return (DDI_SUCCESS);
6165 }
6166 
6167 /*
6168  * We have a SATA target that has changed, which means the "bridge-port"
6169  * property must be updated to reflect the SAS WWN of the new attachment point.
6170  * This may change if a SATA device changes which bay, and therefore phy, it is
6171  * plugged into. This SATA device may be a multipath virtual device or may be a
6172  * physical device. We have to handle both cases.
6173  */
6174 static boolean_t
6175 mptsas_update_sata_bridge(mptsas_t *mpt, dev_info_t *parent,
6176     mptsas_target_t *ptgt)
6177 {
6178 	int			rval;
6179 	uint16_t		dev_hdl;
6180 	uint16_t		pdev_hdl;
6181 	uint64_t		dev_sas_wwn;
6182 	uint8_t			physport;
6183 	uint8_t			phy_id;
6184 	uint32_t		page_address;
6185 	uint16_t		bay_num, enclosure, io_flags;
6186 	uint32_t		dev_info;
6187 	char 			uabuf[SCSI_WWN_BUFLEN];
6188 	dev_info_t		*dip;
6189 	mdi_pathinfo_t		*pip;
6190 
6191 	mutex_enter(&mpt->m_mutex);
6192 	page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6193 	    MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)ptgt->m_devhdl;
6194 	rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
6195 	    &dev_sas_wwn, &dev_info, &physport, &phy_id, &pdev_hdl, &bay_num,
6196 	    &enclosure, &io_flags);
6197 	mutex_exit(&mpt->m_mutex);
6198 	if (rval != DDI_SUCCESS) {
6199 		mptsas_log(mpt, CE_WARN, "unable to get SAS page 0 for "
6200 		    "handle %d", page_address);
6201 		return (B_FALSE);
6202 	}
6203 
6204 	if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) {
6205 		mptsas_log(mpt, CE_WARN,
6206 		    "mptsas unable to format SATA bridge WWN");
6207 		return (B_FALSE);
6208 	}
6209 
6210 	if (mpt->m_mpxio_enable == TRUE && (pip = mptsas_find_path_addr(parent,
6211 	    ptgt->m_addr.mta_wwn, 0)) != NULL) {
6212 		if (mdi_prop_update_string(pip, SCSI_ADDR_PROP_BRIDGE_PORT,
6213 		    uabuf) != DDI_SUCCESS) {
6214 			mptsas_log(mpt, CE_WARN,
6215 			    "mptsas unable to create SCSI bridge port "
6216 			    "property for SATA device");
6217 			return (B_FALSE);
6218 		}
6219 		return (B_TRUE);
6220 	}
6221 
6222 	if ((dip = mptsas_find_child_addr(parent, ptgt->m_addr.mta_wwn,
6223 	    0)) != NULL) {
6224 		if (ndi_prop_update_string(DDI_DEV_T_NONE, dip,
6225 		    SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != DDI_PROP_SUCCESS) {
6226 			mptsas_log(mpt, CE_WARN,
6227 			    "mptsas unable to create SCSI bridge port "
6228 			    "property for SATA device");
6229 			return (B_FALSE);
6230 		}
6231 		return (B_TRUE);
6232 	}
6233 
6234 	mptsas_log(mpt, CE_WARN, "mptsas failed to find dev_info_t or "
6235 	    "mdi_pathinfo_t for target with WWN %016" PRIx64,
6236 	    ptgt->m_addr.mta_wwn);
6237 
6238 	return (B_FALSE);
6239 }
6240 
6241 static void
6242 mptsas_update_phymask(mptsas_t *mpt)
6243 {
6244 	mptsas_phymask_t mask = 0, phy_mask;
6245 	char		*phy_mask_name;
6246 	uint8_t		current_port;
6247 	int		i, j;
6248 
6249 	NDBG20(("mptsas%d update phymask ", mpt->m_instance));
6250 
6251 	ASSERT(mutex_owned(&mpt->m_mutex));
6252 
6253 	(void) mptsas_get_sas_io_unit_page(mpt);
6254 
6255 	phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6256 
6257 	for (i = 0; i < mpt->m_num_phys; i++) {
6258 		phy_mask = 0x00;
6259 
6260 		if (mpt->m_phy_info[i].attached_devhdl == 0)
6261 			continue;
6262 
6263 		bzero(phy_mask_name, sizeof (phy_mask_name));
6264 
6265 		current_port = mpt->m_phy_info[i].port_num;
6266 
6267 		if ((mask & (1 << i)) != 0)
6268 			continue;
6269 
6270 		for (j = 0; j < mpt->m_num_phys; j++) {
6271 			if (mpt->m_phy_info[j].attached_devhdl &&
6272 			    (mpt->m_phy_info[j].port_num == current_port)) {
6273 				phy_mask |= (1 << j);
6274 			}
6275 		}
6276 		mask = mask | phy_mask;
6277 
6278 		for (j = 0; j < mpt->m_num_phys; j++) {
6279 			if ((phy_mask >> j) & 0x01) {
6280 				mpt->m_phy_info[j].phy_mask = phy_mask;
6281 			}
6282 		}
6283 
6284 		(void) sprintf(phy_mask_name, "%x", phy_mask);
6285 
6286 		mutex_exit(&mpt->m_mutex);
6287 		/*
6288 		 * register a iport, if the port has already been existed
6289 		 * SCSA will do nothing and just return.
6290 		 */
6291 		(void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
6292 		mutex_enter(&mpt->m_mutex);
6293 	}
6294 	kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6295 	NDBG20(("mptsas%d update phymask return", mpt->m_instance));
6296 }
6297 
6298 /*
6299  * mptsas_handle_dr is a task handler for DR, the DR action includes:
6300  * 1. Directly attched Device Added/Removed.
6301  * 2. Expander Device Added/Removed.
6302  * 3. Indirectly Attached Device Added/Expander.
6303  * 4. LUNs of a existing device status change.
6304  * 5. RAID volume created/deleted.
6305  * 6. Member of RAID volume is released because of RAID deletion.
6306  * 7. Physical disks are removed because of RAID creation.
6307  */
6308 static void
6309 mptsas_handle_dr(void *args)
6310 {
6311 	mptsas_topo_change_list_t	*topo_node = NULL;
6312 	mptsas_topo_change_list_t	*save_node = NULL;
6313 	mptsas_t			*mpt;
6314 	dev_info_t			*parent = NULL;
6315 	mptsas_phymask_t		phymask = 0;
6316 	char				*phy_mask_name;
6317 	uint8_t				flags = 0, physport = 0xff;
6318 	uint8_t				port_update = 0;
6319 	uint_t				event;
6320 
6321 	topo_node = (mptsas_topo_change_list_t *)args;
6322 
6323 	mpt = topo_node->mpt;
6324 	event = topo_node->event;
6325 	flags = topo_node->flags;
6326 
6327 	phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6328 
6329 	NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
6330 
6331 	switch (event) {
6332 	case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6333 		if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6334 		    (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
6335 		    (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6336 			/*
6337 			 * Direct attached or expander attached device added
6338 			 * into system or a Phys Disk that is being unhidden.
6339 			 */
6340 			port_update = 1;
6341 		}
6342 		break;
6343 	case MPTSAS_DR_EVENT_RECONFIG_SMP:
6344 		/*
6345 		 * New expander added into system, it must be the head
6346 		 * of topo_change_list_t
6347 		 */
6348 		port_update = 1;
6349 		break;
6350 	default:
6351 		port_update = 0;
6352 		break;
6353 	}
6354 	/*
6355 	 * All cases port_update == 1 may cause initiator port form change
6356 	 */
6357 	mutex_enter(&mpt->m_mutex);
6358 	if (mpt->m_port_chng && port_update) {
6359 		/*
6360 		 * mpt->m_port_chng flag indicates some PHYs of initiator
6361 		 * port have changed to online. So when expander added or
6362 		 * directly attached device online event come, we force to
6363 		 * update port information by issueing SAS IO Unit Page and
6364 		 * update PHYMASKs.
6365 		 */
6366 		(void) mptsas_update_phymask(mpt);
6367 		mpt->m_port_chng = 0;
6368 
6369 	}
6370 	mutex_exit(&mpt->m_mutex);
6371 	while (topo_node) {
6372 		phymask = 0;
6373 		if (parent == NULL) {
6374 			physport = topo_node->un.physport;
6375 			event = topo_node->event;
6376 			flags = topo_node->flags;
6377 			if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
6378 			    MPTSAS_DR_EVENT_OFFLINE_SMP)) {
6379 				/*
6380 				 * For all offline events, phymask is known
6381 				 */
6382 				phymask = topo_node->un.phymask;
6383 				goto find_parent;
6384 			}
6385 			if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6386 				goto handle_topo_change;
6387 			}
6388 			if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
6389 				phymask = topo_node->un.phymask;
6390 				goto find_parent;
6391 			}
6392 
6393 			if ((flags ==
6394 			    MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
6395 			    (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
6396 				/*
6397 				 * There is no any field in IR_CONFIG_CHANGE
6398 				 * event indicate physport/phynum, let's get
6399 				 * parent after SAS Device Page0 request.
6400 				 */
6401 				goto handle_topo_change;
6402 			}
6403 
6404 			mutex_enter(&mpt->m_mutex);
6405 			if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6406 				/*
6407 				 * If the direct attached device added or a
6408 				 * phys disk is being unhidden, argument
6409 				 * physport actually is PHY#, so we have to get
6410 				 * phymask according PHY#.
6411 				 */
6412 				physport = mpt->m_phy_info[physport].port_num;
6413 			}
6414 
6415 			/*
6416 			 * Translate physport to phymask so that we can search
6417 			 * parent dip.
6418 			 */
6419 			phymask = mptsas_physport_to_phymask(mpt,
6420 			    physport);
6421 			mutex_exit(&mpt->m_mutex);
6422 
6423 find_parent:
6424 			bzero(phy_mask_name, MPTSAS_MAX_PHYS);
6425 			/*
6426 			 * For RAID topology change node, write the iport name
6427 			 * as v0.
6428 			 */
6429 			if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6430 				(void) sprintf(phy_mask_name, "v0");
6431 			} else {
6432 				/*
6433 				 * phymask can bo 0 if the drive has been
6434 				 * pulled by the time an add event is
6435 				 * processed.  If phymask is 0, just skip this
6436 				 * event and continue.
6437 				 */
6438 				if (phymask == 0) {
6439 					mutex_enter(&mpt->m_mutex);
6440 					save_node = topo_node;
6441 					topo_node = topo_node->next;
6442 					ASSERT(save_node);
6443 					kmem_free(save_node,
6444 					    sizeof (mptsas_topo_change_list_t));
6445 					mutex_exit(&mpt->m_mutex);
6446 
6447 					parent = NULL;
6448 					continue;
6449 				}
6450 				(void) sprintf(phy_mask_name, "%x", phymask);
6451 			}
6452 			parent = scsi_hba_iport_find(mpt->m_dip,
6453 			    phy_mask_name);
6454 			if (parent == NULL) {
6455 				mptsas_log(mpt, CE_WARN, "Failed to find an "
6456 				    "iport, should not happen!");
6457 				goto out;
6458 			}
6459 
6460 		}
6461 		ASSERT(parent);
6462 handle_topo_change:
6463 
6464 		mutex_enter(&mpt->m_mutex);
6465 		/*
6466 		 * If HBA is being reset, don't perform operations depending
6467 		 * on the IOC. We must free the topo list, however.
6468 		 */
6469 		if (!mpt->m_in_reset) {
6470 			mptsas_handle_topo_change(topo_node, parent);
6471 		} else {
6472 			NDBG20(("skipping topo change received during reset"));
6473 		}
6474 		save_node = topo_node;
6475 		topo_node = topo_node->next;
6476 		ASSERT(save_node);
6477 		kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6478 		mutex_exit(&mpt->m_mutex);
6479 
6480 		if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6481 		    (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6482 		    (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6483 			/*
6484 			 * If direct attached device associated, make sure
6485 			 * reset the parent before start the next one. But
6486 			 * all devices associated with expander shares the
6487 			 * parent.  Also, reset parent if this is for RAID.
6488 			 */
6489 			parent = NULL;
6490 		}
6491 	}
6492 out:
6493 	kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6494 }
6495 
6496 static void
6497 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
6498     dev_info_t *parent)
6499 {
6500 	mptsas_target_t	*ptgt = NULL;
6501 	mptsas_smp_t	*psmp = NULL;
6502 	mptsas_t	*mpt = (void *)topo_node->mpt;
6503 	uint16_t	devhdl;
6504 	uint16_t	attached_devhdl;
6505 	uint64_t	sas_wwn = 0;
6506 	int		rval = 0;
6507 	uint32_t	page_address;
6508 	uint8_t		phy, flags;
6509 	char		*addr = NULL;
6510 	dev_info_t	*lundip;
6511 	int		circ = 0, circ1 = 0;
6512 	char		attached_wwnstr[MPTSAS_WWN_STRLEN];
6513 
6514 	NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x,"
6515 	    "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl,
6516 	    topo_node->event, topo_node->flags));
6517 
6518 	ASSERT(mutex_owned(&mpt->m_mutex));
6519 
6520 	switch (topo_node->event) {
6521 	case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6522 	{
6523 		char *phy_mask_name;
6524 		mptsas_phymask_t phymask = 0;
6525 
6526 		if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6527 			/*
6528 			 * Get latest RAID info.
6529 			 */
6530 			(void) mptsas_get_raid_info(mpt);
6531 			ptgt = refhash_linear_search(mpt->m_targets,
6532 			    mptsas_target_eval_devhdl, &topo_node->devhdl);
6533 			if (ptgt == NULL)
6534 				break;
6535 		} else {
6536 			ptgt = (void *)topo_node->object;
6537 		}
6538 
6539 		if (ptgt == NULL) {
6540 			/*
6541 			 * If a Phys Disk was deleted, RAID info needs to be
6542 			 * updated to reflect the new topology.
6543 			 */
6544 			(void) mptsas_get_raid_info(mpt);
6545 
6546 			/*
6547 			 * Get sas device page 0 by DevHandle to make sure if
6548 			 * SSP/SATA end device exist.
6549 			 */
6550 			page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6551 			    MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
6552 			    topo_node->devhdl;
6553 
6554 			rval = mptsas_get_target_device_info(mpt, page_address,
6555 			    &devhdl, &ptgt);
6556 			if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
6557 				mptsas_log(mpt, CE_NOTE,
6558 				    "mptsas_handle_topo_change: target %d is "
6559 				    "not a SAS/SATA device. \n",
6560 				    topo_node->devhdl);
6561 			} else if (rval == DEV_INFO_FAIL_ALLOC) {
6562 				mptsas_log(mpt, CE_NOTE,
6563 				    "mptsas_handle_topo_change: could not "
6564 				    "allocate memory. \n");
6565 			} else if (rval == DEV_INFO_FAIL_GUID) {
6566 				mptsas_log(mpt, CE_NOTE,
6567 				    "mptsas_handle_topo_change: could not "
6568 				    "get SATA GUID for target %d. \n",
6569 				    topo_node->devhdl);
6570 			}
6571 			/*
6572 			 * If rval is DEV_INFO_PHYS_DISK or indicates failure
6573 			 * then there is nothing else to do, just leave.
6574 			 */
6575 			if (rval != DEV_INFO_SUCCESS) {
6576 				return;
6577 			}
6578 		}
6579 
6580 		ASSERT(ptgt->m_devhdl == topo_node->devhdl);
6581 
6582 		mutex_exit(&mpt->m_mutex);
6583 		flags = topo_node->flags;
6584 
6585 		if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
6586 			phymask = ptgt->m_addr.mta_phymask;
6587 			phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6588 			(void) sprintf(phy_mask_name, "%x", phymask);
6589 			parent = scsi_hba_iport_find(mpt->m_dip,
6590 			    phy_mask_name);
6591 			kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6592 			if (parent == NULL) {
6593 				mptsas_log(mpt, CE_WARN, "Failed to find a "
6594 				    "iport for PD, should not happen!");
6595 				mutex_enter(&mpt->m_mutex);
6596 				break;
6597 			}
6598 		}
6599 
6600 		if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6601 			ndi_devi_enter(parent, &circ1);
6602 			(void) mptsas_config_raid(parent, topo_node->devhdl,
6603 			    &lundip);
6604 			ndi_devi_exit(parent, circ1);
6605 		} else {
6606 			/*
6607 			 * hold nexus for bus configure
6608 			 */
6609 			ndi_devi_enter(scsi_vhci_dip, &circ);
6610 			ndi_devi_enter(parent, &circ1);
6611 			rval = mptsas_config_target(parent, ptgt);
6612 			/*
6613 			 * release nexus for bus configure
6614 			 */
6615 			ndi_devi_exit(parent, circ1);
6616 			ndi_devi_exit(scsi_vhci_dip, circ);
6617 
6618 			/*
6619 			 * If this is a SATA device, make sure that the
6620 			 * bridge-port (the SAS WWN that the SATA device is
6621 			 * plugged into) is updated. This may change if a SATA
6622 			 * device changes which bay, and therefore phy, it is
6623 			 * plugged into.
6624 			 */
6625 			if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) {
6626 				if (!mptsas_update_sata_bridge(mpt, parent,
6627 				    ptgt)) {
6628 					mutex_enter(&mpt->m_mutex);
6629 					return;
6630 				}
6631 			}
6632 
6633 			/*
6634 			 * Add parent's props for SMHBA support
6635 			 */
6636 			if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6637 				bzero(attached_wwnstr,
6638 				    sizeof (attached_wwnstr));
6639 				(void) sprintf(attached_wwnstr, "w%016"PRIx64,
6640 				    ptgt->m_addr.mta_wwn);
6641 				if (ddi_prop_update_string(DDI_DEV_T_NONE,
6642 				    parent,
6643 				    SCSI_ADDR_PROP_ATTACHED_PORT,
6644 				    attached_wwnstr)
6645 				    != DDI_PROP_SUCCESS) {
6646 					(void) ddi_prop_remove(DDI_DEV_T_NONE,
6647 					    parent,
6648 					    SCSI_ADDR_PROP_ATTACHED_PORT);
6649 					mptsas_log(mpt, CE_WARN, "Failed to"
6650 					    "attached-port props");
6651 					mutex_enter(&mpt->m_mutex);
6652 					return;
6653 				}
6654 				if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6655 				    MPTSAS_NUM_PHYS, 1) !=
6656 				    DDI_PROP_SUCCESS) {
6657 					(void) ddi_prop_remove(DDI_DEV_T_NONE,
6658 					    parent, MPTSAS_NUM_PHYS);
6659 					mptsas_log(mpt, CE_WARN, "Failed to"
6660 					    " create num-phys props");
6661 					mutex_enter(&mpt->m_mutex);
6662 					return;
6663 				}
6664 
6665 				/*
6666 				 * Update PHY info for smhba
6667 				 */
6668 				mutex_enter(&mpt->m_mutex);
6669 				if (mptsas_smhba_phy_init(mpt)) {
6670 					mptsas_log(mpt, CE_WARN, "mptsas phy"
6671 					    " update failed");
6672 					return;
6673 				}
6674 				mutex_exit(&mpt->m_mutex);
6675 
6676 				/*
6677 				 * topo_node->un.physport is really the PHY#
6678 				 * for direct attached devices
6679 				 */
6680 				mptsas_smhba_set_one_phy_props(mpt, parent,
6681 				    topo_node->un.physport, &attached_devhdl);
6682 
6683 				if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6684 				    MPTSAS_VIRTUAL_PORT, 0) !=
6685 				    DDI_PROP_SUCCESS) {
6686 					(void) ddi_prop_remove(DDI_DEV_T_NONE,
6687 					    parent, MPTSAS_VIRTUAL_PORT);
6688 					mptsas_log(mpt, CE_WARN,
6689 					    "mptsas virtual-port"
6690 					    "port prop update failed");
6691 					mutex_enter(&mpt->m_mutex);
6692 					return;
6693 				}
6694 			}
6695 		}
6696 		mutex_enter(&mpt->m_mutex);
6697 
6698 		NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
6699 		    "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6700 		    ptgt->m_addr.mta_phymask));
6701 		break;
6702 	}
6703 	case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6704 	{
6705 		devhdl = topo_node->devhdl;
6706 		ptgt = refhash_linear_search(mpt->m_targets,
6707 		    mptsas_target_eval_devhdl, &devhdl);
6708 		if (ptgt == NULL)
6709 			break;
6710 
6711 		sas_wwn = ptgt->m_addr.mta_wwn;
6712 		phy = ptgt->m_phynum;
6713 
6714 		addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
6715 
6716 		if (sas_wwn) {
6717 			(void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6718 		} else {
6719 			(void) sprintf(addr, "p%x", phy);
6720 		}
6721 		ASSERT(ptgt->m_devhdl == devhdl);
6722 
6723 		if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6724 		    (topo_node->flags ==
6725 		    MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6726 			/*
6727 			 * Get latest RAID info if RAID volume status changes
6728 			 * or Phys Disk status changes
6729 			 */
6730 			(void) mptsas_get_raid_info(mpt);
6731 		}
6732 		/*
6733 		 * Abort all outstanding command on the device
6734 		 */
6735 		rval = mptsas_do_scsi_reset(mpt, devhdl);
6736 		if (rval) {
6737 			NDBG20(("mptsas%d handle_topo_change to reset target "
6738 			    "before offline devhdl:%x, phymask:%x, rval:%x",
6739 			    mpt->m_instance, ptgt->m_devhdl,
6740 			    ptgt->m_addr.mta_phymask, rval));
6741 		}
6742 
6743 		mutex_exit(&mpt->m_mutex);
6744 
6745 		ndi_devi_enter(scsi_vhci_dip, &circ);
6746 		ndi_devi_enter(parent, &circ1);
6747 		rval = mptsas_offline_target(parent, addr);
6748 		ndi_devi_exit(parent, circ1);
6749 		ndi_devi_exit(scsi_vhci_dip, circ);
6750 		NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6751 		    "phymask:%x, rval:%x", mpt->m_instance,
6752 		    ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval));
6753 
6754 		kmem_free(addr, SCSI_MAXNAMELEN);
6755 
6756 		/*
6757 		 * Clear parent's props for SMHBA support
6758 		 */
6759 		flags = topo_node->flags;
6760 		if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6761 			bzero(attached_wwnstr, sizeof (attached_wwnstr));
6762 			if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6763 			    SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6764 			    DDI_PROP_SUCCESS) {
6765 				(void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6766 				    SCSI_ADDR_PROP_ATTACHED_PORT);
6767 				mptsas_log(mpt, CE_WARN, "mptsas attached port "
6768 				    "prop update failed");
6769 				mutex_enter(&mpt->m_mutex);
6770 				break;
6771 			}
6772 			if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6773 			    MPTSAS_NUM_PHYS, 0) !=
6774 			    DDI_PROP_SUCCESS) {
6775 				(void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6776 				    MPTSAS_NUM_PHYS);
6777 				mptsas_log(mpt, CE_WARN, "mptsas num phys "
6778 				    "prop update failed");
6779 				mutex_enter(&mpt->m_mutex);
6780 				break;
6781 			}
6782 			if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6783 			    MPTSAS_VIRTUAL_PORT, 1) !=
6784 			    DDI_PROP_SUCCESS) {
6785 				(void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6786 				    MPTSAS_VIRTUAL_PORT);
6787 				mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6788 				    "prop update failed");
6789 				mutex_enter(&mpt->m_mutex);
6790 				break;
6791 			}
6792 		}
6793 
6794 		mutex_enter(&mpt->m_mutex);
6795 		if (rval == DDI_SUCCESS) {
6796 			refhash_remove(mpt->m_targets, ptgt);
6797 			ptgt = NULL;
6798 		} else {
6799 			/*
6800 			 * clean DR_INTRANSITION flag to allow I/O down to
6801 			 * PHCI driver since failover finished.
6802 			 * Invalidate the devhdl
6803 			 */
6804 			ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6805 			ptgt->m_tgt_unconfigured = 0;
6806 			mutex_enter(&mpt->m_tx_waitq_mutex);
6807 			ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6808 			mutex_exit(&mpt->m_tx_waitq_mutex);
6809 		}
6810 
6811 		/*
6812 		 * Send SAS IO Unit Control to free the dev handle
6813 		 */
6814 		if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6815 		    (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6816 			rval = mptsas_free_devhdl(mpt, devhdl);
6817 
6818 			NDBG20(("mptsas%d handle_topo_change to remove "
6819 			    "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6820 			    rval));
6821 		}
6822 
6823 		break;
6824 	}
6825 	case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6826 	{
6827 		devhdl = topo_node->devhdl;
6828 		/*
6829 		 * If this is the remove handle event, do a reset first.
6830 		 */
6831 		if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6832 			rval = mptsas_do_scsi_reset(mpt, devhdl);
6833 			if (rval) {
6834 				NDBG20(("mpt%d reset target before remove "
6835 				    "devhdl:%x, rval:%x", mpt->m_instance,
6836 				    devhdl, rval));
6837 			}
6838 		}
6839 
6840 		/*
6841 		 * Send SAS IO Unit Control to free the dev handle
6842 		 */
6843 		rval = mptsas_free_devhdl(mpt, devhdl);
6844 		NDBG20(("mptsas%d handle_topo_change to remove "
6845 		    "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6846 		    rval));
6847 		break;
6848 	}
6849 	case MPTSAS_DR_EVENT_RECONFIG_SMP:
6850 	{
6851 		mptsas_smp_t smp;
6852 		dev_info_t *smpdip;
6853 
6854 		devhdl = topo_node->devhdl;
6855 
6856 		page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6857 		    MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6858 		rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6859 		if (rval != DDI_SUCCESS) {
6860 			mptsas_log(mpt, CE_WARN, "failed to online smp, "
6861 			    "handle %x", devhdl);
6862 			return;
6863 		}
6864 
6865 		psmp = mptsas_smp_alloc(mpt, &smp);
6866 		if (psmp == NULL) {
6867 			return;
6868 		}
6869 
6870 		mutex_exit(&mpt->m_mutex);
6871 		ndi_devi_enter(parent, &circ1);
6872 		(void) mptsas_online_smp(parent, psmp, &smpdip);
6873 		ndi_devi_exit(parent, circ1);
6874 
6875 		mutex_enter(&mpt->m_mutex);
6876 		break;
6877 	}
6878 	case MPTSAS_DR_EVENT_OFFLINE_SMP:
6879 	{
6880 		devhdl = topo_node->devhdl;
6881 		uint32_t dev_info;
6882 
6883 		psmp = refhash_linear_search(mpt->m_smp_targets,
6884 		    mptsas_smp_eval_devhdl, &devhdl);
6885 		if (psmp == NULL)
6886 			break;
6887 		/*
6888 		 * The mptsas_smp_t data is released only if the dip is offlined
6889 		 * successfully.
6890 		 */
6891 		mutex_exit(&mpt->m_mutex);
6892 
6893 		ndi_devi_enter(parent, &circ1);
6894 		rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6895 		ndi_devi_exit(parent, circ1);
6896 
6897 		dev_info = psmp->m_deviceinfo;
6898 		if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6899 		    DEVINFO_DIRECT_ATTACHED) {
6900 			if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6901 			    MPTSAS_VIRTUAL_PORT, 1) !=
6902 			    DDI_PROP_SUCCESS) {
6903 				(void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6904 				    MPTSAS_VIRTUAL_PORT);
6905 				mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6906 				    "prop update failed");
6907 				mutex_enter(&mpt->m_mutex);
6908 				return;
6909 			}
6910 			/*
6911 			 * Check whether the smp connected to the iport,
6912 			 */
6913 			if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6914 			    MPTSAS_NUM_PHYS, 0) !=
6915 			    DDI_PROP_SUCCESS) {
6916 				(void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6917 				    MPTSAS_NUM_PHYS);
6918 				mptsas_log(mpt, CE_WARN, "mptsas num phys"
6919 				    "prop update failed");
6920 				mutex_enter(&mpt->m_mutex);
6921 				return;
6922 			}
6923 			/*
6924 			 * Clear parent's attached-port props
6925 			 */
6926 			bzero(attached_wwnstr, sizeof (attached_wwnstr));
6927 			if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6928 			    SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6929 			    DDI_PROP_SUCCESS) {
6930 				(void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6931 				    SCSI_ADDR_PROP_ATTACHED_PORT);
6932 				mptsas_log(mpt, CE_WARN, "mptsas attached port "
6933 				    "prop update failed");
6934 				mutex_enter(&mpt->m_mutex);
6935 				return;
6936 			}
6937 		}
6938 
6939 		mutex_enter(&mpt->m_mutex);
6940 		NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6941 		    "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6942 		if (rval == DDI_SUCCESS) {
6943 			refhash_remove(mpt->m_smp_targets, psmp);
6944 		} else {
6945 			psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6946 		}
6947 
6948 		bzero(attached_wwnstr, sizeof (attached_wwnstr));
6949 
6950 		break;
6951 	}
6952 	default:
6953 		return;
6954 	}
6955 }
6956 
6957 /*
6958  * Record the event if its type is enabled in mpt instance by ioctl.
6959  */
6960 static void
6961 mptsas_record_event(void *args)
6962 {
6963 	m_replyh_arg_t			*replyh_arg;
6964 	pMpi2EventNotificationReply_t	eventreply;
6965 	uint32_t			event, rfm;
6966 	mptsas_t			*mpt;
6967 	int				i, j;
6968 	uint16_t			event_data_len;
6969 	boolean_t			sendAEN = FALSE;
6970 
6971 	replyh_arg = (m_replyh_arg_t *)args;
6972 	rfm = replyh_arg->rfm;
6973 	mpt = replyh_arg->mpt;
6974 
6975 	eventreply = (pMpi2EventNotificationReply_t)
6976 	    (mpt->m_reply_frame + (rfm -
6977 	    (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
6978 	event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6979 
6980 
6981 	/*
6982 	 * Generate a system event to let anyone who cares know that a
6983 	 * LOG_ENTRY_ADDED event has occurred.  This is sent no matter what the
6984 	 * event mask is set to.
6985 	 */
6986 	if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6987 		sendAEN = TRUE;
6988 	}
6989 
6990 	/*
6991 	 * Record the event only if it is not masked.  Determine which dword
6992 	 * and bit of event mask to test.
6993 	 */
6994 	i = (uint8_t)(event / 32);
6995 	j = (uint8_t)(event % 32);
6996 	if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6997 		i = mpt->m_event_index;
6998 		mpt->m_events[i].Type = event;
6999 		mpt->m_events[i].Number = ++mpt->m_event_number;
7000 		bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
7001 		event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
7002 		    &eventreply->EventDataLength);
7003 
7004 		if (event_data_len > 0) {
7005 			/*
7006 			 * Limit data to size in m_event entry
7007 			 */
7008 			if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
7009 				event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
7010 			}
7011 			for (j = 0; j < event_data_len; j++) {
7012 				mpt->m_events[i].Data[j] =
7013 				    ddi_get32(mpt->m_acc_reply_frame_hdl,
7014 				    &(eventreply->EventData[j]));
7015 			}
7016 
7017 			/*
7018 			 * check for index wrap-around
7019 			 */
7020 			if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
7021 				i = 0;
7022 			}
7023 			mpt->m_event_index = (uint8_t)i;
7024 
7025 			/*
7026 			 * Set flag to send the event.
7027 			 */
7028 			sendAEN = TRUE;
7029 		}
7030 	}
7031 
7032 	/*
7033 	 * Generate a system event if flag is set to let anyone who cares know
7034 	 * that an event has occurred.
7035 	 */
7036 	if (sendAEN) {
7037 		(void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
7038 		    "SAS", NULL, NULL, DDI_NOSLEEP);
7039 	}
7040 }
7041 
7042 #define	SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
7043 /*
7044  * handle sync events from ioc in interrupt
7045  * return value:
7046  * DDI_SUCCESS: The event is handled by this func
7047  * DDI_FAILURE: Event is not handled
7048  */
7049 static int
7050 mptsas_handle_event_sync(void *args)
7051 {
7052 	m_replyh_arg_t			*replyh_arg;
7053 	pMpi2EventNotificationReply_t	eventreply;
7054 	uint32_t			event, rfm;
7055 	mptsas_t			*mpt;
7056 	uint_t				iocstatus;
7057 
7058 	replyh_arg = (m_replyh_arg_t *)args;
7059 	rfm = replyh_arg->rfm;
7060 	mpt = replyh_arg->mpt;
7061 
7062 	ASSERT(mutex_owned(&mpt->m_mutex));
7063 
7064 	eventreply = (pMpi2EventNotificationReply_t)
7065 	    (mpt->m_reply_frame + (rfm -
7066 	    (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
7067 	event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7068 
7069 	if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7070 	    &eventreply->IOCStatus)) != 0) {
7071 		if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7072 			mptsas_log(mpt, CE_WARN,
7073 			    "!mptsas_handle_event_sync: event 0x%x, "
7074 			    "IOCStatus=0x%x, "
7075 			    "IOCLogInfo=0x%x", event, iocstatus,
7076 			    ddi_get32(mpt->m_acc_reply_frame_hdl,
7077 			    &eventreply->IOCLogInfo));
7078 		} else {
7079 			mptsas_log(mpt, CE_WARN,
7080 			    "mptsas_handle_event_sync: event 0x%x, "
7081 			    "IOCStatus=0x%x, "
7082 			    "(IOCLogInfo=0x%x)", event, iocstatus,
7083 			    ddi_get32(mpt->m_acc_reply_frame_hdl,
7084 			    &eventreply->IOCLogInfo));
7085 		}
7086 	}
7087 
7088 	/*
7089 	 * figure out what kind of event we got and handle accordingly
7090 	 */
7091 	switch (event) {
7092 	case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7093 	{
7094 		pMpi2EventDataSasTopologyChangeList_t	sas_topo_change_list;
7095 		uint8_t				num_entries, expstatus, phy;
7096 		uint8_t				phystatus, physport, state, i;
7097 		uint8_t				start_phy_num, link_rate;
7098 		uint16_t			dev_handle, reason_code;
7099 		uint16_t			enc_handle, expd_handle;
7100 		char				string[80], curr[80], prev[80];
7101 		mptsas_topo_change_list_t	*topo_head = NULL;
7102 		mptsas_topo_change_list_t	*topo_tail = NULL;
7103 		mptsas_topo_change_list_t	*topo_node = NULL;
7104 		mptsas_target_t			*ptgt;
7105 		mptsas_smp_t			*psmp;
7106 		uint8_t				flags = 0, exp_flag;
7107 		smhba_info_t			*pSmhba = NULL;
7108 
7109 		NDBG20(("mptsas_handle_event_sync: SAS topology change"));
7110 
7111 		sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
7112 		    eventreply->EventData;
7113 
7114 		enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7115 		    &sas_topo_change_list->EnclosureHandle);
7116 		expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7117 		    &sas_topo_change_list->ExpanderDevHandle);
7118 		num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7119 		    &sas_topo_change_list->NumEntries);
7120 		start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7121 		    &sas_topo_change_list->StartPhyNum);
7122 		expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7123 		    &sas_topo_change_list->ExpStatus);
7124 		physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
7125 		    &sas_topo_change_list->PhysicalPort);
7126 
7127 		string[0] = 0;
7128 		if (expd_handle) {
7129 			flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
7130 			switch (expstatus) {
7131 			case MPI2_EVENT_SAS_TOPO_ES_ADDED:
7132 				(void) sprintf(string, " added");
7133 				/*
7134 				 * New expander device added
7135 				 */
7136 				mpt->m_port_chng = 1;
7137 				topo_node = kmem_zalloc(
7138 				    sizeof (mptsas_topo_change_list_t),
7139 				    KM_SLEEP);
7140 				topo_node->mpt = mpt;
7141 				topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
7142 				topo_node->un.physport = physport;
7143 				topo_node->devhdl = expd_handle;
7144 				topo_node->flags = flags;
7145 				topo_node->object = NULL;
7146 				if (topo_head == NULL) {
7147 					topo_head = topo_tail = topo_node;
7148 				} else {
7149 					topo_tail->next = topo_node;
7150 					topo_tail = topo_node;
7151 				}
7152 				break;
7153 			case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
7154 				(void) sprintf(string, " not responding, "
7155 				    "removed");
7156 				psmp = refhash_linear_search(mpt->m_smp_targets,
7157 				    mptsas_smp_eval_devhdl, &expd_handle);
7158 				if (psmp == NULL)
7159 					break;
7160 
7161 				topo_node = kmem_zalloc(
7162 				    sizeof (mptsas_topo_change_list_t),
7163 				    KM_SLEEP);
7164 				topo_node->mpt = mpt;
7165 				topo_node->un.phymask =
7166 				    psmp->m_addr.mta_phymask;
7167 				topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
7168 				topo_node->devhdl = expd_handle;
7169 				topo_node->flags = flags;
7170 				topo_node->object = NULL;
7171 				if (topo_head == NULL) {
7172 					topo_head = topo_tail = topo_node;
7173 				} else {
7174 					topo_tail->next = topo_node;
7175 					topo_tail = topo_node;
7176 				}
7177 				break;
7178 			case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
7179 				break;
7180 			case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
7181 				(void) sprintf(string, " not responding, "
7182 				    "delaying removal");
7183 				break;
7184 			default:
7185 				break;
7186 			}
7187 		} else {
7188 			flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
7189 		}
7190 
7191 		NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
7192 		    enc_handle, expd_handle, string));
7193 		for (i = 0; i < num_entries; i++) {
7194 			phy = i + start_phy_num;
7195 			phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7196 			    &sas_topo_change_list->PHY[i].PhyStatus);
7197 			dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7198 			    &sas_topo_change_list->PHY[i].AttachedDevHandle);
7199 			reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
7200 			/*
7201 			 * Filter out processing of Phy Vacant Status unless
7202 			 * the reason code is "Not Responding".  Process all
7203 			 * other combinations of Phy Status and Reason Codes.
7204 			 */
7205 			if ((phystatus &
7206 			    MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
7207 			    (reason_code !=
7208 			    MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
7209 				continue;
7210 			}
7211 			curr[0] = 0;
7212 			prev[0] = 0;
7213 			string[0] = 0;
7214 			switch (reason_code) {
7215 			case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
7216 			{
7217 				NDBG20(("mptsas%d phy %d physical_port %d "
7218 				    "dev_handle %d added", mpt->m_instance, phy,
7219 				    physport, dev_handle));
7220 				link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7221 				    &sas_topo_change_list->PHY[i].LinkRate);
7222 				state = (link_rate &
7223 				    MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7224 				    MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7225 				switch (state) {
7226 				case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7227 					(void) sprintf(curr, "is disabled");
7228 					break;
7229 				case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7230 					(void) sprintf(curr, "is offline, "
7231 					    "failed speed negotiation");
7232 					break;
7233 				case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7234 					(void) sprintf(curr, "SATA OOB "
7235 					    "complete");
7236 					break;
7237 				case SMP_RESET_IN_PROGRESS:
7238 					(void) sprintf(curr, "SMP reset in "
7239 					    "progress");
7240 					break;
7241 				case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7242 					(void) sprintf(curr, "is online at "
7243 					    "1.5 Gbps");
7244 					break;
7245 				case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7246 					(void) sprintf(curr, "is online at 3.0 "
7247 					    "Gbps");
7248 					break;
7249 				case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7250 					(void) sprintf(curr, "is online at 6.0 "
7251 					    "Gbps");
7252 					break;
7253 				case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7254 					(void) sprintf(curr,
7255 					    "is online at 12.0 Gbps");
7256 					break;
7257 				default:
7258 					(void) sprintf(curr, "state is "
7259 					    "unknown");
7260 					break;
7261 				}
7262 				/*
7263 				 * New target device added into the system.
7264 				 * Set association flag according to if an
7265 				 * expander is used or not.
7266 				 */
7267 				exp_flag =
7268 				    MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7269 				if (flags ==
7270 				    MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7271 					flags = exp_flag;
7272 				}
7273 				topo_node = kmem_zalloc(
7274 				    sizeof (mptsas_topo_change_list_t),
7275 				    KM_SLEEP);
7276 				topo_node->mpt = mpt;
7277 				topo_node->event =
7278 				    MPTSAS_DR_EVENT_RECONFIG_TARGET;
7279 				if (expd_handle == 0) {
7280 					/*
7281 					 * Per MPI 2, if expander dev handle
7282 					 * is 0, it's a directly attached
7283 					 * device. So driver use PHY to decide
7284 					 * which iport is associated
7285 					 */
7286 					physport = phy;
7287 					mpt->m_port_chng = 1;
7288 				}
7289 				topo_node->un.physport = physport;
7290 				topo_node->devhdl = dev_handle;
7291 				topo_node->flags = flags;
7292 				topo_node->object = NULL;
7293 				if (topo_head == NULL) {
7294 					topo_head = topo_tail = topo_node;
7295 				} else {
7296 					topo_tail->next = topo_node;
7297 					topo_tail = topo_node;
7298 				}
7299 				break;
7300 			}
7301 			case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
7302 			{
7303 				NDBG20(("mptsas%d phy %d physical_port %d "
7304 				    "dev_handle %d removed", mpt->m_instance,
7305 				    phy, physport, dev_handle));
7306 				/*
7307 				 * Set association flag according to if an
7308 				 * expander is used or not.
7309 				 */
7310 				exp_flag =
7311 				    MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7312 				if (flags ==
7313 				    MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7314 					flags = exp_flag;
7315 				}
7316 				/*
7317 				 * Target device is removed from the system
7318 				 * Before the device is really offline from
7319 				 * from system.
7320 				 */
7321 				ptgt = refhash_linear_search(mpt->m_targets,
7322 				    mptsas_target_eval_devhdl, &dev_handle);
7323 				/*
7324 				 * If ptgt is NULL here, it means that the
7325 				 * DevHandle is not in the hash table.  This is
7326 				 * reasonable sometimes.  For example, if a
7327 				 * disk was pulled, then added, then pulled
7328 				 * again, the disk will not have been put into
7329 				 * the hash table because the add event will
7330 				 * have an invalid phymask.  BUT, this does not
7331 				 * mean that the DevHandle is invalid.  The
7332 				 * controller will still have a valid DevHandle
7333 				 * that must be removed.  To do this, use the
7334 				 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
7335 				 */
7336 				if (ptgt == NULL) {
7337 					topo_node = kmem_zalloc(
7338 					    sizeof (mptsas_topo_change_list_t),
7339 					    KM_SLEEP);
7340 					topo_node->mpt = mpt;
7341 					topo_node->un.phymask = 0;
7342 					topo_node->event =
7343 					    MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
7344 					topo_node->devhdl = dev_handle;
7345 					topo_node->flags = flags;
7346 					topo_node->object = NULL;
7347 					if (topo_head == NULL) {
7348 						topo_head = topo_tail =
7349 						    topo_node;
7350 					} else {
7351 						topo_tail->next = topo_node;
7352 						topo_tail = topo_node;
7353 					}
7354 					break;
7355 				}
7356 
7357 				/*
7358 				 * Update DR flag immediately avoid I/O failure
7359 				 * before failover finish. Pay attention to the
7360 				 * mutex protect, we need grab m_tx_waitq_mutex
7361 				 * during set m_dr_flag because we won't add
7362 				 * the following command into waitq, instead,
7363 				 * we need return TRAN_BUSY in the tran_start
7364 				 * context.
7365 				 */
7366 				mutex_enter(&mpt->m_tx_waitq_mutex);
7367 				ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7368 				mutex_exit(&mpt->m_tx_waitq_mutex);
7369 
7370 				topo_node = kmem_zalloc(
7371 				    sizeof (mptsas_topo_change_list_t),
7372 				    KM_SLEEP);
7373 				topo_node->mpt = mpt;
7374 				topo_node->un.phymask =
7375 				    ptgt->m_addr.mta_phymask;
7376 				topo_node->event =
7377 				    MPTSAS_DR_EVENT_OFFLINE_TARGET;
7378 				topo_node->devhdl = dev_handle;
7379 				topo_node->flags = flags;
7380 				topo_node->object = NULL;
7381 				if (topo_head == NULL) {
7382 					topo_head = topo_tail = topo_node;
7383 				} else {
7384 					topo_tail->next = topo_node;
7385 					topo_tail = topo_node;
7386 				}
7387 				break;
7388 			}
7389 			case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
7390 				link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7391 				    &sas_topo_change_list->PHY[i].LinkRate);
7392 				state = (link_rate &
7393 				    MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7394 				    MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7395 				pSmhba = &mpt->m_phy_info[i].smhba_info;
7396 				pSmhba->negotiated_link_rate = state;
7397 				switch (state) {
7398 				case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7399 					(void) sprintf(curr, "is disabled");
7400 					mptsas_smhba_log_sysevent(mpt,
7401 					    ESC_SAS_PHY_EVENT,
7402 					    SAS_PHY_REMOVE,
7403 					    &mpt->m_phy_info[i].smhba_info);
7404 					mpt->m_phy_info[i].smhba_info.
7405 					    negotiated_link_rate
7406 					    = 0x1;
7407 					break;
7408 				case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7409 					(void) sprintf(curr, "is offline, "
7410 					    "failed speed negotiation");
7411 					mptsas_smhba_log_sysevent(mpt,
7412 					    ESC_SAS_PHY_EVENT,
7413 					    SAS_PHY_OFFLINE,
7414 					    &mpt->m_phy_info[i].smhba_info);
7415 					break;
7416 				case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7417 					(void) sprintf(curr, "SATA OOB "
7418 					    "complete");
7419 					break;
7420 				case SMP_RESET_IN_PROGRESS:
7421 					(void) sprintf(curr, "SMP reset in "
7422 					    "progress");
7423 					break;
7424 				case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7425 					(void) sprintf(curr, "is online at "
7426 					    "1.5 Gbps");
7427 					if ((expd_handle == 0) &&
7428 					    (enc_handle == 1)) {
7429 						mpt->m_port_chng = 1;
7430 					}
7431 					mptsas_smhba_log_sysevent(mpt,
7432 					    ESC_SAS_PHY_EVENT,
7433 					    SAS_PHY_ONLINE,
7434 					    &mpt->m_phy_info[i].smhba_info);
7435 					break;
7436 				case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7437 					(void) sprintf(curr, "is online at 3.0 "
7438 					    "Gbps");
7439 					if ((expd_handle == 0) &&
7440 					    (enc_handle == 1)) {
7441 						mpt->m_port_chng = 1;
7442 					}
7443 					mptsas_smhba_log_sysevent(mpt,
7444 					    ESC_SAS_PHY_EVENT,
7445 					    SAS_PHY_ONLINE,
7446 					    &mpt->m_phy_info[i].smhba_info);
7447 					break;
7448 				case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7449 					(void) sprintf(curr, "is online at "
7450 					    "6.0 Gbps");
7451 					if ((expd_handle == 0) &&
7452 					    (enc_handle == 1)) {
7453 						mpt->m_port_chng = 1;
7454 					}
7455 					mptsas_smhba_log_sysevent(mpt,
7456 					    ESC_SAS_PHY_EVENT,
7457 					    SAS_PHY_ONLINE,
7458 					    &mpt->m_phy_info[i].smhba_info);
7459 					break;
7460 				case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7461 					(void) sprintf(curr, "is online at "
7462 					    "12.0 Gbps");
7463 					if ((expd_handle == 0) &&
7464 					    (enc_handle == 1)) {
7465 						mpt->m_port_chng = 1;
7466 					}
7467 					mptsas_smhba_log_sysevent(mpt,
7468 					    ESC_SAS_PHY_EVENT,
7469 					    SAS_PHY_ONLINE,
7470 					    &mpt->m_phy_info[i].smhba_info);
7471 					break;
7472 				default:
7473 					(void) sprintf(curr, "state is "
7474 					    "unknown");
7475 					break;
7476 				}
7477 
7478 				state = (link_rate &
7479 				    MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
7480 				    MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
7481 				switch (state) {
7482 				case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7483 					(void) sprintf(prev, ", was disabled");
7484 					break;
7485 				case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7486 					(void) sprintf(prev, ", was offline, "
7487 					    "failed speed negotiation");
7488 					break;
7489 				case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7490 					(void) sprintf(prev, ", was SATA OOB "
7491 					    "complete");
7492 					break;
7493 				case SMP_RESET_IN_PROGRESS:
7494 					(void) sprintf(prev, ", was SMP reset "
7495 					    "in progress");
7496 					break;
7497 				case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7498 					(void) sprintf(prev, ", was online at "
7499 					    "1.5 Gbps");
7500 					break;
7501 				case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7502 					(void) sprintf(prev, ", was online at "
7503 					    "3.0 Gbps");
7504 					break;
7505 				case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7506 					(void) sprintf(prev, ", was online at "
7507 					    "6.0 Gbps");
7508 					break;
7509 				case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7510 					(void) sprintf(prev, ", was online at "
7511 					    "12.0 Gbps");
7512 					break;
7513 				default:
7514 				break;
7515 				}
7516 				(void) sprintf(&string[strlen(string)], "link "
7517 				    "changed, ");
7518 				break;
7519 			case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
7520 				continue;
7521 			case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
7522 				(void) sprintf(&string[strlen(string)],
7523 				    "target not responding, delaying "
7524 				    "removal");
7525 				break;
7526 			}
7527 			NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
7528 			    mpt->m_instance, phy, dev_handle, string, curr,
7529 			    prev));
7530 		}
7531 		if (topo_head != NULL) {
7532 			/*
7533 			 * Launch DR taskq to handle topology change
7534 			 */
7535 			if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7536 			    mptsas_handle_dr, (void *)topo_head,
7537 			    DDI_NOSLEEP)) != DDI_SUCCESS) {
7538 				while (topo_head != NULL) {
7539 					topo_node = topo_head;
7540 					topo_head = topo_head->next;
7541 					kmem_free(topo_node,
7542 					    sizeof (mptsas_topo_change_list_t));
7543 				}
7544 				mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7545 				    "for handle SAS DR event failed. \n");
7546 			}
7547 		}
7548 		break;
7549 	}
7550 	case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7551 	{
7552 		Mpi2EventDataIrConfigChangeList_t	*irChangeList;
7553 		mptsas_topo_change_list_t		*topo_head = NULL;
7554 		mptsas_topo_change_list_t		*topo_tail = NULL;
7555 		mptsas_topo_change_list_t		*topo_node = NULL;
7556 		mptsas_target_t				*ptgt;
7557 		uint8_t					num_entries, i, reason;
7558 		uint16_t				volhandle, diskhandle;
7559 
7560 		irChangeList = (pMpi2EventDataIrConfigChangeList_t)
7561 		    eventreply->EventData;
7562 		num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7563 		    &irChangeList->NumElements);
7564 
7565 		NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
7566 		    mpt->m_instance));
7567 
7568 		for (i = 0; i < num_entries; i++) {
7569 			reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7570 			    &irChangeList->ConfigElement[i].ReasonCode);
7571 			volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7572 			    &irChangeList->ConfigElement[i].VolDevHandle);
7573 			diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7574 			    &irChangeList->ConfigElement[i].PhysDiskDevHandle);
7575 
7576 			switch (reason) {
7577 			case MPI2_EVENT_IR_CHANGE_RC_ADDED:
7578 			case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
7579 			{
7580 				NDBG20(("mptsas %d volume added\n",
7581 				    mpt->m_instance));
7582 
7583 				topo_node = kmem_zalloc(
7584 				    sizeof (mptsas_topo_change_list_t),
7585 				    KM_SLEEP);
7586 
7587 				topo_node->mpt = mpt;
7588 				topo_node->event =
7589 				    MPTSAS_DR_EVENT_RECONFIG_TARGET;
7590 				topo_node->un.physport = 0xff;
7591 				topo_node->devhdl = volhandle;
7592 				topo_node->flags =
7593 				    MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7594 				topo_node->object = NULL;
7595 				if (topo_head == NULL) {
7596 					topo_head = topo_tail = topo_node;
7597 				} else {
7598 					topo_tail->next = topo_node;
7599 					topo_tail = topo_node;
7600 				}
7601 				break;
7602 			}
7603 			case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
7604 			case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
7605 			{
7606 				NDBG20(("mptsas %d volume deleted\n",
7607 				    mpt->m_instance));
7608 				ptgt = refhash_linear_search(mpt->m_targets,
7609 				    mptsas_target_eval_devhdl, &volhandle);
7610 				if (ptgt == NULL)
7611 					break;
7612 
7613 				/*
7614 				 * Clear any flags related to volume
7615 				 */
7616 				(void) mptsas_delete_volume(mpt, volhandle);
7617 
7618 				/*
7619 				 * Update DR flag immediately avoid I/O failure
7620 				 */
7621 				mutex_enter(&mpt->m_tx_waitq_mutex);
7622 				ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7623 				mutex_exit(&mpt->m_tx_waitq_mutex);
7624 
7625 				topo_node = kmem_zalloc(
7626 				    sizeof (mptsas_topo_change_list_t),
7627 				    KM_SLEEP);
7628 				topo_node->mpt = mpt;
7629 				topo_node->un.phymask =
7630 				    ptgt->m_addr.mta_phymask;
7631 				topo_node->event =
7632 				    MPTSAS_DR_EVENT_OFFLINE_TARGET;
7633 				topo_node->devhdl = volhandle;
7634 				topo_node->flags =
7635 				    MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7636 				topo_node->object = (void *)ptgt;
7637 				if (topo_head == NULL) {
7638 					topo_head = topo_tail = topo_node;
7639 				} else {
7640 					topo_tail->next = topo_node;
7641 					topo_tail = topo_node;
7642 				}
7643 				break;
7644 			}
7645 			case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
7646 			case MPI2_EVENT_IR_CHANGE_RC_HIDE:
7647 			{
7648 				ptgt = refhash_linear_search(mpt->m_targets,
7649 				    mptsas_target_eval_devhdl, &diskhandle);
7650 				if (ptgt == NULL)
7651 					break;
7652 
7653 				/*
7654 				 * Update DR flag immediately avoid I/O failure
7655 				 */
7656 				mutex_enter(&mpt->m_tx_waitq_mutex);
7657 				ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7658 				mutex_exit(&mpt->m_tx_waitq_mutex);
7659 
7660 				topo_node = kmem_zalloc(
7661 				    sizeof (mptsas_topo_change_list_t),
7662 				    KM_SLEEP);
7663 				topo_node->mpt = mpt;
7664 				topo_node->un.phymask =
7665 				    ptgt->m_addr.mta_phymask;
7666 				topo_node->event =
7667 				    MPTSAS_DR_EVENT_OFFLINE_TARGET;
7668 				topo_node->devhdl = diskhandle;
7669 				topo_node->flags =
7670 				    MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7671 				topo_node->object = (void *)ptgt;
7672 				if (topo_head == NULL) {
7673 					topo_head = topo_tail = topo_node;
7674 				} else {
7675 					topo_tail->next = topo_node;
7676 					topo_tail = topo_node;
7677 				}
7678 				break;
7679 			}
7680 			case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
7681 			case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
7682 			{
7683 				/*
7684 				 * The physical drive is released by a IR
7685 				 * volume. But we cannot get the the physport
7686 				 * or phynum from the event data, so we only
7687 				 * can get the physport/phynum after SAS
7688 				 * Device Page0 request for the devhdl.
7689 				 */
7690 				topo_node = kmem_zalloc(
7691 				    sizeof (mptsas_topo_change_list_t),
7692 				    KM_SLEEP);
7693 				topo_node->mpt = mpt;
7694 				topo_node->un.phymask = 0;
7695 				topo_node->event =
7696 				    MPTSAS_DR_EVENT_RECONFIG_TARGET;
7697 				topo_node->devhdl = diskhandle;
7698 				topo_node->flags =
7699 				    MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7700 				topo_node->object = NULL;
7701 				mpt->m_port_chng = 1;
7702 				if (topo_head == NULL) {
7703 					topo_head = topo_tail = topo_node;
7704 				} else {
7705 					topo_tail->next = topo_node;
7706 					topo_tail = topo_node;
7707 				}
7708 				break;
7709 			}
7710 			default:
7711 				break;
7712 			}
7713 		}
7714 
7715 		if (topo_head != NULL) {
7716 			/*
7717 			 * Launch DR taskq to handle topology change
7718 			 */
7719 			if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7720 			    mptsas_handle_dr, (void *)topo_head,
7721 			    DDI_NOSLEEP)) != DDI_SUCCESS) {
7722 				while (topo_head != NULL) {
7723 					topo_node = topo_head;
7724 					topo_head = topo_head->next;
7725 					kmem_free(topo_node,
7726 					    sizeof (mptsas_topo_change_list_t));
7727 				}
7728 				mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7729 				    "for handle SAS DR event failed. \n");
7730 			}
7731 		}
7732 		break;
7733 	}
7734 	default:
7735 		return (DDI_FAILURE);
7736 	}
7737 
7738 	return (DDI_SUCCESS);
7739 }
7740 
7741 /*
7742  * handle events from ioc
7743  */
7744 static void
7745 mptsas_handle_event(void *args)
7746 {
7747 	m_replyh_arg_t			*replyh_arg;
7748 	pMpi2EventNotificationReply_t	eventreply;
7749 	uint32_t			event, iocloginfo, rfm;
7750 	uint32_t			status;
7751 	uint8_t				port;
7752 	mptsas_t			*mpt;
7753 	uint_t				iocstatus;
7754 
7755 	replyh_arg = (m_replyh_arg_t *)args;
7756 	rfm = replyh_arg->rfm;
7757 	mpt = replyh_arg->mpt;
7758 
7759 	mutex_enter(&mpt->m_mutex);
7760 	/*
7761 	 * If HBA is being reset, drop incoming event.
7762 	 */
7763 	if (mpt->m_in_reset) {
7764 		NDBG20(("dropping event received prior to reset"));
7765 		mutex_exit(&mpt->m_mutex);
7766 		return;
7767 	}
7768 
7769 	eventreply = (pMpi2EventNotificationReply_t)
7770 	    (mpt->m_reply_frame + (rfm -
7771 	    (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
7772 	event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7773 
7774 	if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7775 	    &eventreply->IOCStatus)) != 0) {
7776 		if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7777 			mptsas_log(mpt, CE_WARN,
7778 			    "!mptsas_handle_event: IOCStatus=0x%x, "
7779 			    "IOCLogInfo=0x%x", iocstatus,
7780 			    ddi_get32(mpt->m_acc_reply_frame_hdl,
7781 			    &eventreply->IOCLogInfo));
7782 		} else {
7783 			mptsas_log(mpt, CE_WARN,
7784 			    "mptsas_handle_event: IOCStatus=0x%x, "
7785 			    "IOCLogInfo=0x%x", iocstatus,
7786 			    ddi_get32(mpt->m_acc_reply_frame_hdl,
7787 			    &eventreply->IOCLogInfo));
7788 		}
7789 	}
7790 
7791 	/*
7792 	 * figure out what kind of event we got and handle accordingly
7793 	 */
7794 	switch (event) {
7795 	case MPI2_EVENT_LOG_ENTRY_ADDED:
7796 		break;
7797 	case MPI2_EVENT_LOG_DATA:
7798 		iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7799 		    &eventreply->IOCLogInfo);
7800 		NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7801 		    iocloginfo));
7802 		break;
7803 	case MPI2_EVENT_STATE_CHANGE:
7804 		NDBG20(("mptsas%d state change.", mpt->m_instance));
7805 		break;
7806 	case MPI2_EVENT_HARD_RESET_RECEIVED:
7807 		NDBG20(("mptsas%d event change.", mpt->m_instance));
7808 		break;
7809 	case MPI2_EVENT_SAS_DISCOVERY:
7810 	{
7811 		MPI2_EVENT_DATA_SAS_DISCOVERY	*sasdiscovery;
7812 		char				string[80];
7813 		uint8_t				rc;
7814 
7815 		sasdiscovery =
7816 		    (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7817 
7818 		rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7819 		    &sasdiscovery->ReasonCode);
7820 		port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7821 		    &sasdiscovery->PhysicalPort);
7822 		status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7823 		    &sasdiscovery->DiscoveryStatus);
7824 
7825 		string[0] = 0;
7826 		switch (rc) {
7827 		case MPI2_EVENT_SAS_DISC_RC_STARTED:
7828 			(void) sprintf(string, "STARTING");
7829 			break;
7830 		case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7831 			(void) sprintf(string, "COMPLETED");
7832 			break;
7833 		default:
7834 			(void) sprintf(string, "UNKNOWN");
7835 			break;
7836 		}
7837 
7838 		NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7839 		    port, status));
7840 
7841 		break;
7842 	}
7843 	case MPI2_EVENT_EVENT_CHANGE:
7844 		NDBG20(("mptsas%d event change.", mpt->m_instance));
7845 		break;
7846 	case MPI2_EVENT_TASK_SET_FULL:
7847 	{
7848 		pMpi2EventDataTaskSetFull_t	taskfull;
7849 
7850 		taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7851 
7852 		NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7853 		    mpt->m_instance,  ddi_get16(mpt->m_acc_reply_frame_hdl,
7854 		    &taskfull->CurrentDepth)));
7855 		break;
7856 	}
7857 	case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7858 	{
7859 		/*
7860 		 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7861 		 * in mptsas_handle_event_sync() of interrupt context
7862 		 */
7863 		break;
7864 	}
7865 	case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7866 	{
7867 		pMpi2EventDataSasEnclDevStatusChange_t	encstatus;
7868 		uint8_t					rc;
7869 		uint16_t				enchdl;
7870 		char					string[80];
7871 		mptsas_enclosure_t			*mep;
7872 
7873 		encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7874 		    eventreply->EventData;
7875 
7876 		rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7877 		    &encstatus->ReasonCode);
7878 		enchdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7879 		    &encstatus->EnclosureHandle);
7880 
7881 		switch (rc) {
7882 		case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7883 			(void) sprintf(string, "added");
7884 			break;
7885 		case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7886 			mep = mptsas_enc_lookup(mpt, enchdl);
7887 			if (mep != NULL) {
7888 				list_remove(&mpt->m_enclosures, mep);
7889 				mptsas_enc_free(mep);
7890 				mep = NULL;
7891 			}
7892 			(void) sprintf(string, ", not responding");
7893 			break;
7894 		default:
7895 		break;
7896 		}
7897 		NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure "
7898 		    "%x%s\n", mpt->m_instance,
7899 		    ddi_get16(mpt->m_acc_reply_frame_hdl,
7900 		    &encstatus->EnclosureHandle), string));
7901 
7902 		/*
7903 		 * No matter what has happened, update all of our device state
7904 		 * for enclosures, by retriggering an evaluation.
7905 		 */
7906 		mpt->m_done_traverse_enc = 0;
7907 		mptsas_update_hashtab(mpt);
7908 		break;
7909 	}
7910 
7911 	/*
7912 	 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7913 	 * mptsas_handle_event_sync,in here just send ack message.
7914 	 */
7915 	case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7916 	{
7917 		pMpi2EventDataSasDeviceStatusChange_t	statuschange;
7918 		uint8_t					rc;
7919 		uint16_t				devhdl;
7920 		uint64_t				wwn = 0;
7921 		uint32_t				wwn_lo, wwn_hi;
7922 
7923 		statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7924 		    eventreply->EventData;
7925 		rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7926 		    &statuschange->ReasonCode);
7927 		wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7928 		    (uint32_t *)(void *)&statuschange->SASAddress);
7929 		wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7930 		    (uint32_t *)(void *)&statuschange->SASAddress + 1);
7931 		wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7932 		devhdl =  ddi_get16(mpt->m_acc_reply_frame_hdl,
7933 		    &statuschange->DevHandle);
7934 
7935 		NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7936 		    wwn));
7937 
7938 		switch (rc) {
7939 		case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7940 			NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7941 			    ddi_get8(mpt->m_acc_reply_frame_hdl,
7942 			    &statuschange->ASC),
7943 			    ddi_get8(mpt->m_acc_reply_frame_hdl,
7944 			    &statuschange->ASCQ)));
7945 			break;
7946 
7947 		case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7948 			NDBG20(("Device not supported"));
7949 			break;
7950 
7951 		case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7952 			NDBG20(("IOC internally generated the Target Reset "
7953 			    "for devhdl:%x", devhdl));
7954 			break;
7955 
7956 		case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7957 			NDBG20(("IOC's internally generated Target Reset "
7958 			    "completed for devhdl:%x", devhdl));
7959 			break;
7960 
7961 		case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7962 			NDBG20(("IOC internally generated Abort Task"));
7963 			break;
7964 
7965 		case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7966 			NDBG20(("IOC's internally generated Abort Task "
7967 			    "completed"));
7968 			break;
7969 
7970 		case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7971 			NDBG20(("IOC internally generated Abort Task Set"));
7972 			break;
7973 
7974 		case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7975 			NDBG20(("IOC internally generated Clear Task Set"));
7976 			break;
7977 
7978 		case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7979 			NDBG20(("IOC internally generated Query Task"));
7980 			break;
7981 
7982 		case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7983 			NDBG20(("Device sent an Asynchronous Notification"));
7984 			break;
7985 
7986 		default:
7987 			break;
7988 		}
7989 		break;
7990 	}
7991 	case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7992 	{
7993 		/*
7994 		 * IR TOPOLOGY CHANGE LIST Event has already been handled
7995 		 * in mpt_handle_event_sync() of interrupt context
7996 		 */
7997 		break;
7998 	}
7999 	case MPI2_EVENT_IR_OPERATION_STATUS:
8000 	{
8001 		Mpi2EventDataIrOperationStatus_t	*irOpStatus;
8002 		char					reason_str[80];
8003 		uint8_t					rc, percent;
8004 		uint16_t				handle;
8005 
8006 		irOpStatus = (pMpi2EventDataIrOperationStatus_t)
8007 		    eventreply->EventData;
8008 		rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
8009 		    &irOpStatus->RAIDOperation);
8010 		percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
8011 		    &irOpStatus->PercentComplete);
8012 		handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8013 		    &irOpStatus->VolDevHandle);
8014 
8015 		switch (rc) {
8016 			case MPI2_EVENT_IR_RAIDOP_RESYNC:
8017 				(void) sprintf(reason_str, "resync");
8018 				break;
8019 			case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
8020 				(void) sprintf(reason_str, "online capacity "
8021 				    "expansion");
8022 				break;
8023 			case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
8024 				(void) sprintf(reason_str, "consistency check");
8025 				break;
8026 			default:
8027 				(void) sprintf(reason_str, "unknown reason %x",
8028 				    rc);
8029 		}
8030 
8031 		NDBG20(("mptsas%d raid operational status: (%s)"
8032 		    "\thandle(0x%04x), percent complete(%d)\n",
8033 		    mpt->m_instance, reason_str, handle, percent));
8034 		break;
8035 	}
8036 	case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
8037 	{
8038 		pMpi2EventDataSasBroadcastPrimitive_t	sas_broadcast;
8039 		uint8_t					phy_num;
8040 		uint8_t					primitive;
8041 
8042 		sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
8043 		    eventreply->EventData;
8044 
8045 		phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
8046 		    &sas_broadcast->PhyNum);
8047 		primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
8048 		    &sas_broadcast->Primitive);
8049 
8050 		switch (primitive) {
8051 		case MPI2_EVENT_PRIMITIVE_CHANGE:
8052 			mptsas_smhba_log_sysevent(mpt,
8053 			    ESC_SAS_HBA_PORT_BROADCAST,
8054 			    SAS_PORT_BROADCAST_CHANGE,
8055 			    &mpt->m_phy_info[phy_num].smhba_info);
8056 			break;
8057 		case MPI2_EVENT_PRIMITIVE_SES:
8058 			mptsas_smhba_log_sysevent(mpt,
8059 			    ESC_SAS_HBA_PORT_BROADCAST,
8060 			    SAS_PORT_BROADCAST_SES,
8061 			    &mpt->m_phy_info[phy_num].smhba_info);
8062 			break;
8063 		case MPI2_EVENT_PRIMITIVE_EXPANDER:
8064 			mptsas_smhba_log_sysevent(mpt,
8065 			    ESC_SAS_HBA_PORT_BROADCAST,
8066 			    SAS_PORT_BROADCAST_D01_4,
8067 			    &mpt->m_phy_info[phy_num].smhba_info);
8068 			break;
8069 		case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
8070 			mptsas_smhba_log_sysevent(mpt,
8071 			    ESC_SAS_HBA_PORT_BROADCAST,
8072 			    SAS_PORT_BROADCAST_D04_7,
8073 			    &mpt->m_phy_info[phy_num].smhba_info);
8074 			break;
8075 		case MPI2_EVENT_PRIMITIVE_RESERVED3:
8076 			mptsas_smhba_log_sysevent(mpt,
8077 			    ESC_SAS_HBA_PORT_BROADCAST,
8078 			    SAS_PORT_BROADCAST_D16_7,
8079 			    &mpt->m_phy_info[phy_num].smhba_info);
8080 			break;
8081 		case MPI2_EVENT_PRIMITIVE_RESERVED4:
8082 			mptsas_smhba_log_sysevent(mpt,
8083 			    ESC_SAS_HBA_PORT_BROADCAST,
8084 			    SAS_PORT_BROADCAST_D29_7,
8085 			    &mpt->m_phy_info[phy_num].smhba_info);
8086 			break;
8087 		case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
8088 			mptsas_smhba_log_sysevent(mpt,
8089 			    ESC_SAS_HBA_PORT_BROADCAST,
8090 			    SAS_PORT_BROADCAST_D24_0,
8091 			    &mpt->m_phy_info[phy_num].smhba_info);
8092 			break;
8093 		case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
8094 			mptsas_smhba_log_sysevent(mpt,
8095 			    ESC_SAS_HBA_PORT_BROADCAST,
8096 			    SAS_PORT_BROADCAST_D27_4,
8097 			    &mpt->m_phy_info[phy_num].smhba_info);
8098 			break;
8099 		default:
8100 			NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE"
8101 			    " %x received",
8102 			    mpt->m_instance, primitive));
8103 			break;
8104 		}
8105 		NDBG16(("mptsas%d sas broadcast primitive: "
8106 		    "\tprimitive(0x%04x), phy(%d) complete\n",
8107 		    mpt->m_instance, primitive, phy_num));
8108 		break;
8109 	}
8110 	case MPI2_EVENT_IR_VOLUME:
8111 	{
8112 		Mpi2EventDataIrVolume_t		*irVolume;
8113 		uint16_t			devhandle;
8114 		uint32_t			state;
8115 		int				config, vol;
8116 		uint8_t				found = FALSE;
8117 
8118 		irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
8119 		state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8120 		    &irVolume->NewValue);
8121 		devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8122 		    &irVolume->VolDevHandle);
8123 
8124 		NDBG20(("EVENT_IR_VOLUME event is received"));
8125 
8126 		/*
8127 		 * Get latest RAID info and then find the DevHandle for this
8128 		 * event in the configuration.  If the DevHandle is not found
8129 		 * just exit the event.
8130 		 */
8131 		(void) mptsas_get_raid_info(mpt);
8132 		for (config = 0; (config < mpt->m_num_raid_configs) &&
8133 		    (!found); config++) {
8134 			for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
8135 				if (mpt->m_raidconfig[config].m_raidvol[vol].
8136 				    m_raidhandle == devhandle) {
8137 					found = TRUE;
8138 					break;
8139 				}
8140 			}
8141 		}
8142 		if (!found) {
8143 			break;
8144 		}
8145 
8146 		switch (irVolume->ReasonCode) {
8147 		case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
8148 		{
8149 			uint32_t i;
8150 			mpt->m_raidconfig[config].m_raidvol[vol].m_settings =
8151 			    state;
8152 
8153 			i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
8154 			mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
8155 			    ", auto-config of hot-swap drives is %s"
8156 			    ", write caching is %s"
8157 			    ", hot-spare pool mask is %02x\n",
8158 			    vol, state &
8159 			    MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
8160 			    ? "disabled" : "enabled",
8161 			    i == MPI2_RAIDVOL0_SETTING_UNCHANGED
8162 			    ? "controlled by member disks" :
8163 			    i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
8164 			    ? "disabled" :
8165 			    i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
8166 			    ? "enabled" :
8167 			    "incorrectly set",
8168 			    (state >> 16) & 0xff);
8169 				break;
8170 		}
8171 		case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
8172 		{
8173 			mpt->m_raidconfig[config].m_raidvol[vol].m_state =
8174 			    (uint8_t)state;
8175 
8176 			mptsas_log(mpt, CE_NOTE,
8177 			    "Volume %d is now %s\n", vol,
8178 			    state == MPI2_RAID_VOL_STATE_OPTIMAL
8179 			    ? "optimal" :
8180 			    state == MPI2_RAID_VOL_STATE_DEGRADED
8181 			    ? "degraded" :
8182 			    state == MPI2_RAID_VOL_STATE_ONLINE
8183 			    ? "online" :
8184 			    state == MPI2_RAID_VOL_STATE_INITIALIZING
8185 			    ? "initializing" :
8186 			    state == MPI2_RAID_VOL_STATE_FAILED
8187 			    ? "failed" :
8188 			    state == MPI2_RAID_VOL_STATE_MISSING
8189 			    ? "missing" :
8190 			    "state unknown");
8191 			break;
8192 		}
8193 		case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
8194 		{
8195 			mpt->m_raidconfig[config].m_raidvol[vol].
8196 			    m_statusflags = state;
8197 
8198 			mptsas_log(mpt, CE_NOTE,
8199 			    " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
8200 			    vol,
8201 			    state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
8202 			    ? ", enabled" : ", disabled",
8203 			    state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
8204 			    ? ", quiesced" : "",
8205 			    state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
8206 			    ? ", inactive" : ", active",
8207 			    state &
8208 			    MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
8209 			    ? ", bad block table is full" : "",
8210 			    state &
8211 			    MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
8212 			    ? ", resync in progress" : "",
8213 			    state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
8214 			    ? ", background initialization in progress" : "",
8215 			    state &
8216 			    MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
8217 			    ? ", capacity expansion in progress" : "",
8218 			    state &
8219 			    MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
8220 			    ? ", consistency check in progress" : "",
8221 			    state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
8222 			    ? ", data scrub in progress" : "");
8223 			break;
8224 		}
8225 		default:
8226 			break;
8227 		}
8228 		break;
8229 	}
8230 	case MPI2_EVENT_IR_PHYSICAL_DISK:
8231 	{
8232 		Mpi2EventDataIrPhysicalDisk_t	*irPhysDisk;
8233 		uint16_t			devhandle, enchandle, slot;
8234 		uint32_t			status, state;
8235 		uint8_t				physdisknum, reason;
8236 
8237 		irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
8238 		    eventreply->EventData;
8239 		physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
8240 		    &irPhysDisk->PhysDiskNum);
8241 		devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8242 		    &irPhysDisk->PhysDiskDevHandle);
8243 		enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8244 		    &irPhysDisk->EnclosureHandle);
8245 		slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
8246 		    &irPhysDisk->Slot);
8247 		state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8248 		    &irPhysDisk->NewValue);
8249 		reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
8250 		    &irPhysDisk->ReasonCode);
8251 
8252 		NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
8253 
8254 		switch (reason) {
8255 		case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
8256 			mptsas_log(mpt, CE_NOTE,
8257 			    " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8258 			    "for enclosure with handle 0x%x is now in hot "
8259 			    "spare pool %d",
8260 			    physdisknum, devhandle, slot, enchandle,
8261 			    (state >> 16) & 0xff);
8262 			break;
8263 
8264 		case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
8265 			status = state;
8266 			mptsas_log(mpt, CE_NOTE,
8267 			    " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8268 			    "for enclosure with handle 0x%x is now "
8269 			    "%s%s%s%s%s\n", physdisknum, devhandle, slot,
8270 			    enchandle,
8271 			    status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
8272 			    ? ", inactive" : ", active",
8273 			    status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
8274 			    ? ", out of sync" : "",
8275 			    status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
8276 			    ? ", quiesced" : "",
8277 			    status &
8278 			    MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
8279 			    ? ", write cache enabled" : "",
8280 			    status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
8281 			    ? ", capacity expansion target" : "");
8282 			break;
8283 
8284 		case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
8285 			mptsas_log(mpt, CE_NOTE,
8286 			    " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8287 			    "for enclosure with handle 0x%x is now %s\n",
8288 			    physdisknum, devhandle, slot, enchandle,
8289 			    state == MPI2_RAID_PD_STATE_OPTIMAL
8290 			    ? "optimal" :
8291 			    state == MPI2_RAID_PD_STATE_REBUILDING
8292 			    ? "rebuilding" :
8293 			    state == MPI2_RAID_PD_STATE_DEGRADED
8294 			    ? "degraded" :
8295 			    state == MPI2_RAID_PD_STATE_HOT_SPARE
8296 			    ? "a hot spare" :
8297 			    state == MPI2_RAID_PD_STATE_ONLINE
8298 			    ? "online" :
8299 			    state == MPI2_RAID_PD_STATE_OFFLINE
8300 			    ? "offline" :
8301 			    state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
8302 			    ? "not compatible" :
8303 			    state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
8304 			    ? "not configured" :
8305 			    "state unknown");
8306 			break;
8307 		}
8308 		break;
8309 	}
8310 	case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
8311 	{
8312 		pMpi26EventDataActiveCableExcept_t	actcable;
8313 		uint32_t power;
8314 		uint8_t reason, id;
8315 
8316 		actcable = (pMpi26EventDataActiveCableExcept_t)
8317 		    eventreply->EventData;
8318 		power = ddi_get32(mpt->m_acc_reply_frame_hdl,
8319 		    &actcable->ActiveCablePowerRequirement);
8320 		reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
8321 		    &actcable->ReasonCode);
8322 		id = ddi_get8(mpt->m_acc_reply_frame_hdl,
8323 		    &actcable->ReceptacleID);
8324 
8325 		/*
8326 		 * It'd be nice if this weren't just logging to the system but
8327 		 * were telling FMA about the active cable problem and FMA was
8328 		 * aware of the cable topology and state.
8329 		 */
8330 		switch (reason) {
8331 		case MPI26_EVENT_ACTIVE_CABLE_PRESENT:
8332 			/* Don't log anything if it's fine */
8333 			break;
8334 		case MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER:
8335 			mptsas_log(mpt, CE_WARN, "An active cable (id %u) does "
8336 			    "not have sufficient power to be enabled. "
8337 			    "Devices connected to this cable will not be "
8338 			    "visible to the system.", id);
8339 			if (power == UINT32_MAX) {
8340 				mptsas_log(mpt, CE_CONT, "The cable's power "
8341 				    "requirements are unknown.\n");
8342 			} else {
8343 				mptsas_log(mpt, CE_CONT, "The cable requires "
8344 				    "%u mW of power to function.\n", power);
8345 			}
8346 			break;
8347 		case MPI26_EVENT_ACTIVE_CABLE_DEGRADED:
8348 			mptsas_log(mpt, CE_WARN, "An active cable (id %u) is "
8349 			    "degraded and not running at its full speed. "
8350 			    "Some devices might not appear.", id);
8351 			break;
8352 		default:
8353 			break;
8354 		}
8355 		break;
8356 	}
8357 	case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
8358 	case MPI2_EVENT_PCIE_ENUMERATION:
8359 	case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
8360 	case MPI2_EVENT_PCIE_LINK_COUNTER:
8361 		mptsas_log(mpt, CE_NOTE, "Unhandled mpt_sas PCIe device "
8362 		    "event received (0x%x)", event);
8363 		break;
8364 	default:
8365 		NDBG20(("mptsas%d: unknown event %x received",
8366 		    mpt->m_instance, event));
8367 		break;
8368 	}
8369 
8370 	/*
8371 	 * Return the reply frame to the free queue.
8372 	 */
8373 	ddi_put32(mpt->m_acc_free_queue_hdl,
8374 	    &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
8375 	(void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
8376 	    DDI_DMA_SYNC_FORDEV);
8377 	if (++mpt->m_free_index == mpt->m_free_queue_depth) {
8378 		mpt->m_free_index = 0;
8379 	}
8380 	ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
8381 	    mpt->m_free_index);
8382 	mutex_exit(&mpt->m_mutex);
8383 }
8384 
8385 /*
8386  * invoked from timeout() to restart qfull cmds with throttle == 0
8387  */
8388 static void
8389 mptsas_restart_cmd(void *arg)
8390 {
8391 	mptsas_t	*mpt = arg;
8392 	mptsas_target_t	*ptgt = NULL;
8393 
8394 	mutex_enter(&mpt->m_mutex);
8395 
8396 	mpt->m_restart_cmd_timeid = 0;
8397 
8398 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
8399 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
8400 		if (ptgt->m_reset_delay == 0) {
8401 			if (ptgt->m_t_throttle == QFULL_THROTTLE) {
8402 				mptsas_set_throttle(mpt, ptgt,
8403 				    MAX_THROTTLE);
8404 			}
8405 		}
8406 	}
8407 	mptsas_restart_hba(mpt);
8408 	mutex_exit(&mpt->m_mutex);
8409 }
8410 
8411 void
8412 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8413 {
8414 	int		slot;
8415 	mptsas_slots_t	*slots = mpt->m_active;
8416 	mptsas_target_t	*ptgt = cmd->cmd_tgt_addr;
8417 
8418 	ASSERT(cmd != NULL);
8419 	ASSERT(cmd->cmd_queued == FALSE);
8420 
8421 	/*
8422 	 * Task Management cmds are removed in their own routines.  Also,
8423 	 * we don't want to modify timeout based on TM cmds.
8424 	 */
8425 	if (cmd->cmd_flags & CFLAG_TM_CMD) {
8426 		return;
8427 	}
8428 
8429 	slot = cmd->cmd_slot;
8430 
8431 	/*
8432 	 * remove the cmd.
8433 	 */
8434 	if (cmd == slots->m_slot[slot]) {
8435 		NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags "
8436 		    "0x%x", (void *)cmd, cmd->cmd_flags));
8437 		slots->m_slot[slot] = NULL;
8438 		mpt->m_ncmds--;
8439 
8440 		/*
8441 		 * only decrement per target ncmds if command
8442 		 * has a target associated with it.
8443 		 */
8444 		if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8445 			ptgt->m_t_ncmds--;
8446 			/*
8447 			 * reset throttle if we just ran an untagged command
8448 			 * to a tagged target
8449 			 */
8450 			if ((ptgt->m_t_ncmds == 0) &&
8451 			    ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8452 				mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8453 			}
8454 
8455 			/*
8456 			 * Remove this command from the active queue.
8457 			 */
8458 			if (cmd->cmd_active_expiration != 0) {
8459 				TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8460 				    cmd_active_link);
8461 				cmd->cmd_active_expiration = 0;
8462 			}
8463 		}
8464 	}
8465 
8466 	/*
8467 	 * This is all we need to do for ioc commands.
8468 	 */
8469 	if (cmd->cmd_flags & CFLAG_CMDIOC) {
8470 		mptsas_return_to_pool(mpt, cmd);
8471 		return;
8472 	}
8473 
8474 	ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8475 }
8476 
8477 /*
8478  * accept all cmds on the tx_waitq if any and then
8479  * start a fresh request from the top of the device queue.
8480  *
8481  * since there are always cmds queued on the tx_waitq, and rare cmds on
8482  * the instance waitq, so this function should not be invoked in the ISR,
8483  * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
8484  * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
8485  */
8486 static void
8487 mptsas_restart_hba(mptsas_t *mpt)
8488 {
8489 	ASSERT(mutex_owned(&mpt->m_mutex));
8490 
8491 	mutex_enter(&mpt->m_tx_waitq_mutex);
8492 	if (mpt->m_tx_waitq) {
8493 		mptsas_accept_tx_waitq(mpt);
8494 	}
8495 	mutex_exit(&mpt->m_tx_waitq_mutex);
8496 	mptsas_restart_waitq(mpt);
8497 }
8498 
8499 /*
8500  * start a fresh request from the top of the device queue
8501  */
8502 static void
8503 mptsas_restart_waitq(mptsas_t *mpt)
8504 {
8505 	mptsas_cmd_t	*cmd, *next_cmd;
8506 	mptsas_target_t *ptgt = NULL;
8507 
8508 	NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
8509 
8510 	ASSERT(mutex_owned(&mpt->m_mutex));
8511 
8512 	/*
8513 	 * If there is a reset delay, don't start any cmds.  Otherwise, start
8514 	 * as many cmds as possible.
8515 	 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
8516 	 * commands is m_max_requests - 2.
8517 	 */
8518 	cmd = mpt->m_waitq;
8519 
8520 	while (cmd != NULL) {
8521 		next_cmd = cmd->cmd_linkp;
8522 		if (cmd->cmd_flags & CFLAG_PASSTHRU) {
8523 			if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8524 				/*
8525 				 * passthru command get slot need
8526 				 * set CFLAG_PREPARED.
8527 				 */
8528 				cmd->cmd_flags |= CFLAG_PREPARED;
8529 				mptsas_waitq_delete(mpt, cmd);
8530 				mptsas_start_passthru(mpt, cmd);
8531 			}
8532 			cmd = next_cmd;
8533 			continue;
8534 		}
8535 		if (cmd->cmd_flags & CFLAG_CONFIG) {
8536 			if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8537 				/*
8538 				 * Send the config page request and delete it
8539 				 * from the waitq.
8540 				 */
8541 				cmd->cmd_flags |= CFLAG_PREPARED;
8542 				mptsas_waitq_delete(mpt, cmd);
8543 				mptsas_start_config_page_access(mpt, cmd);
8544 			}
8545 			cmd = next_cmd;
8546 			continue;
8547 		}
8548 		if (cmd->cmd_flags & CFLAG_FW_DIAG) {
8549 			if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8550 				/*
8551 				 * Send the FW Diag request and delete if from
8552 				 * the waitq.
8553 				 */
8554 				cmd->cmd_flags |= CFLAG_PREPARED;
8555 				mptsas_waitq_delete(mpt, cmd);
8556 				mptsas_start_diag(mpt, cmd);
8557 			}
8558 			cmd = next_cmd;
8559 			continue;
8560 		}
8561 
8562 		ptgt = cmd->cmd_tgt_addr;
8563 		if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8564 		    (ptgt->m_t_ncmds == 0)) {
8565 			mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8566 		}
8567 		if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
8568 		    (ptgt && (ptgt->m_reset_delay == 0)) &&
8569 		    (ptgt && (ptgt->m_t_ncmds <
8570 		    ptgt->m_t_throttle))) {
8571 			if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8572 				mptsas_waitq_delete(mpt, cmd);
8573 				(void) mptsas_start_cmd(mpt, cmd);
8574 			}
8575 		}
8576 		cmd = next_cmd;
8577 	}
8578 }
8579 /*
8580  * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
8581  * Accept all those queued cmds before new cmd is accept so that the
8582  * cmds are sent in order.
8583  */
8584 static void
8585 mptsas_accept_tx_waitq(mptsas_t *mpt)
8586 {
8587 	mptsas_cmd_t *cmd;
8588 
8589 	ASSERT(mutex_owned(&mpt->m_mutex));
8590 	ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
8591 
8592 	/*
8593 	 * A Bus Reset could occur at any time and flush the tx_waitq,
8594 	 * so we cannot count on the tx_waitq to contain even one cmd.
8595 	 * And when the m_tx_waitq_mutex is released and run
8596 	 * mptsas_accept_pkt(), the tx_waitq may be flushed.
8597 	 */
8598 	cmd = mpt->m_tx_waitq;
8599 	for (;;) {
8600 		if ((cmd = mpt->m_tx_waitq) == NULL) {
8601 			mpt->m_tx_draining = 0;
8602 			break;
8603 		}
8604 		if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
8605 			mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8606 		}
8607 		cmd->cmd_linkp = NULL;
8608 		mutex_exit(&mpt->m_tx_waitq_mutex);
8609 		if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
8610 			cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
8611 			    "to accept cmd on queue\n");
8612 		mutex_enter(&mpt->m_tx_waitq_mutex);
8613 	}
8614 }
8615 
8616 
8617 /*
8618  * mpt tag type lookup
8619  */
8620 static char mptsas_tag_lookup[] =
8621 	{0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
8622 
8623 static int
8624 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8625 {
8626 	struct scsi_pkt		*pkt = CMD2PKT(cmd);
8627 	uint32_t		control = 0;
8628 	caddr_t			mem, arsbuf;
8629 	pMpi2SCSIIORequest_t	io_request;
8630 	ddi_dma_handle_t	dma_hdl = mpt->m_dma_req_frame_hdl;
8631 	ddi_acc_handle_t	acc_hdl = mpt->m_acc_req_frame_hdl;
8632 	mptsas_target_t		*ptgt = cmd->cmd_tgt_addr;
8633 	uint16_t		SMID, io_flags = 0;
8634 	uint8_t			ars_size;
8635 	uint64_t		request_desc;
8636 	uint32_t		ars_dmaaddrlow;
8637 	mptsas_cmd_t		*c;
8638 
8639 	NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd,
8640 	    cmd->cmd_flags));
8641 
8642 	/*
8643 	 * Set SMID and increment index.  Rollover to 1 instead of 0 if index
8644 	 * is at the max.  0 is an invalid SMID, so we call the first index 1.
8645 	 */
8646 	SMID = cmd->cmd_slot;
8647 
8648 	/*
8649 	 * It is possible for back to back device reset to
8650 	 * happen before the reset delay has expired.  That's
8651 	 * ok, just let the device reset go out on the bus.
8652 	 */
8653 	if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8654 		ASSERT(ptgt->m_reset_delay == 0);
8655 	}
8656 
8657 	/*
8658 	 * if a non-tagged cmd is submitted to an active tagged target
8659 	 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8660 	 * to be untagged
8661 	 */
8662 	if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8663 	    (ptgt->m_t_ncmds > 1) &&
8664 	    ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8665 	    (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8666 		if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8667 			NDBG23(("target=%d, untagged cmd, start draining\n",
8668 			    ptgt->m_devhdl));
8669 
8670 			if (ptgt->m_reset_delay == 0) {
8671 				mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8672 			}
8673 
8674 			mptsas_remove_cmd(mpt, cmd);
8675 			cmd->cmd_pkt_flags |= FLAG_HEAD;
8676 			mptsas_waitq_add(mpt, cmd);
8677 		}
8678 		return (DDI_FAILURE);
8679 	}
8680 
8681 	/*
8682 	 * Set correct tag bits.
8683 	 */
8684 	if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8685 		switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8686 		    FLAG_TAGMASK) >> 12)]) {
8687 		case MSG_SIMPLE_QTAG:
8688 			control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8689 			break;
8690 		case MSG_HEAD_QTAG:
8691 			control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8692 			break;
8693 		case MSG_ORDERED_QTAG:
8694 			control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8695 			break;
8696 		default:
8697 			mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8698 			break;
8699 		}
8700 	} else {
8701 		if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8702 				ptgt->m_t_throttle = 1;
8703 		}
8704 		control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8705 	}
8706 
8707 	if (cmd->cmd_pkt_flags & FLAG_TLR) {
8708 		control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8709 	}
8710 
8711 	mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8712 	io_request = (pMpi2SCSIIORequest_t)mem;
8713 	if (cmd->cmd_extrqslen != 0) {
8714 		/*
8715 		 * Mapping of the buffer was done in mptsas_pkt_alloc_extern().
8716 		 * Calculate the DMA address with the same offset.
8717 		 */
8718 		arsbuf = cmd->cmd_arq_buf;
8719 		ars_size = cmd->cmd_extrqslen;
8720 		ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8721 		    ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
8722 		    0xffffffffu;
8723 	} else {
8724 		arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1));
8725 		cmd->cmd_arq_buf = arsbuf;
8726 		ars_size = mpt->m_req_sense_size;
8727 		ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8728 		    (mpt->m_req_sense_size * (SMID-1))) &
8729 		    0xffffffffu;
8730 	}
8731 	bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8732 	bzero(arsbuf, ars_size);
8733 
8734 	ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8735 	    (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8736 	mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8737 	    MPI2_FUNCTION_SCSI_IO_REQUEST);
8738 
8739 	(void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8740 	    io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8741 
8742 	io_flags = cmd->cmd_cdblen;
8743 	if (mptsas_use_fastpath &&
8744 	    ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) {
8745 		io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH;
8746 		request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
8747 	} else {
8748 		request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8749 	}
8750 	ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8751 	/*
8752 	 * setup the Scatter/Gather DMA list for this request
8753 	 */
8754 	if (cmd->cmd_cookiec > 0) {
8755 		mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8756 	} else {
8757 		ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8758 		    ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8759 		    MPI2_SGE_FLAGS_END_OF_BUFFER |
8760 		    MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8761 		    MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8762 	}
8763 
8764 	/*
8765 	 * save ARQ information
8766 	 */
8767 	ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size);
8768 	ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow);
8769 
8770 	ddi_put32(acc_hdl, &io_request->Control, control);
8771 
8772 	NDBG31(("starting message=%d(0x%p), with cmd=0x%p",
8773 	    SMID, (void *)io_request, (void *)cmd));
8774 
8775 	(void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8776 	(void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
8777 	    DDI_DMA_SYNC_FORDEV);
8778 
8779 	/*
8780 	 * Build request descriptor and write it to the request desc post reg.
8781 	 */
8782 	request_desc |= (SMID << 16);
8783 	request_desc |= (uint64_t)ptgt->m_devhdl << 48;
8784 	MPTSAS_START_CMD(mpt, request_desc);
8785 
8786 	/*
8787 	 * Start timeout.
8788 	 */
8789 	cmd->cmd_active_expiration =
8790 	    gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC;
8791 #ifdef MPTSAS_TEST
8792 	/*
8793 	 * Force timeouts to happen immediately.
8794 	 */
8795 	if (mptsas_test_timeouts)
8796 		cmd->cmd_active_expiration = gethrtime();
8797 #endif
8798 	c = TAILQ_FIRST(&ptgt->m_active_cmdq);
8799 	if (c == NULL ||
8800 	    c->cmd_active_expiration < cmd->cmd_active_expiration) {
8801 		/*
8802 		 * Common case is that this is the last pending expiration
8803 		 * (or queue is empty). Insert at head of the queue.
8804 		 */
8805 		TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link);
8806 	} else {
8807 		/*
8808 		 * Queue is not empty and first element expires later than
8809 		 * this command. Search for element expiring sooner.
8810 		 */
8811 		while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) {
8812 			if (c->cmd_active_expiration <
8813 			    cmd->cmd_active_expiration) {
8814 				TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link);
8815 				break;
8816 			}
8817 		}
8818 		if (c == NULL) {
8819 			/*
8820 			 * No element found expiring sooner, append to
8821 			 * non-empty queue.
8822 			 */
8823 			TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd,
8824 			    cmd_active_link);
8825 		}
8826 	}
8827 
8828 	if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8829 	    (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8830 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8831 		return (DDI_FAILURE);
8832 	}
8833 	return (DDI_SUCCESS);
8834 }
8835 
8836 /*
8837  * Select a helper thread to handle current doneq
8838  */
8839 static void
8840 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8841 {
8842 	uint64_t			t, i;
8843 	uint32_t			min = 0xffffffff;
8844 	mptsas_doneq_thread_list_t	*item;
8845 
8846 	for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8847 		item = &mpt->m_doneq_thread_id[i];
8848 		/*
8849 		 * If the completed command on help thread[i] less than
8850 		 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8851 		 * pick a thread which has least completed command.
8852 		 */
8853 
8854 		mutex_enter(&item->mutex);
8855 		if (item->len < mpt->m_doneq_thread_threshold) {
8856 			t = i;
8857 			mutex_exit(&item->mutex);
8858 			break;
8859 		}
8860 		if (item->len < min) {
8861 			min = item->len;
8862 			t = i;
8863 		}
8864 		mutex_exit(&item->mutex);
8865 	}
8866 	mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8867 	mptsas_doneq_mv(mpt, t);
8868 	cv_signal(&mpt->m_doneq_thread_id[t].cv);
8869 	mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8870 }
8871 
8872 /*
8873  * move the current global doneq to the doneq of thead[t]
8874  */
8875 static void
8876 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8877 {
8878 	mptsas_cmd_t			*cmd;
8879 	mptsas_doneq_thread_list_t	*item = &mpt->m_doneq_thread_id[t];
8880 
8881 	ASSERT(mutex_owned(&item->mutex));
8882 	while ((cmd = mpt->m_doneq) != NULL) {
8883 		if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8884 			mpt->m_donetail = &mpt->m_doneq;
8885 		}
8886 		cmd->cmd_linkp = NULL;
8887 		*item->donetail = cmd;
8888 		item->donetail = &cmd->cmd_linkp;
8889 		mpt->m_doneq_len--;
8890 		item->len++;
8891 	}
8892 }
8893 
8894 void
8895 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8896 {
8897 	struct scsi_pkt	*pkt = CMD2PKT(cmd);
8898 
8899 	/* Check all acc and dma handles */
8900 	if ((mptsas_check_acc_handle(mpt->m_datap) !=
8901 	    DDI_SUCCESS) ||
8902 	    (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8903 	    DDI_SUCCESS) ||
8904 	    (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
8905 	    DDI_SUCCESS) ||
8906 	    (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8907 	    DDI_SUCCESS) ||
8908 	    (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8909 	    DDI_SUCCESS) ||
8910 	    (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8911 	    DDI_SUCCESS) ||
8912 	    (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8913 	    DDI_SUCCESS) ||
8914 	    (mptsas_check_acc_handle(mpt->m_config_handle) !=
8915 	    DDI_SUCCESS)) {
8916 		ddi_fm_service_impact(mpt->m_dip,
8917 		    DDI_SERVICE_UNAFFECTED);
8918 		ddi_fm_acc_err_clear(mpt->m_config_handle,
8919 		    DDI_FME_VER0);
8920 		pkt->pkt_reason = CMD_TRAN_ERR;
8921 		pkt->pkt_statistics = 0;
8922 	}
8923 	if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8924 	    DDI_SUCCESS) ||
8925 	    (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
8926 	    DDI_SUCCESS) ||
8927 	    (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8928 	    DDI_SUCCESS) ||
8929 	    (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8930 	    DDI_SUCCESS) ||
8931 	    (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8932 	    DDI_SUCCESS) ||
8933 	    (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8934 	    DDI_SUCCESS)) {
8935 		ddi_fm_service_impact(mpt->m_dip,
8936 		    DDI_SERVICE_UNAFFECTED);
8937 		pkt->pkt_reason = CMD_TRAN_ERR;
8938 		pkt->pkt_statistics = 0;
8939 	}
8940 	if (cmd->cmd_dmahandle &&
8941 	    (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8942 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8943 		pkt->pkt_reason = CMD_TRAN_ERR;
8944 		pkt->pkt_statistics = 0;
8945 	}
8946 	if ((cmd->cmd_extra_frames &&
8947 	    ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8948 	    DDI_SUCCESS) ||
8949 	    (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8950 	    DDI_SUCCESS)))) {
8951 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8952 		pkt->pkt_reason = CMD_TRAN_ERR;
8953 		pkt->pkt_statistics = 0;
8954 	}
8955 }
8956 
8957 /*
8958  * These routines manipulate the queue of commands that
8959  * are waiting for their completion routines to be called.
8960  * The queue is usually in FIFO order but on an MP system
8961  * it's possible for the completion routines to get out
8962  * of order. If that's a problem you need to add a global
8963  * mutex around the code that calls the completion routine
8964  * in the interrupt handler.
8965  */
8966 static void
8967 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8968 {
8969 	struct scsi_pkt	*pkt = CMD2PKT(cmd);
8970 
8971 	NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8972 
8973 	ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8974 	cmd->cmd_linkp = NULL;
8975 	cmd->cmd_flags |= CFLAG_FINISHED;
8976 	cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8977 
8978 	mptsas_fma_check(mpt, cmd);
8979 
8980 	/*
8981 	 * only add scsi pkts that have completion routines to
8982 	 * the doneq.  no intr cmds do not have callbacks.
8983 	 */
8984 	if (pkt && (pkt->pkt_comp)) {
8985 		*mpt->m_donetail = cmd;
8986 		mpt->m_donetail = &cmd->cmd_linkp;
8987 		mpt->m_doneq_len++;
8988 	}
8989 }
8990 
8991 static mptsas_cmd_t *
8992 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8993 {
8994 	mptsas_cmd_t			*cmd;
8995 	mptsas_doneq_thread_list_t	*item = &mpt->m_doneq_thread_id[t];
8996 
8997 	/* pop one off the done queue */
8998 	if ((cmd = item->doneq) != NULL) {
8999 		/* if the queue is now empty fix the tail pointer */
9000 		NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
9001 		if ((item->doneq = cmd->cmd_linkp) == NULL) {
9002 			item->donetail = &item->doneq;
9003 		}
9004 		cmd->cmd_linkp = NULL;
9005 		item->len--;
9006 	}
9007 	return (cmd);
9008 }
9009 
9010 static void
9011 mptsas_doneq_empty(mptsas_t *mpt)
9012 {
9013 	if (mpt->m_doneq && !mpt->m_in_callback) {
9014 		mptsas_cmd_t	*cmd, *next;
9015 		struct scsi_pkt *pkt;
9016 
9017 		mpt->m_in_callback = 1;
9018 		cmd = mpt->m_doneq;
9019 		mpt->m_doneq = NULL;
9020 		mpt->m_donetail = &mpt->m_doneq;
9021 		mpt->m_doneq_len = 0;
9022 
9023 		mutex_exit(&mpt->m_mutex);
9024 		/*
9025 		 * run the completion routines of all the
9026 		 * completed commands
9027 		 */
9028 		while (cmd != NULL) {
9029 			next = cmd->cmd_linkp;
9030 			cmd->cmd_linkp = NULL;
9031 			/* run this command's completion routine */
9032 			cmd->cmd_flags |= CFLAG_COMPLETED;
9033 			pkt = CMD2PKT(cmd);
9034 			mptsas_pkt_comp(pkt, cmd);
9035 			cmd = next;
9036 		}
9037 		mutex_enter(&mpt->m_mutex);
9038 		mpt->m_in_callback = 0;
9039 	}
9040 }
9041 
9042 /*
9043  * These routines manipulate the target's queue of pending requests
9044  */
9045 void
9046 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
9047 {
9048 	NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
9049 	mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
9050 	cmd->cmd_queued = TRUE;
9051 	if (ptgt)
9052 		ptgt->m_t_nwait++;
9053 	if (cmd->cmd_pkt_flags & FLAG_HEAD) {
9054 		if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
9055 			mpt->m_waitqtail = &cmd->cmd_linkp;
9056 		}
9057 		mpt->m_waitq = cmd;
9058 	} else {
9059 		cmd->cmd_linkp = NULL;
9060 		*(mpt->m_waitqtail) = cmd;
9061 		mpt->m_waitqtail = &cmd->cmd_linkp;
9062 	}
9063 }
9064 
9065 static mptsas_cmd_t *
9066 mptsas_waitq_rm(mptsas_t *mpt)
9067 {
9068 	mptsas_cmd_t	*cmd;
9069 	mptsas_target_t *ptgt;
9070 	NDBG7(("mptsas_waitq_rm"));
9071 
9072 	MPTSAS_WAITQ_RM(mpt, cmd);
9073 
9074 	NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
9075 	if (cmd) {
9076 		ptgt = cmd->cmd_tgt_addr;
9077 		if (ptgt) {
9078 			ptgt->m_t_nwait--;
9079 			ASSERT(ptgt->m_t_nwait >= 0);
9080 		}
9081 	}
9082 	return (cmd);
9083 }
9084 
9085 /*
9086  * remove specified cmd from the middle of the wait queue.
9087  */
9088 static void
9089 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
9090 {
9091 	mptsas_cmd_t	*prevp = mpt->m_waitq;
9092 	mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
9093 
9094 	NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9095 	    (void *)mpt, (void *)cmd));
9096 	if (ptgt) {
9097 		ptgt->m_t_nwait--;
9098 		ASSERT(ptgt->m_t_nwait >= 0);
9099 	}
9100 
9101 	if (prevp == cmd) {
9102 		if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
9103 			mpt->m_waitqtail = &mpt->m_waitq;
9104 
9105 		cmd->cmd_linkp = NULL;
9106 		cmd->cmd_queued = FALSE;
9107 		NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9108 		    (void *)mpt, (void *)cmd));
9109 		return;
9110 	}
9111 
9112 	while (prevp != NULL) {
9113 		if (prevp->cmd_linkp == cmd) {
9114 			if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
9115 				mpt->m_waitqtail = &prevp->cmd_linkp;
9116 
9117 			cmd->cmd_linkp = NULL;
9118 			cmd->cmd_queued = FALSE;
9119 			NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9120 			    (void *)mpt, (void *)cmd));
9121 			return;
9122 		}
9123 		prevp = prevp->cmd_linkp;
9124 	}
9125 	cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
9126 }
9127 
9128 static mptsas_cmd_t *
9129 mptsas_tx_waitq_rm(mptsas_t *mpt)
9130 {
9131 	mptsas_cmd_t *cmd;
9132 	NDBG7(("mptsas_tx_waitq_rm"));
9133 
9134 	MPTSAS_TX_WAITQ_RM(mpt, cmd);
9135 
9136 	NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
9137 
9138 	return (cmd);
9139 }
9140 
9141 /*
9142  * remove specified cmd from the middle of the tx_waitq.
9143  */
9144 static void
9145 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
9146 {
9147 	mptsas_cmd_t *prevp = mpt->m_tx_waitq;
9148 
9149 	NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
9150 	    (void *)mpt, (void *)cmd));
9151 
9152 	if (prevp == cmd) {
9153 		if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
9154 			mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
9155 
9156 		cmd->cmd_linkp = NULL;
9157 		cmd->cmd_queued = FALSE;
9158 		NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
9159 		    (void *)mpt, (void *)cmd));
9160 		return;
9161 	}
9162 
9163 	while (prevp != NULL) {
9164 		if (prevp->cmd_linkp == cmd) {
9165 			if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
9166 				mpt->m_tx_waitqtail = &prevp->cmd_linkp;
9167 
9168 			cmd->cmd_linkp = NULL;
9169 			cmd->cmd_queued = FALSE;
9170 			NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
9171 			    (void *)mpt, (void *)cmd));
9172 			return;
9173 		}
9174 		prevp = prevp->cmd_linkp;
9175 	}
9176 	cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
9177 }
9178 
9179 /*
9180  * device and bus reset handling
9181  *
9182  * Notes:
9183  *	- RESET_ALL:	reset the controller
9184  *	- RESET_TARGET:	reset the target specified in scsi_address
9185  */
9186 static int
9187 mptsas_scsi_reset(struct scsi_address *ap, int level)
9188 {
9189 	mptsas_t		*mpt = ADDR2MPT(ap);
9190 	int			rval;
9191 	mptsas_tgt_private_t	*tgt_private;
9192 	mptsas_target_t		*ptgt = NULL;
9193 
9194 	tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
9195 	ptgt = tgt_private->t_private;
9196 	if (ptgt == NULL) {
9197 		return (FALSE);
9198 	}
9199 	NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
9200 	    level));
9201 
9202 	mutex_enter(&mpt->m_mutex);
9203 	/*
9204 	 * if we are not in panic set up a reset delay for this target
9205 	 */
9206 	if (!ddi_in_panic()) {
9207 		mptsas_setup_bus_reset_delay(mpt);
9208 	} else {
9209 		drv_usecwait(mpt->m_scsi_reset_delay * 1000);
9210 	}
9211 	rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
9212 	mutex_exit(&mpt->m_mutex);
9213 
9214 	/*
9215 	 * The transport layer expect to only see TRUE and
9216 	 * FALSE. Therefore, we will adjust the return value
9217 	 * if mptsas_do_scsi_reset returns FAILED.
9218 	 */
9219 	if (rval == FAILED)
9220 		rval = FALSE;
9221 	return (rval);
9222 }
9223 
9224 static int
9225 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
9226 {
9227 	int		rval = FALSE;
9228 	uint8_t		config, disk;
9229 
9230 	ASSERT(mutex_owned(&mpt->m_mutex));
9231 
9232 	if (mptsas_debug_resets) {
9233 		mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
9234 		    devhdl);
9235 	}
9236 
9237 	/*
9238 	 * Issue a Target Reset message to the target specified but not to a
9239 	 * disk making up a raid volume.  Just look through the RAID config
9240 	 * Phys Disk list of DevHandles.  If the target's DevHandle is in this
9241 	 * list, then don't reset this target.
9242 	 */
9243 	for (config = 0; config < mpt->m_num_raid_configs; config++) {
9244 		for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
9245 			if (devhdl == mpt->m_raidconfig[config].
9246 			    m_physdisk_devhdl[disk]) {
9247 				return (TRUE);
9248 			}
9249 		}
9250 	}
9251 
9252 	rval = mptsas_ioc_task_management(mpt,
9253 	    MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
9254 
9255 	mptsas_doneq_empty(mpt);
9256 	return (rval);
9257 }
9258 
9259 static int
9260 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
9261     void (*callback)(caddr_t), caddr_t arg)
9262 {
9263 	mptsas_t	*mpt = ADDR2MPT(ap);
9264 
9265 	NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
9266 
9267 	return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
9268 	    &mpt->m_mutex, &mpt->m_reset_notify_listf));
9269 }
9270 
9271 static int
9272 mptsas_get_name(struct scsi_device *sd, char *name, int len)
9273 {
9274 	dev_info_t	*lun_dip = NULL;
9275 
9276 	ASSERT(sd != NULL);
9277 	ASSERT(name != NULL);
9278 	lun_dip = sd->sd_dev;
9279 	ASSERT(lun_dip != NULL);
9280 
9281 	if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
9282 		return (1);
9283 	} else {
9284 		return (0);
9285 	}
9286 }
9287 
9288 static int
9289 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
9290 {
9291 	return (mptsas_get_name(sd, name, len));
9292 }
9293 
9294 void
9295 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9296 {
9297 
9298 	NDBG25(("mptsas_set_throttle: throttle=%x", what));
9299 
9300 	/*
9301 	 * if the bus is draining/quiesced, no changes to the throttles
9302 	 * are allowed. Not allowing change of throttles during draining
9303 	 * limits error recovery but will reduce draining time
9304 	 *
9305 	 * all throttles should have been set to HOLD_THROTTLE
9306 	 */
9307 	if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9308 		return;
9309 	}
9310 
9311 	if (what == HOLD_THROTTLE) {
9312 		ptgt->m_t_throttle = HOLD_THROTTLE;
9313 	} else if (ptgt->m_reset_delay == 0) {
9314 		ptgt->m_t_throttle = what;
9315 	}
9316 }
9317 
9318 /*
9319  * Clean up from a device reset.
9320  * For the case of target reset, this function clears the waitq of all
9321  * commands for a particular target.   For the case of abort task set, this
9322  * function clears the waitq of all commonds for a particular target/lun.
9323  */
9324 static void
9325 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
9326 {
9327 	mptsas_slots_t	*slots = mpt->m_active;
9328 	mptsas_cmd_t	*cmd, *next_cmd;
9329 	int		slot;
9330 	uchar_t		reason;
9331 	uint_t		stat;
9332 	hrtime_t	timestamp;
9333 
9334 	NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
9335 
9336 	timestamp = gethrtime();
9337 
9338 	/*
9339 	 * Make sure the I/O Controller has flushed all cmds
9340 	 * that are associated with this target for a target reset
9341 	 * and target/lun for abort task set.
9342 	 * Account for TM requests, which use the last SMID.
9343 	 */
9344 	for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9345 		if ((cmd = slots->m_slot[slot]) == NULL)
9346 			continue;
9347 		reason = CMD_RESET;
9348 		stat = STAT_DEV_RESET;
9349 		switch (tasktype) {
9350 		case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9351 			if (Tgt(cmd) == target) {
9352 				if (cmd->cmd_active_expiration <= timestamp) {
9353 					/*
9354 					 * When timeout requested, propagate
9355 					 * proper reason and statistics to
9356 					 * target drivers.
9357 					 */
9358 					reason = CMD_TIMEOUT;
9359 					stat |= STAT_TIMEOUT;
9360 				}
9361 				NDBG25(("mptsas_flush_target discovered non-"
9362 				    "NULL cmd in slot %d, tasktype 0x%x", slot,
9363 				    tasktype));
9364 				mptsas_dump_cmd(mpt, cmd);
9365 				mptsas_remove_cmd(mpt, cmd);
9366 				mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9367 				mptsas_doneq_add(mpt, cmd);
9368 			}
9369 			break;
9370 		case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9371 			reason = CMD_ABORTED;
9372 			stat = STAT_ABORTED;
9373 			/*FALLTHROUGH*/
9374 		case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9375 			if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9376 
9377 				NDBG25(("mptsas_flush_target discovered non-"
9378 				    "NULL cmd in slot %d, tasktype 0x%x", slot,
9379 				    tasktype));
9380 				mptsas_dump_cmd(mpt, cmd);
9381 				mptsas_remove_cmd(mpt, cmd);
9382 				mptsas_set_pkt_reason(mpt, cmd, reason,
9383 				    stat);
9384 				mptsas_doneq_add(mpt, cmd);
9385 			}
9386 			break;
9387 		default:
9388 			break;
9389 		}
9390 	}
9391 
9392 	/*
9393 	 * Flush the waitq and tx_waitq of this target's cmds
9394 	 */
9395 	cmd = mpt->m_waitq;
9396 
9397 	reason = CMD_RESET;
9398 	stat = STAT_DEV_RESET;
9399 
9400 	switch (tasktype) {
9401 	case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9402 		while (cmd != NULL) {
9403 			next_cmd = cmd->cmd_linkp;
9404 			if (Tgt(cmd) == target) {
9405 				mptsas_waitq_delete(mpt, cmd);
9406 				mptsas_set_pkt_reason(mpt, cmd,
9407 				    reason, stat);
9408 				mptsas_doneq_add(mpt, cmd);
9409 			}
9410 			cmd = next_cmd;
9411 		}
9412 		mutex_enter(&mpt->m_tx_waitq_mutex);
9413 		cmd = mpt->m_tx_waitq;
9414 		while (cmd != NULL) {
9415 			next_cmd = cmd->cmd_linkp;
9416 			if (Tgt(cmd) == target) {
9417 				mptsas_tx_waitq_delete(mpt, cmd);
9418 				mutex_exit(&mpt->m_tx_waitq_mutex);
9419 				mptsas_set_pkt_reason(mpt, cmd,
9420 				    reason, stat);
9421 				mptsas_doneq_add(mpt, cmd);
9422 				mutex_enter(&mpt->m_tx_waitq_mutex);
9423 			}
9424 			cmd = next_cmd;
9425 		}
9426 		mutex_exit(&mpt->m_tx_waitq_mutex);
9427 		break;
9428 	case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9429 		reason = CMD_ABORTED;
9430 		stat =  STAT_ABORTED;
9431 		/*FALLTHROUGH*/
9432 	case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9433 		while (cmd != NULL) {
9434 			next_cmd = cmd->cmd_linkp;
9435 			if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9436 				mptsas_waitq_delete(mpt, cmd);
9437 				mptsas_set_pkt_reason(mpt, cmd,
9438 				    reason, stat);
9439 				mptsas_doneq_add(mpt, cmd);
9440 			}
9441 			cmd = next_cmd;
9442 		}
9443 		mutex_enter(&mpt->m_tx_waitq_mutex);
9444 		cmd = mpt->m_tx_waitq;
9445 		while (cmd != NULL) {
9446 			next_cmd = cmd->cmd_linkp;
9447 			if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9448 				mptsas_tx_waitq_delete(mpt, cmd);
9449 				mutex_exit(&mpt->m_tx_waitq_mutex);
9450 				mptsas_set_pkt_reason(mpt, cmd,
9451 				    reason, stat);
9452 				mptsas_doneq_add(mpt, cmd);
9453 				mutex_enter(&mpt->m_tx_waitq_mutex);
9454 			}
9455 			cmd = next_cmd;
9456 		}
9457 		mutex_exit(&mpt->m_tx_waitq_mutex);
9458 		break;
9459 	default:
9460 		mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
9461 		    tasktype);
9462 		break;
9463 	}
9464 }
9465 
9466 /*
9467  * Clean up hba state, abort all outstanding command and commands in waitq
9468  * reset timeout of all targets.
9469  */
9470 static void
9471 mptsas_flush_hba(mptsas_t *mpt)
9472 {
9473 	mptsas_slots_t	*slots = mpt->m_active;
9474 	mptsas_cmd_t	*cmd;
9475 	int		slot;
9476 
9477 	NDBG25(("mptsas_flush_hba"));
9478 
9479 	/*
9480 	 * The I/O Controller should have already sent back
9481 	 * all commands via the scsi I/O reply frame.  Make
9482 	 * sure all commands have been flushed.
9483 	 * Account for TM request, which use the last SMID.
9484 	 */
9485 	for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9486 		if ((cmd = slots->m_slot[slot]) == NULL)
9487 			continue;
9488 
9489 		if (cmd->cmd_flags & CFLAG_CMDIOC) {
9490 			/*
9491 			 * Need to make sure to tell everyone that might be
9492 			 * waiting on this command that it's going to fail.  If
9493 			 * we get here, this command will never timeout because
9494 			 * the active command table is going to be re-allocated,
9495 			 * so there will be nothing to check against a time out.
9496 			 * Instead, mark the command as failed due to reset.
9497 			 */
9498 			mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9499 			    STAT_BUS_RESET);
9500 			if ((cmd->cmd_flags &
9501 			    (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
9502 				cmd->cmd_flags |= CFLAG_FINISHED;
9503 				cv_broadcast(&mpt->m_passthru_cv);
9504 				cv_broadcast(&mpt->m_config_cv);
9505 				cv_broadcast(&mpt->m_fw_diag_cv);
9506 			}
9507 			continue;
9508 		}
9509 
9510 		NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
9511 		    slot));
9512 		mptsas_dump_cmd(mpt, cmd);
9513 
9514 		mptsas_remove_cmd(mpt, cmd);
9515 		mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9516 		mptsas_doneq_add(mpt, cmd);
9517 	}
9518 
9519 	/*
9520 	 * Flush the waitq.
9521 	 */
9522 	while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
9523 		mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9524 		if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9525 		    (cmd->cmd_flags & CFLAG_CONFIG) ||
9526 		    (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9527 			cmd->cmd_flags |= CFLAG_FINISHED;
9528 			cv_broadcast(&mpt->m_passthru_cv);
9529 			cv_broadcast(&mpt->m_config_cv);
9530 			cv_broadcast(&mpt->m_fw_diag_cv);
9531 		} else {
9532 			mptsas_doneq_add(mpt, cmd);
9533 		}
9534 	}
9535 
9536 	/*
9537 	 * Flush the tx_waitq
9538 	 */
9539 	mutex_enter(&mpt->m_tx_waitq_mutex);
9540 	while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
9541 		mutex_exit(&mpt->m_tx_waitq_mutex);
9542 		mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9543 		mptsas_doneq_add(mpt, cmd);
9544 		mutex_enter(&mpt->m_tx_waitq_mutex);
9545 	}
9546 	mutex_exit(&mpt->m_tx_waitq_mutex);
9547 
9548 	/*
9549 	 * Drain the taskqs prior to reallocating resources. The thread
9550 	 * passing through here could be launched from either (dr)
9551 	 * or (event) taskqs so only wait on the 'other' queue since
9552 	 * waiting on 'this' queue is a deadlock condition.
9553 	 */
9554 	mutex_exit(&mpt->m_mutex);
9555 	if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread))
9556 		ddi_taskq_wait(mpt->m_event_taskq);
9557 	if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread))
9558 		ddi_taskq_wait(mpt->m_dr_taskq);
9559 
9560 	mutex_enter(&mpt->m_mutex);
9561 }
9562 
9563 /*
9564  * set pkt_reason and OR in pkt_statistics flag
9565  */
9566 static void
9567 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
9568     uint_t stat)
9569 {
9570 #ifndef __lock_lint
9571 	_NOTE(ARGUNUSED(mpt))
9572 #endif
9573 
9574 	NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
9575 	    (void *)cmd, reason, stat));
9576 
9577 	if (cmd) {
9578 		if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
9579 			cmd->cmd_pkt->pkt_reason = reason;
9580 		}
9581 		cmd->cmd_pkt->pkt_statistics |= stat;
9582 	}
9583 }
9584 
9585 static void
9586 mptsas_start_watch_reset_delay()
9587 {
9588 	NDBG22(("mptsas_start_watch_reset_delay"));
9589 
9590 	mutex_enter(&mptsas_global_mutex);
9591 	if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
9592 		mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
9593 		    drv_usectohz((clock_t)
9594 		    MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
9595 		ASSERT(mptsas_reset_watch != NULL);
9596 	}
9597 	mutex_exit(&mptsas_global_mutex);
9598 }
9599 
9600 static void
9601 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
9602 {
9603 	mptsas_target_t	*ptgt = NULL;
9604 
9605 	ASSERT(MUTEX_HELD(&mpt->m_mutex));
9606 
9607 	NDBG22(("mptsas_setup_bus_reset_delay"));
9608 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9609 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
9610 		mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9611 		ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9612 	}
9613 
9614 	mptsas_start_watch_reset_delay();
9615 }
9616 
9617 /*
9618  * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
9619  * mpt instance for active reset delays
9620  */
9621 static void
9622 mptsas_watch_reset_delay(void *arg)
9623 {
9624 #ifndef __lock_lint
9625 	_NOTE(ARGUNUSED(arg))
9626 #endif
9627 
9628 	mptsas_t	*mpt;
9629 	int		not_done = 0;
9630 
9631 	NDBG22(("mptsas_watch_reset_delay"));
9632 
9633 	mutex_enter(&mptsas_global_mutex);
9634 	mptsas_reset_watch = 0;
9635 	mutex_exit(&mptsas_global_mutex);
9636 	rw_enter(&mptsas_global_rwlock, RW_READER);
9637 	for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
9638 		if (mpt->m_tran == 0) {
9639 			continue;
9640 		}
9641 		mutex_enter(&mpt->m_mutex);
9642 		not_done += mptsas_watch_reset_delay_subr(mpt);
9643 		mutex_exit(&mpt->m_mutex);
9644 	}
9645 	rw_exit(&mptsas_global_rwlock);
9646 
9647 	if (not_done) {
9648 		mptsas_start_watch_reset_delay();
9649 	}
9650 }
9651 
9652 static int
9653 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
9654 {
9655 	int		done = 0;
9656 	int		restart = 0;
9657 	mptsas_target_t	*ptgt = NULL;
9658 
9659 	NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
9660 
9661 	ASSERT(mutex_owned(&mpt->m_mutex));
9662 
9663 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9664 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
9665 		if (ptgt->m_reset_delay != 0) {
9666 			ptgt->m_reset_delay -=
9667 			    MPTSAS_WATCH_RESET_DELAY_TICK;
9668 			if (ptgt->m_reset_delay <= 0) {
9669 				ptgt->m_reset_delay = 0;
9670 				mptsas_set_throttle(mpt, ptgt,
9671 				    MAX_THROTTLE);
9672 				restart++;
9673 			} else {
9674 				done = -1;
9675 			}
9676 		}
9677 	}
9678 
9679 	if (restart > 0) {
9680 		mptsas_restart_hba(mpt);
9681 	}
9682 	return (done);
9683 }
9684 
9685 #ifdef MPTSAS_TEST
9686 static void
9687 mptsas_test_reset(mptsas_t *mpt, int target)
9688 {
9689 	mptsas_target_t    *ptgt = NULL;
9690 
9691 	if (mptsas_rtest == target) {
9692 		if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
9693 			mptsas_rtest = -1;
9694 		}
9695 		if (mptsas_rtest == -1) {
9696 			NDBG22(("mptsas_test_reset success"));
9697 		}
9698 	}
9699 }
9700 #endif
9701 
9702 /*
9703  * abort handling:
9704  *
9705  * Notes:
9706  *	- if pkt is not NULL, abort just that command
9707  *	- if pkt is NULL, abort all outstanding commands for target
9708  */
9709 static int
9710 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
9711 {
9712 	mptsas_t		*mpt = ADDR2MPT(ap);
9713 	int			rval;
9714 	mptsas_tgt_private_t	*tgt_private;
9715 	int			target, lun;
9716 
9717 	tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
9718 	    tran_tgt_private;
9719 	ASSERT(tgt_private != NULL);
9720 	target = tgt_private->t_private->m_devhdl;
9721 	lun = tgt_private->t_lun;
9722 
9723 	NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
9724 
9725 	mutex_enter(&mpt->m_mutex);
9726 	rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
9727 	mutex_exit(&mpt->m_mutex);
9728 	return (rval);
9729 }
9730 
9731 static int
9732 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
9733 {
9734 	mptsas_cmd_t	*sp = NULL;
9735 	mptsas_slots_t	*slots = mpt->m_active;
9736 	int		rval = FALSE;
9737 
9738 	ASSERT(mutex_owned(&mpt->m_mutex));
9739 
9740 	/*
9741 	 * Abort the command pkt on the target/lun in ap.  If pkt is
9742 	 * NULL, abort all outstanding commands on that target/lun.
9743 	 * If you can abort them, return 1, else return 0.
9744 	 * Each packet that's aborted should be sent back to the target
9745 	 * driver through the callback routine, with pkt_reason set to
9746 	 * CMD_ABORTED.
9747 	 *
9748 	 * abort cmd pkt on HBA hardware; clean out of outstanding
9749 	 * command lists, etc.
9750 	 */
9751 	if (pkt != NULL) {
9752 		/* abort the specified packet */
9753 		sp = PKT2CMD(pkt);
9754 
9755 		if (sp->cmd_queued) {
9756 			NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
9757 			    (void *)sp));
9758 			mptsas_waitq_delete(mpt, sp);
9759 			mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
9760 			    STAT_ABORTED);
9761 			mptsas_doneq_add(mpt, sp);
9762 			rval = TRUE;
9763 			goto done;
9764 		}
9765 
9766 		/*
9767 		 * Have mpt firmware abort this command
9768 		 */
9769 
9770 		if (slots->m_slot[sp->cmd_slot] != NULL) {
9771 			rval = mptsas_ioc_task_management(mpt,
9772 			    MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
9773 			    lun, NULL, 0, 0);
9774 
9775 			/*
9776 			 * The transport layer expects only TRUE and FALSE.
9777 			 * Therefore, if mptsas_ioc_task_management returns
9778 			 * FAILED we will return FALSE.
9779 			 */
9780 			if (rval == FAILED)
9781 				rval = FALSE;
9782 			goto done;
9783 		}
9784 	}
9785 
9786 	/*
9787 	 * If pkt is NULL then abort task set
9788 	 */
9789 	rval = mptsas_ioc_task_management(mpt,
9790 	    MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
9791 
9792 	/*
9793 	 * The transport layer expects only TRUE and FALSE.
9794 	 * Therefore, if mptsas_ioc_task_management returns
9795 	 * FAILED we will return FALSE.
9796 	 */
9797 	if (rval == FAILED)
9798 		rval = FALSE;
9799 
9800 #ifdef MPTSAS_TEST
9801 	if (rval && mptsas_test_stop) {
9802 		debug_enter("mptsas_do_scsi_abort");
9803 	}
9804 #endif
9805 
9806 done:
9807 	mptsas_doneq_empty(mpt);
9808 	return (rval);
9809 }
9810 
9811 /*
9812  * capability handling:
9813  * (*tran_getcap).  Get the capability named, and return its value.
9814  */
9815 static int
9816 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9817 {
9818 	mptsas_t	*mpt = ADDR2MPT(ap);
9819 	int		ckey;
9820 	int		rval = FALSE;
9821 
9822 	NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9823 	    ap->a_target, cap, tgtonly));
9824 
9825 	mutex_enter(&mpt->m_mutex);
9826 
9827 	if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9828 		mutex_exit(&mpt->m_mutex);
9829 		return (UNDEFINED);
9830 	}
9831 
9832 	switch (ckey) {
9833 	case SCSI_CAP_DMA_MAX:
9834 		rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9835 		break;
9836 	case SCSI_CAP_ARQ:
9837 		rval = TRUE;
9838 		break;
9839 	case SCSI_CAP_MSG_OUT:
9840 	case SCSI_CAP_PARITY:
9841 	case SCSI_CAP_UNTAGGED_QING:
9842 		rval = TRUE;
9843 		break;
9844 	case SCSI_CAP_TAGGED_QING:
9845 		rval = TRUE;
9846 		break;
9847 	case SCSI_CAP_RESET_NOTIFICATION:
9848 		rval = TRUE;
9849 		break;
9850 	case SCSI_CAP_LINKED_CMDS:
9851 		rval = FALSE;
9852 		break;
9853 	case SCSI_CAP_QFULL_RETRIES:
9854 		rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9855 		    tran_tgt_private))->t_private->m_qfull_retries;
9856 		break;
9857 	case SCSI_CAP_QFULL_RETRY_INTERVAL:
9858 		rval = drv_hztousec(((mptsas_tgt_private_t *)
9859 		    (ap->a_hba_tran->tran_tgt_private))->
9860 		    t_private->m_qfull_retry_interval) / 1000;
9861 		break;
9862 	case SCSI_CAP_CDB_LEN:
9863 		rval = CDB_GROUP4;
9864 		break;
9865 	case SCSI_CAP_INTERCONNECT_TYPE:
9866 		rval = INTERCONNECT_SAS;
9867 		break;
9868 	case SCSI_CAP_TRAN_LAYER_RETRIES:
9869 		if (mpt->m_ioc_capabilities &
9870 		    MPI2_IOCFACTS_CAPABILITY_TLR)
9871 			rval = TRUE;
9872 		else
9873 			rval = FALSE;
9874 		break;
9875 	default:
9876 		rval = UNDEFINED;
9877 		break;
9878 	}
9879 
9880 	NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9881 
9882 	mutex_exit(&mpt->m_mutex);
9883 	return (rval);
9884 }
9885 
9886 /*
9887  * (*tran_setcap).  Set the capability named to the value given.
9888  */
9889 static int
9890 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9891 {
9892 	mptsas_t	*mpt = ADDR2MPT(ap);
9893 	int		ckey;
9894 	int		rval = FALSE;
9895 
9896 	NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9897 	    ap->a_target, cap, value, tgtonly));
9898 
9899 	if (!tgtonly) {
9900 		return (rval);
9901 	}
9902 
9903 	mutex_enter(&mpt->m_mutex);
9904 
9905 	if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9906 		mutex_exit(&mpt->m_mutex);
9907 		return (UNDEFINED);
9908 	}
9909 
9910 	switch (ckey) {
9911 	case SCSI_CAP_DMA_MAX:
9912 	case SCSI_CAP_MSG_OUT:
9913 	case SCSI_CAP_PARITY:
9914 	case SCSI_CAP_INITIATOR_ID:
9915 	case SCSI_CAP_LINKED_CMDS:
9916 	case SCSI_CAP_UNTAGGED_QING:
9917 	case SCSI_CAP_RESET_NOTIFICATION:
9918 		/*
9919 		 * None of these are settable via
9920 		 * the capability interface.
9921 		 */
9922 		break;
9923 	case SCSI_CAP_ARQ:
9924 		/*
9925 		 * We cannot turn off arq so return false if asked to
9926 		 */
9927 		if (value) {
9928 			rval = TRUE;
9929 		} else {
9930 			rval = FALSE;
9931 		}
9932 		break;
9933 	case SCSI_CAP_TAGGED_QING:
9934 		mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9935 		    (ap->a_hba_tran->tran_tgt_private))->t_private,
9936 		    MAX_THROTTLE);
9937 		rval = TRUE;
9938 		break;
9939 	case SCSI_CAP_QFULL_RETRIES:
9940 		((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9941 		    t_private->m_qfull_retries = (uchar_t)value;
9942 		rval = TRUE;
9943 		break;
9944 	case SCSI_CAP_QFULL_RETRY_INTERVAL:
9945 		((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9946 		    t_private->m_qfull_retry_interval =
9947 		    drv_usectohz(value * 1000);
9948 		rval = TRUE;
9949 		break;
9950 	default:
9951 		rval = UNDEFINED;
9952 		break;
9953 	}
9954 	mutex_exit(&mpt->m_mutex);
9955 	return (rval);
9956 }
9957 
9958 /*
9959  * Utility routine for mptsas_ifsetcap/ifgetcap
9960  */
9961 /*ARGSUSED*/
9962 static int
9963 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9964 {
9965 	NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9966 
9967 	if (!cap)
9968 		return (FALSE);
9969 
9970 	*cidxp = scsi_hba_lookup_capstr(cap);
9971 	return (TRUE);
9972 }
9973 
9974 static int
9975 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9976 {
9977 	mptsas_slots_t	*old_active = mpt->m_active;
9978 	mptsas_slots_t	*new_active;
9979 	size_t		size;
9980 
9981 	/*
9982 	 * if there are active commands, then we cannot
9983 	 * change size of active slots array.
9984 	 */
9985 	ASSERT(mpt->m_ncmds == 0);
9986 
9987 	size = MPTSAS_SLOTS_SIZE(mpt);
9988 	new_active = kmem_zalloc(size, flag);
9989 	if (new_active == NULL) {
9990 		NDBG1(("new active alloc failed"));
9991 		return (-1);
9992 	}
9993 	/*
9994 	 * Since SMID 0 is reserved and the TM slot is reserved, the
9995 	 * number of slots that can be used at any one time is
9996 	 * m_max_requests - 2.
9997 	 */
9998 	new_active->m_n_normal = (mpt->m_max_requests - 2);
9999 	new_active->m_size = size;
10000 	new_active->m_rotor = 1;
10001 	if (old_active)
10002 		mptsas_free_active_slots(mpt);
10003 	mpt->m_active = new_active;
10004 
10005 	return (0);
10006 }
10007 
10008 static void
10009 mptsas_free_active_slots(mptsas_t *mpt)
10010 {
10011 	mptsas_slots_t	*active = mpt->m_active;
10012 	size_t		size;
10013 
10014 	if (active == NULL)
10015 		return;
10016 	size = active->m_size;
10017 	kmem_free(active, size);
10018 	mpt->m_active = NULL;
10019 }
10020 
10021 /*
10022  * Error logging, printing, and debug print routines.
10023  */
10024 static char *mptsas_label = "mpt_sas";
10025 
10026 /*PRINTFLIKE3*/
10027 void
10028 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
10029 {
10030 	dev_info_t	*dev;
10031 	va_list		ap;
10032 
10033 	if (mpt) {
10034 		dev = mpt->m_dip;
10035 	} else {
10036 		dev = 0;
10037 	}
10038 
10039 	mutex_enter(&mptsas_log_mutex);
10040 
10041 	va_start(ap, fmt);
10042 	(void) vsprintf(mptsas_log_buf, fmt, ap);
10043 	va_end(ap);
10044 
10045 	if (level == CE_CONT) {
10046 		scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
10047 	} else {
10048 		scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
10049 	}
10050 
10051 	mutex_exit(&mptsas_log_mutex);
10052 }
10053 
10054 #ifdef MPTSAS_DEBUG
10055 /*
10056  * Use a circular buffer to log messages to private memory.
10057  * Increment idx atomically to minimize risk to miss lines.
10058  * It's fast and does not hold up the proceedings too much.
10059  */
10060 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT;
10061 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN;
10062 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN];
10063 static uint32_t mptsas_dbglog_idx = 0;
10064 
10065 /*PRINTFLIKE1*/
10066 void
10067 mptsas_debug_log(char *fmt, ...)
10068 {
10069 	va_list		ap;
10070 	uint32_t	idx;
10071 
10072 	idx = atomic_inc_32_nv(&mptsas_dbglog_idx) &
10073 	    (mptsas_dbglog_linecnt - 1);
10074 
10075 	va_start(ap, fmt);
10076 	(void) vsnprintf(mptsas_dbglog_bufs[idx],
10077 	    mptsas_dbglog_linelen, fmt, ap);
10078 	va_end(ap);
10079 }
10080 
10081 /*PRINTFLIKE1*/
10082 void
10083 mptsas_printf(char *fmt, ...)
10084 {
10085 	dev_info_t	*dev = 0;
10086 	va_list		ap;
10087 
10088 	mutex_enter(&mptsas_log_mutex);
10089 
10090 	va_start(ap, fmt);
10091 	(void) vsprintf(mptsas_log_buf, fmt, ap);
10092 	va_end(ap);
10093 
10094 #ifdef PROM_PRINTF
10095 	prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
10096 #else
10097 	scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf);
10098 #endif
10099 	mutex_exit(&mptsas_log_mutex);
10100 }
10101 #endif
10102 
10103 /*
10104  * timeout handling
10105  */
10106 static void
10107 mptsas_watch(void *arg)
10108 {
10109 #ifndef __lock_lint
10110 	_NOTE(ARGUNUSED(arg))
10111 #endif
10112 
10113 	mptsas_t	*mpt;
10114 	uint32_t	doorbell;
10115 
10116 	NDBG30(("mptsas_watch"));
10117 
10118 	rw_enter(&mptsas_global_rwlock, RW_READER);
10119 	for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
10120 
10121 		mutex_enter(&mpt->m_mutex);
10122 
10123 		/* Skip device if not powered on */
10124 		if (mpt->m_options & MPTSAS_OPT_PM) {
10125 			if (mpt->m_power_level == PM_LEVEL_D0) {
10126 				(void) pm_busy_component(mpt->m_dip, 0);
10127 				mpt->m_busy = 1;
10128 			} else {
10129 				mutex_exit(&mpt->m_mutex);
10130 				continue;
10131 			}
10132 		}
10133 
10134 		/*
10135 		 * Check if controller is in a FAULT state. If so, reset it.
10136 		 */
10137 		doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
10138 		if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
10139 			doorbell &= MPI2_DOORBELL_DATA_MASK;
10140 			mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
10141 			    "code: %04x", doorbell);
10142 			mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
10143 			if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10144 				mptsas_log(mpt, CE_WARN, "Reset failed"
10145 				    "after fault was detected");
10146 			}
10147 		}
10148 
10149 		/*
10150 		 * For now, always call mptsas_watchsubr.
10151 		 */
10152 		mptsas_watchsubr(mpt);
10153 
10154 		if (mpt->m_options & MPTSAS_OPT_PM) {
10155 			mpt->m_busy = 0;
10156 			(void) pm_idle_component(mpt->m_dip, 0);
10157 		}
10158 
10159 		mutex_exit(&mpt->m_mutex);
10160 	}
10161 	rw_exit(&mptsas_global_rwlock);
10162 
10163 	mutex_enter(&mptsas_global_mutex);
10164 	if (mptsas_timeouts_enabled)
10165 		mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
10166 	mutex_exit(&mptsas_global_mutex);
10167 }
10168 
10169 static void
10170 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp)
10171 {
10172 	mptsas_cmd_t	*cmd;
10173 
10174 	/*
10175 	 * If we were draining due to a qfull condition,
10176 	 * go back to full throttle.
10177 	 */
10178 	if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
10179 	    (ptgt->m_t_throttle > HOLD_THROTTLE) &&
10180 	    (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
10181 		mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10182 		mptsas_restart_hba(mpt);
10183 	}
10184 
10185 	cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq);
10186 	if (cmd == NULL)
10187 		return;
10188 
10189 	if (cmd->cmd_active_expiration <= timestamp) {
10190 		/*
10191 		 * Earliest command timeout expired. Drain throttle.
10192 		 */
10193 		mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10194 
10195 		/*
10196 		 * Check for remaining commands.
10197 		 */
10198 		cmd = TAILQ_FIRST(&ptgt->m_active_cmdq);
10199 		if (cmd->cmd_active_expiration > timestamp) {
10200 			/*
10201 			 * Wait for remaining commands to complete or
10202 			 * time out.
10203 			 */
10204 			NDBG23(("command timed out, pending drain"));
10205 			return;
10206 		}
10207 
10208 		/*
10209 		 * All command timeouts expired.
10210 		 */
10211 		mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds "
10212 		    "expired with %d commands on target %d lun %d.",
10213 		    cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds,
10214 		    ptgt->m_devhdl, Lun(cmd));
10215 
10216 		mptsas_cmd_timeout(mpt, ptgt);
10217 	} else if (cmd->cmd_active_expiration <=
10218 	    timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) {
10219 		NDBG23(("pending timeout"));
10220 		mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10221 	}
10222 }
10223 
10224 static void
10225 mptsas_watchsubr(mptsas_t *mpt)
10226 {
10227 	int		i;
10228 	mptsas_cmd_t	*cmd;
10229 	mptsas_target_t	*ptgt = NULL;
10230 	hrtime_t	timestamp = gethrtime();
10231 
10232 	ASSERT(MUTEX_HELD(&mpt->m_mutex));
10233 
10234 	NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
10235 
10236 #ifdef MPTSAS_TEST
10237 	if (mptsas_enable_untagged) {
10238 		mptsas_test_untagged++;
10239 	}
10240 #endif
10241 
10242 	/*
10243 	 * Check for commands stuck in active slot
10244 	 * Account for TM requests, which use the last SMID.
10245 	 */
10246 	for (i = 0; i <= mpt->m_active->m_n_normal; i++) {
10247 		if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
10248 			if (cmd->cmd_active_expiration <= timestamp) {
10249 				if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
10250 					/*
10251 					 * There seems to be a command stuck
10252 					 * in the active slot.  Drain throttle.
10253 					 */
10254 					mptsas_set_throttle(mpt,
10255 					    cmd->cmd_tgt_addr,
10256 					    DRAIN_THROTTLE);
10257 				} else if (cmd->cmd_flags &
10258 				    (CFLAG_PASSTHRU | CFLAG_CONFIG |
10259 				    CFLAG_FW_DIAG)) {
10260 					/*
10261 					 * passthrough command timeout
10262 					 */
10263 					cmd->cmd_flags |= (CFLAG_FINISHED |
10264 					    CFLAG_TIMEOUT);
10265 					cv_broadcast(&mpt->m_passthru_cv);
10266 					cv_broadcast(&mpt->m_config_cv);
10267 					cv_broadcast(&mpt->m_fw_diag_cv);
10268 				}
10269 			}
10270 		}
10271 	}
10272 
10273 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10274 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
10275 		mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10276 	}
10277 
10278 	for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL;
10279 	    ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) {
10280 		mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10281 	}
10282 }
10283 
10284 /*
10285  * timeout recovery
10286  */
10287 static void
10288 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt)
10289 {
10290 	uint16_t	devhdl;
10291 	uint64_t	sas_wwn;
10292 	uint8_t		phy;
10293 	char		wwn_str[MPTSAS_WWN_STRLEN];
10294 
10295 	devhdl = ptgt->m_devhdl;
10296 	sas_wwn = ptgt->m_addr.mta_wwn;
10297 	phy = ptgt->m_phynum;
10298 	if (sas_wwn == 0) {
10299 		(void) sprintf(wwn_str, "p%x", phy);
10300 	} else {
10301 		(void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
10302 	}
10303 
10304 	NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
10305 	mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
10306 	    "target %d %s, enclosure %u", devhdl, wwn_str,
10307 	    ptgt->m_enclosure);
10308 
10309 	/*
10310 	 * Abort all outstanding commands on the device.
10311 	 */
10312 	NDBG29(("mptsas_cmd_timeout: device reset"));
10313 	if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
10314 		mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
10315 		    "recovery failed!", devhdl);
10316 	}
10317 }
10318 
10319 /*
10320  * Device / Hotplug control
10321  */
10322 static int
10323 mptsas_scsi_quiesce(dev_info_t *dip)
10324 {
10325 	mptsas_t	*mpt;
10326 	scsi_hba_tran_t	*tran;
10327 
10328 	tran = ddi_get_driver_private(dip);
10329 	if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10330 		return (-1);
10331 
10332 	return (mptsas_quiesce_bus(mpt));
10333 }
10334 
10335 static int
10336 mptsas_scsi_unquiesce(dev_info_t *dip)
10337 {
10338 	mptsas_t		*mpt;
10339 	scsi_hba_tran_t	*tran;
10340 
10341 	tran = ddi_get_driver_private(dip);
10342 	if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10343 		return (-1);
10344 
10345 	return (mptsas_unquiesce_bus(mpt));
10346 }
10347 
10348 static int
10349 mptsas_quiesce_bus(mptsas_t *mpt)
10350 {
10351 	mptsas_target_t	*ptgt = NULL;
10352 
10353 	NDBG28(("mptsas_quiesce_bus"));
10354 	mutex_enter(&mpt->m_mutex);
10355 
10356 	/* Set all the throttles to zero */
10357 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10358 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
10359 		mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10360 	}
10361 
10362 	/* If there are any outstanding commands in the queue */
10363 	if (mpt->m_ncmds) {
10364 		mpt->m_softstate |= MPTSAS_SS_DRAINING;
10365 		mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10366 		    mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
10367 		if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
10368 			/*
10369 			 * Quiesce has been interrupted
10370 			 */
10371 			mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10372 			for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10373 			    ptgt = refhash_next(mpt->m_targets, ptgt)) {
10374 				mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10375 			}
10376 			mptsas_restart_hba(mpt);
10377 			if (mpt->m_quiesce_timeid != 0) {
10378 				timeout_id_t tid = mpt->m_quiesce_timeid;
10379 				mpt->m_quiesce_timeid = 0;
10380 				mutex_exit(&mpt->m_mutex);
10381 				(void) untimeout(tid);
10382 				return (-1);
10383 			}
10384 			mutex_exit(&mpt->m_mutex);
10385 			return (-1);
10386 		} else {
10387 			/* Bus has been quiesced */
10388 			ASSERT(mpt->m_quiesce_timeid == 0);
10389 			mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10390 			mpt->m_softstate |= MPTSAS_SS_QUIESCED;
10391 			mutex_exit(&mpt->m_mutex);
10392 			return (0);
10393 		}
10394 	}
10395 	/* Bus was not busy - QUIESCED */
10396 	mutex_exit(&mpt->m_mutex);
10397 
10398 	return (0);
10399 }
10400 
10401 static int
10402 mptsas_unquiesce_bus(mptsas_t *mpt)
10403 {
10404 	mptsas_target_t	*ptgt = NULL;
10405 
10406 	NDBG28(("mptsas_unquiesce_bus"));
10407 	mutex_enter(&mpt->m_mutex);
10408 	mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
10409 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10410 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
10411 		mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10412 	}
10413 	mptsas_restart_hba(mpt);
10414 	mutex_exit(&mpt->m_mutex);
10415 	return (0);
10416 }
10417 
10418 static void
10419 mptsas_ncmds_checkdrain(void *arg)
10420 {
10421 	mptsas_t	*mpt = arg;
10422 	mptsas_target_t	*ptgt = NULL;
10423 
10424 	mutex_enter(&mpt->m_mutex);
10425 	if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
10426 		mpt->m_quiesce_timeid = 0;
10427 		if (mpt->m_ncmds == 0) {
10428 			/* Command queue has been drained */
10429 			cv_signal(&mpt->m_cv);
10430 		} else {
10431 			/*
10432 			 * The throttle may have been reset because
10433 			 * of a SCSI bus reset
10434 			 */
10435 			for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10436 			    ptgt = refhash_next(mpt->m_targets, ptgt)) {
10437 				mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10438 			}
10439 
10440 			mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10441 			    mpt, (MPTSAS_QUIESCE_TIMEOUT *
10442 			    drv_usectohz(1000000)));
10443 		}
10444 	}
10445 	mutex_exit(&mpt->m_mutex);
10446 }
10447 
10448 /*ARGSUSED*/
10449 static void
10450 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
10451 {
10452 	int	i;
10453 	uint8_t	*cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
10454 	char	buf[128];
10455 
10456 	buf[0] = '\0';
10457 	NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
10458 	    Tgt(cmd), Lun(cmd)));
10459 	(void) sprintf(&buf[0], "\tcdb=[");
10460 	for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
10461 		(void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
10462 	}
10463 	(void) sprintf(&buf[strlen(buf)], " ]");
10464 	NDBG25(("?%s\n", buf));
10465 	NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
10466 	    cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
10467 	    cmd->cmd_pkt->pkt_state));
10468 	NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
10469 	    *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
10470 }
10471 
10472 static void
10473 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10474     pMpi2SGESimple64_t sgep)
10475 {
10476 	uint32_t		sge_flags;
10477 	uint32_t		data_size, dataout_size;
10478 	ddi_dma_cookie_t	data_cookie;
10479 	ddi_dma_cookie_t	dataout_cookie;
10480 
10481 	data_size = pt->data_size;
10482 	dataout_size = pt->dataout_size;
10483 	data_cookie = pt->data_cookie;
10484 	dataout_cookie = pt->dataout_cookie;
10485 
10486 	if (dataout_size) {
10487 		sge_flags = dataout_size |
10488 		    ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10489 		    MPI2_SGE_FLAGS_END_OF_BUFFER |
10490 		    MPI2_SGE_FLAGS_HOST_TO_IOC |
10491 		    MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10492 		    MPI2_SGE_FLAGS_SHIFT);
10493 		ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10494 		ddi_put32(acc_hdl, &sgep->Address.Low,
10495 		    (uint32_t)(dataout_cookie.dmac_laddress &
10496 		    0xffffffffull));
10497 		ddi_put32(acc_hdl, &sgep->Address.High,
10498 		    (uint32_t)(dataout_cookie.dmac_laddress
10499 		    >> 32));
10500 		sgep++;
10501 	}
10502 	sge_flags = data_size;
10503 	sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10504 	    MPI2_SGE_FLAGS_LAST_ELEMENT |
10505 	    MPI2_SGE_FLAGS_END_OF_BUFFER |
10506 	    MPI2_SGE_FLAGS_END_OF_LIST |
10507 	    MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10508 	    MPI2_SGE_FLAGS_SHIFT);
10509 	if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10510 		sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10511 		    MPI2_SGE_FLAGS_SHIFT);
10512 	} else {
10513 		sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10514 		    MPI2_SGE_FLAGS_SHIFT);
10515 	}
10516 	ddi_put32(acc_hdl, &sgep->FlagsLength,
10517 	    sge_flags);
10518 	ddi_put32(acc_hdl, &sgep->Address.Low,
10519 	    (uint32_t)(data_cookie.dmac_laddress &
10520 	    0xffffffffull));
10521 	ddi_put32(acc_hdl, &sgep->Address.High,
10522 	    (uint32_t)(data_cookie.dmac_laddress >> 32));
10523 }
10524 
10525 static void
10526 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10527     pMpi2IeeeSgeSimple64_t ieeesgep)
10528 {
10529 	uint8_t			sge_flags;
10530 	uint32_t		data_size, dataout_size;
10531 	ddi_dma_cookie_t	data_cookie;
10532 	ddi_dma_cookie_t	dataout_cookie;
10533 
10534 	data_size = pt->data_size;
10535 	dataout_size = pt->dataout_size;
10536 	data_cookie = pt->data_cookie;
10537 	dataout_cookie = pt->dataout_cookie;
10538 
10539 	sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
10540 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
10541 	if (dataout_size) {
10542 		ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size);
10543 		ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10544 		    (uint32_t)(dataout_cookie.dmac_laddress &
10545 		    0xffffffffull));
10546 		ddi_put32(acc_hdl, &ieeesgep->Address.High,
10547 		    (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10548 		ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10549 		ieeesgep++;
10550 	}
10551 	sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
10552 	ddi_put32(acc_hdl, &ieeesgep->Length, data_size);
10553 	ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10554 	    (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10555 	ddi_put32(acc_hdl, &ieeesgep->Address.High,
10556 	    (uint32_t)(data_cookie.dmac_laddress >> 32));
10557 	ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10558 }
10559 
10560 static void
10561 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
10562 {
10563 	caddr_t			memp;
10564 	pMPI2RequestHeader_t	request_hdrp;
10565 	struct scsi_pkt		*pkt = cmd->cmd_pkt;
10566 	mptsas_pt_request_t	*pt = pkt->pkt_ha_private;
10567 	uint32_t		request_size;
10568 	uint32_t		i;
10569 	uint64_t		request_desc = 0;
10570 	uint8_t			desc_type;
10571 	uint16_t		SMID;
10572 	uint8_t			*request, function;
10573 	ddi_dma_handle_t	dma_hdl = mpt->m_dma_req_frame_hdl;
10574 	ddi_acc_handle_t	acc_hdl = mpt->m_acc_req_frame_hdl;
10575 
10576 	desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10577 
10578 	request = pt->request;
10579 	request_size = pt->request_size;
10580 
10581 	SMID = cmd->cmd_slot;
10582 
10583 	/*
10584 	 * Store the passthrough message in memory location
10585 	 * corresponding to our slot number
10586 	 */
10587 	memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
10588 	request_hdrp = (pMPI2RequestHeader_t)memp;
10589 	bzero(memp, mpt->m_req_frame_size);
10590 
10591 	for (i = 0; i < request_size; i++) {
10592 		bcopy(request + i, memp + i, 1);
10593 	}
10594 
10595 	NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, "
10596 	    "size=%d, in %d, out %d, SMID %d", request_hdrp->Function,
10597 	    request_hdrp->MsgFlags, request_size,
10598 	    pt->data_size, pt->dataout_size, SMID));
10599 
10600 	/*
10601 	 * Add an SGE, even if the length is zero.
10602 	 */
10603 	if (mpt->m_MPI25 && pt->simple == 0) {
10604 		mptsas_passthru_ieee_sge(acc_hdl, pt,
10605 		    (pMpi2IeeeSgeSimple64_t)
10606 		    ((uint8_t *)request_hdrp + pt->sgl_offset));
10607 	} else {
10608 		mptsas_passthru_sge(acc_hdl, pt,
10609 		    (pMpi2SGESimple64_t)
10610 		    ((uint8_t *)request_hdrp + pt->sgl_offset));
10611 	}
10612 
10613 	function = request_hdrp->Function;
10614 	if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10615 	    (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10616 		pMpi2SCSIIORequest_t	scsi_io_req;
10617 		caddr_t			arsbuf;
10618 		uint8_t			ars_size;
10619 		uint32_t		ars_dmaaddrlow;
10620 
10621 		NDBG15(("mptsas_start_passthru: Is SCSI IO Req"));
10622 		scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
10623 
10624 		if (cmd->cmd_extrqslen != 0) {
10625 			/*
10626 			 * Mapping of the buffer was done in
10627 			 * mptsas_do_passthru().
10628 			 * Calculate the DMA address with the same offset.
10629 			 */
10630 			arsbuf = cmd->cmd_arq_buf;
10631 			ars_size = cmd->cmd_extrqslen;
10632 			ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10633 			    ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
10634 			    0xffffffffu;
10635 		} else {
10636 			arsbuf = mpt->m_req_sense +
10637 			    (mpt->m_req_sense_size * (SMID-1));
10638 			cmd->cmd_arq_buf = arsbuf;
10639 			ars_size = mpt->m_req_sense_size;
10640 			ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10641 			    (mpt->m_req_sense_size * (SMID-1))) &
10642 			    0xffffffffu;
10643 		}
10644 		bzero(arsbuf, ars_size);
10645 
10646 		ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size);
10647 		ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress,
10648 		    ars_dmaaddrlow);
10649 
10650 		/*
10651 		 * Put SGE for data and data_out buffer at the end of
10652 		 * scsi_io_request message header.(64 bytes in total)
10653 		 * Set SGLOffset0 value
10654 		 */
10655 		ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
10656 		    offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
10657 
10658 		/*
10659 		 * Setup descriptor info.  RAID passthrough must use the
10660 		 * default request descriptor which is already set, so if this
10661 		 * is a SCSI IO request, change the descriptor to SCSI IO.
10662 		 */
10663 		if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
10664 			desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
10665 			request_desc = ((uint64_t)ddi_get16(acc_hdl,
10666 			    &scsi_io_req->DevHandle) << 48);
10667 		}
10668 		(void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
10669 		    DDI_DMA_SYNC_FORDEV);
10670 	}
10671 
10672 	/*
10673 	 * We must wait till the message has been completed before
10674 	 * beginning the next message so we wait for this one to
10675 	 * finish.
10676 	 */
10677 	(void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
10678 	request_desc |= (SMID << 16) + desc_type;
10679 	cmd->cmd_rfm = NULL;
10680 	MPTSAS_START_CMD(mpt, request_desc);
10681 	if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
10682 	    (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
10683 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10684 	}
10685 }
10686 
10687 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *);
10688 static mptsas_pre_f	mpi_pre_ioc_facts;
10689 static mptsas_pre_f	mpi_pre_port_facts;
10690 static mptsas_pre_f	mpi_pre_fw_download;
10691 static mptsas_pre_f	mpi_pre_fw_25_download;
10692 static mptsas_pre_f	mpi_pre_fw_upload;
10693 static mptsas_pre_f	mpi_pre_fw_25_upload;
10694 static mptsas_pre_f	mpi_pre_sata_passthrough;
10695 static mptsas_pre_f	mpi_pre_smp_passthrough;
10696 static mptsas_pre_f	mpi_pre_config;
10697 static mptsas_pre_f	mpi_pre_sas_io_unit_control;
10698 static mptsas_pre_f	mpi_pre_scsi_io_req;
10699 
10700 /*
10701  * Prepare the pt for a SAS2 FW_DOWNLOAD request.
10702  */
10703 static void
10704 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10705 {
10706 	pMpi2FWDownloadTCSGE_t tcsge;
10707 	pMpi2FWDownloadRequest req;
10708 
10709 	/*
10710 	 * If SAS3, call separate function.
10711 	 */
10712 	if (mpt->m_MPI25) {
10713 		mpi_pre_fw_25_download(mpt, pt);
10714 		return;
10715 	}
10716 
10717 	/*
10718 	 * User requests should come in with the Transaction
10719 	 * context element where the SGL will go. Putting the
10720 	 * SGL after that seems to work, but don't really know
10721 	 * why. Other drivers tend to create an extra SGL and
10722 	 * refer to the TCE through that.
10723 	 */
10724 	req = (pMpi2FWDownloadRequest)pt->request;
10725 	tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL;
10726 	if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10727 	    tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10728 		mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10729 	}
10730 
10731 	pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) +
10732 	    sizeof (*tcsge);
10733 	if (pt->request_size != pt->sgl_offset) {
10734 		NDBG15(("mpi_pre_fw_download(): Incorrect req size, "
10735 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10736 		    (int)pt->request_size, (int)pt->sgl_offset,
10737 		    (int)pt->dataout_size));
10738 	}
10739 	if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) {
10740 		NDBG15(("mpi_pre_fw_download(): Incorrect rep size, "
10741 		    "0x%x, should be 0x%x", pt->data_size,
10742 		    (int)sizeof (MPI2_FW_DOWNLOAD_REPLY)));
10743 	}
10744 }
10745 
10746 /*
10747  * Prepare the pt for a SAS3 FW_DOWNLOAD request.
10748  */
10749 static void
10750 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10751 {
10752 	pMpi2FWDownloadTCSGE_t tcsge;
10753 	pMpi2FWDownloadRequest req2;
10754 	pMpi25FWDownloadRequest req25;
10755 
10756 	/*
10757 	 * User requests should come in with the Transaction
10758 	 * context element where the SGL will go. The new firmware
10759 	 * Doesn't use TCE and has space in the main request for
10760 	 * this information. So move to the right place.
10761 	 */
10762 	req2 = (pMpi2FWDownloadRequest)pt->request;
10763 	req25 = (pMpi25FWDownloadRequest)pt->request;
10764 	tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL;
10765 	if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10766 	    tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10767 		mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10768 	}
10769 	req25->ImageOffset = tcsge->ImageOffset;
10770 	req25->ImageSize = tcsge->ImageSize;
10771 
10772 	pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL);
10773 	if (pt->request_size != pt->sgl_offset) {
10774 		NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, "
10775 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10776 		    pt->request_size, pt->sgl_offset,
10777 		    pt->dataout_size));
10778 	}
10779 	if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) {
10780 		NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, "
10781 		    "0x%x, should be 0x%x", pt->data_size,
10782 		    (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10783 	}
10784 }
10785 
10786 /*
10787  * Prepare the pt for a SAS2 FW_UPLOAD request.
10788  */
10789 static void
10790 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10791 {
10792 	pMpi2FWUploadTCSGE_t tcsge;
10793 	pMpi2FWUploadRequest_t req;
10794 
10795 	/*
10796 	 * If SAS3, call separate function.
10797 	 */
10798 	if (mpt->m_MPI25) {
10799 		mpi_pre_fw_25_upload(mpt, pt);
10800 		return;
10801 	}
10802 
10803 	/*
10804 	 * User requests should come in with the Transaction
10805 	 * context element where the SGL will go. Putting the
10806 	 * SGL after that seems to work, but don't really know
10807 	 * why. Other drivers tend to create an extra SGL and
10808 	 * refer to the TCE through that.
10809 	 */
10810 	req = (pMpi2FWUploadRequest_t)pt->request;
10811 	tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL;
10812 	if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10813 	    tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10814 		mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10815 	}
10816 
10817 	pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) +
10818 	    sizeof (*tcsge);
10819 	if (pt->request_size != pt->sgl_offset) {
10820 		NDBG15(("mpi_pre_fw_upload(): Incorrect req size, "
10821 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10822 		    pt->request_size, pt->sgl_offset,
10823 		    pt->dataout_size));
10824 	}
10825 	if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) {
10826 		NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, "
10827 		    "0x%x, should be 0x%x", pt->data_size,
10828 		    (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10829 	}
10830 }
10831 
10832 /*
10833  * Prepare the pt a SAS3 FW_UPLOAD request.
10834  */
10835 static void
10836 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10837 {
10838 	pMpi2FWUploadTCSGE_t tcsge;
10839 	pMpi2FWUploadRequest_t req2;
10840 	pMpi25FWUploadRequest_t req25;
10841 
10842 	/*
10843 	 * User requests should come in with the Transaction
10844 	 * context element where the SGL will go. The new firmware
10845 	 * Doesn't use TCE and has space in the main request for
10846 	 * this information. So move to the right place.
10847 	 */
10848 	req2 = (pMpi2FWUploadRequest_t)pt->request;
10849 	req25 = (pMpi25FWUploadRequest_t)pt->request;
10850 	tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL;
10851 	if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10852 	    tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10853 		mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10854 	}
10855 	req25->ImageOffset = tcsge->ImageOffset;
10856 	req25->ImageSize = tcsge->ImageSize;
10857 
10858 	pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL);
10859 	if (pt->request_size != pt->sgl_offset) {
10860 		NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, "
10861 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10862 		    pt->request_size, pt->sgl_offset,
10863 		    pt->dataout_size));
10864 	}
10865 	if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) {
10866 		NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, "
10867 		    "0x%x, should be 0x%x", pt->data_size,
10868 		    (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10869 	}
10870 }
10871 
10872 /*
10873  * Prepare the pt for an IOC_FACTS request.
10874  */
10875 static void
10876 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10877 {
10878 #ifndef __lock_lint
10879 	_NOTE(ARGUNUSED(mpt))
10880 #endif
10881 	if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) {
10882 		NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, "
10883 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10884 		    pt->request_size,
10885 		    (int)sizeof (MPI2_IOC_FACTS_REQUEST),
10886 		    pt->dataout_size));
10887 	}
10888 	if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) {
10889 		NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, "
10890 		    "0x%x, should be 0x%x", pt->data_size,
10891 		    (int)sizeof (MPI2_IOC_FACTS_REPLY)));
10892 	}
10893 	pt->sgl_offset = (uint16_t)pt->request_size;
10894 }
10895 
10896 /*
10897  * Prepare the pt for a PORT_FACTS request.
10898  */
10899 static void
10900 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10901 {
10902 #ifndef __lock_lint
10903 	_NOTE(ARGUNUSED(mpt))
10904 #endif
10905 	if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) {
10906 		NDBG15(("mpi_pre_port_facts(): Incorrect req size, "
10907 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10908 		    pt->request_size,
10909 		    (int)sizeof (MPI2_PORT_FACTS_REQUEST),
10910 		    pt->dataout_size));
10911 	}
10912 	if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) {
10913 		NDBG15(("mpi_pre_port_facts(): Incorrect rep size, "
10914 		    "0x%x, should be 0x%x", pt->data_size,
10915 		    (int)sizeof (MPI2_PORT_FACTS_REPLY)));
10916 	}
10917 	pt->sgl_offset = (uint16_t)pt->request_size;
10918 }
10919 
10920 /*
10921  * Prepare pt for a SATA_PASSTHROUGH request.
10922  */
10923 static void
10924 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10925 {
10926 #ifndef __lock_lint
10927 	_NOTE(ARGUNUSED(mpt))
10928 #endif
10929 	pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL);
10930 	if (pt->request_size != pt->sgl_offset) {
10931 		NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, "
10932 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10933 		    pt->request_size, pt->sgl_offset,
10934 		    pt->dataout_size));
10935 	}
10936 	if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) {
10937 		NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, "
10938 		    "0x%x, should be 0x%x", pt->data_size,
10939 		    (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY)));
10940 	}
10941 }
10942 
10943 static void
10944 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10945 {
10946 #ifndef __lock_lint
10947 	_NOTE(ARGUNUSED(mpt))
10948 #endif
10949 	pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL);
10950 	if (pt->request_size != pt->sgl_offset) {
10951 		NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, "
10952 		    "0x%x, should be 0x%x, dataoutsz 0x%x",
10953 		    pt->request_size, pt->sgl_offset,
10954 		    pt->dataout_size));
10955 	}
10956 	if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) {
10957 		NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, "
10958 		    "0x%x, should be 0x%x", pt->data_size,
10959 		    (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY)));
10960 	}
10961 }
10962 
10963 /*
10964  * Prepare pt for a CONFIG request.
10965  */
10966 static void
10967 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt)
10968 {
10969 #ifndef __lock_lint
10970 	_NOTE(ARGUNUSED(mpt))
10971 #endif
10972 	pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE);
10973 	if (pt->request_size != pt->sgl_offset) {
10974 		NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10975 		    "should be 0x%x, dataoutsz 0x%x", pt->request_size,
10976 		    pt->sgl_offset, pt->dataout_size));
10977 	}
10978 	if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) {
10979 		NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
10980 		    "should be 0x%x", pt->data_size,
10981 		    (int)sizeof (MPI2_CONFIG_REPLY)));
10982 	}
10983 	pt->simple = 1;
10984 }
10985 
10986 /*
10987  * Prepare pt for a SCSI_IO_REQ request.
10988  */
10989 static void
10990 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt)
10991 {
10992 #ifndef __lock_lint
10993 	_NOTE(ARGUNUSED(mpt))
10994 #endif
10995 	pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL);
10996 	if (pt->request_size != pt->sgl_offset) {
10997 		NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10998 		    "should be 0x%x, dataoutsz 0x%x", pt->request_size,
10999 		    pt->sgl_offset,
11000 		    pt->dataout_size));
11001 	}
11002 	if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) {
11003 		NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
11004 		    "should be 0x%x", pt->data_size,
11005 		    (int)sizeof (MPI2_SCSI_IO_REPLY)));
11006 	}
11007 }
11008 
11009 /*
11010  * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request.
11011  */
11012 static void
11013 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt)
11014 {
11015 #ifndef __lock_lint
11016 	_NOTE(ARGUNUSED(mpt))
11017 #endif
11018 	pt->sgl_offset = (uint16_t)pt->request_size;
11019 }
11020 
11021 /*
11022  * A set of functions to prepare an mptsas_cmd for the various
11023  * supported requests.
11024  */
11025 static struct mptsas_func {
11026 	U8		Function;
11027 	char		*Name;
11028 	mptsas_pre_f	*f_pre;
11029 } mptsas_func_list[] = {
11030 	{ MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS",		mpi_pre_ioc_facts },
11031 	{ MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS",	mpi_pre_port_facts },
11032 	{ MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD",	mpi_pre_fw_download },
11033 	{ MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD",		mpi_pre_fw_upload },
11034 	{ MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH",
11035 	    mpi_pre_sata_passthrough },
11036 	{ MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH",
11037 	    mpi_pre_smp_passthrough},
11038 	{ MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST",
11039 	    mpi_pre_scsi_io_req},
11040 	{ MPI2_FUNCTION_CONFIG, "CONFIG",		mpi_pre_config},
11041 	{ MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL",
11042 	    mpi_pre_sas_io_unit_control },
11043 	{ 0xFF, NULL,				NULL } /* list end */
11044 };
11045 
11046 static void
11047 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt)
11048 {
11049 	pMPI2RequestHeader_t	hdr;
11050 	struct mptsas_func	*f;
11051 
11052 	hdr = (pMPI2RequestHeader_t)pt->request;
11053 
11054 	for (f = mptsas_func_list; f->f_pre != NULL; f++) {
11055 		if (hdr->Function == f->Function) {
11056 			f->f_pre(mpt, pt);
11057 			NDBG15(("mptsas_prep_sgl_offset: Function %s,"
11058 			    " sgl_offset 0x%x", f->Name,
11059 			    pt->sgl_offset));
11060 			return;
11061 		}
11062 	}
11063 	NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x,"
11064 	    " returning req_size 0x%x for sgl_offset",
11065 	    hdr->Function, pt->request_size));
11066 	pt->sgl_offset = (uint16_t)pt->request_size;
11067 }
11068 
11069 
11070 static int
11071 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
11072     uint8_t *data, uint32_t request_size, uint32_t reply_size,
11073     uint32_t data_size, uint32_t direction, uint8_t *dataout,
11074     uint32_t dataout_size, short timeout, int mode)
11075 {
11076 	mptsas_pt_request_t		pt;
11077 	mptsas_dma_alloc_state_t	data_dma_state;
11078 	mptsas_dma_alloc_state_t	dataout_dma_state;
11079 	caddr_t				memp;
11080 	mptsas_cmd_t			*cmd = NULL;
11081 	struct scsi_pkt			*pkt;
11082 	uint32_t			reply_len = 0, sense_len = 0;
11083 	pMPI2RequestHeader_t		request_hdrp;
11084 	pMPI2RequestHeader_t		request_msg;
11085 	pMPI2DefaultReply_t		reply_msg;
11086 	Mpi2SCSIIOReply_t		rep_msg;
11087 	int				rvalue;
11088 	int				i, status = 0, pt_flags = 0, rv = 0;
11089 	uint8_t				function;
11090 
11091 	ASSERT(mutex_owned(&mpt->m_mutex));
11092 
11093 	reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
11094 	bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
11095 	request_msg = kmem_zalloc(request_size, KM_SLEEP);
11096 
11097 	mutex_exit(&mpt->m_mutex);
11098 	/*
11099 	 * copy in the request buffer since it could be used by
11100 	 * another thread when the pt request into waitq
11101 	 */
11102 	if (ddi_copyin(request, request_msg, request_size, mode)) {
11103 		mutex_enter(&mpt->m_mutex);
11104 		status = EFAULT;
11105 		mptsas_log(mpt, CE_WARN, "failed to copy request data");
11106 		goto out;
11107 	}
11108 	NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x",
11109 	    mode, request_size, request_msg->Function));
11110 	mutex_enter(&mpt->m_mutex);
11111 
11112 	function = request_msg->Function;
11113 	if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
11114 		pMpi2SCSITaskManagementRequest_t	task;
11115 		task = (pMpi2SCSITaskManagementRequest_t)request_msg;
11116 		mptsas_setup_bus_reset_delay(mpt);
11117 		rv = mptsas_ioc_task_management(mpt, task->TaskType,
11118 		    task->DevHandle, (int)task->LUN[1], reply, reply_size,
11119 		    mode);
11120 
11121 		if (rv != TRUE) {
11122 			status = EIO;
11123 			mptsas_log(mpt, CE_WARN, "task management failed");
11124 		}
11125 		goto out;
11126 	}
11127 
11128 	if (data_size != 0) {
11129 		data_dma_state.size = data_size;
11130 		if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
11131 			status = ENOMEM;
11132 			mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
11133 			    "resource");
11134 			goto out;
11135 		}
11136 		pt_flags |= MPTSAS_DATA_ALLOCATED;
11137 		if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11138 			mutex_exit(&mpt->m_mutex);
11139 			for (i = 0; i < data_size; i++) {
11140 				if (ddi_copyin(data + i, (uint8_t *)
11141 				    data_dma_state.memp + i, 1, mode)) {
11142 					mutex_enter(&mpt->m_mutex);
11143 					status = EFAULT;
11144 					mptsas_log(mpt, CE_WARN, "failed to "
11145 					    "copy read data");
11146 					goto out;
11147 				}
11148 			}
11149 			mutex_enter(&mpt->m_mutex);
11150 		}
11151 	} else {
11152 		bzero(&data_dma_state, sizeof (data_dma_state));
11153 	}
11154 
11155 	if (dataout_size != 0) {
11156 		dataout_dma_state.size = dataout_size;
11157 		if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
11158 			status = ENOMEM;
11159 			mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
11160 			    "resource");
11161 			goto out;
11162 		}
11163 		pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
11164 		mutex_exit(&mpt->m_mutex);
11165 		for (i = 0; i < dataout_size; i++) {
11166 			if (ddi_copyin(dataout + i, (uint8_t *)
11167 			    dataout_dma_state.memp + i, 1, mode)) {
11168 				mutex_enter(&mpt->m_mutex);
11169 				mptsas_log(mpt, CE_WARN, "failed to copy out"
11170 				    " data");
11171 				status = EFAULT;
11172 				goto out;
11173 			}
11174 		}
11175 		mutex_enter(&mpt->m_mutex);
11176 	} else {
11177 		bzero(&dataout_dma_state, sizeof (dataout_dma_state));
11178 	}
11179 
11180 	if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11181 		status = EAGAIN;
11182 		mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
11183 		goto out;
11184 	}
11185 	pt_flags |= MPTSAS_REQUEST_POOL_CMD;
11186 
11187 	bzero((caddr_t)cmd, sizeof (*cmd));
11188 	bzero((caddr_t)pkt, scsi_pkt_size());
11189 	bzero((caddr_t)&pt, sizeof (pt));
11190 
11191 	cmd->ioc_cmd_slot = (uint32_t)(rvalue);
11192 
11193 	pt.request = (uint8_t *)request_msg;
11194 	pt.direction = direction;
11195 	pt.simple = 0;
11196 	pt.request_size = request_size;
11197 	pt.data_size = data_size;
11198 	pt.dataout_size = dataout_size;
11199 	pt.data_cookie = data_dma_state.cookie;
11200 	pt.dataout_cookie = dataout_dma_state.cookie;
11201 	mptsas_prep_sgl_offset(mpt, &pt);
11202 
11203 	/*
11204 	 * Form a blank cmd/pkt to store the acknowledgement message
11205 	 */
11206 	pkt->pkt_cdbp		= (opaque_t)&cmd->cmd_cdb[0];
11207 	pkt->pkt_scbp		= (opaque_t)&cmd->cmd_scb;
11208 	pkt->pkt_ha_private	= (opaque_t)&pt;
11209 	pkt->pkt_flags		= FLAG_HEAD;
11210 	pkt->pkt_time		= timeout;
11211 	cmd->cmd_pkt		= pkt;
11212 	cmd->cmd_flags		= CFLAG_CMDIOC | CFLAG_PASSTHRU;
11213 
11214 	if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11215 	    (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11216 		uint8_t			com, cdb_group_id;
11217 		boolean_t		ret;
11218 
11219 		pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32;
11220 		com = pkt->pkt_cdbp[0];
11221 		cdb_group_id = CDB_GROUPID(com);
11222 		switch (cdb_group_id) {
11223 		case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break;
11224 		case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break;
11225 		case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break;
11226 		case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break;
11227 		case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break;
11228 		default:
11229 			NDBG27(("mptsas_do_passthru: SCSI_IO, reserved "
11230 			    "CDBGROUP 0x%x requested!", cdb_group_id));
11231 			break;
11232 		}
11233 
11234 		reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11235 		sense_len = reply_size - reply_len;
11236 		ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP);
11237 		VERIFY(ret == B_TRUE);
11238 	} else {
11239 		reply_len = reply_size;
11240 		sense_len = 0;
11241 	}
11242 
11243 	NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, "
11244 	    "snslen 0x%x",
11245 	    (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read",
11246 	    data_size, dataout_size, reply_len, sense_len));
11247 
11248 	/*
11249 	 * Save the command in a slot
11250 	 */
11251 	if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11252 		/*
11253 		 * Once passthru command get slot, set cmd_flags
11254 		 * CFLAG_PREPARED.
11255 		 */
11256 		cmd->cmd_flags |= CFLAG_PREPARED;
11257 		mptsas_start_passthru(mpt, cmd);
11258 	} else {
11259 		mptsas_waitq_add(mpt, cmd);
11260 	}
11261 
11262 	while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11263 		cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
11264 	}
11265 
11266 	NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x "
11267 	    "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm,
11268 	    pkt->pkt_reason));
11269 
11270 	if (cmd->cmd_flags & CFLAG_PREPARED) {
11271 		memp = mpt->m_req_frame + (mpt->m_req_frame_size *
11272 		    cmd->cmd_slot);
11273 		request_hdrp = (pMPI2RequestHeader_t)memp;
11274 	}
11275 
11276 	if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11277 		status = ETIMEDOUT;
11278 		mptsas_log(mpt, CE_WARN, "passthrough command timeout");
11279 		pt_flags |= MPTSAS_CMD_TIMEOUT;
11280 		goto out;
11281 	}
11282 
11283 	if (cmd->cmd_rfm) {
11284 		/*
11285 		 * cmd_rfm is zero means the command reply is a CONTEXT
11286 		 * reply and no PCI Write to post the free reply SMFA
11287 		 * because no reply message frame is used.
11288 		 * cmd_rfm is non-zero means the reply is a ADDRESS
11289 		 * reply and reply message frame is used.
11290 		 */
11291 		pt_flags |= MPTSAS_ADDRESS_REPLY;
11292 		(void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11293 		    DDI_DMA_SYNC_FORCPU);
11294 		reply_msg = (pMPI2DefaultReply_t)
11295 		    (mpt->m_reply_frame + (cmd->cmd_rfm -
11296 		    (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11297 	}
11298 
11299 	mptsas_fma_check(mpt, cmd);
11300 	if (pkt->pkt_reason == CMD_TRAN_ERR) {
11301 		status = EAGAIN;
11302 		mptsas_log(mpt, CE_WARN, "passthru fma error");
11303 		goto out;
11304 	}
11305 	if (pkt->pkt_reason == CMD_RESET) {
11306 		status = EAGAIN;
11307 		mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
11308 		goto out;
11309 	}
11310 
11311 	if (pkt->pkt_reason == CMD_INCOMPLETE) {
11312 		status = EIO;
11313 		mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
11314 		goto out;
11315 	}
11316 
11317 	mutex_exit(&mpt->m_mutex);
11318 	if (cmd->cmd_flags & CFLAG_PREPARED) {
11319 		function = request_hdrp->Function;
11320 		if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11321 		    (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11322 			reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11323 			sense_len = cmd->cmd_extrqslen ?
11324 			    min(sense_len, cmd->cmd_extrqslen) :
11325 			    min(sense_len, cmd->cmd_rqslen);
11326 		} else {
11327 			reply_len = reply_size;
11328 			sense_len = 0;
11329 		}
11330 
11331 		for (i = 0; i < reply_len; i++) {
11332 			if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
11333 			    mode)) {
11334 				mutex_enter(&mpt->m_mutex);
11335 				status = EFAULT;
11336 				mptsas_log(mpt, CE_WARN, "failed to copy out "
11337 				    "reply data");
11338 				goto out;
11339 			}
11340 		}
11341 		for (i = 0; i < sense_len; i++) {
11342 			if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
11343 			    reply + reply_len + i, 1, mode)) {
11344 				mutex_enter(&mpt->m_mutex);
11345 				status = EFAULT;
11346 				mptsas_log(mpt, CE_WARN, "failed to copy out "
11347 				    "sense data");
11348 				goto out;
11349 			}
11350 		}
11351 	}
11352 
11353 	if (data_size) {
11354 		if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11355 			(void) ddi_dma_sync(data_dma_state.handle, 0, 0,
11356 			    DDI_DMA_SYNC_FORCPU);
11357 			for (i = 0; i < data_size; i++) {
11358 				if (ddi_copyout((uint8_t *)(
11359 				    data_dma_state.memp + i), data + i,  1,
11360 				    mode)) {
11361 					mutex_enter(&mpt->m_mutex);
11362 					status = EFAULT;
11363 					mptsas_log(mpt, CE_WARN, "failed to "
11364 					    "copy out the reply data");
11365 					goto out;
11366 				}
11367 			}
11368 		}
11369 	}
11370 	mutex_enter(&mpt->m_mutex);
11371 out:
11372 	/*
11373 	 * Put the reply frame back on the free queue, increment the free
11374 	 * index, and write the new index to the free index register.  But only
11375 	 * if this reply is an ADDRESS reply.
11376 	 */
11377 	if (pt_flags & MPTSAS_ADDRESS_REPLY) {
11378 		ddi_put32(mpt->m_acc_free_queue_hdl,
11379 		    &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11380 		    cmd->cmd_rfm);
11381 		(void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11382 		    DDI_DMA_SYNC_FORDEV);
11383 		if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11384 			mpt->m_free_index = 0;
11385 		}
11386 		ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11387 		    mpt->m_free_index);
11388 	}
11389 	if (cmd) {
11390 		if (cmd->cmd_extrqslen != 0) {
11391 			rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
11392 			    cmd->cmd_extrqsidx + 1);
11393 		}
11394 		if (cmd->cmd_flags & CFLAG_PREPARED) {
11395 			mptsas_remove_cmd(mpt, cmd);
11396 			pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11397 		}
11398 	}
11399 	if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
11400 		mptsas_return_to_pool(mpt, cmd);
11401 	if (pt_flags & MPTSAS_DATA_ALLOCATED) {
11402 		if (mptsas_check_dma_handle(data_dma_state.handle) !=
11403 		    DDI_SUCCESS) {
11404 			ddi_fm_service_impact(mpt->m_dip,
11405 			    DDI_SERVICE_UNAFFECTED);
11406 			status = EFAULT;
11407 		}
11408 		mptsas_dma_free(&data_dma_state);
11409 	}
11410 	if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
11411 		if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
11412 		    DDI_SUCCESS) {
11413 			ddi_fm_service_impact(mpt->m_dip,
11414 			    DDI_SERVICE_UNAFFECTED);
11415 			status = EFAULT;
11416 		}
11417 		mptsas_dma_free(&dataout_dma_state);
11418 	}
11419 	if (pt_flags & MPTSAS_CMD_TIMEOUT) {
11420 		if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11421 			mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
11422 		}
11423 	}
11424 	if (request_msg)
11425 		kmem_free(request_msg, request_size);
11426 	NDBG27(("mptsas_do_passthru: Done status 0x%x", status));
11427 
11428 	return (status);
11429 }
11430 
11431 static int
11432 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
11433 {
11434 	/*
11435 	 * If timeout is 0, set timeout to default of 60 seconds.
11436 	 */
11437 	if (data->Timeout == 0) {
11438 		data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
11439 	}
11440 
11441 	if (((data->DataSize == 0) &&
11442 	    (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
11443 	    ((data->DataSize != 0) &&
11444 	    ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
11445 	    (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
11446 	    ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
11447 	    (data->DataOutSize != 0))))) {
11448 		if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
11449 			data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
11450 		} else {
11451 			data->DataOutSize = 0;
11452 		}
11453 		/*
11454 		 * Send passthru request messages
11455 		 */
11456 		return (mptsas_do_passthru(mpt,
11457 		    (uint8_t *)((uintptr_t)data->PtrRequest),
11458 		    (uint8_t *)((uintptr_t)data->PtrReply),
11459 		    (uint8_t *)((uintptr_t)data->PtrData),
11460 		    data->RequestSize, data->ReplySize,
11461 		    data->DataSize, data->DataDirection,
11462 		    (uint8_t *)((uintptr_t)data->PtrDataOut),
11463 		    data->DataOutSize, data->Timeout, mode));
11464 	} else {
11465 		return (EINVAL);
11466 	}
11467 }
11468 
11469 static uint8_t
11470 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
11471 {
11472 	uint8_t	index;
11473 
11474 	for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
11475 		if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
11476 			return (index);
11477 		}
11478 	}
11479 
11480 	return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
11481 }
11482 
11483 static void
11484 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
11485 {
11486 	pMpi2DiagBufferPostRequest_t	pDiag_post_msg;
11487 	pMpi2DiagReleaseRequest_t	pDiag_release_msg;
11488 	struct scsi_pkt			*pkt = cmd->cmd_pkt;
11489 	mptsas_diag_request_t		*diag = pkt->pkt_ha_private;
11490 	uint32_t			i;
11491 	uint64_t			request_desc;
11492 
11493 	ASSERT(mutex_owned(&mpt->m_mutex));
11494 
11495 	/*
11496 	 * Form the diag message depending on the post or release function.
11497 	 */
11498 	if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
11499 		pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
11500 		    (mpt->m_req_frame + (mpt->m_req_frame_size *
11501 		    cmd->cmd_slot));
11502 		bzero(pDiag_post_msg, mpt->m_req_frame_size);
11503 		ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
11504 		    diag->function);
11505 		ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
11506 		    diag->pBuffer->buffer_type);
11507 		ddi_put8(mpt->m_acc_req_frame_hdl,
11508 		    &pDiag_post_msg->ExtendedType,
11509 		    diag->pBuffer->extended_type);
11510 		ddi_put32(mpt->m_acc_req_frame_hdl,
11511 		    &pDiag_post_msg->BufferLength,
11512 		    diag->pBuffer->buffer_data.size);
11513 		for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
11514 		    i++) {
11515 			ddi_put32(mpt->m_acc_req_frame_hdl,
11516 			    &pDiag_post_msg->ProductSpecific[i],
11517 			    diag->pBuffer->product_specific[i]);
11518 		}
11519 		ddi_put32(mpt->m_acc_req_frame_hdl,
11520 		    &pDiag_post_msg->BufferAddress.Low,
11521 		    (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11522 		    & 0xffffffffull));
11523 		ddi_put32(mpt->m_acc_req_frame_hdl,
11524 		    &pDiag_post_msg->BufferAddress.High,
11525 		    (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11526 		    >> 32));
11527 	} else {
11528 		pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
11529 		    (mpt->m_req_frame + (mpt->m_req_frame_size *
11530 		    cmd->cmd_slot));
11531 		bzero(pDiag_release_msg, mpt->m_req_frame_size);
11532 		ddi_put8(mpt->m_acc_req_frame_hdl,
11533 		    &pDiag_release_msg->Function, diag->function);
11534 		ddi_put8(mpt->m_acc_req_frame_hdl,
11535 		    &pDiag_release_msg->BufferType,
11536 		    diag->pBuffer->buffer_type);
11537 	}
11538 
11539 	/*
11540 	 * Send the message
11541 	 */
11542 	(void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
11543 	    DDI_DMA_SYNC_FORDEV);
11544 	request_desc = (cmd->cmd_slot << 16) +
11545 	    MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
11546 	cmd->cmd_rfm = NULL;
11547 	MPTSAS_START_CMD(mpt, request_desc);
11548 	if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11549 	    DDI_SUCCESS) ||
11550 	    (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11551 	    DDI_SUCCESS)) {
11552 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11553 	}
11554 }
11555 
11556 static int
11557 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
11558     mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
11559 {
11560 	mptsas_diag_request_t		diag;
11561 	int				status, slot_num, post_flags = 0;
11562 	mptsas_cmd_t			*cmd = NULL;
11563 	struct scsi_pkt			*pkt;
11564 	pMpi2DiagBufferPostReply_t	reply;
11565 	uint16_t			iocstatus;
11566 	uint32_t			iocloginfo, transfer_length;
11567 
11568 	/*
11569 	 * If buffer is not enabled, just leave.
11570 	 */
11571 	*return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
11572 	if (!pBuffer->enabled) {
11573 		status = DDI_FAILURE;
11574 		goto out;
11575 	}
11576 
11577 	/*
11578 	 * Clear some flags initially.
11579 	 */
11580 	pBuffer->force_release = FALSE;
11581 	pBuffer->valid_data = FALSE;
11582 	pBuffer->owned_by_firmware = FALSE;
11583 
11584 	/*
11585 	 * Get a cmd buffer from the cmd buffer pool
11586 	 */
11587 	if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11588 		status = DDI_FAILURE;
11589 		mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
11590 		goto out;
11591 	}
11592 	post_flags |= MPTSAS_REQUEST_POOL_CMD;
11593 
11594 	bzero((caddr_t)cmd, sizeof (*cmd));
11595 	bzero((caddr_t)pkt, scsi_pkt_size());
11596 
11597 	cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11598 
11599 	diag.pBuffer = pBuffer;
11600 	diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
11601 
11602 	/*
11603 	 * Form a blank cmd/pkt to store the acknowledgement message
11604 	 */
11605 	pkt->pkt_ha_private	= (opaque_t)&diag;
11606 	pkt->pkt_flags		= FLAG_HEAD;
11607 	pkt->pkt_time		= 60;
11608 	cmd->cmd_pkt		= pkt;
11609 	cmd->cmd_flags		= CFLAG_CMDIOC | CFLAG_FW_DIAG;
11610 
11611 	/*
11612 	 * Save the command in a slot
11613 	 */
11614 	if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11615 		/*
11616 		 * Once passthru command get slot, set cmd_flags
11617 		 * CFLAG_PREPARED.
11618 		 */
11619 		cmd->cmd_flags |= CFLAG_PREPARED;
11620 		mptsas_start_diag(mpt, cmd);
11621 	} else {
11622 		mptsas_waitq_add(mpt, cmd);
11623 	}
11624 
11625 	while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11626 		cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11627 	}
11628 
11629 	if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11630 		status = DDI_FAILURE;
11631 		mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
11632 		goto out;
11633 	}
11634 
11635 	/*
11636 	 * cmd_rfm points to the reply message if a reply was given.  Check the
11637 	 * IOCStatus to make sure everything went OK with the FW diag request
11638 	 * and set buffer flags.
11639 	 */
11640 	if (cmd->cmd_rfm) {
11641 		post_flags |= MPTSAS_ADDRESS_REPLY;
11642 		(void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11643 		    DDI_DMA_SYNC_FORCPU);
11644 		reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
11645 		    (cmd->cmd_rfm -
11646 		    (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11647 
11648 		/*
11649 		 * Get the reply message data
11650 		 */
11651 		iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11652 		    &reply->IOCStatus);
11653 		iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11654 		    &reply->IOCLogInfo);
11655 		transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
11656 		    &reply->TransferLength);
11657 
11658 		/*
11659 		 * If post failed quit.
11660 		 */
11661 		if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
11662 			status = DDI_FAILURE;
11663 			NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
11664 			    "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
11665 			    iocloginfo, transfer_length));
11666 			goto out;
11667 		}
11668 
11669 		/*
11670 		 * Post was successful.
11671 		 */
11672 		pBuffer->valid_data = TRUE;
11673 		pBuffer->owned_by_firmware = TRUE;
11674 		*return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11675 		status = DDI_SUCCESS;
11676 	}
11677 
11678 out:
11679 	/*
11680 	 * Put the reply frame back on the free queue, increment the free
11681 	 * index, and write the new index to the free index register.  But only
11682 	 * if this reply is an ADDRESS reply.
11683 	 */
11684 	if (post_flags & MPTSAS_ADDRESS_REPLY) {
11685 		ddi_put32(mpt->m_acc_free_queue_hdl,
11686 		    &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11687 		    cmd->cmd_rfm);
11688 		(void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11689 		    DDI_DMA_SYNC_FORDEV);
11690 		if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11691 			mpt->m_free_index = 0;
11692 		}
11693 		ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11694 		    mpt->m_free_index);
11695 	}
11696 	if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11697 		mptsas_remove_cmd(mpt, cmd);
11698 		post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11699 	}
11700 	if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
11701 		mptsas_return_to_pool(mpt, cmd);
11702 	}
11703 
11704 	return (status);
11705 }
11706 
11707 static int
11708 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
11709     mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
11710     uint32_t diag_type)
11711 {
11712 	mptsas_diag_request_t	diag;
11713 	int			status, slot_num, rel_flags = 0;
11714 	mptsas_cmd_t		*cmd = NULL;
11715 	struct scsi_pkt		*pkt;
11716 	pMpi2DiagReleaseReply_t	reply;
11717 	uint16_t		iocstatus;
11718 	uint32_t		iocloginfo;
11719 
11720 	/*
11721 	 * If buffer is not enabled, just leave.
11722 	 */
11723 	*return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
11724 	if (!pBuffer->enabled) {
11725 		mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
11726 		    "by the IOC");
11727 		status = DDI_FAILURE;
11728 		goto out;
11729 	}
11730 
11731 	/*
11732 	 * Clear some flags initially.
11733 	 */
11734 	pBuffer->force_release = FALSE;
11735 	pBuffer->valid_data = FALSE;
11736 	pBuffer->owned_by_firmware = FALSE;
11737 
11738 	/*
11739 	 * Get a cmd buffer from the cmd buffer pool
11740 	 */
11741 	if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11742 		status = DDI_FAILURE;
11743 		mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
11744 		    "Diag");
11745 		goto out;
11746 	}
11747 	rel_flags |= MPTSAS_REQUEST_POOL_CMD;
11748 
11749 	bzero((caddr_t)cmd, sizeof (*cmd));
11750 	bzero((caddr_t)pkt, scsi_pkt_size());
11751 
11752 	cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11753 
11754 	diag.pBuffer = pBuffer;
11755 	diag.function = MPI2_FUNCTION_DIAG_RELEASE;
11756 
11757 	/*
11758 	 * Form a blank cmd/pkt to store the acknowledgement message
11759 	 */
11760 	pkt->pkt_ha_private	= (opaque_t)&diag;
11761 	pkt->pkt_flags		= FLAG_HEAD;
11762 	pkt->pkt_time		= 60;
11763 	cmd->cmd_pkt		= pkt;
11764 	cmd->cmd_flags		= CFLAG_CMDIOC | CFLAG_FW_DIAG;
11765 
11766 	/*
11767 	 * Save the command in a slot
11768 	 */
11769 	if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11770 		/*
11771 		 * Once passthru command get slot, set cmd_flags
11772 		 * CFLAG_PREPARED.
11773 		 */
11774 		cmd->cmd_flags |= CFLAG_PREPARED;
11775 		mptsas_start_diag(mpt, cmd);
11776 	} else {
11777 		mptsas_waitq_add(mpt, cmd);
11778 	}
11779 
11780 	while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11781 		cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11782 	}
11783 
11784 	if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11785 		status = DDI_FAILURE;
11786 		mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
11787 		goto out;
11788 	}
11789 
11790 	/*
11791 	 * cmd_rfm points to the reply message if a reply was given.  Check the
11792 	 * IOCStatus to make sure everything went OK with the FW diag request
11793 	 * and set buffer flags.
11794 	 */
11795 	if (cmd->cmd_rfm) {
11796 		rel_flags |= MPTSAS_ADDRESS_REPLY;
11797 		(void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11798 		    DDI_DMA_SYNC_FORCPU);
11799 		reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
11800 		    (cmd->cmd_rfm -
11801 		    (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11802 
11803 		/*
11804 		 * Get the reply message data
11805 		 */
11806 		iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11807 		    &reply->IOCStatus);
11808 		iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11809 		    &reply->IOCLogInfo);
11810 
11811 		/*
11812 		 * If release failed quit.
11813 		 */
11814 		if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
11815 		    pBuffer->owned_by_firmware) {
11816 			status = DDI_FAILURE;
11817 			NDBG13(("release FW Diag Buffer failed: "
11818 			    "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
11819 			    iocloginfo));
11820 			goto out;
11821 		}
11822 
11823 		/*
11824 		 * Release was successful.
11825 		 */
11826 		*return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11827 		status = DDI_SUCCESS;
11828 
11829 		/*
11830 		 * If this was for an UNREGISTER diag type command, clear the
11831 		 * unique ID.
11832 		 */
11833 		if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
11834 			pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11835 		}
11836 	}
11837 
11838 out:
11839 	/*
11840 	 * Put the reply frame back on the free queue, increment the free
11841 	 * index, and write the new index to the free index register.  But only
11842 	 * if this reply is an ADDRESS reply.
11843 	 */
11844 	if (rel_flags & MPTSAS_ADDRESS_REPLY) {
11845 		ddi_put32(mpt->m_acc_free_queue_hdl,
11846 		    &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11847 		    cmd->cmd_rfm);
11848 		(void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11849 		    DDI_DMA_SYNC_FORDEV);
11850 		if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11851 			mpt->m_free_index = 0;
11852 		}
11853 		ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11854 		    mpt->m_free_index);
11855 	}
11856 	if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11857 		mptsas_remove_cmd(mpt, cmd);
11858 		rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11859 	}
11860 	if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
11861 		mptsas_return_to_pool(mpt, cmd);
11862 	}
11863 
11864 	return (status);
11865 }
11866 
11867 static int
11868 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
11869     uint32_t *return_code)
11870 {
11871 	mptsas_fw_diagnostic_buffer_t	*pBuffer;
11872 	uint8_t				extended_type, buffer_type, i;
11873 	uint32_t			buffer_size;
11874 	uint32_t			unique_id;
11875 	int				status;
11876 
11877 	ASSERT(mutex_owned(&mpt->m_mutex));
11878 
11879 	extended_type = diag_register->ExtendedType;
11880 	buffer_type = diag_register->BufferType;
11881 	buffer_size = diag_register->RequestedBufferSize;
11882 	unique_id = diag_register->UniqueId;
11883 
11884 	/*
11885 	 * Check for valid buffer type
11886 	 */
11887 	if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
11888 		*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11889 		return (DDI_FAILURE);
11890 	}
11891 
11892 	/*
11893 	 * Get the current buffer and look up the unique ID.  The unique ID
11894 	 * should not be found.  If it is, the ID is already in use.
11895 	 */
11896 	i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11897 	pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
11898 	if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11899 		*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11900 		return (DDI_FAILURE);
11901 	}
11902 
11903 	/*
11904 	 * The buffer's unique ID should not be registered yet, and the given
11905 	 * unique ID cannot be 0.
11906 	 */
11907 	if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
11908 	    (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11909 		*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11910 		return (DDI_FAILURE);
11911 	}
11912 
11913 	/*
11914 	 * If this buffer is already posted as immediate, just change owner.
11915 	 */
11916 	if (pBuffer->immediate && pBuffer->owned_by_firmware &&
11917 	    (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11918 		pBuffer->immediate = FALSE;
11919 		pBuffer->unique_id = unique_id;
11920 		return (DDI_SUCCESS);
11921 	}
11922 
11923 	/*
11924 	 * Post a new buffer after checking if it's enabled.  The DMA buffer
11925 	 * that is allocated will be contiguous (sgl_len = 1).
11926 	 */
11927 	if (!pBuffer->enabled) {
11928 		*return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11929 		return (DDI_FAILURE);
11930 	}
11931 	bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
11932 	pBuffer->buffer_data.size = buffer_size;
11933 	if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
11934 		mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
11935 		    "diag buffer: size = %d bytes", buffer_size);
11936 		*return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11937 		return (DDI_FAILURE);
11938 	}
11939 
11940 	/*
11941 	 * Copy the given info to the diag buffer and post the buffer.
11942 	 */
11943 	pBuffer->buffer_type = buffer_type;
11944 	pBuffer->immediate = FALSE;
11945 	if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
11946 		for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
11947 		    i++) {
11948 			pBuffer->product_specific[i] =
11949 			    diag_register->ProductSpecific[i];
11950 		}
11951 	}
11952 	pBuffer->extended_type = extended_type;
11953 	pBuffer->unique_id = unique_id;
11954 	status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
11955 
11956 	if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11957 	    DDI_SUCCESS) {
11958 		mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
11959 		    "mptsas_diag_register.");
11960 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11961 		status = DDI_FAILURE;
11962 	}
11963 
11964 	/*
11965 	 * In case there was a failure, free the DMA buffer.
11966 	 */
11967 	if (status == DDI_FAILURE) {
11968 		mptsas_dma_free(&pBuffer->buffer_data);
11969 	}
11970 
11971 	return (status);
11972 }
11973 
11974 static int
11975 mptsas_diag_unregister(mptsas_t *mpt,
11976     mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
11977 {
11978 	mptsas_fw_diagnostic_buffer_t	*pBuffer;
11979 	uint8_t				i;
11980 	uint32_t			unique_id;
11981 	int				status;
11982 
11983 	ASSERT(mutex_owned(&mpt->m_mutex));
11984 
11985 	unique_id = diag_unregister->UniqueId;
11986 
11987 	/*
11988 	 * Get the current buffer and look up the unique ID.  The unique ID
11989 	 * should be there.
11990 	 */
11991 	i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11992 	if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11993 		*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11994 		return (DDI_FAILURE);
11995 	}
11996 
11997 	pBuffer = &mpt->m_fw_diag_buffer_list[i];
11998 
11999 	/*
12000 	 * Try to release the buffer from FW before freeing it.  If release
12001 	 * fails, don't free the DMA buffer in case FW tries to access it
12002 	 * later.  If buffer is not owned by firmware, can't release it.
12003 	 */
12004 	if (!pBuffer->owned_by_firmware) {
12005 		status = DDI_SUCCESS;
12006 	} else {
12007 		status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
12008 		    return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
12009 	}
12010 
12011 	/*
12012 	 * At this point, return the current status no matter what happens with
12013 	 * the DMA buffer.
12014 	 */
12015 	pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
12016 	if (status == DDI_SUCCESS) {
12017 		if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
12018 		    DDI_SUCCESS) {
12019 			mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
12020 			    "in mptsas_diag_unregister.");
12021 			ddi_fm_service_impact(mpt->m_dip,
12022 			    DDI_SERVICE_UNAFFECTED);
12023 		}
12024 		mptsas_dma_free(&pBuffer->buffer_data);
12025 	}
12026 
12027 	return (status);
12028 }
12029 
12030 static int
12031 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
12032     uint32_t *return_code)
12033 {
12034 	mptsas_fw_diagnostic_buffer_t	*pBuffer;
12035 	uint8_t				i;
12036 	uint32_t			unique_id;
12037 
12038 	ASSERT(mutex_owned(&mpt->m_mutex));
12039 
12040 	unique_id = diag_query->UniqueId;
12041 
12042 	/*
12043 	 * If ID is valid, query on ID.
12044 	 * If ID is invalid, query on buffer type.
12045 	 */
12046 	if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
12047 		i = diag_query->BufferType;
12048 		if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
12049 			*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12050 			return (DDI_FAILURE);
12051 		}
12052 	} else {
12053 		i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12054 		if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12055 			*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12056 			return (DDI_FAILURE);
12057 		}
12058 	}
12059 
12060 	/*
12061 	 * Fill query structure with the diag buffer info.
12062 	 */
12063 	pBuffer = &mpt->m_fw_diag_buffer_list[i];
12064 	diag_query->BufferType = pBuffer->buffer_type;
12065 	diag_query->ExtendedType = pBuffer->extended_type;
12066 	if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
12067 		for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
12068 		    i++) {
12069 			diag_query->ProductSpecific[i] =
12070 			    pBuffer->product_specific[i];
12071 		}
12072 	}
12073 	diag_query->TotalBufferSize = pBuffer->buffer_data.size;
12074 	diag_query->DriverAddedBufferSize = 0;
12075 	diag_query->UniqueId = pBuffer->unique_id;
12076 	diag_query->ApplicationFlags = 0;
12077 	diag_query->DiagnosticFlags = 0;
12078 
12079 	/*
12080 	 * Set/Clear application flags
12081 	 */
12082 	if (pBuffer->immediate) {
12083 		diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
12084 	} else {
12085 		diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
12086 	}
12087 	if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
12088 		diag_query->ApplicationFlags |=
12089 		    MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
12090 	} else {
12091 		diag_query->ApplicationFlags &=
12092 		    ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
12093 	}
12094 	if (pBuffer->owned_by_firmware) {
12095 		diag_query->ApplicationFlags |=
12096 		    MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
12097 	} else {
12098 		diag_query->ApplicationFlags &=
12099 		    ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
12100 	}
12101 
12102 	return (DDI_SUCCESS);
12103 }
12104 
12105 static int
12106 mptsas_diag_read_buffer(mptsas_t *mpt,
12107     mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
12108     uint32_t *return_code, int ioctl_mode)
12109 {
12110 	mptsas_fw_diagnostic_buffer_t	*pBuffer;
12111 	uint8_t				i, *pData;
12112 	uint32_t			unique_id, byte;
12113 	int				status;
12114 
12115 	ASSERT(mutex_owned(&mpt->m_mutex));
12116 
12117 	unique_id = diag_read_buffer->UniqueId;
12118 
12119 	/*
12120 	 * Get the current buffer and look up the unique ID.  The unique ID
12121 	 * should be there.
12122 	 */
12123 	i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12124 	if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12125 		*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12126 		return (DDI_FAILURE);
12127 	}
12128 
12129 	pBuffer = &mpt->m_fw_diag_buffer_list[i];
12130 
12131 	/*
12132 	 * Make sure requested read is within limits
12133 	 */
12134 	if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
12135 	    pBuffer->buffer_data.size) {
12136 		*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12137 		return (DDI_FAILURE);
12138 	}
12139 
12140 	/*
12141 	 * Copy the requested data from DMA to the diag_read_buffer.  The DMA
12142 	 * buffer that was allocated is one contiguous buffer.
12143 	 */
12144 	pData = (uint8_t *)(pBuffer->buffer_data.memp +
12145 	    diag_read_buffer->StartingOffset);
12146 	(void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
12147 	    DDI_DMA_SYNC_FORCPU);
12148 	for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
12149 		if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
12150 		    != 0) {
12151 			return (DDI_FAILURE);
12152 		}
12153 	}
12154 	diag_read_buffer->Status = 0;
12155 
12156 	/*
12157 	 * Set or clear the Force Release flag.
12158 	 */
12159 	if (pBuffer->force_release) {
12160 		diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
12161 	} else {
12162 		diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
12163 	}
12164 
12165 	/*
12166 	 * If buffer is to be reregistered, make sure it's not already owned by
12167 	 * firmware first.
12168 	 */
12169 	status = DDI_SUCCESS;
12170 	if (!pBuffer->owned_by_firmware) {
12171 		if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
12172 			status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
12173 			    return_code);
12174 		}
12175 	}
12176 
12177 	return (status);
12178 }
12179 
12180 static int
12181 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
12182     uint32_t *return_code)
12183 {
12184 	mptsas_fw_diagnostic_buffer_t	*pBuffer;
12185 	uint8_t				i;
12186 	uint32_t			unique_id;
12187 	int				status;
12188 
12189 	ASSERT(mutex_owned(&mpt->m_mutex));
12190 
12191 	unique_id = diag_release->UniqueId;
12192 
12193 	/*
12194 	 * Get the current buffer and look up the unique ID.  The unique ID
12195 	 * should be there.
12196 	 */
12197 	i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12198 	if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12199 		*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12200 		return (DDI_FAILURE);
12201 	}
12202 
12203 	pBuffer = &mpt->m_fw_diag_buffer_list[i];
12204 
12205 	/*
12206 	 * If buffer is not owned by firmware, it's already been released.
12207 	 */
12208 	if (!pBuffer->owned_by_firmware) {
12209 		*return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
12210 		return (DDI_FAILURE);
12211 	}
12212 
12213 	/*
12214 	 * Release the buffer.
12215 	 */
12216 	status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
12217 	    MPTSAS_FW_DIAG_TYPE_RELEASE);
12218 	return (status);
12219 }
12220 
12221 static int
12222 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
12223     uint32_t length, uint32_t *return_code, int ioctl_mode)
12224 {
12225 	mptsas_fw_diag_register_t	diag_register;
12226 	mptsas_fw_diag_unregister_t	diag_unregister;
12227 	mptsas_fw_diag_query_t		diag_query;
12228 	mptsas_diag_read_buffer_t	diag_read_buffer;
12229 	mptsas_fw_diag_release_t	diag_release;
12230 	int				status = DDI_SUCCESS;
12231 	uint32_t			original_return_code, read_buf_len;
12232 
12233 	ASSERT(mutex_owned(&mpt->m_mutex));
12234 
12235 	original_return_code = *return_code;
12236 	*return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
12237 
12238 	switch (action) {
12239 		case MPTSAS_FW_DIAG_TYPE_REGISTER:
12240 			if (!length) {
12241 				*return_code =
12242 				    MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12243 				status = DDI_FAILURE;
12244 				break;
12245 			}
12246 			if (ddi_copyin(diag_action, &diag_register,
12247 			    sizeof (diag_register), ioctl_mode) != 0) {
12248 				return (DDI_FAILURE);
12249 			}
12250 			status = mptsas_diag_register(mpt, &diag_register,
12251 			    return_code);
12252 			break;
12253 
12254 		case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
12255 			if (length < sizeof (diag_unregister)) {
12256 				*return_code =
12257 				    MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12258 				status = DDI_FAILURE;
12259 				break;
12260 			}
12261 			if (ddi_copyin(diag_action, &diag_unregister,
12262 			    sizeof (diag_unregister), ioctl_mode) != 0) {
12263 				return (DDI_FAILURE);
12264 			}
12265 			status = mptsas_diag_unregister(mpt, &diag_unregister,
12266 			    return_code);
12267 			break;
12268 
12269 		case MPTSAS_FW_DIAG_TYPE_QUERY:
12270 			if (length < sizeof (diag_query)) {
12271 				*return_code =
12272 				    MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12273 				status = DDI_FAILURE;
12274 				break;
12275 			}
12276 			if (ddi_copyin(diag_action, &diag_query,
12277 			    sizeof (diag_query), ioctl_mode) != 0) {
12278 				return (DDI_FAILURE);
12279 			}
12280 			status = mptsas_diag_query(mpt, &diag_query,
12281 			    return_code);
12282 			if (status == DDI_SUCCESS) {
12283 				if (ddi_copyout(&diag_query, diag_action,
12284 				    sizeof (diag_query), ioctl_mode) != 0) {
12285 					return (DDI_FAILURE);
12286 				}
12287 			}
12288 			break;
12289 
12290 		case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
12291 			if (ddi_copyin(diag_action, &diag_read_buffer,
12292 			    sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
12293 				return (DDI_FAILURE);
12294 			}
12295 			read_buf_len = sizeof (diag_read_buffer) -
12296 			    sizeof (diag_read_buffer.DataBuffer) +
12297 			    diag_read_buffer.BytesToRead;
12298 			if (length < read_buf_len) {
12299 				*return_code =
12300 				    MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12301 				status = DDI_FAILURE;
12302 				break;
12303 			}
12304 			status = mptsas_diag_read_buffer(mpt,
12305 			    &diag_read_buffer, diag_action +
12306 			    sizeof (diag_read_buffer) - 4, return_code,
12307 			    ioctl_mode);
12308 			if (status == DDI_SUCCESS) {
12309 				if (ddi_copyout(&diag_read_buffer, diag_action,
12310 				    sizeof (diag_read_buffer) - 4, ioctl_mode)
12311 				    != 0) {
12312 					return (DDI_FAILURE);
12313 				}
12314 			}
12315 			break;
12316 
12317 		case MPTSAS_FW_DIAG_TYPE_RELEASE:
12318 			if (length < sizeof (diag_release)) {
12319 				*return_code =
12320 				    MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12321 				status = DDI_FAILURE;
12322 				break;
12323 			}
12324 			if (ddi_copyin(diag_action, &diag_release,
12325 			    sizeof (diag_release), ioctl_mode) != 0) {
12326 				return (DDI_FAILURE);
12327 			}
12328 			status = mptsas_diag_release(mpt, &diag_release,
12329 			    return_code);
12330 			break;
12331 
12332 		default:
12333 			*return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12334 			status = DDI_FAILURE;
12335 			break;
12336 	}
12337 
12338 	if ((status == DDI_FAILURE) &&
12339 	    (original_return_code == MPTSAS_FW_DIAG_NEW) &&
12340 	    (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
12341 		status = DDI_SUCCESS;
12342 	}
12343 
12344 	return (status);
12345 }
12346 
12347 static int
12348 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
12349 {
12350 	int			status;
12351 	mptsas_diag_action_t	driver_data;
12352 
12353 	ASSERT(mutex_owned(&mpt->m_mutex));
12354 
12355 	/*
12356 	 * Copy the user data to a driver data buffer.
12357 	 */
12358 	if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
12359 	    mode) == 0) {
12360 		/*
12361 		 * Send diag action request if Action is valid
12362 		 */
12363 		if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
12364 		    driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
12365 		    driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
12366 		    driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
12367 		    driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
12368 			status = mptsas_do_diag_action(mpt, driver_data.Action,
12369 			    (void *)(uintptr_t)driver_data.PtrDiagAction,
12370 			    driver_data.Length, &driver_data.ReturnCode,
12371 			    mode);
12372 			if (status == DDI_SUCCESS) {
12373 				if (ddi_copyout(&driver_data.ReturnCode,
12374 				    &user_data->ReturnCode,
12375 				    sizeof (user_data->ReturnCode), mode)
12376 				    != 0) {
12377 					status = EFAULT;
12378 				} else {
12379 					status = 0;
12380 				}
12381 			} else {
12382 				status = EIO;
12383 			}
12384 		} else {
12385 			status = EINVAL;
12386 		}
12387 	} else {
12388 		status = EFAULT;
12389 	}
12390 
12391 	return (status);
12392 }
12393 
12394 /*
12395  * This routine handles the "event query" ioctl.
12396  */
12397 static int
12398 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
12399     int *rval)
12400 {
12401 	int			status;
12402 	mptsas_event_query_t	driverdata;
12403 	uint8_t			i;
12404 
12405 	driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
12406 
12407 	mutex_enter(&mpt->m_mutex);
12408 	for (i = 0; i < 4; i++) {
12409 		driverdata.Types[i] = mpt->m_event_mask[i];
12410 	}
12411 	mutex_exit(&mpt->m_mutex);
12412 
12413 	if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
12414 		status = EFAULT;
12415 	} else {
12416 		*rval = MPTIOCTL_STATUS_GOOD;
12417 		status = 0;
12418 	}
12419 
12420 	return (status);
12421 }
12422 
12423 /*
12424  * This routine handles the "event enable" ioctl.
12425  */
12426 static int
12427 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
12428     int *rval)
12429 {
12430 	int			status;
12431 	mptsas_event_enable_t	driverdata;
12432 	uint8_t			i;
12433 
12434 	if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12435 		mutex_enter(&mpt->m_mutex);
12436 		for (i = 0; i < 4; i++) {
12437 			mpt->m_event_mask[i] = driverdata.Types[i];
12438 		}
12439 		mutex_exit(&mpt->m_mutex);
12440 
12441 		*rval = MPTIOCTL_STATUS_GOOD;
12442 		status = 0;
12443 	} else {
12444 		status = EFAULT;
12445 	}
12446 	return (status);
12447 }
12448 
12449 /*
12450  * This routine handles the "event report" ioctl.
12451  */
12452 static int
12453 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
12454     int *rval)
12455 {
12456 	int			status;
12457 	mptsas_event_report_t	driverdata;
12458 
12459 	mutex_enter(&mpt->m_mutex);
12460 
12461 	if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
12462 	    mode) == 0) {
12463 		if (driverdata.Size >= sizeof (mpt->m_events)) {
12464 			if (ddi_copyout(mpt->m_events, data->Events,
12465 			    sizeof (mpt->m_events), mode) != 0) {
12466 				status = EFAULT;
12467 			} else {
12468 				if (driverdata.Size > sizeof (mpt->m_events)) {
12469 					driverdata.Size =
12470 					    sizeof (mpt->m_events);
12471 					if (ddi_copyout(&driverdata.Size,
12472 					    &data->Size,
12473 					    sizeof (driverdata.Size),
12474 					    mode) != 0) {
12475 						status = EFAULT;
12476 					} else {
12477 						*rval = MPTIOCTL_STATUS_GOOD;
12478 						status = 0;
12479 					}
12480 				} else {
12481 					*rval = MPTIOCTL_STATUS_GOOD;
12482 					status = 0;
12483 				}
12484 			}
12485 		} else {
12486 			*rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12487 			status = 0;
12488 		}
12489 	} else {
12490 		status = EFAULT;
12491 	}
12492 
12493 	mutex_exit(&mpt->m_mutex);
12494 	return (status);
12495 }
12496 
12497 static void
12498 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12499 {
12500 	int	*reg_data;
12501 	uint_t	reglen;
12502 
12503 	/*
12504 	 * Lookup the 'reg' property and extract the other data
12505 	 */
12506 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12507 	    DDI_PROP_DONTPASS, "reg", &reg_data, &reglen) ==
12508 	    DDI_PROP_SUCCESS) {
12509 		/*
12510 		 * Extract the PCI data from the 'reg' property first DWORD.
12511 		 * The entry looks like the following:
12512 		 * First DWORD:
12513 		 * Bits 0 - 7 8-bit Register number
12514 		 * Bits 8 - 10 3-bit Function number
12515 		 * Bits 11 - 15 5-bit Device number
12516 		 * Bits 16 - 23 8-bit Bus number
12517 		 * Bits 24 - 25 2-bit Address Space type identifier
12518 		 *
12519 		 */
12520 		adapter_data->PciInformation.u.bits.BusNumber =
12521 		    (reg_data[0] & 0x00FF0000) >> 16;
12522 		adapter_data->PciInformation.u.bits.DeviceNumber =
12523 		    (reg_data[0] & 0x0000F800) >> 11;
12524 		adapter_data->PciInformation.u.bits.FunctionNumber =
12525 		    (reg_data[0] & 0x00000700) >> 8;
12526 		ddi_prop_free((void *)reg_data);
12527 	} else {
12528 		/*
12529 		 * If we can't determine the PCI data then we fill in FF's for
12530 		 * the data to indicate this.
12531 		 */
12532 		adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
12533 		adapter_data->MpiPortNumber = 0xFFFFFFFF;
12534 		adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
12535 	}
12536 
12537 	/*
12538 	 * Saved in the mpt->m_fwversion
12539 	 */
12540 	adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
12541 }
12542 
12543 static void
12544 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12545 {
12546 	char	*driver_verstr = MPTSAS_MOD_STRING;
12547 
12548 	mptsas_lookup_pci_data(mpt, adapter_data);
12549 	adapter_data->AdapterType = mpt->m_MPI25 ?
12550 	    MPTIOCTL_ADAPTER_TYPE_SAS3 :
12551 	    MPTIOCTL_ADAPTER_TYPE_SAS2;
12552 	adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
12553 	adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
12554 	adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
12555 	adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
12556 	(void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
12557 	adapter_data->BiosVersion = 0;
12558 	(void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
12559 }
12560 
12561 static void
12562 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
12563 {
12564 	int	*reg_data, i;
12565 	uint_t	reglen;
12566 
12567 	/*
12568 	 * Lookup the 'reg' property and extract the other data
12569 	 */
12570 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12571 	    DDI_PROP_DONTPASS, "reg", &reg_data, &reglen) ==
12572 	    DDI_PROP_SUCCESS) {
12573 		/*
12574 		 * Extract the PCI data from the 'reg' property first DWORD.
12575 		 * The entry looks like the following:
12576 		 * First DWORD:
12577 		 * Bits 8 - 10 3-bit Function number
12578 		 * Bits 11 - 15 5-bit Device number
12579 		 * Bits 16 - 23 8-bit Bus number
12580 		 */
12581 		pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
12582 		pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
12583 		pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
12584 		ddi_prop_free((void *)reg_data);
12585 	} else {
12586 		/*
12587 		 * If we can't determine the PCI info then we fill in FF's for
12588 		 * the data to indicate this.
12589 		 */
12590 		pci_info->BusNumber = 0xFFFFFFFF;
12591 		pci_info->DeviceNumber = 0xFF;
12592 		pci_info->FunctionNumber = 0xFF;
12593 	}
12594 
12595 	/*
12596 	 * Now get the interrupt vector and the pci header.  The vector can
12597 	 * only be 0 right now.  The header is the first 256 bytes of config
12598 	 * space.
12599 	 */
12600 	pci_info->InterruptVector = 0;
12601 	for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
12602 		pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
12603 		    i);
12604 	}
12605 }
12606 
12607 static int
12608 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
12609 {
12610 	int			status = 0;
12611 	mptsas_reg_access_t	driverdata;
12612 
12613 	mutex_enter(&mpt->m_mutex);
12614 	if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12615 		switch (driverdata.Command) {
12616 			/*
12617 			 * IO access is not supported.
12618 			 */
12619 			case REG_IO_READ:
12620 			case REG_IO_WRITE:
12621 				mptsas_log(mpt, CE_WARN, "IO access is not "
12622 				    "supported.  Use memory access.");
12623 				status = EINVAL;
12624 				break;
12625 
12626 			case REG_MEM_READ:
12627 				driverdata.RegData = ddi_get32(mpt->m_datap,
12628 				    (uint32_t *)(void *)mpt->m_reg +
12629 				    driverdata.RegOffset);
12630 				if (ddi_copyout(&driverdata.RegData,
12631 				    &data->RegData,
12632 				    sizeof (driverdata.RegData), mode) != 0) {
12633 					mptsas_log(mpt, CE_WARN, "Register "
12634 					    "Read Failed");
12635 					status = EFAULT;
12636 				}
12637 				break;
12638 
12639 			case REG_MEM_WRITE:
12640 				ddi_put32(mpt->m_datap,
12641 				    (uint32_t *)(void *)mpt->m_reg +
12642 				    driverdata.RegOffset,
12643 				    driverdata.RegData);
12644 				break;
12645 
12646 			default:
12647 				status = EINVAL;
12648 				break;
12649 		}
12650 	} else {
12651 		status = EFAULT;
12652 	}
12653 
12654 	mutex_exit(&mpt->m_mutex);
12655 	return (status);
12656 }
12657 
12658 static int
12659 led_control(mptsas_t *mpt, intptr_t data, int mode)
12660 {
12661 	int ret = 0;
12662 	mptsas_led_control_t lc;
12663 	mptsas_enclosure_t *mep;
12664 	uint16_t slotidx;
12665 
12666 	if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
12667 		return (EFAULT);
12668 	}
12669 
12670 	if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
12671 	    lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
12672 	    lc.Led < MPTSAS_LEDCTL_LED_MIN ||
12673 	    lc.Led > MPTSAS_LEDCTL_LED_MAX ||
12674 	    (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
12675 	    lc.LedStatus != 1)) {
12676 		return (EINVAL);
12677 	}
12678 
12679 	if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
12680 	    (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
12681 		return (EACCES);
12682 
12683 	/* Locate the required enclosure */
12684 	mutex_enter(&mpt->m_mutex);
12685 	mep = mptsas_enc_lookup(mpt, lc.Enclosure);
12686 	if (mep == NULL) {
12687 		mutex_exit(&mpt->m_mutex);
12688 		return (ENOENT);
12689 	}
12690 
12691 	if (lc.Slot < mep->me_fslot) {
12692 		mutex_exit(&mpt->m_mutex);
12693 		return (ENOENT);
12694 	}
12695 
12696 	/*
12697 	 * Slots on the enclosure are maintained in array where me_fslot is
12698 	 * entry zero. We normalize the requested slot.
12699 	 */
12700 	slotidx = lc.Slot - mep->me_fslot;
12701 	if (slotidx >= mep->me_nslots) {
12702 		mutex_exit(&mpt->m_mutex);
12703 		return (ENOENT);
12704 	}
12705 
12706 	if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
12707 		/* Update our internal LED state. */
12708 		mep->me_slotleds[slotidx] &= ~(1 << (lc.Led - 1));
12709 		mep->me_slotleds[slotidx] |= lc.LedStatus << (lc.Led - 1);
12710 
12711 		/* Flush it to the controller. */
12712 		ret = mptsas_flush_led_status(mpt, mep, slotidx);
12713 		mutex_exit(&mpt->m_mutex);
12714 		return (ret);
12715 	}
12716 
12717 	/* Return our internal LED state. */
12718 	lc.LedStatus = (mep->me_slotleds[slotidx] >> (lc.Led - 1)) & 1;
12719 	mutex_exit(&mpt->m_mutex);
12720 
12721 	if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
12722 		return (EFAULT);
12723 	}
12724 
12725 	return (0);
12726 }
12727 
12728 static int
12729 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
12730 {
12731 	uint16_t i = 0;
12732 	uint16_t count = 0;
12733 	int ret = 0;
12734 	mptsas_target_t *ptgt;
12735 	mptsas_disk_info_t *di;
12736 	STRUCT_DECL(mptsas_get_disk_info, gdi);
12737 
12738 	if ((mode & FREAD) == 0)
12739 		return (EACCES);
12740 
12741 	STRUCT_INIT(gdi, get_udatamodel());
12742 
12743 	if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
12744 	    mode) != 0) {
12745 		return (EFAULT);
12746 	}
12747 
12748 	/* Find out how many targets there are. */
12749 	mutex_enter(&mpt->m_mutex);
12750 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12751 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
12752 		count++;
12753 	}
12754 	mutex_exit(&mpt->m_mutex);
12755 
12756 	/*
12757 	 * If we haven't been asked to copy out information on each target,
12758 	 * then just return the count.
12759 	 */
12760 	STRUCT_FSET(gdi, DiskCount, count);
12761 	if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
12762 		goto copy_out;
12763 
12764 	/*
12765 	 * If we haven't been given a large enough buffer to copy out into,
12766 	 * let the caller know.
12767 	 */
12768 	if (STRUCT_FGET(gdi, DiskInfoArraySize) <
12769 	    count * sizeof (mptsas_disk_info_t)) {
12770 		ret = ENOSPC;
12771 		goto copy_out;
12772 	}
12773 
12774 	di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
12775 
12776 	mutex_enter(&mpt->m_mutex);
12777 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12778 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
12779 		if (i >= count) {
12780 			/*
12781 			 * The number of targets changed while we weren't
12782 			 * looking, so give up.
12783 			 */
12784 			refhash_rele(mpt->m_targets, ptgt);
12785 			mutex_exit(&mpt->m_mutex);
12786 			kmem_free(di, count * sizeof (mptsas_disk_info_t));
12787 			return (EAGAIN);
12788 		}
12789 		di[i].Instance = mpt->m_instance;
12790 		di[i].Enclosure = ptgt->m_enclosure;
12791 		di[i].Slot = ptgt->m_slot_num;
12792 		di[i].SasAddress = ptgt->m_addr.mta_wwn;
12793 		i++;
12794 	}
12795 	mutex_exit(&mpt->m_mutex);
12796 	STRUCT_FSET(gdi, DiskCount, i);
12797 
12798 	/* Copy out the disk information to the caller. */
12799 	if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
12800 	    i * sizeof (mptsas_disk_info_t), mode) != 0) {
12801 		ret = EFAULT;
12802 	}
12803 
12804 	kmem_free(di, count * sizeof (mptsas_disk_info_t));
12805 
12806 copy_out:
12807 	if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
12808 	    mode) != 0) {
12809 		ret = EFAULT;
12810 	}
12811 
12812 	return (ret);
12813 }
12814 
12815 static int
12816 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
12817     int *rval)
12818 {
12819 	int			status = 0;
12820 	mptsas_t		*mpt;
12821 	mptsas_update_flash_t	flashdata;
12822 	mptsas_pass_thru_t	passthru_data;
12823 	mptsas_adapter_data_t   adapter_data;
12824 	mptsas_pci_info_t	pci_info;
12825 	int			copylen;
12826 
12827 	int			iport_flag = 0;
12828 	dev_info_t		*dip = NULL;
12829 	mptsas_phymask_t	phymask = 0;
12830 	struct devctl_iocdata	*dcp = NULL;
12831 	char			*addr = NULL;
12832 	mptsas_target_t		*ptgt = NULL;
12833 
12834 	*rval = MPTIOCTL_STATUS_GOOD;
12835 	if (secpolicy_sys_config(credp, B_FALSE) != 0) {
12836 		return (EPERM);
12837 	}
12838 
12839 	mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
12840 	if (mpt == NULL) {
12841 		/*
12842 		 * Called from iport node, get the states
12843 		 */
12844 		iport_flag = 1;
12845 		dip = mptsas_get_dip_from_dev(dev, &phymask);
12846 		if (dip == NULL) {
12847 			return (ENXIO);
12848 		}
12849 		mpt = DIP2MPT(dip);
12850 	}
12851 	/* Make sure power level is D0 before accessing registers */
12852 	mutex_enter(&mpt->m_mutex);
12853 	if (mpt->m_options & MPTSAS_OPT_PM) {
12854 		(void) pm_busy_component(mpt->m_dip, 0);
12855 		if (mpt->m_power_level != PM_LEVEL_D0) {
12856 			mutex_exit(&mpt->m_mutex);
12857 			if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
12858 			    DDI_SUCCESS) {
12859 				mptsas_log(mpt, CE_WARN,
12860 				    "mptsas%d: mptsas_ioctl: Raise power "
12861 				    "request failed.", mpt->m_instance);
12862 				(void) pm_idle_component(mpt->m_dip, 0);
12863 				return (ENXIO);
12864 			}
12865 		} else {
12866 			mutex_exit(&mpt->m_mutex);
12867 		}
12868 	} else {
12869 		mutex_exit(&mpt->m_mutex);
12870 	}
12871 
12872 	if (iport_flag) {
12873 		status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
12874 		if (status != 0) {
12875 			goto out;
12876 		}
12877 		/*
12878 		 * The following code control the OK2RM LED, it doesn't affect
12879 		 * the ioctl return status.
12880 		 */
12881 		if ((cmd == DEVCTL_DEVICE_ONLINE) ||
12882 		    (cmd == DEVCTL_DEVICE_OFFLINE)) {
12883 			if (ndi_dc_allochdl((void *)data, &dcp) !=
12884 			    NDI_SUCCESS) {
12885 				goto out;
12886 			}
12887 			addr = ndi_dc_getaddr(dcp);
12888 			ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
12889 			if (ptgt == NULL) {
12890 				NDBG14(("mptsas_ioctl led control: tgt %s not "
12891 				    "found", addr));
12892 				ndi_dc_freehdl(dcp);
12893 				goto out;
12894 			}
12895 			ndi_dc_freehdl(dcp);
12896 		}
12897 		goto out;
12898 	}
12899 	switch (cmd) {
12900 		case MPTIOCTL_GET_DISK_INFO:
12901 			status = get_disk_info(mpt, data, mode);
12902 			break;
12903 		case MPTIOCTL_LED_CONTROL:
12904 			status = led_control(mpt, data, mode);
12905 			break;
12906 		case MPTIOCTL_UPDATE_FLASH:
12907 			if (ddi_copyin((void *)data, &flashdata,
12908 				sizeof (struct mptsas_update_flash), mode)) {
12909 				status = EFAULT;
12910 				break;
12911 			}
12912 
12913 			mutex_enter(&mpt->m_mutex);
12914 			if (mptsas_update_flash(mpt,
12915 			    (caddr_t)(long)flashdata.PtrBuffer,
12916 			    flashdata.ImageSize, flashdata.ImageType, mode)) {
12917 				status = EFAULT;
12918 			}
12919 
12920 			/*
12921 			 * Reset the chip to start using the new
12922 			 * firmware.  Reset if failed also.
12923 			 */
12924 			mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12925 			if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
12926 				status = EFAULT;
12927 			}
12928 			mutex_exit(&mpt->m_mutex);
12929 			break;
12930 		case MPTIOCTL_PASS_THRU:
12931 			/*
12932 			 * The user has requested to pass through a command to
12933 			 * be executed by the MPT firmware.  Call our routine
12934 			 * which does this.  Only allow one passthru IOCTL at
12935 			 * one time. Other threads will block on
12936 			 * m_passthru_mutex, which is of adaptive variant.
12937 			 */
12938 			if (ddi_copyin((void *)data, &passthru_data,
12939 			    sizeof (mptsas_pass_thru_t), mode)) {
12940 				status = EFAULT;
12941 				break;
12942 			}
12943 			mutex_enter(&mpt->m_passthru_mutex);
12944 			mutex_enter(&mpt->m_mutex);
12945 			status = mptsas_pass_thru(mpt, &passthru_data, mode);
12946 			mutex_exit(&mpt->m_mutex);
12947 			mutex_exit(&mpt->m_passthru_mutex);
12948 
12949 			break;
12950 		case MPTIOCTL_GET_ADAPTER_DATA:
12951 			/*
12952 			 * The user has requested to read adapter data.  Call
12953 			 * our routine which does this.
12954 			 */
12955 			bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
12956 			if (ddi_copyin((void *)data, (void *)&adapter_data,
12957 			    sizeof (mptsas_adapter_data_t), mode)) {
12958 				status = EFAULT;
12959 				break;
12960 			}
12961 			if (adapter_data.StructureLength >=
12962 			    sizeof (mptsas_adapter_data_t)) {
12963 				adapter_data.StructureLength = (uint32_t)
12964 				    sizeof (mptsas_adapter_data_t);
12965 				copylen = sizeof (mptsas_adapter_data_t);
12966 				mutex_enter(&mpt->m_mutex);
12967 				mptsas_read_adapter_data(mpt, &adapter_data);
12968 				mutex_exit(&mpt->m_mutex);
12969 			} else {
12970 				adapter_data.StructureLength = (uint32_t)
12971 				    sizeof (mptsas_adapter_data_t);
12972 				copylen = sizeof (adapter_data.StructureLength);
12973 				*rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12974 			}
12975 			if (ddi_copyout((void *)(&adapter_data), (void *)data,
12976 			    copylen, mode) != 0) {
12977 				status = EFAULT;
12978 			}
12979 			break;
12980 		case MPTIOCTL_GET_PCI_INFO:
12981 			/*
12982 			 * The user has requested to read pci info.  Call
12983 			 * our routine which does this.
12984 			 */
12985 			bzero(&pci_info, sizeof (mptsas_pci_info_t));
12986 			mutex_enter(&mpt->m_mutex);
12987 			mptsas_read_pci_info(mpt, &pci_info);
12988 			mutex_exit(&mpt->m_mutex);
12989 			if (ddi_copyout((void *)(&pci_info), (void *)data,
12990 			    sizeof (mptsas_pci_info_t), mode) != 0) {
12991 				status = EFAULT;
12992 			}
12993 			break;
12994 		case MPTIOCTL_RESET_ADAPTER:
12995 			mutex_enter(&mpt->m_mutex);
12996 			mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12997 			if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
12998 				mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
12999 				    "failed");
13000 				status = EFAULT;
13001 			}
13002 			mutex_exit(&mpt->m_mutex);
13003 			break;
13004 		case MPTIOCTL_DIAG_ACTION:
13005 			/*
13006 			 * The user has done a diag buffer action.  Call our
13007 			 * routine which does this.  Only allow one diag action
13008 			 * at one time.
13009 			 */
13010 			mutex_enter(&mpt->m_mutex);
13011 			if (mpt->m_diag_action_in_progress) {
13012 				mutex_exit(&mpt->m_mutex);
13013 				return (EBUSY);
13014 			}
13015 			mpt->m_diag_action_in_progress = 1;
13016 			status = mptsas_diag_action(mpt,
13017 			    (mptsas_diag_action_t *)data, mode);
13018 			mpt->m_diag_action_in_progress = 0;
13019 			mutex_exit(&mpt->m_mutex);
13020 			break;
13021 		case MPTIOCTL_EVENT_QUERY:
13022 			/*
13023 			 * The user has done an event query. Call our routine
13024 			 * which does this.
13025 			 */
13026 			status = mptsas_event_query(mpt,
13027 			    (mptsas_event_query_t *)data, mode, rval);
13028 			break;
13029 		case MPTIOCTL_EVENT_ENABLE:
13030 			/*
13031 			 * The user has done an event enable. Call our routine
13032 			 * which does this.
13033 			 */
13034 			status = mptsas_event_enable(mpt,
13035 			    (mptsas_event_enable_t *)data, mode, rval);
13036 			break;
13037 		case MPTIOCTL_EVENT_REPORT:
13038 			/*
13039 			 * The user has done an event report. Call our routine
13040 			 * which does this.
13041 			 */
13042 			status = mptsas_event_report(mpt,
13043 			    (mptsas_event_report_t *)data, mode, rval);
13044 			break;
13045 		case MPTIOCTL_REG_ACCESS:
13046 			/*
13047 			 * The user has requested register access.  Call our
13048 			 * routine which does this.
13049 			 */
13050 			status = mptsas_reg_access(mpt,
13051 			    (mptsas_reg_access_t *)data, mode);
13052 			break;
13053 		default:
13054 			status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
13055 			    rval);
13056 			break;
13057 	}
13058 
13059 out:
13060 	return (status);
13061 }
13062 
13063 int
13064 mptsas_restart_ioc(mptsas_t *mpt)
13065 {
13066 	int		rval = DDI_SUCCESS;
13067 	mptsas_target_t	*ptgt = NULL;
13068 
13069 	ASSERT(mutex_owned(&mpt->m_mutex));
13070 
13071 	/*
13072 	 * Set a flag telling I/O path that we're processing a reset.  This is
13073 	 * needed because after the reset is complete, the hash table still
13074 	 * needs to be rebuilt.  If I/Os are started before the hash table is
13075 	 * rebuilt, I/O errors will occur.  This flag allows I/Os to be marked
13076 	 * so that they can be retried.
13077 	 */
13078 	mpt->m_in_reset = TRUE;
13079 
13080 	/*
13081 	 * Wait until all the allocated sense data buffers for DMA are freed.
13082 	 */
13083 	while (mpt->m_extreq_sense_refcount > 0)
13084 		cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex);
13085 
13086 	/*
13087 	 * Set all throttles to HOLD
13088 	 */
13089 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13090 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
13091 		mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
13092 	}
13093 
13094 	/*
13095 	 * Disable interrupts
13096 	 */
13097 	MPTSAS_DISABLE_INTR(mpt);
13098 
13099 	/*
13100 	 * Abort all commands: outstanding commands, commands in waitq and
13101 	 * tx_waitq.
13102 	 */
13103 	mptsas_flush_hba(mpt);
13104 
13105 	/*
13106 	 * Reinitialize the chip.
13107 	 */
13108 	if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
13109 		rval = DDI_FAILURE;
13110 	}
13111 
13112 	/*
13113 	 * Enable interrupts again
13114 	 */
13115 	MPTSAS_ENABLE_INTR(mpt);
13116 
13117 	/*
13118 	 * If mptsas_init_chip was successful, update the driver data.
13119 	 */
13120 	if (rval == DDI_SUCCESS) {
13121 		mptsas_update_driver_data(mpt);
13122 	}
13123 
13124 	/*
13125 	 * Reset the throttles
13126 	 */
13127 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13128 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
13129 		mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
13130 	}
13131 
13132 	mptsas_doneq_empty(mpt);
13133 	mptsas_restart_hba(mpt);
13134 
13135 	if (rval != DDI_SUCCESS) {
13136 		mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
13137 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
13138 	}
13139 
13140 	/*
13141 	 * Clear the reset flag so that I/Os can continue.
13142 	 */
13143 	mpt->m_in_reset = FALSE;
13144 
13145 	return (rval);
13146 }
13147 
13148 static int
13149 mptsas_init_chip(mptsas_t *mpt, int first_time)
13150 {
13151 	ddi_dma_cookie_t	cookie;
13152 	uint32_t		i;
13153 	int			rval;
13154 
13155 	/*
13156 	 * Check to see if the firmware image is valid
13157 	 */
13158 	if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
13159 	    MPI2_DIAG_FLASH_BAD_SIG) {
13160 		mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
13161 		goto fail;
13162 	}
13163 
13164 	/*
13165 	 * Reset the chip
13166 	 */
13167 	rval = mptsas_ioc_reset(mpt, first_time);
13168 	if (rval == MPTSAS_RESET_FAIL) {
13169 		mptsas_log(mpt, CE_WARN, "hard reset failed!");
13170 		goto fail;
13171 	}
13172 
13173 	if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
13174 		goto mur;
13175 	}
13176 	/*
13177 	 * Setup configuration space
13178 	 */
13179 	if (mptsas_config_space_init(mpt) == FALSE) {
13180 		mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
13181 		    "failed!");
13182 		goto fail;
13183 	}
13184 
13185 	/*
13186 	 * IOC facts can change after a diag reset so all buffers that are
13187 	 * based on these numbers must be de-allocated and re-allocated.  Get
13188 	 * new IOC facts each time chip is initialized.
13189 	 */
13190 	if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
13191 		mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
13192 		goto fail;
13193 	}
13194 
13195 	if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
13196 		goto fail;
13197 	}
13198 	/*
13199 	 * Allocate request message frames, reply free queue, reply descriptor
13200 	 * post queue, and reply message frames using latest IOC facts.
13201 	 */
13202 	if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
13203 		mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
13204 		goto fail;
13205 	}
13206 	if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) {
13207 		mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed");
13208 		goto fail;
13209 	}
13210 	if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
13211 		mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
13212 		goto fail;
13213 	}
13214 	if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
13215 		mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
13216 		goto fail;
13217 	}
13218 	if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
13219 		mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
13220 		goto fail;
13221 	}
13222 
13223 mur:
13224 	/*
13225 	 * Re-Initialize ioc to operational state
13226 	 */
13227 	if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
13228 		mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
13229 		goto fail;
13230 	}
13231 
13232 	mptsas_alloc_reply_args(mpt);
13233 
13234 	/*
13235 	 * Initialize reply post index.  Reply free index is initialized after
13236 	 * the next loop.
13237 	 */
13238 	mpt->m_post_index = 0;
13239 
13240 	/*
13241 	 * Initialize the Reply Free Queue with the physical addresses of our
13242 	 * reply frames.
13243 	 */
13244 	cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu;
13245 	for (i = 0; i < mpt->m_max_replies; i++) {
13246 		ddi_put32(mpt->m_acc_free_queue_hdl,
13247 		    &((uint32_t *)(void *)mpt->m_free_queue)[i],
13248 		    cookie.dmac_address);
13249 		cookie.dmac_address += mpt->m_reply_frame_size;
13250 	}
13251 	(void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
13252 	    DDI_DMA_SYNC_FORDEV);
13253 
13254 	/*
13255 	 * Initialize the reply free index to one past the last frame on the
13256 	 * queue.  This will signify that the queue is empty to start with.
13257 	 */
13258 	mpt->m_free_index = i;
13259 	ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
13260 
13261 	/*
13262 	 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
13263 	 */
13264 	for (i = 0; i < mpt->m_post_queue_depth; i++) {
13265 		ddi_put64(mpt->m_acc_post_queue_hdl,
13266 		    &((uint64_t *)(void *)mpt->m_post_queue)[i],
13267 		    0xFFFFFFFFFFFFFFFF);
13268 	}
13269 	(void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
13270 	    DDI_DMA_SYNC_FORDEV);
13271 
13272 	/*
13273 	 * Enable ports
13274 	 */
13275 	if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
13276 		mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
13277 		goto fail;
13278 	}
13279 
13280 	/*
13281 	 * enable events
13282 	 */
13283 	if (mptsas_ioc_enable_event_notification(mpt)) {
13284 		mptsas_log(mpt, CE_WARN,
13285 		    "mptsas_ioc_enable_event_notification failed");
13286 		goto fail;
13287 	}
13288 
13289 	/*
13290 	 * We need checks in attach and these.
13291 	 * chip_init is called in mult. places
13292 	 */
13293 
13294 	if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
13295 	    DDI_SUCCESS) ||
13296 	    (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
13297 	    DDI_SUCCESS) ||
13298 	    (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
13299 	    DDI_SUCCESS) ||
13300 	    (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
13301 	    DDI_SUCCESS) ||
13302 	    (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
13303 	    DDI_SUCCESS) ||
13304 	    (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
13305 	    DDI_SUCCESS)) {
13306 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13307 		goto fail;
13308 	}
13309 
13310 	/* Check all acc handles */
13311 	if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
13312 	    (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
13313 	    DDI_SUCCESS) ||
13314 	    (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
13315 	    DDI_SUCCESS) ||
13316 	    (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
13317 	    DDI_SUCCESS) ||
13318 	    (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
13319 	    DDI_SUCCESS) ||
13320 	    (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
13321 	    DDI_SUCCESS) ||
13322 	    (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
13323 	    DDI_SUCCESS) ||
13324 	    (mptsas_check_acc_handle(mpt->m_config_handle) !=
13325 	    DDI_SUCCESS)) {
13326 		ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13327 		goto fail;
13328 	}
13329 
13330 	return (DDI_SUCCESS);
13331 
13332 fail:
13333 	return (DDI_FAILURE);
13334 }
13335 
13336 static int
13337 mptsas_get_pci_cap(mptsas_t *mpt)
13338 {
13339 	ushort_t caps_ptr, cap, cap_count;
13340 
13341 	if (mpt->m_config_handle == NULL)
13342 		return (FALSE);
13343 	/*
13344 	 * Check if capabilities list is supported and if so,
13345 	 * get initial capabilities pointer and clear bits 0,1.
13346 	 */
13347 	if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
13348 	    & PCI_STAT_CAP) {
13349 		caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13350 		    PCI_CONF_CAP_PTR), 4);
13351 	} else {
13352 		caps_ptr = PCI_CAP_NEXT_PTR_NULL;
13353 	}
13354 
13355 	/*
13356 	 * Walk capabilities if supported.
13357 	 */
13358 	for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
13359 
13360 		/*
13361 		 * Check that we haven't exceeded the maximum number of
13362 		 * capabilities and that the pointer is in a valid range.
13363 		 */
13364 		if (++cap_count > 48) {
13365 			mptsas_log(mpt, CE_WARN,
13366 			    "too many device capabilities.\n");
13367 			break;
13368 		}
13369 		if (caps_ptr < 64) {
13370 			mptsas_log(mpt, CE_WARN,
13371 			    "capabilities pointer 0x%x out of range.\n",
13372 			    caps_ptr);
13373 			break;
13374 		}
13375 
13376 		/*
13377 		 * Get next capability and check that it is valid.
13378 		 * For now, we only support power management.
13379 		 */
13380 		cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
13381 		switch (cap) {
13382 			case PCI_CAP_ID_PM:
13383 				mptsas_log(mpt, CE_NOTE,
13384 				    "?mptsas%d supports power management.\n",
13385 				    mpt->m_instance);
13386 				mpt->m_options |= MPTSAS_OPT_PM;
13387 
13388 				/* Save PMCSR offset */
13389 				mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
13390 				break;
13391 			/*
13392 			 * The following capabilities are valid.  Any others
13393 			 * will cause a message to be logged.
13394 			 */
13395 			case PCI_CAP_ID_VPD:
13396 			case PCI_CAP_ID_MSI:
13397 			case PCI_CAP_ID_PCIX:
13398 			case PCI_CAP_ID_PCI_E:
13399 			case PCI_CAP_ID_MSI_X:
13400 				break;
13401 			default:
13402 				mptsas_log(mpt, CE_NOTE,
13403 				    "?mptsas%d unrecognized capability "
13404 				    "0x%x.\n", mpt->m_instance, cap);
13405 				break;
13406 		}
13407 
13408 		/*
13409 		 * Get next capabilities pointer and clear bits 0,1.
13410 		 */
13411 		caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13412 		    (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
13413 	}
13414 	return (TRUE);
13415 }
13416 
13417 static int
13418 mptsas_init_pm(mptsas_t *mpt)
13419 {
13420 	char		pmc_name[16];
13421 	char		*pmc[] = {
13422 				NULL,
13423 				"0=Off (PCI D3 State)",
13424 				"3=On (PCI D0 State)",
13425 				NULL
13426 			};
13427 	uint16_t	pmcsr_stat;
13428 
13429 	if (mptsas_get_pci_cap(mpt) == FALSE) {
13430 		return (DDI_FAILURE);
13431 	}
13432 	/*
13433 	 * If PCI's capability does not support PM, then don't need
13434 	 * to registe the pm-components
13435 	 */
13436 	if (!(mpt->m_options & MPTSAS_OPT_PM))
13437 		return (DDI_SUCCESS);
13438 	/*
13439 	 * If power management is supported by this chip, create
13440 	 * pm-components property for the power management framework
13441 	 */
13442 	(void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
13443 	pmc[0] = pmc_name;
13444 	if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
13445 	    "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
13446 		mpt->m_options &= ~MPTSAS_OPT_PM;
13447 		mptsas_log(mpt, CE_WARN,
13448 		    "mptsas%d: pm-component property creation failed.",
13449 		    mpt->m_instance);
13450 		return (DDI_FAILURE);
13451 	}
13452 
13453 	/*
13454 	 * Power on device.
13455 	 */
13456 	(void) pm_busy_component(mpt->m_dip, 0);
13457 	pmcsr_stat = pci_config_get16(mpt->m_config_handle,
13458 	    mpt->m_pmcsr_offset);
13459 	if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
13460 		mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
13461 		    mpt->m_instance);
13462 		pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
13463 		    PCI_PMCSR_D0);
13464 	}
13465 	if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
13466 		mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
13467 		return (DDI_FAILURE);
13468 	}
13469 	mpt->m_power_level = PM_LEVEL_D0;
13470 	/*
13471 	 * Set pm idle delay.
13472 	 */
13473 	mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
13474 	    mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
13475 
13476 	return (DDI_SUCCESS);
13477 }
13478 
13479 static int
13480 mptsas_register_intrs(mptsas_t *mpt)
13481 {
13482 	dev_info_t *dip;
13483 	int intr_types;
13484 
13485 	dip = mpt->m_dip;
13486 
13487 	/* Get supported interrupt types */
13488 	if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
13489 		mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
13490 		    "failed\n");
13491 		return (FALSE);
13492 	}
13493 
13494 	NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
13495 
13496 	/*
13497 	 * Try MSI, but fall back to FIXED
13498 	 */
13499 	if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
13500 		if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
13501 			NDBG0(("Using MSI interrupt type"));
13502 			mpt->m_intr_type = DDI_INTR_TYPE_MSI;
13503 			return (TRUE);
13504 		}
13505 	}
13506 	if (intr_types & DDI_INTR_TYPE_FIXED) {
13507 		if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
13508 			NDBG0(("Using FIXED interrupt type"));
13509 			mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
13510 			return (TRUE);
13511 		} else {
13512 			NDBG0(("FIXED interrupt registration failed"));
13513 			return (FALSE);
13514 		}
13515 	}
13516 
13517 	return (FALSE);
13518 }
13519 
13520 static void
13521 mptsas_unregister_intrs(mptsas_t *mpt)
13522 {
13523 	mptsas_rem_intrs(mpt);
13524 }
13525 
13526 /*
13527  * mptsas_add_intrs:
13528  *
13529  * Register FIXED or MSI interrupts.
13530  */
13531 static int
13532 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
13533 {
13534 	dev_info_t	*dip = mpt->m_dip;
13535 	int		avail, actual, count = 0;
13536 	int		i, flag, ret;
13537 
13538 	NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
13539 
13540 	/* Get number of interrupts */
13541 	ret = ddi_intr_get_nintrs(dip, intr_type, &count);
13542 	if ((ret != DDI_SUCCESS) || (count <= 0)) {
13543 		mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
13544 		    "ret %d count %d\n", ret, count);
13545 
13546 		return (DDI_FAILURE);
13547 	}
13548 
13549 	/* Get number of available interrupts */
13550 	ret = ddi_intr_get_navail(dip, intr_type, &avail);
13551 	if ((ret != DDI_SUCCESS) || (avail == 0)) {
13552 		mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
13553 		    "ret %d avail %d\n", ret, avail);
13554 
13555 		return (DDI_FAILURE);
13556 	}
13557 
13558 	if (avail < count) {
13559 		mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
13560 		    "navail() returned %d", count, avail);
13561 	}
13562 
13563 	/* Mpt only have one interrupt routine */
13564 	if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
13565 		count = 1;
13566 	}
13567 
13568 	/* Allocate an array of interrupt handles */
13569 	mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
13570 	mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
13571 
13572 	flag = DDI_INTR_ALLOC_NORMAL;
13573 
13574 	/* call ddi_intr_alloc() */
13575 	ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
13576 	    count, &actual, flag);
13577 
13578 	if ((ret != DDI_SUCCESS) || (actual == 0)) {
13579 		mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
13580 		    ret);
13581 		kmem_free(mpt->m_htable, mpt->m_intr_size);
13582 		return (DDI_FAILURE);
13583 	}
13584 
13585 	/* use interrupt count returned or abort? */
13586 	if (actual < count) {
13587 		mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
13588 		    count, actual);
13589 	}
13590 
13591 	mpt->m_intr_cnt = actual;
13592 
13593 	/*
13594 	 * Get priority for first msi, assume remaining are all the same
13595 	 */
13596 	if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
13597 	    &mpt->m_intr_pri)) != DDI_SUCCESS) {
13598 		mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
13599 
13600 		/* Free already allocated intr */
13601 		for (i = 0; i < actual; i++) {
13602 			(void) ddi_intr_free(mpt->m_htable[i]);
13603 		}
13604 
13605 		kmem_free(mpt->m_htable, mpt->m_intr_size);
13606 		return (DDI_FAILURE);
13607 	}
13608 
13609 	/* Test for high level mutex */
13610 	if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
13611 		mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
13612 		    "Hi level interrupt not supported\n");
13613 
13614 		/* Free already allocated intr */
13615 		for (i = 0; i < actual; i++) {
13616 			(void) ddi_intr_free(mpt->m_htable[i]);
13617 		}
13618 
13619 		kmem_free(mpt->m_htable, mpt->m_intr_size);
13620 		return (DDI_FAILURE);
13621 	}
13622 
13623 	/* Call ddi_intr_add_handler() */
13624 	for (i = 0; i < actual; i++) {
13625 		if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
13626 		    (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
13627 			mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
13628 			    "failed %d\n", ret);
13629 
13630 			/* Free already allocated intr */
13631 			for (i = 0; i < actual; i++) {
13632 				(void) ddi_intr_free(mpt->m_htable[i]);
13633 			}
13634 
13635 			kmem_free(mpt->m_htable, mpt->m_intr_size);
13636 			return (DDI_FAILURE);
13637 		}
13638 	}
13639 
13640 	if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
13641 	    != DDI_SUCCESS) {
13642 		mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
13643 
13644 		/* Free already allocated intr */
13645 		for (i = 0; i < actual; i++) {
13646 			(void) ddi_intr_free(mpt->m_htable[i]);
13647 		}
13648 
13649 		kmem_free(mpt->m_htable, mpt->m_intr_size);
13650 		return (DDI_FAILURE);
13651 	}
13652 
13653 	/*
13654 	 * Enable interrupts
13655 	 */
13656 	if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13657 		/* Call ddi_intr_block_enable() for MSI interrupts */
13658 		(void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
13659 	} else {
13660 		/* Call ddi_intr_enable for MSI or FIXED interrupts */
13661 		for (i = 0; i < mpt->m_intr_cnt; i++) {
13662 			(void) ddi_intr_enable(mpt->m_htable[i]);
13663 		}
13664 	}
13665 	return (DDI_SUCCESS);
13666 }
13667 
13668 /*
13669  * mptsas_rem_intrs:
13670  *
13671  * Unregister FIXED or MSI interrupts
13672  */
13673 static void
13674 mptsas_rem_intrs(mptsas_t *mpt)
13675 {
13676 	int	i;
13677 
13678 	NDBG6(("mptsas_rem_intrs"));
13679 
13680 	/* Disable all interrupts */
13681 	if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13682 		/* Call ddi_intr_block_disable() */
13683 		(void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
13684 	} else {
13685 		for (i = 0; i < mpt->m_intr_cnt; i++) {
13686 			(void) ddi_intr_disable(mpt->m_htable[i]);
13687 		}
13688 	}
13689 
13690 	/* Call ddi_intr_remove_handler() */
13691 	for (i = 0; i < mpt->m_intr_cnt; i++) {
13692 		(void) ddi_intr_remove_handler(mpt->m_htable[i]);
13693 		(void) ddi_intr_free(mpt->m_htable[i]);
13694 	}
13695 
13696 	kmem_free(mpt->m_htable, mpt->m_intr_size);
13697 }
13698 
13699 /*
13700  * The IO fault service error handling callback function
13701  */
13702 /*ARGSUSED*/
13703 static int
13704 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
13705 {
13706 	/*
13707 	 * as the driver can always deal with an error in any dma or
13708 	 * access handle, we can just return the fme_status value.
13709 	 */
13710 	pci_ereport_post(dip, err, NULL);
13711 	return (err->fme_status);
13712 }
13713 
13714 /*
13715  * mptsas_fm_init - initialize fma capabilities and register with IO
13716  *               fault services.
13717  */
13718 static void
13719 mptsas_fm_init(mptsas_t *mpt)
13720 {
13721 	/*
13722 	 * Need to change iblock to priority for new MSI intr
13723 	 */
13724 	ddi_iblock_cookie_t	fm_ibc;
13725 
13726 	/* Only register with IO Fault Services if we have some capability */
13727 	if (mpt->m_fm_capabilities) {
13728 		/* Adjust access and dma attributes for FMA */
13729 		mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
13730 		mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13731 		mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13732 
13733 		/*
13734 		 * Register capabilities with IO Fault Services.
13735 		 * mpt->m_fm_capabilities will be updated to indicate
13736 		 * capabilities actually supported (not requested.)
13737 		 */
13738 		ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
13739 
13740 		/*
13741 		 * Initialize pci ereport capabilities if ereport
13742 		 * capable (should always be.)
13743 		 */
13744 		if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13745 		    DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13746 			pci_ereport_setup(mpt->m_dip);
13747 		}
13748 
13749 		/*
13750 		 * Register error callback if error callback capable.
13751 		 */
13752 		if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13753 			ddi_fm_handler_register(mpt->m_dip,
13754 			    mptsas_fm_error_cb, (void *) mpt);
13755 		}
13756 	}
13757 }
13758 
13759 /*
13760  * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
13761  *               fault services.
13762  *
13763  */
13764 static void
13765 mptsas_fm_fini(mptsas_t *mpt)
13766 {
13767 	/* Only unregister FMA capabilities if registered */
13768 	if (mpt->m_fm_capabilities) {
13769 
13770 		/*
13771 		 * Un-register error callback if error callback capable.
13772 		 */
13773 
13774 		if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13775 			ddi_fm_handler_unregister(mpt->m_dip);
13776 		}
13777 
13778 		/*
13779 		 * Release any resources allocated by pci_ereport_setup()
13780 		 */
13781 
13782 		if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13783 		    DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13784 			pci_ereport_teardown(mpt->m_dip);
13785 		}
13786 
13787 		/* Unregister from IO Fault Services */
13788 		ddi_fm_fini(mpt->m_dip);
13789 
13790 		/* Adjust access and dma attributes for FMA */
13791 		mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
13792 		mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13793 		mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13794 
13795 	}
13796 }
13797 
13798 int
13799 mptsas_check_acc_handle(ddi_acc_handle_t handle)
13800 {
13801 	ddi_fm_error_t	de;
13802 
13803 	if (handle == NULL)
13804 		return (DDI_FAILURE);
13805 	ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
13806 	return (de.fme_status);
13807 }
13808 
13809 int
13810 mptsas_check_dma_handle(ddi_dma_handle_t handle)
13811 {
13812 	ddi_fm_error_t	de;
13813 
13814 	if (handle == NULL)
13815 		return (DDI_FAILURE);
13816 	ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
13817 	return (de.fme_status);
13818 }
13819 
13820 void
13821 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
13822 {
13823 	uint64_t	ena;
13824 	char		buf[FM_MAX_CLASS];
13825 
13826 	(void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
13827 	ena = fm_ena_generate(0, FM_ENA_FMT1);
13828 	if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
13829 		ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
13830 		    FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
13831 	}
13832 }
13833 
13834 static int
13835 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
13836     uint16_t *dev_handle, mptsas_target_t **pptgt)
13837 {
13838 	int		rval;
13839 	uint32_t	dev_info;
13840 	uint64_t	sas_wwn;
13841 	mptsas_phymask_t phymask;
13842 	uint8_t		physport, phynum, config, disk;
13843 	uint64_t	devicename;
13844 	uint16_t	pdev_hdl;
13845 	mptsas_target_t	*tmp_tgt = NULL;
13846 	uint16_t	bay_num, enclosure, io_flags;
13847 
13848 	ASSERT(*pptgt == NULL);
13849 
13850 	rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
13851 	    &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
13852 	    &bay_num, &enclosure, &io_flags);
13853 	if (rval != DDI_SUCCESS) {
13854 		rval = DEV_INFO_FAIL_PAGE0;
13855 		return (rval);
13856 	}
13857 
13858 	if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
13859 	    MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13860 	    MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
13861 		rval = DEV_INFO_WRONG_DEVICE_TYPE;
13862 		return (rval);
13863 	}
13864 
13865 	/*
13866 	 * Check if the dev handle is for a Phys Disk. If so, set return value
13867 	 * and exit.  Don't add Phys Disks to hash.
13868 	 */
13869 	for (config = 0; config < mpt->m_num_raid_configs; config++) {
13870 		for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
13871 			if (*dev_handle == mpt->m_raidconfig[config].
13872 			    m_physdisk_devhdl[disk]) {
13873 				rval = DEV_INFO_PHYS_DISK;
13874 				return (rval);
13875 			}
13876 		}
13877 	}
13878 
13879 	/*
13880 	 * Get SATA Device Name from SAS device page0 for
13881 	 * sata device, if device name doesn't exist, set mta_wwn to
13882 	 * 0 for direct attached SATA. For the device behind the expander
13883 	 * we still can use STP address assigned by expander.
13884 	 */
13885 	if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13886 	    MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13887 		/* alloc a temporary target to send the cmd to */
13888 		tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle,
13889 		    0, dev_info, 0, 0);
13890 		mutex_exit(&mpt->m_mutex);
13891 
13892 		devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
13893 
13894 		if (devicename == -1) {
13895 			mutex_enter(&mpt->m_mutex);
13896 			refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13897 			rval = DEV_INFO_FAIL_GUID;
13898 			return (rval);
13899 		}
13900 
13901 		if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
13902 			sas_wwn = devicename;
13903 		} else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
13904 			sas_wwn = 0;
13905 		}
13906 
13907 		mutex_enter(&mpt->m_mutex);
13908 		refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13909 	}
13910 
13911 	phymask = mptsas_physport_to_phymask(mpt, physport);
13912 	*pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn,
13913 	    dev_info, phymask, phynum);
13914 	if (*pptgt == NULL) {
13915 		mptsas_log(mpt, CE_WARN, "Failed to allocated target"
13916 		    "structure!");
13917 		rval = DEV_INFO_FAIL_ALLOC;
13918 		return (rval);
13919 	}
13920 	(*pptgt)->m_io_flags = io_flags;
13921 	(*pptgt)->m_enclosure = enclosure;
13922 	(*pptgt)->m_slot_num = bay_num;
13923 	return (DEV_INFO_SUCCESS);
13924 }
13925 
13926 uint64_t
13927 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
13928 {
13929 	uint64_t	sata_guid = 0, *pwwn = NULL;
13930 	int		target = ptgt->m_devhdl;
13931 	uchar_t		*inq83 = NULL;
13932 	int		inq83_len = 0xFF;
13933 	uchar_t		*dblk = NULL;
13934 	int		inq83_retry = 3;
13935 	int		rval = DDI_FAILURE;
13936 
13937 	inq83	= kmem_zalloc(inq83_len, KM_SLEEP);
13938 
13939 inq83_retry:
13940 	rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13941 	    inq83_len, NULL, 1);
13942 	if (rval != DDI_SUCCESS) {
13943 		mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13944 		    "0x83 for target:%x, lun:%x failed!", target, lun);
13945 		sata_guid = -1;
13946 		goto out;
13947 	}
13948 	/* According to SAT2, the first descriptor is logic unit name */
13949 	dblk = &inq83[4];
13950 	if ((dblk[1] & 0x30) != 0) {
13951 		mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
13952 		goto out;
13953 	}
13954 	pwwn = (uint64_t *)(void *)(&dblk[4]);
13955 	if ((dblk[4] & 0xf0) == 0x50) {
13956 		sata_guid = BE_64(*pwwn);
13957 		goto out;
13958 	} else if (dblk[4] == 'A') {
13959 		NDBG20(("SATA drive has no NAA format GUID."));
13960 		goto out;
13961 	} else {
13962 		/* The data is not ready, wait and retry */
13963 		inq83_retry--;
13964 		if (inq83_retry <= 0) {
13965 			goto out;
13966 		}
13967 		NDBG20(("The GUID is not ready, retry..."));
13968 		delay(1 * drv_usectohz(1000000));
13969 		goto inq83_retry;
13970 	}
13971 out:
13972 	kmem_free(inq83, inq83_len);
13973 	return (sata_guid);
13974 }
13975 
13976 static int
13977 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
13978     unsigned char *buf, int len, int *reallen, uchar_t evpd)
13979 {
13980 	uchar_t			cdb[CDB_GROUP0];
13981 	struct scsi_address	ap;
13982 	struct buf		*data_bp = NULL;
13983 	int			resid = 0;
13984 	int			ret = DDI_FAILURE;
13985 
13986 	ASSERT(len <= 0xffff);
13987 
13988 	ap.a_target = MPTSAS_INVALID_DEVHDL;
13989 	ap.a_lun = (uchar_t)(lun);
13990 	ap.a_hba_tran = mpt->m_tran;
13991 
13992 	data_bp = scsi_alloc_consistent_buf(&ap,
13993 	    (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
13994 	if (data_bp == NULL) {
13995 		return (ret);
13996 	}
13997 	bzero(cdb, CDB_GROUP0);
13998 	cdb[0] = SCMD_INQUIRY;
13999 	cdb[1] = evpd;
14000 	cdb[2] = page;
14001 	cdb[3] = (len & 0xff00) >> 8;
14002 	cdb[4] = (len & 0x00ff);
14003 	cdb[5] = 0;
14004 
14005 	ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
14006 	    &resid);
14007 	if (ret == DDI_SUCCESS) {
14008 		if (reallen) {
14009 			*reallen = len - resid;
14010 		}
14011 		bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
14012 	}
14013 	if (data_bp) {
14014 		scsi_free_consistent_buf(data_bp);
14015 	}
14016 	return (ret);
14017 }
14018 
14019 static int
14020 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
14021     mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
14022     int *resid)
14023 {
14024 	struct scsi_pkt		*pktp = NULL;
14025 	scsi_hba_tran_t		*tran_clone = NULL;
14026 	mptsas_tgt_private_t	*tgt_private = NULL;
14027 	int			ret = DDI_FAILURE;
14028 
14029 	/*
14030 	 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
14031 	 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
14032 	 * to simulate the cmds from sd
14033 	 */
14034 	tran_clone = kmem_alloc(
14035 	    sizeof (scsi_hba_tran_t), KM_SLEEP);
14036 	if (tran_clone == NULL) {
14037 		goto out;
14038 	}
14039 	bcopy((caddr_t)mpt->m_tran,
14040 	    (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
14041 	tgt_private = kmem_alloc(
14042 	    sizeof (mptsas_tgt_private_t), KM_SLEEP);
14043 	if (tgt_private == NULL) {
14044 		goto out;
14045 	}
14046 	tgt_private->t_lun = ap->a_lun;
14047 	tgt_private->t_private = ptgt;
14048 	tran_clone->tran_tgt_private = tgt_private;
14049 	ap->a_hba_tran = tran_clone;
14050 
14051 	pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
14052 	    data_bp, cdblen, sizeof (struct scsi_arq_status),
14053 	    0, PKT_CONSISTENT, NULL, NULL);
14054 	if (pktp == NULL) {
14055 		goto out;
14056 	}
14057 	bcopy(cdb, pktp->pkt_cdbp, cdblen);
14058 	pktp->pkt_flags = FLAG_NOPARITY;
14059 	if (scsi_poll(pktp) < 0) {
14060 		goto out;
14061 	}
14062 	if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
14063 		goto out;
14064 	}
14065 	if (resid != NULL) {
14066 		*resid = pktp->pkt_resid;
14067 	}
14068 
14069 	ret = DDI_SUCCESS;
14070 out:
14071 	if (pktp) {
14072 		scsi_destroy_pkt(pktp);
14073 	}
14074 	if (tran_clone) {
14075 		kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
14076 	}
14077 	if (tgt_private) {
14078 		kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
14079 	}
14080 	return (ret);
14081 }
14082 static int
14083 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
14084 {
14085 	char	*cp = NULL;
14086 	char	*ptr = NULL;
14087 	size_t	s = 0;
14088 	char	*wwid_str = NULL;
14089 	char	*lun_str = NULL;
14090 	long	lunnum;
14091 	long	phyid = -1;
14092 	int	rc = DDI_FAILURE;
14093 
14094 	ptr = name;
14095 	ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
14096 	ptr++;
14097 	if ((cp = strchr(ptr, ',')) == NULL) {
14098 		return (DDI_FAILURE);
14099 	}
14100 
14101 	wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14102 	s = (uintptr_t)cp - (uintptr_t)ptr;
14103 
14104 	bcopy(ptr, wwid_str, s);
14105 	wwid_str[s] = '\0';
14106 
14107 	ptr = ++cp;
14108 
14109 	if ((cp = strchr(ptr, '\0')) == NULL) {
14110 		goto out;
14111 	}
14112 	lun_str =  kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14113 	s = (uintptr_t)cp - (uintptr_t)ptr;
14114 
14115 	bcopy(ptr, lun_str, s);
14116 	lun_str[s] = '\0';
14117 
14118 	if (name[0] == 'p') {
14119 		rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
14120 	} else {
14121 		rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
14122 	}
14123 	if (rc != DDI_SUCCESS)
14124 		goto out;
14125 
14126 	if (phyid != -1) {
14127 		ASSERT(phyid < MPTSAS_MAX_PHYS);
14128 		*phy = (uint8_t)phyid;
14129 	}
14130 	rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
14131 	if (rc != 0)
14132 		goto out;
14133 
14134 	*lun = (int)lunnum;
14135 	rc = DDI_SUCCESS;
14136 out:
14137 	if (wwid_str)
14138 		kmem_free(wwid_str, SCSI_MAXNAMELEN);
14139 	if (lun_str)
14140 		kmem_free(lun_str, SCSI_MAXNAMELEN);
14141 
14142 	return (rc);
14143 }
14144 
14145 /*
14146  * mptsas_parse_smp_name() is to parse sas wwn string
14147  * which format is "wWWN"
14148  */
14149 static int
14150 mptsas_parse_smp_name(char *name, uint64_t *wwn)
14151 {
14152 	char	*ptr = name;
14153 
14154 	if (*ptr != 'w') {
14155 		return (DDI_FAILURE);
14156 	}
14157 
14158 	ptr++;
14159 	if (scsi_wwnstr_to_wwn(ptr, wwn)) {
14160 		return (DDI_FAILURE);
14161 	}
14162 	return (DDI_SUCCESS);
14163 }
14164 
14165 static int
14166 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
14167     ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
14168 {
14169 	int		ret = NDI_FAILURE;
14170 	int		circ = 0;
14171 	int		circ1 = 0;
14172 	mptsas_t	*mpt;
14173 	char		*ptr = NULL;
14174 	char		*devnm = NULL;
14175 	uint64_t	wwid = 0;
14176 	uint8_t		phy = 0xFF;
14177 	int		lun = 0;
14178 	uint_t		mflags = flag;
14179 	int		bconfig = TRUE;
14180 
14181 	if (scsi_hba_iport_unit_address(pdip) == 0) {
14182 		return (DDI_FAILURE);
14183 	}
14184 
14185 	mpt = DIP2MPT(pdip);
14186 	if (!mpt) {
14187 		return (DDI_FAILURE);
14188 	}
14189 	/*
14190 	 * Hold the nexus across the bus_config
14191 	 */
14192 	ndi_devi_enter(scsi_vhci_dip, &circ);
14193 	ndi_devi_enter(pdip, &circ1);
14194 	switch (op) {
14195 	case BUS_CONFIG_ONE:
14196 		/* parse wwid/target name out of name given */
14197 		if ((ptr = strchr((char *)arg, '@')) == NULL) {
14198 			ret = NDI_FAILURE;
14199 			break;
14200 		}
14201 		ptr++;
14202 		if (strncmp((char *)arg, "smp", 3) == 0) {
14203 			/*
14204 			 * This is a SMP target device
14205 			 */
14206 			ret = mptsas_parse_smp_name(ptr, &wwid);
14207 			if (ret != DDI_SUCCESS) {
14208 				ret = NDI_FAILURE;
14209 				break;
14210 			}
14211 			ret = mptsas_config_smp(pdip, wwid, childp);
14212 		} else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
14213 			/*
14214 			 * OBP could pass down a non-canonical form
14215 			 * bootpath without LUN part when LUN is 0.
14216 			 * So driver need adjust the string.
14217 			 */
14218 			if (strchr(ptr, ',') == NULL) {
14219 				devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14220 				(void) sprintf(devnm, "%s,0", (char *)arg);
14221 				ptr = strchr(devnm, '@');
14222 				ptr++;
14223 			}
14224 
14225 			/*
14226 			 * The device path is wWWID format and the device
14227 			 * is not SMP target device.
14228 			 */
14229 			ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
14230 			if (ret != DDI_SUCCESS) {
14231 				ret = NDI_FAILURE;
14232 				break;
14233 			}
14234 			*childp = NULL;
14235 			if (ptr[0] == 'w') {
14236 				ret = mptsas_config_one_addr(pdip, wwid,
14237 				    lun, childp);
14238 			} else if (ptr[0] == 'p') {
14239 				ret = mptsas_config_one_phy(pdip, phy, lun,
14240 				    childp);
14241 			}
14242 
14243 			/*
14244 			 * If this is CD/DVD device in OBP path, the
14245 			 * ndi_busop_bus_config can be skipped as config one
14246 			 * operation is done above.
14247 			 */
14248 			if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
14249 			    (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
14250 			    (strncmp((char *)arg, "disk", 4) == 0)) {
14251 				bconfig = FALSE;
14252 				ndi_hold_devi(*childp);
14253 			}
14254 		} else {
14255 			ret = NDI_FAILURE;
14256 			break;
14257 		}
14258 
14259 		/*
14260 		 * DDI group instructed us to use this flag.
14261 		 */
14262 		mflags |= NDI_MDI_FALLBACK;
14263 		break;
14264 	case BUS_CONFIG_DRIVER:
14265 	case BUS_CONFIG_ALL:
14266 		mptsas_config_all(pdip);
14267 		ret = NDI_SUCCESS;
14268 		break;
14269 	default:
14270 		ret = NDI_FAILURE;
14271 		break;
14272 	}
14273 
14274 	if ((ret == NDI_SUCCESS) && bconfig) {
14275 		ret = ndi_busop_bus_config(pdip, mflags, op,
14276 		    (devnm == NULL) ? arg : devnm, childp, 0);
14277 	}
14278 
14279 	ndi_devi_exit(pdip, circ1);
14280 	ndi_devi_exit(scsi_vhci_dip, circ);
14281 	if (devnm != NULL)
14282 		kmem_free(devnm, SCSI_MAXNAMELEN);
14283 	return (ret);
14284 }
14285 
14286 static int
14287 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
14288     mptsas_target_t *ptgt)
14289 {
14290 	int			rval = DDI_FAILURE;
14291 	struct scsi_inquiry	*sd_inq = NULL;
14292 	mptsas_t		*mpt = DIP2MPT(pdip);
14293 
14294 	sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14295 
14296 	rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
14297 	    SUN_INQSIZE, 0, (uchar_t)0);
14298 
14299 	if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14300 		rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
14301 	} else {
14302 		rval = DDI_FAILURE;
14303 	}
14304 
14305 	kmem_free(sd_inq, SUN_INQSIZE);
14306 	return (rval);
14307 }
14308 
14309 static int
14310 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
14311     dev_info_t **lundip)
14312 {
14313 	int		rval;
14314 	mptsas_t		*mpt = DIP2MPT(pdip);
14315 	int		phymask;
14316 	mptsas_target_t	*ptgt = NULL;
14317 
14318 	/*
14319 	 * Get the physical port associated to the iport
14320 	 */
14321 	phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14322 	    "phymask", 0);
14323 
14324 	ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
14325 	if (ptgt == NULL) {
14326 		/*
14327 		 * didn't match any device by searching
14328 		 */
14329 		return (DDI_FAILURE);
14330 	}
14331 	/*
14332 	 * If the LUN already exists and the status is online,
14333 	 * we just return the pointer to dev_info_t directly.
14334 	 * For the mdi_pathinfo node, we'll handle it in
14335 	 * mptsas_create_virt_lun()
14336 	 * TODO should be also in mptsas_handle_dr
14337 	 */
14338 
14339 	*lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
14340 	if (*lundip != NULL) {
14341 		/*
14342 		 * TODO Another senario is, we hotplug the same disk
14343 		 * on the same slot, the devhdl changed, is this
14344 		 * possible?
14345 		 * tgt_private->t_private != ptgt
14346 		 */
14347 		if (sasaddr != ptgt->m_addr.mta_wwn) {
14348 			/*
14349 			 * The device has changed although the devhdl is the
14350 			 * same (Enclosure mapping mode, change drive on the
14351 			 * same slot)
14352 			 */
14353 			return (DDI_FAILURE);
14354 		}
14355 		return (DDI_SUCCESS);
14356 	}
14357 
14358 	if (phymask == 0) {
14359 		/*
14360 		 * Configure IR volume
14361 		 */
14362 		rval =  mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
14363 		return (rval);
14364 	}
14365 	rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14366 
14367 	return (rval);
14368 }
14369 
14370 static int
14371 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
14372     dev_info_t **lundip)
14373 {
14374 	int		rval;
14375 	mptsas_t	*mpt = DIP2MPT(pdip);
14376 	mptsas_phymask_t phymask;
14377 	mptsas_target_t	*ptgt = NULL;
14378 
14379 	/*
14380 	 * Get the physical port associated to the iport
14381 	 */
14382 	phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14383 	    "phymask", 0);
14384 
14385 	ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
14386 	if (ptgt == NULL) {
14387 		/*
14388 		 * didn't match any device by searching
14389 		 */
14390 		return (DDI_FAILURE);
14391 	}
14392 
14393 	/*
14394 	 * If the LUN already exists and the status is online,
14395 	 * we just return the pointer to dev_info_t directly.
14396 	 * For the mdi_pathinfo node, we'll handle it in
14397 	 * mptsas_create_virt_lun().
14398 	 */
14399 
14400 	*lundip = mptsas_find_child_phy(pdip, phy);
14401 	if (*lundip != NULL) {
14402 		return (DDI_SUCCESS);
14403 	}
14404 
14405 	rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14406 
14407 	return (rval);
14408 }
14409 
14410 static int
14411 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
14412     uint8_t *lun_addr_type)
14413 {
14414 	uint32_t	lun_idx = 0;
14415 
14416 	ASSERT(lun_num != NULL);
14417 	ASSERT(lun_addr_type != NULL);
14418 
14419 	lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14420 	/* determine report luns addressing type */
14421 	switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
14422 		/*
14423 		 * Vendors in the field have been found to be concatenating
14424 		 * bus/target/lun to equal the complete lun value instead
14425 		 * of switching to flat space addressing
14426 		 */
14427 		/* 00b - peripheral device addressing method */
14428 	case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
14429 		/* FALLTHRU */
14430 		/* 10b - logical unit addressing method */
14431 	case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
14432 		/* FALLTHRU */
14433 		/* 01b - flat space addressing method */
14434 	case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
14435 		/* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
14436 		*lun_addr_type = (buf[lun_idx] &
14437 		    MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
14438 		*lun_num = (buf[lun_idx] & 0x3F) << 8;
14439 		*lun_num |= buf[lun_idx + 1];
14440 		return (DDI_SUCCESS);
14441 	default:
14442 		return (DDI_FAILURE);
14443 	}
14444 }
14445 
14446 static int
14447 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
14448 {
14449 	struct buf		*repluns_bp = NULL;
14450 	struct scsi_address	ap;
14451 	uchar_t			cdb[CDB_GROUP5];
14452 	int			ret = DDI_FAILURE;
14453 	int			retry = 0;
14454 	int			lun_list_len = 0;
14455 	uint16_t		lun_num = 0;
14456 	uint8_t			lun_addr_type = 0;
14457 	uint32_t		lun_cnt = 0;
14458 	uint32_t		lun_total = 0;
14459 	dev_info_t		*cdip = NULL;
14460 	uint16_t		*saved_repluns = NULL;
14461 	char			*buffer = NULL;
14462 	int			buf_len = 128;
14463 	mptsas_t		*mpt = DIP2MPT(pdip);
14464 	uint64_t		sas_wwn = 0;
14465 	uint8_t			phy = 0xFF;
14466 	uint32_t		dev_info = 0;
14467 
14468 	mutex_enter(&mpt->m_mutex);
14469 	sas_wwn = ptgt->m_addr.mta_wwn;
14470 	phy = ptgt->m_phynum;
14471 	dev_info = ptgt->m_deviceinfo;
14472 	mutex_exit(&mpt->m_mutex);
14473 
14474 	if (sas_wwn == 0) {
14475 		/*
14476 		 * It's a SATA without Device Name
14477 		 * So don't try multi-LUNs
14478 		 */
14479 		if (mptsas_find_child_phy(pdip, phy)) {
14480 			return (DDI_SUCCESS);
14481 		} else {
14482 			/*
14483 			 * need configure and create node
14484 			 */
14485 			return (DDI_FAILURE);
14486 		}
14487 	}
14488 
14489 	/*
14490 	 * WWN (SAS address or Device Name exist)
14491 	 */
14492 	if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14493 	    MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14494 		/*
14495 		 * SATA device with Device Name
14496 		 * So don't try multi-LUNs
14497 		 */
14498 		if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
14499 			return (DDI_SUCCESS);
14500 		} else {
14501 			return (DDI_FAILURE);
14502 		}
14503 	}
14504 
14505 	do {
14506 		ap.a_target = MPTSAS_INVALID_DEVHDL;
14507 		ap.a_lun = 0;
14508 		ap.a_hba_tran = mpt->m_tran;
14509 		repluns_bp = scsi_alloc_consistent_buf(&ap,
14510 		    (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
14511 		if (repluns_bp == NULL) {
14512 			retry++;
14513 			continue;
14514 		}
14515 		bzero(cdb, CDB_GROUP5);
14516 		cdb[0] = SCMD_REPORT_LUNS;
14517 		cdb[6] = (buf_len & 0xff000000) >> 24;
14518 		cdb[7] = (buf_len & 0x00ff0000) >> 16;
14519 		cdb[8] = (buf_len & 0x0000ff00) >> 8;
14520 		cdb[9] = (buf_len & 0x000000ff);
14521 
14522 		ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
14523 		    repluns_bp, NULL);
14524 		if (ret != DDI_SUCCESS) {
14525 			scsi_free_consistent_buf(repluns_bp);
14526 			retry++;
14527 			continue;
14528 		}
14529 		lun_list_len = BE_32(*(int *)((void *)(
14530 		    repluns_bp->b_un.b_addr)));
14531 		if (buf_len >= lun_list_len + 8) {
14532 			ret = DDI_SUCCESS;
14533 			break;
14534 		}
14535 		scsi_free_consistent_buf(repluns_bp);
14536 		buf_len = lun_list_len + 8;
14537 
14538 	} while (retry < 3);
14539 
14540 	if (ret != DDI_SUCCESS)
14541 		return (ret);
14542 	buffer = (char *)repluns_bp->b_un.b_addr;
14543 	/*
14544 	 * find out the number of luns returned by the SCSI ReportLun call
14545 	 * and allocate buffer space
14546 	 */
14547 	lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14548 	saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
14549 	if (saved_repluns == NULL) {
14550 		scsi_free_consistent_buf(repluns_bp);
14551 		return (DDI_FAILURE);
14552 	}
14553 	for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
14554 		if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
14555 		    &lun_num, &lun_addr_type) != DDI_SUCCESS) {
14556 			continue;
14557 		}
14558 		saved_repluns[lun_cnt] = lun_num;
14559 		if ((cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) !=
14560 		    NULL) {
14561 			ret = DDI_SUCCESS;
14562 		} else {
14563 			ret = mptsas_probe_lun(pdip, lun_num, &cdip,
14564 			    ptgt);
14565 		}
14566 		if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
14567 			(void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
14568 			    MPTSAS_DEV_GONE);
14569 		}
14570 	}
14571 	mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
14572 	kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
14573 	scsi_free_consistent_buf(repluns_bp);
14574 	return (DDI_SUCCESS);
14575 }
14576 
14577 static int
14578 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
14579 {
14580 	int			rval = DDI_FAILURE;
14581 	struct scsi_inquiry	*sd_inq = NULL;
14582 	mptsas_t		*mpt = DIP2MPT(pdip);
14583 	mptsas_target_t		*ptgt = NULL;
14584 
14585 	mutex_enter(&mpt->m_mutex);
14586 	ptgt = refhash_linear_search(mpt->m_targets,
14587 	    mptsas_target_eval_devhdl, &target);
14588 	mutex_exit(&mpt->m_mutex);
14589 	if (ptgt == NULL) {
14590 		mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
14591 		    "not found.", target);
14592 		return (rval);
14593 	}
14594 
14595 	sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14596 	rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
14597 	    SUN_INQSIZE, 0, (uchar_t)0);
14598 
14599 	if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14600 		rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
14601 		    0);
14602 	} else {
14603 		rval = DDI_FAILURE;
14604 	}
14605 
14606 	kmem_free(sd_inq, SUN_INQSIZE);
14607 	return (rval);
14608 }
14609 
14610 /*
14611  * configure all RAID volumes for virtual iport
14612  */
14613 static void
14614 mptsas_config_all_viport(dev_info_t *pdip)
14615 {
14616 	mptsas_t	*mpt = DIP2MPT(pdip);
14617 	int		config, vol;
14618 	int		target;
14619 	dev_info_t	*lundip = NULL;
14620 
14621 	/*
14622 	 * Get latest RAID info and search for any Volume DevHandles.  If any
14623 	 * are found, configure the volume.
14624 	 */
14625 	mutex_enter(&mpt->m_mutex);
14626 	for (config = 0; config < mpt->m_num_raid_configs; config++) {
14627 		for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
14628 			if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid
14629 			    == 1) {
14630 				target = mpt->m_raidconfig[config].
14631 				    m_raidvol[vol].m_raidhandle;
14632 				mutex_exit(&mpt->m_mutex);
14633 				(void) mptsas_config_raid(pdip, target,
14634 				    &lundip);
14635 				mutex_enter(&mpt->m_mutex);
14636 			}
14637 		}
14638 	}
14639 	mutex_exit(&mpt->m_mutex);
14640 }
14641 
14642 static void
14643 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
14644     int lun_cnt, mptsas_target_t *ptgt)
14645 {
14646 	dev_info_t	*child = NULL, *savechild = NULL;
14647 	mdi_pathinfo_t	*pip = NULL, *savepip = NULL;
14648 	uint64_t	sas_wwn, wwid;
14649 	uint8_t		phy;
14650 	int		lun;
14651 	int		i;
14652 	int		find;
14653 	char		*addr;
14654 	char		*nodename;
14655 	mptsas_t	*mpt = DIP2MPT(pdip);
14656 
14657 	mutex_enter(&mpt->m_mutex);
14658 	wwid = ptgt->m_addr.mta_wwn;
14659 	mutex_exit(&mpt->m_mutex);
14660 
14661 	child = ddi_get_child(pdip);
14662 	while (child) {
14663 		find = 0;
14664 		savechild = child;
14665 		child = ddi_get_next_sibling(child);
14666 
14667 		nodename = ddi_node_name(savechild);
14668 		if (strcmp(nodename, "smp") == 0) {
14669 			continue;
14670 		}
14671 
14672 		addr = ddi_get_name_addr(savechild);
14673 		if (addr == NULL) {
14674 			continue;
14675 		}
14676 
14677 		if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
14678 		    DDI_SUCCESS) {
14679 			continue;
14680 		}
14681 
14682 		if (wwid == sas_wwn) {
14683 			for (i = 0; i < lun_cnt; i++) {
14684 				if (repluns[i] == lun) {
14685 					find = 1;
14686 					break;
14687 				}
14688 			}
14689 		} else {
14690 			continue;
14691 		}
14692 		if (find == 0) {
14693 			/*
14694 			 * The lun has not been there already
14695 			 */
14696 			(void) mptsas_offline_lun(pdip, savechild, NULL,
14697 			    NDI_DEVI_REMOVE);
14698 		}
14699 	}
14700 
14701 	pip = mdi_get_next_client_path(pdip, NULL);
14702 	while (pip) {
14703 		find = 0;
14704 		savepip = pip;
14705 		addr = MDI_PI(pip)->pi_addr;
14706 
14707 		pip = mdi_get_next_client_path(pdip, pip);
14708 
14709 		if (addr == NULL) {
14710 			continue;
14711 		}
14712 
14713 		if (mptsas_parse_address(addr, &sas_wwn, &phy,
14714 		    &lun) != DDI_SUCCESS) {
14715 			continue;
14716 		}
14717 
14718 		if (sas_wwn == wwid) {
14719 			for (i = 0; i < lun_cnt; i++) {
14720 				if (repluns[i] == lun) {
14721 					find = 1;
14722 					break;
14723 				}
14724 			}
14725 		} else {
14726 			continue;
14727 		}
14728 
14729 		if (find == 0) {
14730 			/*
14731 			 * The lun has not been there already
14732 			 */
14733 			(void) mptsas_offline_lun(pdip, NULL, savepip,
14734 			    NDI_DEVI_REMOVE);
14735 		}
14736 	}
14737 }
14738 
14739 /*
14740  * If this enclosure doesn't exist in the enclosure list, add it. If it does,
14741  * update it.
14742  */
14743 static void
14744 mptsas_enclosure_update(mptsas_t *mpt, mptsas_enclosure_t *mep)
14745 {
14746 	mptsas_enclosure_t *m;
14747 
14748 	ASSERT(MUTEX_HELD(&mpt->m_mutex));
14749 	m = mptsas_enc_lookup(mpt, mep->me_enchdl);
14750 	if (m != NULL) {
14751 		uint8_t *ledp;
14752 		m->me_flags = mep->me_flags;
14753 
14754 
14755 		/*
14756 		 * If the number of slots and the first slot entry in the
14757 		 * enclosure has not changed, then we don't need to do anything
14758 		 * here. Otherwise, we need to allocate a new array for the LED
14759 		 * status of the slot.
14760 		 */
14761 		if (m->me_fslot == mep->me_fslot &&
14762 		    m->me_nslots == mep->me_nslots)
14763 			return;
14764 
14765 		/*
14766 		 * If the number of slots or the first slot has changed, it's
14767 		 * not clear that we're really in a place that we can continue
14768 		 * to honor the existing flags.
14769 		 */
14770 		if (mep->me_nslots > 0) {
14771 			ledp = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots,
14772 			    KM_SLEEP);
14773 		} else {
14774 			ledp = NULL;
14775 		}
14776 
14777 		if (m->me_slotleds != NULL) {
14778 			kmem_free(m->me_slotleds, sizeof (uint8_t) *
14779 			    m->me_nslots);
14780 		}
14781 		m->me_slotleds = ledp;
14782 		m->me_fslot = mep->me_fslot;
14783 		m->me_nslots = mep->me_nslots;
14784 		return;
14785 	}
14786 
14787 	m = kmem_zalloc(sizeof (*m), KM_SLEEP);
14788 	m->me_enchdl = mep->me_enchdl;
14789 	m->me_flags = mep->me_flags;
14790 	m->me_nslots = mep->me_nslots;
14791 	m->me_fslot = mep->me_fslot;
14792 	if (m->me_nslots > 0) {
14793 		m->me_slotleds = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots,
14794 		    KM_SLEEP);
14795 		/*
14796 		 * It may make sense to optionally flush all of the slots and/or
14797 		 * read the slot status flag here to synchronize between
14798 		 * ourselves and the card. So far, that hasn't been needed
14799 		 * annecdotally when enumerating something new. If we do, we
14800 		 * should kick that off in a taskq potentially.
14801 		 */
14802 	}
14803 	list_insert_tail(&mpt->m_enclosures, m);
14804 }
14805 
14806 static void
14807 mptsas_update_hashtab(struct mptsas *mpt)
14808 {
14809 	uint32_t	page_address;
14810 	int		rval = 0;
14811 	uint16_t	dev_handle;
14812 	mptsas_target_t	*ptgt = NULL;
14813 	mptsas_smp_t	smp_node;
14814 
14815 	/*
14816 	 * Get latest RAID info.
14817 	 */
14818 	(void) mptsas_get_raid_info(mpt);
14819 
14820 	dev_handle = mpt->m_smp_devhdl;
14821 	while (mpt->m_done_traverse_smp == 0) {
14822 		page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
14823 		    MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
14824 		if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
14825 		    != DDI_SUCCESS) {
14826 			break;
14827 		}
14828 		mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
14829 		(void) mptsas_smp_alloc(mpt, &smp_node);
14830 	}
14831 
14832 	/*
14833 	 * Loop over enclosures so we can understand what's there.
14834 	 */
14835 	dev_handle = MPTSAS_INVALID_DEVHDL;
14836 	while (mpt->m_done_traverse_enc == 0) {
14837 		mptsas_enclosure_t me;
14838 
14839 		page_address = (MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE &
14840 		    MPI2_SAS_ENCLOS_PGAD_FORM_MASK) | (uint32_t)dev_handle;
14841 
14842 		if (mptsas_get_enclosure_page0(mpt, page_address, &me) !=
14843 		    DDI_SUCCESS) {
14844 			break;
14845 		}
14846 		dev_handle = me.me_enchdl;
14847 		mptsas_enclosure_update(mpt, &me);
14848 	}
14849 
14850 	/*
14851 	 * Config target devices
14852 	 */
14853 	dev_handle = mpt->m_dev_handle;
14854 
14855 	/*
14856 	 * Loop to get sas device page 0 by GetNextHandle till the
14857 	 * the last handle. If the sas device is a SATA/SSP target,
14858 	 * we try to config it.
14859 	 */
14860 	while (mpt->m_done_traverse_dev == 0) {
14861 		ptgt = NULL;
14862 		page_address =
14863 		    (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
14864 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14865 		    (uint32_t)dev_handle;
14866 		rval = mptsas_get_target_device_info(mpt, page_address,
14867 		    &dev_handle, &ptgt);
14868 		if ((rval == DEV_INFO_FAIL_PAGE0) ||
14869 		    (rval == DEV_INFO_FAIL_ALLOC) ||
14870 		    (rval == DEV_INFO_FAIL_GUID)) {
14871 			break;
14872 		}
14873 
14874 		mpt->m_dev_handle = dev_handle;
14875 	}
14876 
14877 }
14878 
14879 void
14880 mptsas_update_driver_data(struct mptsas *mpt)
14881 {
14882 	mptsas_target_t *tp;
14883 	mptsas_smp_t *sp;
14884 
14885 	ASSERT(MUTEX_HELD(&mpt->m_mutex));
14886 
14887 	/*
14888 	 * TODO after hard reset, update the driver data structures
14889 	 * 1. update port/phymask mapping table mpt->m_phy_info
14890 	 * 2. invalid all the entries in hash table
14891 	 *    m_devhdl = 0xffff and m_deviceinfo = 0
14892 	 * 3. call sas_device_page/expander_page to update hash table
14893 	 */
14894 	mptsas_update_phymask(mpt);
14895 
14896 	/*
14897 	 * Remove all the devhdls for existing entries but leave their
14898 	 * addresses alone.  In update_hashtab() below, we'll find all
14899 	 * targets that are still present and reassociate them with
14900 	 * their potentially new devhdls.  Leaving the targets around in
14901 	 * this fashion allows them to be used on the tx waitq even
14902 	 * while IOC reset is occurring.
14903 	 */
14904 	for (tp = refhash_first(mpt->m_targets); tp != NULL;
14905 	    tp = refhash_next(mpt->m_targets, tp)) {
14906 		tp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14907 		tp->m_deviceinfo = 0;
14908 		tp->m_dr_flag = MPTSAS_DR_INACTIVE;
14909 	}
14910 	for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
14911 	    sp = refhash_next(mpt->m_smp_targets, sp)) {
14912 		sp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14913 		sp->m_deviceinfo = 0;
14914 	}
14915 	mpt->m_done_traverse_dev = 0;
14916 	mpt->m_done_traverse_smp = 0;
14917 	mpt->m_done_traverse_enc = 0;
14918 	mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
14919 	mptsas_update_hashtab(mpt);
14920 }
14921 
14922 static void
14923 mptsas_config_all(dev_info_t *pdip)
14924 {
14925 	dev_info_t	*smpdip = NULL;
14926 	mptsas_t	*mpt = DIP2MPT(pdip);
14927 	int		phymask = 0;
14928 	mptsas_phymask_t phy_mask;
14929 	mptsas_target_t	*ptgt = NULL;
14930 	mptsas_smp_t	*psmp;
14931 
14932 	/*
14933 	 * Get the phymask associated to the iport
14934 	 */
14935 	phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14936 	    "phymask", 0);
14937 
14938 	/*
14939 	 * Enumerate RAID volumes here (phymask == 0).
14940 	 */
14941 	if (phymask == 0) {
14942 		mptsas_config_all_viport(pdip);
14943 		return;
14944 	}
14945 
14946 	mutex_enter(&mpt->m_mutex);
14947 
14948 	if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp ||
14949 	    !mpt->m_done_traverse_enc) {
14950 		mptsas_update_hashtab(mpt);
14951 	}
14952 
14953 	for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL;
14954 	    psmp = refhash_next(mpt->m_smp_targets, psmp)) {
14955 		phy_mask = psmp->m_addr.mta_phymask;
14956 		if (phy_mask == phymask) {
14957 			smpdip = NULL;
14958 			mutex_exit(&mpt->m_mutex);
14959 			(void) mptsas_online_smp(pdip, psmp, &smpdip);
14960 			mutex_enter(&mpt->m_mutex);
14961 		}
14962 	}
14963 
14964 	for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
14965 	    ptgt = refhash_next(mpt->m_targets, ptgt)) {
14966 		phy_mask = ptgt->m_addr.mta_phymask;
14967 		if (phy_mask == phymask) {
14968 			mutex_exit(&mpt->m_mutex);
14969 			(void) mptsas_config_target(pdip, ptgt);
14970 			mutex_enter(&mpt->m_mutex);
14971 		}
14972 	}
14973 	mutex_exit(&mpt->m_mutex);
14974 }
14975 
14976 static int
14977 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
14978 {
14979 	int		rval = DDI_FAILURE;
14980 	dev_info_t	*tdip;
14981 
14982 	rval = mptsas_config_luns(pdip, ptgt);
14983 	if (rval != DDI_SUCCESS) {
14984 		/*
14985 		 * The return value means the SCMD_REPORT_LUNS
14986 		 * did not execute successfully. The target maybe
14987 		 * doesn't support such command.
14988 		 */
14989 		rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
14990 	}
14991 	return (rval);
14992 }
14993 
14994 /*
14995  * Return fail if not all the childs/paths are freed.
14996  * if there is any path under the HBA, the return value will be always fail
14997  * because we didn't call mdi_pi_free for path
14998  */
14999 static int
15000 mptsas_offline_target(dev_info_t *pdip, char *name)
15001 {
15002 	dev_info_t		*child = NULL, *prechild = NULL;
15003 	mdi_pathinfo_t		*pip = NULL, *savepip = NULL;
15004 	int			tmp_rval, rval = DDI_SUCCESS;
15005 	char			*addr, *cp;
15006 	size_t			s;
15007 	mptsas_t		*mpt = DIP2MPT(pdip);
15008 
15009 	child = ddi_get_child(pdip);
15010 	while (child) {
15011 		addr = ddi_get_name_addr(child);
15012 		prechild = child;
15013 		child = ddi_get_next_sibling(child);
15014 
15015 		if (addr == NULL) {
15016 			continue;
15017 		}
15018 		if ((cp = strchr(addr, ',')) == NULL) {
15019 			continue;
15020 		}
15021 
15022 		s = (uintptr_t)cp - (uintptr_t)addr;
15023 
15024 		if (strncmp(addr, name, s) != 0) {
15025 			continue;
15026 		}
15027 
15028 		tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
15029 		    NDI_DEVI_REMOVE);
15030 		if (tmp_rval != DDI_SUCCESS) {
15031 			rval = DDI_FAILURE;
15032 			if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15033 			    prechild, MPTSAS_DEV_GONE) !=
15034 			    DDI_PROP_SUCCESS) {
15035 				mptsas_log(mpt, CE_WARN, "mptsas driver "
15036 				    "unable to create property for "
15037 				    "SAS %s (MPTSAS_DEV_GONE)", addr);
15038 			}
15039 		}
15040 	}
15041 
15042 	pip = mdi_get_next_client_path(pdip, NULL);
15043 	while (pip) {
15044 		addr = MDI_PI(pip)->pi_addr;
15045 		savepip = pip;
15046 		pip = mdi_get_next_client_path(pdip, pip);
15047 		if (addr == NULL) {
15048 			continue;
15049 		}
15050 
15051 		if ((cp = strchr(addr, ',')) == NULL) {
15052 			continue;
15053 		}
15054 
15055 		s = (uintptr_t)cp - (uintptr_t)addr;
15056 
15057 		if (strncmp(addr, name, s) != 0) {
15058 			continue;
15059 		}
15060 
15061 		(void) mptsas_offline_lun(pdip, NULL, savepip,
15062 		    NDI_DEVI_REMOVE);
15063 		/*
15064 		 * driver will not invoke mdi_pi_free, so path will not
15065 		 * be freed forever, return DDI_FAILURE.
15066 		 */
15067 		rval = DDI_FAILURE;
15068 	}
15069 	return (rval);
15070 }
15071 
15072 static int
15073 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
15074     mdi_pathinfo_t *rpip, uint_t flags)
15075 {
15076 	int		rval = DDI_FAILURE;
15077 	char		*devname;
15078 	dev_info_t	*cdip, *parent;
15079 
15080 	if (rpip != NULL) {
15081 		parent = scsi_vhci_dip;
15082 		cdip = mdi_pi_get_client(rpip);
15083 	} else if (rdip != NULL) {
15084 		parent = pdip;
15085 		cdip = rdip;
15086 	} else {
15087 		return (DDI_FAILURE);
15088 	}
15089 
15090 	/*
15091 	 * Make sure node is attached otherwise
15092 	 * it won't have related cache nodes to
15093 	 * clean up.  i_ddi_devi_attached is
15094 	 * similiar to i_ddi_node_state(cdip) >=
15095 	 * DS_ATTACHED.
15096 	 */
15097 	if (i_ddi_devi_attached(cdip)) {
15098 
15099 		/* Get full devname */
15100 		devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
15101 		(void) ddi_deviname(cdip, devname);
15102 		/* Clean cache */
15103 		(void) devfs_clean(parent, devname + 1,
15104 		    DV_CLEAN_FORCE);
15105 		kmem_free(devname, MAXNAMELEN + 1);
15106 	}
15107 	if (rpip != NULL) {
15108 		if (MDI_PI_IS_OFFLINE(rpip)) {
15109 			rval = DDI_SUCCESS;
15110 		} else {
15111 			rval = mdi_pi_offline(rpip, 0);
15112 		}
15113 	} else {
15114 		rval = ndi_devi_offline(cdip, flags);
15115 	}
15116 
15117 	return (rval);
15118 }
15119 
15120 static dev_info_t *
15121 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
15122 {
15123 	dev_info_t	*child = NULL;
15124 	char		*smp_wwn = NULL;
15125 
15126 	child = ddi_get_child(parent);
15127 	while (child) {
15128 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
15129 		    DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
15130 		    != DDI_SUCCESS) {
15131 			child = ddi_get_next_sibling(child);
15132 			continue;
15133 		}
15134 
15135 		if (strcmp(smp_wwn, str_wwn) == 0) {
15136 			ddi_prop_free(smp_wwn);
15137 			break;
15138 		}
15139 		child = ddi_get_next_sibling(child);
15140 		ddi_prop_free(smp_wwn);
15141 	}
15142 	return (child);
15143 }
15144 
15145 static int
15146 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
15147 {
15148 	int		rval = DDI_FAILURE;
15149 	char		*devname;
15150 	char		wwn_str[MPTSAS_WWN_STRLEN];
15151 	dev_info_t	*cdip;
15152 
15153 	(void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
15154 
15155 	cdip = mptsas_find_smp_child(pdip, wwn_str);
15156 
15157 	if (cdip == NULL)
15158 		return (DDI_SUCCESS);
15159 
15160 	/*
15161 	 * Make sure node is attached otherwise
15162 	 * it won't have related cache nodes to
15163 	 * clean up.  i_ddi_devi_attached is
15164 	 * similiar to i_ddi_node_state(cdip) >=
15165 	 * DS_ATTACHED.
15166 	 */
15167 	if (i_ddi_devi_attached(cdip)) {
15168 
15169 		/* Get full devname */
15170 		devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
15171 		(void) ddi_deviname(cdip, devname);
15172 		/* Clean cache */
15173 		(void) devfs_clean(pdip, devname + 1,
15174 		    DV_CLEAN_FORCE);
15175 		kmem_free(devname, MAXNAMELEN + 1);
15176 	}
15177 
15178 	rval = ndi_devi_offline(cdip, flags);
15179 
15180 	return (rval);
15181 }
15182 
15183 static dev_info_t *
15184 mptsas_find_child(dev_info_t *pdip, char *name)
15185 {
15186 	dev_info_t	*child = NULL;
15187 	char		*rname = NULL;
15188 	int		rval = DDI_FAILURE;
15189 
15190 	rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15191 
15192 	child = ddi_get_child(pdip);
15193 	while (child) {
15194 		rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
15195 		if (rval != DDI_SUCCESS) {
15196 			child = ddi_get_next_sibling(child);
15197 			bzero(rname, SCSI_MAXNAMELEN);
15198 			continue;
15199 		}
15200 
15201 		if (strcmp(rname, name) == 0) {
15202 			break;
15203 		}
15204 		child = ddi_get_next_sibling(child);
15205 		bzero(rname, SCSI_MAXNAMELEN);
15206 	}
15207 
15208 	kmem_free(rname, SCSI_MAXNAMELEN);
15209 
15210 	return (child);
15211 }
15212 
15213 
15214 static dev_info_t *
15215 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
15216 {
15217 	dev_info_t	*child = NULL;
15218 	char		*name = NULL;
15219 	char		*addr = NULL;
15220 
15221 	name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15222 	addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15223 	(void) sprintf(name, "%016"PRIx64, sasaddr);
15224 	(void) sprintf(addr, "w%s,%x", name, lun);
15225 	child = mptsas_find_child(pdip, addr);
15226 	kmem_free(name, SCSI_MAXNAMELEN);
15227 	kmem_free(addr, SCSI_MAXNAMELEN);
15228 	return (child);
15229 }
15230 
15231 static dev_info_t *
15232 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
15233 {
15234 	dev_info_t	*child;
15235 	char		*addr;
15236 
15237 	addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15238 	(void) sprintf(addr, "p%x,0", phy);
15239 	child = mptsas_find_child(pdip, addr);
15240 	kmem_free(addr, SCSI_MAXNAMELEN);
15241 	return (child);
15242 }
15243 
15244 static mdi_pathinfo_t *
15245 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
15246 {
15247 	mdi_pathinfo_t	*path;
15248 	char		*addr = NULL;
15249 
15250 	addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15251 	(void) sprintf(addr, "p%x,0", phy);
15252 	path = mdi_pi_find(pdip, NULL, addr);
15253 	kmem_free(addr, SCSI_MAXNAMELEN);
15254 	return (path);
15255 }
15256 
15257 static mdi_pathinfo_t *
15258 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
15259 {
15260 	mdi_pathinfo_t	*path;
15261 	char		*name = NULL;
15262 	char		*addr = NULL;
15263 
15264 	name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15265 	addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15266 	(void) sprintf(name, "%016"PRIx64, sasaddr);
15267 	(void) sprintf(addr, "w%s,%x", name, lun);
15268 	path = mdi_pi_find(parent, NULL, addr);
15269 	kmem_free(name, SCSI_MAXNAMELEN);
15270 	kmem_free(addr, SCSI_MAXNAMELEN);
15271 
15272 	return (path);
15273 }
15274 
15275 static int
15276 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
15277     dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
15278 {
15279 	int			i = 0;
15280 	uchar_t			*inq83 = NULL;
15281 	int			inq83_len1 = 0xFF;
15282 	int			inq83_len = 0;
15283 	int			rval = DDI_FAILURE;
15284 	ddi_devid_t		devid;
15285 	char			*guid = NULL;
15286 	int			target = ptgt->m_devhdl;
15287 	mdi_pathinfo_t		*pip = NULL;
15288 	mptsas_t		*mpt = DIP2MPT(pdip);
15289 
15290 	/*
15291 	 * For DVD/CD ROM and tape devices and optical
15292 	 * devices, we won't try to enumerate them under
15293 	 * scsi_vhci, so no need to try page83
15294 	 */
15295 	if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
15296 	    sd_inq->inq_dtype == DTYPE_OPTICAL ||
15297 	    sd_inq->inq_dtype == DTYPE_ESI))
15298 		goto create_lun;
15299 
15300 	/*
15301 	 * The LCA returns good SCSI status, but corrupt page 83 data the first
15302 	 * time it is queried. The solution is to keep trying to request page83
15303 	 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
15304 	 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
15305 	 * give up to get VPD page at this stage and fail the enumeration.
15306 	 */
15307 
15308 	inq83	= kmem_zalloc(inq83_len1, KM_SLEEP);
15309 
15310 	for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
15311 		rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
15312 		    inq83_len1, &inq83_len, 1);
15313 		if (rval != 0) {
15314 			mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
15315 			    "0x83 for target:%x, lun:%x failed!", target, lun);
15316 			if (mptsas_physical_bind_failed_page_83 != B_FALSE)
15317 				goto create_lun;
15318 			goto out;
15319 		}
15320 		/*
15321 		 * create DEVID from inquiry data
15322 		 */
15323 		if ((rval = ddi_devid_scsi_encode(
15324 		    DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
15325 		    sizeof (struct scsi_inquiry), NULL, 0, inq83,
15326 		    (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
15327 			/*
15328 			 * extract GUID from DEVID
15329 			 */
15330 			guid = ddi_devid_to_guid(devid);
15331 
15332 			/*
15333 			 * Do not enable MPXIO if the strlen(guid) is greater
15334 			 * than MPTSAS_MAX_GUID_LEN, this constrain would be
15335 			 * handled by framework later.
15336 			 */
15337 			if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
15338 				ddi_devid_free_guid(guid);
15339 				guid = NULL;
15340 				if (mpt->m_mpxio_enable == TRUE) {
15341 					mptsas_log(mpt, CE_NOTE, "!Target:%x, "
15342 					    "lun:%x doesn't have a valid GUID, "
15343 					    "multipathing for this drive is "
15344 					    "not enabled", target, lun);
15345 				}
15346 			}
15347 
15348 			/*
15349 			 * devid no longer needed
15350 			 */
15351 			ddi_devid_free(devid);
15352 			break;
15353 		} else if (rval == DDI_NOT_WELL_FORMED) {
15354 			/*
15355 			 * return value of ddi_devid_scsi_encode equal to
15356 			 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
15357 			 * to retry inquiry page 0x83 and get GUID.
15358 			 */
15359 			NDBG20(("Not well formed devid, retry..."));
15360 			delay(1 * drv_usectohz(1000000));
15361 			continue;
15362 		} else {
15363 			mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
15364 			    "path target:%x, lun:%x", target, lun);
15365 			rval = DDI_FAILURE;
15366 			goto create_lun;
15367 		}
15368 	}
15369 
15370 	if (i == mptsas_inq83_retry_timeout) {
15371 		mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
15372 		    "for path target:%x, lun:%x", target, lun);
15373 	}
15374 
15375 	rval = DDI_FAILURE;
15376 
15377 create_lun:
15378 	if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
15379 		rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
15380 		    ptgt, lun);
15381 	}
15382 	if (rval != DDI_SUCCESS) {
15383 		rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
15384 		    ptgt, lun);
15385 
15386 	}
15387 out:
15388 	if (guid != NULL) {
15389 		/*
15390 		 * guid no longer needed
15391 		 */
15392 		ddi_devid_free_guid(guid);
15393 	}
15394 	if (inq83 != NULL)
15395 		kmem_free(inq83, inq83_len1);
15396 	return (rval);
15397 }
15398 
15399 static int
15400 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
15401     dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
15402 {
15403 	int			target;
15404 	char			*nodename = NULL;
15405 	char			**compatible = NULL;
15406 	int			ncompatible	= 0;
15407 	int			mdi_rtn = MDI_FAILURE;
15408 	int			rval = DDI_FAILURE;
15409 	char			*old_guid = NULL;
15410 	mptsas_t		*mpt = DIP2MPT(pdip);
15411 	char			*lun_addr = NULL;
15412 	char			*wwn_str = NULL;
15413 	char			*attached_wwn_str = NULL;
15414 	char			*component = NULL;
15415 	uint8_t			phy = 0xFF;
15416 	uint64_t		sas_wwn;
15417 	int64_t			lun64 = 0;
15418 	uint32_t		devinfo;
15419 	uint16_t		dev_hdl;
15420 	uint16_t		pdev_hdl;
15421 	uint64_t		dev_sas_wwn;
15422 	uint64_t		pdev_sas_wwn;
15423 	uint32_t		pdev_info;
15424 	uint8_t			physport;
15425 	uint8_t			phy_id;
15426 	uint32_t		page_address;
15427 	uint16_t		bay_num, enclosure, io_flags;
15428 	char			pdev_wwn_str[MPTSAS_WWN_STRLEN];
15429 	uint32_t		dev_info;
15430 
15431 	mutex_enter(&mpt->m_mutex);
15432 	target = ptgt->m_devhdl;
15433 	sas_wwn = ptgt->m_addr.mta_wwn;
15434 	devinfo = ptgt->m_deviceinfo;
15435 	phy = ptgt->m_phynum;
15436 	mutex_exit(&mpt->m_mutex);
15437 
15438 	if (sas_wwn) {
15439 		*pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
15440 	} else {
15441 		*pip = mptsas_find_path_phy(pdip, phy);
15442 	}
15443 
15444 	if (*pip != NULL) {
15445 		*lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15446 		ASSERT(*lun_dip != NULL);
15447 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
15448 		    (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
15449 		    MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
15450 			if (strncmp(guid, old_guid, strlen(guid)) == 0) {
15451 				/*
15452 				 * Same path back online again.
15453 				 */
15454 				(void) ddi_prop_free(old_guid);
15455 				if ((!MDI_PI_IS_ONLINE(*pip)) &&
15456 				    (!MDI_PI_IS_STANDBY(*pip)) &&
15457 				    (ptgt->m_tgt_unconfigured == 0)) {
15458 					rval = mdi_pi_online(*pip, 0);
15459 				} else {
15460 					rval = DDI_SUCCESS;
15461 				}
15462 				if (rval != DDI_SUCCESS) {
15463 					mptsas_log(mpt, CE_WARN, "path:target: "
15464 					    "%x, lun:%x online failed!", target,
15465 					    lun);
15466 					*pip = NULL;
15467 					*lun_dip = NULL;
15468 				}
15469 				return (rval);
15470 			} else {
15471 				/*
15472 				 * The GUID of the LUN has changed which maybe
15473 				 * because customer mapped another volume to the
15474 				 * same LUN.
15475 				 */
15476 				mptsas_log(mpt, CE_WARN, "The GUID of the "
15477 				    "target:%x, lun:%x was changed, maybe "
15478 				    "because someone mapped another volume "
15479 				    "to the same LUN", target, lun);
15480 				(void) ddi_prop_free(old_guid);
15481 				if (!MDI_PI_IS_OFFLINE(*pip)) {
15482 					rval = mdi_pi_offline(*pip, 0);
15483 					if (rval != MDI_SUCCESS) {
15484 						mptsas_log(mpt, CE_WARN, "path:"
15485 						    "target:%x, lun:%x offline "
15486 						    "failed!", target, lun);
15487 						*pip = NULL;
15488 						*lun_dip = NULL;
15489 						return (DDI_FAILURE);
15490 					}
15491 				}
15492 				if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
15493 					mptsas_log(mpt, CE_WARN, "path:target:"
15494 					    "%x, lun:%x free failed!", target,
15495 					    lun);
15496 					*pip = NULL;
15497 					*lun_dip = NULL;
15498 					return (DDI_FAILURE);
15499 				}
15500 			}
15501 		} else {
15502 			mptsas_log(mpt, CE_WARN, "Can't get client-guid "
15503 			    "property for path:target:%x, lun:%x", target, lun);
15504 			*pip = NULL;
15505 			*lun_dip = NULL;
15506 			return (DDI_FAILURE);
15507 		}
15508 	}
15509 	scsi_hba_nodename_compatible_get(inq, NULL,
15510 	    inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
15511 
15512 	/*
15513 	 * if nodename can't be determined then print a message and skip it
15514 	 */
15515 	if (nodename == NULL) {
15516 		mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
15517 		    "driver for target%d lun %d dtype:0x%02x", target, lun,
15518 		    inq->inq_dtype);
15519 		return (DDI_FAILURE);
15520 	}
15521 
15522 	wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15523 	/* The property is needed by MPAPI */
15524 	(void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15525 
15526 	lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15527 	if (guid) {
15528 		(void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
15529 		(void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15530 	} else {
15531 		(void) sprintf(lun_addr, "p%x,%x", phy, lun);
15532 		(void) sprintf(wwn_str, "p%x", phy);
15533 	}
15534 
15535 	mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
15536 	    guid, lun_addr, compatible, ncompatible,
15537 	    0, pip);
15538 	if (mdi_rtn == MDI_SUCCESS) {
15539 
15540 		if (mdi_prop_update_string(*pip, MDI_GUID,
15541 		    guid) != DDI_SUCCESS) {
15542 			mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15543 			    "create prop for target %d lun %d (MDI_GUID)",
15544 			    target, lun);
15545 			mdi_rtn = MDI_FAILURE;
15546 			goto virt_create_done;
15547 		}
15548 
15549 		if (mdi_prop_update_int(*pip, LUN_PROP,
15550 		    lun) != DDI_SUCCESS) {
15551 			mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15552 			    "create prop for target %d lun %d (LUN_PROP)",
15553 			    target, lun);
15554 			mdi_rtn = MDI_FAILURE;
15555 			goto virt_create_done;
15556 		}
15557 		lun64 = (int64_t)lun;
15558 		if (mdi_prop_update_int64(*pip, LUN64_PROP,
15559 		    lun64) != DDI_SUCCESS) {
15560 			mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15561 			    "create prop for target %d (LUN64_PROP)",
15562 			    target);
15563 			mdi_rtn = MDI_FAILURE;
15564 			goto virt_create_done;
15565 		}
15566 		if (mdi_prop_update_string_array(*pip, "compatible",
15567 		    compatible, ncompatible) !=
15568 		    DDI_PROP_SUCCESS) {
15569 			mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15570 			    "create prop for target %d lun %d (COMPATIBLE)",
15571 			    target, lun);
15572 			mdi_rtn = MDI_FAILURE;
15573 			goto virt_create_done;
15574 		}
15575 		if (sas_wwn && (mdi_prop_update_string(*pip,
15576 		    SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
15577 			mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15578 			    "create prop for target %d lun %d "
15579 			    "(target-port)", target, lun);
15580 			mdi_rtn = MDI_FAILURE;
15581 			goto virt_create_done;
15582 		} else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
15583 		    "sata-phy", phy) != DDI_PROP_SUCCESS)) {
15584 			/*
15585 			 * Direct attached SATA device without DeviceName
15586 			 */
15587 			mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15588 			    "create prop for SAS target %d lun %d "
15589 			    "(sata-phy)", target, lun);
15590 			mdi_rtn = MDI_FAILURE;
15591 			goto virt_create_done;
15592 		}
15593 		mutex_enter(&mpt->m_mutex);
15594 
15595 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15596 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15597 		    (uint32_t)ptgt->m_devhdl;
15598 		rval = mptsas_get_sas_device_page0(mpt, page_address,
15599 		    &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
15600 		    &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15601 		if (rval != DDI_SUCCESS) {
15602 			mutex_exit(&mpt->m_mutex);
15603 			mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15604 			    "parent device for handle %d", page_address);
15605 			mdi_rtn = MDI_FAILURE;
15606 			goto virt_create_done;
15607 		}
15608 
15609 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15610 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15611 		rval = mptsas_get_sas_device_page0(mpt, page_address,
15612 		    &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15613 		    &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15614 		if (rval != DDI_SUCCESS) {
15615 			mutex_exit(&mpt->m_mutex);
15616 			mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15617 			    "device info for handle %d", page_address);
15618 			mdi_rtn = MDI_FAILURE;
15619 			goto virt_create_done;
15620 		}
15621 
15622 		mutex_exit(&mpt->m_mutex);
15623 
15624 		/*
15625 		 * If this device direct attached to the controller
15626 		 * set the attached-port to the base wwid
15627 		 */
15628 		if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15629 		    != DEVINFO_DIRECT_ATTACHED) {
15630 			(void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15631 			    pdev_sas_wwn);
15632 		} else {
15633 			/*
15634 			 * Update the iport's attached-port to guid
15635 			 */
15636 			if (sas_wwn == 0) {
15637 				(void) sprintf(wwn_str, "p%x", phy);
15638 			} else {
15639 				(void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15640 			}
15641 			if (ddi_prop_update_string(DDI_DEV_T_NONE,
15642 			    pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15643 			    DDI_PROP_SUCCESS) {
15644 				mptsas_log(mpt, CE_WARN,
15645 				    "mptsas unable to create "
15646 				    "property for iport target-port"
15647 				    " %s (sas_wwn)",
15648 				    wwn_str);
15649 				mdi_rtn = MDI_FAILURE;
15650 				goto virt_create_done;
15651 			}
15652 
15653 			(void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15654 			    mpt->un.m_base_wwid);
15655 		}
15656 
15657 		if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) {
15658 			char	uabuf[SCSI_WWN_BUFLEN];
15659 
15660 			if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) {
15661 				mptsas_log(mpt, CE_WARN,
15662 				    "mptsas unable to format SATA bridge WWN");
15663 				mdi_rtn = MDI_FAILURE;
15664 				goto virt_create_done;
15665 			}
15666 
15667 			if (mdi_prop_update_string(*pip,
15668 			    SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) !=
15669 			    DDI_SUCCESS) {
15670 				mptsas_log(mpt, CE_WARN,
15671 				    "mptsas unable to create SCSI bridge port "
15672 				    "property for SATA device");
15673 				mdi_rtn = MDI_FAILURE;
15674 				goto virt_create_done;
15675 			}
15676 		}
15677 
15678 		if (mdi_prop_update_string(*pip,
15679 		    SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15680 		    DDI_PROP_SUCCESS) {
15681 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15682 			    "property for iport attached-port %s (sas_wwn)",
15683 			    attached_wwn_str);
15684 			mdi_rtn = MDI_FAILURE;
15685 			goto virt_create_done;
15686 		}
15687 
15688 
15689 		if (inq->inq_dtype == 0) {
15690 			component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15691 			/*
15692 			 * set obp path for pathinfo
15693 			 */
15694 			(void) snprintf(component, MAXPATHLEN,
15695 			    "disk@%s", lun_addr);
15696 
15697 			if (mdi_pi_pathname_obp_set(*pip, component) !=
15698 			    DDI_SUCCESS) {
15699 				mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15700 				    "unable to set obp-path for object %s",
15701 				    component);
15702 				mdi_rtn = MDI_FAILURE;
15703 				goto virt_create_done;
15704 			}
15705 		}
15706 
15707 		*lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15708 		if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15709 		    MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15710 			if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
15711 			    "pm-capable", 1)) !=
15712 			    DDI_PROP_SUCCESS) {
15713 				mptsas_log(mpt, CE_WARN, "mptsas driver"
15714 				    "failed to create pm-capable "
15715 				    "property, target %d", target);
15716 				mdi_rtn = MDI_FAILURE;
15717 				goto virt_create_done;
15718 			}
15719 		}
15720 		/*
15721 		 * Create the phy-num property
15722 		 */
15723 		if (mdi_prop_update_int(*pip, "phy-num",
15724 		    ptgt->m_phynum) != DDI_SUCCESS) {
15725 			mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15726 			    "create phy-num property for target %d lun %d",
15727 			    target, lun);
15728 			mdi_rtn = MDI_FAILURE;
15729 			goto virt_create_done;
15730 		}
15731 		NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
15732 		mdi_rtn = mdi_pi_online(*pip, 0);
15733 		if (mdi_rtn == MDI_NOT_SUPPORTED) {
15734 			mdi_rtn = MDI_FAILURE;
15735 		}
15736 virt_create_done:
15737 		if (*pip && mdi_rtn != MDI_SUCCESS) {
15738 			(void) mdi_pi_free(*pip, 0);
15739 			*pip = NULL;
15740 			*lun_dip = NULL;
15741 		}
15742 	}
15743 
15744 	scsi_hba_nodename_compatible_free(nodename, compatible);
15745 	if (lun_addr != NULL) {
15746 		kmem_free(lun_addr, SCSI_MAXNAMELEN);
15747 	}
15748 	if (wwn_str != NULL) {
15749 		kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15750 	}
15751 	if (component != NULL) {
15752 		kmem_free(component, MAXPATHLEN);
15753 	}
15754 
15755 	return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15756 }
15757 
15758 static int
15759 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
15760     char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
15761 {
15762 	int			target;
15763 	int			rval;
15764 	int			ndi_rtn = NDI_FAILURE;
15765 	uint64_t		be_sas_wwn;
15766 	char			*nodename = NULL;
15767 	char			**compatible = NULL;
15768 	int			ncompatible = 0;
15769 	int			instance = 0;
15770 	mptsas_t		*mpt = DIP2MPT(pdip);
15771 	char			*wwn_str = NULL;
15772 	char			*component = NULL;
15773 	char			*attached_wwn_str = NULL;
15774 	uint8_t			phy = 0xFF;
15775 	uint64_t		sas_wwn;
15776 	uint32_t		devinfo;
15777 	uint16_t		dev_hdl;
15778 	uint16_t		pdev_hdl;
15779 	uint64_t		pdev_sas_wwn;
15780 	uint64_t		dev_sas_wwn;
15781 	uint32_t		pdev_info;
15782 	uint8_t			physport;
15783 	uint8_t			phy_id;
15784 	uint32_t		page_address;
15785 	uint16_t		bay_num, enclosure, io_flags;
15786 	char			pdev_wwn_str[MPTSAS_WWN_STRLEN];
15787 	uint32_t		dev_info;
15788 	int64_t			lun64 = 0;
15789 
15790 	mutex_enter(&mpt->m_mutex);
15791 	target = ptgt->m_devhdl;
15792 	sas_wwn = ptgt->m_addr.mta_wwn;
15793 	devinfo = ptgt->m_deviceinfo;
15794 	phy = ptgt->m_phynum;
15795 	mutex_exit(&mpt->m_mutex);
15796 
15797 	/*
15798 	 * generate compatible property with binding-set "mpt"
15799 	 */
15800 	scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
15801 	    &nodename, &compatible, &ncompatible);
15802 
15803 	/*
15804 	 * if nodename can't be determined then print a message and skip it
15805 	 */
15806 	if (nodename == NULL) {
15807 		mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
15808 		    "for target %d lun %d", target, lun);
15809 		return (DDI_FAILURE);
15810 	}
15811 
15812 	ndi_rtn = ndi_devi_alloc(pdip, nodename,
15813 	    DEVI_SID_NODEID, lun_dip);
15814 
15815 	/*
15816 	 * if lun alloc success, set props
15817 	 */
15818 	if (ndi_rtn == NDI_SUCCESS) {
15819 
15820 		if (ndi_prop_update_int(DDI_DEV_T_NONE,
15821 		    *lun_dip, LUN_PROP, lun) !=
15822 		    DDI_PROP_SUCCESS) {
15823 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15824 			    "property for target %d lun %d (LUN_PROP)",
15825 			    target, lun);
15826 			ndi_rtn = NDI_FAILURE;
15827 			goto phys_create_done;
15828 		}
15829 
15830 		lun64 = (int64_t)lun;
15831 		if (ndi_prop_update_int64(DDI_DEV_T_NONE,
15832 		    *lun_dip, LUN64_PROP, lun64) !=
15833 		    DDI_PROP_SUCCESS) {
15834 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15835 			    "property for target %d lun64 %d (LUN64_PROP)",
15836 			    target, lun);
15837 			ndi_rtn = NDI_FAILURE;
15838 			goto phys_create_done;
15839 		}
15840 		if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
15841 		    *lun_dip, "compatible", compatible, ncompatible)
15842 		    != DDI_PROP_SUCCESS) {
15843 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15844 			    "property for target %d lun %d (COMPATIBLE)",
15845 			    target, lun);
15846 			ndi_rtn = NDI_FAILURE;
15847 			goto phys_create_done;
15848 		}
15849 
15850 		/*
15851 		 * We need the SAS WWN for non-multipath devices, so
15852 		 * we'll use the same property as that multipathing
15853 		 * devices need to present for MPAPI. If we don't have
15854 		 * a WWN (e.g. parallel SCSI), don't create the prop.
15855 		 */
15856 		wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15857 		(void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15858 		if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
15859 		    *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
15860 		    != DDI_PROP_SUCCESS) {
15861 			mptsas_log(mpt, CE_WARN, "mptsas unable to "
15862 			    "create property for SAS target %d lun %d "
15863 			    "(target-port)", target, lun);
15864 			ndi_rtn = NDI_FAILURE;
15865 			goto phys_create_done;
15866 		}
15867 
15868 		be_sas_wwn = BE_64(sas_wwn);
15869 		if (sas_wwn && ndi_prop_update_byte_array(
15870 		    DDI_DEV_T_NONE, *lun_dip, "port-wwn",
15871 		    (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
15872 			mptsas_log(mpt, CE_WARN, "mptsas unable to "
15873 			    "create property for SAS target %d lun %d "
15874 			    "(port-wwn)", target, lun);
15875 			ndi_rtn = NDI_FAILURE;
15876 			goto phys_create_done;
15877 		} else if ((sas_wwn == 0) && (ndi_prop_update_int(
15878 		    DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
15879 		    DDI_PROP_SUCCESS)) {
15880 			/*
15881 			 * Direct attached SATA device without DeviceName
15882 			 */
15883 			mptsas_log(mpt, CE_WARN, "mptsas unable to "
15884 			    "create property for SAS target %d lun %d "
15885 			    "(sata-phy)", target, lun);
15886 			ndi_rtn = NDI_FAILURE;
15887 			goto phys_create_done;
15888 		}
15889 
15890 		if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15891 		    *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
15892 			mptsas_log(mpt, CE_WARN, "mptsas unable to"
15893 			    "create property for SAS target %d lun %d"
15894 			    " (SAS_PROP)", target, lun);
15895 			ndi_rtn = NDI_FAILURE;
15896 			goto phys_create_done;
15897 		}
15898 		if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
15899 		    *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
15900 			mptsas_log(mpt, CE_WARN, "mptsas unable "
15901 			    "to create guid property for target %d "
15902 			    "lun %d", target, lun);
15903 			ndi_rtn = NDI_FAILURE;
15904 			goto phys_create_done;
15905 		}
15906 
15907 		/*
15908 		 * The following code is to set properties for SM-HBA support,
15909 		 * it doesn't apply to RAID volumes
15910 		 */
15911 		if (ptgt->m_addr.mta_phymask == 0)
15912 			goto phys_raid_lun;
15913 
15914 		mutex_enter(&mpt->m_mutex);
15915 
15916 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15917 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15918 		    (uint32_t)ptgt->m_devhdl;
15919 		rval = mptsas_get_sas_device_page0(mpt, page_address,
15920 		    &dev_hdl, &dev_sas_wwn, &dev_info,
15921 		    &physport, &phy_id, &pdev_hdl,
15922 		    &bay_num, &enclosure, &io_flags);
15923 		if (rval != DDI_SUCCESS) {
15924 			mutex_exit(&mpt->m_mutex);
15925 			mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15926 			    "parent device for handle %d.", page_address);
15927 			ndi_rtn = NDI_FAILURE;
15928 			goto phys_create_done;
15929 		}
15930 
15931 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15932 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15933 		rval = mptsas_get_sas_device_page0(mpt, page_address,
15934 		    &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15935 		    &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15936 		if (rval != DDI_SUCCESS) {
15937 			mutex_exit(&mpt->m_mutex);
15938 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15939 			    "device for handle %d.", page_address);
15940 			ndi_rtn = NDI_FAILURE;
15941 			goto phys_create_done;
15942 		}
15943 
15944 		mutex_exit(&mpt->m_mutex);
15945 
15946 		/*
15947 		 * If this device direct attached to the controller
15948 		 * set the attached-port to the base wwid
15949 		 */
15950 		if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15951 		    != DEVINFO_DIRECT_ATTACHED) {
15952 			(void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15953 			    pdev_sas_wwn);
15954 		} else {
15955 			/*
15956 			 * Update the iport's attached-port to guid
15957 			 */
15958 			if (sas_wwn == 0) {
15959 				(void) sprintf(wwn_str, "p%x", phy);
15960 			} else {
15961 				(void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15962 			}
15963 			if (ddi_prop_update_string(DDI_DEV_T_NONE,
15964 			    pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15965 			    DDI_PROP_SUCCESS) {
15966 				mptsas_log(mpt, CE_WARN,
15967 				    "mptsas unable to create "
15968 				    "property for iport target-port"
15969 				    " %s (sas_wwn)",
15970 				    wwn_str);
15971 				ndi_rtn = NDI_FAILURE;
15972 				goto phys_create_done;
15973 			}
15974 
15975 			(void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15976 			    mpt->un.m_base_wwid);
15977 		}
15978 
15979 		if (ndi_prop_update_string(DDI_DEV_T_NONE,
15980 		    *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15981 		    DDI_PROP_SUCCESS) {
15982 			mptsas_log(mpt, CE_WARN,
15983 			    "mptsas unable to create "
15984 			    "property for iport attached-port %s (sas_wwn)",
15985 			    attached_wwn_str);
15986 			ndi_rtn = NDI_FAILURE;
15987 			goto phys_create_done;
15988 		}
15989 
15990 		if (IS_SATA_DEVICE(dev_info)) {
15991 			char	uabuf[SCSI_WWN_BUFLEN];
15992 
15993 			if (ndi_prop_update_string(DDI_DEV_T_NONE,
15994 			    *lun_dip, MPTSAS_VARIANT, "sata") !=
15995 			    DDI_PROP_SUCCESS) {
15996 				mptsas_log(mpt, CE_WARN,
15997 				    "mptsas unable to create "
15998 				    "property for device variant ");
15999 				ndi_rtn = NDI_FAILURE;
16000 				goto phys_create_done;
16001 			}
16002 
16003 			if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) {
16004 				mptsas_log(mpt, CE_WARN,
16005 				    "mptsas unable to format SATA bridge WWN");
16006 				ndi_rtn = NDI_FAILURE;
16007 				goto phys_create_done;
16008 			}
16009 
16010 			if (ndi_prop_update_string(DDI_DEV_T_NONE, *lun_dip,
16011 			    SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) !=
16012 			    DDI_PROP_SUCCESS) {
16013 				mptsas_log(mpt, CE_WARN,
16014 				    "mptsas unable to create SCSI bridge port "
16015 				    "property for SATA device");
16016 				ndi_rtn = NDI_FAILURE;
16017 				goto phys_create_done;
16018 			}
16019 		}
16020 
16021 		if (IS_ATAPI_DEVICE(dev_info)) {
16022 			if (ndi_prop_update_string(DDI_DEV_T_NONE,
16023 			    *lun_dip, MPTSAS_VARIANT, "atapi") !=
16024 			    DDI_PROP_SUCCESS) {
16025 				mptsas_log(mpt, CE_WARN,
16026 				    "mptsas unable to create "
16027 				    "property for device variant ");
16028 				ndi_rtn = NDI_FAILURE;
16029 				goto phys_create_done;
16030 			}
16031 		}
16032 
16033 phys_raid_lun:
16034 		/*
16035 		 * if this is a SAS controller, and the target is a SATA
16036 		 * drive, set the 'pm-capable' property for sd and if on
16037 		 * an OPL platform, also check if this is an ATAPI
16038 		 * device.
16039 		 */
16040 		instance = ddi_get_instance(mpt->m_dip);
16041 		if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
16042 		    MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
16043 			NDBG2(("mptsas%d: creating pm-capable property, "
16044 			    "target %d", instance, target));
16045 
16046 			if ((ndi_prop_update_int(DDI_DEV_T_NONE,
16047 			    *lun_dip, "pm-capable", 1)) !=
16048 			    DDI_PROP_SUCCESS) {
16049 				mptsas_log(mpt, CE_WARN, "mptsas "
16050 				    "failed to create pm-capable "
16051 				    "property, target %d", target);
16052 				ndi_rtn = NDI_FAILURE;
16053 				goto phys_create_done;
16054 			}
16055 
16056 		}
16057 
16058 		if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
16059 			/*
16060 			 * add 'obp-path' properties for devinfo
16061 			 */
16062 			bzero(wwn_str, sizeof (wwn_str));
16063 			(void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
16064 			component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
16065 			if (guid) {
16066 				(void) snprintf(component, MAXPATHLEN,
16067 				    "disk@w%s,%x", wwn_str, lun);
16068 			} else {
16069 				(void) snprintf(component, MAXPATHLEN,
16070 				    "disk@p%x,%x", phy, lun);
16071 			}
16072 			if (ddi_pathname_obp_set(*lun_dip, component)
16073 			    != DDI_SUCCESS) {
16074 				mptsas_log(mpt, CE_WARN, "mpt_sas driver "
16075 				    "unable to set obp-path for SAS "
16076 				    "object %s", component);
16077 				ndi_rtn = NDI_FAILURE;
16078 				goto phys_create_done;
16079 			}
16080 		}
16081 		/*
16082 		 * Create the phy-num property for non-raid disk
16083 		 */
16084 		if (ptgt->m_addr.mta_phymask != 0) {
16085 			if (ndi_prop_update_int(DDI_DEV_T_NONE,
16086 			    *lun_dip, "phy-num", ptgt->m_phynum) !=
16087 			    DDI_PROP_SUCCESS) {
16088 				mptsas_log(mpt, CE_WARN, "mptsas driver "
16089 				    "failed to create phy-num property for "
16090 				    "target %d", target);
16091 				ndi_rtn = NDI_FAILURE;
16092 				goto phys_create_done;
16093 			}
16094 		}
16095 phys_create_done:
16096 		/*
16097 		 * If props were setup ok, online the lun
16098 		 */
16099 		if (ndi_rtn == NDI_SUCCESS) {
16100 			/*
16101 			 * Try to online the new node
16102 			 */
16103 			ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
16104 		}
16105 
16106 		/*
16107 		 * If success set rtn flag, else unwire alloc'd lun
16108 		 */
16109 		if (ndi_rtn != NDI_SUCCESS) {
16110 			NDBG12(("mptsas driver unable to online "
16111 			    "target %d lun %d", target, lun));
16112 			ndi_prop_remove_all(*lun_dip);
16113 			(void) ndi_devi_free(*lun_dip);
16114 			*lun_dip = NULL;
16115 		}
16116 	}
16117 
16118 	scsi_hba_nodename_compatible_free(nodename, compatible);
16119 
16120 	if (wwn_str != NULL) {
16121 		kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
16122 	}
16123 	if (component != NULL) {
16124 		kmem_free(component, MAXPATHLEN);
16125 	}
16126 
16127 
16128 	return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16129 }
16130 
16131 static int
16132 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
16133 {
16134 	mptsas_t	*mpt = DIP2MPT(pdip);
16135 	struct smp_device smp_sd;
16136 
16137 	/* XXX An HBA driver should not be allocating an smp_device. */
16138 	bzero(&smp_sd, sizeof (struct smp_device));
16139 	smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
16140 	bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
16141 
16142 	if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
16143 		return (NDI_FAILURE);
16144 	return (NDI_SUCCESS);
16145 }
16146 
16147 static int
16148 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
16149 {
16150 	mptsas_t	*mpt = DIP2MPT(pdip);
16151 	mptsas_smp_t	*psmp = NULL;
16152 	int		rval;
16153 	int		phymask;
16154 
16155 	/*
16156 	 * Get the physical port associated to the iport
16157 	 * PHYMASK TODO
16158 	 */
16159 	phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
16160 	    "phymask", 0);
16161 	/*
16162 	 * Find the smp node in hash table with specified sas address and
16163 	 * physical port
16164 	 */
16165 	psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
16166 	if (psmp == NULL) {
16167 		return (DDI_FAILURE);
16168 	}
16169 
16170 	rval = mptsas_online_smp(pdip, psmp, smp_dip);
16171 
16172 	return (rval);
16173 }
16174 
16175 static int
16176 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
16177     dev_info_t **smp_dip)
16178 {
16179 	char		wwn_str[MPTSAS_WWN_STRLEN];
16180 	char		attached_wwn_str[MPTSAS_WWN_STRLEN];
16181 	int		ndi_rtn = NDI_FAILURE;
16182 	int		rval = 0;
16183 	mptsas_smp_t	dev_info;
16184 	uint32_t	page_address;
16185 	mptsas_t	*mpt = DIP2MPT(pdip);
16186 	uint16_t	dev_hdl;
16187 	uint64_t	sas_wwn;
16188 	uint64_t	smp_sas_wwn;
16189 	uint8_t		physport;
16190 	uint8_t		phy_id;
16191 	uint16_t	pdev_hdl;
16192 	uint8_t		numphys = 0;
16193 	uint16_t	i = 0;
16194 	char		phymask[MPTSAS_MAX_PHYS];
16195 	char		*iport = NULL;
16196 	mptsas_phymask_t	phy_mask = 0;
16197 	uint16_t	attached_devhdl;
16198 	uint16_t	bay_num, enclosure, io_flags;
16199 
16200 	(void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
16201 
16202 	/*
16203 	 * Probe smp device, prevent the node of removed device from being
16204 	 * configured succesfully
16205 	 */
16206 	if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) {
16207 		return (DDI_FAILURE);
16208 	}
16209 
16210 	if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
16211 		return (DDI_SUCCESS);
16212 	}
16213 
16214 	ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
16215 
16216 	/*
16217 	 * if lun alloc success, set props
16218 	 */
16219 	if (ndi_rtn == NDI_SUCCESS) {
16220 		/*
16221 		 * Set the flavor of the child to be SMP flavored
16222 		 */
16223 		ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
16224 
16225 		if (ndi_prop_update_string(DDI_DEV_T_NONE,
16226 		    *smp_dip, SMP_WWN, wwn_str) !=
16227 		    DDI_PROP_SUCCESS) {
16228 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16229 			    "property for smp device %s (sas_wwn)",
16230 			    wwn_str);
16231 			ndi_rtn = NDI_FAILURE;
16232 			goto smp_create_done;
16233 		}
16234 		(void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn);
16235 		if (ndi_prop_update_string(DDI_DEV_T_NONE,
16236 		    *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
16237 		    DDI_PROP_SUCCESS) {
16238 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16239 			    "property for iport target-port %s (sas_wwn)",
16240 			    wwn_str);
16241 			ndi_rtn = NDI_FAILURE;
16242 			goto smp_create_done;
16243 		}
16244 
16245 		mutex_enter(&mpt->m_mutex);
16246 
16247 		page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
16248 		    MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
16249 		rval = mptsas_get_sas_expander_page0(mpt, page_address,
16250 		    &dev_info);
16251 		if (rval != DDI_SUCCESS) {
16252 			mutex_exit(&mpt->m_mutex);
16253 			mptsas_log(mpt, CE_WARN,
16254 			    "mptsas unable to get expander "
16255 			    "parent device info for %x", page_address);
16256 			ndi_rtn = NDI_FAILURE;
16257 			goto smp_create_done;
16258 		}
16259 
16260 		smp_node->m_pdevhdl = dev_info.m_pdevhdl;
16261 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16262 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
16263 		    (uint32_t)dev_info.m_pdevhdl;
16264 		rval = mptsas_get_sas_device_page0(mpt, page_address,
16265 		    &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport,
16266 		    &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
16267 		if (rval != DDI_SUCCESS) {
16268 			mutex_exit(&mpt->m_mutex);
16269 			mptsas_log(mpt, CE_WARN, "mptsas unable to get "
16270 			    "device info for %x", page_address);
16271 			ndi_rtn = NDI_FAILURE;
16272 			goto smp_create_done;
16273 		}
16274 
16275 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16276 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
16277 		    (uint32_t)dev_info.m_devhdl;
16278 		rval = mptsas_get_sas_device_page0(mpt, page_address,
16279 		    &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
16280 		    &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure,
16281 		    &io_flags);
16282 		if (rval != DDI_SUCCESS) {
16283 			mutex_exit(&mpt->m_mutex);
16284 			mptsas_log(mpt, CE_WARN, "mptsas unable to get "
16285 			    "device info for %x", page_address);
16286 			ndi_rtn = NDI_FAILURE;
16287 			goto smp_create_done;
16288 		}
16289 		mutex_exit(&mpt->m_mutex);
16290 
16291 		/*
16292 		 * If this smp direct attached to the controller
16293 		 * set the attached-port to the base wwid
16294 		 */
16295 		if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16296 		    != DEVINFO_DIRECT_ATTACHED) {
16297 			(void) sprintf(attached_wwn_str, "w%016"PRIx64,
16298 			    sas_wwn);
16299 		} else {
16300 			(void) sprintf(attached_wwn_str, "w%016"PRIx64,
16301 			    mpt->un.m_base_wwid);
16302 		}
16303 
16304 		if (ndi_prop_update_string(DDI_DEV_T_NONE,
16305 		    *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
16306 		    DDI_PROP_SUCCESS) {
16307 			mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16308 			    "property for smp attached-port %s (sas_wwn)",
16309 			    attached_wwn_str);
16310 			ndi_rtn = NDI_FAILURE;
16311 			goto smp_create_done;
16312 		}
16313 
16314 		if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
16315 		    *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
16316 			mptsas_log(mpt, CE_WARN, "mptsas unable to "
16317 			    "create property for SMP %s (SMP_PROP) ",
16318 			    wwn_str);
16319 			ndi_rtn = NDI_FAILURE;
16320 			goto smp_create_done;
16321 		}
16322 
16323 		/*
16324 		 * check the smp to see whether it direct
16325 		 * attached to the controller
16326 		 */
16327 		if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16328 		    != DEVINFO_DIRECT_ATTACHED) {
16329 			goto smp_create_done;
16330 		}
16331 		numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
16332 		    DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
16333 		if (numphys > 0) {
16334 			goto smp_create_done;
16335 		}
16336 		/*
16337 		 * this iport is an old iport, we need to
16338 		 * reconfig the props for it.
16339 		 */
16340 		if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16341 		    MPTSAS_VIRTUAL_PORT, 0) !=
16342 		    DDI_PROP_SUCCESS) {
16343 			(void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16344 			    MPTSAS_VIRTUAL_PORT);
16345 			mptsas_log(mpt, CE_WARN, "mptsas virtual port "
16346 			    "prop update failed");
16347 			goto smp_create_done;
16348 		}
16349 
16350 		mutex_enter(&mpt->m_mutex);
16351 		numphys = 0;
16352 		iport = ddi_get_name_addr(pdip);
16353 		for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16354 			bzero(phymask, sizeof (phymask));
16355 			(void) sprintf(phymask,
16356 			    "%x", mpt->m_phy_info[i].phy_mask);
16357 			if (strcmp(phymask, iport) == 0) {
16358 				phy_mask = mpt->m_phy_info[i].phy_mask;
16359 				break;
16360 			}
16361 		}
16362 
16363 		for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16364 			if ((phy_mask >> i) & 0x01) {
16365 				numphys++;
16366 			}
16367 		}
16368 		/*
16369 		 * Update PHY info for smhba
16370 		 */
16371 		if (mptsas_smhba_phy_init(mpt)) {
16372 			mutex_exit(&mpt->m_mutex);
16373 			mptsas_log(mpt, CE_WARN, "mptsas phy update "
16374 			    "failed");
16375 			goto smp_create_done;
16376 		}
16377 		mutex_exit(&mpt->m_mutex);
16378 
16379 		mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
16380 		    &attached_devhdl);
16381 
16382 		if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16383 		    MPTSAS_NUM_PHYS, numphys) !=
16384 		    DDI_PROP_SUCCESS) {
16385 			(void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16386 			    MPTSAS_NUM_PHYS);
16387 			mptsas_log(mpt, CE_WARN, "mptsas update "
16388 			    "num phys props failed");
16389 			goto smp_create_done;
16390 		}
16391 		/*
16392 		 * Add parent's props for SMHBA support
16393 		 */
16394 		if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
16395 		    SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
16396 		    DDI_PROP_SUCCESS) {
16397 			(void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16398 			    SCSI_ADDR_PROP_ATTACHED_PORT);
16399 			mptsas_log(mpt, CE_WARN, "mptsas update iport"
16400 			    "attached-port failed");
16401 			goto smp_create_done;
16402 		}
16403 
16404 smp_create_done:
16405 		/*
16406 		 * If props were setup ok, online the lun
16407 		 */
16408 		if (ndi_rtn == NDI_SUCCESS) {
16409 			/*
16410 			 * Try to online the new node
16411 			 */
16412 			ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
16413 		}
16414 
16415 		/*
16416 		 * If success set rtn flag, else unwire alloc'd lun
16417 		 */
16418 		if (ndi_rtn != NDI_SUCCESS) {
16419 			NDBG12(("mptsas unable to online "
16420 			    "SMP target %s", wwn_str));
16421 			ndi_prop_remove_all(*smp_dip);
16422 			(void) ndi_devi_free(*smp_dip);
16423 		}
16424 	}
16425 
16426 	return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16427 }
16428 
16429 /* smp transport routine */
16430 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
16431 {
16432 	uint64_t			wwn;
16433 	Mpi2SmpPassthroughRequest_t	req;
16434 	Mpi2SmpPassthroughReply_t	rep;
16435 	uint32_t			direction = 0;
16436 	mptsas_t			*mpt;
16437 	int				ret;
16438 	uint64_t			tmp64;
16439 
16440 	mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
16441 	    smp_a_hba_tran->smp_tran_hba_private;
16442 
16443 	bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
16444 	/*
16445 	 * Need to compose a SMP request message
16446 	 * and call mptsas_do_passthru() function
16447 	 */
16448 	bzero(&req, sizeof (req));
16449 	bzero(&rep, sizeof (rep));
16450 	req.PassthroughFlags = 0;
16451 	req.PhysicalPort = 0xff;
16452 	req.ChainOffset = 0;
16453 	req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
16454 
16455 	if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
16456 		smp_pkt->smp_pkt_reason = ERANGE;
16457 		return (DDI_FAILURE);
16458 	}
16459 	req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
16460 
16461 	req.MsgFlags = 0;
16462 	tmp64 = LE_64(wwn);
16463 	bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
16464 	if (smp_pkt->smp_pkt_rspsize > 0) {
16465 		direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
16466 	}
16467 	if (smp_pkt->smp_pkt_reqsize > 0) {
16468 		direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
16469 	}
16470 
16471 	mutex_enter(&mpt->m_mutex);
16472 	ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
16473 	    (uint8_t *)smp_pkt->smp_pkt_rsp,
16474 	    offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
16475 	    smp_pkt->smp_pkt_rspsize - 4, direction,
16476 	    (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
16477 	    smp_pkt->smp_pkt_timeout, FKIOCTL);
16478 	mutex_exit(&mpt->m_mutex);
16479 	if (ret != 0) {
16480 		cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
16481 		smp_pkt->smp_pkt_reason = (uchar_t)(ret);
16482 		return (DDI_FAILURE);
16483 	}
16484 	/* do passthrough success, check the smp status */
16485 	if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16486 		switch (LE_16(rep.IOCStatus)) {
16487 		case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
16488 			smp_pkt->smp_pkt_reason = ENODEV;
16489 			break;
16490 		case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
16491 			smp_pkt->smp_pkt_reason = EOVERFLOW;
16492 			break;
16493 		case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
16494 			smp_pkt->smp_pkt_reason = EIO;
16495 			break;
16496 		default:
16497 			mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
16498 			    "status:%x", LE_16(rep.IOCStatus));
16499 			smp_pkt->smp_pkt_reason = EIO;
16500 			break;
16501 		}
16502 		return (DDI_FAILURE);
16503 	}
16504 	if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
16505 		mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
16506 		    rep.SASStatus);
16507 		smp_pkt->smp_pkt_reason = EIO;
16508 		return (DDI_FAILURE);
16509 	}
16510 
16511 	return (DDI_SUCCESS);
16512 }
16513 
16514 /*
16515  * If we didn't get a match, we need to get sas page0 for each device, and
16516  * untill we get a match. If failed, return NULL
16517  */
16518 static mptsas_target_t *
16519 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy)
16520 {
16521 	int		i, j = 0;
16522 	int		rval = 0;
16523 	uint16_t	cur_handle;
16524 	uint32_t	page_address;
16525 	mptsas_target_t	*ptgt = NULL;
16526 
16527 	/*
16528 	 * PHY named device must be direct attached and attaches to
16529 	 * narrow port, if the iport is not parent of the device which
16530 	 * we are looking for.
16531 	 */
16532 	for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16533 		if ((1 << i) & phymask)
16534 			j++;
16535 	}
16536 
16537 	if (j > 1)
16538 		return (NULL);
16539 
16540 	/*
16541 	 * Must be a narrow port and single device attached to the narrow port
16542 	 * So the physical port num of device  which is equal to the iport's
16543 	 * port num is the device what we are looking for.
16544 	 */
16545 
16546 	if (mpt->m_phy_info[phy].phy_mask != phymask)
16547 		return (NULL);
16548 
16549 	mutex_enter(&mpt->m_mutex);
16550 
16551 	ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn,
16552 	    &phy);
16553 	if (ptgt != NULL) {
16554 		mutex_exit(&mpt->m_mutex);
16555 		return (ptgt);
16556 	}
16557 
16558 	if (mpt->m_done_traverse_dev) {
16559 		mutex_exit(&mpt->m_mutex);
16560 		return (NULL);
16561 	}
16562 
16563 	/* If didn't get a match, come here */
16564 	cur_handle = mpt->m_dev_handle;
16565 	for (; ; ) {
16566 		ptgt = NULL;
16567 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16568 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16569 		rval = mptsas_get_target_device_info(mpt, page_address,
16570 		    &cur_handle, &ptgt);
16571 		if ((rval == DEV_INFO_FAIL_PAGE0) ||
16572 		    (rval == DEV_INFO_FAIL_ALLOC) ||
16573 		    (rval == DEV_INFO_FAIL_GUID)) {
16574 			break;
16575 		}
16576 		if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16577 		    (rval == DEV_INFO_PHYS_DISK)) {
16578 			continue;
16579 		}
16580 		mpt->m_dev_handle = cur_handle;
16581 
16582 		if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) {
16583 			break;
16584 		}
16585 	}
16586 
16587 	mutex_exit(&mpt->m_mutex);
16588 	return (ptgt);
16589 }
16590 
16591 /*
16592  * The ptgt->m_addr.mta_wwn contains the wwid for each disk.
16593  * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
16594  * If we didn't get a match, we need to get sas page0 for each device, and
16595  * untill we get a match
16596  * If failed, return NULL
16597  */
16598 static mptsas_target_t *
16599 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16600 {
16601 	int		rval = 0;
16602 	uint16_t	cur_handle;
16603 	uint32_t	page_address;
16604 	mptsas_target_t	*tmp_tgt = NULL;
16605 	mptsas_target_addr_t addr;
16606 
16607 	addr.mta_wwn = wwid;
16608 	addr.mta_phymask = phymask;
16609 	mutex_enter(&mpt->m_mutex);
16610 	tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16611 	if (tmp_tgt != NULL) {
16612 		mutex_exit(&mpt->m_mutex);
16613 		return (tmp_tgt);
16614 	}
16615 
16616 	if (phymask == 0) {
16617 		/*
16618 		 * It's IR volume
16619 		 */
16620 		rval = mptsas_get_raid_info(mpt);
16621 		if (rval) {
16622 			tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16623 		}
16624 		mutex_exit(&mpt->m_mutex);
16625 		return (tmp_tgt);
16626 	}
16627 
16628 	if (mpt->m_done_traverse_dev) {
16629 		mutex_exit(&mpt->m_mutex);
16630 		return (NULL);
16631 	}
16632 
16633 	/* If didn't get a match, come here */
16634 	cur_handle = mpt->m_dev_handle;
16635 	for (;;) {
16636 		tmp_tgt = NULL;
16637 		page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16638 		    MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
16639 		rval = mptsas_get_target_device_info(mpt, page_address,
16640 		    &cur_handle, &tmp_tgt);
16641 		if ((rval == DEV_INFO_FAIL_PAGE0) ||
16642 		    (rval == DEV_INFO_FAIL_ALLOC) ||
16643 		    (rval == DEV_INFO_FAIL_GUID)) {
16644 			tmp_tgt = NULL;
16645 			break;
16646 		}
16647 		if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16648 		    (rval == DEV_INFO_PHYS_DISK)) {
16649 			continue;
16650 		}
16651 		mpt->m_dev_handle = cur_handle;
16652 		if ((tmp_tgt->m_addr.mta_wwn) &&
16653 		    (tmp_tgt->m_addr.mta_wwn == wwid) &&
16654 		    (tmp_tgt->m_addr.mta_phymask == phymask)) {
16655 			break;
16656 		}
16657 	}
16658 
16659 	mutex_exit(&mpt->m_mutex);
16660 	return (tmp_tgt);
16661 }
16662 
16663 static mptsas_smp_t *
16664 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16665 {
16666 	int		rval = 0;
16667 	uint16_t	cur_handle;
16668 	uint32_t	page_address;
16669 	mptsas_smp_t	smp_node, *psmp = NULL;
16670 	mptsas_target_addr_t addr;
16671 
16672 	addr.mta_wwn = wwid;
16673 	addr.mta_phymask = phymask;
16674 	mutex_enter(&mpt->m_mutex);
16675 	psmp = refhash_lookup(mpt->m_smp_targets, &addr);
16676 	if (psmp != NULL) {
16677 		mutex_exit(&mpt->m_mutex);
16678 		return (psmp);
16679 	}
16680 
16681 	if (mpt->m_done_traverse_smp) {
16682 		mutex_exit(&mpt->m_mutex);
16683 		return (NULL);
16684 	}
16685 
16686 	/* If didn't get a match, come here */
16687 	cur_handle = mpt->m_smp_devhdl;
16688 	for (;;) {
16689 		psmp = NULL;
16690 		page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
16691 		    MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16692 		rval = mptsas_get_sas_expander_page0(mpt, page_address,
16693 		    &smp_node);
16694 		if (rval != DDI_SUCCESS) {
16695 			break;
16696 		}
16697 		mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
16698 		psmp = mptsas_smp_alloc(mpt, &smp_node);
16699 		ASSERT(psmp);
16700 		if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) &&
16701 		    (psmp->m_addr.mta_phymask == phymask)) {
16702 			break;
16703 		}
16704 	}
16705 
16706 	mutex_exit(&mpt->m_mutex);
16707 	return (psmp);
16708 }
16709 
16710 mptsas_target_t *
16711 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid,
16712     uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
16713 {
16714 	mptsas_target_t *tmp_tgt = NULL;
16715 	mptsas_target_addr_t addr;
16716 
16717 	addr.mta_wwn = wwid;
16718 	addr.mta_phymask = phymask;
16719 	tmp_tgt = refhash_lookup(refhash, &addr);
16720 	if (tmp_tgt != NULL) {
16721 		NDBG20(("Hash item already exist"));
16722 		tmp_tgt->m_deviceinfo = devinfo;
16723 		tmp_tgt->m_devhdl = devhdl;	/* XXX - duplicate? */
16724 		return (tmp_tgt);
16725 	}
16726 	tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
16727 	if (tmp_tgt == NULL) {
16728 		cmn_err(CE_WARN, "Fatal, allocated tgt failed");
16729 		return (NULL);
16730 	}
16731 	tmp_tgt->m_devhdl = devhdl;
16732 	tmp_tgt->m_addr.mta_wwn = wwid;
16733 	tmp_tgt->m_deviceinfo = devinfo;
16734 	tmp_tgt->m_addr.mta_phymask = phymask;
16735 	tmp_tgt->m_phynum = phynum;
16736 	/* Initialized the tgt structure */
16737 	tmp_tgt->m_qfull_retries = QFULL_RETRIES;
16738 	tmp_tgt->m_qfull_retry_interval =
16739 	    drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
16740 	tmp_tgt->m_t_throttle = MAX_THROTTLE;
16741 	TAILQ_INIT(&tmp_tgt->m_active_cmdq);
16742 
16743 	refhash_insert(refhash, tmp_tgt);
16744 
16745 	return (tmp_tgt);
16746 }
16747 
16748 static void
16749 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst)
16750 {
16751 	dst->m_devhdl = src->m_devhdl;
16752 	dst->m_deviceinfo = src->m_deviceinfo;
16753 	dst->m_pdevhdl = src->m_pdevhdl;
16754 	dst->m_pdevinfo = src->m_pdevinfo;
16755 }
16756 
16757 static mptsas_smp_t *
16758 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data)
16759 {
16760 	mptsas_target_addr_t addr;
16761 	mptsas_smp_t *ret_data;
16762 
16763 	addr.mta_wwn = data->m_addr.mta_wwn;
16764 	addr.mta_phymask = data->m_addr.mta_phymask;
16765 	ret_data = refhash_lookup(mpt->m_smp_targets, &addr);
16766 	/*
16767 	 * If there's already a matching SMP target, update its fields
16768 	 * in place.  Since the address is not changing, it's safe to do
16769 	 * this.  We cannot just bcopy() here because the structure we've
16770 	 * been given has invalid hash links.
16771 	 */
16772 	if (ret_data != NULL) {
16773 		mptsas_smp_target_copy(data, ret_data);
16774 		return (ret_data);
16775 	}
16776 
16777 	ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
16778 	bcopy(data, ret_data, sizeof (mptsas_smp_t));
16779 	refhash_insert(mpt->m_smp_targets, ret_data);
16780 	return (ret_data);
16781 }
16782 
16783 /*
16784  * Functions for SGPIO LED support
16785  */
16786 static dev_info_t *
16787 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
16788 {
16789 	dev_info_t	*dip;
16790 	int		prop;
16791 	dip = e_ddi_hold_devi_by_dev(dev, 0);
16792 	if (dip == NULL)
16793 		return (dip);
16794 	prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
16795 	    "phymask", 0);
16796 	*phymask = (mptsas_phymask_t)prop;
16797 	ddi_release_devi(dip);
16798 	return (dip);
16799 }
16800 static mptsas_target_t *
16801 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
16802 {
16803 	uint8_t			phynum;
16804 	uint64_t		wwn;
16805 	int			lun;
16806 	mptsas_target_t		*ptgt = NULL;
16807 
16808 	if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
16809 		return (NULL);
16810 	}
16811 	if (addr[0] == 'w') {
16812 		ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
16813 	} else {
16814 		ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
16815 	}
16816 	return (ptgt);
16817 }
16818 
16819 static int
16820 mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx)
16821 {
16822 	uint32_t slotstatus = 0;
16823 
16824 	ASSERT3U(idx, <, mep->me_nslots);
16825 
16826 	/* Build an MPI2 Slot Status based on our view of the world */
16827 	if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
16828 		slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
16829 	if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
16830 		slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
16831 	if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
16832 		slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
16833 
16834 	/* Write it to the controller */
16835 	NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
16836 	    slotstatus, idx + mep->me_fslot));
16837 	return (mptsas_send_sep(mpt, mep, idx, &slotstatus,
16838 	    MPI2_SEP_REQ_ACTION_WRITE_STATUS));
16839 }
16840 
16841 /*
16842  *  send sep request, use enclosure/slot addressing
16843  */
16844 static int
16845 mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx,
16846     uint32_t *status, uint8_t act)
16847 {
16848 	Mpi2SepRequest_t	req;
16849 	Mpi2SepReply_t		rep;
16850 	int			ret;
16851 	uint16_t 		enctype;
16852 	uint16_t		slot;
16853 
16854 	ASSERT(mutex_owned(&mpt->m_mutex));
16855 
16856 	/*
16857 	 * Look through the enclosures and make sure that this enclosure is
16858 	 * something that is directly attached device. If we didn't find an
16859 	 * enclosure for this device, don't send the ioctl.
16860 	 */
16861 	enctype = mep->me_flags & MPI2_SAS_ENCLS0_FLAGS_MNG_MASK;
16862 	if (enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES &&
16863 	    enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO &&
16864 	    enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO) {
16865 		return (ENOTTY);
16866 	}
16867 	slot = idx + mep->me_fslot;
16868 
16869 	bzero(&req, sizeof (req));
16870 	bzero(&rep, sizeof (rep));
16871 
16872 	req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
16873 	req.Action = act;
16874 	req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
16875 	req.EnclosureHandle = LE_16(mep->me_enchdl);
16876 	req.Slot = LE_16(slot);
16877 	if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16878 		req.SlotStatus = LE_32(*status);
16879 	}
16880 	ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
16881 	    sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
16882 	if (ret != 0) {
16883 		mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
16884 		    "Processor Request message error %d", ret);
16885 		return (ret);
16886 	}
16887 	/* do passthrough success, check the ioc status */
16888 	if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16889 		mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
16890 		    "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
16891 		    LE_32(rep.IOCLogInfo));
16892 		switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
16893 		case MPI2_IOCSTATUS_INVALID_FUNCTION:
16894 		case MPI2_IOCSTATUS_INVALID_VPID:
16895 		case MPI2_IOCSTATUS_INVALID_FIELD:
16896 		case MPI2_IOCSTATUS_INVALID_STATE:
16897 		case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
16898 		case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
16899 		case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
16900 		case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
16901 		case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
16902 		case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
16903 			return (EINVAL);
16904 		case MPI2_IOCSTATUS_BUSY:
16905 			return (EBUSY);
16906 		case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
16907 			return (EAGAIN);
16908 		case MPI2_IOCSTATUS_INVALID_SGL:
16909 		case MPI2_IOCSTATUS_INTERNAL_ERROR:
16910 		case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
16911 		default:
16912 			return (EIO);
16913 		}
16914 	}
16915 	if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16916 		*status = LE_32(rep.SlotStatus);
16917 	}
16918 
16919 	return (0);
16920 }
16921 
16922 int
16923 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
16924     ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
16925     uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
16926 {
16927 	ddi_dma_cookie_t	new_cookie;
16928 	size_t			alloc_len;
16929 	uint_t			ncookie;
16930 
16931 	if (cookiep == NULL)
16932 		cookiep = &new_cookie;
16933 
16934 	if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
16935 	    NULL, dma_hdp) != DDI_SUCCESS) {
16936 		return (FALSE);
16937 	}
16938 
16939 	if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
16940 	    DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
16941 	    acc_hdp) != DDI_SUCCESS) {
16942 		ddi_dma_free_handle(dma_hdp);
16943 		*dma_hdp = NULL;
16944 		return (FALSE);
16945 	}
16946 
16947 	if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
16948 	    (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
16949 	    cookiep, &ncookie) != DDI_DMA_MAPPED) {
16950 		(void) ddi_dma_mem_free(acc_hdp);
16951 		ddi_dma_free_handle(dma_hdp);
16952 		*dma_hdp = NULL;
16953 		return (FALSE);
16954 	}
16955 
16956 	return (TRUE);
16957 }
16958 
16959 void
16960 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
16961 {
16962 	if (*dma_hdp == NULL)
16963 		return;
16964 
16965 	(void) ddi_dma_unbind_handle(*dma_hdp);
16966 	(void) ddi_dma_mem_free(acc_hdp);
16967 	ddi_dma_free_handle(dma_hdp);
16968 	*dma_hdp = NULL;
16969 }
16970