1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 25 */ 26 27/* 28 * Copyright (c) 2000 to 2010, LSI Corporation. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms of all code within 32 * this file that is exclusively owned by LSI, with or without 33 * modification, is permitted provided that, in addition to the CDDL 1.0 34 * License requirements, the following conditions are met: 35 * 36 * Neither the name of the author nor the names of its contributors may be 37 * used to endorse or promote products derived from this software without 38 * specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 43 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 44 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 46 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 47 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 48 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 51 * DAMAGE. 52 */ 53 54/* 55 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface. 56 * 57 */ 58 59#if defined(lint) || defined(DEBUG) 60#define MPTSAS_DEBUG 61#endif 62 63/* 64 * standard header files. 65 */ 66#include <sys/note.h> 67#include <sys/scsi/scsi.h> 68#include <sys/pci.h> 69#include <sys/file.h> 70#include <sys/cpuvar.h> 71#include <sys/policy.h> 72#include <sys/sysevent.h> 73#include <sys/sysevent/eventdefs.h> 74#include <sys/sysevent/dr.h> 75#include <sys/sata/sata_defs.h> 76#include <sys/scsi/generic/sas.h> 77#include <sys/scsi/impl/scsi_sas.h> 78 79#pragma pack(1) 80#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 81#include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 82#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 83#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 84#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 85#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 86#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 87#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 88#pragma pack() 89 90/* 91 * private header files. 92 * 93 */ 94#include <sys/scsi/impl/scsi_reset_notify.h> 95#include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 96#include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 97#include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h> 98 99#include <sys/raidioctl.h> 100 101#include <sys/fs/dv_node.h> /* devfs_clean */ 102 103/* 104 * FMA header files 105 */ 106#include <sys/ddifm.h> 107#include <sys/fm/protocol.h> 108#include <sys/fm/util.h> 109#include <sys/fm/io/ddi.h> 110 111/* 112 * For anyone who would modify the code in mptsas_driver, it must be awared 113 * that from snv_145 where CR6910752(mpt_sas driver performance can be 114 * improved) is integrated, the per_instance mutex m_mutex is not hold 115 * in the key IO code path, including mptsas_scsi_start(), mptsas_intr() 116 * and all of the recursive functions called in them, so don't 117 * make it for granted that all operations are sync/exclude correctly. Before 118 * doing any modification in key code path, and even other code path such as 119 * DR, watchsubr, ioctl, passthrough etc, make sure the elements modified have 120 * no releationship to elements shown in the fastpath 121 * (function mptsas_handle_io_fastpath()) in ISR and its recursive functions. 122 * otherwise, you have to use the new introduced mutex to protect them. 123 * As to how to do correctly, refer to the comments in mptsas_intr(). 124 */ 125 126/* 127 * autoconfiguration data and routines. 128 */ 129static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 130static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 131static int mptsas_power(dev_info_t *dip, int component, int level); 132 133/* 134 * cb_ops function 135 */ 136static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 137 cred_t *credp, int *rval); 138#ifdef __sparc 139static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 140#else /* __sparc */ 141static int mptsas_quiesce(dev_info_t *devi); 142#endif /* __sparc */ 143 144/* 145 * Resource initilaization for hardware 146 */ 147static void mptsas_setup_cmd_reg(mptsas_t *mpt); 148static void mptsas_disable_bus_master(mptsas_t *mpt); 149static void mptsas_hba_fini(mptsas_t *mpt); 150static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 151static int mptsas_hba_setup(mptsas_t *mpt); 152static void mptsas_hba_teardown(mptsas_t *mpt); 153static int mptsas_config_space_init(mptsas_t *mpt); 154static void mptsas_config_space_fini(mptsas_t *mpt); 155static void mptsas_iport_register(mptsas_t *mpt); 156static int mptsas_smp_setup(mptsas_t *mpt); 157static void mptsas_smp_teardown(mptsas_t *mpt); 158static int mptsas_cache_create(mptsas_t *mpt); 159static void mptsas_cache_destroy(mptsas_t *mpt); 160static int mptsas_alloc_request_frames(mptsas_t *mpt); 161static int mptsas_alloc_reply_frames(mptsas_t *mpt); 162static int mptsas_alloc_free_queue(mptsas_t *mpt); 163static int mptsas_alloc_post_queue(mptsas_t *mpt); 164static void mptsas_alloc_reply_args(mptsas_t *mpt); 165static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 166static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 167static int mptsas_init_chip(mptsas_t *mpt, int first_time); 168 169/* 170 * SCSA function prototypes 171 */ 172static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 173static int mptsas_scsi_reset(struct scsi_address *ap, int level); 174static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 175static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 176static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 177 int tgtonly); 178static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 179static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 180 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 181 int tgtlen, int flags, int (*callback)(), caddr_t arg); 182static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 183static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 184 struct scsi_pkt *pkt); 185static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 186 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 187static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 188 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 189static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 190 void (*callback)(caddr_t), caddr_t arg); 191static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 192static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 193static int mptsas_scsi_quiesce(dev_info_t *dip); 194static int mptsas_scsi_unquiesce(dev_info_t *dip); 195static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 196 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 197 198/* 199 * SMP functions 200 */ 201static int mptsas_smp_start(struct smp_pkt *smp_pkt); 202 203/* 204 * internal function prototypes. 205 */ 206static void mptsas_list_add(mptsas_t *mpt); 207static void mptsas_list_del(mptsas_t *mpt); 208 209static int mptsas_quiesce_bus(mptsas_t *mpt); 210static int mptsas_unquiesce_bus(mptsas_t *mpt); 211 212static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 213static void mptsas_free_handshake_msg(mptsas_t *mpt); 214 215static void mptsas_ncmds_checkdrain(void *arg); 216 217static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 218static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 219 220static int mptsas_do_detach(dev_info_t *dev); 221static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 222static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 223 struct scsi_pkt *pkt); 224static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 225 226static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 227static void mptsas_handle_event(void *args); 228static int mptsas_handle_event_sync(void *args); 229static void mptsas_handle_dr(void *args); 230static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 231 dev_info_t *pdip); 232 233static void mptsas_restart_cmd(void *); 234 235static void mptsas_flush_hba(mptsas_t *mpt); 236static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 237 uint8_t tasktype); 238static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 239 uchar_t reason, uint_t stat); 240 241static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 242static void mptsas_process_intr(mptsas_t *mpt, 243 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 244static int mptsas_handle_io_fastpath(mptsas_t *mpt, uint16_t SMID); 245static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 246 pMpi2ReplyDescriptorsUnion_t reply_desc); 247static void mptsas_handle_address_reply(mptsas_t *mpt, 248 pMpi2ReplyDescriptorsUnion_t reply_desc); 249static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 250static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 251 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 252 253static void mptsas_watch(void *arg); 254static void mptsas_watchsubr(mptsas_t *mpt); 255static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl); 256 257static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 258static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 259 uint8_t *data, uint32_t request_size, uint32_t reply_size, 260 uint32_t data_size, uint32_t direction, uint8_t *dataout, 261 uint32_t dataout_size, short timeout, int mode); 262static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 263 264static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 265 uint32_t unique_id); 266static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 267static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 268 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 269static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 270 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 271 uint32_t diag_type); 272static int mptsas_diag_register(mptsas_t *mpt, 273 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 274static int mptsas_diag_unregister(mptsas_t *mpt, 275 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 276static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 277 uint32_t *return_code); 278static int mptsas_diag_read_buffer(mptsas_t *mpt, 279 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 280 uint32_t *return_code, int ioctl_mode); 281static int mptsas_diag_release(mptsas_t *mpt, 282 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 283static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 284 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 285 int ioctl_mode); 286static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 287 int mode); 288 289static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 290 int cmdlen, int tgtlen, int statuslen, int kf); 291static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 292 293static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 294static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 295 296static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 297 int kmflags); 298static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 299 300static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 301 mptsas_cmd_t *cmd); 302static void mptsas_check_task_mgt(mptsas_t *mpt, 303 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 304static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 305 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 306 int *resid); 307 308static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 309static void mptsas_free_active_slots(mptsas_t *mpt); 310static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 311static int mptsas_start_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd); 312 313static void mptsas_restart_hba(mptsas_t *mpt); 314 315static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 316static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 317static inline void mptsas_doneq_add0(mptsas_t *mpt, mptsas_cmd_t *cmd); 318static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 319 320static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 321static void mptsas_doneq_empty(mptsas_t *mpt); 322static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 323 324static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 325static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 326 327static void mptsas_start_watch_reset_delay(); 328static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 329static void mptsas_watch_reset_delay(void *arg); 330static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 331 332static int mptsas_outstanding_cmds_n(mptsas_t *mpt); 333/* 334 * helper functions 335 */ 336static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 337 338static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 339static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 340static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 341 int lun); 342static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 343 int lun); 344static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 345static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 346 347static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 348 int *lun); 349static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 350 351static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, 352 uint8_t phy); 353static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, 354 uint64_t wwid); 355static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, 356 uint64_t wwid); 357 358static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 359 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 360 361static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 362 uint16_t *handle, mptsas_target_t **pptgt); 363static void mptsas_update_phymask(mptsas_t *mpt); 364static inline void mptsas_remove_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd); 365 366static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 367 uint32_t *status, uint8_t cmd); 368static dev_info_t *mptsas_get_dip_from_dev(dev_t dev, 369 mptsas_phymask_t *phymask); 370static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, 371 mptsas_phymask_t phymask); 372static int mptsas_set_led_status(mptsas_t *mpt, mptsas_target_t *ptgt, 373 uint32_t slotstatus); 374 375 376/* 377 * Enumeration / DR functions 378 */ 379static void mptsas_config_all(dev_info_t *pdip); 380static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 381 dev_info_t **lundip); 382static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 383 dev_info_t **lundip); 384 385static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 386static int mptsas_offline_target(dev_info_t *pdip, char *name); 387 388static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 389 dev_info_t **dip); 390 391static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 392static int mptsas_probe_lun(dev_info_t *pdip, int lun, 393 dev_info_t **dip, mptsas_target_t *ptgt); 394 395static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 396 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 397 398static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 399 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 400static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 401 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 402 int lun); 403 404static void mptsas_offline_missed_luns(dev_info_t *pdip, 405 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 406static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 407 mdi_pathinfo_t *rpip, uint_t flags); 408 409static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 410 dev_info_t **smp_dip); 411static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 412 uint_t flags); 413 414static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 415 int mode, int *rval); 416static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 417 int mode, int *rval); 418static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 419 int mode, int *rval); 420static void mptsas_record_event(void *args); 421static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 422 int mode); 423 424static void mptsas_hash_init(mptsas_hash_table_t *hashtab); 425static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen); 426static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data); 427static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1, 428 mptsas_phymask_t key2); 429static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1, 430 mptsas_phymask_t key2); 431static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos); 432 433mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t, 434 uint32_t, mptsas_phymask_t, uint8_t, mptsas_t *); 435static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab, 436 mptsas_smp_t *data); 437static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid, 438 mptsas_phymask_t phymask); 439static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t); 440static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t); 441static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 442 dev_info_t **smp_dip); 443 444/* 445 * Power management functions 446 */ 447static int mptsas_get_pci_cap(mptsas_t *mpt); 448static int mptsas_init_pm(mptsas_t *mpt); 449 450/* 451 * MPT MSI tunable: 452 * 453 * By default MSI is enabled on all supported platforms. 454 */ 455boolean_t mptsas_enable_msi = B_TRUE; 456boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE; 457 458static int mptsas_register_intrs(mptsas_t *); 459static void mptsas_unregister_intrs(mptsas_t *); 460static int mptsas_add_intrs(mptsas_t *, int); 461static void mptsas_rem_intrs(mptsas_t *); 462 463/* 464 * FMA Prototypes 465 */ 466static void mptsas_fm_init(mptsas_t *mpt); 467static void mptsas_fm_fini(mptsas_t *mpt); 468static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 469 470extern pri_t minclsyspri, maxclsyspri; 471 472/* 473 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 474 * under this device that the paths to a physical device are created when 475 * MPxIO is used. 476 */ 477extern dev_info_t *scsi_vhci_dip; 478 479/* 480 * Tunable timeout value for Inquiry VPD page 0x83 481 * By default the value is 30 seconds. 482 */ 483int mptsas_inq83_retry_timeout = 30; 484 485/* 486 * This is used to allocate memory for message frame storage, not for 487 * data I/O DMA. All message frames must be stored in the first 4G of 488 * physical memory. 489 */ 490ddi_dma_attr_t mptsas_dma_attrs = { 491 DMA_ATTR_V0, /* attribute layout version */ 492 0x0ull, /* address low - should be 0 (longlong) */ 493 0xffffffffull, /* address high - 32-bit max range */ 494 0x00ffffffull, /* count max - max DMA object size */ 495 4, /* allocation alignment requirements */ 496 0x78, /* burstsizes - binary encoded values */ 497 1, /* minxfer - gran. of DMA engine */ 498 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 499 0xffffffffull, /* max segment size (DMA boundary) */ 500 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 501 512, /* granularity - device transfer size */ 502 0 /* flags, set to 0 */ 503}; 504 505/* 506 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 507 * physical addresses are supported.) 508 */ 509ddi_dma_attr_t mptsas_dma_attrs64 = { 510 DMA_ATTR_V0, /* attribute layout version */ 511 0x0ull, /* address low - should be 0 (longlong) */ 512 0xffffffffffffffffull, /* address high - 64-bit max */ 513 0x00ffffffull, /* count max - max DMA object size */ 514 4, /* allocation alignment requirements */ 515 0x78, /* burstsizes - binary encoded values */ 516 1, /* minxfer - gran. of DMA engine */ 517 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 518 0xffffffffull, /* max segment size (DMA boundary) */ 519 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 520 512, /* granularity - device transfer size */ 521 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */ 522}; 523 524ddi_device_acc_attr_t mptsas_dev_attr = { 525 DDI_DEVICE_ATTR_V1, 526 DDI_STRUCTURE_LE_ACC, 527 DDI_STRICTORDER_ACC, 528 DDI_DEFAULT_ACC 529}; 530 531static struct cb_ops mptsas_cb_ops = { 532 scsi_hba_open, /* open */ 533 scsi_hba_close, /* close */ 534 nodev, /* strategy */ 535 nodev, /* print */ 536 nodev, /* dump */ 537 nodev, /* read */ 538 nodev, /* write */ 539 mptsas_ioctl, /* ioctl */ 540 nodev, /* devmap */ 541 nodev, /* mmap */ 542 nodev, /* segmap */ 543 nochpoll, /* chpoll */ 544 ddi_prop_op, /* cb_prop_op */ 545 NULL, /* streamtab */ 546 D_MP, /* cb_flag */ 547 CB_REV, /* rev */ 548 nodev, /* aread */ 549 nodev /* awrite */ 550}; 551 552static struct dev_ops mptsas_ops = { 553 DEVO_REV, /* devo_rev, */ 554 0, /* refcnt */ 555 ddi_no_info, /* info */ 556 nulldev, /* identify */ 557 nulldev, /* probe */ 558 mptsas_attach, /* attach */ 559 mptsas_detach, /* detach */ 560#ifdef __sparc 561 mptsas_reset, 562#else 563 nodev, /* reset */ 564#endif /* __sparc */ 565 &mptsas_cb_ops, /* driver operations */ 566 NULL, /* bus operations */ 567 mptsas_power, /* power management */ 568#ifdef __sparc 569 ddi_quiesce_not_needed 570#else 571 mptsas_quiesce /* quiesce */ 572#endif /* __sparc */ 573}; 574 575 576#define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24" 577 578static struct modldrv modldrv = { 579 &mod_driverops, /* Type of module. This one is a driver */ 580 MPTSAS_MOD_STRING, /* Name of the module. */ 581 &mptsas_ops, /* driver ops */ 582}; 583 584static struct modlinkage modlinkage = { 585 MODREV_1, &modldrv, NULL 586}; 587#define TARGET_PROP "target" 588#define LUN_PROP "lun" 589#define LUN64_PROP "lun64" 590#define SAS_PROP "sas-mpt" 591#define MDI_GUID "wwn" 592#define NDI_GUID "guid" 593#define MPTSAS_DEV_GONE "mptsas_dev_gone" 594 595/* 596 * Local static data 597 */ 598#if defined(MPTSAS_DEBUG) 599uint32_t mptsas_debug_flags = 0; 600#endif /* defined(MPTSAS_DEBUG) */ 601uint32_t mptsas_debug_resets = 0; 602 603static kmutex_t mptsas_global_mutex; 604static void *mptsas_state; /* soft state ptr */ 605static krwlock_t mptsas_global_rwlock; 606 607static kmutex_t mptsas_log_mutex; 608static char mptsas_log_buf[256]; 609_NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 610 611static mptsas_t *mptsas_head, *mptsas_tail; 612static clock_t mptsas_scsi_watchdog_tick; 613static clock_t mptsas_tick; 614static timeout_id_t mptsas_reset_watch; 615static timeout_id_t mptsas_timeout_id; 616static int mptsas_timeouts_enabled = 0; 617/* 618 * warlock directives 619 */ 620_NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 621 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 622_NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 623_NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 624_NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 625_NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 626 627/* 628 * SM - HBA statics 629 */ 630char *mptsas_driver_rev = MPTSAS_MOD_STRING; 631 632#ifdef MPTSAS_DEBUG 633void debug_enter(char *); 634#endif 635 636/* 637 * Notes: 638 * - scsi_hba_init(9F) initializes SCSI HBA modules 639 * - must call scsi_hba_fini(9F) if modload() fails 640 */ 641int 642_init(void) 643{ 644 int status; 645 /* CONSTCOND */ 646 ASSERT(NO_COMPETING_THREADS); 647 648 NDBG0(("_init")); 649 650 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 651 MPTSAS_INITIAL_SOFT_SPACE); 652 if (status != 0) { 653 return (status); 654 } 655 656 if ((status = scsi_hba_init(&modlinkage)) != 0) { 657 ddi_soft_state_fini(&mptsas_state); 658 return (status); 659 } 660 661 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 662 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 663 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 664 665 if ((status = mod_install(&modlinkage)) != 0) { 666 mutex_destroy(&mptsas_log_mutex); 667 rw_destroy(&mptsas_global_rwlock); 668 mutex_destroy(&mptsas_global_mutex); 669 ddi_soft_state_fini(&mptsas_state); 670 scsi_hba_fini(&modlinkage); 671 } 672 673 return (status); 674} 675 676/* 677 * Notes: 678 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 679 */ 680int 681_fini(void) 682{ 683 int status; 684 /* CONSTCOND */ 685 ASSERT(NO_COMPETING_THREADS); 686 687 NDBG0(("_fini")); 688 689 if ((status = mod_remove(&modlinkage)) == 0) { 690 ddi_soft_state_fini(&mptsas_state); 691 scsi_hba_fini(&modlinkage); 692 mutex_destroy(&mptsas_global_mutex); 693 rw_destroy(&mptsas_global_rwlock); 694 mutex_destroy(&mptsas_log_mutex); 695 } 696 return (status); 697} 698 699/* 700 * The loadable-module _info(9E) entry point 701 */ 702int 703_info(struct modinfo *modinfop) 704{ 705 /* CONSTCOND */ 706 ASSERT(NO_COMPETING_THREADS); 707 NDBG0(("mptsas _info")); 708 709 return (mod_info(&modlinkage, modinfop)); 710} 711 712 713static int 714mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 715{ 716 dev_info_t *pdip; 717 mptsas_t *mpt; 718 scsi_hba_tran_t *hba_tran; 719 char *iport = NULL; 720 char phymask[MPTSAS_MAX_PHYS]; 721 mptsas_phymask_t phy_mask = 0; 722 int dynamic_port = 0; 723 uint32_t page_address; 724 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 725 int rval = DDI_FAILURE; 726 int i = 0; 727 uint8_t numphys = 0; 728 uint8_t phy_id; 729 uint8_t phy_port = 0; 730 uint16_t attached_devhdl = 0; 731 uint32_t dev_info; 732 uint64_t attached_sas_wwn; 733 uint16_t dev_hdl; 734 uint16_t pdev_hdl; 735 uint16_t bay_num, enclosure; 736 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 737 738 /* CONSTCOND */ 739 ASSERT(NO_COMPETING_THREADS); 740 741 switch (cmd) { 742 case DDI_ATTACH: 743 break; 744 745 case DDI_RESUME: 746 /* 747 * If this a scsi-iport node, nothing to do here. 748 */ 749 return (DDI_SUCCESS); 750 751 default: 752 return (DDI_FAILURE); 753 } 754 755 pdip = ddi_get_parent(dip); 756 757 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 758 NULL) { 759 cmn_err(CE_WARN, "Failed attach iport because fail to " 760 "get tran vector for the HBA node"); 761 return (DDI_FAILURE); 762 } 763 764 mpt = TRAN2MPT(hba_tran); 765 ASSERT(mpt != NULL); 766 if (mpt == NULL) 767 return (DDI_FAILURE); 768 769 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 770 NULL) { 771 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 772 "get tran vector for the iport node"); 773 return (DDI_FAILURE); 774 } 775 776 /* 777 * Overwrite parent's tran_hba_private to iport's tran vector 778 */ 779 hba_tran->tran_hba_private = mpt; 780 781 ddi_report_dev(dip); 782 783 /* 784 * Get SAS address for initiator port according dev_handle 785 */ 786 iport = ddi_get_name_addr(dip); 787 if (iport && strncmp(iport, "v0", 2) == 0) { 788 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 789 MPTSAS_VIRTUAL_PORT, 1) != 790 DDI_PROP_SUCCESS) { 791 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 792 MPTSAS_VIRTUAL_PORT); 793 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 794 "prop update failed"); 795 return (DDI_FAILURE); 796 } 797 return (DDI_SUCCESS); 798 } 799 800 mutex_enter(&mpt->m_mutex); 801 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 802 bzero(phymask, sizeof (phymask)); 803 (void) sprintf(phymask, 804 "%x", mpt->m_phy_info[i].phy_mask); 805 if (strcmp(phymask, iport) == 0) { 806 break; 807 } 808 } 809 810 if (i == MPTSAS_MAX_PHYS) { 811 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 812 "seems not exist", iport); 813 mutex_exit(&mpt->m_mutex); 814 return (DDI_FAILURE); 815 } 816 817 phy_mask = mpt->m_phy_info[i].phy_mask; 818 819 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 820 dynamic_port = 1; 821 else 822 dynamic_port = 0; 823 824 /* 825 * Update PHY info for smhba 826 */ 827 if (mptsas_smhba_phy_init(mpt)) { 828 mutex_exit(&mpt->m_mutex); 829 mptsas_log(mpt, CE_WARN, "mptsas phy update " 830 "failed"); 831 return (DDI_FAILURE); 832 } 833 834 mutex_exit(&mpt->m_mutex); 835 836 numphys = 0; 837 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 838 if ((phy_mask >> i) & 0x01) { 839 numphys++; 840 } 841 } 842 843 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 844 (void) sprintf(initiator_wwnstr, "w%016"PRIx64, 845 mpt->un.m_base_wwid); 846 847 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 848 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) != 849 DDI_PROP_SUCCESS) { 850 (void) ddi_prop_remove(DDI_DEV_T_NONE, 851 dip, SCSI_ADDR_PROP_INITIATOR_PORT); 852 mptsas_log(mpt, CE_WARN, "mptsas Initiator port " 853 "prop update failed"); 854 return (DDI_FAILURE); 855 } 856 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 857 MPTSAS_NUM_PHYS, numphys) != 858 DDI_PROP_SUCCESS) { 859 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS); 860 return (DDI_FAILURE); 861 } 862 863 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 864 "phymask", phy_mask) != 865 DDI_PROP_SUCCESS) { 866 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 867 mptsas_log(mpt, CE_WARN, "mptsas phy mask " 868 "prop update failed"); 869 return (DDI_FAILURE); 870 } 871 872 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 873 "dynamic-port", dynamic_port) != 874 DDI_PROP_SUCCESS) { 875 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 876 mptsas_log(mpt, CE_WARN, "mptsas dynamic port " 877 "prop update failed"); 878 return (DDI_FAILURE); 879 } 880 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 881 MPTSAS_VIRTUAL_PORT, 0) != 882 DDI_PROP_SUCCESS) { 883 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 884 MPTSAS_VIRTUAL_PORT); 885 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 886 "prop update failed"); 887 return (DDI_FAILURE); 888 } 889 mptsas_smhba_set_phy_props(mpt, 890 iport, dip, numphys, &attached_devhdl); 891 892 mutex_enter(&mpt->m_mutex); 893 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 894 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl; 895 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 896 &attached_sas_wwn, &dev_info, &phy_port, &phy_id, 897 &pdev_hdl, &bay_num, &enclosure); 898 if (rval != DDI_SUCCESS) { 899 mptsas_log(mpt, CE_WARN, 900 "Failed to get device page0 for handle:%d", 901 attached_devhdl); 902 mutex_exit(&mpt->m_mutex); 903 return (DDI_FAILURE); 904 } 905 906 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 907 bzero(phymask, sizeof (phymask)); 908 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 909 if (strcmp(phymask, iport) == 0) { 910 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0], 911 "%x", 912 mpt->m_phy_info[i].phy_mask); 913 } 914 } 915 mutex_exit(&mpt->m_mutex); 916 917 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 918 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 919 attached_sas_wwn); 920 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 921 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 922 DDI_PROP_SUCCESS) { 923 (void) ddi_prop_remove(DDI_DEV_T_NONE, 924 dip, SCSI_ADDR_PROP_ATTACHED_PORT); 925 return (DDI_FAILURE); 926 } 927 928 /* Create kstats for each phy on this iport */ 929 930 mptsas_create_phy_stats(mpt, iport, dip); 931 932 /* 933 * register sas hba iport with mdi (MPxIO/vhci) 934 */ 935 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 936 dip, 0) == MDI_SUCCESS) { 937 mpt->m_mpxio_enable = TRUE; 938 } 939 return (DDI_SUCCESS); 940} 941 942/* 943 * Notes: 944 * Set up all device state and allocate data structures, 945 * mutexes, condition variables, etc. for device operation. 946 * Add interrupts needed. 947 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 948 */ 949static int 950mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 951{ 952 mptsas_t *mpt = NULL; 953 int instance, i, j; 954 int doneq_thread_num; 955 char intr_added = 0; 956 char map_setup = 0; 957 char config_setup = 0; 958 char hba_attach_setup = 0; 959 char smp_attach_setup = 0; 960 char mutex_init_done = 0; 961 char event_taskq_create = 0; 962 char dr_taskq_create = 0; 963 char doneq_thread_create = 0; 964 scsi_hba_tran_t *hba_tran; 965 uint_t mem_bar = MEM_SPACE; 966 int rval = DDI_FAILURE; 967 968 /* CONSTCOND */ 969 ASSERT(NO_COMPETING_THREADS); 970 971 if (scsi_hba_iport_unit_address(dip)) { 972 return (mptsas_iport_attach(dip, cmd)); 973 } 974 975 switch (cmd) { 976 case DDI_ATTACH: 977 break; 978 979 case DDI_RESUME: 980 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 981 return (DDI_FAILURE); 982 983 mpt = TRAN2MPT(hba_tran); 984 985 if (!mpt) { 986 return (DDI_FAILURE); 987 } 988 989 /* 990 * Reset hardware and softc to "no outstanding commands" 991 * Note that a check condition can result on first command 992 * to a target. 993 */ 994 mutex_enter(&mpt->m_mutex); 995 996 /* 997 * raise power. 998 */ 999 if (mpt->m_options & MPTSAS_OPT_PM) { 1000 mutex_exit(&mpt->m_mutex); 1001 (void) pm_busy_component(dip, 0); 1002 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0); 1003 if (rval == DDI_SUCCESS) { 1004 mutex_enter(&mpt->m_mutex); 1005 } else { 1006 /* 1007 * The pm_raise_power() call above failed, 1008 * and that can only occur if we were unable 1009 * to reset the hardware. This is probably 1010 * due to unhealty hardware, and because 1011 * important filesystems(such as the root 1012 * filesystem) could be on the attached disks, 1013 * it would not be a good idea to continue, 1014 * as we won't be entirely certain we are 1015 * writing correct data. So we panic() here 1016 * to not only prevent possible data corruption, 1017 * but to give developers or end users a hope 1018 * of identifying and correcting any problems. 1019 */ 1020 fm_panic("mptsas could not reset hardware " 1021 "during resume"); 1022 } 1023 } 1024 1025 mpt->m_suspended = 0; 1026 1027 /* 1028 * Reinitialize ioc 1029 */ 1030 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1031 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 1032 mutex_exit(&mpt->m_mutex); 1033 if (mpt->m_options & MPTSAS_OPT_PM) { 1034 (void) pm_idle_component(dip, 0); 1035 } 1036 fm_panic("mptsas init chip fail during resume"); 1037 } 1038 /* 1039 * mptsas_update_driver_data needs interrupts so enable them 1040 * first. 1041 */ 1042 MPTSAS_ENABLE_INTR(mpt); 1043 mptsas_update_driver_data(mpt); 1044 1045 /* start requests, if possible */ 1046 mptsas_restart_hba(mpt); 1047 1048 mutex_exit(&mpt->m_mutex); 1049 1050 /* 1051 * Restart watch thread 1052 */ 1053 mutex_enter(&mptsas_global_mutex); 1054 if (mptsas_timeout_id == 0) { 1055 mptsas_timeout_id = timeout(mptsas_watch, NULL, 1056 mptsas_tick); 1057 mptsas_timeouts_enabled = 1; 1058 } 1059 mutex_exit(&mptsas_global_mutex); 1060 1061 /* report idle status to pm framework */ 1062 if (mpt->m_options & MPTSAS_OPT_PM) { 1063 (void) pm_idle_component(dip, 0); 1064 } 1065 1066 return (DDI_SUCCESS); 1067 1068 default: 1069 return (DDI_FAILURE); 1070 1071 } 1072 1073 instance = ddi_get_instance(dip); 1074 1075 /* 1076 * Allocate softc information. 1077 */ 1078 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 1079 mptsas_log(NULL, CE_WARN, 1080 "mptsas%d: cannot allocate soft state", instance); 1081 goto fail; 1082 } 1083 1084 mpt = ddi_get_soft_state(mptsas_state, instance); 1085 1086 if (mpt == NULL) { 1087 mptsas_log(NULL, CE_WARN, 1088 "mptsas%d: cannot get soft state", instance); 1089 goto fail; 1090 } 1091 1092 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 1093 scsi_size_clean(dip); 1094 1095 mpt->m_dip = dip; 1096 mpt->m_instance = instance; 1097 1098 /* Make a per-instance copy of the structures */ 1099 mpt->m_io_dma_attr = mptsas_dma_attrs64; 1100 mpt->m_msg_dma_attr = mptsas_dma_attrs; 1101 mpt->m_reg_acc_attr = mptsas_dev_attr; 1102 mpt->m_dev_acc_attr = mptsas_dev_attr; 1103 1104 /* 1105 * Initialize FMA 1106 */ 1107 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 1108 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 1109 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 1110 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1111 1112 mptsas_fm_init(mpt); 1113 1114 if (mptsas_alloc_handshake_msg(mpt, 1115 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 1116 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 1117 goto fail; 1118 } 1119 1120 /* 1121 * Setup configuration space 1122 */ 1123 if (mptsas_config_space_init(mpt) == FALSE) { 1124 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1125 goto fail; 1126 } 1127 config_setup++; 1128 1129 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1130 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1131 mptsas_log(mpt, CE_WARN, "map setup failed"); 1132 goto fail; 1133 } 1134 map_setup++; 1135 1136 /* 1137 * A taskq is created for dealing with the event handler 1138 */ 1139 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1140 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1141 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1142 goto fail; 1143 } 1144 event_taskq_create++; 1145 1146 /* 1147 * A taskq is created for dealing with dr events 1148 */ 1149 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1150 "mptsas_dr_taskq", 1151 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1152 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1153 "failed"); 1154 goto fail; 1155 } 1156 dr_taskq_create++; 1157 1158 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1159 0, "mptsas_doneq_thread_threshold_prop", 10); 1160 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1161 0, "mptsas_doneq_length_threshold_prop", 8); 1162 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1163 0, "mptsas_doneq_thread_n_prop", 8); 1164 1165 if (mpt->m_doneq_thread_n) { 1166 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1167 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1168 1169 mutex_enter(&mpt->m_doneq_mutex); 1170 mpt->m_doneq_thread_id = 1171 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1172 * mpt->m_doneq_thread_n, KM_SLEEP); 1173 1174 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1175 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1176 CV_DRIVER, NULL); 1177 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1178 MUTEX_DRIVER, NULL); 1179 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1180 mpt->m_doneq_thread_id[j].flag |= 1181 MPTSAS_DONEQ_THREAD_ACTIVE; 1182 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1183 mpt->m_doneq_thread_id[j].arg.t = j; 1184 mpt->m_doneq_thread_id[j].threadp = 1185 thread_create(NULL, 0, mptsas_doneq_thread, 1186 &mpt->m_doneq_thread_id[j].arg, 1187 0, &p0, TS_RUN, minclsyspri); 1188 mpt->m_doneq_thread_id[j].donetail = 1189 &mpt->m_doneq_thread_id[j].doneq; 1190 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1191 } 1192 mutex_exit(&mpt->m_doneq_mutex); 1193 doneq_thread_create++; 1194 } 1195 1196 /* Initialize mutex used in interrupt handler */ 1197 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1198 DDI_INTR_PRI(mpt->m_intr_pri)); 1199 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL); 1200 mutex_init(&mpt->m_intr_mutex, NULL, MUTEX_DRIVER, 1201 DDI_INTR_PRI(mpt->m_intr_pri)); 1202 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1203 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex, 1204 NULL, MUTEX_DRIVER, 1205 DDI_INTR_PRI(mpt->m_intr_pri)); 1206 } 1207 1208 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1209 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1210 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1211 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1212 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1213 mutex_init_done++; 1214 1215 /* 1216 * Disable hardware interrupt since we're not ready to 1217 * handle it yet. 1218 */ 1219 MPTSAS_DISABLE_INTR(mpt); 1220 if (mptsas_register_intrs(mpt) == FALSE) 1221 goto fail; 1222 intr_added++; 1223 1224 mutex_enter(&mpt->m_mutex); 1225 /* 1226 * Initialize power management component 1227 */ 1228 if (mpt->m_options & MPTSAS_OPT_PM) { 1229 if (mptsas_init_pm(mpt)) { 1230 mutex_exit(&mpt->m_mutex); 1231 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1232 "failed"); 1233 goto fail; 1234 } 1235 } 1236 1237 /* 1238 * Initialize chip using Message Unit Reset, if allowed 1239 */ 1240 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1241 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1242 mutex_exit(&mpt->m_mutex); 1243 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1244 goto fail; 1245 } 1246 1247 /* 1248 * Fill in the phy_info structure and get the base WWID 1249 */ 1250 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 1251 mptsas_log(mpt, CE_WARN, 1252 "mptsas_get_manufacture_page5 failed!"); 1253 goto fail; 1254 } 1255 1256 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 1257 mptsas_log(mpt, CE_WARN, 1258 "mptsas_get_sas_io_unit_page_hndshk failed!"); 1259 goto fail; 1260 } 1261 1262 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) { 1263 mptsas_log(mpt, CE_WARN, 1264 "mptsas_get_manufacture_page0 failed!"); 1265 goto fail; 1266 } 1267 1268 mutex_exit(&mpt->m_mutex); 1269 1270 /* 1271 * Register the iport for multiple port HBA 1272 */ 1273 mptsas_iport_register(mpt); 1274 1275 /* 1276 * initialize SCSI HBA transport structure 1277 */ 1278 if (mptsas_hba_setup(mpt) == FALSE) 1279 goto fail; 1280 hba_attach_setup++; 1281 1282 if (mptsas_smp_setup(mpt) == FALSE) 1283 goto fail; 1284 smp_attach_setup++; 1285 1286 if (mptsas_cache_create(mpt) == FALSE) 1287 goto fail; 1288 1289 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1290 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1291 if (mpt->m_scsi_reset_delay == 0) { 1292 mptsas_log(mpt, CE_NOTE, 1293 "scsi_reset_delay of 0 is not recommended," 1294 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1295 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1296 } 1297 1298 /* 1299 * Initialize the wait and done FIFO queue 1300 */ 1301 mpt->m_donetail = &mpt->m_doneq; 1302 mpt->m_waitqtail = &mpt->m_waitq; 1303 1304 /* 1305 * ioc cmd queue initialize 1306 */ 1307 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1308 mpt->m_dev_handle = 0xFFFF; 1309 1310 MPTSAS_ENABLE_INTR(mpt); 1311 1312 /* 1313 * enable event notification 1314 */ 1315 mutex_enter(&mpt->m_mutex); 1316 if (mptsas_ioc_enable_event_notification(mpt)) { 1317 mutex_exit(&mpt->m_mutex); 1318 goto fail; 1319 } 1320 mutex_exit(&mpt->m_mutex); 1321 1322 /* 1323 * Initialize PHY info for smhba 1324 */ 1325 if (mptsas_smhba_setup(mpt)) { 1326 mptsas_log(mpt, CE_WARN, "mptsas phy initialization " 1327 "failed"); 1328 goto fail; 1329 } 1330 1331 /* Check all dma handles allocated in attach */ 1332 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1333 != DDI_SUCCESS) || 1334 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1335 != DDI_SUCCESS) || 1336 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1337 != DDI_SUCCESS) || 1338 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1339 != DDI_SUCCESS) || 1340 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1341 != DDI_SUCCESS)) { 1342 goto fail; 1343 } 1344 1345 /* Check all acc handles allocated in attach */ 1346 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1347 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1348 != DDI_SUCCESS) || 1349 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1350 != DDI_SUCCESS) || 1351 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1352 != DDI_SUCCESS) || 1353 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1354 != DDI_SUCCESS) || 1355 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1356 != DDI_SUCCESS) || 1357 (mptsas_check_acc_handle(mpt->m_config_handle) 1358 != DDI_SUCCESS)) { 1359 goto fail; 1360 } 1361 1362 /* 1363 * After this point, we are not going to fail the attach. 1364 */ 1365 /* 1366 * used for mptsas_watch 1367 */ 1368 mptsas_list_add(mpt); 1369 1370 mutex_enter(&mptsas_global_mutex); 1371 if (mptsas_timeouts_enabled == 0) { 1372 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1373 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1374 1375 mptsas_tick = mptsas_scsi_watchdog_tick * 1376 drv_usectohz((clock_t)1000000); 1377 1378 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1379 mptsas_timeouts_enabled = 1; 1380 } 1381 mutex_exit(&mptsas_global_mutex); 1382 1383 /* Print message of HBA present */ 1384 ddi_report_dev(dip); 1385 1386 /* report idle status to pm framework */ 1387 if (mpt->m_options & MPTSAS_OPT_PM) { 1388 (void) pm_idle_component(dip, 0); 1389 } 1390 1391 return (DDI_SUCCESS); 1392 1393fail: 1394 mptsas_log(mpt, CE_WARN, "attach failed"); 1395 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1396 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1397 if (mpt) { 1398 mutex_enter(&mptsas_global_mutex); 1399 1400 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1401 timeout_id_t tid = mptsas_timeout_id; 1402 mptsas_timeouts_enabled = 0; 1403 mptsas_timeout_id = 0; 1404 mutex_exit(&mptsas_global_mutex); 1405 (void) untimeout(tid); 1406 mutex_enter(&mptsas_global_mutex); 1407 } 1408 mutex_exit(&mptsas_global_mutex); 1409 /* deallocate in reverse order */ 1410 mptsas_cache_destroy(mpt); 1411 1412 if (smp_attach_setup) { 1413 mptsas_smp_teardown(mpt); 1414 } 1415 if (hba_attach_setup) { 1416 mptsas_hba_teardown(mpt); 1417 } 1418 1419 if (mpt->m_active) { 1420 mptsas_hash_uninit(&mpt->m_active->m_smptbl, 1421 sizeof (mptsas_smp_t)); 1422 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, 1423 sizeof (mptsas_target_t)); 1424 mptsas_free_active_slots(mpt); 1425 } 1426 if (intr_added) { 1427 mptsas_unregister_intrs(mpt); 1428 } 1429 1430 if (doneq_thread_create) { 1431 mutex_enter(&mpt->m_doneq_mutex); 1432 doneq_thread_num = mpt->m_doneq_thread_n; 1433 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1434 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1435 mpt->m_doneq_thread_id[j].flag &= 1436 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1437 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1438 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1439 } 1440 while (mpt->m_doneq_thread_n) { 1441 cv_wait(&mpt->m_doneq_thread_cv, 1442 &mpt->m_doneq_mutex); 1443 } 1444 for (j = 0; j < doneq_thread_num; j++) { 1445 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1446 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1447 } 1448 kmem_free(mpt->m_doneq_thread_id, 1449 sizeof (mptsas_doneq_thread_list_t) 1450 * doneq_thread_num); 1451 mutex_exit(&mpt->m_doneq_mutex); 1452 cv_destroy(&mpt->m_doneq_thread_cv); 1453 mutex_destroy(&mpt->m_doneq_mutex); 1454 } 1455 if (event_taskq_create) { 1456 ddi_taskq_destroy(mpt->m_event_taskq); 1457 } 1458 if (dr_taskq_create) { 1459 ddi_taskq_destroy(mpt->m_dr_taskq); 1460 } 1461 if (mutex_init_done) { 1462 mutex_destroy(&mpt->m_intr_mutex); 1463 mutex_destroy(&mpt->m_passthru_mutex); 1464 mutex_destroy(&mpt->m_mutex); 1465 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1466 mutex_destroy( 1467 &mpt->m_phy_info[i].smhba_info.phy_mutex); 1468 } 1469 cv_destroy(&mpt->m_cv); 1470 cv_destroy(&mpt->m_passthru_cv); 1471 cv_destroy(&mpt->m_fw_cv); 1472 cv_destroy(&mpt->m_config_cv); 1473 cv_destroy(&mpt->m_fw_diag_cv); 1474 } 1475 1476 if (map_setup) { 1477 mptsas_cfg_fini(mpt); 1478 } 1479 if (config_setup) { 1480 mptsas_config_space_fini(mpt); 1481 } 1482 mptsas_free_handshake_msg(mpt); 1483 mptsas_hba_fini(mpt); 1484 1485 mptsas_fm_fini(mpt); 1486 ddi_soft_state_free(mptsas_state, instance); 1487 ddi_prop_remove_all(dip); 1488 } 1489 return (DDI_FAILURE); 1490} 1491 1492static int 1493mptsas_suspend(dev_info_t *devi) 1494{ 1495 mptsas_t *mpt, *g; 1496 scsi_hba_tran_t *tran; 1497 1498 if (scsi_hba_iport_unit_address(devi)) { 1499 return (DDI_SUCCESS); 1500 } 1501 1502 if ((tran = ddi_get_driver_private(devi)) == NULL) 1503 return (DDI_SUCCESS); 1504 1505 mpt = TRAN2MPT(tran); 1506 if (!mpt) { 1507 return (DDI_SUCCESS); 1508 } 1509 1510 mutex_enter(&mpt->m_mutex); 1511 1512 if (mpt->m_suspended++) { 1513 mutex_exit(&mpt->m_mutex); 1514 return (DDI_SUCCESS); 1515 } 1516 1517 /* 1518 * Cancel timeout threads for this mpt 1519 */ 1520 if (mpt->m_quiesce_timeid) { 1521 timeout_id_t tid = mpt->m_quiesce_timeid; 1522 mpt->m_quiesce_timeid = 0; 1523 mutex_exit(&mpt->m_mutex); 1524 (void) untimeout(tid); 1525 mutex_enter(&mpt->m_mutex); 1526 } 1527 1528 if (mpt->m_restart_cmd_timeid) { 1529 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1530 mpt->m_restart_cmd_timeid = 0; 1531 mutex_exit(&mpt->m_mutex); 1532 (void) untimeout(tid); 1533 mutex_enter(&mpt->m_mutex); 1534 } 1535 1536 mutex_exit(&mpt->m_mutex); 1537 1538 (void) pm_idle_component(mpt->m_dip, 0); 1539 1540 /* 1541 * Cancel watch threads if all mpts suspended 1542 */ 1543 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1544 for (g = mptsas_head; g != NULL; g = g->m_next) { 1545 if (!g->m_suspended) 1546 break; 1547 } 1548 rw_exit(&mptsas_global_rwlock); 1549 1550 mutex_enter(&mptsas_global_mutex); 1551 if (g == NULL) { 1552 timeout_id_t tid; 1553 1554 mptsas_timeouts_enabled = 0; 1555 if (mptsas_timeout_id) { 1556 tid = mptsas_timeout_id; 1557 mptsas_timeout_id = 0; 1558 mutex_exit(&mptsas_global_mutex); 1559 (void) untimeout(tid); 1560 mutex_enter(&mptsas_global_mutex); 1561 } 1562 if (mptsas_reset_watch) { 1563 tid = mptsas_reset_watch; 1564 mptsas_reset_watch = 0; 1565 mutex_exit(&mptsas_global_mutex); 1566 (void) untimeout(tid); 1567 mutex_enter(&mptsas_global_mutex); 1568 } 1569 } 1570 mutex_exit(&mptsas_global_mutex); 1571 1572 mutex_enter(&mpt->m_mutex); 1573 1574 /* 1575 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1576 */ 1577 if ((mpt->m_options & MPTSAS_OPT_PM) && 1578 (mpt->m_power_level != PM_LEVEL_D0)) { 1579 mutex_exit(&mpt->m_mutex); 1580 return (DDI_SUCCESS); 1581 } 1582 1583 /* Disable HBA interrupts in hardware */ 1584 MPTSAS_DISABLE_INTR(mpt); 1585 /* 1586 * Send RAID action system shutdown to sync IR 1587 */ 1588 mptsas_raid_action_system_shutdown(mpt); 1589 1590 mutex_exit(&mpt->m_mutex); 1591 1592 /* drain the taskq */ 1593 ddi_taskq_wait(mpt->m_event_taskq); 1594 ddi_taskq_wait(mpt->m_dr_taskq); 1595 1596 return (DDI_SUCCESS); 1597} 1598 1599#ifdef __sparc 1600/*ARGSUSED*/ 1601static int 1602mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1603{ 1604 mptsas_t *mpt; 1605 scsi_hba_tran_t *tran; 1606 1607 /* 1608 * If this call is for iport, just return. 1609 */ 1610 if (scsi_hba_iport_unit_address(devi)) 1611 return (DDI_SUCCESS); 1612 1613 if ((tran = ddi_get_driver_private(devi)) == NULL) 1614 return (DDI_SUCCESS); 1615 1616 if ((mpt = TRAN2MPT(tran)) == NULL) 1617 return (DDI_SUCCESS); 1618 1619 /* 1620 * Send RAID action system shutdown to sync IR. Disable HBA 1621 * interrupts in hardware first. 1622 */ 1623 MPTSAS_DISABLE_INTR(mpt); 1624 mptsas_raid_action_system_shutdown(mpt); 1625 1626 return (DDI_SUCCESS); 1627} 1628#else /* __sparc */ 1629/* 1630 * quiesce(9E) entry point. 1631 * 1632 * This function is called when the system is single-threaded at high 1633 * PIL with preemption disabled. Therefore, this function must not be 1634 * blocked. 1635 * 1636 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1637 * DDI_FAILURE indicates an error condition and should almost never happen. 1638 */ 1639static int 1640mptsas_quiesce(dev_info_t *devi) 1641{ 1642 mptsas_t *mpt; 1643 scsi_hba_tran_t *tran; 1644 1645 /* 1646 * If this call is for iport, just return. 1647 */ 1648 if (scsi_hba_iport_unit_address(devi)) 1649 return (DDI_SUCCESS); 1650 1651 if ((tran = ddi_get_driver_private(devi)) == NULL) 1652 return (DDI_SUCCESS); 1653 1654 if ((mpt = TRAN2MPT(tran)) == NULL) 1655 return (DDI_SUCCESS); 1656 1657 /* Disable HBA interrupts in hardware */ 1658 MPTSAS_DISABLE_INTR(mpt); 1659 /* Send RAID action system shutdonw to sync IR */ 1660 mptsas_raid_action_system_shutdown(mpt); 1661 1662 return (DDI_SUCCESS); 1663} 1664#endif /* __sparc */ 1665 1666/* 1667 * detach(9E). Remove all device allocations and system resources; 1668 * disable device interrupts. 1669 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1670 */ 1671static int 1672mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1673{ 1674 /* CONSTCOND */ 1675 ASSERT(NO_COMPETING_THREADS); 1676 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1677 1678 switch (cmd) { 1679 case DDI_DETACH: 1680 return (mptsas_do_detach(devi)); 1681 1682 case DDI_SUSPEND: 1683 return (mptsas_suspend(devi)); 1684 1685 default: 1686 return (DDI_FAILURE); 1687 } 1688 /* NOTREACHED */ 1689} 1690 1691static int 1692mptsas_do_detach(dev_info_t *dip) 1693{ 1694 mptsas_t *mpt; 1695 scsi_hba_tran_t *tran; 1696 int circ = 0; 1697 int circ1 = 0; 1698 mdi_pathinfo_t *pip = NULL; 1699 int i; 1700 int doneq_thread_num = 0; 1701 1702 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1703 1704 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1705 return (DDI_FAILURE); 1706 1707 mpt = TRAN2MPT(tran); 1708 if (!mpt) { 1709 return (DDI_FAILURE); 1710 } 1711 /* 1712 * Still have pathinfo child, should not detach mpt driver 1713 */ 1714 if (scsi_hba_iport_unit_address(dip)) { 1715 if (mpt->m_mpxio_enable) { 1716 /* 1717 * MPxIO enabled for the iport 1718 */ 1719 ndi_devi_enter(scsi_vhci_dip, &circ1); 1720 ndi_devi_enter(dip, &circ); 1721 while (pip = mdi_get_next_client_path(dip, NULL)) { 1722 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1723 continue; 1724 } 1725 ndi_devi_exit(dip, circ); 1726 ndi_devi_exit(scsi_vhci_dip, circ1); 1727 NDBG12(("detach failed because of " 1728 "outstanding path info")); 1729 return (DDI_FAILURE); 1730 } 1731 ndi_devi_exit(dip, circ); 1732 ndi_devi_exit(scsi_vhci_dip, circ1); 1733 (void) mdi_phci_unregister(dip, 0); 1734 } 1735 1736 ddi_prop_remove_all(dip); 1737 1738 return (DDI_SUCCESS); 1739 } 1740 1741 /* Make sure power level is D0 before accessing registers */ 1742 if (mpt->m_options & MPTSAS_OPT_PM) { 1743 (void) pm_busy_component(dip, 0); 1744 if (mpt->m_power_level != PM_LEVEL_D0) { 1745 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1746 DDI_SUCCESS) { 1747 mptsas_log(mpt, CE_WARN, 1748 "mptsas%d: Raise power request failed.", 1749 mpt->m_instance); 1750 (void) pm_idle_component(dip, 0); 1751 return (DDI_FAILURE); 1752 } 1753 } 1754 } 1755 1756 /* 1757 * Send RAID action system shutdown to sync IR. After action, send a 1758 * Message Unit Reset. Since after that DMA resource will be freed, 1759 * set ioc to READY state will avoid HBA initiated DMA operation. 1760 */ 1761 mutex_enter(&mpt->m_mutex); 1762 MPTSAS_DISABLE_INTR(mpt); 1763 mptsas_raid_action_system_shutdown(mpt); 1764 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1765 (void) mptsas_ioc_reset(mpt, FALSE); 1766 mutex_exit(&mpt->m_mutex); 1767 mptsas_rem_intrs(mpt); 1768 ddi_taskq_destroy(mpt->m_event_taskq); 1769 ddi_taskq_destroy(mpt->m_dr_taskq); 1770 1771 if (mpt->m_doneq_thread_n) { 1772 mutex_enter(&mpt->m_doneq_mutex); 1773 doneq_thread_num = mpt->m_doneq_thread_n; 1774 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1775 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1776 mpt->m_doneq_thread_id[i].flag &= 1777 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1778 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1779 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1780 } 1781 while (mpt->m_doneq_thread_n) { 1782 cv_wait(&mpt->m_doneq_thread_cv, 1783 &mpt->m_doneq_mutex); 1784 } 1785 for (i = 0; i < doneq_thread_num; i++) { 1786 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1787 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1788 } 1789 kmem_free(mpt->m_doneq_thread_id, 1790 sizeof (mptsas_doneq_thread_list_t) 1791 * doneq_thread_num); 1792 mutex_exit(&mpt->m_doneq_mutex); 1793 cv_destroy(&mpt->m_doneq_thread_cv); 1794 mutex_destroy(&mpt->m_doneq_mutex); 1795 } 1796 1797 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1798 1799 mptsas_list_del(mpt); 1800 1801 /* 1802 * Cancel timeout threads for this mpt 1803 */ 1804 mutex_enter(&mpt->m_mutex); 1805 if (mpt->m_quiesce_timeid) { 1806 timeout_id_t tid = mpt->m_quiesce_timeid; 1807 mpt->m_quiesce_timeid = 0; 1808 mutex_exit(&mpt->m_mutex); 1809 (void) untimeout(tid); 1810 mutex_enter(&mpt->m_mutex); 1811 } 1812 1813 if (mpt->m_restart_cmd_timeid) { 1814 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1815 mpt->m_restart_cmd_timeid = 0; 1816 mutex_exit(&mpt->m_mutex); 1817 (void) untimeout(tid); 1818 mutex_enter(&mpt->m_mutex); 1819 } 1820 1821 mutex_exit(&mpt->m_mutex); 1822 1823 /* 1824 * last mpt? ... if active, CANCEL watch threads. 1825 */ 1826 mutex_enter(&mptsas_global_mutex); 1827 if (mptsas_head == NULL) { 1828 timeout_id_t tid; 1829 /* 1830 * Clear mptsas_timeouts_enable so that the watch thread 1831 * gets restarted on DDI_ATTACH 1832 */ 1833 mptsas_timeouts_enabled = 0; 1834 if (mptsas_timeout_id) { 1835 tid = mptsas_timeout_id; 1836 mptsas_timeout_id = 0; 1837 mutex_exit(&mptsas_global_mutex); 1838 (void) untimeout(tid); 1839 mutex_enter(&mptsas_global_mutex); 1840 } 1841 if (mptsas_reset_watch) { 1842 tid = mptsas_reset_watch; 1843 mptsas_reset_watch = 0; 1844 mutex_exit(&mptsas_global_mutex); 1845 (void) untimeout(tid); 1846 mutex_enter(&mptsas_global_mutex); 1847 } 1848 } 1849 mutex_exit(&mptsas_global_mutex); 1850 1851 /* 1852 * Delete Phy stats 1853 */ 1854 mptsas_destroy_phy_stats(mpt); 1855 1856 /* 1857 * Delete nt_active. 1858 */ 1859 mutex_enter(&mpt->m_mutex); 1860 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, sizeof (mptsas_target_t)); 1861 mptsas_hash_uninit(&mpt->m_active->m_smptbl, sizeof (mptsas_smp_t)); 1862 mptsas_free_active_slots(mpt); 1863 mutex_exit(&mpt->m_mutex); 1864 1865 /* deallocate everything that was allocated in mptsas_attach */ 1866 mptsas_cache_destroy(mpt); 1867 1868 mptsas_hba_fini(mpt); 1869 mptsas_cfg_fini(mpt); 1870 1871 /* Lower the power informing PM Framework */ 1872 if (mpt->m_options & MPTSAS_OPT_PM) { 1873 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 1874 mptsas_log(mpt, CE_WARN, 1875 "!mptsas%d: Lower power request failed " 1876 "during detach, ignoring.", 1877 mpt->m_instance); 1878 } 1879 1880 mutex_destroy(&mpt->m_intr_mutex); 1881 mutex_destroy(&mpt->m_passthru_mutex); 1882 mutex_destroy(&mpt->m_mutex); 1883 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1884 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex); 1885 } 1886 cv_destroy(&mpt->m_cv); 1887 cv_destroy(&mpt->m_passthru_cv); 1888 cv_destroy(&mpt->m_fw_cv); 1889 cv_destroy(&mpt->m_config_cv); 1890 cv_destroy(&mpt->m_fw_diag_cv); 1891 1892 1893 mptsas_smp_teardown(mpt); 1894 mptsas_hba_teardown(mpt); 1895 1896 mptsas_config_space_fini(mpt); 1897 1898 mptsas_free_handshake_msg(mpt); 1899 1900 mptsas_fm_fini(mpt); 1901 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 1902 ddi_prop_remove_all(dip); 1903 1904 return (DDI_SUCCESS); 1905} 1906 1907static void 1908mptsas_list_add(mptsas_t *mpt) 1909{ 1910 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1911 1912 if (mptsas_head == NULL) { 1913 mptsas_head = mpt; 1914 } else { 1915 mptsas_tail->m_next = mpt; 1916 } 1917 mptsas_tail = mpt; 1918 rw_exit(&mptsas_global_rwlock); 1919} 1920 1921static void 1922mptsas_list_del(mptsas_t *mpt) 1923{ 1924 mptsas_t *m; 1925 /* 1926 * Remove device instance from the global linked list 1927 */ 1928 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1929 if (mptsas_head == mpt) { 1930 m = mptsas_head = mpt->m_next; 1931 } else { 1932 for (m = mptsas_head; m != NULL; m = m->m_next) { 1933 if (m->m_next == mpt) { 1934 m->m_next = mpt->m_next; 1935 break; 1936 } 1937 } 1938 if (m == NULL) { 1939 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 1940 } 1941 } 1942 1943 if (mptsas_tail == mpt) { 1944 mptsas_tail = m; 1945 } 1946 rw_exit(&mptsas_global_rwlock); 1947} 1948 1949static int 1950mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 1951{ 1952 ddi_dma_attr_t task_dma_attrs; 1953 1954 task_dma_attrs = mpt->m_msg_dma_attr; 1955 task_dma_attrs.dma_attr_sgllen = 1; 1956 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 1957 1958 /* allocate Task Management ddi_dma resources */ 1959 if (mptsas_dma_addr_create(mpt, task_dma_attrs, 1960 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp, 1961 alloc_size, NULL) == FALSE) { 1962 return (DDI_FAILURE); 1963 } 1964 mpt->m_hshk_dma_size = alloc_size; 1965 1966 return (DDI_SUCCESS); 1967} 1968 1969static void 1970mptsas_free_handshake_msg(mptsas_t *mpt) 1971{ 1972 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl); 1973 mpt->m_hshk_dma_size = 0; 1974} 1975 1976static int 1977mptsas_hba_setup(mptsas_t *mpt) 1978{ 1979 scsi_hba_tran_t *hba_tran; 1980 int tran_flags; 1981 1982 /* Allocate a transport structure */ 1983 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip, 1984 SCSI_HBA_CANSLEEP); 1985 ASSERT(mpt->m_tran != NULL); 1986 1987 hba_tran->tran_hba_private = mpt; 1988 hba_tran->tran_tgt_private = NULL; 1989 1990 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 1991 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 1992 1993 hba_tran->tran_start = mptsas_scsi_start; 1994 hba_tran->tran_reset = mptsas_scsi_reset; 1995 hba_tran->tran_abort = mptsas_scsi_abort; 1996 hba_tran->tran_getcap = mptsas_scsi_getcap; 1997 hba_tran->tran_setcap = mptsas_scsi_setcap; 1998 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 1999 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 2000 2001 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 2002 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 2003 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 2004 2005 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 2006 hba_tran->tran_get_name = mptsas_get_name; 2007 2008 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 2009 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 2010 hba_tran->tran_bus_reset = NULL; 2011 2012 hba_tran->tran_add_eventcall = NULL; 2013 hba_tran->tran_get_eventcookie = NULL; 2014 hba_tran->tran_post_event = NULL; 2015 hba_tran->tran_remove_eventcall = NULL; 2016 2017 hba_tran->tran_bus_config = mptsas_bus_config; 2018 2019 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 2020 2021 /* 2022 * All children of the HBA are iports. We need tran was cloned. 2023 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 2024 * inherited to iport's tran vector. 2025 */ 2026 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 2027 2028 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr, 2029 hba_tran, tran_flags) != DDI_SUCCESS) { 2030 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 2031 scsi_hba_tran_free(hba_tran); 2032 mpt->m_tran = NULL; 2033 return (FALSE); 2034 } 2035 return (TRUE); 2036} 2037 2038static void 2039mptsas_hba_teardown(mptsas_t *mpt) 2040{ 2041 (void) scsi_hba_detach(mpt->m_dip); 2042 if (mpt->m_tran != NULL) { 2043 scsi_hba_tran_free(mpt->m_tran); 2044 mpt->m_tran = NULL; 2045 } 2046} 2047 2048static void 2049mptsas_iport_register(mptsas_t *mpt) 2050{ 2051 int i, j; 2052 mptsas_phymask_t mask = 0x0; 2053 /* 2054 * initial value of mask is 0 2055 */ 2056 mutex_enter(&mpt->m_mutex); 2057 for (i = 0; i < mpt->m_num_phys; i++) { 2058 mptsas_phymask_t phy_mask = 0x0; 2059 char phy_mask_name[MPTSAS_MAX_PHYS]; 2060 uint8_t current_port; 2061 2062 if (mpt->m_phy_info[i].attached_devhdl == 0) 2063 continue; 2064 2065 bzero(phy_mask_name, sizeof (phy_mask_name)); 2066 2067 current_port = mpt->m_phy_info[i].port_num; 2068 2069 if ((mask & (1 << i)) != 0) 2070 continue; 2071 2072 for (j = 0; j < mpt->m_num_phys; j++) { 2073 if (mpt->m_phy_info[j].attached_devhdl && 2074 (mpt->m_phy_info[j].port_num == current_port)) { 2075 phy_mask |= (1 << j); 2076 } 2077 } 2078 mask = mask | phy_mask; 2079 2080 for (j = 0; j < mpt->m_num_phys; j++) { 2081 if ((phy_mask >> j) & 0x01) { 2082 mpt->m_phy_info[j].phy_mask = phy_mask; 2083 } 2084 } 2085 2086 (void) sprintf(phy_mask_name, "%x", phy_mask); 2087 2088 mutex_exit(&mpt->m_mutex); 2089 /* 2090 * register a iport 2091 */ 2092 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 2093 mutex_enter(&mpt->m_mutex); 2094 } 2095 mutex_exit(&mpt->m_mutex); 2096 /* 2097 * register a virtual port for RAID volume always 2098 */ 2099 (void) scsi_hba_iport_register(mpt->m_dip, "v0"); 2100 2101} 2102 2103static int 2104mptsas_smp_setup(mptsas_t *mpt) 2105{ 2106 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip); 2107 ASSERT(mpt->m_smptran != NULL); 2108 mpt->m_smptran->smp_tran_hba_private = mpt; 2109 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 2110 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) { 2111 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 2112 smp_hba_tran_free(mpt->m_smptran); 2113 mpt->m_smptran = NULL; 2114 return (FALSE); 2115 } 2116 /* 2117 * Initialize smp hash table 2118 */ 2119 mptsas_hash_init(&mpt->m_active->m_smptbl); 2120 mpt->m_smp_devhdl = 0xFFFF; 2121 2122 return (TRUE); 2123} 2124 2125static void 2126mptsas_smp_teardown(mptsas_t *mpt) 2127{ 2128 (void) smp_hba_detach(mpt->m_dip); 2129 if (mpt->m_smptran != NULL) { 2130 smp_hba_tran_free(mpt->m_smptran); 2131 mpt->m_smptran = NULL; 2132 } 2133 mpt->m_smp_devhdl = 0; 2134} 2135 2136static int 2137mptsas_cache_create(mptsas_t *mpt) 2138{ 2139 int instance = mpt->m_instance; 2140 char buf[64]; 2141 2142 /* 2143 * create kmem cache for packets 2144 */ 2145 (void) sprintf(buf, "mptsas%d_cache", instance); 2146 mpt->m_kmem_cache = kmem_cache_create(buf, 2147 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 2148 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 2149 NULL, (void *)mpt, NULL, 0); 2150 2151 if (mpt->m_kmem_cache == NULL) { 2152 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 2153 return (FALSE); 2154 } 2155 2156 /* 2157 * create kmem cache for extra SGL frames if SGL cannot 2158 * be accomodated into main request frame. 2159 */ 2160 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 2161 mpt->m_cache_frames = kmem_cache_create(buf, 2162 sizeof (mptsas_cache_frames_t), 8, 2163 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 2164 NULL, (void *)mpt, NULL, 0); 2165 2166 if (mpt->m_cache_frames == NULL) { 2167 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 2168 return (FALSE); 2169 } 2170 2171 return (TRUE); 2172} 2173 2174static void 2175mptsas_cache_destroy(mptsas_t *mpt) 2176{ 2177 /* deallocate in reverse order */ 2178 if (mpt->m_cache_frames) { 2179 kmem_cache_destroy(mpt->m_cache_frames); 2180 mpt->m_cache_frames = NULL; 2181 } 2182 if (mpt->m_kmem_cache) { 2183 kmem_cache_destroy(mpt->m_kmem_cache); 2184 mpt->m_kmem_cache = NULL; 2185 } 2186} 2187 2188static int 2189mptsas_power(dev_info_t *dip, int component, int level) 2190{ 2191#ifndef __lock_lint 2192 _NOTE(ARGUNUSED(component)) 2193#endif 2194 mptsas_t *mpt; 2195 int rval = DDI_SUCCESS; 2196 int polls = 0; 2197 uint32_t ioc_status; 2198 2199 if (scsi_hba_iport_unit_address(dip) != 0) 2200 return (DDI_SUCCESS); 2201 2202 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2203 if (mpt == NULL) { 2204 return (DDI_FAILURE); 2205 } 2206 2207 mutex_enter(&mpt->m_mutex); 2208 2209 /* 2210 * If the device is busy, don't lower its power level 2211 */ 2212 if (mpt->m_busy && (mpt->m_power_level > level)) { 2213 mutex_exit(&mpt->m_mutex); 2214 return (DDI_FAILURE); 2215 } 2216 switch (level) { 2217 case PM_LEVEL_D0: 2218 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2219 MPTSAS_POWER_ON(mpt); 2220 /* 2221 * Wait up to 30 seconds for IOC to come out of reset. 2222 */ 2223 while (((ioc_status = ddi_get32(mpt->m_datap, 2224 &mpt->m_reg->Doorbell)) & 2225 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2226 if (polls++ > 3000) { 2227 break; 2228 } 2229 delay(drv_usectohz(10000)); 2230 } 2231 /* 2232 * If IOC is not in operational state, try to hard reset it. 2233 */ 2234 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2235 MPI2_IOC_STATE_OPERATIONAL) { 2236 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 2237 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2238 mptsas_log(mpt, CE_WARN, 2239 "mptsas_power: hard reset failed"); 2240 mutex_exit(&mpt->m_mutex); 2241 return (DDI_FAILURE); 2242 } 2243 } 2244 mutex_enter(&mpt->m_intr_mutex); 2245 mpt->m_power_level = PM_LEVEL_D0; 2246 mutex_exit(&mpt->m_intr_mutex); 2247 break; 2248 case PM_LEVEL_D3: 2249 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2250 MPTSAS_POWER_OFF(mpt); 2251 break; 2252 default: 2253 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2254 mpt->m_instance, level); 2255 rval = DDI_FAILURE; 2256 break; 2257 } 2258 mutex_exit(&mpt->m_mutex); 2259 return (rval); 2260} 2261 2262/* 2263 * Initialize configuration space and figure out which 2264 * chip and revison of the chip the mpt driver is using. 2265 */ 2266static int 2267mptsas_config_space_init(mptsas_t *mpt) 2268{ 2269 NDBG0(("mptsas_config_space_init")); 2270 2271 if (mpt->m_config_handle != NULL) 2272 return (TRUE); 2273 2274 if (pci_config_setup(mpt->m_dip, 2275 &mpt->m_config_handle) != DDI_SUCCESS) { 2276 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 2277 return (FALSE); 2278 } 2279 2280 /* 2281 * This is a workaround for a XMITS ASIC bug which does not 2282 * drive the CBE upper bits. 2283 */ 2284 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 2285 PCI_STAT_PERROR) { 2286 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 2287 PCI_STAT_PERROR); 2288 } 2289 2290 mptsas_setup_cmd_reg(mpt); 2291 2292 /* 2293 * Get the chip device id: 2294 */ 2295 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2296 2297 /* 2298 * Save the revision. 2299 */ 2300 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2301 2302 /* 2303 * Save the SubSystem Vendor and Device IDs 2304 */ 2305 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2306 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2307 2308 /* 2309 * Set the latency timer to 0x40 as specified by the upa -> pci 2310 * bridge chip design team. This may be done by the sparc pci 2311 * bus nexus driver, but the driver should make sure the latency 2312 * timer is correct for performance reasons. 2313 */ 2314 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2315 MPTSAS_LATENCY_TIMER); 2316 2317 (void) mptsas_get_pci_cap(mpt); 2318 return (TRUE); 2319} 2320 2321static void 2322mptsas_config_space_fini(mptsas_t *mpt) 2323{ 2324 if (mpt->m_config_handle != NULL) { 2325 mptsas_disable_bus_master(mpt); 2326 pci_config_teardown(&mpt->m_config_handle); 2327 mpt->m_config_handle = NULL; 2328 } 2329} 2330 2331static void 2332mptsas_setup_cmd_reg(mptsas_t *mpt) 2333{ 2334 ushort_t cmdreg; 2335 2336 /* 2337 * Set the command register to the needed values. 2338 */ 2339 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2340 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2341 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2342 cmdreg &= ~PCI_COMM_IO; 2343 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2344} 2345 2346static void 2347mptsas_disable_bus_master(mptsas_t *mpt) 2348{ 2349 ushort_t cmdreg; 2350 2351 /* 2352 * Clear the master enable bit in the PCI command register. 2353 * This prevents any bus mastering activity like DMA. 2354 */ 2355 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2356 cmdreg &= ~PCI_COMM_ME; 2357 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2358} 2359 2360int 2361mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2362{ 2363 ddi_dma_attr_t attrs; 2364 2365 attrs = mpt->m_io_dma_attr; 2366 attrs.dma_attr_sgllen = 1; 2367 2368 ASSERT(dma_statep != NULL); 2369 2370 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle, 2371 &dma_statep->accessp, &dma_statep->memp, dma_statep->size, 2372 &dma_statep->cookie) == FALSE) { 2373 return (DDI_FAILURE); 2374 } 2375 2376 return (DDI_SUCCESS); 2377} 2378 2379void 2380mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2381{ 2382 ASSERT(dma_statep != NULL); 2383 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp); 2384 dma_statep->size = 0; 2385} 2386 2387int 2388mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2389{ 2390 ddi_dma_attr_t attrs; 2391 ddi_dma_handle_t dma_handle; 2392 caddr_t memp; 2393 ddi_acc_handle_t accessp; 2394 int rval; 2395 2396 ASSERT(mutex_owned(&mpt->m_mutex)); 2397 2398 attrs = mpt->m_msg_dma_attr; 2399 attrs.dma_attr_sgllen = 1; 2400 attrs.dma_attr_granular = size; 2401 2402 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle, 2403 &accessp, &memp, size, NULL) == FALSE) { 2404 return (DDI_FAILURE); 2405 } 2406 2407 rval = (*callback) (mpt, memp, var, accessp); 2408 2409 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2410 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2411 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2412 rval = DDI_FAILURE; 2413 } 2414 2415 mptsas_dma_addr_destroy(&dma_handle, &accessp); 2416 return (rval); 2417 2418} 2419 2420static int 2421mptsas_alloc_request_frames(mptsas_t *mpt) 2422{ 2423 ddi_dma_attr_t frame_dma_attrs; 2424 caddr_t memp; 2425 ddi_dma_cookie_t cookie; 2426 size_t mem_size; 2427 2428 /* 2429 * re-alloc when it has already alloced 2430 */ 2431 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2432 &mpt->m_acc_req_frame_hdl); 2433 2434 /* 2435 * The size of the request frame pool is: 2436 * Number of Request Frames * Request Frame Size 2437 */ 2438 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2439 2440 /* 2441 * set the DMA attributes. System Request Message Frames must be 2442 * aligned on a 16-byte boundry. 2443 */ 2444 frame_dma_attrs = mpt->m_msg_dma_attr; 2445 frame_dma_attrs.dma_attr_align = 16; 2446 frame_dma_attrs.dma_attr_sgllen = 1; 2447 2448 /* 2449 * allocate the request frame pool. 2450 */ 2451 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2452 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp, 2453 mem_size, &cookie) == FALSE) { 2454 return (DDI_FAILURE); 2455 } 2456 2457 /* 2458 * Store the request frame memory address. This chip uses this 2459 * address to dma to and from the driver's frame. The second 2460 * address is the address mpt uses to fill in the frame. 2461 */ 2462 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2463 mpt->m_req_frame = memp; 2464 2465 /* 2466 * Clear the request frame pool. 2467 */ 2468 bzero(mpt->m_req_frame, mem_size); 2469 2470 return (DDI_SUCCESS); 2471} 2472 2473static int 2474mptsas_alloc_reply_frames(mptsas_t *mpt) 2475{ 2476 ddi_dma_attr_t frame_dma_attrs; 2477 caddr_t memp; 2478 ddi_dma_cookie_t cookie; 2479 size_t mem_size; 2480 2481 /* 2482 * re-alloc when it has already alloced 2483 */ 2484 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2485 &mpt->m_acc_reply_frame_hdl); 2486 2487 /* 2488 * The size of the reply frame pool is: 2489 * Number of Reply Frames * Reply Frame Size 2490 */ 2491 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2492 2493 /* 2494 * set the DMA attributes. System Reply Message Frames must be 2495 * aligned on a 4-byte boundry. This is the default. 2496 */ 2497 frame_dma_attrs = mpt->m_msg_dma_attr; 2498 frame_dma_attrs.dma_attr_sgllen = 1; 2499 2500 /* 2501 * allocate the reply frame pool 2502 */ 2503 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2504 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp, 2505 mem_size, &cookie) == FALSE) { 2506 return (DDI_FAILURE); 2507 } 2508 2509 /* 2510 * Store the reply frame memory address. This chip uses this 2511 * address to dma to and from the driver's frame. The second 2512 * address is the address mpt uses to process the frame. 2513 */ 2514 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2515 mpt->m_reply_frame = memp; 2516 2517 /* 2518 * Clear the reply frame pool. 2519 */ 2520 bzero(mpt->m_reply_frame, mem_size); 2521 2522 return (DDI_SUCCESS); 2523} 2524 2525static int 2526mptsas_alloc_free_queue(mptsas_t *mpt) 2527{ 2528 ddi_dma_attr_t frame_dma_attrs; 2529 caddr_t memp; 2530 ddi_dma_cookie_t cookie; 2531 size_t mem_size; 2532 2533 /* 2534 * re-alloc when it has already alloced 2535 */ 2536 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2537 &mpt->m_acc_free_queue_hdl); 2538 2539 /* 2540 * The reply free queue size is: 2541 * Reply Free Queue Depth * 4 2542 * The "4" is the size of one 32 bit address (low part of 64-bit 2543 * address) 2544 */ 2545 mem_size = mpt->m_free_queue_depth * 4; 2546 2547 /* 2548 * set the DMA attributes The Reply Free Queue must be aligned on a 2549 * 16-byte boundry. 2550 */ 2551 frame_dma_attrs = mpt->m_msg_dma_attr; 2552 frame_dma_attrs.dma_attr_align = 16; 2553 frame_dma_attrs.dma_attr_sgllen = 1; 2554 2555 /* 2556 * allocate the reply free queue 2557 */ 2558 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2559 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp, 2560 mem_size, &cookie) == FALSE) { 2561 return (DDI_FAILURE); 2562 } 2563 2564 /* 2565 * Store the reply free queue memory address. This chip uses this 2566 * address to read from the reply free queue. The second address 2567 * is the address mpt uses to manage the queue. 2568 */ 2569 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2570 mpt->m_free_queue = memp; 2571 2572 /* 2573 * Clear the reply free queue memory. 2574 */ 2575 bzero(mpt->m_free_queue, mem_size); 2576 2577 return (DDI_SUCCESS); 2578} 2579 2580static int 2581mptsas_alloc_post_queue(mptsas_t *mpt) 2582{ 2583 ddi_dma_attr_t frame_dma_attrs; 2584 caddr_t memp; 2585 ddi_dma_cookie_t cookie; 2586 size_t mem_size; 2587 2588 /* 2589 * re-alloc when it has already alloced 2590 */ 2591 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2592 &mpt->m_acc_post_queue_hdl); 2593 2594 /* 2595 * The reply descriptor post queue size is: 2596 * Reply Descriptor Post Queue Depth * 8 2597 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2598 */ 2599 mem_size = mpt->m_post_queue_depth * 8; 2600 2601 /* 2602 * set the DMA attributes. The Reply Descriptor Post Queue must be 2603 * aligned on a 16-byte boundry. 2604 */ 2605 frame_dma_attrs = mpt->m_msg_dma_attr; 2606 frame_dma_attrs.dma_attr_align = 16; 2607 frame_dma_attrs.dma_attr_sgllen = 1; 2608 2609 /* 2610 * allocate the reply post queue 2611 */ 2612 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2613 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp, 2614 mem_size, &cookie) == FALSE) { 2615 return (DDI_FAILURE); 2616 } 2617 2618 /* 2619 * Store the reply descriptor post queue memory address. This chip 2620 * uses this address to write to the reply descriptor post queue. The 2621 * second address is the address mpt uses to manage the queue. 2622 */ 2623 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2624 mpt->m_post_queue = memp; 2625 2626 /* 2627 * Clear the reply post queue memory. 2628 */ 2629 bzero(mpt->m_post_queue, mem_size); 2630 2631 return (DDI_SUCCESS); 2632} 2633 2634static void 2635mptsas_alloc_reply_args(mptsas_t *mpt) 2636{ 2637 if (mpt->m_replyh_args != NULL) { 2638 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 2639 * mpt->m_max_replies); 2640 mpt->m_replyh_args = NULL; 2641 } 2642 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 2643 mpt->m_max_replies, KM_SLEEP); 2644} 2645 2646static int 2647mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2648{ 2649 mptsas_cache_frames_t *frames = NULL; 2650 if (cmd->cmd_extra_frames == NULL) { 2651 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2652 if (frames == NULL) { 2653 return (DDI_FAILURE); 2654 } 2655 cmd->cmd_extra_frames = frames; 2656 } 2657 return (DDI_SUCCESS); 2658} 2659 2660static void 2661mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2662{ 2663 if (cmd->cmd_extra_frames) { 2664 kmem_cache_free(mpt->m_cache_frames, 2665 (void *)cmd->cmd_extra_frames); 2666 cmd->cmd_extra_frames = NULL; 2667 } 2668} 2669 2670static void 2671mptsas_cfg_fini(mptsas_t *mpt) 2672{ 2673 NDBG0(("mptsas_cfg_fini")); 2674 ddi_regs_map_free(&mpt->m_datap); 2675} 2676 2677static void 2678mptsas_hba_fini(mptsas_t *mpt) 2679{ 2680 NDBG0(("mptsas_hba_fini")); 2681 2682 /* 2683 * Free up any allocated memory 2684 */ 2685 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2686 &mpt->m_acc_req_frame_hdl); 2687 2688 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2689 &mpt->m_acc_reply_frame_hdl); 2690 2691 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2692 &mpt->m_acc_free_queue_hdl); 2693 2694 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2695 &mpt->m_acc_post_queue_hdl); 2696 2697 if (mpt->m_replyh_args != NULL) { 2698 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 2699 * mpt->m_max_replies); 2700 } 2701} 2702 2703static int 2704mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 2705{ 2706 int lun = 0; 2707 char *sas_wwn = NULL; 2708 int phynum = -1; 2709 int reallen = 0; 2710 2711 /* Get the target num */ 2712 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 2713 LUN_PROP, 0); 2714 2715 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 2716 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 2717 /* 2718 * Stick in the address of form "pPHY,LUN" 2719 */ 2720 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 2721 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, 2722 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) 2723 == DDI_PROP_SUCCESS) { 2724 /* 2725 * Stick in the address of the form "wWWN,LUN" 2726 */ 2727 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun); 2728 ddi_prop_free(sas_wwn); 2729 } else { 2730 return (DDI_FAILURE); 2731 } 2732 2733 ASSERT(reallen < len); 2734 if (reallen >= len) { 2735 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 2736 "length too small, it needs to be %d bytes", reallen + 1); 2737 } 2738 return (DDI_SUCCESS); 2739} 2740 2741/* 2742 * tran_tgt_init(9E) - target device instance initialization 2743 */ 2744static int 2745mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 2746 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 2747{ 2748#ifndef __lock_lint 2749 _NOTE(ARGUNUSED(hba_tran)) 2750#endif 2751 2752 /* 2753 * At this point, the scsi_device structure already exists 2754 * and has been initialized. 2755 * 2756 * Use this function to allocate target-private data structures, 2757 * if needed by this HBA. Add revised flow-control and queue 2758 * properties for child here, if desired and if you can tell they 2759 * support tagged queueing by now. 2760 */ 2761 mptsas_t *mpt; 2762 int lun = sd->sd_address.a_lun; 2763 mdi_pathinfo_t *pip = NULL; 2764 mptsas_tgt_private_t *tgt_private = NULL; 2765 mptsas_target_t *ptgt = NULL; 2766 char *psas_wwn = NULL; 2767 int phymask = 0; 2768 uint64_t sas_wwn = 0; 2769 mpt = SDEV2MPT(sd); 2770 2771 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 2772 2773 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 2774 (void *)hba_dip, (void *)tgt_dip, lun)); 2775 2776 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 2777 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 2778 ddi_set_name_addr(tgt_dip, NULL); 2779 return (DDI_FAILURE); 2780 } 2781 /* 2782 * phymask is 0 means the virtual port for RAID 2783 */ 2784 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 2785 "phymask", 0); 2786 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2787 if ((pip = (void *)(sd->sd_private)) == NULL) { 2788 /* 2789 * Very bad news if this occurs. Somehow scsi_vhci has 2790 * lost the pathinfo node for this target. 2791 */ 2792 return (DDI_NOT_WELL_FORMED); 2793 } 2794 2795 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 2796 DDI_PROP_SUCCESS) { 2797 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 2798 return (DDI_FAILURE); 2799 } 2800 2801 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 2802 &psas_wwn) == MDI_SUCCESS) { 2803 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2804 sas_wwn = 0; 2805 } 2806 (void) mdi_prop_free(psas_wwn); 2807 } 2808 } else { 2809 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 2810 DDI_PROP_DONTPASS, LUN_PROP, 0); 2811 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 2812 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 2813 DDI_PROP_SUCCESS) { 2814 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2815 sas_wwn = 0; 2816 } 2817 ddi_prop_free(psas_wwn); 2818 } else { 2819 sas_wwn = 0; 2820 } 2821 } 2822 ASSERT((sas_wwn != 0) || (phymask != 0)); 2823 mutex_enter(&mpt->m_mutex); 2824 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask); 2825 mutex_exit(&mpt->m_mutex); 2826 if (ptgt == NULL) { 2827 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 2828 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 2829 sas_wwn); 2830 return (DDI_FAILURE); 2831 } 2832 if (hba_tran->tran_tgt_private == NULL) { 2833 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 2834 KM_SLEEP); 2835 tgt_private->t_lun = lun; 2836 tgt_private->t_private = ptgt; 2837 hba_tran->tran_tgt_private = tgt_private; 2838 } 2839 2840 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2841 return (DDI_SUCCESS); 2842 } 2843 mutex_enter(&mpt->m_mutex); 2844 2845 if (ptgt->m_deviceinfo & 2846 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 2847 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 2848 uchar_t *inq89 = NULL; 2849 int inq89_len = 0x238; 2850 int reallen = 0; 2851 int rval = 0; 2852 struct sata_id *sid = NULL; 2853 char model[SATA_ID_MODEL_LEN + 1]; 2854 char fw[SATA_ID_FW_LEN + 1]; 2855 char *vid, *pid; 2856 int i; 2857 2858 mutex_exit(&mpt->m_mutex); 2859 /* 2860 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 2861 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 2862 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 2863 */ 2864 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 2865 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 2866 inq89, inq89_len, &reallen, 1); 2867 2868 if (rval != 0) { 2869 if (inq89 != NULL) { 2870 kmem_free(inq89, inq89_len); 2871 } 2872 2873 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 2874 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 2875 return (DDI_SUCCESS); 2876 } 2877 sid = (void *)(&inq89[60]); 2878 2879 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 2880 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 2881 2882 model[SATA_ID_MODEL_LEN] = 0; 2883 fw[SATA_ID_FW_LEN] = 0; 2884 2885 /* 2886 * split model into into vid/pid 2887 */ 2888 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++) 2889 if ((*pid == ' ') || (*pid == '\t')) 2890 break; 2891 if (i < SATA_ID_MODEL_LEN) { 2892 vid = model; 2893 /* 2894 * terminate vid, establish pid 2895 */ 2896 *pid++ = 0; 2897 } else { 2898 /* 2899 * vid will stay "ATA ", the rule is same 2900 * as sata framework implementation. 2901 */ 2902 vid = NULL; 2903 /* 2904 * model is all pid 2905 */ 2906 pid = model; 2907 } 2908 2909 /* 2910 * override SCSA "inquiry-*" properties 2911 */ 2912 if (vid) 2913 (void) scsi_device_prop_update_inqstring(sd, 2914 INQUIRY_VENDOR_ID, vid, strlen(vid)); 2915 if (pid) 2916 (void) scsi_device_prop_update_inqstring(sd, 2917 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 2918 (void) scsi_device_prop_update_inqstring(sd, 2919 INQUIRY_REVISION_ID, fw, strlen(fw)); 2920 2921 if (inq89 != NULL) { 2922 kmem_free(inq89, inq89_len); 2923 } 2924 } else { 2925 mutex_exit(&mpt->m_mutex); 2926 } 2927 2928 return (DDI_SUCCESS); 2929} 2930/* 2931 * tran_tgt_free(9E) - target device instance deallocation 2932 */ 2933static void 2934mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 2935 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 2936{ 2937#ifndef __lock_lint 2938 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 2939#endif 2940 2941 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 2942 2943 if (tgt_private != NULL) { 2944 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 2945 hba_tran->tran_tgt_private = NULL; 2946 } 2947} 2948 2949/* 2950 * scsi_pkt handling 2951 * 2952 * Visible to the external world via the transport structure. 2953 */ 2954 2955/* 2956 * Notes: 2957 * - transport the command to the addressed SCSI target/lun device 2958 * - normal operation is to schedule the command to be transported, 2959 * and return TRAN_ACCEPT if this is successful. 2960 * - if NO_INTR, tran_start must poll device for command completion 2961 */ 2962static int 2963mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 2964{ 2965#ifndef __lock_lint 2966 _NOTE(ARGUNUSED(ap)) 2967#endif 2968 mptsas_t *mpt = PKT2MPT(pkt); 2969 mptsas_cmd_t *cmd = PKT2CMD(pkt); 2970 int rval; 2971 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 2972 2973 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 2974 ASSERT(ptgt); 2975 if (ptgt == NULL) 2976 return (TRAN_FATAL_ERROR); 2977 2978 /* 2979 * prepare the pkt before taking mutex. 2980 */ 2981 rval = mptsas_prepare_pkt(cmd); 2982 if (rval != TRAN_ACCEPT) { 2983 return (rval); 2984 } 2985 2986 /* 2987 * Send the command to target/lun, however your HBA requires it. 2988 * If busy, return TRAN_BUSY; if there's some other formatting error 2989 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 2990 * return of TRAN_ACCEPT. 2991 * 2992 * Remember that access to shared resources, including the mptsas_t 2993 * data structure and the HBA hardware registers, must be protected 2994 * with mutexes, here and everywhere. 2995 * 2996 * Also remember that at interrupt time, you'll get an argument 2997 * to the interrupt handler which is a pointer to your mptsas_t 2998 * structure; you'll have to remember which commands are outstanding 2999 * and which scsi_pkt is the currently-running command so the 3000 * interrupt handler can refer to the pkt to set completion 3001 * status, call the target driver back through pkt_comp, etc. 3002 */ 3003 3004 mutex_enter(&ptgt->m_tgt_intr_mutex); 3005 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3006 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3007 /* 3008 * commands should be allowed to retry by 3009 * returning TRAN_BUSY to stall the I/O's 3010 * which come from scsi_vhci since the device/ 3011 * path is in unstable state now. 3012 */ 3013 mutex_exit(&ptgt->m_tgt_intr_mutex); 3014 return (TRAN_BUSY); 3015 } else { 3016 /* 3017 * The device is offline, just fail the 3018 * command by returning TRAN_FATAL_ERROR. 3019 */ 3020 mutex_exit(&ptgt->m_tgt_intr_mutex); 3021 return (TRAN_FATAL_ERROR); 3022 } 3023 } 3024 mutex_exit(&ptgt->m_tgt_intr_mutex); 3025 rval = mptsas_accept_pkt(mpt, cmd); 3026 3027 return (rval); 3028} 3029 3030static int 3031mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3032{ 3033 int rval = TRAN_ACCEPT; 3034 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3035 3036 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3037 3038 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3039 rval = mptsas_prepare_pkt(cmd); 3040 if (rval != TRAN_ACCEPT) { 3041 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3042 return (rval); 3043 } 3044 } 3045 3046 /* 3047 * reset the throttle if we were draining 3048 */ 3049 mutex_enter(&ptgt->m_tgt_intr_mutex); 3050 if ((ptgt->m_t_ncmds == 0) && 3051 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3052 NDBG23(("reset throttle")); 3053 ASSERT(ptgt->m_reset_delay == 0); 3054 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3055 } 3056 3057 /* 3058 * If device handle has already been invalidated, just 3059 * fail the command. In theory, command from scsi_vhci 3060 * client is impossible send down command with invalid 3061 * devhdl since devhdl is set after path offline, target 3062 * driver is not suppose to select a offlined path. 3063 */ 3064 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3065 NDBG20(("rejecting command, it might because invalid devhdl " 3066 "request.")); 3067 mutex_exit(&ptgt->m_tgt_intr_mutex); 3068 mutex_enter(&mpt->m_mutex); 3069 /* 3070 * If HBA is being reset, the DevHandles are being 3071 * re-initialized, which means that they could be invalid 3072 * even if the target is still attached. Check if being reset 3073 * and if DevHandle is being re-initialized. If this is the 3074 * case, return BUSY so the I/O can be retried later. 3075 */ 3076 if (mpt->m_in_reset) { 3077 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 3078 STAT_BUS_RESET); 3079 if (cmd->cmd_flags & CFLAG_TXQ) { 3080 mptsas_doneq_add(mpt, cmd); 3081 mptsas_doneq_empty(mpt); 3082 mutex_exit(&mpt->m_mutex); 3083 return (rval); 3084 } else { 3085 mutex_exit(&mpt->m_mutex); 3086 return (TRAN_BUSY); 3087 } 3088 } 3089 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3090 if (cmd->cmd_flags & CFLAG_TXQ) { 3091 mptsas_doneq_add(mpt, cmd); 3092 mptsas_doneq_empty(mpt); 3093 mutex_exit(&mpt->m_mutex); 3094 return (rval); 3095 } else { 3096 mutex_exit(&mpt->m_mutex); 3097 return (TRAN_FATAL_ERROR); 3098 } 3099 } 3100 mutex_exit(&ptgt->m_tgt_intr_mutex); 3101 /* 3102 * The first case is the normal case. mpt gets a command from the 3103 * target driver and starts it. 3104 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3105 * commands is m_max_requests - 2. 3106 */ 3107 mutex_enter(&ptgt->m_tgt_intr_mutex); 3108 if ((ptgt->m_t_throttle > HOLD_THROTTLE) && 3109 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3110 (ptgt->m_reset_delay == 0) && 3111 (ptgt->m_t_nwait == 0) && 3112 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3113 mutex_exit(&ptgt->m_tgt_intr_mutex); 3114 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3115 (void) mptsas_start_cmd0(mpt, cmd); 3116 } else { 3117 mutex_enter(&mpt->m_mutex); 3118 mptsas_waitq_add(mpt, cmd); 3119 mutex_exit(&mpt->m_mutex); 3120 } 3121 } else { 3122 /* 3123 * Add this pkt to the work queue 3124 */ 3125 mutex_exit(&ptgt->m_tgt_intr_mutex); 3126 mutex_enter(&mpt->m_mutex); 3127 mptsas_waitq_add(mpt, cmd); 3128 3129 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3130 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3131 3132 /* 3133 * Only flush the doneq if this is not a TM 3134 * cmd. For TM cmds the flushing of the 3135 * doneq will be done in those routines. 3136 */ 3137 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3138 mptsas_doneq_empty(mpt); 3139 } 3140 } 3141 mutex_exit(&mpt->m_mutex); 3142 } 3143 return (rval); 3144} 3145 3146int 3147mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3148{ 3149 mptsas_slots_t *slots; 3150 int slot; 3151 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3152 mptsas_slot_free_e_t *pe; 3153 int qn, qn_first; 3154 3155 slots = mpt->m_active; 3156 3157 /* 3158 * Account for reserved TM request slot and reserved SMID of 0. 3159 */ 3160 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2)); 3161 3162 qn = qn_first = CPU->cpu_seqid & (mpt->m_slot_freeq_pair_n - 1); 3163 3164qpair_retry: 3165 ASSERT(qn < mpt->m_slot_freeq_pair_n); 3166 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex); 3167 pe = list_head(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq. 3168 s.m_fq_list); 3169 if (!pe) { /* switch the allocq and releq */ 3170 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_releq. 3171 s.m_fq_mutex); 3172 if (mpt->m_slot_freeq_pairp[qn].m_slot_releq.s.m_fq_n) { 3173 mpt->m_slot_freeq_pairp[qn]. 3174 m_slot_allocq.s.m_fq_n = 3175 mpt->m_slot_freeq_pairp[qn]. 3176 m_slot_releq.s.m_fq_n; 3177 mpt->m_slot_freeq_pairp[qn]. 3178 m_slot_allocq.s.m_fq_list.list_head.list_next = 3179 mpt->m_slot_freeq_pairp[qn]. 3180 m_slot_releq.s.m_fq_list.list_head.list_next; 3181 mpt->m_slot_freeq_pairp[qn]. 3182 m_slot_allocq.s.m_fq_list.list_head.list_prev = 3183 mpt->m_slot_freeq_pairp[qn]. 3184 m_slot_releq.s.m_fq_list.list_head.list_prev; 3185 mpt->m_slot_freeq_pairp[qn]. 3186 m_slot_releq.s.m_fq_list.list_head.list_prev-> 3187 list_next = 3188 &mpt->m_slot_freeq_pairp[qn]. 3189 m_slot_allocq.s.m_fq_list.list_head; 3190 mpt->m_slot_freeq_pairp[qn]. 3191 m_slot_releq.s.m_fq_list.list_head.list_next-> 3192 list_prev = 3193 &mpt->m_slot_freeq_pairp[qn]. 3194 m_slot_allocq.s.m_fq_list.list_head; 3195 3196 mpt->m_slot_freeq_pairp[qn]. 3197 m_slot_releq.s.m_fq_list.list_head.list_next = 3198 mpt->m_slot_freeq_pairp[qn]. 3199 m_slot_releq.s.m_fq_list.list_head.list_prev = 3200 &mpt->m_slot_freeq_pairp[qn]. 3201 m_slot_releq.s.m_fq_list.list_head; 3202 mpt->m_slot_freeq_pairp[qn]. 3203 m_slot_releq.s.m_fq_n = 0; 3204 } else { 3205 mutex_exit(&mpt->m_slot_freeq_pairp[qn]. 3206 m_slot_releq.s.m_fq_mutex); 3207 mutex_exit(&mpt->m_slot_freeq_pairp[qn]. 3208 m_slot_allocq.s.m_fq_mutex); 3209 qn = (qn + 1) & (mpt->m_slot_freeq_pair_n - 1); 3210 if (qn == qn_first) 3211 return (FALSE); 3212 else 3213 goto qpair_retry; 3214 } 3215 mutex_exit(&mpt->m_slot_freeq_pairp[qn]. 3216 m_slot_releq.s.m_fq_mutex); 3217 pe = list_head(&mpt->m_slot_freeq_pairp[qn]. 3218 m_slot_allocq.s.m_fq_list); 3219 ASSERT(pe); 3220 } 3221 list_remove(&mpt->m_slot_freeq_pairp[qn]. 3222 m_slot_allocq.s.m_fq_list, pe); 3223 slot = pe->slot; 3224 /* 3225 * Make sure SMID is not using reserved value of 0 3226 * and the TM request slot. 3227 */ 3228 ASSERT((slot > 0) && (slot <= slots->m_n_slots) && 3229 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n > 0); 3230 cmd->cmd_slot = slot; 3231 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n--; 3232 ASSERT(mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n >= 0); 3233 3234 mutex_exit(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex); 3235 /* 3236 * only increment per target ncmds if this is not a 3237 * command that has no target associated with it (i.e. a 3238 * event acknoledgment) 3239 */ 3240 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3241 mutex_enter(&ptgt->m_tgt_intr_mutex); 3242 ptgt->m_t_ncmds++; 3243 mutex_exit(&ptgt->m_tgt_intr_mutex); 3244 } 3245 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time; 3246 3247 /* 3248 * If initial timout is less than or equal to one tick, bump 3249 * the timeout by a tick so that command doesn't timeout before 3250 * its allotted time. 3251 */ 3252 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) { 3253 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick; 3254 } 3255 return (TRUE); 3256} 3257 3258/* 3259 * prepare the pkt: 3260 * the pkt may have been resubmitted or just reused so 3261 * initialize some fields and do some checks. 3262 */ 3263static int 3264mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3265{ 3266 struct scsi_pkt *pkt = CMD2PKT(cmd); 3267 3268 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3269 3270 /* 3271 * Reinitialize some fields that need it; the packet may 3272 * have been resubmitted 3273 */ 3274 pkt->pkt_reason = CMD_CMPLT; 3275 pkt->pkt_state = 0; 3276 pkt->pkt_statistics = 0; 3277 pkt->pkt_resid = 0; 3278 cmd->cmd_age = 0; 3279 cmd->cmd_pkt_flags = pkt->pkt_flags; 3280 3281 /* 3282 * zero status byte. 3283 */ 3284 *(pkt->pkt_scbp) = 0; 3285 3286 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3287 pkt->pkt_resid = cmd->cmd_dmacount; 3288 3289 /* 3290 * consistent packets need to be sync'ed first 3291 * (only for data going out) 3292 */ 3293 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3294 (cmd->cmd_flags & CFLAG_DMASEND)) { 3295 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3296 DDI_DMA_SYNC_FORDEV); 3297 } 3298 } 3299 3300 cmd->cmd_flags = 3301 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3302 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3303 3304 return (TRAN_ACCEPT); 3305} 3306 3307/* 3308 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3309 * 3310 * One of three possibilities: 3311 * - allocate scsi_pkt 3312 * - allocate scsi_pkt and DMA resources 3313 * - allocate DMA resources to an already-allocated pkt 3314 */ 3315static struct scsi_pkt * 3316mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3317 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3318 int (*callback)(), caddr_t arg) 3319{ 3320 mptsas_cmd_t *cmd, *new_cmd; 3321 mptsas_t *mpt = ADDR2MPT(ap); 3322 int failure = 1; 3323#ifndef __sparc 3324 uint_t oldcookiec; 3325#endif /* __sparc */ 3326 mptsas_target_t *ptgt = NULL; 3327 int rval; 3328 mptsas_tgt_private_t *tgt_private; 3329 int kf; 3330 3331 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3332 3333 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3334 tran_tgt_private; 3335 ASSERT(tgt_private != NULL); 3336 if (tgt_private == NULL) { 3337 return (NULL); 3338 } 3339 ptgt = tgt_private->t_private; 3340 ASSERT(ptgt != NULL); 3341 if (ptgt == NULL) 3342 return (NULL); 3343 ap->a_target = ptgt->m_devhdl; 3344 ap->a_lun = tgt_private->t_lun; 3345 3346 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3347#ifdef MPTSAS_TEST_EXTRN_ALLOC 3348 statuslen *= 100; tgtlen *= 4; 3349#endif 3350 NDBG3(("mptsas_scsi_init_pkt:\n" 3351 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3352 ap->a_target, (void *)pkt, (void *)bp, 3353 cmdlen, statuslen, tgtlen, flags)); 3354 3355 /* 3356 * Allocate the new packet. 3357 */ 3358 if (pkt == NULL) { 3359 ddi_dma_handle_t save_dma_handle; 3360 ddi_dma_handle_t save_arq_dma_handle; 3361 struct buf *save_arq_bp; 3362 ddi_dma_cookie_t save_arqcookie; 3363#ifdef __sparc 3364 mptti_t *save_sg; 3365#endif /* __sparc */ 3366 3367 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3368 3369 if (cmd) { 3370 save_dma_handle = cmd->cmd_dmahandle; 3371 save_arq_dma_handle = cmd->cmd_arqhandle; 3372 save_arq_bp = cmd->cmd_arq_buf; 3373 save_arqcookie = cmd->cmd_arqcookie; 3374#ifdef __sparc 3375 save_sg = cmd->cmd_sg; 3376#endif /* __sparc */ 3377 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3378 cmd->cmd_dmahandle = save_dma_handle; 3379 cmd->cmd_arqhandle = save_arq_dma_handle; 3380 cmd->cmd_arq_buf = save_arq_bp; 3381 cmd->cmd_arqcookie = save_arqcookie; 3382#ifdef __sparc 3383 cmd->cmd_sg = save_sg; 3384#endif /* __sparc */ 3385 pkt = (void *)((uchar_t *)cmd + 3386 sizeof (struct mptsas_cmd)); 3387 pkt->pkt_ha_private = (opaque_t)cmd; 3388 pkt->pkt_address = *ap; 3389 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3390 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3391 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3392 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3393 cmd->cmd_cdblen = (uchar_t)cmdlen; 3394 cmd->cmd_scblen = statuslen; 3395 cmd->cmd_rqslen = SENSE_LENGTH; 3396 cmd->cmd_tgt_addr = ptgt; 3397 failure = 0; 3398 } 3399 3400 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) || 3401 (tgtlen > PKT_PRIV_LEN) || 3402 (statuslen > EXTCMDS_STATUS_SIZE)) { 3403 if (failure == 0) { 3404 /* 3405 * if extern alloc fails, all will be 3406 * deallocated, including cmd 3407 */ 3408 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3409 cmdlen, tgtlen, statuslen, kf); 3410 } 3411 if (failure) { 3412 /* 3413 * if extern allocation fails, it will 3414 * deallocate the new pkt as well 3415 */ 3416 return (NULL); 3417 } 3418 } 3419 new_cmd = cmd; 3420 3421 } else { 3422 cmd = PKT2CMD(pkt); 3423 new_cmd = NULL; 3424 } 3425 3426 3427#ifndef __sparc 3428 /* grab cmd->cmd_cookiec here as oldcookiec */ 3429 3430 oldcookiec = cmd->cmd_cookiec; 3431#endif /* __sparc */ 3432 3433 /* 3434 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3435 * greater than 0 and we'll need to grab the next dma window 3436 */ 3437 /* 3438 * SLM-not doing extra command frame right now; may add later 3439 */ 3440 3441 if (cmd->cmd_nwin > 0) { 3442 3443 /* 3444 * Make sure we havn't gone past the the total number 3445 * of windows 3446 */ 3447 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3448 return (NULL); 3449 } 3450 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3451 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3452 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3453 return (NULL); 3454 } 3455 goto get_dma_cookies; 3456 } 3457 3458 3459 if (flags & PKT_XARQ) { 3460 cmd->cmd_flags |= CFLAG_XARQ; 3461 } 3462 3463 /* 3464 * DMA resource allocation. This version assumes your 3465 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3466 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3467 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3468 */ 3469 if (bp && (bp->b_bcount != 0) && 3470 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3471 3472 int cnt, dma_flags; 3473 mptti_t *dmap; /* ptr to the S/G list */ 3474 3475 /* 3476 * Set up DMA memory and position to the next DMA segment. 3477 */ 3478 ASSERT(cmd->cmd_dmahandle != NULL); 3479 3480 if (bp->b_flags & B_READ) { 3481 dma_flags = DDI_DMA_READ; 3482 cmd->cmd_flags &= ~CFLAG_DMASEND; 3483 } else { 3484 dma_flags = DDI_DMA_WRITE; 3485 cmd->cmd_flags |= CFLAG_DMASEND; 3486 } 3487 if (flags & PKT_CONSISTENT) { 3488 cmd->cmd_flags |= CFLAG_CMDIOPB; 3489 dma_flags |= DDI_DMA_CONSISTENT; 3490 } 3491 3492 if (flags & PKT_DMA_PARTIAL) { 3493 dma_flags |= DDI_DMA_PARTIAL; 3494 } 3495 3496 /* 3497 * workaround for byte hole issue on psycho and 3498 * schizo pre 2.1 3499 */ 3500 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3501 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3502 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3503 dma_flags |= DDI_DMA_CONSISTENT; 3504 } 3505 3506 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3507 dma_flags, callback, arg, 3508 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3509 if (rval == DDI_DMA_PARTIAL_MAP) { 3510 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3511 &cmd->cmd_nwin); 3512 cmd->cmd_winindex = 0; 3513 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3514 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3515 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3516 &cmd->cmd_cookiec); 3517 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3518 switch (rval) { 3519 case DDI_DMA_NORESOURCES: 3520 bioerror(bp, 0); 3521 break; 3522 case DDI_DMA_BADATTR: 3523 case DDI_DMA_NOMAPPING: 3524 bioerror(bp, EFAULT); 3525 break; 3526 case DDI_DMA_TOOBIG: 3527 default: 3528 bioerror(bp, EINVAL); 3529 break; 3530 } 3531 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3532 if (new_cmd) { 3533 mptsas_scsi_destroy_pkt(ap, pkt); 3534 } 3535 return ((struct scsi_pkt *)NULL); 3536 } 3537 3538get_dma_cookies: 3539 cmd->cmd_flags |= CFLAG_DMAVALID; 3540 ASSERT(cmd->cmd_cookiec > 0); 3541 3542 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3543 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3544 cmd->cmd_cookiec); 3545 bioerror(bp, EINVAL); 3546 if (new_cmd) { 3547 mptsas_scsi_destroy_pkt(ap, pkt); 3548 } 3549 return ((struct scsi_pkt *)NULL); 3550 } 3551 3552 /* 3553 * Allocate extra SGL buffer if needed. 3554 */ 3555 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3556 (cmd->cmd_extra_frames == NULL)) { 3557 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3558 DDI_FAILURE) { 3559 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3560 "failed"); 3561 bioerror(bp, ENOMEM); 3562 if (new_cmd) { 3563 mptsas_scsi_destroy_pkt(ap, pkt); 3564 } 3565 return ((struct scsi_pkt *)NULL); 3566 } 3567 } 3568 3569 /* 3570 * Always use scatter-gather transfer 3571 * Use the loop below to store physical addresses of 3572 * DMA segments, from the DMA cookies, into your HBA's 3573 * scatter-gather list. 3574 * We need to ensure we have enough kmem alloc'd 3575 * for the sg entries since we are no longer using an 3576 * array inside mptsas_cmd_t. 3577 * 3578 * We check cmd->cmd_cookiec against oldcookiec so 3579 * the scatter-gather list is correctly allocated 3580 */ 3581#ifndef __sparc 3582 if (oldcookiec != cmd->cmd_cookiec) { 3583 if (cmd->cmd_sg != (mptti_t *)NULL) { 3584 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3585 oldcookiec); 3586 cmd->cmd_sg = NULL; 3587 } 3588 } 3589 3590 if (cmd->cmd_sg == (mptti_t *)NULL) { 3591 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3592 cmd->cmd_cookiec), kf); 3593 3594 if (cmd->cmd_sg == (mptti_t *)NULL) { 3595 mptsas_log(mpt, CE_WARN, 3596 "unable to kmem_alloc enough memory " 3597 "for scatter/gather list"); 3598 /* 3599 * if we have an ENOMEM condition we need to behave 3600 * the same way as the rest of this routine 3601 */ 3602 3603 bioerror(bp, ENOMEM); 3604 if (new_cmd) { 3605 mptsas_scsi_destroy_pkt(ap, pkt); 3606 } 3607 return ((struct scsi_pkt *)NULL); 3608 } 3609 } 3610#endif /* __sparc */ 3611 dmap = cmd->cmd_sg; 3612 3613 ASSERT(cmd->cmd_cookie.dmac_size != 0); 3614 3615 /* 3616 * store the first segment into the S/G list 3617 */ 3618 dmap->count = cmd->cmd_cookie.dmac_size; 3619 dmap->addr.address64.Low = (uint32_t) 3620 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3621 dmap->addr.address64.High = (uint32_t) 3622 (cmd->cmd_cookie.dmac_laddress >> 32); 3623 3624 /* 3625 * dmacount counts the size of the dma for this window 3626 * (if partial dma is being used). totaldmacount 3627 * keeps track of the total amount of dma we have 3628 * transferred for all the windows (needed to calculate 3629 * the resid value below). 3630 */ 3631 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 3632 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3633 3634 /* 3635 * We already stored the first DMA scatter gather segment, 3636 * start at 1 if we need to store more. 3637 */ 3638 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 3639 /* 3640 * Get next DMA cookie 3641 */ 3642 ddi_dma_nextcookie(cmd->cmd_dmahandle, 3643 &cmd->cmd_cookie); 3644 dmap++; 3645 3646 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 3647 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3648 3649 /* 3650 * store the segment parms into the S/G list 3651 */ 3652 dmap->count = cmd->cmd_cookie.dmac_size; 3653 dmap->addr.address64.Low = (uint32_t) 3654 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3655 dmap->addr.address64.High = (uint32_t) 3656 (cmd->cmd_cookie.dmac_laddress >> 32); 3657 } 3658 3659 /* 3660 * If this was partially allocated we set the resid 3661 * the amount of data NOT transferred in this window 3662 * If there is only one window, the resid will be 0 3663 */ 3664 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 3665 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount)); 3666 } 3667 return (pkt); 3668} 3669 3670/* 3671 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 3672 * 3673 * Notes: 3674 * - also frees DMA resources if allocated 3675 * - implicit DMA synchonization 3676 */ 3677static void 3678mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 3679{ 3680 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3681 mptsas_t *mpt = ADDR2MPT(ap); 3682 3683 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 3684 ap->a_target, (void *)pkt)); 3685 3686 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3687 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 3688 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3689 } 3690#ifndef __sparc 3691 if (cmd->cmd_sg) { 3692 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 3693 cmd->cmd_sg = NULL; 3694 } 3695#endif /* __sparc */ 3696 mptsas_free_extra_sgl_frame(mpt, cmd); 3697 3698 if ((cmd->cmd_flags & 3699 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 3700 CFLAG_SCBEXTERN)) == 0) { 3701 cmd->cmd_flags = CFLAG_FREE; 3702 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 3703 } else { 3704 mptsas_pkt_destroy_extern(mpt, cmd); 3705 } 3706} 3707 3708/* 3709 * kmem cache constructor and destructor: 3710 * When constructing, we bzero the cmd and allocate the dma handle 3711 * When destructing, just free the dma handle 3712 */ 3713static int 3714mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 3715{ 3716 mptsas_cmd_t *cmd = buf; 3717 mptsas_t *mpt = cdrarg; 3718 struct scsi_address ap; 3719 uint_t cookiec; 3720 ddi_dma_attr_t arq_dma_attr; 3721 int (*callback)(caddr_t); 3722 3723 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3724 3725 NDBG4(("mptsas_kmem_cache_constructor")); 3726 3727 ap.a_hba_tran = mpt->m_tran; 3728 ap.a_target = 0; 3729 ap.a_lun = 0; 3730 3731 /* 3732 * allocate a dma handle 3733 */ 3734 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 3735 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 3736 cmd->cmd_dmahandle = NULL; 3737 return (-1); 3738 } 3739 3740 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL, 3741 SENSE_LENGTH, B_READ, callback, NULL); 3742 if (cmd->cmd_arq_buf == NULL) { 3743 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3744 cmd->cmd_dmahandle = NULL; 3745 return (-1); 3746 } 3747 3748 /* 3749 * allocate a arq handle 3750 */ 3751 arq_dma_attr = mpt->m_msg_dma_attr; 3752 arq_dma_attr.dma_attr_sgllen = 1; 3753 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback, 3754 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) { 3755 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3756 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3757 cmd->cmd_dmahandle = NULL; 3758 cmd->cmd_arqhandle = NULL; 3759 return (-1); 3760 } 3761 3762 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle, 3763 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 3764 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) { 3765 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3766 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3767 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3768 cmd->cmd_dmahandle = NULL; 3769 cmd->cmd_arqhandle = NULL; 3770 cmd->cmd_arq_buf = NULL; 3771 return (-1); 3772 } 3773 /* 3774 * In sparc, the sgl length in most of the cases would be 1, so we 3775 * pre-allocate it in cache. On x86, the max number would be 256, 3776 * pre-allocate a maximum would waste a lot of memory especially 3777 * when many cmds are put onto waitq. 3778 */ 3779#ifdef __sparc 3780 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3781 MPTSAS_MAX_CMD_SEGS), KM_SLEEP); 3782#endif /* __sparc */ 3783 3784 return (0); 3785} 3786 3787static void 3788mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 3789{ 3790#ifndef __lock_lint 3791 _NOTE(ARGUNUSED(cdrarg)) 3792#endif 3793 mptsas_cmd_t *cmd = buf; 3794 3795 NDBG4(("mptsas_kmem_cache_destructor")); 3796 3797 if (cmd->cmd_arqhandle) { 3798 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle); 3799 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3800 cmd->cmd_arqhandle = NULL; 3801 } 3802 if (cmd->cmd_arq_buf) { 3803 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3804 cmd->cmd_arq_buf = NULL; 3805 } 3806 if (cmd->cmd_dmahandle) { 3807 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3808 cmd->cmd_dmahandle = NULL; 3809 } 3810#ifdef __sparc 3811 if (cmd->cmd_sg) { 3812 kmem_free(cmd->cmd_sg, sizeof (mptti_t)* MPTSAS_MAX_CMD_SEGS); 3813 cmd->cmd_sg = NULL; 3814 } 3815#endif /* __sparc */ 3816} 3817 3818static int 3819mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 3820{ 3821 mptsas_cache_frames_t *p = buf; 3822 mptsas_t *mpt = cdrarg; 3823 ddi_dma_attr_t frame_dma_attr; 3824 size_t mem_size, alloc_len; 3825 ddi_dma_cookie_t cookie; 3826 uint_t ncookie; 3827 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 3828 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3829 3830 frame_dma_attr = mpt->m_msg_dma_attr; 3831 frame_dma_attr.dma_attr_align = 0x10; 3832 frame_dma_attr.dma_attr_sgllen = 1; 3833 3834 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 3835 &p->m_dma_hdl) != DDI_SUCCESS) { 3836 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 3837 " extra SGL."); 3838 return (DDI_FAILURE); 3839 } 3840 3841 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 3842 3843 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 3844 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 3845 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 3846 ddi_dma_free_handle(&p->m_dma_hdl); 3847 p->m_dma_hdl = NULL; 3848 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 3849 " extra SGL."); 3850 return (DDI_FAILURE); 3851 } 3852 3853 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 3854 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 3855 &cookie, &ncookie) != DDI_DMA_MAPPED) { 3856 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3857 ddi_dma_free_handle(&p->m_dma_hdl); 3858 p->m_dma_hdl = NULL; 3859 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 3860 " extra SGL"); 3861 return (DDI_FAILURE); 3862 } 3863 3864 /* 3865 * Store the SGL memory address. This chip uses this 3866 * address to dma to and from the driver. The second 3867 * address is the address mpt uses to fill in the SGL. 3868 */ 3869 p->m_phys_addr = cookie.dmac_address; 3870 3871 return (DDI_SUCCESS); 3872} 3873 3874static void 3875mptsas_cache_frames_destructor(void *buf, void *cdrarg) 3876{ 3877#ifndef __lock_lint 3878 _NOTE(ARGUNUSED(cdrarg)) 3879#endif 3880 mptsas_cache_frames_t *p = buf; 3881 if (p->m_dma_hdl != NULL) { 3882 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 3883 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3884 ddi_dma_free_handle(&p->m_dma_hdl); 3885 p->m_phys_addr = NULL; 3886 p->m_frames_addr = NULL; 3887 p->m_dma_hdl = NULL; 3888 p->m_acc_hdl = NULL; 3889 } 3890 3891} 3892 3893/* 3894 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 3895 * for non-standard length cdb, pkt_private, status areas 3896 * if allocation fails, then deallocate all external space and the pkt 3897 */ 3898/* ARGSUSED */ 3899static int 3900mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 3901 int cmdlen, int tgtlen, int statuslen, int kf) 3902{ 3903 caddr_t cdbp, scbp, tgt; 3904 int (*callback)(caddr_t) = (kf == KM_SLEEP) ? 3905 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT; 3906 struct scsi_address ap; 3907 size_t senselength; 3908 ddi_dma_attr_t ext_arq_dma_attr; 3909 uint_t cookiec; 3910 3911 NDBG3(("mptsas_pkt_alloc_extern: " 3912 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 3913 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 3914 3915 tgt = cdbp = scbp = NULL; 3916 cmd->cmd_scblen = statuslen; 3917 cmd->cmd_privlen = (uchar_t)tgtlen; 3918 3919 if (cmdlen > sizeof (cmd->cmd_cdb)) { 3920 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 3921 goto fail; 3922 } 3923 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 3924 cmd->cmd_flags |= CFLAG_CDBEXTERN; 3925 } 3926 if (tgtlen > PKT_PRIV_LEN) { 3927 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 3928 goto fail; 3929 } 3930 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 3931 cmd->cmd_pkt->pkt_private = tgt; 3932 } 3933 if (statuslen > EXTCMDS_STATUS_SIZE) { 3934 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 3935 goto fail; 3936 } 3937 cmd->cmd_flags |= CFLAG_SCBEXTERN; 3938 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 3939 3940 /* allocate sense data buf for DMA */ 3941 3942 senselength = statuslen - MPTSAS_GET_ITEM_OFF( 3943 struct scsi_arq_status, sts_sensedata); 3944 cmd->cmd_rqslen = (uchar_t)senselength; 3945 3946 ap.a_hba_tran = mpt->m_tran; 3947 ap.a_target = 0; 3948 ap.a_lun = 0; 3949 3950 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap, 3951 (struct buf *)NULL, senselength, B_READ, 3952 callback, NULL); 3953 3954 if (cmd->cmd_ext_arq_buf == NULL) { 3955 goto fail; 3956 } 3957 /* 3958 * allocate a extern arq handle and bind the buf 3959 */ 3960 ext_arq_dma_attr = mpt->m_msg_dma_attr; 3961 ext_arq_dma_attr.dma_attr_sgllen = 1; 3962 if ((ddi_dma_alloc_handle(mpt->m_dip, 3963 &ext_arq_dma_attr, callback, 3964 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) { 3965 goto fail; 3966 } 3967 3968 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle, 3969 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 3970 callback, NULL, &cmd->cmd_ext_arqcookie, 3971 &cookiec) 3972 != DDI_SUCCESS) { 3973 goto fail; 3974 } 3975 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID; 3976 } 3977 return (0); 3978fail: 3979 mptsas_pkt_destroy_extern(mpt, cmd); 3980 return (1); 3981} 3982 3983/* 3984 * deallocate external pkt space and deallocate the pkt 3985 */ 3986static void 3987mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 3988{ 3989 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 3990 3991 if (cmd->cmd_flags & CFLAG_FREE) { 3992 mptsas_log(mpt, CE_PANIC, 3993 "mptsas_pkt_destroy_extern: freeing free packet"); 3994 _NOTE(NOT_REACHED) 3995 /* NOTREACHED */ 3996 } 3997 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 3998 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 3999 } 4000 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 4001 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4002 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4003 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4004 } 4005 if (cmd->cmd_ext_arqhandle) { 4006 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle); 4007 cmd->cmd_ext_arqhandle = NULL; 4008 } 4009 if (cmd->cmd_ext_arq_buf) 4010 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf); 4011 } 4012 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4013 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4014 } 4015 cmd->cmd_flags = CFLAG_FREE; 4016 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4017} 4018 4019/* 4020 * tran_sync_pkt(9E) - explicit DMA synchronization 4021 */ 4022/*ARGSUSED*/ 4023static void 4024mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4025{ 4026 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4027 4028 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4029 ap->a_target, (void *)pkt)); 4030 4031 if (cmd->cmd_dmahandle) { 4032 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4033 (cmd->cmd_flags & CFLAG_DMASEND) ? 4034 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4035 } 4036} 4037 4038/* 4039 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4040 */ 4041/*ARGSUSED*/ 4042static void 4043mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4044{ 4045 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4046 mptsas_t *mpt = ADDR2MPT(ap); 4047 4048 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4049 ap->a_target, (void *)pkt)); 4050 4051 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4052 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4053 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4054 } 4055 4056 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4057 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4058 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID; 4059 } 4060 4061 mptsas_free_extra_sgl_frame(mpt, cmd); 4062} 4063 4064static void 4065mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4066{ 4067 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4068 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4069 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4070 DDI_DMA_SYNC_FORCPU); 4071 } 4072 (*pkt->pkt_comp)(pkt); 4073} 4074 4075static void 4076mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 4077 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4078{ 4079 uint_t cookiec; 4080 mptti_t *dmap; 4081 uint32_t flags; 4082 pMpi2SGESimple64_t sge; 4083 pMpi2SGEChain64_t sgechain; 4084 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 4085 4086 /* 4087 * Save the number of entries in the DMA 4088 * Scatter/Gather list 4089 */ 4090 cookiec = cmd->cmd_cookiec; 4091 4092 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec)); 4093 4094 /* 4095 * Set read/write bit in control. 4096 */ 4097 if (cmd->cmd_flags & CFLAG_DMASEND) { 4098 *control |= MPI2_SCSIIO_CONTROL_WRITE; 4099 } else { 4100 *control |= MPI2_SCSIIO_CONTROL_READ; 4101 } 4102 4103 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 4104 4105 /* 4106 * We have 2 cases here. First where we can fit all the 4107 * SG elements into the main frame, and the case 4108 * where we can't. 4109 * If we have more cookies than we can attach to a frame 4110 * we will need to use a chain element to point 4111 * a location of memory where the rest of the S/G 4112 * elements reside. 4113 */ 4114 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 4115 dmap = cmd->cmd_sg; 4116 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4117 while (cookiec--) { 4118 ddi_put32(acc_hdl, 4119 &sge->Address.Low, dmap->addr.address64.Low); 4120 ddi_put32(acc_hdl, 4121 &sge->Address.High, dmap->addr.address64.High); 4122 ddi_put32(acc_hdl, &sge->FlagsLength, 4123 dmap->count); 4124 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4125 flags |= ((uint32_t) 4126 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4127 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4128 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4129 MPI2_SGE_FLAGS_SHIFT); 4130 4131 /* 4132 * If this is the last cookie, we set the flags 4133 * to indicate so 4134 */ 4135 if (cookiec == 0) { 4136 flags |= 4137 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 4138 | MPI2_SGE_FLAGS_END_OF_BUFFER 4139 | MPI2_SGE_FLAGS_END_OF_LIST) << 4140 MPI2_SGE_FLAGS_SHIFT); 4141 } 4142 if (cmd->cmd_flags & CFLAG_DMASEND) { 4143 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4144 MPI2_SGE_FLAGS_SHIFT); 4145 } else { 4146 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4147 MPI2_SGE_FLAGS_SHIFT); 4148 } 4149 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4150 dmap++; 4151 sge++; 4152 } 4153 } else { 4154 /* 4155 * Hereby we start to deal with multiple frames. 4156 * The process is as follows: 4157 * 1. Determine how many frames are needed for SGL element 4158 * storage; Note that all frames are stored in contiguous 4159 * memory space and in 64-bit DMA mode each element is 4160 * 3 double-words (12 bytes) long. 4161 * 2. Fill up the main frame. We need to do this separately 4162 * since it contains the SCSI IO request header and needs 4163 * dedicated processing. Note that the last 4 double-words 4164 * of the SCSI IO header is for SGL element storage 4165 * (MPI2_SGE_IO_UNION). 4166 * 3. Fill the chain element in the main frame, so the DMA 4167 * engine can use the following frames. 4168 * 4. Enter a loop to fill the remaining frames. Note that the 4169 * last frame contains no chain element. The remaining 4170 * frames go into the mpt SGL buffer allocated on the fly, 4171 * not immediately following the main message frame, as in 4172 * Gen1. 4173 * Some restrictions: 4174 * 1. For 64-bit DMA, the simple element and chain element 4175 * are both of 3 double-words (12 bytes) in size, even 4176 * though all frames are stored in the first 4G of mem 4177 * range and the higher 32-bits of the address are always 0. 4178 * 2. On some controllers (like the 1064/1068), a frame can 4179 * hold SGL elements with the last 1 or 2 double-words 4180 * (4 or 8 bytes) un-used. On these controllers, we should 4181 * recognize that there's not enough room for another SGL 4182 * element and move the sge pointer to the next frame. 4183 */ 4184 int i, j, k, l, frames, sgemax; 4185 int temp; 4186 uint8_t chainflags; 4187 uint16_t chainlength; 4188 mptsas_cache_frames_t *p; 4189 4190 /* 4191 * Sgemax is the number of SGE's that will fit 4192 * each extra frame and frames is total 4193 * number of frames we'll need. 1 sge entry per 4194 * frame is reseverd for the chain element thus the -1 below. 4195 */ 4196 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4197 - 1); 4198 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4199 4200 /* 4201 * A little check to see if we need to round up the number 4202 * of frames we need 4203 */ 4204 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4205 sgemax) > 1) { 4206 frames = (temp + 1); 4207 } else { 4208 frames = temp; 4209 } 4210 dmap = cmd->cmd_sg; 4211 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4212 4213 /* 4214 * First fill in the main frame 4215 */ 4216 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) { 4217 ddi_put32(acc_hdl, &sge->Address.Low, 4218 dmap->addr.address64.Low); 4219 ddi_put32(acc_hdl, &sge->Address.High, 4220 dmap->addr.address64.High); 4221 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count); 4222 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4223 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4224 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4225 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4226 MPI2_SGE_FLAGS_SHIFT); 4227 4228 /* 4229 * If this is the last SGE of this frame 4230 * we set the end of list flag 4231 */ 4232 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) { 4233 flags |= ((uint32_t) 4234 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4235 MPI2_SGE_FLAGS_SHIFT); 4236 } 4237 if (cmd->cmd_flags & CFLAG_DMASEND) { 4238 flags |= 4239 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4240 MPI2_SGE_FLAGS_SHIFT); 4241 } else { 4242 flags |= 4243 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4244 MPI2_SGE_FLAGS_SHIFT); 4245 } 4246 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4247 dmap++; 4248 sge++; 4249 } 4250 4251 /* 4252 * Fill in the chain element in the main frame. 4253 * About calculation on ChainOffset: 4254 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4255 * in the end reserved for SGL element storage 4256 * (MPI2_SGE_IO_UNION); we should count it in our 4257 * calculation. See its definition in the header file. 4258 * 2. Constant j is the counter of the current SGL element 4259 * that will be processed, and (j - 1) is the number of 4260 * SGL elements that have been processed (stored in the 4261 * main frame). 4262 * 3. ChainOffset value should be in units of double-words (4 4263 * bytes) so the last value should be divided by 4. 4264 */ 4265 ddi_put8(acc_hdl, &frame->ChainOffset, 4266 (sizeof (MPI2_SCSI_IO_REQUEST) - 4267 sizeof (MPI2_SGE_IO_UNION) + 4268 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4269 sgechain = (pMpi2SGEChain64_t)sge; 4270 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4271 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4272 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4273 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4274 4275 /* 4276 * The size of the next frame is the accurate size of space 4277 * (in bytes) used to store the SGL elements. j is the counter 4278 * of SGL elements. (j - 1) is the number of SGL elements that 4279 * have been processed (stored in frames). 4280 */ 4281 if (frames >= 2) { 4282 chainlength = mpt->m_req_frame_size / 4283 sizeof (MPI2_SGE_SIMPLE64) * 4284 sizeof (MPI2_SGE_SIMPLE64); 4285 } else { 4286 chainlength = ((cookiec - (j - 1)) * 4287 sizeof (MPI2_SGE_SIMPLE64)); 4288 } 4289 4290 p = cmd->cmd_extra_frames; 4291 4292 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4293 ddi_put32(acc_hdl, &sgechain->Address.Low, 4294 p->m_phys_addr); 4295 /* SGL is allocated in the first 4G mem range */ 4296 ddi_put32(acc_hdl, &sgechain->Address.High, 0); 4297 4298 /* 4299 * If there are more than 2 frames left we have to 4300 * fill in the next chain offset to the location of 4301 * the chain element in the next frame. 4302 * sgemax is the number of simple elements in an extra 4303 * frame. Note that the value NextChainOffset should be 4304 * in double-words (4 bytes). 4305 */ 4306 if (frames >= 2) { 4307 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4308 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4309 } else { 4310 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4311 } 4312 4313 /* 4314 * Jump to next frame; 4315 * Starting here, chain buffers go into the per command SGL. 4316 * This buffer is allocated when chain buffers are needed. 4317 */ 4318 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4319 i = cookiec; 4320 4321 /* 4322 * Start filling in frames with SGE's. If we 4323 * reach the end of frame and still have SGE's 4324 * to fill we need to add a chain element and 4325 * use another frame. j will be our counter 4326 * for what cookie we are at and i will be 4327 * the total cookiec. k is the current frame 4328 */ 4329 for (k = 1; k <= frames; k++) { 4330 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4331 4332 /* 4333 * If we have reached the end of frame 4334 * and we have more SGE's to fill in 4335 * we have to fill the final entry 4336 * with a chain element and then 4337 * continue to the next frame 4338 */ 4339 if ((l == (sgemax + 1)) && (k != frames)) { 4340 sgechain = (pMpi2SGEChain64_t)sge; 4341 j--; 4342 chainflags = ( 4343 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4344 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4345 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4346 ddi_put8(p->m_acc_hdl, 4347 &sgechain->Flags, chainflags); 4348 /* 4349 * k is the frame counter and (k + 1) 4350 * is the number of the next frame. 4351 * Note that frames are in contiguous 4352 * memory space. 4353 */ 4354 ddi_put32(p->m_acc_hdl, 4355 &sgechain->Address.Low, 4356 (p->m_phys_addr + 4357 (mpt->m_req_frame_size * k))); 4358 ddi_put32(p->m_acc_hdl, 4359 &sgechain->Address.High, 0); 4360 4361 /* 4362 * If there are more than 2 frames left 4363 * we have to next chain offset to 4364 * the location of the chain element 4365 * in the next frame and fill in the 4366 * length of the next chain 4367 */ 4368 if ((frames - k) >= 2) { 4369 ddi_put8(p->m_acc_hdl, 4370 &sgechain->NextChainOffset, 4371 (sgemax * 4372 sizeof (MPI2_SGE_SIMPLE64)) 4373 >> 2); 4374 ddi_put16(p->m_acc_hdl, 4375 &sgechain->Length, 4376 mpt->m_req_frame_size / 4377 sizeof (MPI2_SGE_SIMPLE64) * 4378 sizeof (MPI2_SGE_SIMPLE64)); 4379 } else { 4380 /* 4381 * This is the last frame. Set 4382 * the NextChainOffset to 0 and 4383 * Length is the total size of 4384 * all remaining simple elements 4385 */ 4386 ddi_put8(p->m_acc_hdl, 4387 &sgechain->NextChainOffset, 4388 0); 4389 ddi_put16(p->m_acc_hdl, 4390 &sgechain->Length, 4391 (cookiec - j) * 4392 sizeof (MPI2_SGE_SIMPLE64)); 4393 } 4394 4395 /* Jump to the next frame */ 4396 sge = (pMpi2SGESimple64_t) 4397 ((char *)p->m_frames_addr + 4398 (int)mpt->m_req_frame_size * k); 4399 4400 continue; 4401 } 4402 4403 ddi_put32(p->m_acc_hdl, 4404 &sge->Address.Low, 4405 dmap->addr.address64.Low); 4406 ddi_put32(p->m_acc_hdl, 4407 &sge->Address.High, 4408 dmap->addr.address64.High); 4409 ddi_put32(p->m_acc_hdl, 4410 &sge->FlagsLength, dmap->count); 4411 flags = ddi_get32(p->m_acc_hdl, 4412 &sge->FlagsLength); 4413 flags |= ((uint32_t)( 4414 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4415 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4416 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4417 MPI2_SGE_FLAGS_SHIFT); 4418 4419 /* 4420 * If we are at the end of the frame and 4421 * there is another frame to fill in 4422 * we set the last simple element as last 4423 * element 4424 */ 4425 if ((l == sgemax) && (k != frames)) { 4426 flags |= ((uint32_t) 4427 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4428 MPI2_SGE_FLAGS_SHIFT); 4429 } 4430 4431 /* 4432 * If this is the final cookie we 4433 * indicate it by setting the flags 4434 */ 4435 if (j == i) { 4436 flags |= ((uint32_t) 4437 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4438 MPI2_SGE_FLAGS_END_OF_BUFFER | 4439 MPI2_SGE_FLAGS_END_OF_LIST) << 4440 MPI2_SGE_FLAGS_SHIFT); 4441 } 4442 if (cmd->cmd_flags & CFLAG_DMASEND) { 4443 flags |= 4444 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4445 MPI2_SGE_FLAGS_SHIFT); 4446 } else { 4447 flags |= 4448 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4449 MPI2_SGE_FLAGS_SHIFT); 4450 } 4451 ddi_put32(p->m_acc_hdl, 4452 &sge->FlagsLength, flags); 4453 dmap++; 4454 sge++; 4455 } 4456 } 4457 4458 /* 4459 * Sync DMA with the chain buffers that were just created 4460 */ 4461 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4462 } 4463} 4464 4465/* 4466 * Interrupt handling 4467 * Utility routine. Poll for status of a command sent to HBA 4468 * without interrupts (a FLAG_NOINTR command). 4469 */ 4470int 4471mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 4472{ 4473 int rval = TRUE; 4474 4475 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 4476 4477 /* 4478 * In order to avoid using m_mutex in ISR(a new separate mutex 4479 * m_intr_mutex is introduced) and keep the same lock logic, 4480 * the m_intr_mutex should be used to protect the getting and 4481 * setting of the ReplyDescriptorIndex. 4482 * 4483 * Since the m_intr_mutex would be released during processing the poll 4484 * cmd, so we should set the poll flag earlier here to make sure the 4485 * polled cmd be handled in this thread/context. A side effect is other 4486 * cmds during the period between the flag set and reset are also 4487 * handled in this thread and not the ISR. Since the poll cmd is not 4488 * so common, so the performance degradation in this case is not a big 4489 * issue. 4490 */ 4491 mutex_enter(&mpt->m_intr_mutex); 4492 mpt->m_polled_intr = 1; 4493 mutex_exit(&mpt->m_intr_mutex); 4494 4495 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 4496 mptsas_restart_hba(mpt); 4497 } 4498 4499 /* 4500 * Wait, using drv_usecwait(), long enough for the command to 4501 * reasonably return from the target if the target isn't 4502 * "dead". A polled command may well be sent from scsi_poll, and 4503 * there are retries built in to scsi_poll if the transport 4504 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 4505 * and retries the transport up to scsi_poll_busycnt times 4506 * (currently 60) if 4507 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 4508 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 4509 * 4510 * limit the waiting to avoid a hang in the event that the 4511 * cmd never gets started but we are still receiving interrupts 4512 */ 4513 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 4514 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 4515 NDBG5(("mptsas_poll: command incomplete")); 4516 rval = FALSE; 4517 break; 4518 } 4519 } 4520 4521 mutex_enter(&mpt->m_intr_mutex); 4522 mpt->m_polled_intr = 0; 4523 mutex_exit(&mpt->m_intr_mutex); 4524 4525 if (rval == FALSE) { 4526 4527 /* 4528 * this isn't supposed to happen, the hba must be wedged 4529 * Mark this cmd as a timeout. 4530 */ 4531 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 4532 (STAT_TIMEOUT|STAT_ABORTED)); 4533 4534 if (poll_cmd->cmd_queued == FALSE) { 4535 4536 NDBG5(("mptsas_poll: not on waitq")); 4537 4538 poll_cmd->cmd_pkt->pkt_state |= 4539 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 4540 } else { 4541 4542 /* find and remove it from the waitq */ 4543 NDBG5(("mptsas_poll: delete from waitq")); 4544 mptsas_waitq_delete(mpt, poll_cmd); 4545 } 4546 4547 } 4548 mptsas_fma_check(mpt, poll_cmd); 4549 NDBG5(("mptsas_poll: done")); 4550 return (rval); 4551} 4552 4553/* 4554 * Used for polling cmds and TM function 4555 */ 4556static int 4557mptsas_wait_intr(mptsas_t *mpt, int polltime) 4558{ 4559 int cnt; 4560 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 4561 Mpi2ReplyDescriptorsUnion_t reply_desc_union_v; 4562 uint32_t int_mask; 4563 uint8_t reply_type; 4564 4565 NDBG5(("mptsas_wait_intr")); 4566 4567 4568 /* 4569 * Get the current interrupt mask and disable interrupts. When 4570 * re-enabling ints, set mask to saved value. 4571 */ 4572 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 4573 MPTSAS_DISABLE_INTR(mpt); 4574 4575 /* 4576 * Keep polling for at least (polltime * 1000) seconds 4577 */ 4578 for (cnt = 0; cnt < polltime; cnt++) { 4579 mutex_enter(&mpt->m_intr_mutex); 4580 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 4581 DDI_DMA_SYNC_FORCPU); 4582 4583 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 4584 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 4585 4586 if (ddi_get32(mpt->m_acc_post_queue_hdl, 4587 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 4588 ddi_get32(mpt->m_acc_post_queue_hdl, 4589 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 4590 mutex_exit(&mpt->m_intr_mutex); 4591 drv_usecwait(1000); 4592 continue; 4593 } 4594 4595 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 4596 &reply_desc_union->Default.ReplyFlags); 4597 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 4598 reply_desc_union_v.Default.ReplyFlags = reply_type; 4599 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 4600 reply_desc_union_v.SCSIIOSuccess.SMID = 4601 ddi_get16(mpt->m_acc_post_queue_hdl, 4602 &reply_desc_union->SCSIIOSuccess.SMID); 4603 } else if (reply_type == 4604 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 4605 reply_desc_union_v.AddressReply.ReplyFrameAddress = 4606 ddi_get32(mpt->m_acc_post_queue_hdl, 4607 &reply_desc_union->AddressReply.ReplyFrameAddress); 4608 reply_desc_union_v.AddressReply.SMID = 4609 ddi_get16(mpt->m_acc_post_queue_hdl, 4610 &reply_desc_union->AddressReply.SMID); 4611 } 4612 /* 4613 * Clear the reply descriptor for re-use and increment 4614 * index. 4615 */ 4616 ddi_put64(mpt->m_acc_post_queue_hdl, 4617 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 4618 0xFFFFFFFFFFFFFFFF); 4619 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 4620 DDI_DMA_SYNC_FORDEV); 4621 4622 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 4623 mpt->m_post_index = 0; 4624 } 4625 4626 /* 4627 * Update the global reply index 4628 */ 4629 ddi_put32(mpt->m_datap, 4630 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 4631 mutex_exit(&mpt->m_intr_mutex); 4632 4633 /* 4634 * The reply is valid, process it according to its 4635 * type. 4636 */ 4637 mptsas_process_intr(mpt, &reply_desc_union_v); 4638 4639 4640 /* 4641 * Re-enable interrupts and quit. 4642 */ 4643 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 4644 int_mask); 4645 return (TRUE); 4646 4647 } 4648 4649 /* 4650 * Clear polling flag, re-enable interrupts and quit. 4651 */ 4652 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 4653 return (FALSE); 4654} 4655 4656/* 4657 * For fastpath, the m_intr_mutex should be held from the begining to the end, 4658 * so we only treat those cmds that need not release m_intr_mutex(even just for 4659 * a moment) as candidate for fast processing. otherwise, we don't handle them 4660 * and just return, then in ISR, those cmds would be handled later with m_mutex 4661 * held and m_intr_mutex not held. 4662 */ 4663static int 4664mptsas_handle_io_fastpath(mptsas_t *mpt, 4665 uint16_t SMID) 4666{ 4667 mptsas_slots_t *slots = mpt->m_active; 4668 mptsas_cmd_t *cmd = NULL; 4669 struct scsi_pkt *pkt; 4670 4671 /* 4672 * This is a success reply so just complete the IO. First, do a sanity 4673 * check on the SMID. The final slot is used for TM requests, which 4674 * would not come into this reply handler. 4675 */ 4676 if ((SMID == 0) || (SMID > slots->m_n_slots)) { 4677 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 4678 SMID); 4679 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4680 return (TRUE); 4681 } 4682 4683 cmd = slots->m_slot[SMID]; 4684 4685 /* 4686 * print warning and return if the slot is empty 4687 */ 4688 if (cmd == NULL) { 4689 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 4690 "in slot %d", SMID); 4691 return (TRUE); 4692 } 4693 4694 pkt = CMD2PKT(cmd); 4695 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 4696 STATE_GOT_STATUS); 4697 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4698 pkt->pkt_state |= STATE_XFERRED_DATA; 4699 } 4700 pkt->pkt_resid = 0; 4701 4702 /* 4703 * If the cmd is a IOC, or a passthrough, then we don't process it in 4704 * fastpath, and later it would be handled by mptsas_process_intr() 4705 * with m_mutex protected. 4706 */ 4707 if (cmd->cmd_flags & (CFLAG_PASSTHRU | CFLAG_CMDIOC)) { 4708 return (FALSE); 4709 } else { 4710 mptsas_remove_cmd0(mpt, cmd); 4711 } 4712 4713 if (cmd->cmd_flags & CFLAG_RETRY) { 4714 /* 4715 * The target returned QFULL or busy, do not add tihs 4716 * pkt to the doneq since the hba will retry 4717 * this cmd. 4718 * 4719 * The pkt has already been resubmitted in 4720 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4721 * Remove this cmd_flag here. 4722 */ 4723 cmd->cmd_flags &= ~CFLAG_RETRY; 4724 } else { 4725 mptsas_doneq_add0(mpt, cmd); 4726 } 4727 4728 /* 4729 * In fastpath, the cmd should only be a context reply, so just check 4730 * the post queue of the reply descriptor and the dmahandle of the cmd 4731 * is enough. No sense data in this case and no need to check the dma 4732 * handle where sense data dma info is saved, the dma handle of the 4733 * reply frame, and the dma handle of the reply free queue. 4734 * For the dma handle of the request queue. Check fma here since we 4735 * are sure the request must have already been sent/DMAed correctly. 4736 * otherwise checking in mptsas_scsi_start() is not correct since 4737 * at that time the dma may not start. 4738 */ 4739 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 4740 DDI_SUCCESS) || 4741 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 4742 DDI_SUCCESS)) { 4743 ddi_fm_service_impact(mpt->m_dip, 4744 DDI_SERVICE_UNAFFECTED); 4745 pkt->pkt_reason = CMD_TRAN_ERR; 4746 pkt->pkt_statistics = 0; 4747 } 4748 if (cmd->cmd_dmahandle && 4749 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 4750 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4751 pkt->pkt_reason = CMD_TRAN_ERR; 4752 pkt->pkt_statistics = 0; 4753 } 4754 if ((cmd->cmd_extra_frames && 4755 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 4756 DDI_SUCCESS) || 4757 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 4758 DDI_SUCCESS)))) { 4759 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4760 pkt->pkt_reason = CMD_TRAN_ERR; 4761 pkt->pkt_statistics = 0; 4762 } 4763 4764 return (TRUE); 4765} 4766 4767static void 4768mptsas_handle_scsi_io_success(mptsas_t *mpt, 4769 pMpi2ReplyDescriptorsUnion_t reply_desc) 4770{ 4771 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 4772 uint16_t SMID; 4773 mptsas_slots_t *slots = mpt->m_active; 4774 mptsas_cmd_t *cmd = NULL; 4775 struct scsi_pkt *pkt; 4776 4777 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 4778 SMID = scsi_io_success->SMID; 4779 4780 /* 4781 * This is a success reply so just complete the IO. First, do a sanity 4782 * check on the SMID. The final slot is used for TM requests, which 4783 * would not come into this reply handler. 4784 */ 4785 if ((SMID == 0) || (SMID > slots->m_n_slots)) { 4786 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 4787 SMID); 4788 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4789 return; 4790 } 4791 4792 cmd = slots->m_slot[SMID]; 4793 4794 /* 4795 * print warning and return if the slot is empty 4796 */ 4797 if (cmd == NULL) { 4798 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 4799 "in slot %d", SMID); 4800 return; 4801 } 4802 4803 pkt = CMD2PKT(cmd); 4804 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 4805 STATE_GOT_STATUS); 4806 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4807 pkt->pkt_state |= STATE_XFERRED_DATA; 4808 } 4809 pkt->pkt_resid = 0; 4810 4811 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 4812 cmd->cmd_flags |= CFLAG_FINISHED; 4813 cv_broadcast(&mpt->m_passthru_cv); 4814 return; 4815 } else { 4816 mptsas_remove_cmd(mpt, cmd); 4817 } 4818 4819 if (cmd->cmd_flags & CFLAG_RETRY) { 4820 /* 4821 * The target returned QFULL or busy, do not add tihs 4822 * pkt to the doneq since the hba will retry 4823 * this cmd. 4824 * 4825 * The pkt has already been resubmitted in 4826 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4827 * Remove this cmd_flag here. 4828 */ 4829 cmd->cmd_flags &= ~CFLAG_RETRY; 4830 } else { 4831 mptsas_doneq_add(mpt, cmd); 4832 } 4833} 4834 4835static void 4836mptsas_handle_address_reply(mptsas_t *mpt, 4837 pMpi2ReplyDescriptorsUnion_t reply_desc) 4838{ 4839 pMpi2AddressReplyDescriptor_t address_reply; 4840 pMPI2DefaultReply_t reply; 4841 mptsas_fw_diagnostic_buffer_t *pBuffer; 4842 uint32_t reply_addr; 4843 uint16_t SMID, iocstatus; 4844 mptsas_slots_t *slots = mpt->m_active; 4845 mptsas_cmd_t *cmd = NULL; 4846 uint8_t function, buffer_type; 4847 m_replyh_arg_t *args; 4848 int reply_frame_no; 4849 4850 ASSERT(mutex_owned(&mpt->m_mutex)); 4851 4852 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 4853 4854 reply_addr = address_reply->ReplyFrameAddress; 4855 SMID = address_reply->SMID; 4856 /* 4857 * If reply frame is not in the proper range we should ignore this 4858 * message and exit the interrupt handler. 4859 */ 4860 if ((reply_addr < mpt->m_reply_frame_dma_addr) || 4861 (reply_addr >= (mpt->m_reply_frame_dma_addr + 4862 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 4863 ((reply_addr - mpt->m_reply_frame_dma_addr) % 4864 mpt->m_reply_frame_size != 0)) { 4865 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 4866 "address 0x%x\n", reply_addr); 4867 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4868 return; 4869 } 4870 4871 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 4872 DDI_DMA_SYNC_FORCPU); 4873 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 4874 mpt->m_reply_frame_dma_addr)); 4875 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 4876 4877 /* 4878 * don't get slot information and command for events since these values 4879 * don't exist 4880 */ 4881 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 4882 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 4883 /* 4884 * This could be a TM reply, which use the last allocated SMID, 4885 * so allow for that. 4886 */ 4887 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) { 4888 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 4889 "%d\n", SMID); 4890 ddi_fm_service_impact(mpt->m_dip, 4891 DDI_SERVICE_UNAFFECTED); 4892 return; 4893 } 4894 4895 cmd = slots->m_slot[SMID]; 4896 4897 /* 4898 * print warning and return if the slot is empty 4899 */ 4900 if (cmd == NULL) { 4901 mptsas_log(mpt, CE_WARN, "?NULL command for address " 4902 "reply in slot %d", SMID); 4903 return; 4904 } 4905 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 4906 (cmd->cmd_flags & CFLAG_CONFIG) || 4907 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 4908 cmd->cmd_rfm = reply_addr; 4909 cmd->cmd_flags |= CFLAG_FINISHED; 4910 cv_broadcast(&mpt->m_passthru_cv); 4911 cv_broadcast(&mpt->m_config_cv); 4912 cv_broadcast(&mpt->m_fw_diag_cv); 4913 return; 4914 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 4915 mptsas_remove_cmd(mpt, cmd); 4916 } 4917 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 4918 } 4919 /* 4920 * Depending on the function, we need to handle 4921 * the reply frame (and cmd) differently. 4922 */ 4923 switch (function) { 4924 case MPI2_FUNCTION_SCSI_IO_REQUEST: 4925 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 4926 break; 4927 case MPI2_FUNCTION_SCSI_TASK_MGMT: 4928 cmd->cmd_rfm = reply_addr; 4929 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 4930 cmd); 4931 break; 4932 case MPI2_FUNCTION_FW_DOWNLOAD: 4933 cmd->cmd_flags |= CFLAG_FINISHED; 4934 cv_signal(&mpt->m_fw_cv); 4935 break; 4936 case MPI2_FUNCTION_EVENT_NOTIFICATION: 4937 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) / 4938 mpt->m_reply_frame_size; 4939 args = &mpt->m_replyh_args[reply_frame_no]; 4940 args->mpt = (void *)mpt; 4941 args->rfm = reply_addr; 4942 4943 /* 4944 * Record the event if its type is enabled in 4945 * this mpt instance by ioctl. 4946 */ 4947 mptsas_record_event(args); 4948 4949 /* 4950 * Handle time critical events 4951 * NOT_RESPONDING/ADDED only now 4952 */ 4953 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 4954 /* 4955 * Would not return main process, 4956 * just let taskq resolve ack action 4957 * and ack would be sent in taskq thread 4958 */ 4959 NDBG20(("send mptsas_handle_event_sync success")); 4960 } 4961 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 4962 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 4963 mptsas_log(mpt, CE_WARN, "No memory available" 4964 "for dispatch taskq"); 4965 /* 4966 * Return the reply frame to the free queue. 4967 */ 4968 ddi_put32(mpt->m_acc_free_queue_hdl, 4969 &((uint32_t *)(void *) 4970 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 4971 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 4972 DDI_DMA_SYNC_FORDEV); 4973 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 4974 mpt->m_free_index = 0; 4975 } 4976 4977 ddi_put32(mpt->m_datap, 4978 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 4979 } 4980 return; 4981 case MPI2_FUNCTION_DIAG_BUFFER_POST: 4982 /* 4983 * If SMID is 0, this implies that the reply is due to a 4984 * release function with a status that the buffer has been 4985 * released. Set the buffer flags accordingly. 4986 */ 4987 if (SMID == 0) { 4988 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 4989 &reply->IOCStatus); 4990 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 4991 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 4992 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 4993 pBuffer = 4994 &mpt->m_fw_diag_buffer_list[buffer_type]; 4995 pBuffer->valid_data = TRUE; 4996 pBuffer->owned_by_firmware = FALSE; 4997 pBuffer->immediate = FALSE; 4998 } 4999 } else { 5000 /* 5001 * Normal handling of diag post reply with SMID. 5002 */ 5003 cmd = slots->m_slot[SMID]; 5004 5005 /* 5006 * print warning and return if the slot is empty 5007 */ 5008 if (cmd == NULL) { 5009 mptsas_log(mpt, CE_WARN, "?NULL command for " 5010 "address reply in slot %d", SMID); 5011 return; 5012 } 5013 cmd->cmd_rfm = reply_addr; 5014 cmd->cmd_flags |= CFLAG_FINISHED; 5015 cv_broadcast(&mpt->m_fw_diag_cv); 5016 } 5017 return; 5018 default: 5019 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 5020 break; 5021 } 5022 5023 /* 5024 * Return the reply frame to the free queue. 5025 */ 5026 ddi_put32(mpt->m_acc_free_queue_hdl, 5027 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 5028 reply_addr); 5029 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5030 DDI_DMA_SYNC_FORDEV); 5031 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5032 mpt->m_free_index = 0; 5033 } 5034 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 5035 mpt->m_free_index); 5036 5037 if (cmd->cmd_flags & CFLAG_FW_CMD) 5038 return; 5039 5040 if (cmd->cmd_flags & CFLAG_RETRY) { 5041 /* 5042 * The target returned QFULL or busy, do not add tihs 5043 * pkt to the doneq since the hba will retry 5044 * this cmd. 5045 * 5046 * The pkt has already been resubmitted in 5047 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5048 * Remove this cmd_flag here. 5049 */ 5050 cmd->cmd_flags &= ~CFLAG_RETRY; 5051 } else { 5052 mptsas_doneq_add(mpt, cmd); 5053 } 5054} 5055 5056static void 5057mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 5058 mptsas_cmd_t *cmd) 5059{ 5060 uint8_t scsi_status, scsi_state; 5061 uint16_t ioc_status; 5062 uint32_t xferred, sensecount, responsedata, loginfo = 0; 5063 struct scsi_pkt *pkt; 5064 struct scsi_arq_status *arqstat; 5065 struct buf *bp; 5066 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5067 uint8_t *sensedata = NULL; 5068 5069 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 5070 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 5071 bp = cmd->cmd_ext_arq_buf; 5072 } else { 5073 bp = cmd->cmd_arq_buf; 5074 } 5075 5076 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 5077 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5078 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 5079 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 5080 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 5081 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 5082 &reply->ResponseInfo); 5083 5084 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 5085 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 5086 &reply->IOCLogInfo); 5087 mptsas_log(mpt, CE_NOTE, 5088 "?Log info 0x%x received for target %d.\n" 5089 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5090 loginfo, Tgt(cmd), scsi_status, ioc_status, 5091 scsi_state); 5092 } 5093 5094 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5095 scsi_status, ioc_status, scsi_state)); 5096 5097 pkt = CMD2PKT(cmd); 5098 *(pkt->pkt_scbp) = scsi_status; 5099 5100 if (loginfo == 0x31170000) { 5101 /* 5102 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5103 * 0x31170000 comes, that means the device missing delay 5104 * is in progressing, the command need retry later. 5105 */ 5106 *(pkt->pkt_scbp) = STATUS_BUSY; 5107 return; 5108 } 5109 5110 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5111 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5112 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5113 pkt->pkt_reason = CMD_INCOMPLETE; 5114 pkt->pkt_state |= STATE_GOT_BUS; 5115 mutex_enter(&ptgt->m_tgt_intr_mutex); 5116 if (ptgt->m_reset_delay == 0) { 5117 mptsas_set_throttle(mpt, ptgt, 5118 DRAIN_THROTTLE); 5119 } 5120 mutex_exit(&ptgt->m_tgt_intr_mutex); 5121 return; 5122 } 5123 5124 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5125 responsedata &= 0x000000FF; 5126 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5127 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5128 pkt->pkt_reason = CMD_TLR_OFF; 5129 return; 5130 } 5131 } 5132 5133 5134 switch (scsi_status) { 5135 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5136 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5137 arqstat = (void*)(pkt->pkt_scbp); 5138 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5139 (pkt->pkt_scbp)); 5140 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5141 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5142 if (cmd->cmd_flags & CFLAG_XARQ) { 5143 pkt->pkt_state |= STATE_XARQ_DONE; 5144 } 5145 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5146 pkt->pkt_state |= STATE_XFERRED_DATA; 5147 } 5148 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5149 arqstat->sts_rqpkt_state = pkt->pkt_state; 5150 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5151 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5152 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5153 5154 bcopy((uchar_t *)bp->b_un.b_addr, sensedata, 5155 ((cmd->cmd_rqslen >= sensecount) ? sensecount : 5156 cmd->cmd_rqslen)); 5157 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount); 5158 cmd->cmd_flags |= CFLAG_CMDARQ; 5159 /* 5160 * Set proper status for pkt if autosense was valid 5161 */ 5162 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5163 struct scsi_status zero_status = { 0 }; 5164 arqstat->sts_rqpkt_status = zero_status; 5165 } 5166 5167 /* 5168 * ASC=0x47 is parity error 5169 * ASC=0x48 is initiator detected error received 5170 */ 5171 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5172 ((scsi_sense_asc(sensedata) == 0x47) || 5173 (scsi_sense_asc(sensedata) == 0x48))) { 5174 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5175 } 5176 5177 /* 5178 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5179 * ASC/ASCQ=0x25/0x00 means invalid lun 5180 */ 5181 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5182 (scsi_sense_asc(sensedata) == 0x3F) && 5183 (scsi_sense_ascq(sensedata) == 0x0E)) || 5184 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5185 (scsi_sense_asc(sensedata) == 0x25) && 5186 (scsi_sense_ascq(sensedata) == 0x00))) { 5187 mptsas_topo_change_list_t *topo_node = NULL; 5188 5189 topo_node = kmem_zalloc( 5190 sizeof (mptsas_topo_change_list_t), 5191 KM_NOSLEEP); 5192 if (topo_node == NULL) { 5193 mptsas_log(mpt, CE_NOTE, "No memory" 5194 "resource for handle SAS dynamic" 5195 "reconfigure.\n"); 5196 break; 5197 } 5198 topo_node->mpt = mpt; 5199 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5200 topo_node->un.phymask = ptgt->m_phymask; 5201 topo_node->devhdl = ptgt->m_devhdl; 5202 topo_node->object = (void *)ptgt; 5203 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5204 5205 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5206 mptsas_handle_dr, 5207 (void *)topo_node, 5208 DDI_NOSLEEP)) != DDI_SUCCESS) { 5209 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5210 "for handle SAS dynamic reconfigure" 5211 "failed. \n"); 5212 } 5213 } 5214 break; 5215 case MPI2_SCSI_STATUS_GOOD: 5216 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5217 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5218 pkt->pkt_reason = CMD_DEV_GONE; 5219 pkt->pkt_state |= STATE_GOT_BUS; 5220 mutex_enter(&ptgt->m_tgt_intr_mutex); 5221 if (ptgt->m_reset_delay == 0) { 5222 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5223 } 5224 mutex_exit(&ptgt->m_tgt_intr_mutex); 5225 NDBG31(("lost disk for target%d, command:%x", 5226 Tgt(cmd), pkt->pkt_cdbp[0])); 5227 break; 5228 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5229 NDBG31(("data overrun: xferred=%d", xferred)); 5230 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5231 pkt->pkt_reason = CMD_DATA_OVR; 5232 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5233 | STATE_SENT_CMD | STATE_GOT_STATUS 5234 | STATE_XFERRED_DATA); 5235 pkt->pkt_resid = 0; 5236 break; 5237 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5238 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5239 NDBG31(("data underrun: xferred=%d", xferred)); 5240 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5241 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5242 | STATE_SENT_CMD | STATE_GOT_STATUS); 5243 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5244 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5245 pkt->pkt_state |= STATE_XFERRED_DATA; 5246 } 5247 break; 5248 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5249 mptsas_set_pkt_reason(mpt, 5250 cmd, CMD_RESET, STAT_BUS_RESET); 5251 break; 5252 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5253 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5254 mptsas_set_pkt_reason(mpt, 5255 cmd, CMD_RESET, STAT_DEV_RESET); 5256 break; 5257 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5258 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5259 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5260 mptsas_set_pkt_reason(mpt, 5261 cmd, CMD_TERMINATED, STAT_TERMINATED); 5262 break; 5263 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5264 case MPI2_IOCSTATUS_BUSY: 5265 /* 5266 * set throttles to drain 5267 */ 5268 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 5269 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST); 5270 while (ptgt != NULL) { 5271 mutex_enter(&ptgt->m_tgt_intr_mutex); 5272 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5273 mutex_exit(&ptgt->m_tgt_intr_mutex); 5274 5275 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 5276 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 5277 } 5278 5279 /* 5280 * retry command 5281 */ 5282 cmd->cmd_flags |= CFLAG_RETRY; 5283 cmd->cmd_pkt_flags |= FLAG_HEAD; 5284 5285 mutex_exit(&mpt->m_mutex); 5286 (void) mptsas_accept_pkt(mpt, cmd); 5287 mutex_enter(&mpt->m_mutex); 5288 break; 5289 default: 5290 mptsas_log(mpt, CE_WARN, 5291 "unknown ioc_status = %x\n", ioc_status); 5292 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5293 "count = %x, scsi_status = %x", scsi_state, 5294 xferred, scsi_status); 5295 break; 5296 } 5297 break; 5298 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5299 mptsas_handle_qfull(mpt, cmd); 5300 break; 5301 case MPI2_SCSI_STATUS_BUSY: 5302 NDBG31(("scsi_status busy received")); 5303 break; 5304 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5305 NDBG31(("scsi_status reservation conflict received")); 5306 break; 5307 default: 5308 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5309 scsi_status, ioc_status); 5310 mptsas_log(mpt, CE_WARN, 5311 "mptsas_process_intr: invalid scsi status\n"); 5312 break; 5313 } 5314} 5315 5316static void 5317mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5318 mptsas_cmd_t *cmd) 5319{ 5320 uint8_t task_type; 5321 uint16_t ioc_status; 5322 uint32_t log_info; 5323 uint16_t dev_handle; 5324 struct scsi_pkt *pkt = CMD2PKT(cmd); 5325 5326 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5327 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5328 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5329 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5330 5331 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5332 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5333 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5334 task_type, ioc_status, log_info, dev_handle); 5335 pkt->pkt_reason = CMD_INCOMPLETE; 5336 return; 5337 } 5338 5339 switch (task_type) { 5340 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5341 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5342 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5343 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5344 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5345 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5346 break; 5347 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5348 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5349 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5350 /* 5351 * Check for invalid DevHandle of 0 in case application 5352 * sends bad command. DevHandle of 0 could cause problems. 5353 */ 5354 if (dev_handle == 0) { 5355 mptsas_log(mpt, CE_WARN, "!Can't flush target with" 5356 " DevHandle of 0."); 5357 } else { 5358 mptsas_flush_target(mpt, dev_handle, Lun(cmd), 5359 task_type); 5360 } 5361 break; 5362 default: 5363 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5364 task_type); 5365 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5366 break; 5367 } 5368} 5369 5370static void 5371mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5372{ 5373 mptsas_t *mpt = arg->mpt; 5374 uint64_t t = arg->t; 5375 mptsas_cmd_t *cmd; 5376 struct scsi_pkt *pkt; 5377 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5378 5379 mutex_enter(&item->mutex); 5380 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5381 if (!item->doneq) { 5382 cv_wait(&item->cv, &item->mutex); 5383 } 5384 pkt = NULL; 5385 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5386 cmd->cmd_flags |= CFLAG_COMPLETED; 5387 pkt = CMD2PKT(cmd); 5388 } 5389 mutex_exit(&item->mutex); 5390 if (pkt) { 5391 mptsas_pkt_comp(pkt, cmd); 5392 } 5393 mutex_enter(&item->mutex); 5394 } 5395 mutex_exit(&item->mutex); 5396 mutex_enter(&mpt->m_doneq_mutex); 5397 mpt->m_doneq_thread_n--; 5398 cv_broadcast(&mpt->m_doneq_thread_cv); 5399 mutex_exit(&mpt->m_doneq_mutex); 5400} 5401 5402/* 5403 * mpt interrupt handler. 5404 */ 5405static uint_t 5406mptsas_intr(caddr_t arg1, caddr_t arg2) 5407{ 5408 mptsas_t *mpt = (void *)arg1; 5409 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5410 uchar_t did_reply = FALSE; 5411 int i = 0, j; 5412 uint8_t reply_type; 5413 uint16_t SMID; 5414 5415 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5416 5417 /* 5418 * 1. 5419 * To avoid using m_mutex in the ISR(ISR referes not only mptsas_intr, 5420 * but all of the recursive called functions in it. the same below), 5421 * separate mutexs are introduced to protect the elements shown in ISR. 5422 * 3 type of mutex are involved here: 5423 * a)per instance mutex m_intr_mutex. 5424 * b)per target mutex m_tgt_intr_mutex. 5425 * c)mutex that protect the free slot. 5426 * 5427 * a)per instance mutex m_intr_mutex: 5428 * used to protect m_options, m_power, m_waitq, etc that would be 5429 * checked/modified in ISR; protect the getting and setting the reply 5430 * descriptor index; protect the m_slots[]; 5431 * 5432 * b)per target mutex m_tgt_intr_mutex: 5433 * used to protect per target element which has relationship to ISR. 5434 * contention for the new per target mutex is just as high as it in 5435 * sd(7d) driver. 5436 * 5437 * c)mutexs that protect the free slots: 5438 * those mutexs are introduced to minimize the mutex contentions 5439 * between the IO request threads where free slots are allocated 5440 * for sending cmds and ISR where slots holding outstanding cmds 5441 * are returned to the free pool. 5442 * the idea is like this: 5443 * 1) Partition all of the free slot into NCPU groups. For example, 5444 * In system where we have 15 slots, and 4 CPU, then slot s1,s5,s9,s13 5445 * are marked belonging to CPU1, s2,s6,s10,s14 to CPU2, s3,s7,s11,s15 5446 * to CPU3, and s4,s8,s12 to CPU4. 5447 * 2) In each of the group, an alloc/release queue pair is created, 5448 * and both the allocq and the releaseq have a dedicated mutex. 5449 * 3) When init, all of the slots in a CPU group are inserted into the 5450 * allocq of its CPU's pair. 5451 * 4) When doing IO, 5452 * mptsas_scsi_start() 5453 * { 5454 * cpuid = the cpu NO of the cpu where this thread is running on 5455 * retry: 5456 * mutex_enter(&allocq[cpuid]); 5457 * if (get free slot = success) { 5458 * remove the slot from the allocq 5459 * mutex_exit(&allocq[cpuid]); 5460 * return(success); 5461 * } else { // exchange allocq and releaseq and try again 5462 * mutex_enter(&releq[cpuid]); 5463 * exchange the allocq and releaseq of this pair; 5464 * mutex_exit(&releq[cpuid]); 5465 * if (try to get free slot again = success) { 5466 * remove the slot from the allocq 5467 * mutex_exit(&allocq[cpuid]); 5468 * return(success); 5469 * } else { 5470 * MOD(cpuid)++; 5471 * goto retry; 5472 * if (all CPU groups tried) 5473 * mutex_exit(&allocq[cpuid]); 5474 * return(failure); 5475 * } 5476 * } 5477 * } 5478 * ISR() 5479 * { 5480 * cpuid = the CPU group id where the slot sending the 5481 * cmd belongs; 5482 * mutex_enter(&releq[cpuid]); 5483 * remove the slot from the releaseq 5484 * mutex_exit(&releq[cpuid]); 5485 * } 5486 * This way, only when the queue pair doing exchange have mutex 5487 * contentions. 5488 * 5489 * For mutex m_intr_mutex and m_tgt_intr_mutex, there are 2 scenarios: 5490 * 5491 * a)If the elements are only checked but not modified in the ISR, then 5492 * only the places where those elements are modifed(outside of ISR) 5493 * need to be protected by the new introduced mutex. 5494 * For example, data A is only read/checked in ISR, then we need do 5495 * like this: 5496 * In ISR: 5497 * { 5498 * mutex_enter(&new_mutex); 5499 * read(A); 5500 * mutex_exit(&new_mutex); 5501 * //the new_mutex here is either the m_tgt_intr_mutex or 5502 * //the m_intr_mutex. 5503 * } 5504 * In non-ISR 5505 * { 5506 * mutex_enter(&m_mutex); //the stock driver already did this 5507 * mutex_enter(&new_mutex); 5508 * write(A); 5509 * mutex_exit(&new_mutex); 5510 * mutex_exit(&m_mutex); //the stock driver already did this 5511 * 5512 * read(A); 5513 * // read(A) in non-ISR is not required to be protected by new 5514 * // mutex since 'A' has already been protected by m_mutex 5515 * // outside of the ISR 5516 * } 5517 * 5518 * Those fields in mptsas_target_t/ptgt which are only read in ISR 5519 * fall into this catergory. So they, together with the fields which 5520 * are never read in ISR, are not necessary to be protected by 5521 * m_tgt_intr_mutex, don't bother. 5522 * checking of m_waitq also falls into this catergory. so all of the 5523 * place outside of ISR where the m_waitq is modified, such as in 5524 * mptsas_waitq_add(), mptsas_waitq_delete(), mptsas_waitq_rm(), 5525 * m_intr_mutex should be used. 5526 * 5527 * b)If the elements are modified in the ISR, then each place where 5528 * those elements are referred(outside of ISR) need to be protected 5529 * by the new introduced mutex. Of course, if those elements only 5530 * appear in the non-key code path, that is, they don't affect 5531 * performance, then the m_mutex can still be used as before. 5532 * For example, data B is modified in key code path in ISR, and data C 5533 * is modified in non-key code path in ISR, then we can do like this: 5534 * In ISR: 5535 * { 5536 * mutex_enter(&new_mutex); 5537 * wirte(B); 5538 * mutex_exit(&new_mutex); 5539 * if (seldom happen) { 5540 * mutex_enter(&m_mutex); 5541 * write(C); 5542 * mutex_exit(&m_mutex); 5543 * } 5544 * //the new_mutex here is either the m_tgt_intr_mutex or 5545 * //the m_intr_mutex. 5546 * } 5547 * In non-ISR 5548 * { 5549 * mutex_enter(&new_mutex); 5550 * write(B); 5551 * mutex_exit(&new_mutex); 5552 * 5553 * mutex_enter(&new_mutex); 5554 * read(B); 5555 * mutex_exit(&new_mutex); 5556 * // both write(B) and read(B) in non-ISR is required to be 5557 * // protected by new mutex outside of the ISR 5558 * 5559 * mutex_enter(&m_mutex); //the stock driver already did this 5560 * read(C); 5561 * write(C); 5562 * mutex_exit(&m_mutex); //the stock driver already did this 5563 * // both write(C) and read(C) in non-ISR have been already 5564 * // been protected by m_mutex outside of the ISR 5565 * } 5566 * 5567 * For example, ptgt->m_t_ncmds fall into 'B' of this catergory, and 5568 * elements shown in address reply, restart_hba, passthrough, IOC 5569 * fall into 'C' of this catergory. 5570 * 5571 * In any case where mutexs are nested, make sure in the following 5572 * order: 5573 * m_mutex -> m_intr_mutex -> m_tgt_intr_mutex 5574 * m_intr_mutex -> m_tgt_intr_mutex 5575 * m_mutex -> m_intr_mutex 5576 * m_mutex -> m_tgt_intr_mutex 5577 * 5578 * 2. 5579 * Make sure at any time, getting the ReplyDescriptor by m_post_index 5580 * and setting m_post_index to the ReplyDescriptorIndex register are 5581 * atomic. Since m_mutex is not used for this purpose in ISR, the new 5582 * mutex m_intr_mutex must play this role. So mptsas_poll(), where this 5583 * kind of getting/setting is also performed, must use m_intr_mutex. 5584 * Note, since context reply in ISR/process_intr is the only code path 5585 * which affect performance, a fast path is introduced to only handle 5586 * the read/write IO having context reply. For other IOs such as 5587 * passthrough and IOC with context reply and all address reply, we 5588 * use the as-is process_intr() to handle them. In order to keep the 5589 * same semantics in process_intr(), make sure any new mutex is not held 5590 * before enterring it. 5591 */ 5592 5593 mutex_enter(&mpt->m_intr_mutex); 5594 5595 /* 5596 * If interrupts are shared by two channels then check whether this 5597 * interrupt is genuinely for this channel by making sure first the 5598 * chip is in high power state. 5599 */ 5600 if ((mpt->m_options & MPTSAS_OPT_PM) && 5601 (mpt->m_power_level != PM_LEVEL_D0)) { 5602 mutex_exit(&mpt->m_intr_mutex); 5603 return (DDI_INTR_UNCLAIMED); 5604 } 5605 5606 /* 5607 * If polling, interrupt was triggered by some shared interrupt because 5608 * IOC interrupts are disabled during polling, so polling routine will 5609 * handle any replies. Considering this, if polling is happening, 5610 * return with interrupt unclaimed. 5611 */ 5612 if (mpt->m_polled_intr) { 5613 mutex_exit(&mpt->m_intr_mutex); 5614 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5615 return (DDI_INTR_UNCLAIMED); 5616 } 5617 5618 /* 5619 * Read the istat register. 5620 */ 5621 if ((INTPENDING(mpt)) != 0) { 5622 /* 5623 * read fifo until empty. 5624 */ 5625#ifndef __lock_lint 5626 _NOTE(CONSTCOND) 5627#endif 5628 while (TRUE) { 5629 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5630 DDI_DMA_SYNC_FORCPU); 5631 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5632 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5633 5634 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5635 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5636 ddi_get32(mpt->m_acc_post_queue_hdl, 5637 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5638 break; 5639 } 5640 5641 /* 5642 * The reply is valid, process it according to its 5643 * type. Also, set a flag for updating the reply index 5644 * after they've all been processed. 5645 */ 5646 did_reply = TRUE; 5647 5648 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 5649 &reply_desc_union->Default.ReplyFlags); 5650 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 5651 mpt->m_reply[i].Default.ReplyFlags = reply_type; 5652 if (reply_type == 5653 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 5654 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, 5655 &reply_desc_union->SCSIIOSuccess.SMID); 5656 if (mptsas_handle_io_fastpath(mpt, SMID) != 5657 TRUE) { 5658 mpt->m_reply[i].SCSIIOSuccess.SMID = 5659 SMID; 5660 i++; 5661 } 5662 } else if (reply_type == 5663 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 5664 mpt->m_reply[i].AddressReply.ReplyFrameAddress = 5665 ddi_get32(mpt->m_acc_post_queue_hdl, 5666 &reply_desc_union->AddressReply. 5667 ReplyFrameAddress); 5668 mpt->m_reply[i].AddressReply.SMID = 5669 ddi_get16(mpt->m_acc_post_queue_hdl, 5670 &reply_desc_union->AddressReply.SMID); 5671 i++; 5672 } 5673 /* 5674 * Clear the reply descriptor for re-use and increment 5675 * index. 5676 */ 5677 ddi_put64(mpt->m_acc_post_queue_hdl, 5678 &((uint64_t *)(void *)mpt->m_post_queue) 5679 [mpt->m_post_index], 0xFFFFFFFFFFFFFFFF); 5680 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5681 DDI_DMA_SYNC_FORDEV); 5682 5683 /* 5684 * Increment post index and roll over if needed. 5685 */ 5686 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5687 mpt->m_post_index = 0; 5688 } 5689 if (i >= MPI_ADDRESS_COALSCE_MAX) 5690 break; 5691 } 5692 5693 /* 5694 * Update the global reply index if at least one reply was 5695 * processed. 5696 */ 5697 if (did_reply) { 5698 ddi_put32(mpt->m_datap, 5699 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5700 5701 /* 5702 * For fma, only check the PIO is required and enough 5703 * here. Those cases where fastpath is not hit, the 5704 * mptsas_fma_check() check all of the types of 5705 * fma. That is not necessary and sometimes not 5706 * correct. fma check should only be done after 5707 * the PIO and/or dma is performed. 5708 */ 5709 if ((mptsas_check_acc_handle(mpt->m_datap) != 5710 DDI_SUCCESS)) { 5711 ddi_fm_service_impact(mpt->m_dip, 5712 DDI_SERVICE_UNAFFECTED); 5713 } 5714 5715 } 5716 } else { 5717 mutex_exit(&mpt->m_intr_mutex); 5718 return (DDI_INTR_UNCLAIMED); 5719 } 5720 NDBG1(("mptsas_intr complete")); 5721 mutex_exit(&mpt->m_intr_mutex); 5722 5723 /* 5724 * Since most of the cmds(read and write IO with success return.) 5725 * have already been processed in fast path in which the m_mutex 5726 * is not held, handling here the address reply and other context reply 5727 * such as passthrough and IOC cmd with m_mutex held should be a big 5728 * issue for performance. 5729 * If holding m_mutex to process these cmds was still an obvious issue, 5730 * we can process them in a taskq. 5731 */ 5732 for (j = 0; j < i; j++) { 5733 mutex_enter(&mpt->m_mutex); 5734 mptsas_process_intr(mpt, &mpt->m_reply[j]); 5735 mutex_exit(&mpt->m_mutex); 5736 } 5737 5738 /* 5739 * If no helper threads are created, process the doneq in ISR. If 5740 * helpers are created, use the doneq length as a metric to measure the 5741 * load on the interrupt CPU. If it is long enough, which indicates the 5742 * load is heavy, then we deliver the IO completions to the helpers. 5743 * This measurement has some limitations, although it is simple and 5744 * straightforward and works well for most of the cases at present. 5745 */ 5746 if (!mpt->m_doneq_thread_n) { 5747 mptsas_doneq_empty(mpt); 5748 } else { 5749 int helper = 1; 5750 mutex_enter(&mpt->m_intr_mutex); 5751 if (mpt->m_doneq_len <= mpt->m_doneq_length_threshold) 5752 helper = 0; 5753 mutex_exit(&mpt->m_intr_mutex); 5754 if (helper) { 5755 mptsas_deliver_doneq_thread(mpt); 5756 } else { 5757 mptsas_doneq_empty(mpt); 5758 } 5759 } 5760 5761 /* 5762 * If there are queued cmd, start them now. 5763 */ 5764 mutex_enter(&mpt->m_intr_mutex); 5765 if (mpt->m_waitq != NULL) { 5766 mutex_exit(&mpt->m_intr_mutex); 5767 mutex_enter(&mpt->m_mutex); 5768 mptsas_restart_hba(mpt); 5769 mutex_exit(&mpt->m_mutex); 5770 return (DDI_INTR_CLAIMED); 5771 } 5772 mutex_exit(&mpt->m_intr_mutex); 5773 return (DDI_INTR_CLAIMED); 5774} 5775 5776/* 5777 * In ISR, the successfully completed read and write IO are processed in a 5778 * fast path. This function is only used to handle non-fastpath IO, including 5779 * all of the address reply, and the context reply for IOC cmd, passthrough, 5780 * etc. 5781 * This function is also used to process polled cmd. 5782 */ 5783static void 5784mptsas_process_intr(mptsas_t *mpt, 5785 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 5786{ 5787 uint8_t reply_type; 5788 5789 /* 5790 * The reply is valid, process it according to its 5791 * type. Also, set a flag for updated the reply index 5792 * after they've all been processed. 5793 */ 5794 reply_type = reply_desc_union->Default.ReplyFlags; 5795 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 5796 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 5797 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 5798 mptsas_handle_address_reply(mpt, reply_desc_union); 5799 } else { 5800 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 5801 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5802 } 5803} 5804 5805/* 5806 * handle qfull condition 5807 */ 5808static void 5809mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 5810{ 5811 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5812 5813 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 5814 (ptgt->m_qfull_retries == 0)) { 5815 /* 5816 * We have exhausted the retries on QFULL, or, 5817 * the target driver has indicated that it 5818 * wants to handle QFULL itself by setting 5819 * qfull-retries capability to 0. In either case 5820 * we want the target driver's QFULL handling 5821 * to kick in. We do this by having pkt_reason 5822 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 5823 */ 5824 mutex_enter(&ptgt->m_tgt_intr_mutex); 5825 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5826 mutex_exit(&ptgt->m_tgt_intr_mutex); 5827 } else { 5828 mutex_enter(&ptgt->m_tgt_intr_mutex); 5829 if (ptgt->m_reset_delay == 0) { 5830 ptgt->m_t_throttle = 5831 max((ptgt->m_t_ncmds - 2), 0); 5832 } 5833 mutex_exit(&ptgt->m_tgt_intr_mutex); 5834 5835 cmd->cmd_pkt_flags |= FLAG_HEAD; 5836 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 5837 cmd->cmd_flags |= CFLAG_RETRY; 5838 5839 mutex_exit(&mpt->m_mutex); 5840 (void) mptsas_accept_pkt(mpt, cmd); 5841 mutex_enter(&mpt->m_mutex); 5842 5843 /* 5844 * when target gives queue full status with no commands 5845 * outstanding (m_t_ncmds == 0), throttle is set to 0 5846 * (HOLD_THROTTLE), and the queue full handling start 5847 * (see psarc/1994/313); if there are commands outstanding, 5848 * throttle is set to (m_t_ncmds - 2) 5849 */ 5850 mutex_enter(&ptgt->m_tgt_intr_mutex); 5851 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 5852 /* 5853 * By setting throttle to QFULL_THROTTLE, we 5854 * avoid submitting new commands and in 5855 * mptsas_restart_cmd find out slots which need 5856 * their throttles to be cleared. 5857 */ 5858 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 5859 if (mpt->m_restart_cmd_timeid == 0) { 5860 mpt->m_restart_cmd_timeid = 5861 timeout(mptsas_restart_cmd, mpt, 5862 ptgt->m_qfull_retry_interval); 5863 } 5864 } 5865 mutex_exit(&ptgt->m_tgt_intr_mutex); 5866 } 5867} 5868 5869mptsas_phymask_t 5870mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 5871{ 5872 mptsas_phymask_t phy_mask = 0; 5873 uint8_t i = 0; 5874 5875 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 5876 5877 ASSERT(mutex_owned(&mpt->m_mutex)); 5878 5879 /* 5880 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 5881 */ 5882 if (physport == 0xFF) { 5883 return (0); 5884 } 5885 5886 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 5887 if (mpt->m_phy_info[i].attached_devhdl && 5888 (mpt->m_phy_info[i].phy_mask != 0) && 5889 (mpt->m_phy_info[i].port_num == physport)) { 5890 phy_mask = mpt->m_phy_info[i].phy_mask; 5891 break; 5892 } 5893 } 5894 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 5895 mpt->m_instance, physport, phy_mask)); 5896 return (phy_mask); 5897} 5898 5899/* 5900 * mpt free device handle after device gone, by use of passthrough 5901 */ 5902static int 5903mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 5904{ 5905 Mpi2SasIoUnitControlRequest_t req; 5906 Mpi2SasIoUnitControlReply_t rep; 5907 int ret; 5908 5909 ASSERT(mutex_owned(&mpt->m_mutex)); 5910 5911 /* 5912 * Need to compose a SAS IO Unit Control request message 5913 * and call mptsas_do_passthru() function 5914 */ 5915 bzero(&req, sizeof (req)); 5916 bzero(&rep, sizeof (rep)); 5917 5918 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 5919 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 5920 req.DevHandle = LE_16(devhdl); 5921 5922 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 5923 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 5924 if (ret != 0) { 5925 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5926 "Control error %d", ret); 5927 return (DDI_FAILURE); 5928 } 5929 5930 /* do passthrough success, check the ioc status */ 5931 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 5932 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5933 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 5934 return (DDI_FAILURE); 5935 } 5936 5937 return (DDI_SUCCESS); 5938} 5939 5940static void 5941mptsas_update_phymask(mptsas_t *mpt) 5942{ 5943 mptsas_phymask_t mask = 0, phy_mask; 5944 char *phy_mask_name; 5945 uint8_t current_port; 5946 int i, j; 5947 5948 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 5949 5950 ASSERT(mutex_owned(&mpt->m_mutex)); 5951 5952 (void) mptsas_get_sas_io_unit_page(mpt); 5953 5954 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5955 5956 for (i = 0; i < mpt->m_num_phys; i++) { 5957 phy_mask = 0x00; 5958 5959 if (mpt->m_phy_info[i].attached_devhdl == 0) 5960 continue; 5961 5962 bzero(phy_mask_name, sizeof (phy_mask_name)); 5963 5964 current_port = mpt->m_phy_info[i].port_num; 5965 5966 if ((mask & (1 << i)) != 0) 5967 continue; 5968 5969 for (j = 0; j < mpt->m_num_phys; j++) { 5970 if (mpt->m_phy_info[j].attached_devhdl && 5971 (mpt->m_phy_info[j].port_num == current_port)) { 5972 phy_mask |= (1 << j); 5973 } 5974 } 5975 mask = mask | phy_mask; 5976 5977 for (j = 0; j < mpt->m_num_phys; j++) { 5978 if ((phy_mask >> j) & 0x01) { 5979 mpt->m_phy_info[j].phy_mask = phy_mask; 5980 } 5981 } 5982 5983 (void) sprintf(phy_mask_name, "%x", phy_mask); 5984 5985 mutex_exit(&mpt->m_mutex); 5986 /* 5987 * register a iport, if the port has already been existed 5988 * SCSA will do nothing and just return. 5989 */ 5990 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 5991 mutex_enter(&mpt->m_mutex); 5992 } 5993 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5994 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 5995} 5996 5997/* 5998 * mptsas_handle_dr is a task handler for DR, the DR action includes: 5999 * 1. Directly attched Device Added/Removed. 6000 * 2. Expander Device Added/Removed. 6001 * 3. Indirectly Attached Device Added/Expander. 6002 * 4. LUNs of a existing device status change. 6003 * 5. RAID volume created/deleted. 6004 * 6. Member of RAID volume is released because of RAID deletion. 6005 * 7. Physical disks are removed because of RAID creation. 6006 */ 6007static void 6008mptsas_handle_dr(void *args) { 6009 mptsas_topo_change_list_t *topo_node = NULL; 6010 mptsas_topo_change_list_t *save_node = NULL; 6011 mptsas_t *mpt; 6012 dev_info_t *parent = NULL; 6013 mptsas_phymask_t phymask = 0; 6014 char *phy_mask_name; 6015 uint8_t flags = 0, physport = 0xff; 6016 uint8_t port_update = 0; 6017 uint_t event; 6018 6019 topo_node = (mptsas_topo_change_list_t *)args; 6020 6021 mpt = topo_node->mpt; 6022 event = topo_node->event; 6023 flags = topo_node->flags; 6024 6025 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6026 6027 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 6028 6029 switch (event) { 6030 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6031 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6032 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 6033 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6034 /* 6035 * Direct attached or expander attached device added 6036 * into system or a Phys Disk that is being unhidden. 6037 */ 6038 port_update = 1; 6039 } 6040 break; 6041 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6042 /* 6043 * New expander added into system, it must be the head 6044 * of topo_change_list_t 6045 */ 6046 port_update = 1; 6047 break; 6048 default: 6049 port_update = 0; 6050 break; 6051 } 6052 /* 6053 * All cases port_update == 1 may cause initiator port form change 6054 */ 6055 mutex_enter(&mpt->m_mutex); 6056 if (mpt->m_port_chng && port_update) { 6057 /* 6058 * mpt->m_port_chng flag indicates some PHYs of initiator 6059 * port have changed to online. So when expander added or 6060 * directly attached device online event come, we force to 6061 * update port information by issueing SAS IO Unit Page and 6062 * update PHYMASKs. 6063 */ 6064 (void) mptsas_update_phymask(mpt); 6065 mpt->m_port_chng = 0; 6066 6067 } 6068 mutex_exit(&mpt->m_mutex); 6069 while (topo_node) { 6070 phymask = 0; 6071 if (parent == NULL) { 6072 physport = topo_node->un.physport; 6073 event = topo_node->event; 6074 flags = topo_node->flags; 6075 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 6076 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 6077 /* 6078 * For all offline events, phymask is known 6079 */ 6080 phymask = topo_node->un.phymask; 6081 goto find_parent; 6082 } 6083 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6084 goto handle_topo_change; 6085 } 6086 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 6087 phymask = topo_node->un.phymask; 6088 goto find_parent; 6089 } 6090 6091 if ((flags == 6092 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 6093 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 6094 /* 6095 * There is no any field in IR_CONFIG_CHANGE 6096 * event indicate physport/phynum, let's get 6097 * parent after SAS Device Page0 request. 6098 */ 6099 goto handle_topo_change; 6100 } 6101 6102 mutex_enter(&mpt->m_mutex); 6103 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6104 /* 6105 * If the direct attached device added or a 6106 * phys disk is being unhidden, argument 6107 * physport actually is PHY#, so we have to get 6108 * phymask according PHY#. 6109 */ 6110 physport = mpt->m_phy_info[physport].port_num; 6111 } 6112 6113 /* 6114 * Translate physport to phymask so that we can search 6115 * parent dip. 6116 */ 6117 phymask = mptsas_physport_to_phymask(mpt, 6118 physport); 6119 mutex_exit(&mpt->m_mutex); 6120 6121find_parent: 6122 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 6123 /* 6124 * For RAID topology change node, write the iport name 6125 * as v0. 6126 */ 6127 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6128 (void) sprintf(phy_mask_name, "v0"); 6129 } else { 6130 /* 6131 * phymask can bo 0 if the drive has been 6132 * pulled by the time an add event is 6133 * processed. If phymask is 0, just skip this 6134 * event and continue. 6135 */ 6136 if (phymask == 0) { 6137 mutex_enter(&mpt->m_mutex); 6138 save_node = topo_node; 6139 topo_node = topo_node->next; 6140 ASSERT(save_node); 6141 kmem_free(save_node, 6142 sizeof (mptsas_topo_change_list_t)); 6143 mutex_exit(&mpt->m_mutex); 6144 6145 parent = NULL; 6146 continue; 6147 } 6148 (void) sprintf(phy_mask_name, "%x", phymask); 6149 } 6150 parent = scsi_hba_iport_find(mpt->m_dip, 6151 phy_mask_name); 6152 if (parent == NULL) { 6153 mptsas_log(mpt, CE_WARN, "Failed to find an " 6154 "iport, should not happen!"); 6155 goto out; 6156 } 6157 6158 } 6159 ASSERT(parent); 6160handle_topo_change: 6161 6162 mutex_enter(&mpt->m_mutex); 6163 6164 mptsas_handle_topo_change(topo_node, parent); 6165 save_node = topo_node; 6166 topo_node = topo_node->next; 6167 ASSERT(save_node); 6168 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 6169 mutex_exit(&mpt->m_mutex); 6170 6171 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6172 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 6173 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 6174 /* 6175 * If direct attached device associated, make sure 6176 * reset the parent before start the next one. But 6177 * all devices associated with expander shares the 6178 * parent. Also, reset parent if this is for RAID. 6179 */ 6180 parent = NULL; 6181 } 6182 } 6183out: 6184 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6185} 6186 6187static void 6188mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 6189 dev_info_t *parent) 6190{ 6191 mptsas_target_t *ptgt = NULL; 6192 mptsas_smp_t *psmp = NULL; 6193 mptsas_t *