1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 
26 
27 /*
28  * SiliconImage 3124/3132/3531 sata controller driver
29  */
30 
31 /*
32  *
33  *
34  *			Few Design notes
35  *
36  *
37  * I. General notes
38  *
39  * Even though the driver is named as si3124, it is actually meant to
40  * work with SiI3124, SiI3132 and SiI3531 controllers.
41  *
42  * The current file si3124.c is the main driver code. The si3124reg.h
43  * holds the register definitions from SiI 3124/3132/3531 data sheets. The
44  * si3124var.h holds the driver specific definitions which are not
45  * directly derived from data sheets.
46  *
47  *
48  * II. Data structures
49  *
50  * si_ctl_state_t: This holds the driver private information for each
51  *	controller instance. Each of the sata ports within a single
52  *	controller are represented by si_port_state_t. The
53  *	sictl_global_acc_handle and sictl_global_address map the
54  *	controller-wide global register space and are derived from pci
55  *	BAR 0. The sictl_port_acc_handle and sictl_port_addr map the
56  *	per-port register space and are derived from pci BAR 1.
57  *
58  * si_port_state_t: This holds the per port information. The siport_mutex
59  *	holds the per port mutex. The siport_pending_tags is the bit mask of
60  *	commands posted to controller. The siport_slot_pkts[] holds the
61  *	pending sata packets. The siport_port_type holds the device type
62  *	connected directly to the port while the siport_portmult_state
63  *	holds the similar information for the devices behind a port
64  *	multiplier.
65  *
66  * si_prb_t: This contains the PRB being posted to the controller.
67  *	The two SGE entries contained within si_prb_t itself are not
68  *	really used to hold any scatter gather entries. The scatter gather
69  *	list is maintained external to PRB and is linked from one
70  *	of the contained SGEs inside the PRB. For atapi devices, the
71  *	first contained SGE holds the PACKET and second contained
72  *	SGE holds the link to an external SGT. For non-atapi devices,
73  *	the first contained SGE works as link to external SGT while
74  *	second SGE is blank.
75  *
76  * external SGT tables: The external SGT tables pointed to from
77  *	within si_prb_t are actually abstracted as si_sgblock_t. Each
78  *	si_sgblock_t contains si_dma_sg_number number of
79  *	SGT tables linked in a chain. Currently this default value of
80  *	SGT tables per block is at 85 as  which translates
81  *	to a maximum of 256 dma cookies per single dma transfer.
82  *	This value can be changed through the global var: si_dma_sg_number
83  *	in /etc/system, the maxium is at 21844 as which translates to 65535
84  *	dma cookies per single dma transfer.
85  *
86  *
87  * III. Driver operation
88  *
89  * Command Issuing: We use the "indirect method of command issuance". The
90  *	PRB contains the command [and atapi PACKET] and a link to the
91  *	external SGT chain. We write the physical address of the PRB into
92  *	command activation register. There are 31 command slots for
93  *	each port. After posting a command, we remember the posted slot &
94  *	the sata packet in siport_pending_tags & siport_slot_pkts[]
95  *	respectively.
96  *
97  * Command completion: On a successful completion, intr_command_complete()
98  *	receives the control. The slot_status register holds the outstanding
99  *	commands. Any reading of slot_status register automatically clears
100  *	the interrupt. By comparing the slot_status register contents with
101  *	per port siport_pending_tags, we determine which of the previously
102  *	posted commands have finished.
103  *
104  * Timeout handling: Every 5 seconds, the watchdog handler scans thru the
105  *	pending packets. The satapkt->satapkt_hba_driver_private field is
106  *	overloaded with the count of watchdog cycles a packet has survived.
107  *	If a packet has not completed within satapkt->satapkt_time, it is
108  *	failed with error code of SATA_PKT_TIMEOUT. There is one watchdog
109  *	handler running for each instance of controller.
110  *
111  * Error handling: For 3124, whenever any single command has encountered
112  *	an error, the whole port execution completely stalls; there is no
113  *	way of canceling or aborting the particular failed command. If
114  *	the port is connected to a port multiplier, we can however RESUME
115  *	other non-error devices connected to the port multiplier.
116  *	The only way to recover the failed commands is to either initialize
117  *	the port or reset the port/device. Both port initialize and reset
118  *	operations result in discarding any of pending commands on the port.
119  *	All such discarded commands are sent up to framework with PKT_RESET
120  *	satapkt_reason. The assumption is that framework [and sd] would
121  *	retry these commands again. The failed command itself however is
122  *	sent up with PKT_DEV_ERROR.
123  *
124  *	Here is the implementation strategy based on SiliconImage email
125  *	regarding how they handle the errors for their Windows driver:
126  *
127  *	  a) for DEVICEERROR:
128  *		If the port is connected to port multiplier, then
129  *		 1) Resume the port
130  *		 2) Wait for all the non-failed commands to complete
131  *		 3) Perform a Port Initialize
132  *
133  *		If the port is not connected to port multiplier, issue
134  *		a Port Initialize.
135  *
136  *	  b) for SDBERROR: [SDBERROR means failed command is an NCQ command]
137  *		Handle exactly like DEVICEERROR handling.
138  *		After the Port Initialize done, do a Read Log Extended.
139  *
140  *	  c) for SENDFISERROR:
141  *		If the port is connected to port multiplier, then
142  *		 1) Resume the port
143  *		 2) Wait for all the non-failed commands to complete
144  *		 3) Perform a Port Initialize
145  *
146  *		If the port is not connected to port multiplier, issue
147  *		a Device Reset.
148  *
149  *	  d) for DATAFISERROR:
150  *		If the port was executing an NCQ command, issue a Device
151  *		Reset.
152  *
153  *		Otherwise, follow the same error recovery as DEVICEERROR.
154  *
155  *	  e) for any other error, simply issue a Device Reset.
156  *
157  *	To synchronize the interactions between various control flows (e.g.
158  *	error recovery, timeout handling, si_poll_timeout, incoming flow
159  *	from framework etc.), the following precautions are taken care of:
160  *		a) During mopping_in_progress, no more commands are
161  *		accepted from the framework.
162  *
163  *		b) While draining the port multiplier commands, we should
164  *		handle the possibility of any of the other waited commands
165  *		failing (possibly with a different error code)
166  *
167  * Atapi handling: For atapi devices, we use the first SGE within the PRB
168  *	to fill the scsi cdb while the second SGE points to external SGT.
169  *
170  * Queuing: Queue management is achieved external to the driver inside sd.
171  *	Based on sata_hba_tran->qdepth and IDENTIFY data, the framework
172  *	enables or disables the queuing. The qdepth for si3124 is 31
173  *	commands.
174  *
175  * Port Multiplier: Enumeration of port multiplier is handled during the
176  *	controller initialization and also during the a hotplug operation.
177  *	Current logic takes care of situation where a port multiplier
178  *	is hotplugged into a port which had a cdisk connected previously
179  *	and vice versa.
180  *
181  * Register poll timeouts: Currently most of poll timeouts on register
182  *	reads is set to 0.5 seconds except for a value of 10 seconds
183  *	while reading the device signature. [Such a big timeout values
184  *	for device signature were found needed during cold reboots
185  *	for devices behind port multiplier].
186  *
187  *
188  * IV. Known Issues
189  *
190  * 1) Currently the atapi packet length is hard coded to 12 bytes
191  *	This is wrong. The framework should determine it just like they
192  *	determine ad_cdb_len in legacy atapi.c. It should even reject
193  *	init_pkt() for greater CDB lengths. See atapi.c. Revisit this
194  *	in 2nd phase of framework project.
195  *
196  * 2) Do real REQUEST SENSE command instead of faking for ATAPI case.
197  *
198  */
199 
200 
201 #include <sys/note.h>
202 #include <sys/scsi/scsi.h>
203 #include <sys/pci.h>
204 #include <sys/sata/sata_hba.h>
205 #include <sys/sata/adapters/si3124/si3124reg.h>
206 #include <sys/sata/adapters/si3124/si3124var.h>
207 #include <sys/sdt.h>
208 
209 /*
210  * FMA header files
211  */
212 #include <sys/ddifm.h>
213 #include <sys/fm/protocol.h>
214 #include <sys/fm/util.h>
215 #include <sys/fm/io/ddi.h>
216 
217 /*
218  * Function prototypes for driver entry points
219  */
220 static	int si_attach(dev_info_t *, ddi_attach_cmd_t);
221 static	int si_detach(dev_info_t *, ddi_detach_cmd_t);
222 static	int si_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
223 static	int si_power(dev_info_t *, int, int);
224 static	int si_quiesce(dev_info_t *);
225 /*
226  * Function prototypes for SATA Framework interfaces
227  */
228 static	int si_register_sata_hba_tran(si_ctl_state_t *);
229 static	int si_unregister_sata_hba_tran(si_ctl_state_t *);
230 
231 static	int si_tran_probe_port(dev_info_t *, sata_device_t *);
232 static	int si_tran_start(dev_info_t *, sata_pkt_t *spkt);
233 static	int si_tran_abort(dev_info_t *, sata_pkt_t *, int);
234 static	int si_tran_reset_dport(dev_info_t *, sata_device_t *);
235 static	int si_tran_hotplug_port_activate(dev_info_t *, sata_device_t *);
236 static	int si_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *);
237 
238 /*
239  * Local function prototypes
240  */
241 
242 static	int si_alloc_port_state(si_ctl_state_t *, int);
243 static	void si_dealloc_port_state(si_ctl_state_t *, int);
244 static	int si_alloc_sgbpool(si_ctl_state_t *, int);
245 static	void si_dealloc_sgbpool(si_ctl_state_t *, int);
246 static	int si_alloc_prbpool(si_ctl_state_t *, int);
247 static	void si_dealloc_prbpool(si_ctl_state_t *, int);
248 
249 static void si_find_dev_signature(si_ctl_state_t *, si_port_state_t *,
250 						int, int);
251 static void si_poll_cmd(si_ctl_state_t *, si_port_state_t *, int, int,
252 						sata_pkt_t *);
253 static	int si_claim_free_slot(si_ctl_state_t *, si_port_state_t *, int);
254 static	int si_deliver_satapkt(si_ctl_state_t *, si_port_state_t *, int,
255 						sata_pkt_t *);
256 
257 static	int si_initialize_controller(si_ctl_state_t *);
258 static	void si_deinitialize_controller(si_ctl_state_t *);
259 static void si_init_port(si_ctl_state_t *, int);
260 static	int si_enumerate_port_multiplier(si_ctl_state_t *,
261 						si_port_state_t *, int);
262 static int si_read_portmult_reg(si_ctl_state_t *, si_port_state_t *,
263 						int, int, int, uint32_t *);
264 static int si_write_portmult_reg(si_ctl_state_t *, si_port_state_t *,
265 						int, int, int, uint32_t);
266 static void si_set_sense_data(sata_pkt_t *, int);
267 
268 static uint_t si_intr(caddr_t, caddr_t);
269 static int si_intr_command_complete(si_ctl_state_t *,
270 					si_port_state_t *, int);
271 static void si_schedule_intr_command_error(si_ctl_state_t *,
272 					si_port_state_t *, int);
273 static void si_do_intr_command_error(void *);
274 static int si_intr_command_error(si_ctl_state_t *,
275 					si_port_state_t *, int);
276 static void si_error_recovery_DEVICEERROR(si_ctl_state_t *,
277 					si_port_state_t *, int);
278 static void si_error_recovery_SDBERROR(si_ctl_state_t *,
279 					si_port_state_t *, int);
280 static void si_error_recovery_DATAFISERROR(si_ctl_state_t *,
281 					si_port_state_t *, int);
282 static void si_error_recovery_SENDFISERROR(si_ctl_state_t *,
283 					si_port_state_t *, int);
284 static void si_error_recovery_default(si_ctl_state_t *,
285 					si_port_state_t *, int);
286 static uint8_t si_read_log_ext(si_ctl_state_t *,
287 					si_port_state_t *si_portp, int);
288 static void si_log_error_message(si_ctl_state_t *, int, uint32_t);
289 static int si_intr_port_ready(si_ctl_state_t *, si_port_state_t *, int);
290 static int si_intr_pwr_change(si_ctl_state_t *, si_port_state_t *, int);
291 static int si_intr_phy_ready_change(si_ctl_state_t *, si_port_state_t *, int);
292 static int si_intr_comwake_rcvd(si_ctl_state_t *, si_port_state_t *, int);
293 static int si_intr_unrecognised_fis(si_ctl_state_t *, si_port_state_t *, int);
294 static int si_intr_dev_xchanged(si_ctl_state_t *, si_port_state_t *, int);
295 static int si_intr_decode_err_threshold(si_ctl_state_t *,
296 					si_port_state_t *, int);
297 static int si_intr_crc_err_threshold(si_ctl_state_t *, si_port_state_t *, int);
298 static int si_intr_handshake_err_threshold(si_ctl_state_t *,
299 					si_port_state_t *, int);
300 static int si_intr_set_devbits_notify(si_ctl_state_t *, si_port_state_t *, int);
301 
302 static	void si_enable_port_interrupts(si_ctl_state_t *, int);
303 static	void si_enable_all_interrupts(si_ctl_state_t *);
304 static	void si_disable_port_interrupts(si_ctl_state_t *, int);
305 static	void si_disable_all_interrupts(si_ctl_state_t *);
306 static	void fill_dev_sregisters(si_ctl_state_t *, int, sata_device_t *);
307 static	int si_add_legacy_intrs(si_ctl_state_t *);
308 static	int si_add_msi_intrs(si_ctl_state_t *);
309 static	void si_rem_intrs(si_ctl_state_t *);
310 
311 static	int si_reset_dport_wait_till_ready(si_ctl_state_t *,
312 				si_port_state_t *, int, int);
313 static int si_clear_port(si_ctl_state_t *, int);
314 static void si_schedule_port_initialize(si_ctl_state_t *,
315 				si_port_state_t *, int);
316 static void si_do_initialize_port(void *);
317 static	int si_initialize_port_wait_till_ready(si_ctl_state_t *, int);
318 
319 static void si_timeout_pkts(si_ctl_state_t *, si_port_state_t *, int, uint32_t);
320 static	void si_watchdog_handler(si_ctl_state_t *);
321 
322 /*
323  * FMA Prototypes
324  */
325 static void si_fm_init(si_ctl_state_t *);
326 static void si_fm_fini(si_ctl_state_t *);
327 static int si_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
328 static int si_check_acc_handle(ddi_acc_handle_t);
329 static int si_check_dma_handle(ddi_dma_handle_t);
330 static int si_check_ctl_handles(si_ctl_state_t *);
331 static int si_check_port_handles(si_port_state_t *);
332 static void si_fm_ereport(si_ctl_state_t *, char *, char *);
333 
334 static	void si_log(si_ctl_state_t *, si_port_state_t *, char *, ...);
335 
336 static void si_copy_out_regs(sata_cmd_t *, si_ctl_state_t *, uint8_t, uint8_t);
337 
338 /*
339  * DMA attributes for the data buffer
340  */
341 
342 static ddi_dma_attr_t buffer_dma_attr = {
343 	DMA_ATTR_V0,		/* dma_attr_version */
344 	0,			/* dma_attr_addr_lo: lowest bus address */
345 	0xffffffffffffffffull,	/* dma_attr_addr_hi: highest bus address */
346 	0xffffffffull,		/* dma_attr_count_max i.e. for one cookie */
347 	1,			/* dma_attr_align: single byte aligned */
348 	1,			/* dma_attr_burstsizes */
349 	1,			/* dma_attr_minxfer */
350 	0xffffffffull,		/* dma_attr_maxxfer i.e. includes all cookies */
351 	0xffffffffull,		/* dma_attr_seg */
352 	SI_DEFAULT_SGL_LENGTH,	/* dma_attr_sgllen */
353 	512,			/* dma_attr_granular */
354 	0,			/* dma_attr_flags */
355 };
356 
357 /*
358  * DMA attributes for incore RPB and SGT pool
359  */
360 static ddi_dma_attr_t prb_sgt_dma_attr = {
361 	DMA_ATTR_V0,		/* dma_attr_version */
362 	0,			/* dma_attr_addr_lo: lowest bus address */
363 	0xffffffffffffffffull,	/* dma_attr_addr_hi: highest bus address */
364 	0xffffffffull,		/* dma_attr_count_max i.e. for one cookie */
365 	8,			/* dma_attr_align: quad word aligned */
366 	1,			/* dma_attr_burstsizes */
367 	1,			/* dma_attr_minxfer */
368 	0xffffffffull,		/* dma_attr_maxxfer i.e. includes all cookies */
369 	0xffffffffull,		/* dma_attr_seg */
370 	1,			/* dma_attr_sgllen */
371 	1,			/* dma_attr_granular */
372 	0,			/* dma_attr_flags */
373 };
374 
375 /* Device access attributes */
376 static ddi_device_acc_attr_t accattr = {
377     DDI_DEVICE_ATTR_V1,
378     DDI_STRUCTURE_LE_ACC,
379     DDI_STRICTORDER_ACC,
380     DDI_DEFAULT_ACC
381 };
382 
383 
384 static struct dev_ops sictl_dev_ops = {
385 	DEVO_REV,		/* devo_rev */
386 	0,			/* refcnt  */
387 	si_getinfo,		/* info */
388 	nulldev,		/* identify */
389 	nulldev,		/* probe */
390 	si_attach,		/* attach */
391 	si_detach,		/* detach */
392 	nodev,			/* no reset */
393 	(struct cb_ops *)0,	/* driver operations */
394 	NULL,			/* bus operations */
395 	si_power,		/* power */
396 	si_quiesce,		/* devo_quiesce */
397 };
398 
399 static sata_tran_hotplug_ops_t si_tran_hotplug_ops = {
400 	SATA_TRAN_HOTPLUG_OPS_REV_1,
401 	si_tran_hotplug_port_activate,
402 	si_tran_hotplug_port_deactivate
403 };
404 
405 
406 static int si_watchdog_timeout = 5; /* 5 seconds */
407 static int si_watchdog_tick;
408 
409 extern struct mod_ops mod_driverops;
410 
411 static  struct modldrv modldrv = {
412 	&mod_driverops,	/* driverops */
413 	"si3124 driver",
414 	&sictl_dev_ops,	/* driver ops */
415 };
416 
417 static  struct modlinkage modlinkage = {
418 	MODREV_1,
419 	&modldrv,
420 	NULL
421 };
422 
423 
424 /* The following are needed for si_log() */
425 static kmutex_t si_log_mutex;
426 static char si_log_buf[SI_LOGBUF_LEN];
427 uint32_t si_debug_flags =
428     SIDBG_ERRS|SIDBG_INIT|SIDBG_EVENT|SIDBG_TIMEOUT|SIDBG_RESET;
429 
430 static int is_msi_supported = 0;
431 
432 /*
433  * The below global variables are tunable via /etc/system
434  *
435  * si_dma_sg_number
436  */
437 
438 int si_dma_sg_number = SI_DEFAULT_SGT_TABLES_PER_PRB;
439 
440 /* Opaque state pointer to be initialized by ddi_soft_state_init() */
441 static void *si_statep	= NULL;
442 
443 /*
444  *  si3124 module initialization.
445  *
446  */
447 int
_init(void)448 _init(void)
449 {
450 	int	error;
451 
452 	error = ddi_soft_state_init(&si_statep, sizeof (si_ctl_state_t), 0);
453 	if (error != 0) {
454 		return (error);
455 	}
456 
457 	mutex_init(&si_log_mutex, NULL, MUTEX_DRIVER, NULL);
458 
459 	if ((error = sata_hba_init(&modlinkage)) != 0) {
460 		mutex_destroy(&si_log_mutex);
461 		ddi_soft_state_fini(&si_statep);
462 		return (error);
463 	}
464 
465 	error = mod_install(&modlinkage);
466 	if (error != 0) {
467 		sata_hba_fini(&modlinkage);
468 		mutex_destroy(&si_log_mutex);
469 		ddi_soft_state_fini(&si_statep);
470 		return (error);
471 	}
472 
473 	si_watchdog_tick = drv_usectohz((clock_t)si_watchdog_timeout * 1000000);
474 
475 	return (error);
476 }
477 
478 /*
479  * si3124 module uninitialize.
480  *
481  */
482 int
_fini(void)483 _fini(void)
484 {
485 	int	error;
486 
487 	error = mod_remove(&modlinkage);
488 	if (error != 0) {
489 		return (error);
490 	}
491 
492 	/* Remove the resources allocated in _init(). */
493 	sata_hba_fini(&modlinkage);
494 	mutex_destroy(&si_log_mutex);
495 	ddi_soft_state_fini(&si_statep);
496 
497 	return (error);
498 }
499 
500 /*
501  * _info entry point
502  *
503  */
504 int
_info(struct modinfo * modinfop)505 _info(struct modinfo *modinfop)
506 {
507 	return (mod_info(&modlinkage, modinfop));
508 }
509 
510 
511 /*
512  * The attach entry point for dev_ops.
513  *
514  * We initialize the controller, initialize the soft state, register
515  * the interrupt handlers and then register ourselves with sata framework.
516  */
517 static int
si_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)518 si_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
519 {
520 	si_ctl_state_t *si_ctlp;
521 	int instance;
522 	int status;
523 	int attach_state;
524 	int intr_types;
525 	sata_device_t sdevice;
526 
527 	SIDBG(SIDBG_ENTRY, "si_attach enter", NULL);
528 	instance = ddi_get_instance(dip);
529 	attach_state = ATTACH_PROGRESS_NONE;
530 
531 	switch (cmd) {
532 
533 	case DDI_ATTACH:
534 
535 		/* Allocate si_softc. */
536 		status = ddi_soft_state_zalloc(si_statep, instance);
537 		if (status != DDI_SUCCESS) {
538 			goto err_out;
539 		}
540 
541 		si_ctlp = ddi_get_soft_state(si_statep, instance);
542 		si_ctlp->sictl_devinfop = dip;
543 
544 		attach_state |= ATTACH_PROGRESS_STATEP_ALLOC;
545 
546 		/* Initialize FMA */
547 		si_ctlp->fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, dip,
548 		    DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
549 		    DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
550 		    DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
551 
552 		si_fm_init(si_ctlp);
553 
554 		attach_state |= ATTACH_PROGRESS_INIT_FMA;
555 
556 		/* Configure pci config space handle. */
557 		status = pci_config_setup(dip, &si_ctlp->sictl_pci_conf_handle);
558 		if (status != DDI_SUCCESS) {
559 			goto err_out;
560 		}
561 
562 		si_ctlp->sictl_devid =
563 		    pci_config_get16(si_ctlp->sictl_pci_conf_handle,
564 		    PCI_CONF_DEVID);
565 		switch (si_ctlp->sictl_devid) {
566 			case SI3124_DEV_ID:
567 				si_ctlp->sictl_num_ports = SI3124_MAX_PORTS;
568 				break;
569 
570 			case SI3132_DEV_ID:
571 				si_ctlp->sictl_num_ports = SI3132_MAX_PORTS;
572 				break;
573 
574 			case SI3531_DEV_ID:
575 				si_ctlp->sictl_num_ports = SI3531_MAX_PORTS;
576 				break;
577 
578 			default:
579 				/*
580 				 * Driver should not have attatched if device
581 				 * ID is not already known and is supported.
582 				 */
583 				goto err_out;
584 		}
585 
586 		attach_state |= ATTACH_PROGRESS_CONF_HANDLE;
587 
588 		/* Now map the bar0; the bar0 contains the global registers. */
589 		status = ddi_regs_map_setup(dip,
590 		    PCI_BAR0,
591 		    (caddr_t *)&si_ctlp->sictl_global_addr,
592 		    0,
593 		    0,
594 		    &accattr,
595 		    &si_ctlp->sictl_global_acc_handle);
596 		if (status != DDI_SUCCESS) {
597 			goto err_out;
598 		}
599 
600 		attach_state |= ATTACH_PROGRESS_BAR0_MAP;
601 
602 		/* Now map bar1; the bar1 contains the port registers. */
603 		status = ddi_regs_map_setup(dip,
604 		    PCI_BAR1,
605 		    (caddr_t *)&si_ctlp->sictl_port_addr,
606 		    0,
607 		    0,
608 		    &accattr,
609 		    &si_ctlp->sictl_port_acc_handle);
610 		if (status != DDI_SUCCESS) {
611 			goto err_out;
612 		}
613 
614 		attach_state |= ATTACH_PROGRESS_BAR1_MAP;
615 
616 		/*
617 		 * Disable all the interrupts before adding interrupt
618 		 * handler(s). The interrupts shall be re-enabled selectively
619 		 * out of si_init_port().
620 		 */
621 		si_disable_all_interrupts(si_ctlp);
622 
623 		/* Get supported interrupt types. */
624 		if (ddi_intr_get_supported_types(dip, &intr_types)
625 		    != DDI_SUCCESS) {
626 			SIDBG_C(SIDBG_INIT, si_ctlp,
627 			    "ddi_intr_get_supported_types failed", NULL);
628 			goto err_out;
629 		}
630 
631 		SIDBG_C(SIDBG_INIT, si_ctlp,
632 		    "ddi_intr_get_supported_types() returned: 0x%x",
633 		    intr_types);
634 
635 		if (is_msi_supported && (intr_types & DDI_INTR_TYPE_MSI)) {
636 			SIDBG_C(SIDBG_INIT, si_ctlp,
637 			    "Using MSI interrupt type", NULL);
638 
639 			/*
640 			 * Try MSI first, but fall back to legacy if MSI
641 			 * attach fails.
642 			 */
643 			if (si_add_msi_intrs(si_ctlp) == DDI_SUCCESS) {
644 				si_ctlp->sictl_intr_type = DDI_INTR_TYPE_MSI;
645 				attach_state |= ATTACH_PROGRESS_INTR_ADDED;
646 				SIDBG_C(SIDBG_INIT, si_ctlp,
647 				    "MSI interrupt setup done", NULL);
648 			} else {
649 				SIDBG_C(SIDBG_INIT, si_ctlp,
650 				    "MSI registration failed "
651 				    "will try Legacy interrupts", NULL);
652 			}
653 		}
654 
655 		if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED) &&
656 		    (intr_types & DDI_INTR_TYPE_FIXED)) {
657 			/*
658 			 * Either the MSI interrupt setup has failed or only
659 			 * fixed interrupts are available on the system.
660 			 */
661 			SIDBG_C(SIDBG_INIT, si_ctlp,
662 			    "Using Legacy interrupt type", NULL);
663 
664 			if (si_add_legacy_intrs(si_ctlp) == DDI_SUCCESS) {
665 				si_ctlp->sictl_intr_type = DDI_INTR_TYPE_FIXED;
666 				attach_state |= ATTACH_PROGRESS_INTR_ADDED;
667 				SIDBG_C(SIDBG_INIT, si_ctlp,
668 				    "Legacy interrupt setup done", NULL);
669 			} else {
670 				SIDBG_C(SIDBG_INIT, si_ctlp,
671 				    "legacy interrupt setup failed", NULL);
672 				goto err_out;
673 			}
674 		}
675 
676 		if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED)) {
677 			SIDBG_C(SIDBG_INIT, si_ctlp,
678 			    "si3124: No interrupts registered", NULL);
679 			goto err_out;
680 		}
681 
682 
683 		/* Initialize the mutex. */
684 		mutex_init(&si_ctlp->sictl_mutex, NULL, MUTEX_DRIVER,
685 		    (void *)(uintptr_t)si_ctlp->sictl_intr_pri);
686 
687 		attach_state |= ATTACH_PROGRESS_MUTEX_INIT;
688 
689 		/*
690 		 * Initialize the controller and driver core.
691 		 */
692 		si_ctlp->sictl_flags |= SI_ATTACH;
693 		status = si_initialize_controller(si_ctlp);
694 		si_ctlp->sictl_flags &= ~SI_ATTACH;
695 		if (status) {
696 			goto err_out;
697 		}
698 
699 		attach_state |= ATTACH_PROGRESS_HW_INIT;
700 
701 		if (si_register_sata_hba_tran(si_ctlp)) {
702 			SIDBG_C(SIDBG_INIT, si_ctlp,
703 			    "si3124: setting sata hba tran failed", NULL);
704 			goto err_out;
705 		}
706 
707 		si_ctlp->sictl_timeout_id = timeout(
708 		    (void (*)(void *))si_watchdog_handler,
709 		    (caddr_t)si_ctlp, si_watchdog_tick);
710 
711 		si_ctlp->sictl_power_level = PM_LEVEL_D0;
712 
713 		return (DDI_SUCCESS);
714 
715 	case DDI_RESUME:
716 		si_ctlp = ddi_get_soft_state(si_statep, instance);
717 
718 		status = si_initialize_controller(si_ctlp);
719 		if (status) {
720 			return (DDI_FAILURE);
721 		}
722 
723 		si_ctlp->sictl_timeout_id = timeout(
724 		    (void (*)(void *))si_watchdog_handler,
725 		    (caddr_t)si_ctlp, si_watchdog_tick);
726 
727 		(void) pm_power_has_changed(dip, 0, PM_LEVEL_D0);
728 
729 		/* Notify SATA framework about RESUME. */
730 		if (sata_hba_attach(si_ctlp->sictl_devinfop,
731 		    si_ctlp->sictl_sata_hba_tran,
732 		    DDI_RESUME) != DDI_SUCCESS) {
733 			return (DDI_FAILURE);
734 		}
735 
736 		/*
737 		 * Notify the "framework" that it should reprobe ports to see
738 		 * if any device got changed while suspended.
739 		 */
740 		bzero((void *)&sdevice, sizeof (sata_device_t));
741 		sata_hba_event_notify(dip, &sdevice,
742 		    SATA_EVNT_PWR_LEVEL_CHANGED);
743 		SIDBG_C(SIDBG_INIT|SIDBG_EVENT, si_ctlp,
744 		    "sending event up: SATA_EVNT_PWR_LEVEL_CHANGED", NULL);
745 
746 		(void) pm_idle_component(si_ctlp->sictl_devinfop, 0);
747 
748 		si_ctlp->sictl_power_level = PM_LEVEL_D0;
749 
750 		return (DDI_SUCCESS);
751 
752 	default:
753 		return (DDI_FAILURE);
754 
755 	}
756 
757 err_out:
758 	if (attach_state & ATTACH_PROGRESS_HW_INIT) {
759 		si_ctlp->sictl_flags |= SI_DETACH;
760 		/* We want to set SI_DETACH to deallocate all memory */
761 		si_deinitialize_controller(si_ctlp);
762 		si_ctlp->sictl_flags &= ~SI_DETACH;
763 	}
764 
765 	if (attach_state & ATTACH_PROGRESS_MUTEX_INIT) {
766 		mutex_destroy(&si_ctlp->sictl_mutex);
767 	}
768 
769 	if (attach_state & ATTACH_PROGRESS_INTR_ADDED) {
770 		si_rem_intrs(si_ctlp);
771 	}
772 
773 	if (attach_state & ATTACH_PROGRESS_BAR1_MAP) {
774 		ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle);
775 	}
776 
777 	if (attach_state & ATTACH_PROGRESS_BAR0_MAP) {
778 		ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle);
779 	}
780 
781 	if (attach_state & ATTACH_PROGRESS_CONF_HANDLE) {
782 		pci_config_teardown(&si_ctlp->sictl_pci_conf_handle);
783 	}
784 
785 	if (attach_state & ATTACH_PROGRESS_INIT_FMA) {
786 		si_fm_fini(si_ctlp);
787 	}
788 
789 	if (attach_state & ATTACH_PROGRESS_STATEP_ALLOC) {
790 		ddi_soft_state_free(si_statep, instance);
791 	}
792 
793 	return (DDI_FAILURE);
794 }
795 
796 
797 /*
798  * The detach entry point for dev_ops.
799  *
800  * We undo the things we did in si_attach().
801  */
802 static int
si_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)803 si_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
804 {
805 	si_ctl_state_t *si_ctlp;
806 	int instance;
807 
808 	SIDBG(SIDBG_ENTRY, "si_detach enter", NULL);
809 	instance = ddi_get_instance(dip);
810 	si_ctlp = ddi_get_soft_state(si_statep, instance);
811 
812 	switch (cmd) {
813 
814 	case DDI_DETACH:
815 
816 		mutex_enter(&si_ctlp->sictl_mutex);
817 
818 		/* disable the interrupts for an uninterrupted detach */
819 		si_disable_all_interrupts(si_ctlp);
820 
821 		mutex_exit(&si_ctlp->sictl_mutex);
822 		/* unregister from the sata framework. */
823 		if (si_unregister_sata_hba_tran(si_ctlp) != SI_SUCCESS) {
824 			si_enable_all_interrupts(si_ctlp);
825 			return (DDI_FAILURE);
826 		}
827 		mutex_enter(&si_ctlp->sictl_mutex);
828 
829 		/* now cancel the timeout handler. */
830 		si_ctlp->sictl_flags |= SI_NO_TIMEOUTS;
831 		(void) untimeout(si_ctlp->sictl_timeout_id);
832 		si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS;
833 
834 		/* de-initialize the controller. */
835 		si_ctlp->sictl_flags |= SI_DETACH;
836 		si_deinitialize_controller(si_ctlp);
837 		si_ctlp->sictl_flags &= ~SI_DETACH;
838 
839 		/* destroy any mutexes */
840 		mutex_exit(&si_ctlp->sictl_mutex);
841 		mutex_destroy(&si_ctlp->sictl_mutex);
842 
843 		/* remove the interrupts */
844 		si_rem_intrs(si_ctlp);
845 
846 		/* remove the reg maps. */
847 		ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle);
848 		ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle);
849 		pci_config_teardown(&si_ctlp->sictl_pci_conf_handle);
850 
851 		/* deinit FMA */
852 		si_fm_fini(si_ctlp);
853 
854 		/* free the soft state. */
855 		ddi_soft_state_free(si_statep, instance);
856 
857 		return (DDI_SUCCESS);
858 
859 	case DDI_SUSPEND:
860 		/* Inform SATA framework */
861 		if (sata_hba_detach(dip, cmd) != DDI_SUCCESS) {
862 			return (DDI_FAILURE);
863 		}
864 
865 		mutex_enter(&si_ctlp->sictl_mutex);
866 
867 		/*
868 		 * Device needs to be at full power in case it is needed to
869 		 * handle dump(9e) to save CPR state after DDI_SUSPEND
870 		 * completes.  This is OK since presumably power will be
871 		 * removed anyways.  No outstanding transactions should be
872 		 * on the controller since the children are already quiesced.
873 		 *
874 		 * If any ioctls/cfgadm support is added that touches
875 		 * hardware, those entry points will need to check for
876 		 * suspend and then block or return errors until resume.
877 		 *
878 		 */
879 		if (pm_busy_component(si_ctlp->sictl_devinfop, 0) ==
880 		    DDI_SUCCESS) {
881 			mutex_exit(&si_ctlp->sictl_mutex);
882 			(void) pm_raise_power(si_ctlp->sictl_devinfop, 0,
883 			    PM_LEVEL_D0);
884 			mutex_enter(&si_ctlp->sictl_mutex);
885 		}
886 
887 		si_deinitialize_controller(si_ctlp);
888 
889 		si_ctlp->sictl_flags |= SI_NO_TIMEOUTS;
890 		(void) untimeout(si_ctlp->sictl_timeout_id);
891 		si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS;
892 
893 		SIDBG_C(SIDBG_POWER, si_ctlp, "si3124%d: DDI_SUSPEND",
894 		    instance);
895 
896 		mutex_exit(&si_ctlp->sictl_mutex);
897 
898 		return (DDI_SUCCESS);
899 
900 	default:
901 		return (DDI_FAILURE);
902 
903 	}
904 
905 }
906 
907 static int
si_power(dev_info_t * dip,int component,int level)908 si_power(dev_info_t *dip, int component, int level)
909 {
910 #ifndef __lock_lint
911 	_NOTE(ARGUNUSED(component))
912 #endif /* __lock_lint */
913 
914 	si_ctl_state_t *si_ctlp;
915 	int instance = ddi_get_instance(dip);
916 	int rval = DDI_SUCCESS;
917 	int old_level;
918 	sata_device_t sdevice;
919 
920 	si_ctlp = ddi_get_soft_state(si_statep, instance);
921 
922 	if (si_ctlp == NULL) {
923 		return (DDI_FAILURE);
924 	}
925 
926 	SIDBG_C(SIDBG_ENTRY, si_ctlp, "si_power enter", NULL);
927 
928 	mutex_enter(&si_ctlp->sictl_mutex);
929 	old_level = si_ctlp->sictl_power_level;
930 
931 	switch (level) {
932 	case PM_LEVEL_D0: /* fully on */
933 		pci_config_put16(si_ctlp->sictl_pci_conf_handle,
934 		    PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D0);
935 #ifndef __lock_lint
936 		delay(drv_usectohz(10000));
937 #endif  /* __lock_lint */
938 		si_ctlp->sictl_power_level = PM_LEVEL_D0;
939 		(void) pci_restore_config_regs(si_ctlp->sictl_devinfop);
940 
941 		SIDBG_C(SIDBG_POWER, si_ctlp,
942 		    "si3124%d: turning power ON. old level %d",
943 		    instance, old_level);
944 		/*
945 		 * If called from attach, just raise device power,
946 		 * restore config registers (if they were saved
947 		 * from a previous detach that lowered power),
948 		 * and exit.
949 		 */
950 		if (si_ctlp->sictl_flags & SI_ATTACH)
951 			break;
952 
953 		mutex_exit(&si_ctlp->sictl_mutex);
954 		(void) si_initialize_controller(si_ctlp);
955 		mutex_enter(&si_ctlp->sictl_mutex);
956 
957 		si_ctlp->sictl_timeout_id = timeout(
958 		    (void (*)(void *))si_watchdog_handler,
959 		    (caddr_t)si_ctlp, si_watchdog_tick);
960 
961 		bzero((void *)&sdevice, sizeof (sata_device_t));
962 		sata_hba_event_notify(
963 		    si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip,
964 		    &sdevice, SATA_EVNT_PWR_LEVEL_CHANGED);
965 		SIDBG_C(SIDBG_EVENT|SIDBG_POWER, si_ctlp,
966 		    "sending event up: PWR_LEVEL_CHANGED", NULL);
967 
968 		break;
969 
970 	case PM_LEVEL_D3: /* fully off */
971 		if (!(si_ctlp->sictl_flags & SI_DETACH)) {
972 			si_ctlp->sictl_flags |= SI_NO_TIMEOUTS;
973 			(void) untimeout(si_ctlp->sictl_timeout_id);
974 			si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS;
975 
976 			si_deinitialize_controller(si_ctlp);
977 
978 			si_ctlp->sictl_power_level = PM_LEVEL_D3;
979 		}
980 
981 		(void) pci_save_config_regs(si_ctlp->sictl_devinfop);
982 
983 		pci_config_put16(si_ctlp->sictl_pci_conf_handle,
984 		    PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D3HOT);
985 
986 		SIDBG_C(SIDBG_POWER, si_ctlp, "si3124%d: turning power OFF. "
987 		    "old level %d", instance, old_level);
988 
989 		break;
990 
991 	default:
992 		SIDBG_C(SIDBG_POWER, si_ctlp, "si3124%d: turning power OFF. "
993 		    "old level %d", instance, old_level);
994 		rval = DDI_FAILURE;
995 		break;
996 	}
997 
998 	mutex_exit(&si_ctlp->sictl_mutex);
999 
1000 	return (rval);
1001 }
1002 
1003 
1004 /*
1005  * The info entry point for dev_ops.
1006  *
1007  */
1008 static int
si_getinfo(dev_info_t * dip,ddi_info_cmd_t infocmd,void * arg,void ** result)1009 si_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
1010 {
1011 #ifndef __lock_lint
1012 	_NOTE(ARGUNUSED(dip))
1013 #endif /* __lock_lint */
1014 	si_ctl_state_t *si_ctlp;
1015 	int instance;
1016 	dev_t dev;
1017 
1018 	dev = (dev_t)arg;
1019 	instance = getminor(dev);
1020 
1021 	switch (infocmd) {
1022 		case DDI_INFO_DEVT2DEVINFO:
1023 			si_ctlp = ddi_get_soft_state(si_statep,  instance);
1024 			if (si_ctlp != NULL) {
1025 				*result = si_ctlp->sictl_devinfop;
1026 				return (DDI_SUCCESS);
1027 			} else {
1028 				*result = NULL;
1029 				return (DDI_FAILURE);
1030 			}
1031 		case DDI_INFO_DEVT2INSTANCE:
1032 			*(int *)result = instance;
1033 			break;
1034 		default:
1035 			break;
1036 	}
1037 	return (DDI_SUCCESS);
1038 }
1039 
1040 
1041 
1042 /*
1043  * Registers the si3124 with sata framework.
1044  */
1045 static int
si_register_sata_hba_tran(si_ctl_state_t * si_ctlp)1046 si_register_sata_hba_tran(si_ctl_state_t *si_ctlp)
1047 {
1048 	struct	sata_hba_tran	*sata_hba_tran;
1049 
1050 	SIDBG_C(SIDBG_ENTRY, si_ctlp,
1051 	    "si_register_sata_hba_tran entry", NULL);
1052 
1053 	mutex_enter(&si_ctlp->sictl_mutex);
1054 
1055 	/* Allocate memory for the sata_hba_tran  */
1056 	sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP);
1057 
1058 	sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV;
1059 	sata_hba_tran->sata_tran_hba_dip = si_ctlp->sictl_devinfop;
1060 
1061 	if (si_dma_sg_number > SI_MAX_SGT_TABLES_PER_PRB) {
1062 		si_dma_sg_number = SI_MAX_SGT_TABLES_PER_PRB;
1063 	} else if (si_dma_sg_number < SI_MIN_SGT_TABLES_PER_PRB) {
1064 		si_dma_sg_number = SI_MIN_SGT_TABLES_PER_PRB;
1065 	}
1066 
1067 	if (si_dma_sg_number != SI_DEFAULT_SGT_TABLES_PER_PRB) {
1068 		buffer_dma_attr.dma_attr_sgllen = SGE_LENGTH(si_dma_sg_number);
1069 	}
1070 	sata_hba_tran->sata_tran_hba_dma_attr = &buffer_dma_attr;
1071 
1072 	sata_hba_tran->sata_tran_hba_num_cports = si_ctlp->sictl_num_ports;
1073 	sata_hba_tran->sata_tran_hba_features_support = 0;
1074 	sata_hba_tran->sata_tran_hba_qdepth = SI_NUM_SLOTS;
1075 
1076 	sata_hba_tran->sata_tran_probe_port = si_tran_probe_port;
1077 	sata_hba_tran->sata_tran_start = si_tran_start;
1078 	sata_hba_tran->sata_tran_abort = si_tran_abort;
1079 	sata_hba_tran->sata_tran_reset_dport = si_tran_reset_dport;
1080 	sata_hba_tran->sata_tran_selftest = NULL;
1081 	sata_hba_tran->sata_tran_hotplug_ops = &si_tran_hotplug_ops;
1082 	sata_hba_tran->sata_tran_pwrmgt_ops = NULL;
1083 	sata_hba_tran->sata_tran_ioctl = NULL;
1084 	mutex_exit(&si_ctlp->sictl_mutex);
1085 
1086 	/* Attach it to SATA framework */
1087 	if (sata_hba_attach(si_ctlp->sictl_devinfop, sata_hba_tran, DDI_ATTACH)
1088 	    != DDI_SUCCESS) {
1089 		kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t));
1090 		return (SI_FAILURE);
1091 	}
1092 
1093 	mutex_enter(&si_ctlp->sictl_mutex);
1094 	si_ctlp->sictl_sata_hba_tran = sata_hba_tran;
1095 	mutex_exit(&si_ctlp->sictl_mutex);
1096 
1097 	return (SI_SUCCESS);
1098 }
1099 
1100 
1101 /*
1102  * Unregisters the si3124 with sata framework.
1103  */
1104 static int
si_unregister_sata_hba_tran(si_ctl_state_t * si_ctlp)1105 si_unregister_sata_hba_tran(si_ctl_state_t *si_ctlp)
1106 {
1107 
1108 	/* Detach from the SATA framework. */
1109 	if (sata_hba_detach(si_ctlp->sictl_devinfop, DDI_DETACH) !=
1110 	    DDI_SUCCESS) {
1111 		return (SI_FAILURE);
1112 	}
1113 
1114 	/* Deallocate sata_hba_tran. */
1115 	kmem_free((void *)si_ctlp->sictl_sata_hba_tran,
1116 	    sizeof (sata_hba_tran_t));
1117 
1118 	si_ctlp->sictl_sata_hba_tran = NULL;
1119 
1120 	return (SI_SUCCESS);
1121 }
1122 
1123 /*
1124  * Called by sata framework to probe a port. We return the
1125  * cached information from a previous hardware probe.
1126  *
1127  * The actual hardware probing itself was done either from within
1128  * si_initialize_controller() during the driver attach or
1129  * from a phy ready change interrupt handler.
1130  */
1131 static int
si_tran_probe_port(dev_info_t * dip,sata_device_t * sd)1132 si_tran_probe_port(dev_info_t *dip, sata_device_t *sd)
1133 {
1134 
1135 	si_ctl_state_t	*si_ctlp;
1136 	uint8_t cport = sd->satadev_addr.cport;
1137 	uint8_t pmport = sd->satadev_addr.pmport;
1138 	uint8_t qual = sd->satadev_addr.qual;
1139 	uint8_t port_type;
1140 	si_port_state_t *si_portp;
1141 	si_portmult_state_t *si_portmultp;
1142 
1143 	si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip));
1144 
1145 	SIDBG_C(SIDBG_ENTRY, si_ctlp,
1146 	    "si_tran_probe_port: cport: 0x%x, pmport: 0x%x, qual: 0x%x",
1147 	    cport, pmport, qual);
1148 
1149 	if (cport >= SI_MAX_PORTS) {
1150 		sd->satadev_type = SATA_DTYPE_NONE;
1151 		sd->satadev_state = SATA_STATE_UNKNOWN; /* invalid port */
1152 		return (SATA_FAILURE);
1153 	}
1154 
1155 	mutex_enter(&si_ctlp->sictl_mutex);
1156 	si_portp = si_ctlp->sictl_ports[cport];
1157 	mutex_exit(&si_ctlp->sictl_mutex);
1158 	if (si_portp == NULL) {
1159 		sd->satadev_type = SATA_DTYPE_NONE;
1160 		sd->satadev_state = SATA_STATE_UNKNOWN;
1161 		return (SATA_FAILURE);
1162 	}
1163 
1164 	mutex_enter(&si_portp->siport_mutex);
1165 
1166 	if (qual == SATA_ADDR_PMPORT) {
1167 		if (pmport >= si_portp->siport_portmult_state.sipm_num_ports) {
1168 			sd->satadev_type = SATA_DTYPE_NONE;
1169 			sd->satadev_state = SATA_STATE_UNKNOWN;
1170 			mutex_exit(&si_portp->siport_mutex);
1171 			return (SATA_FAILURE);
1172 		} else {
1173 			si_portmultp = &si_portp->siport_portmult_state;
1174 			port_type = si_portmultp->sipm_port_type[pmport];
1175 		}
1176 	} else {
1177 		port_type = si_portp->siport_port_type;
1178 	}
1179 
1180 	switch (port_type) {
1181 
1182 	case PORT_TYPE_DISK:
1183 		sd->satadev_type = SATA_DTYPE_ATADISK;
1184 		break;
1185 
1186 	case PORT_TYPE_ATAPI:
1187 		sd->satadev_type = SATA_DTYPE_ATAPICD;
1188 		break;
1189 
1190 	case PORT_TYPE_MULTIPLIER:
1191 		sd->satadev_type = SATA_DTYPE_PMULT;
1192 		sd->satadev_add_info =
1193 		    si_portp->siport_portmult_state.sipm_num_ports;
1194 		break;
1195 
1196 	case PORT_TYPE_UNKNOWN:
1197 		sd->satadev_type = SATA_DTYPE_UNKNOWN;
1198 		break;
1199 
1200 	default:
1201 		/* we don't support any other device types. */
1202 		sd->satadev_type = SATA_DTYPE_NONE;
1203 		break;
1204 	}
1205 	sd->satadev_state = SATA_STATE_READY;
1206 
1207 	if (qual == SATA_ADDR_PMPORT) {
1208 		(void) si_read_portmult_reg(si_ctlp, si_portp, cport,
1209 		    pmport, PSCR_REG0, &sd->satadev_scr.sstatus);
1210 		(void) si_read_portmult_reg(si_ctlp, si_portp, cport,
1211 		    pmport, PSCR_REG1, &sd->satadev_scr.serror);
1212 		(void) si_read_portmult_reg(si_ctlp, si_portp, cport,
1213 		    pmport, PSCR_REG2, &sd->satadev_scr.scontrol);
1214 		(void) si_read_portmult_reg(si_ctlp, si_portp, cport,
1215 		    pmport, PSCR_REG3, &sd->satadev_scr.sactive);
1216 	} else {
1217 		fill_dev_sregisters(si_ctlp, cport, sd);
1218 		if (!(si_portp->siport_active)) {
1219 			/*
1220 			 * Since we are implementing the port deactivation
1221 			 * in software only, we need to fake a valid value
1222 			 * for sstatus when the device is in deactivated state.
1223 			 */
1224 			SSTATUS_SET_DET(sd->satadev_scr.sstatus,
1225 			    SSTATUS_DET_PHYOFFLINE);
1226 			SSTATUS_SET_IPM(sd->satadev_scr.sstatus,
1227 			    SSTATUS_IPM_NODEV_NOPHY);
1228 			sd->satadev_state = SATA_PSTATE_SHUTDOWN;
1229 		}
1230 	}
1231 
1232 	mutex_exit(&si_portp->siport_mutex);
1233 	return (SATA_SUCCESS);
1234 }
1235 
1236 /*
1237  * Called by sata framework to transport a sata packet down stream.
1238  *
1239  * The actual work of building the FIS & transporting it to the hardware
1240  * is done out of the subroutine si_deliver_satapkt().
1241  */
1242 static int
si_tran_start(dev_info_t * dip,sata_pkt_t * spkt)1243 si_tran_start(dev_info_t *dip, sata_pkt_t *spkt)
1244 {
1245 	si_ctl_state_t *si_ctlp;
1246 	uint8_t	cport;
1247 	si_port_state_t *si_portp;
1248 	int slot;
1249 
1250 	cport = spkt->satapkt_device.satadev_addr.cport;
1251 	si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip));
1252 	mutex_enter(&si_ctlp->sictl_mutex);
1253 	si_portp = si_ctlp->sictl_ports[cport];
1254 	mutex_exit(&si_ctlp->sictl_mutex);
1255 
1256 	SIDBG_P(SIDBG_ENTRY, si_portp,
1257 	    "si_tran_start entry", NULL);
1258 
1259 	mutex_enter(&si_portp->siport_mutex);
1260 
1261 	if ((si_portp->siport_port_type == PORT_TYPE_NODEV) ||
1262 	    !si_portp->siport_active) {
1263 		/*
1264 		 * si_intr_phy_ready_change() may have rendered it to
1265 		 * PORT_TYPE_NODEV. cfgadm operation may have rendered
1266 		 * it inactive.
1267 		 */
1268 		spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1269 		fill_dev_sregisters(si_ctlp, cport, &spkt->satapkt_device);
1270 		mutex_exit(&si_portp->siport_mutex);
1271 		return (SATA_TRAN_PORT_ERROR);
1272 	}
1273 
1274 	if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) {
1275 		si_portp->siport_reset_in_progress = 0;
1276 		SIDBG_P(SIDBG_RESET, si_portp,
1277 		    "si_tran_start clearing the "
1278 		    "reset_in_progress for port", NULL);
1279 	}
1280 
1281 	if (si_portp->siport_reset_in_progress &&
1282 	    ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset &&
1283 	    ! ddi_in_panic()) {
1284 
1285 		spkt->satapkt_reason = SATA_PKT_BUSY;
1286 		SIDBG_P(SIDBG_RESET, si_portp,
1287 		    "si_tran_start returning BUSY while "
1288 		    "reset in progress for port", NULL);
1289 		mutex_exit(&si_portp->siport_mutex);
1290 		return (SATA_TRAN_BUSY);
1291 	}
1292 
1293 	if (si_portp->mopping_in_progress > 0) {
1294 		spkt->satapkt_reason = SATA_PKT_BUSY;
1295 		SIDBG_P(SIDBG_RESET, si_portp,
1296 		    "si_tran_start returning BUSY while "
1297 		    "mopping in progress for port", NULL);
1298 		mutex_exit(&si_portp->siport_mutex);
1299 		return (SATA_TRAN_BUSY);
1300 	}
1301 
1302 	if ((slot = si_deliver_satapkt(si_ctlp, si_portp, cport, spkt))
1303 	    == SI_FAILURE) {
1304 		spkt->satapkt_reason = SATA_PKT_QUEUE_FULL;
1305 		SIDBG_P(SIDBG_ERRS, si_portp,
1306 		    "si_tran_start returning QUEUE_FULL",
1307 		    NULL);
1308 		mutex_exit(&si_portp->siport_mutex);
1309 		return (SATA_TRAN_QUEUE_FULL);
1310 	}
1311 
1312 	if (spkt->satapkt_op_mode & (SATA_OPMODE_POLLING|SATA_OPMODE_SYNCH)) {
1313 		/* we need to poll now */
1314 		si_poll_cmd(si_ctlp, si_portp, cport, slot, spkt);
1315 		/*
1316 		 * The command has completed, and spkt will be freed by the
1317 		 * sata module, so don't keep a pointer to it lying around.
1318 		 */
1319 		si_portp->siport_slot_pkts[slot] = NULL;
1320 	}
1321 
1322 	mutex_exit(&si_portp->siport_mutex);
1323 	return (SATA_TRAN_ACCEPTED);
1324 }
1325 
1326 #define	SENDUP_PACKET(si_portp, satapkt, reason)			\
1327 	if (satapkt) {							\
1328 		if ((satapkt->satapkt_cmd.satacmd_cmd_reg ==		\
1329 					SATAC_WRITE_FPDMA_QUEUED) ||	\
1330 		    (satapkt->satapkt_cmd.satacmd_cmd_reg ==		\
1331 					SATAC_READ_FPDMA_QUEUED)) {	\
1332 			si_portp->siport_pending_ncq_count--;		\
1333 		}							\
1334 		satapkt->satapkt_reason = reason;			\
1335 		/*							\
1336 		 * We set the satapkt_reason in both synch and		\
1337 		 * non-synch cases.					\
1338 		 */							\
1339 		if (!(satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) &&	\
1340 			satapkt->satapkt_comp) {			\
1341 			mutex_exit(&si_portp->siport_mutex);		\
1342 			(*satapkt->satapkt_comp)(satapkt);		\
1343 			mutex_enter(&si_portp->siport_mutex);		\
1344 		}							\
1345 	}
1346 
1347 /*
1348  * Mopping is necessitated because of the si3124 hardware limitation.
1349  * The only way to recover from errors or to abort a command is to
1350  * reset the port/device but such a reset also results in throwing
1351  * away all the unfinished pending commands.
1352  *
1353  * A port or device is reset in four scenarios:
1354  *	a) some commands failed with errors
1355  *	b) or we need to timeout some commands
1356  *	c) or we need to abort some commands
1357  *	d) or we need reset the port at the request of sata framework
1358  *
1359  * In all these scenarios, we need to send any pending unfinished
1360  * commands up to sata framework.
1361  *
1362  * WARNING!!! siport_mutex should be acquired before the function is called.
1363  */
1364 static void
si_mop_commands(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,uint8_t port,uint32_t slot_status,uint32_t failed_tags,uint32_t timedout_tags,uint32_t aborting_tags,uint32_t reset_tags)1365 si_mop_commands(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp,
1366     uint8_t port, uint32_t slot_status, uint32_t failed_tags,
1367     uint32_t timedout_tags, uint32_t aborting_tags, uint32_t reset_tags)
1368 {
1369 	uint32_t finished_tags, unfinished_tags;
1370 	int tmpslot;
1371 	sata_pkt_t *satapkt;
1372 	struct sata_cmd_flags *flagsp;
1373 
1374 	SIDBG_P(SIDBG_ERRS, si_portp,
1375 	    "si_mop_commands entered: slot_status: 0x%x",
1376 	    slot_status);
1377 
1378 	SIDBG_P(SIDBG_ERRS, si_portp,
1379 	    "si_mop_commands: failed_tags: 0x%x, timedout_tags: 0x%x"
1380 	    "aborting_tags: 0x%x, reset_tags: 0x%x",
1381 	    failed_tags,
1382 	    timedout_tags,
1383 	    aborting_tags,
1384 	    reset_tags);
1385 
1386 	/*
1387 	 * We could be here for four reasons: abort, reset,
1388 	 * timeout or error handling. Only one such mopping
1389 	 * is allowed at a time.
1390 	 */
1391 
1392 	finished_tags =  si_portp->siport_pending_tags &
1393 	    ~slot_status & SI_SLOT_MASK;
1394 
1395 	unfinished_tags = slot_status & SI_SLOT_MASK &
1396 	    ~failed_tags &
1397 	    ~aborting_tags &
1398 	    ~reset_tags &
1399 	    ~timedout_tags;
1400 
1401 	/* Send up the finished_tags with SATA_PKT_COMPLETED. */
1402 	while (finished_tags) {
1403 		tmpslot = ddi_ffs(finished_tags) - 1;
1404 		if (tmpslot == -1) {
1405 			break;
1406 		}
1407 
1408 		satapkt = si_portp->siport_slot_pkts[tmpslot];
1409 
1410 		if (satapkt != NULL &&
1411 		    satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
1412 			si_copy_out_regs(&satapkt->satapkt_cmd, si_ctlp,
1413 			    port, tmpslot);
1414 		}
1415 
1416 		SIDBG_P(SIDBG_ERRS, si_portp,
1417 		    "si_mop_commands sending up completed satapkt: %x",
1418 		    satapkt);
1419 
1420 		CLEAR_BIT(si_portp->siport_pending_tags, tmpslot);
1421 		CLEAR_BIT(finished_tags, tmpslot);
1422 		SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED);
1423 	}
1424 
1425 	ASSERT(finished_tags == 0);
1426 
1427 	/* Send up failed_tags with SATA_PKT_DEV_ERROR. */
1428 	while (failed_tags) {
1429 		tmpslot = ddi_ffs(failed_tags) - 1;
1430 		if (tmpslot == -1) {
1431 			break;
1432 		}
1433 		SIDBG_P(SIDBG_ERRS, si_portp, "si3124: si_mop_commands: "
1434 		    "handling failed slot: 0x%x", tmpslot);
1435 
1436 		satapkt = si_portp->siport_slot_pkts[tmpslot];
1437 
1438 		if (satapkt != NULL) {
1439 
1440 			if (satapkt->satapkt_device.satadev_type ==
1441 			    SATA_DTYPE_ATAPICD) {
1442 				si_set_sense_data(satapkt, SATA_PKT_DEV_ERROR);
1443 			}
1444 
1445 
1446 			flagsp = &satapkt->satapkt_cmd.satacmd_flags;
1447 
1448 			flagsp->sata_copy_out_lba_low_msb = B_TRUE;
1449 			flagsp->sata_copy_out_lba_mid_msb = B_TRUE;
1450 			flagsp->sata_copy_out_lba_high_msb = B_TRUE;
1451 			flagsp->sata_copy_out_lba_low_lsb = B_TRUE;
1452 			flagsp->sata_copy_out_lba_mid_lsb = B_TRUE;
1453 			flagsp->sata_copy_out_lba_high_lsb = B_TRUE;
1454 			flagsp->sata_copy_out_error_reg = B_TRUE;
1455 			flagsp->sata_copy_out_sec_count_msb = B_TRUE;
1456 			flagsp->sata_copy_out_sec_count_lsb = B_TRUE;
1457 			flagsp->sata_copy_out_device_reg = B_TRUE;
1458 
1459 			si_copy_out_regs(&satapkt->satapkt_cmd, si_ctlp,
1460 			    port, tmpslot);
1461 
1462 			/*
1463 			 * In the case of NCQ command failures, the error is
1464 			 * overwritten by the one obtained from issuing of a
1465 			 * READ LOG EXTENDED command.
1466 			 */
1467 			if (si_portp->siport_err_tags_SDBERROR &
1468 			    (1 << tmpslot)) {
1469 				satapkt->satapkt_cmd.satacmd_error_reg =
1470 				    si_read_log_ext(si_ctlp, si_portp, port);
1471 			}
1472 		}
1473 
1474 		CLEAR_BIT(failed_tags, tmpslot);
1475 		CLEAR_BIT(si_portp->siport_pending_tags, tmpslot);
1476 		SENDUP_PACKET(si_portp, satapkt, SATA_PKT_DEV_ERROR);
1477 	}
1478 
1479 	ASSERT(failed_tags == 0);
1480 
1481 	/* Send up timedout_tags with SATA_PKT_TIMEOUT. */
1482 	while (timedout_tags) {
1483 		tmpslot = ddi_ffs(timedout_tags) - 1;
1484 		if (tmpslot == -1) {
1485 			break;
1486 		}
1487 
1488 		satapkt = si_portp->siport_slot_pkts[tmpslot];
1489 		SIDBG_P(SIDBG_ERRS, si_portp,
1490 		    "si_mop_commands sending "
1491 		    "spkt up with PKT_TIMEOUT: %x",
1492 		    satapkt);
1493 
1494 		CLEAR_BIT(si_portp->siport_pending_tags, tmpslot);
1495 		CLEAR_BIT(timedout_tags, tmpslot);
1496 		SENDUP_PACKET(si_portp, satapkt, SATA_PKT_TIMEOUT);
1497 	}
1498 
1499 	ASSERT(timedout_tags == 0);
1500 
1501 	/* Send up aborting packets with SATA_PKT_ABORTED. */
1502 	while (aborting_tags) {
1503 		tmpslot = ddi_ffs(aborting_tags) - 1;
1504 		if (tmpslot == -1) {
1505 			break;
1506 		}
1507 
1508 		satapkt = si_portp->siport_slot_pkts[tmpslot];
1509 		SIDBG_P(SIDBG_ERRS, si_portp,
1510 		    "si_mop_commands aborting spkt: %x",
1511 		    satapkt);
1512 		if (satapkt != NULL && satapkt->satapkt_device.satadev_type ==
1513 		    SATA_DTYPE_ATAPICD) {
1514 			si_set_sense_data(satapkt, SATA_PKT_ABORTED);
1515 		}
1516 
1517 		CLEAR_BIT(si_portp->siport_pending_tags, tmpslot);
1518 		CLEAR_BIT(aborting_tags, tmpslot);
1519 		SENDUP_PACKET(si_portp, satapkt, SATA_PKT_ABORTED);
1520 
1521 	}
1522 
1523 	ASSERT(aborting_tags == 0);
1524 
1525 	/* Reset tags are sent up to framework with SATA_PKT_RESET. */
1526 	while (reset_tags) {
1527 		tmpslot = ddi_ffs(reset_tags) - 1;
1528 		if (tmpslot == -1) {
1529 			break;
1530 		}
1531 		satapkt = si_portp->siport_slot_pkts[tmpslot];
1532 		SIDBG_P(SIDBG_ERRS, si_portp,
1533 		    "si_mop_commands sending PKT_RESET for "
1534 		    "reset spkt: %x",
1535 		    satapkt);
1536 
1537 		CLEAR_BIT(reset_tags, tmpslot);
1538 		CLEAR_BIT(si_portp->siport_pending_tags, tmpslot);
1539 		SENDUP_PACKET(si_portp, satapkt, SATA_PKT_RESET);
1540 	}
1541 
1542 	ASSERT(reset_tags == 0);
1543 
1544 	/* Send up the unfinished_tags with SATA_PKT_RESET. */
1545 	while (unfinished_tags) {
1546 		tmpslot = ddi_ffs(unfinished_tags) - 1;
1547 		if (tmpslot == -1) {
1548 			break;
1549 		}
1550 		satapkt = si_portp->siport_slot_pkts[tmpslot];
1551 		SIDBG_P(SIDBG_ERRS, si_portp,
1552 		    "si_mop_commands sending SATA_PKT_RESET for "
1553 		    "retry spkt: %x",
1554 		    satapkt);
1555 
1556 		CLEAR_BIT(unfinished_tags, tmpslot);
1557 		CLEAR_BIT(si_portp->siport_pending_tags, tmpslot);
1558 		SENDUP_PACKET(si_portp, satapkt, SATA_PKT_RESET);
1559 	}
1560 
1561 	ASSERT(unfinished_tags == 0);
1562 
1563 	si_portp->mopping_in_progress--;
1564 	ASSERT(si_portp->mopping_in_progress >= 0);
1565 }
1566 
1567 /*
1568  * Called by the sata framework to abort the previously sent packet(s).
1569  *
1570  * We reset the device and mop the commands on the port.
1571  */
1572 static int
si_tran_abort(dev_info_t * dip,sata_pkt_t * spkt,int flag)1573 si_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag)
1574 {
1575 	uint32_t slot_status;
1576 	uint8_t	port;
1577 	int tmpslot;
1578 	uint32_t aborting_tags;
1579 	uint32_t finished_tags;
1580 	si_port_state_t *si_portp;
1581 	si_ctl_state_t *si_ctlp;
1582 
1583 	port = spkt->satapkt_device.satadev_addr.cport;
1584 	si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip));
1585 	mutex_enter(&si_ctlp->sictl_mutex);
1586 	si_portp = si_ctlp->sictl_ports[port];
1587 	mutex_exit(&si_ctlp->sictl_mutex);
1588 
1589 	SIDBG_P(SIDBG_ERRS, si_portp, "si_tran_abort on port: %x", port);
1590 
1591 	mutex_enter(&si_portp->siport_mutex);
1592 
1593 	/*
1594 	 * If already mopping, then no need to abort anything.
1595 	 */
1596 	if (si_portp->mopping_in_progress > 0) {
1597 		SIDBG_P(SIDBG_ERRS, si_portp,
1598 		    "si_tran_abort: port %d mopping "
1599 		    "in progress, so just return", port);
1600 		mutex_exit(&si_portp->siport_mutex);
1601 		return (SATA_SUCCESS);
1602 	}
1603 
1604 	if ((si_portp->siport_port_type == PORT_TYPE_NODEV) ||
1605 	    !si_portp->siport_active) {
1606 		/*
1607 		 * si_intr_phy_ready_change() may have rendered it to
1608 		 * PORT_TYPE_NODEV. cfgadm operation may have rendered
1609 		 * it inactive.
1610 		 */
1611 		spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1612 		fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device);
1613 		mutex_exit(&si_portp->siport_mutex);
1614 		return (SATA_FAILURE);
1615 	}
1616 
1617 	if (flag == SATA_ABORT_ALL_PACKETS) {
1618 		aborting_tags = si_portp->siport_pending_tags;
1619 	} else {
1620 		/*
1621 		 * Need to abort a single packet.
1622 		 * Search our siport_slot_pkts[] list for matching spkt.
1623 		 */
1624 		aborting_tags = 0xffffffff; /* 0xffffffff is impossible tag */
1625 		for (tmpslot = 0; tmpslot < SI_NUM_SLOTS; tmpslot++) {
1626 			if (si_portp->siport_slot_pkts[tmpslot] == spkt) {
1627 				aborting_tags = (0x1 << tmpslot);
1628 				break;
1629 			}
1630 		}
1631 
1632 		if (aborting_tags == 0xffffffff) {
1633 			/* requested packet is not on pending list. */
1634 			fill_dev_sregisters(si_ctlp, port,
1635 			    &spkt->satapkt_device);
1636 			mutex_exit(&si_portp->siport_mutex);
1637 			return (SATA_FAILURE);
1638 		}
1639 	}
1640 
1641 	si_portp->mopping_in_progress++;
1642 
1643 	slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle,
1644 	    (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port)));
1645 	(void) si_reset_dport_wait_till_ready(si_ctlp, si_portp,
1646 	    port, SI_DEVICE_RESET);
1647 
1648 	/*
1649 	 * Compute which have finished and which need to be retried.
1650 	 *
1651 	 * The finished tags are siport_pending_tags minus the slot_status.
1652 	 * The aborting_tags have to be reduced by finished_tags since we
1653 	 * can't possibly abort a tag which had finished already.
1654 	 */
1655 	finished_tags =  si_portp->siport_pending_tags &
1656 	    ~slot_status & SI_SLOT_MASK;
1657 	aborting_tags &= ~finished_tags;
1658 
1659 	si_mop_commands(si_ctlp,
1660 	    si_portp,
1661 	    port,
1662 	    slot_status,
1663 	    0, /* failed_tags */
1664 	    0, /* timedout_tags */
1665 	    aborting_tags,
1666 	    0); /* reset_tags */
1667 
1668 	fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device);
1669 	mutex_exit(&si_portp->siport_mutex);
1670 	return (SATA_SUCCESS);
1671 }
1672 
1673 
1674 /*
1675  * Used to reject all the pending packets on a port during a reset
1676  * operation.
1677  *
1678  * WARNING, WARNING: The caller is expected to obtain the siport_mutex
1679  * before calling us.
1680  */
1681 static void
si_reject_all_reset_pkts(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port)1682 si_reject_all_reset_pkts(
1683 	si_ctl_state_t *si_ctlp,
1684 	si_port_state_t *si_portp,
1685 	int port)
1686 {
1687 	uint32_t slot_status;
1688 	uint32_t reset_tags;
1689 
1690 	_NOTE(ASSUMING_PROTECTED(si_portp))
1691 
1692 	SIDBG_P(SIDBG_RESET, si_portp,
1693 	    "si_reject_all_reset_pkts on port: %x",
1694 	    port);
1695 
1696 	slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle,
1697 	    (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port)));
1698 
1699 	/* Compute which tags need to be sent up. */
1700 	reset_tags = slot_status & SI_SLOT_MASK;
1701 
1702 	si_portp->mopping_in_progress++;
1703 
1704 	si_mop_commands(si_ctlp,
1705 	    si_portp,
1706 	    port,
1707 	    slot_status,
1708 	    0, /* failed_tags */
1709 	    0, /* timedout_tags */
1710 	    0, /* aborting_tags */
1711 	    reset_tags);
1712 }
1713 
1714 
1715 /*
1716  * Called by sata framework to reset a port(s) or device.
1717  *
1718  */
1719 static int
si_tran_reset_dport(dev_info_t * dip,sata_device_t * sd)1720 si_tran_reset_dport(dev_info_t *dip, sata_device_t *sd)
1721 {
1722 	si_ctl_state_t	*si_ctlp;
1723 	uint8_t port = sd->satadev_addr.cport;
1724 	int i;
1725 	si_port_state_t *si_portp;
1726 	int retval = SI_SUCCESS;
1727 
1728 	si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip));
1729 	SIDBG_C(SIDBG_RESET, si_ctlp,
1730 	    "si_tran_reset_port entry: port: 0x%x",
1731 	    port);
1732 
1733 	switch (sd->satadev_addr.qual) {
1734 	case SATA_ADDR_CPORT:
1735 		mutex_enter(&si_ctlp->sictl_mutex);
1736 		si_portp = si_ctlp->sictl_ports[port];
1737 		mutex_exit(&si_ctlp->sictl_mutex);
1738 
1739 		mutex_enter(&si_portp->siport_mutex);
1740 
1741 		/*
1742 		 * If already mopping, then no need to reset or mop again.
1743 		 */
1744 		if (si_portp->mopping_in_progress > 0) {
1745 			SIDBG_P(SIDBG_RESET, si_portp,
1746 			    "si_tran_reset_dport: CPORT port %d mopping "
1747 			    "in progress, so just return", port);
1748 			mutex_exit(&si_portp->siport_mutex);
1749 			retval = SI_SUCCESS;
1750 			break;
1751 		}
1752 
1753 		retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port,
1754 		    SI_PORT_RESET);
1755 		si_reject_all_reset_pkts(si_ctlp,  si_portp, port);
1756 		mutex_exit(&si_portp->siport_mutex);
1757 
1758 		break;
1759 
1760 	case SATA_ADDR_DCPORT:
1761 		mutex_enter(&si_ctlp->sictl_mutex);
1762 		si_portp = si_ctlp->sictl_ports[port];
1763 		mutex_exit(&si_ctlp->sictl_mutex);
1764 
1765 		mutex_enter(&si_portp->siport_mutex);
1766 
1767 		if ((si_portp->siport_port_type == PORT_TYPE_NODEV) ||
1768 		    !si_portp->siport_active) {
1769 			mutex_exit(&si_portp->siport_mutex);
1770 			retval = SI_FAILURE;
1771 			break;
1772 		}
1773 
1774 		/*
1775 		 * If already mopping, then no need to reset or mop again.
1776 		 */
1777 		if (si_portp->mopping_in_progress > 0) {
1778 			SIDBG_P(SIDBG_RESET, si_portp,
1779 			    "si_tran_reset_dport: DCPORT port %d mopping "
1780 			    "in progress, so just return", port);
1781 			mutex_exit(&si_portp->siport_mutex);
1782 			retval = SI_SUCCESS;
1783 			break;
1784 		}
1785 
1786 		retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port,
1787 		    SI_DEVICE_RESET);
1788 		si_reject_all_reset_pkts(si_ctlp,  si_portp, port);
1789 		mutex_exit(&si_portp->siport_mutex);
1790 
1791 		break;
1792 
1793 	case SATA_ADDR_CNTRL:
1794 		for (i = 0; i < si_ctlp->sictl_num_ports; i++) {
1795 			mutex_enter(&si_ctlp->sictl_mutex);
1796 			si_portp = si_ctlp->sictl_ports[i];
1797 			mutex_exit(&si_ctlp->sictl_mutex);
1798 
1799 			mutex_enter(&si_portp->siport_mutex);
1800 
1801 			/*
1802 			 * If mopping, then all the pending commands are being
1803 			 * mopped, therefore there is nothing else to do.
1804 			 */
1805 			if (si_portp->mopping_in_progress > 0) {
1806 				SIDBG_P(SIDBG_RESET, si_portp,
1807 				    "si_tran_reset_dport: CNTRL port %d mopping"
1808 				    " in progress, so just return", i);
1809 				mutex_exit(&si_portp->siport_mutex);
1810 				retval = SI_SUCCESS;
1811 				break;
1812 			}
1813 
1814 			retval = si_reset_dport_wait_till_ready(si_ctlp,
1815 			    si_portp, i, SI_PORT_RESET);
1816 			if (retval) {
1817 				mutex_exit(&si_portp->siport_mutex);
1818 				break;
1819 			}
1820 			si_reject_all_reset_pkts(si_ctlp,  si_portp, i);
1821 			mutex_exit(&si_portp->siport_mutex);
1822 		}
1823 		break;
1824 
1825 	case SATA_ADDR_PMPORT:
1826 	case SATA_ADDR_DPMPORT:
1827 		SIDBG_P(SIDBG_RESET, si_portp,
1828 		    "port mult reset not implemented yet", NULL);
1829 		/* FALLTHROUGH */
1830 
1831 	default:
1832 		retval = SI_FAILURE;
1833 
1834 	}
1835 
1836 	return (retval);
1837 }
1838 
1839 
1840 /*
1841  * Called by sata framework to activate a port as part of hotplug.
1842  *
1843  * Note: Not port-mult aware.
1844  */
1845 static int
si_tran_hotplug_port_activate(dev_info_t * dip,sata_device_t * satadev)1846 si_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev)
1847 {
1848 	si_ctl_state_t *si_ctlp;
1849 	si_port_state_t *si_portp;
1850 	uint8_t	port;
1851 
1852 	si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip));
1853 	port = satadev->satadev_addr.cport;
1854 	mutex_enter(&si_ctlp->sictl_mutex);
1855 	si_portp = si_ctlp->sictl_ports[port];
1856 	mutex_exit(&si_ctlp->sictl_mutex);
1857 
1858 	SIDBG_P(SIDBG_EVENT, si_portp, "si_tran_hotplug_port_activate entry",
1859 	    NULL);
1860 
1861 	mutex_enter(&si_portp->siport_mutex);
1862 	si_enable_port_interrupts(si_ctlp, port);
1863 
1864 	/*
1865 	 * Reset the device so that a si_find_dev_signature() would trigger.
1866 	 * But this reset is an internal operation; the sata framework does
1867 	 * not need to know about it.
1868 	 */
1869 	(void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port,
1870 	    SI_DEVICE_RESET|SI_RESET_NO_EVENTS_UP);
1871 
1872 	satadev->satadev_state = SATA_STATE_READY;
1873 
1874 	si_portp->siport_active = PORT_ACTIVE;
1875 
1876 	fill_dev_sregisters(si_ctlp, port, satadev);
1877 
1878 	mutex_exit(&si_portp->siport_mutex);
1879 	return (SATA_SUCCESS);
1880 }
1881 
1882 /*
1883  * Called by sata framework to deactivate a port as part of hotplug.
1884  *
1885  * Note: Not port-mult aware.
1886  */
1887 static int
si_tran_hotplug_port_deactivate(dev_info_t * dip,sata_device_t * satadev)1888 si_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev)
1889 {
1890 	si_ctl_state_t *si_ctlp;
1891 	si_port_state_t *si_portp;
1892 	uint8_t	port;
1893 
1894 	si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip));
1895 	port = satadev->satadev_addr.cport;
1896 	mutex_enter(&si_ctlp->sictl_mutex);
1897 	si_portp = si_ctlp->sictl_ports[port];
1898 	mutex_exit(&si_ctlp->sictl_mutex);
1899 
1900 	SIDBG(SIDBG_EVENT, "si_tran_hotplug_port_deactivate entry", NULL);
1901 
1902 	mutex_enter(&si_portp->siport_mutex);
1903 	if (si_portp->siport_pending_tags & SI_SLOT_MASK) {
1904 		/*
1905 		 * There are pending commands on this port.
1906 		 * Fail the deactivate request.
1907 		 */
1908 		satadev->satadev_state = SATA_STATE_READY;
1909 		mutex_exit(&si_portp->siport_mutex);
1910 		return (SATA_FAILURE);
1911 	}
1912 
1913 	/* mark the device as not accessible any more. */
1914 	si_portp->siport_active = PORT_INACTIVE;
1915 
1916 	/* disable the interrupts on the port. */
1917 	si_disable_port_interrupts(si_ctlp, port);
1918 
1919 	satadev->satadev_state = SATA_PSTATE_SHUTDOWN;
1920 
1921 	fill_dev_sregisters(si_ctlp, port, satadev);
1922 	/*
1923 	 * Since we are implementing the port deactivation in software only,
1924 	 * we need to fake a valid value for sstatus.
1925 	 */
1926 	SSTATUS_SET_DET(satadev->satadev_scr.sstatus, SSTATUS_DET_PHYOFFLINE);
1927 	SSTATUS_SET_IPM(satadev->satadev_scr.sstatus, SSTATUS_IPM_NODEV_NOPHY);
1928 
1929 	mutex_exit(&si_portp->siport_mutex);
1930 	return (SATA_SUCCESS);
1931 }
1932 
1933 
1934 /*
1935  * Allocates the si_port_state_t.
1936  */
1937 static int
si_alloc_port_state(si_ctl_state_t * si_ctlp,int port)1938 si_alloc_port_state(si_ctl_state_t *si_ctlp, int port)
1939 {
1940 	si_port_state_t *si_portp;
1941 
1942 	si_ctlp->sictl_ports[port] = (si_port_state_t *)kmem_zalloc(
1943 	    sizeof (si_port_state_t), KM_SLEEP);
1944 
1945 	si_portp = si_ctlp->sictl_ports[port];
1946 	mutex_init(&si_portp->siport_mutex, NULL, MUTEX_DRIVER,
1947 	    (void *)(uintptr_t)si_ctlp->sictl_intr_pri);
1948 	mutex_enter(&si_portp->siport_mutex);
1949 
1950 	/* allocate prb & sgt pkts for this port. */
1951 	if (si_alloc_prbpool(si_ctlp, port)) {
1952 		mutex_exit(&si_portp->siport_mutex);
1953 		kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t));
1954 		return (SI_FAILURE);
1955 	}
1956 	if (si_alloc_sgbpool(si_ctlp, port)) {
1957 		si_dealloc_prbpool(si_ctlp, port);
1958 		mutex_exit(&si_portp->siport_mutex);
1959 		kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t));
1960 		return (SI_FAILURE);
1961 	}
1962 
1963 	/* Allocate the argument for the timeout */
1964 	si_portp->siport_event_args =
1965 	    kmem_zalloc(sizeof (si_event_arg_t), KM_SLEEP);
1966 
1967 	si_portp->siport_active = PORT_ACTIVE;
1968 	mutex_exit(&si_portp->siport_mutex);
1969 
1970 	return (SI_SUCCESS);
1971 
1972 }
1973 
1974 /*
1975  * Deallocates the si_port_state_t.
1976  */
1977 static void
si_dealloc_port_state(si_ctl_state_t * si_ctlp,int port)1978 si_dealloc_port_state(si_ctl_state_t *si_ctlp, int port)
1979 {
1980 	si_port_state_t *si_portp;
1981 	si_portp = si_ctlp->sictl_ports[port];
1982 
1983 	mutex_enter(&si_portp->siport_mutex);
1984 	kmem_free(si_portp->siport_event_args, sizeof (si_event_arg_t));
1985 	si_dealloc_sgbpool(si_ctlp, port);
1986 	si_dealloc_prbpool(si_ctlp, port);
1987 	mutex_exit(&si_portp->siport_mutex);
1988 
1989 	mutex_destroy(&si_portp->siport_mutex);
1990 
1991 	kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t));
1992 
1993 }
1994 
1995 /*
1996  * Allocates the SGB (Scatter Gather Block) incore buffer.
1997  */
1998 static int
si_alloc_sgbpool(si_ctl_state_t * si_ctlp,int port)1999 si_alloc_sgbpool(si_ctl_state_t *si_ctlp, int port)
2000 {
2001 	si_port_state_t *si_portp;
2002 	uint_t cookie_count;
2003 	size_t incore_sgbpool_size = SI_NUM_SLOTS * sizeof (si_sgblock_t)
2004 	    * si_dma_sg_number;
2005 	size_t ret_len;
2006 	ddi_dma_cookie_t sgbpool_dma_cookie;
2007 
2008 	si_portp = si_ctlp->sictl_ports[port];
2009 
2010 	/* allocate sgbpool dma handle. */
2011 	if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop,
2012 	    &prb_sgt_dma_attr,
2013 	    DDI_DMA_SLEEP,
2014 	    NULL,
2015 	    &si_portp->siport_sgbpool_dma_handle) !=
2016 	    DDI_SUCCESS) {
2017 
2018 		return (SI_FAILURE);
2019 	}
2020 
2021 	/* allocate the memory for sgbpool. */
2022 	if (ddi_dma_mem_alloc(si_portp->siport_sgbpool_dma_handle,
2023 	    incore_sgbpool_size,
2024 	    &accattr,
2025 	    DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
2026 	    DDI_DMA_SLEEP,
2027 	    NULL,
2028 	    (caddr_t *)&si_portp->siport_sgbpool,
2029 	    &ret_len,
2030 	    &si_portp->siport_sgbpool_acc_handle) != DDI_SUCCESS) {
2031 
2032 		/*  error.. free the dma handle. */
2033 		ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle);
2034 		return (SI_FAILURE);
2035 	}
2036 
2037 	/* now bind it */
2038 	if (ddi_dma_addr_bind_handle(si_portp->siport_sgbpool_dma_handle,
2039 	    NULL,
2040 	    (caddr_t)si_portp->siport_sgbpool,
2041 	    incore_sgbpool_size,
2042 	    DDI_DMA_CONSISTENT,
2043 	    DDI_DMA_SLEEP,
2044 	    NULL,
2045 	    &sgbpool_dma_cookie,
2046 	    &cookie_count) !=  DDI_DMA_MAPPED) {
2047 		/*  error.. free the dma handle & free the memory. */
2048 		ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle);
2049 		ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle);
2050 		return (SI_FAILURE);
2051 	}
2052 
2053 	si_portp->siport_sgbpool_physaddr = sgbpool_dma_cookie.dmac_laddress;
2054 	return (SI_SUCCESS);
2055 }
2056 
2057 /*
2058  * Deallocates the SGB (Scatter Gather Block) incore buffer.
2059  */
2060 static void
si_dealloc_sgbpool(si_ctl_state_t * si_ctlp,int port)2061 si_dealloc_sgbpool(si_ctl_state_t *si_ctlp, int port)
2062 {
2063 	si_port_state_t *si_portp = si_ctlp->sictl_ports[port];
2064 
2065 	/* Unbind the dma handle first. */
2066 	(void) ddi_dma_unbind_handle(si_portp->siport_sgbpool_dma_handle);
2067 
2068 	/* Then free the underlying memory. */
2069 	ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle);
2070 
2071 	/* Now free the handle itself. */
2072 	ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle);
2073 
2074 }
2075 
2076 /*
2077  * Allocates the PRB (Port Request Block) incore packets.
2078  */
2079 static int
si_alloc_prbpool(si_ctl_state_t * si_ctlp,int port)2080 si_alloc_prbpool(si_ctl_state_t *si_ctlp, int port)
2081 {
2082 	si_port_state_t *si_portp;
2083 	uint_t cookie_count;
2084 	size_t incore_pkt_size = SI_NUM_SLOTS * sizeof (si_prb_t);
2085 	size_t ret_len;
2086 	ddi_dma_cookie_t prbpool_dma_cookie;
2087 
2088 	si_portp = si_ctlp->sictl_ports[port];
2089 
2090 	/* allocate prb pkts. */
2091 	if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop,
2092 	    &prb_sgt_dma_attr,
2093 	    DDI_DMA_SLEEP,
2094 	    NULL,
2095 	    &si_portp->siport_prbpool_dma_handle) !=
2096 	    DDI_SUCCESS) {
2097 
2098 		return (SI_FAILURE);
2099 	}
2100 
2101 	if (ddi_dma_mem_alloc(si_portp->siport_prbpool_dma_handle,
2102 	    incore_pkt_size,
2103 	    &accattr,
2104 	    DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
2105 	    DDI_DMA_SLEEP,
2106 	    NULL,
2107 	    (caddr_t *)&si_portp->siport_prbpool,
2108 	    &ret_len,
2109 	    &si_portp->siport_prbpool_acc_handle) != DDI_SUCCESS) {
2110 
2111 		/* error.. free the dma handle. */
2112 		ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle);
2113 		return (SI_FAILURE);
2114 	}
2115 
2116 	if (ddi_dma_addr_bind_handle(si_portp->siport_prbpool_dma_handle,
2117 	    NULL,
2118 	    (caddr_t)si_portp->siport_prbpool,
2119 	    incore_pkt_size,
2120 	    DDI_DMA_CONSISTENT,
2121 	    DDI_DMA_SLEEP,
2122 	    NULL,
2123 	    &prbpool_dma_cookie,
2124 	    &cookie_count) !=  DDI_DMA_MAPPED) {
2125 		/*  error.. free the dma handle & free the memory. */
2126 		ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle);
2127 		ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle);
2128 		return (SI_FAILURE);
2129 	}
2130 
2131 	si_portp->siport_prbpool_physaddr =
2132 	    prbpool_dma_cookie.dmac_laddress;
2133 	return (SI_SUCCESS);
2134 }
2135 
2136 /*
2137  * Deallocates the PRB (Port Request Block) incore packets.
2138  */
2139 static void
si_dealloc_prbpool(si_ctl_state_t * si_ctlp,int port)2140 si_dealloc_prbpool(si_ctl_state_t *si_ctlp, int port)
2141 {
2142 	si_port_state_t *si_portp = si_ctlp->sictl_ports[port];
2143 
2144 	/* Unbind the prb dma handle first. */
2145 	(void) ddi_dma_unbind_handle(si_portp->siport_prbpool_dma_handle);
2146 
2147 	/* Then free the underlying memory. */
2148 	ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle);
2149 
2150 	/* Now free the handle itself. */
2151 	ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle);
2152 
2153 }
2154 
2155 
2156 
2157 /*
2158  * Soft-reset the port to find the signature of the device connected to
2159  * the port.
2160  */
2161 static void
si_find_dev_signature(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port,int pmp)2162 si_find_dev_signature(
2163 	si_ctl_state_t *si_ctlp,
2164 	si_port_state_t *si_portp,
2165 	int port,
2166 	int pmp)
2167 {
2168 	si_prb_t *prb;
2169 	uint32_t slot_status, signature;
2170 	int slot, loop_count;
2171 
2172 	SIDBG_P(SIDBG_INIT, si_portp,
2173 	    "si_find_dev_signature enter: port: %x, pmp: %x",
2174 	    port, pmp);
2175 
2176 	/* Build a Soft Reset PRB in host memory. */
2177 	mutex_enter(&si_portp->siport_mutex);
2178 
2179 	slot = si_claim_free_slot(si_ctlp, si_portp, port);
2180 	if (slot == SI_FAILURE) {
2181 		/* Empty slot could not be found. */
2182 		if (pmp != PORTMULT_CONTROL_PORT) {
2183 			/* We are behind port multiplier. */
2184 			si_portp->siport_portmult_state.sipm_port_type[pmp] =
2185 			    PORT_TYPE_NODEV;
2186 		} else {
2187 			si_portp->siport_port_type = PORT_TYPE_NODEV;
2188 		}
2189 
2190 		mutex_exit(&si_portp->siport_mutex);
2191 		return;
2192 	}
2193 	prb = &si_portp->siport_prbpool[slot];
2194 	bzero((void *)prb, sizeof (si_prb_t));
2195 
2196 	SET_FIS_PMP(prb->prb_fis, pmp);
2197 	SET_PRB_CONTROL_SOFT_RESET(prb);
2198 
2199 #if SI_DEBUG
2200 	if (si_debug_flags & SIDBG_DUMP_PRB) {
2201 		char *ptr;
2202 		int j;
2203 
2204 		ptr = (char *)prb;
2205 		cmn_err(CE_WARN, "si_find_dev_signature, prb: ");
2206 		for (j = 0; j < (sizeof (si_prb_t)); j++) {
2207 			if (j%4 == 0) {
2208 				cmn_err(CE_WARN, "----");
2209 			}
2210 			cmn_err(CE_WARN, "%x ", ptr[j]);
2211 		}
2212 
2213 	}
2214 #endif /* SI_DEBUG */
2215 
2216 	/* deliver soft reset prb to empty slot. */
2217 	POST_PRB_ADDR(si_ctlp, si_portp, port, slot);
2218 
2219 	loop_count = 0;
2220 	/* Loop till the soft reset is finished. */
2221 	do {
2222 		slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle,
2223 		    (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port)));
2224 
2225 		if (loop_count++ > SI_POLLRATE_SOFT_RESET) {
2226 			/* We are effectively timing out after 10 sec. */
2227 			break;
2228 		}
2229 
2230 		/* Wait for 10 millisec */
2231 #ifndef __lock_lint
2232 		delay(SI_10MS_TICKS);
2233 #endif /* __lock_lint */
2234 
2235 	} while (slot_status & SI_SLOT_MASK & (0x1 << slot));
2236 
2237 	SIDBG_P(SIDBG_POLL_LOOP, si_portp,
2238 	    "si_find_dev_signature: loop count: %d, slot_status: 0x%x",
2239 	    loop_count, slot_status);
2240 
2241 	CLEAR_BIT(si_portp->siport_pending_tags, slot);
2242 
2243 	/* Read device signature from command slot. */
2244 	signature = ddi_get32(si_ctlp->sictl_port_acc_handle,
2245 	    (uint32_t *)(PORT_SIGNATURE_MSB(si_ctlp, port, slot)));
2246 	signature <<= 8;
2247 	signature |= (0xff & ddi_get32(si_ctlp->sictl_port_acc_handle,
2248 	    (uint32_t *)(PORT_SIGNATURE_LSB(si_ctlp,
2249 	    port, slot))));
2250 
2251 	SIDBG_P(SIDBG_INIT, si_portp, "Device signature: 0x%x", signature);
2252 
2253 	if (signature == SI_SIGNATURE_PORT_MULTIPLIER) {
2254 
2255 		SIDBG_P(SIDBG_INIT, si_portp,
2256 		    "Found multiplier at cport: 0x%d, pmport: 0x%x",
2257 		    port, pmp);
2258 
2259 		if (pmp != PORTMULT_CONTROL_PORT) {
2260 			/*
2261 			 * It is wrong to chain a port multiplier behind
2262 			 * another port multiplier.
2263 			 */
2264 			si_portp->siport_portmult_state.sipm_port_type[pmp] =
2265 			    PORT_TYPE_NODEV;
2266 		} else {
2267 			si_portp->siport_port_type = PORT_TYPE_MULTIPLIER;
2268 			mutex_exit(&si_portp->siport_mutex);
2269 			(void) si_enumerate_port_multiplier(si_ctlp,
2270 			    si_portp, port);
2271 			mutex_enter(&si_portp->siport_mutex);
2272 		}
2273 		si_init_port(si_ctlp, port);
2274 
2275 	} else if (signature == SI_SIGNATURE_ATAPI) {
2276 		if (pmp != PORTMULT_CONTROL_PORT) {
2277 			/* We are behind port multiplier. */
2278 			si_portp->siport_portmult_state.sipm_port_type[pmp] =
2279 			    PORT_TYPE_ATAPI;
2280 		} else {
2281 			si_portp->siport_port_type = PORT_TYPE_ATAPI;
2282 			si_init_port(si_ctlp, port);
2283 		}
2284 		SIDBG_P(SIDBG_INIT, si_portp,
2285 		    "Found atapi at : cport: %x, pmport: %x",
2286 		    port, pmp);
2287 
2288 	} else if (signature == SI_SIGNATURE_DISK) {
2289 
2290 		if (pmp != PORTMULT_CONTROL_PORT) {
2291 			/* We are behind port multiplier. */
2292 			si_portp->siport_portmult_state.sipm_port_type[pmp] =
2293 			    PORT_TYPE_DISK;
2294 		} else {
2295 			si_portp->siport_port_type = PORT_TYPE_DISK;
2296 			si_init_port(si_ctlp, port);
2297 		}
2298 		SIDBG_P(SIDBG_INIT, si_portp,
2299 		    "found disk at : cport: %x, pmport: %x",
2300 		    port, pmp);
2301 
2302 	} else {
2303 		if (pmp != PORTMULT_CONTROL_PORT) {
2304 			/* We are behind port multiplier. */
2305 			si_portp->siport_portmult_state.sipm_port_type[pmp] =
2306 			    PORT_TYPE_UNKNOWN;
2307 		} else {
2308 			si_portp->siport_port_type = PORT_TYPE_UNKNOWN;
2309 		}
2310 		SIDBG_P(SIDBG_INIT, si_portp,
2311 		    "Found unknown signature 0x%x at: port: %x, pmp: %x",
2312 		    signature, port, pmp);
2313 	}
2314 
2315 	mutex_exit(&si_portp->siport_mutex);
2316 }
2317 
2318 
2319 /*
2320  * Polls for the completion of the command. This is safe with both
2321  * interrupts enabled or disabled.
2322  */
2323 static void
si_poll_cmd(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port,int slot,sata_pkt_t * satapkt)2324 si_poll_cmd(
2325 	si_ctl_state_t *si_ctlp,
2326 	si_port_state_t *si_portp,
2327 	int port,
2328 	int slot,
2329 	sata_pkt_t *satapkt)
2330 {
2331 	uint32_t slot_status;
2332 	int pkt_timeout_ticks;
2333 	uint32_t port_intr_status;
2334 	int in_panic = ddi_in_panic();
2335 
2336 	SIDBG_P(SIDBG_ENTRY, si_portp, "si_poll_cmd entered: port: 0x%x", port);
2337 
2338 	pkt_timeout_ticks = drv_usectohz((clock_t)satapkt->satapkt_time *
2339 	    1000000);
2340 
2341 
2342 	/* we start out with SATA_PKT_COMPLETED as the satapkt_reason */
2343 	satapkt->satapkt_reason = SATA_PKT_COMPLETED;
2344 
2345 	do {
2346 		slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle,
2347 		    (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port)));
2348 
2349 		if (slot_status & SI_SLOT_MASK & (0x1 << slot)) {
2350 			if (in_panic) {
2351 				/*
2352 				 * If we are in panic, we can't rely on
2353 				 * timers; so, busy wait instead of delay().
2354 				 */
2355 				mutex_exit(&si_portp->siport_mutex);
2356 				drv_usecwait(SI_1MS_USECS);
2357 				mutex_enter(&si_portp->siport_mutex);
2358 			} else {
2359 				mutex_exit(&si_portp->siport_mutex);
2360 #ifndef __lock_lint
2361 				delay(SI_1MS_TICKS);
2362 #endif /* __lock_lint */
2363 				mutex_enter(&si_portp->siport_mutex);
2364 			}
2365 		} else {
2366 			break;
2367 		}
2368 
2369 		pkt_timeout_ticks -= SI_1MS_TICKS;
2370 
2371 	} while (pkt_timeout_ticks > 0);
2372 
2373 	if (satapkt->satapkt_reason != SATA_PKT_COMPLETED) {
2374 		/* The si_mop_command() got to our packet before us */
2375 
2376 		return;
2377 	}
2378 
2379 	/*
2380 	 * Interrupts and timers may not be working properly in a crash dump
2381 	 * situation; we may need to handle all the three conditions here:
2382 	 * successful completion, packet failure and packet timeout.
2383 	 */
2384 	if (IS_ATTENTION_RAISED(slot_status)) { /* error seen on port */
2385 
2386 		port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle,
2387 		    (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port));
2388 
2389 		SIDBG_P(SIDBG_VERBOSE, si_portp,
2390 		    "si_poll_cmd: port_intr_status: 0x%x, port: %x",
2391 		    port_intr_status, port);
2392 
2393 		if (port_intr_status & INTR_COMMAND_ERROR) {
2394 			mutex_exit(&si_portp->siport_mutex);
2395 			(void) si_intr_command_error(si_ctlp, si_portp, port);
2396 			mutex_enter(&si_portp->siport_mutex);
2397 
2398 			return;
2399 
2400 			/*
2401 			 * Why do we need to call si_intr_command_error() ?
2402 			 *
2403 			 * Answer: Even if the current packet is not the
2404 			 * offending command, we need to restart the stalled
2405 			 * port; (may be, the interrupts are not working well
2406 			 * in panic condition). The call to routine
2407 			 * si_intr_command_error() will achieve that.
2408 			 *
2409 			 * What if the interrupts are working fine and the
2410 			 * si_intr_command_error() gets called once more from
2411 			 * interrupt context ?
2412 			 *
2413 			 * Answer: The second instance of routine
2414 			 * si_intr_command_error() will not mop anything
2415 			 * since the first error handler has already blown
2416 			 * away the hardware pending queues through reset.
2417 			 *
2418 			 * Will the si_intr_command_error() hurt current
2419 			 * packet ?
2420 			 *
2421 			 * Answer: No.
2422 			 */
2423 		} else {
2424 			/* Ignore any non-error interrupts at this stage */
2425 			ddi_put32(si_ctlp->sictl_port_acc_handle,
2426 			    (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp,
2427 			    port)),
2428 			    port_intr_status & INTR_MASK);
2429 		}
2430 
2431 	} else if (slot_status & SI_SLOT_MASK & (0x1 << slot)) {
2432 		satapkt->satapkt_reason = SATA_PKT_TIMEOUT;
2433 
2434 	} /* else: the command completed successfully */
2435 
2436 	if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
2437 		si_copy_out_regs(&satapkt->satapkt_cmd, si_ctlp, port, slot);
2438 	}
2439 
2440 	if ((satapkt->satapkt_cmd.satacmd_cmd_reg ==
2441 	    SATAC_WRITE_FPDMA_QUEUED) ||
2442 	    (satapkt->satapkt_cmd.satacmd_cmd_reg ==
2443 	    SATAC_READ_FPDMA_QUEUED)) {
2444 		si_portp->siport_pending_ncq_count--;
2445 	}
2446 
2447 	CLEAR_BIT(si_portp->siport_pending_tags, slot);
2448 
2449 	/*
2450 	 * tidbit: What is the interaction of abort with polling ?
2451 	 * What happens if the current polled pkt is aborted in parallel ?
2452 	 *
2453 	 * Answer: Assuming that the si_mop_commands() completes ahead
2454 	 * of polling, all it does is to set the satapkt_reason to
2455 	 * SPKT_PKT_ABORTED. That would be fine with us.
2456 	 *
2457 	 * The same logic applies to reset interacting with polling.
2458 	 */
2459 }
2460 
2461 
2462 /*
2463  * Searches for and claims a free slot.
2464  *
2465  * Returns:	SI_FAILURE if no slots found
2466  *		claimed slot number if successful
2467  *
2468  * WARNING, WARNING: The caller is expected to obtain the siport_mutex
2469  * before calling us.
2470  */
2471 /*ARGSUSED*/
2472 static int
si_claim_free_slot(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port)2473 si_claim_free_slot(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port)
2474 {
2475 	uint32_t free_slots;
2476 	int slot;
2477 
2478 	_NOTE(ASSUMING_PROTECTED(si_portp))
2479 
2480 	SIDBG_P(SIDBG_ENTRY, si_portp,
2481 	    "si_claim_free_slot entry: siport_pending_tags: %x",
2482 	    si_portp->siport_pending_tags);
2483 
2484 	free_slots = (~si_portp->siport_pending_tags) & SI_SLOT_MASK;
2485 	slot = ddi_ffs(free_slots) - 1;
2486 	if (slot == -1) {
2487 		SIDBG_P(SIDBG_VERBOSE, si_portp,
2488 		    "si_claim_free_slot: no empty slots", NULL);
2489 		return (SI_FAILURE);
2490 	}
2491 
2492 	si_portp->siport_pending_tags |= (0x1 << slot);
2493 	SIDBG_P(SIDBG_VERBOSE, si_portp, "si_claim_free_slot: found slot: 0x%x",
2494 	    slot);
2495 	return (slot);
2496 }
2497 
2498 /*
2499  * Builds the PRB for the sata packet and delivers it to controller.
2500  *
2501  * Returns:
2502  *	slot number if we can obtain a slot successfully
2503  *	otherwise, return SI_FAILURE
2504  *
2505  * WARNING, WARNING: The caller is expected to obtain the siport_mutex
2506  * before calling us.
2507  */
2508 static int
si_deliver_satapkt(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port,sata_pkt_t * spkt)2509 si_deliver_satapkt(
2510 	si_ctl_state_t *si_ctlp,
2511 	si_port_state_t *si_portp,
2512 	int port,
2513 	sata_pkt_t *spkt)
2514 {
2515 	int slot;
2516 	si_prb_t *prb;
2517 	sata_cmd_t *cmd;
2518 	si_sge_t *sgep; /* scatter gather entry pointer */
2519 	si_sgt_t *sgtp; /* scatter gather table pointer */
2520 	si_sgblock_t *sgbp; /* scatter gather block pointer */
2521 	int i, j, cookie_index;
2522 	int ncookies;
2523 	int is_atapi = 0;
2524 	ddi_dma_cookie_t cookie;
2525 
2526 	_NOTE(ASSUMING_PROTECTED(si_portp))
2527 
2528 	slot = si_claim_free_slot(si_ctlp, si_portp, port);
2529 	if (slot == SI_FAILURE) {
2530 		return (SI_FAILURE);
2531 	}
2532 
2533 	if (spkt->satapkt_device.satadev_type == SATA_DTYPE_ATAPICD) {
2534 		is_atapi = 1;
2535 	}
2536 
2537 	if ((si_portp->siport_port_type == PORT_TYPE_NODEV) ||
2538 	    !si_portp->siport_active) {
2539 		/*
2540 		 * si_intr_phy_ready_change() may have rendered it to
2541 		 * PORT_TYPE_NODEV. cfgadm operation may have rendered
2542 		 * it inactive.
2543 		 */
2544 		spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
2545 		fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device);
2546 		CLEAR_BIT(si_portp->siport_pending_tags, slot);
2547 
2548 		return (SI_FAILURE);
2549 	}
2550 
2551 
2552 	prb =  &(si_portp->siport_prbpool[slot]);
2553 	bzero((void *)prb, sizeof (si_prb_t));
2554 
2555 	cmd = &spkt->satapkt_cmd;
2556 
2557 	SIDBG_P(SIDBG_ENTRY, si_portp,
2558 	    "si_deliver_satpkt entry: cmd_reg: 0x%x, slot: 0x%x, \
2559 		port: %x, satapkt: %x",
2560 	    cmd->satacmd_cmd_reg, slot, port, (uint32_t)(intptr_t)spkt);
2561 
2562 	/* Now fill the prb. */
2563 	if (is_atapi) {
2564 		if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction ==
2565 		    SATA_DIR_READ) {
2566 			SET_PRB_CONTROL_PKT_READ(prb);
2567 		} else if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction
2568 		    == SATA_DIR_WRITE) {
2569 			SET_PRB_CONTROL_PKT_WRITE(prb);
2570 		}
2571 	}
2572 
2573 	SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D);
2574 	if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) ||
2575 	    (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) {
2576 		SET_FIS_PMP(prb->prb_fis,
2577 		    spkt->satapkt_device.satadev_addr.pmport);
2578 	}
2579 	SET_FIS_CDMDEVCTL(prb->prb_fis, 1);
2580 	SET_FIS_COMMAND(prb->prb_fis, cmd->satacmd_cmd_reg);
2581 	SET_FIS_FEATURES(prb->prb_fis, cmd->satacmd_features_reg);
2582 	SET_FIS_SECTOR_COUNT(prb->prb_fis, cmd->satacmd_sec_count_lsb);
2583 
2584 	switch (cmd->satacmd_addr_type) {
2585 
2586 	case 0:
2587 		/*
2588 		 * satacmd_addr_type will be 0 for the commands below:
2589 		 *	SATAC_PACKET
2590 		 *	SATAC_IDLE_IM
2591 		 *	SATAC_STANDBY_IM
2592 		 *	SATAC_DOWNLOAD_MICROCODE
2593 		 *	SATAC_FLUSH_CACHE
2594 		 *	SATAC_SET_FEATURES
2595 		 *	SATAC_SMART
2596 		 *	SATAC_ID_PACKET_DEVICE
2597 		 *	SATAC_ID_DEVICE
2598 		 *	SATAC_READ_PORTMULT
2599 		 *	SATAC_WRITE_PORTMULT
2600 		 */
2601 		/* FALLTHRU */
2602 
2603 	case ATA_ADDR_LBA:
2604 		/* FALLTHRU */
2605 
2606 	case ATA_ADDR_LBA28:
2607 		/* LBA[7:0] */
2608 		SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb);
2609 
2610 		/* LBA[15:8] */
2611 		SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb);
2612 
2613 		/* LBA[23:16] */
2614 		SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb);
2615 
2616 		/* LBA [27:24] (also called dev_head) */
2617 		SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg);
2618 
2619 		break;
2620 
2621 	case ATA_ADDR_LBA48:
2622 		/* LBA[7:0] */
2623 		SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb);
2624 
2625 		/* LBA[15:8] */
2626 		SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb);
2627 
2628 		/* LBA[23:16] */
2629 		SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb);
2630 
2631 		/* LBA [31:24] */
2632 		SET_FIS_SECTOR_EXP(prb->prb_fis, cmd->satacmd_lba_low_msb);
2633 
2634 		/* LBA [39:32] */
2635 		SET_FIS_CYL_LOW_EXP(prb->prb_fis, cmd->satacmd_lba_mid_msb);
2636 
2637 		/* LBA [47:40] */
2638 		SET_FIS_CYL_HI_EXP(prb->prb_fis, cmd->satacmd_lba_high_msb);
2639 
2640 		/* Set dev_head */
2641 		SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg);
2642 
2643 		/* Set the extended sector count and features */
2644 		SET_FIS_SECTOR_COUNT_EXP(prb->prb_fis,
2645 		    cmd->satacmd_sec_count_msb);
2646 		SET_FIS_FEATURES_EXP(prb->prb_fis,
2647 		    cmd->satacmd_features_reg_ext);
2648 
2649 		break;
2650 
2651 	}
2652 
2653 	if (cmd->satacmd_flags.sata_queued) {
2654 		/*
2655 		 * For queued commands, the TAG for the sector count lsb is
2656 		 * generated from current slot number.
2657 		 */
2658 		SET_FIS_SECTOR_COUNT(prb->prb_fis, slot << 3);
2659 	}
2660 
2661 	if ((cmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) ||
2662 	    (cmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED)) {
2663 		si_portp->siport_pending_ncq_count++;
2664 	}
2665 
2666 	/* *** now fill the scatter gather list ******* */
2667 
2668 	if (is_atapi) { /* It is an ATAPI drive */
2669 		/* atapi command goes into sge0 */
2670 		bcopy(cmd->satacmd_acdb, &prb->prb_sge0, sizeof (si_sge_t));
2671 
2672 		/* Now fill sge1 with pointer to external SGT. */
2673 		if (spkt->satapkt_cmd.satacmd_num_dma_cookies) {
2674 			prb->prb_sge1.sge_addr =
2675 			    si_portp->siport_sgbpool_physaddr +
2676 			    slot * sizeof (si_sgblock_t) * si_dma_sg_number;
2677 			SET_SGE_LNK(prb->prb_sge1);
2678 		} else {
2679 			SET_SGE_TRM(prb->prb_sge1);
2680 		}
2681 	} else {
2682 		/* Fill the sge0 */
2683 		if (spkt->satapkt_cmd.satacmd_num_dma_cookies) {
2684 			prb->prb_sge0.sge_addr =
2685 			    si_portp->siport_sgbpool_physaddr +
2686 			    slot * sizeof (si_sgblock_t) * si_dma_sg_number;
2687 			SET_SGE_LNK(prb->prb_sge0);
2688 
2689 		} else {
2690 			SET_SGE_TRM(prb->prb_sge0);
2691 		}
2692 
2693 		/* sge1 is left empty in non-ATAPI case */
2694 	}
2695 
2696 	bzero(&si_portp->siport_sgbpool[slot * si_dma_sg_number],
2697 	    sizeof (si_sgblock_t) * si_dma_sg_number);
2698 
2699 	ncookies = spkt->satapkt_cmd.satacmd_num_dma_cookies;
2700 	ASSERT(ncookies <= (SGE_LENGTH(si_dma_sg_number)));
2701 
2702 	SIDBG_P(SIDBG_COOKIES, si_portp, "total ncookies: %d", ncookies);
2703 	if (ncookies == 0) {
2704 		sgbp = &si_portp->siport_sgbpool[slot * si_dma_sg_number];
2705 		sgtp = &sgbp->sgb_sgt[0];
2706 		sgep = &sgtp->sgt_sge[0];
2707 
2708 		/* No cookies. Terminate the chain. */
2709 		SIDBG_P(SIDBG_COOKIES, si_portp, "empty cookies: terminating.",
2710 		    NULL);
2711 
2712 		sgep->sge_addr_low = 0;
2713 		sgep->sge_addr_high = 0;
2714 		sgep->sge_data_count = 0;
2715 		SET_SGE_TRM((*sgep));
2716 
2717 		goto sgl_fill_done;
2718 	}
2719 
2720 	for (i = 0, cookie_index = 0,
2721 	    sgbp = &si_portp->siport_sgbpool[slot * si_dma_sg_number];
2722 	    i < si_dma_sg_number; i++) {
2723 
2724 		sgtp = &sgbp->sgb_sgt[0] + i;
2725 
2726 		/* Now fill the first 3 entries of SGT in the loop below. */
2727 		for (j = 0, sgep = &sgtp->sgt_sge[0];
2728 		    ((j < 3) && (cookie_index < ncookies-1));
2729 		    j++, cookie_index++, sgep++)  {
2730 			ASSERT(cookie_index < ncookies);
2731 			SIDBG_P(SIDBG_COOKIES, si_portp,
2732 			    "inner loop: cookie_index: %d, ncookies: %d",
2733 			    cookie_index,
2734 			    ncookies);
2735 			cookie = spkt->satapkt_cmd.
2736 			    satacmd_dma_cookie_list[cookie_index];
2737 
2738 			sgep->sge_addr_low = cookie._dmu._dmac_la[0];
2739 			sgep->sge_addr_high = cookie._dmu._dmac_la[1];
2740 			sgep->sge_data_count = (uint32_t)cookie.dmac_size;
2741 		}
2742 
2743 		/*
2744 		 * If this happens to be the last cookie, we terminate it here.
2745 		 * Otherwise, we link to next SGT.
2746 		 */
2747 
2748 		if (cookie_index == ncookies-1) {
2749 			/* This is the last cookie. Terminate the chain. */
2750 			SIDBG_P(SIDBG_COOKIES, si_portp,
2751 			    "filling the last: cookie_index: %d, "
2752 			    "ncookies: %d",
2753 			    cookie_index,
2754 			    ncookies);
2755 			cookie = spkt->satapkt_cmd.
2756 			    satacmd_dma_cookie_list[cookie_index];
2757 
2758 			sgep->sge_addr_low = cookie._dmu._dmac_la[0];
2759 			sgep->sge_addr_high = cookie._dmu._dmac_la[1];
2760 			sgep->sge_data_count = (uint32_t)cookie.dmac_size;
2761 			SET_SGE_TRM((*sgep));
2762 
2763 			break; /* we break the loop */
2764 
2765 		} else {
2766 			/* This is not the last one. So link it. */
2767 			SIDBG_P(SIDBG_COOKIES, si_portp,
2768 			    "linking SGT: cookie_index: %d, ncookies: %d",
2769 			    cookie_index,
2770 			    ncookies);
2771 			sgep->sge_addr = si_portp->siport_sgbpool_physaddr +
2772 			    slot * sizeof (si_sgblock_t) * si_dma_sg_number +
2773 			    (i+1) * sizeof (si_sgt_t);
2774 
2775 			SET_SGE_LNK((*sgep));
2776 		}
2777 
2778 	}
2779 
2780 	/* *** finished filling the scatter gather list ******* */
2781 
2782 sgl_fill_done:
2783 	/* Now remember the sata packet in siport_slot_pkts[]. */
2784 	si_portp->siport_slot_pkts[slot] = spkt;
2785 
2786 	/*
2787 	 * We are overloading satapkt_hba_driver_private with
2788 	 * watched_cycle count.
2789 	 */
2790 	spkt->satapkt_hba_driver_private = (void *)(intptr_t)0;
2791 
2792 	if (is_atapi) {
2793 		/* program the packet_lenth if it is atapi device. */
2794 
2795 
2796 #ifdef ATAPI_2nd_PHASE
2797 		/*
2798 		 * Framework needs to calculate the acdb_len based on
2799 		 * identify packet data. This needs to be accomplished
2800 		 * in second phase of the project.
2801 		 */
2802 		ASSERT((cmd->satacmd_acdb_len == 12) ||
2803 		    (cmd->satacmd_acdb_len == 16));
2804 		SIDBG_P(SIDBG_VERBOSE, si_portp, "deliver: acdb_len: %d",
2805 		    cmd->satacmd_acdb_len);
2806 
2807 		if (cmd->satacmd_acdb_len == 16) {
2808 			ddi_put32(si_ctlp->sictl_port_acc_handle,
2809 			    (uint32_t *)PORT_CONTROL_SET(si_ctlp, port),
2810 			    PORT_CONTROL_SET_BITS_PACKET_LEN);
2811 		} else {
2812 			ddi_put32(si_ctlp->sictl_port_acc_handle,
2813 			    (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port),
2814 			    PORT_CONTROL_CLEAR_BITS_PACKET_LEN);
2815 		}
2816 
2817 #else /* ATAPI_2nd_PHASE */
2818 		/* hard coding for now to 12 bytes */
2819 		ddi_put32(si_ctlp->sictl_port_acc_handle,
2820 		    (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port),
2821 		    PORT_CONTROL_CLEAR_BITS_PACKET_LEN);
2822 #endif /* ATAPI_2nd_PHASE */
2823 	}
2824 
2825 
2826 #if SI_DEBUG
2827 	if (si_debug_flags & SIDBG_DUMP_PRB) {
2828 		if (!(is_atapi && (prb->prb_sge0.sge_addr_low == 0))) {
2829 			/*
2830 			 * Do not dump the atapi Test-Unit-Ready commands.
2831 			 * The sd_media_watch spews too many of these.
2832 			 */
2833 			int *ptr;
2834 			si_sge_t *tmpsgep;
2835 			int j;
2836 
2837 			ptr = (int *)(void *)prb;
2838 			cmn_err(CE_WARN, "si_deliver_satpkt prb: ");
2839 			for (j = 0; j < (sizeof (si_prb_t)/4); j++) {
2840 				cmn_err(CE_WARN, "%x ", ptr[j]);
2841 			}
2842 
2843 			cmn_err(CE_WARN,
2844 			    "si_deliver_satpkt sgt: low, high, count link");
2845 			for (j = 0,
2846 			    tmpsgep = (si_sge_t *)
2847 			    &si_portp->siport_sgbpool[slot * si_dma_sg_number];
2848 			    j < (sizeof (si_sgblock_t)/ sizeof (si_sge_t))
2849 			    *si_dma_sg_number;
2850 			    j++, tmpsgep++) {
2851 				ptr = (int *)(void *)tmpsgep;
2852 				cmn_err(CE_WARN, "%x %x %x %x",
2853 				    ptr[0],
2854 				    ptr[1],
2855 				    ptr[2],
2856 				    ptr[3]);
2857 				if (IS_SGE_TRM_SET((*tmpsgep))) {
2858 					break;
2859 				}
2860 
2861 			}
2862 		}
2863 
2864 	}
2865 #endif  /* SI_DEBUG */
2866 
2867 	/* Deliver PRB */
2868 	POST_PRB_ADDR(si_ctlp, si_portp, port, slot);
2869 
2870 	return (slot);
2871 }
2872 
2873 /*
2874  * Initialize the controller and set up driver data structures.
2875  *
2876  * This routine can be called from three separate cases: DDI_ATTACH, PM_LEVEL_D0
2877  * and DDI_RESUME. The DDI_ATTACH case is different from other two cases; the
2878  * memory allocation & device signature probing are attempted only during
2879  * DDI_ATTACH case. In the case of PM_LEVEL_D0 & DDI_RESUME, we are starting
2880  * from a previously initialized state; so there is no need to allocate memory
2881  * or to attempt probing the device signatures.
2882  */
2883 static int
si_initialize_controller(si_ctl_state_t * si_ctlp)2884 si_initialize_controller(si_ctl_state_t *si_ctlp)
2885 {
2886 	uint32_t port_status;
2887 	uint32_t SStatus;
2888 	uint32_t SControl;
2889 	uint8_t port;
2890 	int loop_count = 0;
2891 	si_port_state_t *si_portp;
2892 
2893 	SIDBG_C(SIDBG_INIT, si_ctlp,
2894 	    "si3124: si_initialize_controller entered", NULL);
2895 
2896 	mutex_enter(&si_ctlp->sictl_mutex);
2897 
2898 	/* Remove the Global Reset. */
2899 	ddi_put32(si_ctlp->sictl_global_acc_handle,
2900 	    (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp),
2901 	    GLOBAL_CONTROL_REG_BITS_CLEAR);
2902 
2903 	for (port = 0; port < si_ctlp->sictl_num_ports; port++) {
2904 
2905 		if (si_ctlp->sictl_flags & SI_ATTACH) {
2906 			/*
2907 			 * We allocate the port state only during attach
2908 			 * sequence. We don't want to do it during
2909 			 * suspend/resume sequence.
2910 			 */
2911 			if (si_alloc_port_state(si_ctlp, port)) {
2912 				mutex_exit(&si_ctlp->sictl_mutex);
2913 				return (SI_FAILURE);
2914 			}
2915 		}
2916 
2917 		si_portp = si_ctlp->sictl_ports[port];
2918 		mutex_enter(&si_portp->siport_mutex);
2919 		si_portp->siport_ctlp = si_ctlp;
2920 		si_portp->siport_port_num = port;
2921 
2922 		/* Clear Port Reset. */
2923 		ddi_put32(si_ctlp->sictl_port_acc_handle,
2924 		    (uint32_t *)PORT_CONTROL_SET(si_ctlp, port),
2925 		    PORT_CONTROL_SET_BITS_PORT_RESET);
2926 		ddi_put32(si_ctlp->sictl_port_acc_handle,
2927 		    (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port),
2928 		    PORT_CONTROL_CLEAR_BITS_PORT_RESET);
2929 
2930 		/*
2931 		 * Arm the interrupts for: Cmd completion, Cmd error,
2932 		 * Port Ready, PM Change, PhyRdyChange, Commwake,
2933 		 * UnrecFIS, Devxchanged, SDBNotify.
2934 		 */
2935 		ddi_put32(si_ctlp->sictl_port_acc_handle,
2936 		    (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port),
2937 		    (INTR_COMMAND_COMPLETE |
2938 		    INTR_COMMAND_ERROR |
2939 		    INTR_PORT_READY |
2940 		    INTR_POWER_CHANGE |
2941 		    INTR_PHYRDY_CHANGE |
2942 		    INTR_COMWAKE_RECEIVED |
2943 		    INTR_UNRECOG_FIS |
2944 		    INTR_DEV_XCHANGED |
2945 		    INTR_SETDEVBITS_NOTIFY));
2946 
2947 		/* Now enable the interrupts. */
2948 		si_enable_port_interrupts(si_ctlp, port);
2949 
2950 		/*
2951 		 * The following PHY initialization is redundant in
2952 		 * in x86 since the BIOS anyway does this as part of
2953 		 * device enumeration during the power up. But this
2954 		 * is a required step in sparc since there is no BIOS.
2955 		 *
2956 		 * The way to initialize the PHY is to write a 1 and then
2957 		 * a 0 to DET field of SControl register.
2958 		 */
2959 
2960 		/*
2961 		 * Fetch the current SControl before writing the
2962 		 * DET part with 1
2963 		 */
2964 		SControl = ddi_get32(si_ctlp->sictl_port_acc_handle,
2965 		    (uint32_t *)PORT_SCONTROL(si_ctlp, port));
2966 		SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET);
2967 		ddi_put32(si_ctlp->sictl_port_acc_handle,
2968 		    (uint32_t *)(PORT_SCONTROL(si_ctlp, port)),
2969 		    SControl);
2970 #ifndef __lock_lint
2971 		delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */
2972 #endif /* __lock_lint */
2973 
2974 		/*
2975 		 * Now fetch the SControl again and rewrite the
2976 		 * DET part with 0
2977 		 */
2978 		SControl = ddi_get32(si_ctlp->sictl_port_acc_handle,
2979 		    (uint32_t *)PORT_SCONTROL(si_ctlp, port));
2980 		SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION);
2981 		ddi_put32(si_ctlp->sictl_port_acc_handle,
2982 		    (uint32_t *)(PORT_SCONTROL(si_ctlp, port)),
2983 		    SControl);
2984 
2985 		/*
2986 		 * PHY may be initialized by now. Check the DET field of
2987 		 * SStatus to determine if there is a device present.
2988 		 *
2989 		 * The DET field is valid only if IPM field indicates that
2990 		 * the interface is in active state.
2991 		 */
2992 
2993 		loop_count = 0;
2994 		do {
2995 			SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle,
2996 			    (uint32_t *)PORT_SSTATUS(si_ctlp, port));
2997 
2998 			if (SSTATUS_GET_IPM(SStatus) !=
2999 			    SSTATUS_IPM_INTERFACE_ACTIVE) {
3000 				/*
3001 				 * If the interface is not active, the DET field
3002 				 * is considered not accurate. So we want to
3003 				 * continue looping.
3004 				 */
3005 				SSTATUS_SET_DET(SStatus,
3006 				    SSTATUS_DET_NODEV_NOPHY);
3007 			}
3008 
3009 			if (loop_count++ > SI_POLLRATE_SSTATUS) {
3010 				/*
3011 				 * We are effectively timing out after 0.1 sec.
3012 				 */
3013 				break;
3014 			}
3015 
3016 			/* Wait for 10 millisec */
3017 #ifndef __lock_lint
3018 			delay(SI_10MS_TICKS);
3019 #endif /* __lock_lint */
3020 
3021 		} while (SSTATUS_GET_DET(SStatus) !=
3022 		    SSTATUS_DET_DEVPRESENT_PHYONLINE);
3023 
3024 		SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3025 		    "si_initialize_controller: 1st loop count: %d, "
3026 		    "SStatus: 0x%x",
3027 		    loop_count,
3028 		    SStatus);
3029 
3030 		if ((SSTATUS_GET_IPM(SStatus) !=
3031 		    SSTATUS_IPM_INTERFACE_ACTIVE) ||
3032 		    (SSTATUS_GET_DET(SStatus) !=
3033 		    SSTATUS_DET_DEVPRESENT_PHYONLINE)) {
3034 			/*
3035 			 * Either the port is not active or there
3036 			 * is no device present.
3037 			 */
3038 			si_ctlp->sictl_ports[port]->siport_port_type =
3039 			    PORT_TYPE_NODEV;
3040 			mutex_exit(&si_portp->siport_mutex);
3041 			continue;
3042 		}
3043 
3044 		/* Wait until Port Ready */
3045 		loop_count = 0;
3046 		do {
3047 			port_status = ddi_get32(si_ctlp->sictl_port_acc_handle,
3048 			    (uint32_t *)PORT_STATUS(si_ctlp, port));
3049 
3050 			if (loop_count++ > SI_POLLRATE_PORTREADY) {
3051 				/*
3052 				 * We are effectively timing out after 0.5 sec.
3053 				 */
3054 				break;
3055 			}
3056 
3057 			/* Wait for 10 millisec */
3058 #ifndef __lock_lint
3059 			delay(SI_10MS_TICKS);
3060 #endif /* __lock_lint */
3061 
3062 		} while (!(port_status & PORT_STATUS_BITS_PORT_READY));
3063 
3064 		SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3065 		    "si_initialize_controller: 2nd loop count: %d",
3066 		    loop_count);
3067 
3068 		if (si_ctlp->sictl_flags & SI_ATTACH) {
3069 			/*
3070 			 * We want to probe for dev signature only during attach
3071 			 * case. Don't do it during suspend/resume sequence.
3072 			 */
3073 			if (port_status & PORT_STATUS_BITS_PORT_READY) {
3074 				mutex_exit(&si_portp->siport_mutex);
3075 				si_find_dev_signature(si_ctlp, si_portp, port,
3076 				    PORTMULT_CONTROL_PORT);
3077 				mutex_enter(&si_portp->siport_mutex);
3078 			} else {
3079 				si_ctlp->sictl_ports[port]->siport_port_type =
3080 				    PORT_TYPE_NODEV;
3081 			}
3082 		}
3083 
3084 		if (si_check_ctl_handles(si_ctlp) != DDI_SUCCESS ||
3085 		    si_check_port_handles(si_portp) != DDI_SUCCESS) {
3086 			ddi_fm_service_impact(si_ctlp->sictl_devinfop,
3087 			    DDI_SERVICE_LOST);
3088 			mutex_exit(&si_portp->siport_mutex);
3089 			mutex_exit(&si_ctlp->sictl_mutex);
3090 			return (SI_FAILURE);
3091 		}
3092 
3093 		mutex_exit(&si_portp->siport_mutex);
3094 	}
3095 
3096 	mutex_exit(&si_ctlp->sictl_mutex);
3097 	return (SI_SUCCESS);
3098 }
3099 
3100 /*
3101  * Reverse of si_initialize_controller().
3102  *
3103  * WARNING, WARNING: The caller is expected to obtain the sictl_mutex
3104  * before calling us.
3105  */
3106 static void
si_deinitialize_controller(si_ctl_state_t * si_ctlp)3107 si_deinitialize_controller(si_ctl_state_t *si_ctlp)
3108 {
3109 	int port;
3110 
3111 	_NOTE(ASSUMING_PROTECTED(si_ctlp))
3112 
3113 	SIDBG_C(SIDBG_INIT, si_ctlp,
3114 	    "si3124: si_deinitialize_controller entered", NULL);
3115 
3116 	/* disable all the interrupts. */
3117 	si_disable_all_interrupts(si_ctlp);
3118 
3119 	if (si_ctlp->sictl_flags & SI_DETACH) {
3120 		/*
3121 		 * We want to dealloc all the memory in detach case.
3122 		 */
3123 		for (port = 0; port < si_ctlp->sictl_num_ports; port++) {
3124 			si_dealloc_port_state(si_ctlp, port);
3125 		}
3126 	}
3127 
3128 }
3129 
3130 /*
3131  * Prepare the port ready for usage.
3132  *
3133  * WARNING, WARNING: The caller is expected to obtain the siport_mutex
3134  * before calling us.
3135  */
3136 static void
si_init_port(si_ctl_state_t * si_ctlp,int port)3137 si_init_port(si_ctl_state_t *si_ctlp, int port)
3138 {
3139 
3140 	SIDBG_C(SIDBG_INIT, si_ctlp,
3141 	    "si_init_port entered: port: 0x%x",
3142 	    port);
3143 
3144 	/* Initialize the port. */
3145 	ddi_put32(si_ctlp->sictl_port_acc_handle,
3146 	    (uint32_t *)PORT_CONTROL_SET(si_ctlp, port),
3147 	    PORT_CONTROL_SET_BITS_PORT_INITIALIZE);
3148 
3149 	/*
3150 	 * Clear the InterruptNCOR (Interrupt No Clear on Read).
3151 	 * This step ensures that a mere reading of slot_status will clear
3152 	 * the interrupt; no explicit clearing of interrupt condition
3153 	 * will be needed for successful completion of commands.
3154 	 */
3155 	ddi_put32(si_ctlp->sictl_port_acc_handle,
3156 	    (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port),
3157 	    PORT_CONTROL_CLEAR_BITS_INTR_NCoR);
3158 
3159 	/* clear any pending interrupts at this point */
3160 	ddi_put32(si_ctlp->sictl_port_acc_handle,
3161 	    (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)),
3162 	    INTR_MASK);
3163 
3164 }
3165 
3166 
3167 /*
3168  * Enumerate the devices connected to the port multiplier.
3169  * Once a device is detected, we call si_find_dev_signature()
3170  * to find the type of device connected. Even though we are
3171  * called from within si_find_dev_signature(), there is no
3172  * recursion possible.
3173  */
3174 static int
si_enumerate_port_multiplier(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port)3175 si_enumerate_port_multiplier(
3176 	si_ctl_state_t *si_ctlp,
3177 	si_port_state_t *si_portp,
3178 	int port)
3179 {
3180 	uint32_t num_dev_ports = 0;
3181 	int pmport;
3182 	uint32_t SControl = 0;
3183 	uint32_t SStatus = 0;
3184 	uint32_t SError = 0;
3185 	int loop_count = 0;
3186 
3187 	SIDBG_P(SIDBG_INIT, si_portp,
3188 	    "si_enumerate_port_multiplier entered: port: %d",
3189 	    port);
3190 
3191 	mutex_enter(&si_portp->siport_mutex);
3192 
3193 	/* Enable Port Multiplier context switching. */
3194 	ddi_put32(si_ctlp->sictl_port_acc_handle,
3195 	    (uint32_t *)PORT_CONTROL_SET(si_ctlp, port),
3196 	    PORT_CONTROL_SET_BITS_PM_ENABLE);
3197 
3198 	/*
3199 	 * Read the num dev ports connected.
3200 	 * GSCR[2] contains the number of device ports.
3201 	 */
3202 	if (si_read_portmult_reg(si_ctlp, si_portp, port, PORTMULT_CONTROL_PORT,
3203 	    PSCR_REG2, &num_dev_ports)) {
3204 		mutex_exit(&si_portp->siport_mutex);
3205 		return (SI_FAILURE);
3206 	}
3207 	si_portp->siport_portmult_state.sipm_num_ports = num_dev_ports;
3208 
3209 	SIDBG_P(SIDBG_INIT, si_portp,
3210 	    "si_enumerate_port_multiplier: ports found: %d",
3211 	    num_dev_ports);
3212 
3213 	for (pmport = 0; pmport < num_dev_ports-1; pmport++) {
3214 		/*
3215 		 * Enable PHY by writing a 1, then a 0 to SControl
3216 		 * (i.e. PSCR[2]) DET field.
3217 		 */
3218 		if (si_read_portmult_reg(si_ctlp, si_portp, port, pmport,
3219 		    PSCR_REG2, &SControl)) {
3220 			continue;
3221 		}
3222 
3223 		/* First write a 1 to DET field of SControl. */
3224 		SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET);
3225 		if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport,
3226 		    PSCR_REG2, SControl)) {
3227 			continue;
3228 		}
3229 #ifndef __lock_lint
3230 		delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */
3231 #endif /* __lock_lint */
3232 
3233 		/* Then write a 0 to the DET field of SControl. */
3234 		SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION);
3235 		if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport,
3236 		    PSCR_REG2, SControl)) {
3237 			continue;
3238 		}
3239 
3240 		/* Wait for PHYRDY by polling SStatus (i.e. PSCR[0]). */
3241 		loop_count = 0;
3242 		do {
3243 			if (si_read_portmult_reg(si_ctlp, si_portp, port,
3244 			    pmport, PSCR_REG0, &SStatus)) {
3245 				break;
3246 			}
3247 			SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3248 			    "looping for PHYRDY: SStatus: %x",
3249 			    SStatus);
3250 
3251 			if (SSTATUS_GET_IPM(SStatus) !=
3252 			    SSTATUS_IPM_INTERFACE_ACTIVE) {
3253 				/*
3254 				 * If the interface is not active, the DET field
3255 				 * is considered not accurate. So we want to
3256 				 * continue looping.
3257 				 */
3258 				SSTATUS_SET_DET(SStatus,
3259 				    SSTATUS_DET_NODEV_NOPHY);
3260 			}
3261 
3262 			if (loop_count++ > SI_POLLRATE_SSTATUS) {
3263 				/*
3264 				 * We are effectively timing out after 0.1 sec.
3265 				 */
3266 				break;
3267 			}
3268 
3269 			/* Wait for 10 millisec */
3270 #ifndef __lock_lint
3271 			delay(SI_10MS_TICKS);
3272 #endif /* __lock_lint */
3273 
3274 		} while (SSTATUS_GET_DET(SStatus) !=
3275 		    SSTATUS_DET_DEVPRESENT_PHYONLINE);
3276 
3277 		SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3278 		    "si_enumerate_port_multiplier: "
3279 		    "loop count: %d, SStatus: 0x%x",
3280 		    loop_count,
3281 		    SStatus);
3282 
3283 		if ((SSTATUS_GET_IPM(SStatus) ==
3284 		    SSTATUS_IPM_INTERFACE_ACTIVE) &&
3285 		    (SSTATUS_GET_DET(SStatus) ==
3286 		    SSTATUS_DET_DEVPRESENT_PHYONLINE)) {
3287 			/* The interface is active and the device is present */
3288 			SIDBG_P(SIDBG_INIT, si_portp,
3289 			    "Status: %x, device exists",
3290 			    SStatus);
3291 			/*
3292 			 * Clear error bits in SError register (i.e. PSCR[1]
3293 			 * by writing back error bits.
3294 			 */
3295 			if (si_read_portmult_reg(si_ctlp, si_portp, port,
3296 			    pmport, PSCR_REG1, &SError)) {
3297 				continue;
3298 			}
3299 			SIDBG_P(SIDBG_INIT, si_portp,
3300 			    "SError bits are: %x", SError);
3301 			if (si_write_portmult_reg(si_ctlp, si_portp, port,
3302 			    pmport, PSCR_REG1, SError)) {
3303 				continue;
3304 			}
3305 
3306 			/* There exists a device. */
3307 			mutex_exit(&si_portp->siport_mutex);
3308 			si_find_dev_signature(si_ctlp, si_portp, port, pmport);
3309 			mutex_enter(&si_portp->siport_mutex);
3310 		}
3311 	}
3312 
3313 	mutex_exit(&si_portp->siport_mutex);
3314 
3315 	return (SI_SUCCESS);
3316 }
3317 
3318 
3319 /*
3320  * Read a port multiplier register.
3321  *
3322  * WARNING, WARNING: The caller is expected to obtain the siport_mutex
3323  * before calling us.
3324  */
3325 static int
si_read_portmult_reg(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port,int pmport,int regnum,uint32_t * regval)3326 si_read_portmult_reg(
3327 	si_ctl_state_t *si_ctlp,
3328 	si_port_state_t *si_portp,
3329 	int port,
3330 	int pmport,
3331 	int regnum,
3332 	uint32_t *regval)
3333 {
3334 	int slot;
3335 	si_prb_t *prb;
3336 	uint32_t *prb_word_ptr;
3337 	int i;
3338 	uint32_t slot_status;
3339 	int loop_count = 0;
3340 
3341 	_NOTE(ASSUMING_PROTECTED(si_portp))
3342 
3343 	SIDBG_P(SIDBG_ENTRY, si_portp, "si_read_portmult_reg: port: %x,"
3344 	    "pmport: %x, regnum: %x",
3345 	    port, pmport, regnum);
3346 
3347 	slot = si_claim_free_slot(si_ctlp, si_portp, port);
3348 	if (slot == SI_FAILURE) {
3349 		return (SI_FAILURE);
3350 	}
3351 
3352 	prb =  &(si_portp->siport_prbpool[slot]);
3353 	bzero((void *)prb, sizeof (si_prb_t));
3354 
3355 	/* Now fill the prb. */
3356 	SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D);
3357 	SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT);
3358 	SET_FIS_CDMDEVCTL(prb->prb_fis, 1);
3359 	SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_PM_REG);
3360 
3361 	SET_FIS_DEV_HEAD(prb->prb_fis, pmport);
3362 	SET_FIS_FEATURES(prb->prb_fis, regnum);
3363 
3364 	/* no real data transfer is involved. */
3365 	SET_SGE_TRM(prb->prb_sge0);
3366 
3367 #if SI_DEBUG
3368 	if (si_debug_flags & SIDBG_DUMP_PRB) {
3369 		int *ptr;
3370 		int j;
3371 
3372 		ptr = (int *)(void *)prb;
3373 		cmn_err(CE_WARN, "read_port_mult_reg, prb: ");
3374 		for (j = 0; j < (sizeof (si_prb_t)/4); j++) {
3375 			cmn_err(CE_WARN, "%x ", ptr[j]);
3376 		}
3377 
3378 	}
3379 #endif /* SI_DEBUG */
3380 
3381 	/* Deliver PRB */
3382 	POST_PRB_ADDR(si_ctlp, si_portp, port, slot);
3383 
3384 	/* Loop till the command is finished. */
3385 	do {
3386 		slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle,
3387 		    (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port)));
3388 
3389 		SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3390 		    "looping read_pm slot_status: 0x%x",
3391 		    slot_status);
3392 
3393 		if (loop_count++ > SI_POLLRATE_SLOTSTATUS) {
3394 			/* We are effectively timing out after 0.5 sec. */
3395 			break;
3396 		}
3397 
3398 		/* Wait for 10 millisec */
3399 #ifndef __lock_lint
3400 		delay(SI_10MS_TICKS);
3401 #endif /* __lock_lint */
3402 
3403 	} while (slot_status & SI_SLOT_MASK & (0x1 << slot));
3404 
3405 	SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3406 	    "read_portmult_reg: loop count: %d",
3407 	    loop_count);
3408 
3409 	CLEAR_BIT(si_portp->siport_pending_tags, slot);
3410 
3411 	/* Now inspect the port LRAM for the modified FIS. */
3412 	prb_word_ptr = (uint32_t *)(void *)prb;
3413 	for (i = 0; i < (sizeof (si_prb_t)/4); i++) {
3414 		prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle,
3415 		    (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4));
3416 	}
3417 
3418 	if (si_check_ctl_handles(si_ctlp) != DDI_SUCCESS ||
3419 	    si_check_port_handles(si_portp) != DDI_SUCCESS) {
3420 		ddi_fm_service_impact(si_ctlp->sictl_devinfop,
3421 		    DDI_SERVICE_UNAFFECTED);
3422 		return (SI_FAILURE);
3423 	}
3424 
3425 	if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) ||
3426 	    (GET_FIS_FEATURES(prb->prb_fis) != 0)) {
3427 		/* command failed. */
3428 		return (SI_FAILURE);
3429 	}
3430 
3431 	/* command succeeded. */
3432 	*regval = (GET_FIS_SECTOR_COUNT(prb->prb_fis) & 0xff) |
3433 	    ((GET_FIS_SECTOR(prb->prb_fis) << 8)  & 0xff00) |
3434 	    ((GET_FIS_CYL_LOW(prb->prb_fis) << 16)  & 0xff0000) |
3435 	    ((GET_FIS_CYL_HI(prb->prb_fis) << 24)  & 0xff000000);
3436 
3437 	return (SI_SUCCESS);
3438 }
3439 
3440 /*
3441  * Write a port multiplier register.
3442  *
3443  * WARNING, WARNING: The caller is expected to obtain the siport_mutex
3444  * before calling us.
3445  */
3446 static int
si_write_portmult_reg(si_ctl_state_t * si_ctlp,si_port_state_t * si_portp,int port,int pmport,int regnum,uint32_t regval)3447 si_write_portmult_reg(
3448 	si_ctl_state_t *si_ctlp,
3449 	si_port_state_t *si_portp,
3450 	int port,
3451 	int pmport,
3452 	int regnum,
3453 	uint32_t regval)
3454 {
3455 	int slot;
3456 	si_prb_t *prb;
3457 	uint32_t *prb_word_ptr;
3458 	uint32_t slot_status;
3459 	int i;
3460 	int loop_count = 0;
3461 
3462 	_NOTE(ASSUMING_PROTECTED(si_portp))
3463 
3464 	SIDBG_P(SIDBG_ENTRY, si_portp,
3465 	    "si_write_portmult_reg: port: %x, pmport: %x,"
3466 	    "regnum: %x, regval: %x",
3467 	    port, pmport, regnum, regval);
3468 
3469 	slot = si_claim_free_slot(si_ctlp, si_portp, port);
3470 	if (slot == SI_FAILURE) {
3471 		return (SI_FAILURE);
3472 	}
3473 
3474 	prb =  &(si_portp->siport_prbpool[slot]);
3475 	bzero((void *)prb, sizeof (si_prb_t));
3476 
3477 	/* Now fill the prb. */
3478 	SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D);
3479 	SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT);
3480 	SET_FIS_CDMDEVCTL(prb->prb_fis, 1);
3481 
3482 	SET_FIS_COMMAND(prb->prb_fis, SATAC_WRITE_PM_REG);
3483 	SET_FIS_DEV_HEAD(prb->prb_fis, pmport);
3484 	SET_FIS_FEATURES(prb->prb_fis, regnum);
3485 
3486 	SET_FIS_SECTOR_COUNT(prb->prb_fis, regval & 0xff);
3487 	SET_FIS_SECTOR(prb->prb_fis, (regval >> 8) & 0xff);
3488 	SET_FIS_CYL_LOW(prb->prb_fis, (regval >> 16) & 0xff);
3489 	SET_FIS_CYL_HI(prb->prb_fis, (regval >> 24)  & 0xff);
3490 
3491 	/* no real data transfer is involved. */
3492 	SET_SGE_TRM(prb->prb_sge0);
3493 
3494 #if SI_DEBUG
3495 	if (si_debug_flags & SIDBG_DUMP_PRB) {
3496 		int *ptr;
3497 		int j;
3498 
3499 		ptr = (int *)(void *)prb;
3500 		cmn_err(CE_WARN, "read_port_mult_reg, prb: ");
3501 		for (j = 0; j < (sizeof (si_prb_t)/4); j++) {
3502 			cmn_err(CE_WARN, "%x ", ptr[j]);
3503 		}
3504 
3505 	}
3506 #endif /* SI_DEBUG */
3507 
3508 	/* Deliver PRB */
3509 	POST_PRB_ADDR(si_ctlp, si_portp, port, slot);
3510 
3511 	/* Loop till the command is finished. */
3512 	do {
3513 		slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle,
3514 		    (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port)));
3515 
3516 		SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3517 		    "looping write_pmp slot_status: 0x%x",
3518 		    slot_status);
3519 
3520 		if (loop_count++ > SI_POLLRATE_SLOTSTATUS) {
3521 			/* We are effectively timing out after 0.5 sec. */
3522 			break;
3523 		}
3524 
3525 		/* Wait for 10 millisec */
3526 #ifndef __lock_lint
3527 		delay(SI_10MS_TICKS);
3528 #endif /* __lock_lint */
3529 
3530 	} while (slot_status & SI_SLOT_MASK & (0x1 << slot));
3531 
3532 	SIDBG_P(SIDBG_POLL_LOOP, si_portp,
3533 	    "write_portmult_reg: loop count: %d",
3534 	    loop_count);
3535 
3536 	CLEAR_BIT(si_portp->siport_pending_tags, slot);
3537 
3538 	/* Now inspect the port LRAM for the modified FIS. */
3539 	prb_word_ptr = (uint32_t *)(void *)prb;
3540 	for (i = 0; i < (sizeof (si_prb_t)/4); i++) {
3541 		prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle,
3542 		    (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4));
3543 	}
3544 
3545 	if (si_check_ctl_handles(si_ctlp) != DDI_SUCCESS ||
3546 	    si_check_port_handles(si_portp) != DDI_SUCCESS) {
3547 		ddi_fm_service_impact(si_ctlp->sictl_devinfop,
3548 		    DDI_SERVICE_UNAFFECTED);
3549 		return (SI_FAILURE);
3550 	}
3551 
3552 	if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) ||
3553 	    (GET_FIS_FEATURES(prb->prb_fis) != 0)) {
3554 		/* command failed */
3555 		return (SI_FAILURE);
3556 	}
3557 
3558 	/* command succeeded */
3559 	return (SI_SUCCESS);
3560 }
3561 
3562 
3563 /*
3564  * Set the auto sense data for ATAPI devices.
3565  *
3566  * Note: Currently the sense data is simulated; this code will be enhanced
3567  * in second phase to fetch the real sense data from the atapi device.
3568  */
3569 static void
si_set_sense_data(sata_pkt_t * satapkt,int reason)3570 si_set_sense_data(sata_pkt_t *satapkt, int reason)
3571 {
3572 	struct scsi_extended_sense *sense;
3573 
3574 	sense = (struct scsi_extended_sense *)
3575 	    satapkt->satapkt_cmd.satacmd_rqsense;
3576 	bzero(sense, sizeof (struct scsi_extended_sense));
3577 	sense->es_valid = 1;		/* Valid sense */
3578 	sense->es_class = 7;		/* Response code 0x70 - current err */
3579 	sense->es_key = 0;
3580 	sense->es_info_1 = 0;
3581 	sense->es_info_2 = 0;
3582 	sense->es_info_3 = 0;
3583 	sense->es_info_4 = 0;
3584 	sense->es_add_len = 6;		/* Additional length */
3585 	sense->es_cmd_info[0] = 0;
3586 	sense->es_cmd_info[1] = 0;
3587 	sense->es_cmd_info[2] = 0;
3588 	sense->es_cmd_info[3] = 0;
3589 	sense->es_add_code = 0;
3590 	sense->es_qual_code = 0;
3591 
3592 	if ((reason == SATA_PKT_DEV_ERROR) || (reason == SATA_PKT_TIMEOUT)) {
3593 		sense->es_key = KEY_HARDWARE_ERROR;
3594 	}
3595 }
3596 
3597 
3598 /*
3599  * Interrupt service handler. We loop through each of the ports to find
3600  * if the interrupt belongs to any of them.
3601  *
3602  * Bulk of the interrupt handling is actually done out of subroutines
3603  * like si_intr_command_complete() etc.
3604  */
3605 /*ARGSUSED*/
3606 static uint_t
si_intr(caddr_t arg1,caddr_t arg2)3607 si_intr(caddr_t arg1, caddr_t arg2)
3608 {
3609 	si_ctl_state_t *si_ctlp = (si_ctl_state_t *)(void *)arg1;
3610 	si_port_state_t *si_portp;
3611 	uint32_t global_intr_status;
3612 	uint32_t mask, port_intr_status;
3613 	int port;
3614 
3615 	global_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle,
3616 	    (uint32_t *)GLOBAL_INTERRUPT_STATUS(si_ctlp));
3617 
3618 	SIDBG_C(SIDBG_INTR, si_ctlp,
3619 	    "si_intr: global_int_status: 0x%x",
3620 	    global_intr_status);
3621 
3622 	if (si_check_acc_handle(si_ctlp->sictl_global_acc_handle) !=
3623 	    DDI_SUCCESS) {
3624 		ddi_fm_service_impact(si_ctlp->sictl_devinfop,
3625 		    DDI_SERVICE_UNAFFECTED);
3626 		return (DDI_INTR_UNCLAIMED);
3627 	}
3628 
3629 	if (!(global_intr_status & SI31xx_INTR_PORT_MASK)) {
3630 		/* Sorry, the interrupt is not ours. */
3631 		return (DDI_INTR_UNCLAIMED);
3632 	}
3633 
3634 	/* Loop for all the ports. */
3635 	for (port = 0; port < si_ctlp->sictl_num_ports; port++) {
3636 
3637 		mask = 0x1 << port;
3638 		if (!(global_intr_status & mask)) {
3639 			continue;
3640 		}
3641 
3642 		mutex_enter(&si_ctlp->sictl_mutex);
3643 		si_portp = si_ctlp->sictl_ports[port];
3644 		mutex_exit(&si_ctlp->sictl_mutex);
3645 
3646 		port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle,
3647 		    (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port));
3648 
3649 		SIDBG_P(SIDBG_VERBOSE, si_portp,
3650 		    "s_intr: port_intr_status: 0x%x, port: %x",
3651 		    port_intr_status,
3652 		    port);
3653 
3654 		if (port_intr_status & INTR_COMMAND_COMPLETE) {
3655 			(void) si_intr_command_complete(si_ctlp, si_portp,
3656 			    port);
3657 
3658 			mutex_enter(&si_portp->siport_mutex);
3659 			if (si_check_ctl_handles(si_ctlp) != DDI_SUCCESS ||
3660 			    si_check_port_handles(si_portp) != DDI_SUCCESS) {
3661 				ddi_fm_service_impact(si_ctlp->sictl_devinfop,
3662 				    DDI_SERVICE_UNAFFECTED);
3663 				si_schedule_port_initialize(si_ctlp, si_portp,
3664 				    port);
3665 			}
3666 			mutex_exit(&si_portp->siport_mutex);
3667 		} else {
3668 			/* Clear the interrupts */
3669 			ddi_put32(si_ctlp->sictl_port_acc_handle,
3670 			    (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)),
3671 			    port_intr_status & INTR_MASK);
3672 		}
3673 
3674 		/*
3675 		 * Note that we did not clear the interrupt for command
3676 		 * completion interrupt. Reading of slot_status takes care
3677 		 * of clearing the interrupt for command completion case.
3678 		 */
3679 
3680 		if (port_intr_status & INTR_COMMAND_ERROR) {
3681 			si_schedule_intr_command_error(si_ctlp, si_portp, port);
3682 		}
3683 
3684 		if (port_intr_status & INTR_PORT_READY) {
3685 			(void) si_intr_port_ready(si_ctlp, si_portp, port);
3686 		}
3687 
3688 		if (port_intr_status & INTR_POWER_CHANGE) {
3689 			(void) si_intr_pwr_change(si_ctlp, si_portp, port);
3690 		}
3691 
3692 		if (port_intr_status & INTR_PHYRDY_CHANGE) {
3693 			(void) si_intr_phy_ready_change(si_ctlp, si_portp,
3694 			    port);
3695 		}
3696 
3697 		if (port_intr_status & INTR_COMWAKE_RECEIVED) {
3698 			(void) si_intr_comwake_rcvd(si_ctlp, si_portp,
3699 			    port);
3700 		}
3701 
3702 		if (port_intr_status & INTR_UNRECOG_FIS) {
3703 			(void) si_intr_unrecognised_fis(si_ctlp, si_portp,
3704 			    port);
3705 		}
3706 
3707 		if (port_intr_status & INTR_DEV_XCHANGED) {
3708 			(void) si_intr_dev_xchanged(si_ctlp, si_portp, port);
3709 		}
3710 
3711 		if (port_intr_status & INTR_8B10B_DECODE_ERROR) {
3712 			(void) si_intr_decode_err_threshold(si_ctlp, si_portp,
3713 			    port);
3714 		}
3715 
3716 		if (port_intr_status & INTR_CRC_ERROR) {
3717 			(void) si_intr_crc_err_threshold(si_ctlp, si_portp,
3718 			    port);
3719 		}
3720 
3721 		if (port_intr_status & INTR_HANDSHAKE_ERROR) {
3722 			(void) si_intr_handshake_err_threshold(si_ctlp,
3723 			    si_portp, port);
3724 		}
3725 
3726 		if (port_intr_status & INTR_SETDEVBITS_NOTIFY) {
3727 			(void)