1e07d9cb8Szf /* 2*1a932f2eSQuaker Fang * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3e07d9cb8Szf * Use is subject to license terms. 4e07d9cb8Szf */ 5e07d9cb8Szf 6e07d9cb8Szf /* 7e07d9cb8Szf * Copyright (c) 2005, 2006 8e07d9cb8Szf * Damien Bergamini <damien.bergamini@free.fr> 9e07d9cb8Szf * 10e07d9cb8Szf * Permission to use, copy, modify, and distribute this software for any 11e07d9cb8Szf * purpose with or without fee is hereby granted, provided that the above 12e07d9cb8Szf * copyright notice and this permission notice appear in all copies. 13e07d9cb8Szf * 14e07d9cb8Szf * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15e07d9cb8Szf * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16e07d9cb8Szf * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17e07d9cb8Szf * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18e07d9cb8Szf * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19e07d9cb8Szf * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20e07d9cb8Szf * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21e07d9cb8Szf */ 22e07d9cb8Szf #ifndef _RT2560_VAR_H 23e07d9cb8Szf #define _RT2560_VAR_H 24e07d9cb8Szf 25e07d9cb8Szf #ifdef __cplusplus 26e07d9cb8Szf extern "C" { 27e07d9cb8Szf #endif 28e07d9cb8Szf 29e07d9cb8Szf #define RAL_FLAG_RUNNING (1<<0) 30fe3e6e3aSQuaker Fang #define RAL_FLAG_SUSPENDING (1<<1) 31e07d9cb8Szf 32e07d9cb8Szf #define RAL_RCR_PROMISC (1<<0) 33e07d9cb8Szf #define RAL_RCR_MULTI (2<<0) 34e07d9cb8Szf 35e07d9cb8Szf #ifndef DDI_NT_NET_WIFI 36e07d9cb8Szf #define DDI_NT_NET_WIFI "ddi_network:wifi" 37e07d9cb8Szf #endif 38e07d9cb8Szf 39e07d9cb8Szf /* 40e07d9cb8Szf * Bit flags in the ral_dbg_flags 41e07d9cb8Szf */ 42e07d9cb8Szf #define RAL_DBG_MSG 0x000001 43e07d9cb8Szf #define RAL_DBG_HW 0x000002 44e07d9cb8Szf #define RAL_DBG_DMA 0x000004 45e07d9cb8Szf #define RAL_DBG_INTR 0x000008 46e07d9cb8Szf #define RAL_DBG_TX 0x000010 47e07d9cb8Szf #define RAL_DBG_RX 0x000020 48e07d9cb8Szf #define RAL_DBG_CHAN 0x000040 49e07d9cb8Szf #define RAL_DBG_IOCTL 0x000080 50e07d9cb8Szf #define RAL_DBG_MGMT 0x000100 51e07d9cb8Szf #define RAL_DBG_STAT 0x000200 52e07d9cb8Szf #define RAL_DBG_GLD 0x000400 53e07d9cb8Szf #define RAL_DBG_80211 0x000800 54e07d9cb8Szf #define RAL_DBG_STATE 0x001000 55e07d9cb8Szf #define RAL_DBG_RXPACKET 0x002000 56e07d9cb8Szf #define RAL_DBG_TXPACKET 0x004000 57fe3e6e3aSQuaker Fang #define RAL_DBG_SUSPEND 0x008000 58fe3e6e3aSQuaker Fang #define RAL_DBG_ALL 0x00ffff 59e07d9cb8Szf 60e07d9cb8Szf #define RT2560_RX_RADIOTAP_PRESENT \ 61e07d9cb8Szf ((1 << IEEE80211_RADIOTAP_TSFT) | \ 62e07d9cb8Szf (1 << IEEE80211_RADIOTAP_FLAGS) | \ 63e07d9cb8Szf (1 << IEEE80211_RADIOTAP_RATE) | \ 64e07d9cb8Szf (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 65e07d9cb8Szf (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 66e07d9cb8Szf (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) 67e07d9cb8Szf 68e07d9cb8Szf #define RT2560_TX_RADIOTAP_PRESENT \ 69e07d9cb8Szf ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 70e07d9cb8Szf (1 << IEEE80211_RADIOTAP_RATE) | \ 71e07d9cb8Szf (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 72e07d9cb8Szf (1 << IEEE80211_RADIOTAP_ANTENNA)) 73e07d9cb8Szf 74e07d9cb8Szf struct dma_region { 75e07d9cb8Szf ddi_dma_handle_t dr_hnd; 76e07d9cb8Szf ddi_acc_handle_t dr_acc; 77e07d9cb8Szf ddi_dma_cookie_t dr_cookie; 78e07d9cb8Szf uint_t dr_ccnt; 79e07d9cb8Szf uint32_t dr_pbase; 80e07d9cb8Szf caddr_t dr_base; 81e07d9cb8Szf size_t dr_size; 82e07d9cb8Szf }; 83e07d9cb8Szf 84e07d9cb8Szf struct rt2560_tx_data { 85e07d9cb8Szf caddr_t buf; 86e07d9cb8Szf struct ieee80211_node *ni; 87e07d9cb8Szf struct ral_rssdesc id; 88e07d9cb8Szf }; 89e07d9cb8Szf 90e07d9cb8Szf /* 91e07d9cb8Szf * physaddr = dr_desc.dr_pbase 92e07d9cb8Szf * desc = dr_desc.dr_base, desc[i].physaddr = dr_txbuf[i].dr_pbase 93e07d9cb8Szf * data[i]->buf = dr_txbuf[i].dr_bas 94e07d9cb8Szf */ 95e07d9cb8Szf struct rt2560_tx_ring { 96e07d9cb8Szf uint32_t physaddr; 97e07d9cb8Szf struct rt2560_tx_desc *desc; 98e07d9cb8Szf struct rt2560_tx_data *data; 99e07d9cb8Szf 100e07d9cb8Szf struct dma_region dr_desc; 101e07d9cb8Szf struct dma_region *dr_txbuf; 102e07d9cb8Szf 103e07d9cb8Szf int count; 104e07d9cb8Szf int queued; 105e07d9cb8Szf int cur; 106e07d9cb8Szf int next; 107e07d9cb8Szf int cur_encrypt; 108e07d9cb8Szf int next_encrypt; 109e07d9cb8Szf kmutex_t tx_lock; 110e07d9cb8Szf }; 111e07d9cb8Szf 112e07d9cb8Szf struct rt2560_rx_data { 113e07d9cb8Szf caddr_t buf; 114e07d9cb8Szf int drop; 115e07d9cb8Szf }; 116e07d9cb8Szf 117e07d9cb8Szf struct rt2560_rx_ring { 118e07d9cb8Szf uint32_t physaddr; 119e07d9cb8Szf struct rt2560_rx_desc *desc; 120e07d9cb8Szf struct rt2560_rx_data *data; 121e07d9cb8Szf 122e07d9cb8Szf struct dma_region dr_desc; 123e07d9cb8Szf struct dma_region *dr_rxbuf; 124e07d9cb8Szf 125e07d9cb8Szf int count; 126e07d9cb8Szf int cur; 127e07d9cb8Szf int next; 128e07d9cb8Szf int cur_decrypt; 129e07d9cb8Szf kmutex_t rx_lock; 130e07d9cb8Szf }; 131e07d9cb8Szf 132e07d9cb8Szf struct rt2560_node { 133e07d9cb8Szf struct ieee80211_node ni; 134e07d9cb8Szf struct ral_rssadapt rssadapt; 135e07d9cb8Szf }; 136e07d9cb8Szf 137e07d9cb8Szf struct rt2560_softc { 138e07d9cb8Szf struct ieee80211com sc_ic; 139e07d9cb8Szf dev_info_t *sc_dev; 140e07d9cb8Szf 141e07d9cb8Szf /* ddi i/o handler */ 142e07d9cb8Szf ddi_acc_handle_t sc_ioh; 143e07d9cb8Szf caddr_t sc_rbase; 144e07d9cb8Szf 145e07d9cb8Szf /* interrupt */ 146e07d9cb8Szf ddi_iblock_cookie_t sc_iblock; 147e07d9cb8Szf 148e07d9cb8Szf kmutex_t sc_genlock; 149e07d9cb8Szf 150e07d9cb8Szf timeout_id_t sc_scan_id; 151e07d9cb8Szf timeout_id_t sc_rssadapt_id; 152e07d9cb8Szf 153e07d9cb8Szf enum ieee80211_state sc_ostate; 154e07d9cb8Szf timeout_id_t sc_state_id; 155e07d9cb8Szf 156e07d9cb8Szf int sc_tx_timer; 157e07d9cb8Szf 158e07d9cb8Szf uint32_t asic_rev; 159e07d9cb8Szf uint32_t eeprom_rev; 160e07d9cb8Szf uint8_t rf_rev; 161e07d9cb8Szf 162e07d9cb8Szf struct rt2560_tx_ring txq; 163e07d9cb8Szf struct rt2560_tx_ring prioq; 164e07d9cb8Szf struct rt2560_rx_ring rxq; 165e07d9cb8Szf 166e07d9cb8Szf uint32_t sc_need_sched; 167e07d9cb8Szf uint32_t sc_flags; 168e07d9cb8Szf uint32_t sc_rcr; /* RAL RCR */ 169e07d9cb8Szf 170e07d9cb8Szf uint16_t sc_cachelsz; 171e07d9cb8Szf ddi_softintr_t sc_softint_id; 172e07d9cb8Szf 173e07d9cb8Szf uint32_t sc_rx_pend; 174e07d9cb8Szf 175e07d9cb8Szf uint32_t rf_regs[4]; 176e07d9cb8Szf uint8_t txpow[14]; 177e07d9cb8Szf 178e07d9cb8Szf struct { 179e07d9cb8Szf uint8_t reg; 180e07d9cb8Szf uint8_t val; 181e07d9cb8Szf } bbp_prom[16]; 182e07d9cb8Szf 183e07d9cb8Szf int led_mode; 184e07d9cb8Szf int hw_radio; 185e07d9cb8Szf int rx_ant; 186e07d9cb8Szf int tx_ant; 187e07d9cb8Szf int nb_ant; 188e07d9cb8Szf 189e07d9cb8Szf int dwelltime; 190e07d9cb8Szf 191e07d9cb8Szf /* kstats */ 192e07d9cb8Szf uint32_t sc_tx_nobuf; 193e07d9cb8Szf uint32_t sc_rx_nobuf; 194e07d9cb8Szf uint32_t sc_tx_err; 195e07d9cb8Szf uint32_t sc_rx_err; 196e07d9cb8Szf uint32_t sc_tx_retries; 197e07d9cb8Szf 198e07d9cb8Szf int (*sc_newstate)(struct ieee80211com *, 199e07d9cb8Szf enum ieee80211_state, int); 200e07d9cb8Szf }; 201e07d9cb8Szf 202fe3e6e3aSQuaker Fang #define RAL_IS_RUNNING(_sc) (((_sc)->sc_flags & RAL_FLAG_RUNNING) && \ 203fe3e6e3aSQuaker Fang !((_sc)->sc_flags & RAL_FLAG_SUSPENDING)) 204fe3e6e3aSQuaker Fang #define RAL_IS_INITED(_sc) ((_sc)->sc_flags & RAL_FLAG_RUNNING) 205e07d9cb8Szf #define RAL_LOCK(sc) mutex_enter(&(sc)->sc_genlock) 206e07d9cb8Szf #define RAL_UNLOCK(sc) mutex_exit(&(sc)->sc_genlock) 207e07d9cb8Szf 208e07d9cb8Szf #define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] 209e07d9cb8Szf #define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" 210e07d9cb8Szf 211e07d9cb8Szf #ifdef __cplusplus 212e07d9cb8Szf } 213e07d9cb8Szf #endif 214e07d9cb8Szf 215e07d9cb8Szf #endif /* _RT2560_VAR_H */ 216