xref: /illumos-gate/usr/src/uts/common/io/qede/qede_main.c (revision 8af61ecc)
114b24e2bSVaishali Kulkarni /*
214b24e2bSVaishali Kulkarni * CDDL HEADER START
314b24e2bSVaishali Kulkarni *
414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
514b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
614b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
714b24e2bSVaishali Kulkarni *
814b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
914b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
1014b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
1114b24e2bSVaishali Kulkarni * and limitations under the License.
1214b24e2bSVaishali Kulkarni *
1314b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
1414b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1514b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
1614b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
1714b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
1814b24e2bSVaishali Kulkarni *
1914b24e2bSVaishali Kulkarni * CDDL HEADER END
2014b24e2bSVaishali Kulkarni */
2114b24e2bSVaishali Kulkarni 
2214b24e2bSVaishali Kulkarni /*
2314b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
2414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
2514b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
2614b24e2bSVaishali Kulkarni 
2714b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
2814b24e2bSVaishali Kulkarni 
2914b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
3014b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
3114b24e2bSVaishali Kulkarni 
3214b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
3314b24e2bSVaishali Kulkarni * limitations under the License.
3414b24e2bSVaishali Kulkarni */
3514b24e2bSVaishali Kulkarni 
3614b24e2bSVaishali Kulkarni 
3714b24e2bSVaishali Kulkarni #include "qede.h"
3814b24e2bSVaishali Kulkarni 
3914b24e2bSVaishali Kulkarni ddi_device_acc_attr_t qede_regs_acc_attr = {
4014b24e2bSVaishali Kulkarni 	DDI_DEVICE_ATTR_V1,     // devacc_attr_version;
4114b24e2bSVaishali Kulkarni 	DDI_STRUCTURE_LE_ACC,   // devacc_attr_endian_flags;
4214b24e2bSVaishali Kulkarni 	DDI_STRICTORDER_ACC,    // devacc_attr_dataorder;
4314b24e2bSVaishali Kulkarni 	DDI_FLAGERR_ACC         // devacc_attr_access;
4414b24e2bSVaishali Kulkarni };
4514b24e2bSVaishali Kulkarni 
4614b24e2bSVaishali Kulkarni ddi_device_acc_attr_t qede_desc_acc_attr = {
4714b24e2bSVaishali Kulkarni 	DDI_DEVICE_ATTR_V0,    // devacc_attr_version;
4814b24e2bSVaishali Kulkarni 	DDI_STRUCTURE_LE_ACC,  // devacc_attr_endian_flags;
4914b24e2bSVaishali Kulkarni 	DDI_STRICTORDER_ACC    // devacc_attr_dataorder;
5014b24e2bSVaishali Kulkarni };
5114b24e2bSVaishali Kulkarni 
5214b24e2bSVaishali Kulkarni /*
5314b24e2bSVaishali Kulkarni  * DMA access attributes for BUFFERS.
5414b24e2bSVaishali Kulkarni  */
5514b24e2bSVaishali Kulkarni ddi_device_acc_attr_t qede_buf_acc_attr =
5614b24e2bSVaishali Kulkarni {
5714b24e2bSVaishali Kulkarni 	DDI_DEVICE_ATTR_V0,   // devacc_attr_version;
5814b24e2bSVaishali Kulkarni 	DDI_NEVERSWAP_ACC,    // devacc_attr_endian_flags;
5914b24e2bSVaishali Kulkarni 	DDI_STRICTORDER_ACC   // devacc_attr_dataorder;
6014b24e2bSVaishali Kulkarni };
6114b24e2bSVaishali Kulkarni 
6214b24e2bSVaishali Kulkarni 
6314b24e2bSVaishali Kulkarni ddi_dma_attr_t qede_desc_dma_attr =
6414b24e2bSVaishali Kulkarni {
6514b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,
6614b24e2bSVaishali Kulkarni 	0x0000000000000000ull,
6714b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,
6814b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,
6914b24e2bSVaishali Kulkarni 	QEDE_PAGE_ALIGNMENT,
7014b24e2bSVaishali Kulkarni 	0x00000FFF,
7114b24e2bSVaishali Kulkarni 	0x00000001,
7214b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,
7314b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,
7414b24e2bSVaishali Kulkarni 	1,
7514b24e2bSVaishali Kulkarni 	0x00000001,
7614b24e2bSVaishali Kulkarni 	DDI_DMA_FLAGERR
7714b24e2bSVaishali Kulkarni };
7814b24e2bSVaishali Kulkarni 
7914b24e2bSVaishali Kulkarni ddi_dma_attr_t qede_gen_buf_dma_attr =
8014b24e2bSVaishali Kulkarni {
8114b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,
8214b24e2bSVaishali Kulkarni 	0x0000000000000000ull,
8314b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,
8414b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,
8514b24e2bSVaishali Kulkarni 	QEDE_PAGE_ALIGNMENT,
8614b24e2bSVaishali Kulkarni 	0x00000FFF,
8714b24e2bSVaishali Kulkarni 	0x00000001,
8814b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,
8914b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,
9014b24e2bSVaishali Kulkarni 	1,
9114b24e2bSVaishali Kulkarni 	0x00000001,
9214b24e2bSVaishali Kulkarni 	DDI_DMA_FLAGERR
9314b24e2bSVaishali Kulkarni };
9414b24e2bSVaishali Kulkarni 
9514b24e2bSVaishali Kulkarni /*
9614b24e2bSVaishali Kulkarni  * DMA attributes for transmit.
9714b24e2bSVaishali Kulkarni  */
9814b24e2bSVaishali Kulkarni ddi_dma_attr_t qede_tx_buf_dma_attr =
9914b24e2bSVaishali Kulkarni {
10014b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,
10114b24e2bSVaishali Kulkarni 	0x0000000000000000ull,
10214b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,
10314b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,
10414b24e2bSVaishali Kulkarni 	1,
10514b24e2bSVaishali Kulkarni 	0x00000FFF,
10614b24e2bSVaishali Kulkarni 	0x00000001,
10714b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,
10814b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,
10914b24e2bSVaishali Kulkarni 	ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1,
11014b24e2bSVaishali Kulkarni 	0x00000001,
11114b24e2bSVaishali Kulkarni 	DDI_DMA_FLAGERR
11214b24e2bSVaishali Kulkarni };
11314b24e2bSVaishali Kulkarni 
11414b24e2bSVaishali Kulkarni 
11514b24e2bSVaishali Kulkarni ddi_dma_attr_t qede_dma_attr_desc =
11614b24e2bSVaishali Kulkarni {
11714b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,		/* dma_attr_version */
11814b24e2bSVaishali Kulkarni 	0,			/* dma_attr_addr_lo */
11914b24e2bSVaishali Kulkarni 	0xffffffffffffffffull,	/* dma_attr_addr_hi */
12014b24e2bSVaishali Kulkarni 	0x000fffffull,		/* dma_attr_count_max */
12114b24e2bSVaishali Kulkarni 	4096,			/* dma_attr_align */
12214b24e2bSVaishali Kulkarni 	0x000fffffull,		/* dma_attr_burstsizes */
12314b24e2bSVaishali Kulkarni 	4,			/* dma_attr_minxfer */
12414b24e2bSVaishali Kulkarni 	0xffffffffull,		/* dma_attr_maxxfer */
12514b24e2bSVaishali Kulkarni 	0xffffffffull,		/* dma_attr_seg */
12614b24e2bSVaishali Kulkarni 	1,			/* dma_attr_sgllen */
12714b24e2bSVaishali Kulkarni 	1,			/* dma_attr_granular */
12814b24e2bSVaishali Kulkarni 	DDI_DMA_FLAGERR		/* dma_attr_flags */
12914b24e2bSVaishali Kulkarni };
13014b24e2bSVaishali Kulkarni 
13114b24e2bSVaishali Kulkarni static ddi_dma_attr_t qede_dma_attr_txbuf =
13214b24e2bSVaishali Kulkarni {
13314b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,		/* dma_attr_version */
13414b24e2bSVaishali Kulkarni 	0,			/* dma_attr_addr_lo */
13514b24e2bSVaishali Kulkarni 	0xffffffffffffffffull,	/* dma_attr_addr_hi */
13614b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,	/* dma_attr_count_max */
13714b24e2bSVaishali Kulkarni 	QEDE_PAGE_ALIGNMENT, /* dma_attr_align */
13814b24e2bSVaishali Kulkarni 	0xfff8ull,		/* dma_attr_burstsizes */
13914b24e2bSVaishali Kulkarni 	1,			/* dma_attr_minxfer */
14014b24e2bSVaishali Kulkarni 	0xffffffffull,		/* dma_attr_maxxfer */
14114b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,	/* maximum segment size */
14214b24e2bSVaishali Kulkarni 	1,			/* dma_attr_sgllen */
14314b24e2bSVaishali Kulkarni 	1,			/* dma_attr_granular */
14414b24e2bSVaishali Kulkarni 	0			/* dma_attr_flags */
14514b24e2bSVaishali Kulkarni };
14614b24e2bSVaishali Kulkarni 
14714b24e2bSVaishali Kulkarni ddi_dma_attr_t qede_dma_attr_rxbuf =
14814b24e2bSVaishali Kulkarni {
14914b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,		/* dma_attr_version */
15014b24e2bSVaishali Kulkarni 	0,			/* dma_attr_addr_lo */
15114b24e2bSVaishali Kulkarni 	0xffffffffffffffffull,	/* dma_attr_addr_hi */
15214b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,	/* dma counter max */
15314b24e2bSVaishali Kulkarni 	QEDE_PAGE_ALIGNMENT,	/* dma_attr_align */
15414b24e2bSVaishali Kulkarni 	0xfff8ull,		/* dma_attr_burstsizes */
15514b24e2bSVaishali Kulkarni 	1,			/* dma_attr_minxfer */
15614b24e2bSVaishali Kulkarni 	0xffffffffull,		/* dma_attr_maxxfer */
15714b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,	/* maximum segment size */
15814b24e2bSVaishali Kulkarni 	1,			/* dma_attr_sgllen */
15914b24e2bSVaishali Kulkarni 	1,			/* dma_attr_granular */
16014b24e2bSVaishali Kulkarni 	DDI_DMA_RELAXED_ORDERING	/* dma_attr_flags */
16114b24e2bSVaishali Kulkarni };
16214b24e2bSVaishali Kulkarni 
16314b24e2bSVaishali Kulkarni /* LINTED E_STATIC_UNUSED */
16414b24e2bSVaishali Kulkarni static ddi_dma_attr_t qede_dma_attr_cmddesc =
16514b24e2bSVaishali Kulkarni {
16614b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,		/* dma_attr_version */
16714b24e2bSVaishali Kulkarni 	0,			/* dma_attr_addr_lo */
16814b24e2bSVaishali Kulkarni 	0xffffffffffffffffull,	/* dma_attr_addr_hi */
16914b24e2bSVaishali Kulkarni 	0xffffffffull,		/* dma_attr_count_max */
17014b24e2bSVaishali Kulkarni 	1,			/* dma_attr_align */
17114b24e2bSVaishali Kulkarni 	0xfff8ull,		/* dma_attr_burstsizes */
17214b24e2bSVaishali Kulkarni 	1,			/* dma_attr_minxfer */
17314b24e2bSVaishali Kulkarni 	0xffffffff,		/* dma_attr_maxxfer */
17414b24e2bSVaishali Kulkarni 	0xffffffff,		/* dma_attr_seg */
17514b24e2bSVaishali Kulkarni 	ETH_TX_MAX_BDS_PER_NON_LSO_PACKET,	/* dma_attr_sgllen */
17614b24e2bSVaishali Kulkarni 	1,			/* dma_attr_granular */
17714b24e2bSVaishali Kulkarni 	0			/* dma_attr_flags */
17814b24e2bSVaishali Kulkarni };
17914b24e2bSVaishali Kulkarni 
18014b24e2bSVaishali Kulkarni 
18114b24e2bSVaishali Kulkarni 
18214b24e2bSVaishali Kulkarni /*
18314b24e2bSVaishali Kulkarni  * Generic dma attribute for single sg
18414b24e2bSVaishali Kulkarni  */
18514b24e2bSVaishali Kulkarni /* LINTED E_STATIC_UNUSED */
18614b24e2bSVaishali Kulkarni static ddi_dma_attr_t qede_gen_dma_attr_desc =
18714b24e2bSVaishali Kulkarni {
18814b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,            /* dma_attr_version */
18914b24e2bSVaishali Kulkarni 	0,                      /* dma_attr_addr_lo */
19014b24e2bSVaishali Kulkarni 	0xffffffffffffffffull,	/* dma_attr_addr_hi */
19114b24e2bSVaishali Kulkarni 	0x000fffffull,          /* dma_attr_count_max */
19214b24e2bSVaishali Kulkarni 	4096,                   /* dma_attr_align */
19314b24e2bSVaishali Kulkarni 	0x000fffffull,          /* dma_attr_burstsizes */
19414b24e2bSVaishali Kulkarni 	4,                      /* dma_attr_minxfer */
19514b24e2bSVaishali Kulkarni 	0xffffffffull,          /* dma_attr_maxxfer */
19614b24e2bSVaishali Kulkarni 	0xffffffffull,          /* dma_attr_seg */
19714b24e2bSVaishali Kulkarni 	1,                      /* dma_attr_sgllen */
19814b24e2bSVaishali Kulkarni 	1,                      /* dma_attr_granular */
19914b24e2bSVaishali Kulkarni 	DDI_DMA_FLAGERR         /* dma_attr_flags */
20014b24e2bSVaishali Kulkarni };
20114b24e2bSVaishali Kulkarni 
20214b24e2bSVaishali Kulkarni ddi_dma_attr_t qede_buf2k_dma_attr_txbuf =
20314b24e2bSVaishali Kulkarni {
20414b24e2bSVaishali Kulkarni 	DMA_ATTR_V0,		/* dma_attr_version */
20514b24e2bSVaishali Kulkarni 	0,			/* dma_attr_addr_lo */
20614b24e2bSVaishali Kulkarni 	0xffffffffffffffffull,	/* dma_attr_addr_hi */
20714b24e2bSVaishali Kulkarni 	0x00000000FFFFFFFFull,	/* dma_attr_count_max */
20814b24e2bSVaishali Kulkarni 	BUF_2K_ALIGNMENT,	/* dma_attr_align */
20914b24e2bSVaishali Kulkarni 	0xfff8ull,		/* dma_attr_burstsizes */
21014b24e2bSVaishali Kulkarni 	1,			/* dma_attr_minxfer */
21114b24e2bSVaishali Kulkarni 	0xffffffffull,		/* dma_attr_maxxfer */
21214b24e2bSVaishali Kulkarni 	0xFFFFFFFFFFFFFFFFull,	/* maximum segment size */
21314b24e2bSVaishali Kulkarni 	1,			/* dma_attr_sgllen */
21414b24e2bSVaishali Kulkarni 	0x00000001,		/* dma_attr_granular */
21514b24e2bSVaishali Kulkarni 	0			/* dma_attr_flags */
21614b24e2bSVaishali Kulkarni };
21714b24e2bSVaishali Kulkarni 
21814b24e2bSVaishali Kulkarni char *
qede_get_ddi_fail(int status)21914b24e2bSVaishali Kulkarni qede_get_ddi_fail(int status)
22014b24e2bSVaishali Kulkarni {
22114b24e2bSVaishali Kulkarni 	switch (status) {
22214b24e2bSVaishali Kulkarni 	case DDI_FAILURE:
22314b24e2bSVaishali Kulkarni 		return ("DDI_FAILURE");
22414b24e2bSVaishali Kulkarni 	case DDI_NOT_WELL_FORMED:
22514b24e2bSVaishali Kulkarni 		return ("DDI_NOT_WELL_FORMED");
22614b24e2bSVaishali Kulkarni 	case DDI_EAGAIN:
22714b24e2bSVaishali Kulkarni 		return ("DDI_EAGAIN");
22814b24e2bSVaishali Kulkarni 	case DDI_EINVAL:
22914b24e2bSVaishali Kulkarni 		return ("DDI_EINVAL");
23014b24e2bSVaishali Kulkarni 	case DDI_ENOTSUP:
23114b24e2bSVaishali Kulkarni 		return ("DDI_ENOTSUP");
23214b24e2bSVaishali Kulkarni 	case DDI_EPENDING:
23314b24e2bSVaishali Kulkarni 		return ("DDI_EPENDING");
23414b24e2bSVaishali Kulkarni 	case DDI_EALREADY:
23514b24e2bSVaishali Kulkarni 		return ("DDI_EALREADY");
23614b24e2bSVaishali Kulkarni 	case DDI_ENOMEM:
23714b24e2bSVaishali Kulkarni 		return ("DDI_ENOMEM");
23814b24e2bSVaishali Kulkarni 	case DDI_EBUSY:
23914b24e2bSVaishali Kulkarni 		return ("DDI_EBUSY");
24014b24e2bSVaishali Kulkarni 	case DDI_ETRANSPORT:
24114b24e2bSVaishali Kulkarni 		return ("DDI_ETRANSPORT");
24214b24e2bSVaishali Kulkarni 	case DDI_ECONTEXT:
24314b24e2bSVaishali Kulkarni 		return ("DDI_ECONTEXT");
24414b24e2bSVaishali Kulkarni 	default:
24514b24e2bSVaishali Kulkarni 		return ("ERROR CODE NOT FOUND!");
24614b24e2bSVaishali Kulkarni 	}
24714b24e2bSVaishali Kulkarni }
24814b24e2bSVaishali Kulkarni 
24914b24e2bSVaishali Kulkarni char *
qede_get_ecore_fail(int status)25014b24e2bSVaishali Kulkarni qede_get_ecore_fail(int status)
25114b24e2bSVaishali Kulkarni {
25214b24e2bSVaishali Kulkarni 	switch (status) {
25314b24e2bSVaishali Kulkarni 	case ECORE_UNKNOWN_ERROR:
25414b24e2bSVaishali Kulkarni 		return ("ECORE_UNKNOWN_ERROR");
25514b24e2bSVaishali Kulkarni 	case ECORE_NORESOURCES:
25614b24e2bSVaishali Kulkarni 		return ("ECORE_NORESOURCES");
25714b24e2bSVaishali Kulkarni 	case ECORE_NODEV:
25814b24e2bSVaishali Kulkarni 		return ("ECORE_NODEV");
25914b24e2bSVaishali Kulkarni 	case ECORE_ABORTED:
26014b24e2bSVaishali Kulkarni 		return ("ECORE_ABORTED");
26114b24e2bSVaishali Kulkarni 	case ECORE_AGAIN:
26214b24e2bSVaishali Kulkarni 		return ("ECORE_AGAIN");
26314b24e2bSVaishali Kulkarni 	case ECORE_NOTIMPL:
26414b24e2bSVaishali Kulkarni 		return ("ECORE_NOTIMPL");
26514b24e2bSVaishali Kulkarni 	case ECORE_EXISTS:
26614b24e2bSVaishali Kulkarni 		return ("ECORE_EXISTS");
26714b24e2bSVaishali Kulkarni 	case ECORE_IO:
26814b24e2bSVaishali Kulkarni 		return ("ECORE_IO");
26914b24e2bSVaishali Kulkarni 	case ECORE_TIMEOUT:
27014b24e2bSVaishali Kulkarni 		return ("ECORE_TIMEOUT");
27114b24e2bSVaishali Kulkarni 	case ECORE_INVAL:
27214b24e2bSVaishali Kulkarni 		return ("ECORE_INVAL");
27314b24e2bSVaishali Kulkarni 	case ECORE_BUSY:
27414b24e2bSVaishali Kulkarni 		return ("ECORE_BUSY");
27514b24e2bSVaishali Kulkarni 	case ECORE_NOMEM:
27614b24e2bSVaishali Kulkarni 		return ("ECORE_NOMEM");
27714b24e2bSVaishali Kulkarni 	case ECORE_SUCCESS:
27814b24e2bSVaishali Kulkarni 		return ("ECORE_SUCCESS");
27914b24e2bSVaishali Kulkarni 	case ECORE_PENDING:
28014b24e2bSVaishali Kulkarni 		return ("ECORE_PENDING");
28114b24e2bSVaishali Kulkarni 	default:
28214b24e2bSVaishali Kulkarni 		return ("ECORE ERROR CODE NOT FOUND!");
28314b24e2bSVaishali Kulkarni 	}
28414b24e2bSVaishali Kulkarni }
28514b24e2bSVaishali Kulkarni 
28614b24e2bSVaishali Kulkarni #define QEDE_CHIP_NUM(_p)\
28714b24e2bSVaishali Kulkarni  (((_p)->edev.chip_num) & 0xffff)
28814b24e2bSVaishali Kulkarni 
28914b24e2bSVaishali Kulkarni char *
qede_chip_name(qede_t * qede)29014b24e2bSVaishali Kulkarni qede_chip_name(qede_t *qede)
29114b24e2bSVaishali Kulkarni {
29214b24e2bSVaishali Kulkarni     switch (QEDE_CHIP_NUM(qede)) {
29314b24e2bSVaishali Kulkarni         case 0x1634:
29414b24e2bSVaishali Kulkarni 		return ("BCM57980E");
29514b24e2bSVaishali Kulkarni 
29614b24e2bSVaishali Kulkarni         case 0x1629:
29714b24e2bSVaishali Kulkarni 		return ("BCM57980S");
29814b24e2bSVaishali Kulkarni 
29914b24e2bSVaishali Kulkarni         case 0x1630:
30014b24e2bSVaishali Kulkarni 		return ("BCM57940_KR2");
30114b24e2bSVaishali Kulkarni 
30214b24e2bSVaishali Kulkarni 	case 0x8070:
30314b24e2bSVaishali Kulkarni 		return ("ARROWHEAD");
30414b24e2bSVaishali Kulkarni 
30514b24e2bSVaishali Kulkarni 	case 0x8071:
30614b24e2bSVaishali Kulkarni 		return ("ARROWHEAD");
30714b24e2bSVaishali Kulkarni 
30814b24e2bSVaishali Kulkarni 	case 0x8072:
30914b24e2bSVaishali Kulkarni 		return ("ARROWHEAD");
31014b24e2bSVaishali Kulkarni 
31114b24e2bSVaishali Kulkarni 	case 0x8073:
31214b24e2bSVaishali Kulkarni 		return ("ARROWHEAD");
31314b24e2bSVaishali Kulkarni 
31414b24e2bSVaishali Kulkarni         default:
31514b24e2bSVaishali Kulkarni 		return ("UNKNOWN");
31614b24e2bSVaishali Kulkarni     }
31714b24e2bSVaishali Kulkarni }
31814b24e2bSVaishali Kulkarni 
31914b24e2bSVaishali Kulkarni 
32014b24e2bSVaishali Kulkarni 
32114b24e2bSVaishali Kulkarni 
32214b24e2bSVaishali Kulkarni static void
qede_destroy_locks(qede_t * qede)32314b24e2bSVaishali Kulkarni qede_destroy_locks(qede_t *qede)
32414b24e2bSVaishali Kulkarni {
32514b24e2bSVaishali Kulkarni 	qede_fastpath_t *fp = &qede->fp_array[0];
32614b24e2bSVaishali Kulkarni 	qede_rx_ring_t *rx_ring;
32714b24e2bSVaishali Kulkarni 	qede_tx_ring_t *tx_ring;
32814b24e2bSVaishali Kulkarni 	int i, j;
32914b24e2bSVaishali Kulkarni 
33014b24e2bSVaishali Kulkarni 	mutex_destroy(&qede->drv_lock);
33114b24e2bSVaishali Kulkarni 	mutex_destroy(&qede->watch_lock);
33214b24e2bSVaishali Kulkarni 
33314b24e2bSVaishali Kulkarni 	for (i = 0; i < qede->num_fp; i++, fp++) {
33414b24e2bSVaishali Kulkarni 		mutex_destroy(&fp->fp_lock);
33514b24e2bSVaishali Kulkarni 
33614b24e2bSVaishali Kulkarni 		rx_ring = fp->rx_ring;
33714b24e2bSVaishali Kulkarni 		mutex_destroy(&rx_ring->rx_lock);
33814b24e2bSVaishali Kulkarni 		mutex_destroy(&rx_ring->rx_replen_lock);
33914b24e2bSVaishali Kulkarni 
34014b24e2bSVaishali Kulkarni 		for (j = 0; j < qede->num_tc; j++) {
34114b24e2bSVaishali Kulkarni 			tx_ring = fp->tx_ring[j];
34214b24e2bSVaishali Kulkarni 			mutex_destroy(&tx_ring->tx_lock);
34314b24e2bSVaishali Kulkarni 		}
34414b24e2bSVaishali Kulkarni 	}
34514b24e2bSVaishali Kulkarni 	mutex_destroy(&qede->gld_lock);
34614b24e2bSVaishali Kulkarni 	mutex_destroy(&qede->kstat_lock);
34714b24e2bSVaishali Kulkarni }
34814b24e2bSVaishali Kulkarni 
34914b24e2bSVaishali Kulkarni static void
qede_init_locks(qede_t * qede)35014b24e2bSVaishali Kulkarni qede_init_locks(qede_t *qede)
35114b24e2bSVaishali Kulkarni {
35214b24e2bSVaishali Kulkarni 	qede_intr_context_t *intr_ctx = &qede->intr_ctx;
35314b24e2bSVaishali Kulkarni 	qede_fastpath_t *fp = &qede->fp_array[0];
35414b24e2bSVaishali Kulkarni 	qede_rx_ring_t *rx_ring;
35514b24e2bSVaishali Kulkarni 	qede_tx_ring_t *tx_ring;
35614b24e2bSVaishali Kulkarni 	int i, tc;
35714b24e2bSVaishali Kulkarni 
35814b24e2bSVaishali Kulkarni 	mutex_init(&qede->drv_lock, NULL,
35914b24e2bSVaishali Kulkarni 	    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
36014b24e2bSVaishali Kulkarni 	mutex_init(&qede->watch_lock, NULL,
36114b24e2bSVaishali Kulkarni 	    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
36214b24e2bSVaishali Kulkarni 
36314b24e2bSVaishali Kulkarni 	for (i = 0; i < qede->num_fp; i++, fp++) {
36414b24e2bSVaishali Kulkarni 		mutex_init(&fp->fp_lock, NULL,
36514b24e2bSVaishali Kulkarni 		    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
36614b24e2bSVaishali Kulkarni 
36714b24e2bSVaishali Kulkarni 		rx_ring = fp->rx_ring;
36814b24e2bSVaishali Kulkarni 		mutex_init(&rx_ring->rx_lock, NULL,
36914b24e2bSVaishali Kulkarni 		    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
37014b24e2bSVaishali Kulkarni 		mutex_init(&rx_ring->rx_replen_lock, NULL,
37114b24e2bSVaishali Kulkarni 		    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
37214b24e2bSVaishali Kulkarni 
37314b24e2bSVaishali Kulkarni 		for (tc = 0; tc < qede->num_tc; tc++) {
37414b24e2bSVaishali Kulkarni 			tx_ring = fp->tx_ring[tc];
37514b24e2bSVaishali Kulkarni 			mutex_init(&tx_ring->tx_lock, NULL,
37614b24e2bSVaishali Kulkarni 		    	    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
37714b24e2bSVaishali Kulkarni 		}
37814b24e2bSVaishali Kulkarni 	}
37914b24e2bSVaishali Kulkarni 
38014b24e2bSVaishali Kulkarni 	mutex_init(&qede->gld_lock, NULL,
38114b24e2bSVaishali Kulkarni 	    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
38214b24e2bSVaishali Kulkarni 	mutex_init(&qede->kstat_lock, NULL,
38314b24e2bSVaishali Kulkarni 	    MUTEX_DRIVER, DDI_INTR_PRI(intr_ctx->intr_pri));
38414b24e2bSVaishali Kulkarni }
38514b24e2bSVaishali Kulkarni 
38614b24e2bSVaishali Kulkarni /* LINTED E_FUNC_ARG_UNUSED */
qede_free_io_structs(qede_t * qede)38714b24e2bSVaishali Kulkarni static void qede_free_io_structs(qede_t *qede)
38814b24e2bSVaishali Kulkarni {
38914b24e2bSVaishali Kulkarni }
39014b24e2bSVaishali Kulkarni 
39114b24e2bSVaishali Kulkarni static int
qede_alloc_io_structs(qede_t * qede)39214b24e2bSVaishali Kulkarni qede_alloc_io_structs(qede_t *qede)
39314b24e2bSVaishali Kulkarni {
39414b24e2bSVaishali Kulkarni 	qede_fastpath_t *fp;
39514b24e2bSVaishali Kulkarni 	qede_rx_ring_t *rx_ring;
39614b24e2bSVaishali Kulkarni 	qede_tx_ring_t *tx_array, *tx_ring;
39714b24e2bSVaishali Kulkarni 	int i, tc;
39814b24e2bSVaishali Kulkarni 
39914b24e2bSVaishali Kulkarni 	/*
40014b24e2bSVaishali Kulkarni 	 * Put rx ring + tx_ring pointers paired
40114b24e2bSVaishali Kulkarni 	 * into the fp data structure array
40214b24e2bSVaishali Kulkarni 	 */
40314b24e2bSVaishali Kulkarni 	for (i = 0; i < qede->num_fp; i++) {
40414b24e2bSVaishali Kulkarni 		fp = &qede->fp_array[i];
40514b24e2bSVaishali Kulkarni 		rx_ring = &qede->rx_array[i];
40614b24e2bSVaishali Kulkarni 
40714b24e2bSVaishali Kulkarni 		for (tc = 0; tc < qede->num_tc; tc++) {
40814b24e2bSVaishali Kulkarni 			tx_array = qede->tx_array[tc];
40914b24e2bSVaishali Kulkarni 			tx_ring = &tx_array[i];
41014b24e2bSVaishali Kulkarni 			fp->tx_ring[tc] = tx_ring;
41114b24e2bSVaishali Kulkarni 		}
41214b24e2bSVaishali Kulkarni 
41314b24e2bSVaishali Kulkarni 		fp->rx_ring = rx_ring;
41414b24e2bSVaishali Kulkarni 		rx_ring->group_index = 0;
41514b24e2bSVaishali Kulkarni 	}
41614b24e2bSVaishali Kulkarni 
41714b24e2bSVaishali Kulkarni 	return (DDI_SUCCESS);
41814b24e2bSVaishali Kulkarni }
41914b24e2bSVaishali Kulkarni 
42014b24e2bSVaishali Kulkarni static int
qede_get_config_params(qede_t * qede)42114b24e2bSVaishali Kulkarni qede_get_config_params(qede_t *qede)
42214b24e2bSVaishali Kulkarni {
42314b24e2bSVaishali Kulkarni 	struct ecore_dev *edev = &qede->edev;
42414b24e2bSVaishali Kulkarni 
42514b24e2bSVaishali Kulkarni 	qede_cfg_init(qede);
42614b24e2bSVaishali Kulkarni 
42714b24e2bSVaishali Kulkarni 	qede->num_tc = DEFAULT_TRFK_CLASS_COUNT;
42814b24e2bSVaishali Kulkarni 	qede->num_hwfns = edev->num_hwfns;
42914b24e2bSVaishali Kulkarni 	qede->rx_buf_count = qede->rx_ring_size;
43014b24e2bSVaishali Kulkarni 	qede->rx_buf_size = DEFAULT_RX_BUF_SIZE;
43114b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->num_fp = %d\n", __func__, qede->instance,
43214b24e2bSVaishali Kulkarni 		qede->num_fp);
43314b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->rx_ring_size = %d\n", __func__,
43414b24e2bSVaishali Kulkarni 		qede->instance, qede->rx_ring_size);
43514b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->rx_buf_count = %d\n", __func__,
43614b24e2bSVaishali Kulkarni 		qede->instance, qede->rx_buf_count);
43714b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->rx_buf_size = %d\n", __func__,
43814b24e2bSVaishali Kulkarni 		qede->instance, qede->rx_buf_size);
43914b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->rx_copy_threshold = %d\n", __func__,
44014b24e2bSVaishali Kulkarni 		qede->instance, qede->rx_copy_threshold);
44114b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->tx_ring_size = %d\n", __func__,
44214b24e2bSVaishali Kulkarni 		qede->instance, qede->tx_ring_size);
44314b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->tx_copy_threshold = %d\n", __func__,
44414b24e2bSVaishali Kulkarni 		qede->instance, qede->tx_bcopy_threshold);
44514b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->lso_enable = %d\n", __func__,
44614b24e2bSVaishali Kulkarni 		qede->instance, qede->lso_enable);
44714b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->lro_enable = %d\n", __func__,
44814b24e2bSVaishali Kulkarni 		qede->instance, qede->lro_enable);
44914b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->jumbo_enable = %d\n", __func__,
45014b24e2bSVaishali Kulkarni 		qede->instance, qede->jumbo_enable);
45114b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->log_enable = %d\n", __func__,
45214b24e2bSVaishali Kulkarni 		qede->instance, qede->log_enable);
45314b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->checksum = %d\n", __func__,
45414b24e2bSVaishali Kulkarni 		qede->instance, qede->checksum);
45514b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->debug_level = 0x%x\n", __func__,
45614b24e2bSVaishali Kulkarni 		qede->instance, qede->ecore_debug_level);
45714b24e2bSVaishali Kulkarni 	qede_print("!%s:%d: qede->num_hwfns = %d\n", __func__,
45814b24e2bSVaishali Kulkarni 		qede->instance,qede->num_hwfns);
45914b24e2bSVaishali Kulkarni 
46014b24e2bSVaishali Kulkarni 	//qede->tx_buf_size = qede->mtu + QEDE_MAX_ETHER_HDR;
46114b24e2bSVaishali Kulkarni 	qede->tx_buf_size = BUF_2K_SIZE;
46214b24e2bSVaishali Kulkarni 	return (DDI_SUCCESS);
46314b24e2bSVaishali Kulkarni }
46414b24e2bSVaishali Kulkarni 
46514b24e2bSVaishali Kulkarni void
qede_config_debug(qede_t * qede)46614b24e2bSVaishali Kulkarni qede_config_debug(qede_t *qede)
46714b24e2bSVaishali Kulkarni {
46814b24e2bSVaishali Kulkarni 
46914b24e2bSVaishali Kulkarni 	struct ecore_dev *edev = &qede->edev;
47014b24e2bSVaishali Kulkarni 	u32 dp_level = 0;
47114b24e2bSVaishali Kulkarni 	u8 dp_module = 0;
47214b24e2bSVaishali Kulkarni 
47314b24e2bSVaishali Kulkarni 	dp_level = qede->ecore_debug_level;
47414b24e2bSVaishali Kulkarni 	dp_module = qede->ecore_debug_module;
47514b24e2bSVaishali Kulkarni 	ecore_init_dp(edev, dp_module, dp_level, NULL);
47614b24e2bSVaishali Kulkarni }
47714b24e2bSVaishali Kulkarni 
47814b24e2bSVaishali Kulkarni 
47914b24e2bSVaishali Kulkarni 
48014b24e2bSVaishali Kulkarni static int
qede_set_operating_params(qede_t * qede)48114b24e2bSVaishali Kulkarni qede_set_operating_params(qede_t *qede)
48214b24e2bSVaishali Kulkarni {
48314b24e2bSVaishali Kulkarni 	int status = 0;
48414b24e2bSVaishali Kulkarni 	qede_intr_context_t *intr_ctx = &qede->intr_ctx;
48514b24e2bSVaishali Kulkarni 
48614b24e2bSVaishali Kulkarni 	/* Get qede.conf paramters from user */
48714b24e2bSVaishali Kulkarni 	status = qede_get_config_params(qede);
48814b24e2bSVaishali Kulkarni 	if (status != DDI_SUCCESS) {
48914b24e2bSVaishali Kulkarni 		return (DDI_FAILURE);
49014b24e2bSVaishali Kulkarni 	}
49114b24e2bSVaishali Kulkarni 	/* config debug level */
49214b24e2bSVaishali Kulkarni 	qede_config_debug(qede);
49314b24e2bSVaishali Kulkarni 
49414b24e2bSVaishali Kulkarni 
49514b24e2bSVaishali Kulkarni 	intr_ctx->intr_vect_to_request =
49614b24e2bSVaishali Kulkarni 		qede->num_fp + qede->num_hwfns;
49714b24e2bSVaishali Kulkarni 	intr_ctx->intr_fp_vector_count = qede->num_fp - qede->num_hwfns;
49814b24e2bSVaishali Kulkarni 
49914b24e2bSVaishali Kulkarni 	/* set max number of Unicast list */
50014b24e2bSVaishali Kulkarni 	qede->ucst_total = QEDE_MAX_UCST_CNT;
50114b24e2bSVaishali Kulkarni 	qede->ucst_avail = QEDE_MAX_UCST_CNT;
50214b24e2bSVaishali Kulkarni 	bzero(&qede->ucst_mac[0], sizeof (qede_mac_addr_t) * qede->ucst_total);
50314b24e2bSVaishali Kulkarni 	qede->params.multi_promisc_fl = B_FALSE;
50414b24e2bSVaishali Kulkarni 	qede->params.promisc_fl = B_FALSE;
50514b24e2bSVaishali Kulkarni 	qede->mc_cnt = 0;
50614b24e2bSVaishali Kulkarni 	qede->rx_low_buffer_threshold = RX_LOW_BUFFER_THRESHOLD;
50714b24e2bSVaishali Kulkarni 
50814b24e2bSVaishali Kulkarni 	return (status);
50914b24e2bSVaishali Kulkarni }
51014b24e2bSVaishali Kulkarni 
51114b24e2bSVaishali Kulkarni /* Resume the interface */
51214b24e2bSVaishali Kulkarni static int
qede_resume(qede_t * qede)51314b24e2bSVaishali Kulkarni qede_resume(qede_t *qede)
51414b24e2bSVaishali Kulkarni {
51514b24e2bSVaishali Kulkarni 	mutex_enter(&qede->drv_lock);
51614b24e2bSVaishali Kulkarni 	cmn_err(CE_NOTE, "%s:%d Enter\n", __func__, qede->instance);
51714b24e2bSVaishali Kulkarni 	qede->qede_state = QEDE_STATE_ATTACHED;
51814b24e2bSVaishali Kulkarni 	mutex_exit(&qede->drv_lock);
51914b24e2bSVaishali Kulkarni 	return (DDI_FAILURE);
52014b24e2bSVaishali Kulkarni }
52114b24e2bSVaishali Kulkarni 
52214b24e2bSVaishali Kulkarni /*
52314b24e2bSVaishali Kulkarni  * Write dword to doorbell from tx_path
52414b24e2bSVaishali Kulkarni  * Avoid use of qede_t * pointer
52514b24e2bSVaishali Kulkarni  */
52614b24e2bSVaishali Kulkarni #pragma inline(qede_bar2_write32_tx_doorbell)
52714b24e2bSVaishali Kulkarni void
qede_bar2_write32_tx_doorbell(qede_tx_ring_t * tx_ring,u32 val)52814b24e2bSVaishali Kulkarni qede_bar2_write32_tx_doorbell(qede_tx_ring_t *tx_ring, u32 val)
52914b24e2bSVaishali Kulkarni {
53014b24e2bSVaishali Kulkarni 	u64 addr = (u64)tx_ring->doorbell_addr;
53114b24e2bSVaishali Kulkarni 	ddi_put32(tx_ring->doorbell_handle, (u32 *)addr, val);
53214b24e2bSVaishali Kulkarni }
53314b24e2bSVaishali Kulkarni 
53414b24e2bSVaishali Kulkarni static void
qede_unconfig_pci(qede_t * qede)53514b24e2bSVaishali Kulkarni qede_unconfig_pci(qede_t *qede)
53614b24e2bSVaishali Kulkarni {
53714b24e2bSVaishali Kulkarni 	if (qede->doorbell_handle != NULL) {
53814b24e2bSVaishali Kulkarni 		ddi_regs_map_free(&(qede->doorbell_handle));
53914b24e2bSVaishali Kulkarni 		qede->doorbell_handle = NULL;
54014b24e2bSVaishali Kulkarni 	}
54114b24e2bSVaishali Kulkarni 
54214b24e2bSVaishali Kulkarni 	if (qede->regs_handle != NULL) {
54314b24e2bSVaishali Kulkarni 		ddi_regs_map_free(&qede->regs_handle);
54414b24e2bSVaishali Kulkarni 		qede->regs_handle = NULL;
54514b24e2bSVaishali Kulkarni 	}
54614b24e2bSVaishali Kulkarni 	if (qede->pci_cfg_handle != NULL) {
54714b24e2bSVaishali Kulkarni 		pci_config_teardown(&qede->pci_cfg_handle);
54814b24e2bSVaishali Kulkarni 		qede->pci_cfg_handle = NULL;
54914b24e2bSVaishali Kulkarni 	}
55014b24e2bSVaishali Kulkarni }
55114b24e2bSVaishali Kulkarni 
55214b24e2bSVaishali Kulkarni static int
qede_config_pci(qede_t * qede)55314b24e2bSVaishali Kulkarni qede_config_pci(qede_t *qede)
55414b24e2bSVaishali Kulkarni {
55514b24e2bSVaishali Kulkarni 	int ret;
55614b24e2bSVaishali Kulkarni 
55714b24e2bSVaishali Kulkarni 	ret = pci_config_setup(qede->dip, &qede->pci_cfg_handle);
55814b24e2bSVaishali Kulkarni 	if (ret != DDI_SUCCESS) {
55914b24e2bSVaishali Kulkarni 		cmn_err(CE_NOTE, "%s:%d Failed to get PCI config handle\n",
56014b24e2bSVaishali Kulkarni 			__func__, qede->instance);
56114b24e2bSVaishali Kulkarni 		return (DDI_FAILURE);
56214b24e2bSVaishali Kulkarni 	}
56314b24e2bSVaishali Kulkarni 
56414b24e2bSVaishali Kulkarni 	/* get register size */
56514b24e2bSVaishali Kulkarni 	ret = ddi_dev_regsize(qede->dip, 1, &qede->regview_size);
56614b24e2bSVaishali Kulkarni 	if (ret != DDI_SUCCESS) {
56714b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "%s%d: failed to read reg size for bar0",
56814b24e2bSVaishali Kulkarni 			__func__, qede->instance);
56914b24e2bSVaishali Kulkarni 		goto err_exit;
57014b24e2bSVaishali Kulkarni 	}
57114b24e2bSVaishali Kulkarni 
57214b24e2bSVaishali Kulkarni 	/* get doorbell size */
57314b24e2bSVaishali Kulkarni 	ret = ddi_dev_regsize(qede->dip, 3, &qede->doorbell_size);
57414b24e2bSVaishali Kulkarni 	if (ret != DDI_SUCCESS) {
57514b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "%s%d: failed to read doorbell size for bar2",
57614b24e2bSVaishali Kulkarni 			__func__, qede->instance);
57714b24e2bSVaishali Kulkarni 		goto err_exit;
57814b24e2bSVaishali Kulkarni 	}
57914b24e2bSVaishali Kulkarni 
58014b24e2bSVaishali Kulkarni 	/* map register space */
58114b24e2bSVaishali Kulkarni 	ret = ddi_regs_map_setup(
58214b24e2bSVaishali Kulkarni 	/* Pointer to the device's dev_info structure. */
58314b24e2bSVaishali Kulkarni 	    qede->dip,
58414b24e2bSVaishali Kulkarni 	/*
58514b24e2bSVaishali Kulkarni 	 * Index number to the register address space  set.
58614b24e2bSVaishali Kulkarni 	 * A  value of 0 indicates PCI configuration space,
58714b24e2bSVaishali Kulkarni 	 * while a value of 1 indicates the real  start  of
58814b24e2bSVaishali Kulkarni 	 * device register sets.
58914b24e2bSVaishali Kulkarni 	 */
59014b24e2bSVaishali Kulkarni 	    1,
59114b24e2bSVaishali Kulkarni 	/*
59214b24e2bSVaishali Kulkarni 	 * A platform-dependent value that, when  added  to
59314b24e2bSVaishali Kulkarni 	 * an  offset that is less than or equal to the len
59414b24e2bSVaishali Kulkarni 	 * parameter (see below), is used for the  dev_addr
59514b24e2bSVaishali Kulkarni 	 * argument   to   the  ddi_get,  ddi_mem_get,  and
59614b24e2bSVaishali Kulkarni 	 * ddi_io_get/put routines.
59714b24e2bSVaishali Kulkarni 	 */
59814b24e2bSVaishali Kulkarni 	    &qede->regview,
59914b24e2bSVaishali Kulkarni 	/*
60014b24e2bSVaishali Kulkarni 	 * Offset into the register address space.
60114b24e2bSVaishali Kulkarni 	 */
60214b24e2bSVaishali Kulkarni 	    0,
60314b24e2bSVaishali Kulkarni 	/* Length to be mapped. */
60414b24e2bSVaishali Kulkarni 	    qede->regview_size,
60514b24e2bSVaishali Kulkarni 	/*
60614b24e2bSVaishali Kulkarni 	 * Pointer to a device access  attribute  structure
60714b24e2bSVaishali Kulkarni 	 * of this mapping.
60814b24e2bSVaishali Kulkarni 	 */
60914b24e2bSVaishali Kulkarni 	    &qede_regs_acc_attr,
61014b24e2bSVaishali Kulkarni 	/* Pointer to a data access handle. */
61114b24e2bSVaishali Kulkarni 	    &qede->regs_handle);
61214b24e2bSVaishali Kulkarni 
61314b24e2bSVaishali Kulkarni 	if (ret != DDI_SUCCESS) {
61414b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "!qede(%d): failed to map registers, err %d",
61514b24e2bSVaishali Kulkarni 		    qede->instance, ret);
61614b24e2bSVaishali Kulkarni 		goto err_exit;
61714b24e2bSVaishali Kulkarni 	}
61814b24e2bSVaishali Kulkarni 
61914b24e2bSVaishali Kulkarni 	qede->pci_bar0_base = (unsigned long)qede->regview;
62014b24e2bSVaishali Kulkarni 
62114b24e2bSVaishali Kulkarni 	/* map doorbell space */
62214b24e2bSVaishali Kulkarni 	ret = ddi_regs_map_setup(qede->dip,
62314b24e2bSVaishali Kulkarni 	    2,
62414b24e2bSVaishali Kulkarni 	    &qede->doorbell,
62514b24e2bSVaishali Kulkarni 	    0,
62614b24e2bSVaishali Kulkarni 	    qede->doorbell_size,
62714b24e2bSVaishali Kulkarni 	    &qede_regs_acc_attr,
62814b24e2bSVaishali Kulkarni 	    &qede->doorbell_handle);
62914b24e2bSVaishali Kulkarni 
63014b24e2bSVaishali Kulkarni 	if (ret != DDI_SUCCESS) {
63114b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "qede%d: failed to map doorbell, err %d",
63214b24e2bSVaishali Kulkarni 		    qede->instance, ret);
63314b24e2bSVaishali Kulkarni 		goto err_exit;
63414b24e2bSVaishali Kulkarni 	}
63514b24e2bSVaishali Kulkarni 
63614b24e2bSVaishali Kulkarni 	qede->pci_bar2_base = (unsigned long)qede->doorbell;
63714b24e2bSVaishali Kulkarni 
63814b24e2bSVaishali Kulkarni 	return (ret);
63914b24e2bSVaishali Kulkarni err_exit:
64014b24e2bSVaishali Kulkarni 	qede_unconfig_pci(qede);
64114b24e2bSVaishali Kulkarni 	return (DDI_FAILURE);
64214b24e2bSVaishali Kulkarni }
64314b24e2bSVaishali Kulkarni 
64414b24e2bSVaishali Kulkarni static uint_t
qede_sp_handler(caddr_t arg1,caddr_t arg2)64514b24e2bSVaishali Kulkarni qede_sp_handler(caddr_t arg1, caddr_t arg2)
64614b24e2bSVaishali Kulkarni {
64714b24e2bSVaishali Kulkarni 	/*LINTED E_BAD_PTR_CAST_ALIGN*/
64814b24e2bSVaishali Kulkarni 	struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)arg1;
64914b24e2bSVaishali Kulkarni 	/* LINTED E_BAD_PTR_CAST_ALIGN */
65014b24e2bSVaishali Kulkarni 	qede_vector_info_t *vect_info = (qede_vector_info_t *)arg2;
65114b24e2bSVaishali Kulkarni 	struct ecore_dev *edev = p_hwfn->p_dev;
65214b24e2bSVaishali Kulkarni 	qede_t *qede = (qede_t *)edev;
65314b24e2bSVaishali Kulkarni 
65414b24e2bSVaishali Kulkarni 	if ((arg1 == NULL) || (arg2 == NULL)) {
65514b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "qede_sp_handler: invalid parameters");
65614b24e2bSVaishali Kulkarni 		/*
65714b24e2bSVaishali Kulkarni 		 * MSIX intr should always
65814b24e2bSVaishali Kulkarni 		 * return DDI_INTR_CLAIMED
65914b24e2bSVaishali Kulkarni 		 */
66014b24e2bSVaishali Kulkarni         	return (DDI_INTR_CLAIMED);
66114b24e2bSVaishali Kulkarni 	}
66214b24e2bSVaishali Kulkarni 
66314b24e2bSVaishali Kulkarni 
66414b24e2bSVaishali Kulkarni 	vect_info->in_isr = B_TRUE;
66514b24e2bSVaishali Kulkarni 
66614b24e2bSVaishali Kulkarni 	atomic_add_64((volatile uint64_t *)&qede->intrFired, 1);
66714b24e2bSVaishali Kulkarni 	qede->intrSbCnt[vect_info->vect_index]++;
66814b24e2bSVaishali Kulkarni 
66914b24e2bSVaishali Kulkarni 
67014b24e2bSVaishali Kulkarni 	ecore_int_sp_dpc((osal_int_ptr_t)p_hwfn);
67114b24e2bSVaishali Kulkarni 
67214b24e2bSVaishali Kulkarni 	vect_info->in_isr = B_FALSE;
67314b24e2bSVaishali Kulkarni 
67414b24e2bSVaishali Kulkarni     	return (DDI_INTR_CLAIMED);
67514b24e2bSVaishali Kulkarni }
67614b24e2bSVaishali Kulkarni 
67714b24e2bSVaishali Kulkarni void
qede_enable_hw_intr(qede_fastpath_t * fp)67814b24e2bSVaishali Kulkarni qede_enable_hw_intr(qede_fastpath_t *fp)
67914b24e2bSVaishali Kulkarni {
68014b24e2bSVaishali Kulkarni 	ecore_sb_ack(fp->sb_info, IGU_INT_ENABLE, 1);
68114b24e2bSVaishali Kulkarni 	ddi_dma_sync(fp->sb_dma_handle, 0, 0, DDI_DMA_SYNC_FORDEV);
68214b24e2bSVaishali Kulkarni }
68314b24e2bSVaishali Kulkarni 
68414b24e2bSVaishali Kulkarni void
qede_disable_hw_intr(qede_fastpath_t * fp)68514b24e2bSVaishali Kulkarni qede_disable_hw_intr(qede_fastpath_t *fp)
68614b24e2bSVaishali Kulkarni {
68714b24e2bSVaishali Kulkarni 	ddi_dma_sync(fp->sb_dma_handle, 0, 0, DDI_DMA_SYNC_FORKERNEL);
68814b24e2bSVaishali Kulkarni 	ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
68914b24e2bSVaishali Kulkarni }
69014b24e2bSVaishali Kulkarni 
69114b24e2bSVaishali Kulkarni 
69214b24e2bSVaishali Kulkarni static uint_t
qede_fp_handler(caddr_t arg1,caddr_t arg2)69314b24e2bSVaishali Kulkarni qede_fp_handler(caddr_t arg1, caddr_t arg2)
69414b24e2bSVaishali Kulkarni {
69514b24e2bSVaishali Kulkarni 	/* LINTED E_BAD_PTR_CAST_ALIGN */
69614b24e2bSVaishali Kulkarni 	qede_vector_info_t *vect_info = (qede_vector_info_t *)arg1;
69714b24e2bSVaishali Kulkarni 	/* LINTED E_BAD_PTR_CAST_ALIGN */
69814b24e2bSVaishali Kulkarni 	qede_t *qede = (qede_t *)arg2;
69914b24e2bSVaishali Kulkarni 	qede_fastpath_t *fp;
70014b24e2bSVaishali Kulkarni 	qede_rx_ring_t *rx_ring;
70114b24e2bSVaishali Kulkarni 	mblk_t *mp;
70214b24e2bSVaishali Kulkarni 	int work_done = 0;
70314b24e2bSVaishali Kulkarni 
70414b24e2bSVaishali Kulkarni 	if ((vect_info == NULL) || (vect_info->fp == NULL)) {
70514b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "qede_fp_handler: invalid parameters");
70614b24e2bSVaishali Kulkarni         	return (DDI_INTR_UNCLAIMED);
70714b24e2bSVaishali Kulkarni 	}
70814b24e2bSVaishali Kulkarni 
70914b24e2bSVaishali Kulkarni 	fp = (qede_fastpath_t *)vect_info->fp;
71014b24e2bSVaishali Kulkarni 	rx_ring = fp->rx_ring;
71114b24e2bSVaishali Kulkarni 
71214b24e2bSVaishali Kulkarni 	mutex_enter(&fp->fp_lock);
71314b24e2bSVaishali Kulkarni 
71414b24e2bSVaishali Kulkarni 	atomic_add_64((volatile uint64_t *)&qede->intrFired, 1);
71514b24e2bSVaishali Kulkarni 	qede->intrSbCnt[vect_info->vect_index]++;
71614b24e2bSVaishali Kulkarni 
71714b24e2bSVaishali Kulkarni 	mutex_enter(&fp->qede->drv_lock);
71814b24e2bSVaishali Kulkarni 	qede_disable_hw_intr(fp);
71914b24e2bSVaishali Kulkarni 	mutex_exit(&fp->qede->drv_lock);
72014b24e2bSVaishali Kulkarni 
72114b24e2bSVaishali Kulkarni 	mp = qede_process_fastpath(fp, QEDE_POLL_ALL,
72214b24e2bSVaishali Kulkarni 	    QEDE_MAX_RX_PKTS_PER_INTR, &work_done);
72314b24e2bSVaishali Kulkarni 
72414b24e2bSVaishali Kulkarni 	if (mp)
72514b24e2bSVaishali Kulkarni #ifndef NO_CROSSBOW
72614b24e2bSVaishali Kulkarni 	{
72714b24e2bSVaishali Kulkarni 		mac_rx_ring(rx_ring->qede->mac_handle,
72814b24e2bSVaishali Kulkarni 		    rx_ring->mac_ring_handle,
72914b24e2bSVaishali Kulkarni 		    mp,
73014b24e2bSVaishali Kulkarni 		    rx_ring->mr_gen_num);
73114b24e2bSVaishali Kulkarni 	}
73214b24e2bSVaishali Kulkarni #else
73314b24e2bSVaishali Kulkarni 	{
73414b24e2bSVaishali Kulkarni 		mac_rx(qede->mac_handle, NULL, mp);
73514b24e2bSVaishali Kulkarni 	}
73614b24e2bSVaishali Kulkarni #endif
73714b24e2bSVaishali Kulkarni        else if (!mp && (work_done == 0)) {
73814b24e2bSVaishali Kulkarni 		qede->intrSbNoChangeCnt[vect_info->vect_index]++;
73914b24e2bSVaishali Kulkarni 	}
74014b24e2bSVaishali Kulkarni 
74114b24e2bSVaishali Kulkarni 
74214b24e2bSVaishali Kulkarni 	mutex_enter(&fp->qede->drv_lock);
74314b24e2bSVaishali Kulkarni 	/*
74414b24e2bSVaishali Kulkarni 	 * The mac layer may disabled interrupts
74514b24e2bSVaishali Kulkarni 	 * in the context of the mac_rx_ring call
74614b24e2bSVaishali Kulkarni 	 * above while readying for poll process.
74714b24e2bSVaishali Kulkarni 	 * In this case we do not want to
74814b24e2bSVaishali Kulkarni 	 * enable them here.
74914b24e2bSVaishali Kulkarni 	 */
75014b24e2bSVaishali Kulkarni 	if (fp->disabled_by_poll == 0) {
75114b24e2bSVaishali Kulkarni 		qede_enable_hw_intr(fp);
75214b24e2bSVaishali Kulkarni 	}
75314b24e2bSVaishali Kulkarni 	mutex_exit(&fp->qede->drv_lock);
75414b24e2bSVaishali Kulkarni 
75514b24e2bSVaishali Kulkarni 	mutex_exit(&fp->fp_lock);
75614b24e2bSVaishali Kulkarni 
75714b24e2bSVaishali Kulkarni 	return (work_done ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
75814b24e2bSVaishali Kulkarni }
75914b24e2bSVaishali Kulkarni 
76014b24e2bSVaishali Kulkarni static int
qede_disable_intr(qede_t * qede,uint32_t index)76114b24e2bSVaishali Kulkarni qede_disable_intr(qede_t *qede, uint32_t index)
76214b24e2bSVaishali Kulkarni {
76314b24e2bSVaishali Kulkarni 	int status;
76414b24e2bSVaishali Kulkarni 	qede_intr_context_t *intr_ctx = &qede->intr_ctx;
76514b24e2bSVaishali Kulkarni 
76614b24e2bSVaishali Kulkarni 	status = ddi_intr_disable(intr_ctx->intr_hdl_array[index]);
76714b24e2bSVaishali Kulkarni 	if (status != DDI_SUCCESS) {
76814b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "qede:%s: Failed ddi_intr_enable with %s"
76914b24e2bSVaishali Kulkarni 		    " for index %d\n",
77014b24e2bSVaishali Kulkarni 		    __func__, qede_get_ddi_fail(status), index);
77114b24e2bSVaishali Kulkarni 		return (status);
77214b24e2bSVaishali Kulkarni 	}
77314b24e2bSVaishali Kulkarni 	atomic_and_32(&intr_ctx->intr_state, ~(1 << index));
77414b24e2bSVaishali Kulkarni 
77514b24e2bSVaishali Kulkarni 	return (status);
77614b24e2bSVaishali Kulkarni }
77714b24e2bSVaishali Kulkarni 
77814b24e2bSVaishali Kulkarni static int
qede_enable_intr(qede_t * qede,int index)77914b24e2bSVaishali Kulkarni qede_enable_intr(qede_t *qede, int index)
78014b24e2bSVaishali Kulkarni {
78114b24e2bSVaishali Kulkarni 	int status = 0;
78214b24e2bSVaishali Kulkarni 
78314b24e2bSVaishali Kulkarni 	qede_intr_context_t *intr_ctx = &qede->intr_ctx;
78414b24e2bSVaishali Kulkarni 
78514b24e2bSVaishali Kulkarni 	status = ddi_intr_enable(intr_ctx->intr_hdl_array[index]);
78614b24e2bSVaishali Kulkarni 
78714b24e2bSVaishali Kulkarni 	if (status != DDI_SUCCESS) {
78814b24e2bSVaishali Kulkarni 		cmn_err(CE_WARN, "qede:%s: Failed ddi_intr_enable with %s"
78914b24e2bSVaishali Kulkarni 		    " for index %d\n",
79014b24e2bSVaishali Kulkarni 		    __func__, qede_get_ddi_fail(status), index);
79114b24e2bSVaishali Kulkarni 		return (status);
79214b24e2bSVaishali Kulkarni 	}
79314b24e2bSVaishali Kulkarni 
79414b24e2bSVaishali Kulkarni 	atomic_or_32(&intr_ctx->intr_state, (1 << index));
79514b24e2bSVaishali Kulkarni 
79614b24e2bSVaishali Kulkarni 	return (status);
79714b24e2bSVaishali Kulkarni }
79814b24e2bSVaishali Kulkarni 
79914b24e2bSVaishali Kulkarni static int
qede_disable_all_fastpath_intrs(qede_t * qede)80014b24e2bSVaishali Kulkarni qede_disable_all_fastpath_intrs(qede_t *qede)
80114b24e2bSVaishali Kulkarni {
80214b24e2bSVaishali Kulkarni 	int i, status;
80314b24e2bSVaishali Kulkarni 
80414b24e2bSVaishali Kulkarni 	for (i =