1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni /**************************************************************************** 37*14b24e2bSVaishali Kulkarni * Name: spad_layout.h 38*14b24e2bSVaishali Kulkarni * 39*14b24e2bSVaishali Kulkarni * Description: Global definitions 40*14b24e2bSVaishali Kulkarni * 41*14b24e2bSVaishali Kulkarni * Created: 01/09/2013 42*14b24e2bSVaishali Kulkarni * 43*14b24e2bSVaishali Kulkarni ****************************************************************************/ 44*14b24e2bSVaishali Kulkarni /* 45*14b24e2bSVaishali Kulkarni * Spad Layout NVM CFG MCP public 46*14b24e2bSVaishali Kulkarni *========================================================================================================== 47*14b24e2bSVaishali Kulkarni * MCP_REG_SCRATCH REG_RD(MISC_REG_GEN_PURP_CR0) REG_RD(MISC_REG_SHARED_MEM_ADDR) 48*14b24e2bSVaishali Kulkarni * +------------------+ +-------------------------+ +-------------------+ 49*14b24e2bSVaishali Kulkarni * | Num Sections(4B)|Currently 4 | Num Sections(4B) | | Num Sections(4B)|Currently 6 50*14b24e2bSVaishali Kulkarni * +------------------+ +-------------------------+ +-------------------+ 51*14b24e2bSVaishali Kulkarni * | Offsize(Trace) |4B -+ +-- | Offset(NVM_CFG1) | | Offsize(drv_mb) | 52*14b24e2bSVaishali Kulkarni * +-| Offsize(NVM_CFG) |4B | | | (Size is fixed) | | Offsize(mfw_mb) | 53*14b24e2bSVaishali Kulkarni *+-|-| Offsize(Public) |4B | +-> +-------------------------+ | Offsize(global) | 54*14b24e2bSVaishali Kulkarni *| | | Offsize(Private) |4B | | | | Offsize(path) | 55*14b24e2bSVaishali Kulkarni *| | +------------------+ <--+ | nvm_cfg1_glob | | Offsize(port) | 56*14b24e2bSVaishali Kulkarni *| | | | +-------------------------+ | Offsize(func) | 57*14b24e2bSVaishali Kulkarni *| | | Trace | | nvm_cfg1_path 0 | +-------------------+ 58*14b24e2bSVaishali Kulkarni *| +>+------------------+ | nvm_cfg1_path 1 | | drv_mb PF0/2/4..|8 Funcs of engine0 59*14b24e2bSVaishali Kulkarni *| | | +-------------------------+ | drv_mb PF1/3/5..|8 Funcs of engine1 60*14b24e2bSVaishali Kulkarni *| | NVM_CFG | | nvm_cfg1_port 0 | +-------------------+ 61*14b24e2bSVaishali Kulkarni *+-> +------------------+ | .... | | mfw_mb PF0/2/4..|8 Funcs of engine0 62*14b24e2bSVaishali Kulkarni * | | | nvm_cfg1_port 3 | | mfw_mb PF1/3/5..|8 Funcs of engine1 63*14b24e2bSVaishali Kulkarni * | Public Data | +-------------------------+ +-------------------+ 64*14b24e2bSVaishali Kulkarni * +------------------+ 8 Funcs of Engine 0| nvm_cfg1_func PF0/2/4/..| | | 65*14b24e2bSVaishali Kulkarni * | | 8 Funcs of Engine 1| nvm_cfg1_func PF1/3/5/..| | public_global | 66*14b24e2bSVaishali Kulkarni * | Private Data | +-------------------------+ +-------------------+ 67*14b24e2bSVaishali Kulkarni * +------------------+ | public_path 0 | 68*14b24e2bSVaishali Kulkarni * | Code | | public_path 1 | 69*14b24e2bSVaishali Kulkarni * | Static Area | +-------------------+ 70*14b24e2bSVaishali Kulkarni * +--- ---+ | public_port 0 | 71*14b24e2bSVaishali Kulkarni * | Code | | .... | 72*14b24e2bSVaishali Kulkarni * | PIM Area | | public_port 3 | 73*14b24e2bSVaishali Kulkarni * +------------------+ +-------------------+ 74*14b24e2bSVaishali Kulkarni * | public_func 0/2/4.|8 Funcs of engine0 75*14b24e2bSVaishali Kulkarni * | public_func 1/3/5.|8 Funcs of engine1 76*14b24e2bSVaishali Kulkarni * +-------------------+ 77*14b24e2bSVaishali Kulkarni */ 78*14b24e2bSVaishali Kulkarni #ifndef SPAD_LAYOUT_H 79*14b24e2bSVaishali Kulkarni #define SPAD_LAYOUT_H 80*14b24e2bSVaishali Kulkarni 81*14b24e2bSVaishali Kulkarni #ifndef MDUMP_PARSE_TOOL 82*14b24e2bSVaishali Kulkarni 83*14b24e2bSVaishali Kulkarni #define PORT_0 0 84*14b24e2bSVaishali Kulkarni #define PORT_1 1 85*14b24e2bSVaishali Kulkarni #define PORT_2 2 86*14b24e2bSVaishali Kulkarni #define PORT_3 3 87*14b24e2bSVaishali Kulkarni 88*14b24e2bSVaishali Kulkarni #include "mcp_public.h" 89*14b24e2bSVaishali Kulkarni #include "mfw_hsi.h" 90*14b24e2bSVaishali Kulkarni #include "nvm_cfg.h" 91*14b24e2bSVaishali Kulkarni 92*14b24e2bSVaishali Kulkarni #ifdef MFW 93*14b24e2bSVaishali Kulkarni #include "mcp_private.h" 94*14b24e2bSVaishali Kulkarni #endif 95*14b24e2bSVaishali Kulkarni 96*14b24e2bSVaishali Kulkarni extern struct spad_layout g_spad; 97*14b24e2bSVaishali Kulkarni 98*14b24e2bSVaishali Kulkarni /* TBD - Consider renaming to MCP_STATIC_SPAD_SIZE, since the real size includes another 64kb */ 99*14b24e2bSVaishali Kulkarni #define MCP_SPAD_SIZE 0x00028000 /* 160 KB */ 100*14b24e2bSVaishali Kulkarni 101*14b24e2bSVaishali Kulkarni #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE)) 102*14b24e2bSVaishali Kulkarni #endif /* MDUMP_PARSE_TOOL */ 103*14b24e2bSVaishali Kulkarni 104*14b24e2bSVaishali Kulkarni #define TO_OFFSIZE(_offset, _size) \ 105*14b24e2bSVaishali Kulkarni (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \ 106*14b24e2bSVaishali Kulkarni (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT)) 107*14b24e2bSVaishali Kulkarni 108*14b24e2bSVaishali Kulkarni enum spad_sections { 109*14b24e2bSVaishali Kulkarni SPAD_SECTION_TRACE, 110*14b24e2bSVaishali Kulkarni SPAD_SECTION_NVM_CFG, 111*14b24e2bSVaishali Kulkarni SPAD_SECTION_PUBLIC, 112*14b24e2bSVaishali Kulkarni SPAD_SECTION_PRIVATE, 113*14b24e2bSVaishali Kulkarni SPAD_SECTION_MAX 114*14b24e2bSVaishali Kulkarni }; 115*14b24e2bSVaishali Kulkarni 116*14b24e2bSVaishali Kulkarni #ifndef MDUMP_PARSE_TOOL 117*14b24e2bSVaishali Kulkarni struct spad_layout { 118*14b24e2bSVaishali Kulkarni struct nvm_cfg nvm_cfg; 119*14b24e2bSVaishali Kulkarni struct mcp_public_data public_data; 120*14b24e2bSVaishali Kulkarni #ifdef MFW /* Drivers will not be compiled with this flag. */ 121*14b24e2bSVaishali Kulkarni /* Linux should remove this appearance at all. */ 122*14b24e2bSVaishali Kulkarni struct mcp_private_data private_data; 123*14b24e2bSVaishali Kulkarni #endif 124*14b24e2bSVaishali Kulkarni }; 125*14b24e2bSVaishali Kulkarni 126*14b24e2bSVaishali Kulkarni #endif /* MDUMP_PARSE_TOOL */ 127*14b24e2bSVaishali Kulkarni 128*14b24e2bSVaishali Kulkarni #define MCP_TRACE_SIZE 2048 /* 2kb */ 129*14b24e2bSVaishali Kulkarni #define STRUCT_OFFSET(f) (STATIC_INIT_BASE + __builtin_offsetof(struct static_init, f)) 130*14b24e2bSVaishali Kulkarni 131*14b24e2bSVaishali Kulkarni /* This section is located at a fixed location in the beginning of the scratchpad, 132*14b24e2bSVaishali Kulkarni * to ensure that the MCP trace is not run over during MFW upgrade. 133*14b24e2bSVaishali Kulkarni * All the rest of data has a floating location which differs from version to version, 134*14b24e2bSVaishali Kulkarni * and is pointed by the mcp_meta_data below. 135*14b24e2bSVaishali Kulkarni * Moreover, the spad_layout section is part of the MFW firmware, and is loaded with it 136*14b24e2bSVaishali Kulkarni * from nvram in order to clear this portion. 137*14b24e2bSVaishali Kulkarni */ 138*14b24e2bSVaishali Kulkarni struct static_init { 139*14b24e2bSVaishali Kulkarni u32 num_sections; /* 0xe20000 */ 140*14b24e2bSVaishali Kulkarni offsize_t sections[SPAD_SECTION_MAX]; /* 0xe20004 */ 141*14b24e2bSVaishali Kulkarni #define SECTION(_sec_) *((offsize_t*)(STRUCT_OFFSET(sections[_sec_]))) 142*14b24e2bSVaishali Kulkarni 143*14b24e2bSVaishali Kulkarni struct mcp_trace trace; /* 0xe20014 */ 144*14b24e2bSVaishali Kulkarni #define MCP_TRACE_P ((struct mcp_trace*)(STRUCT_OFFSET(trace))) 145*14b24e2bSVaishali Kulkarni u8 trace_buffer[MCP_TRACE_SIZE]; /* 0xe20030 */ 146*14b24e2bSVaishali Kulkarni #define MCP_TRACE_BUF ((u8*)(STRUCT_OFFSET(trace_buffer))) 147*14b24e2bSVaishali Kulkarni /* running_mfw has the same definition as in nvm_map.h. 148*14b24e2bSVaishali Kulkarni * This bit indicate both the running dir, and the running bundle. 149*14b24e2bSVaishali Kulkarni * It is set once when the LIM is loaded. 150*14b24e2bSVaishali Kulkarni */ 151*14b24e2bSVaishali Kulkarni u32 running_mfw; /* 0xe20830 */ 152*14b24e2bSVaishali Kulkarni #define RUNNING_MFW *((u32*)(STRUCT_OFFSET(running_mfw))) 153*14b24e2bSVaishali Kulkarni u32 build_time; /* 0xe20834 */ 154*14b24e2bSVaishali Kulkarni #define MFW_BUILD_TIME *((u32*)(STRUCT_OFFSET(build_time))) 155*14b24e2bSVaishali Kulkarni u32 reset_type; /* 0xe20838 */ 156*14b24e2bSVaishali Kulkarni #define RESET_TYPE *((u32*)(STRUCT_OFFSET(reset_type))) 157*14b24e2bSVaishali Kulkarni u32 mfw_secure_mode; /* 0xe2083c */ 158*14b24e2bSVaishali Kulkarni #define MFW_SECURE_MODE *((u32*)(STRUCT_OFFSET(mfw_secure_mode))) 159*14b24e2bSVaishali Kulkarni u16 pme_status_pf_bitmap; /* 0xe20840 */ 160*14b24e2bSVaishali Kulkarni #define PME_STATUS_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_status_pf_bitmap))) 161*14b24e2bSVaishali Kulkarni u16 pme_enable_pf_bitmap; 162*14b24e2bSVaishali Kulkarni #define PME_ENABLE_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_enable_pf_bitmap))) 163*14b24e2bSVaishali Kulkarni u32 mim_nvm_addr; /* 0xe20844 */ 164*14b24e2bSVaishali Kulkarni u32 mim_start_addr; /* 0xe20848 */ 165*14b24e2bSVaishali Kulkarni u32 ah_pcie_link_params; /* 0xe20850 Stores PCIe link configuration at start, so they can be used later also for Hot-Reset, without the need to re-reading them from nvm cfg. */ 166*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff) 167*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0) 168*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00) 169*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8) 170*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000) 171*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16) 172*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000) 173*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24) 174*14b24e2bSVaishali Kulkarni #define AH_PCIE_LINK_PARAMS *((u32*)(STRUCT_OFFSET(ah_pcie_link_params))) 175*14b24e2bSVaishali Kulkarni 176*14b24e2bSVaishali Kulkarni u32 flags; /* 0xe20850 */ 177*14b24e2bSVaishali Kulkarni #define M_GLOB_FLAGS *((u32*)(STRUCT_OFFSET(flags))) 178*14b24e2bSVaishali Kulkarni #define FLAGS_VAUX_REQUIRED (1 << 0) 179*14b24e2bSVaishali Kulkarni #define FLAGS_WAIT_AVS_READY (1 << 1) 180*14b24e2bSVaishali Kulkarni #define FLAGS_FAILURE_ISSUED (1 << 2) 181*14b24e2bSVaishali Kulkarni #define FLAGS_FAILURE_DETECTED (1 << 3) 182*14b24e2bSVaishali Kulkarni #define FLAGS_VAUX (1 << 4) 183*14b24e2bSVaishali Kulkarni #define FLAGS_PERST_ASSERT_OCCURED (1 << 5) 184*14b24e2bSVaishali Kulkarni #define FLAGS_HOT_RESET_STEP2 (1 << 6) 185*14b24e2bSVaishali Kulkarni #define FLAGS_MSIX_SYNC_ALLOWED (1 << 7) 186*14b24e2bSVaishali Kulkarni #define FLAGS_PROGRAM_PCI_COMPLETED (1 << 8) 187*14b24e2bSVaishali Kulkarni #define FLAGS_SMBUS_AUX_MODE (1 << 9) 188*14b24e2bSVaishali Kulkarni #define FLAGS_PEND_SMBUS_VMAIN_TO_AUX (1 << 10) 189*14b24e2bSVaishali Kulkarni #define FLAGS_NVM_CFG_EFUSE_FAILURE (1 << 11) 190*14b24e2bSVaishali Kulkarni #define FLAGS_POWER_TRANSITION (1 << 12) 191*14b24e2bSVaishali Kulkarni #define FLAGS_OS_DRV_LOADED (1 << 29) 192*14b24e2bSVaishali Kulkarni #define FLAGS_OVER_TEMP_OCCUR (1 << 30) 193*14b24e2bSVaishali Kulkarni #define FLAGS_FAN_FAIL_OCCUR (1 << 31) 194*14b24e2bSVaishali Kulkarni u32 rsrv_persist[4]; /* Persist reserved for MFW upgrades */ /* 0xe20854 */ 195*14b24e2bSVaishali Kulkarni 196*14b24e2bSVaishali Kulkarni }; 197*14b24e2bSVaishali Kulkarni 198*14b24e2bSVaishali Kulkarni #ifndef MDUMP_PARSE_TOOL 199*14b24e2bSVaishali Kulkarni #define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x 200*14b24e2bSVaishali Kulkarni #define NVM_GLOB(x) NVM_CFG1(glob).x 201*14b24e2bSVaishali Kulkarni #define NVM_GLOB_VAL(n, m, o) ((NVM_GLOB(n) & m) >> o) 202*14b24e2bSVaishali Kulkarni #endif /* MDUMP_PARSE_TOOL */ 203*14b24e2bSVaishali Kulkarni 204*14b24e2bSVaishali Kulkarni #endif /* SPAD_LAYOUT_H */ 205