xref: /illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/mcp/mcp_public.h (revision 14b24e2b79293068c8e016a69ef1d872fb5e2fd5)
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 /****************************************************************************
37  *
38  * Name:        mcp_public.h
39  *
40  * Description: MCP public data
41  *
42  * Created:     13/01/2013 yanivr
43  *
44  ****************************************************************************/
45 
46 #ifndef MCP_PUBLIC_H
47 #define MCP_PUBLIC_H
48 
49 #define VF_MAX_STATIC 192	/* In case of AH */
50 
51 #define MCP_GLOB_PATH_MAX	2
52 #define MCP_PORT_MAX		2	/* Global */
53 #define MCP_GLOB_PORT_MAX	4	/* Global */
54 #define MCP_GLOB_FUNC_MAX	16	/* Global */
55 
56 typedef u32 offsize_t;      /* In DWORDS !!! */
57 /* Offset from the beginning of the MCP scratchpad */
58 #define OFFSIZE_OFFSET_SHIFT	0
59 #define OFFSIZE_OFFSET_MASK	0x0000ffff
60 /* Size of specific element (not the whole array if any) */
61 #define OFFSIZE_SIZE_SHIFT	16
62 #define OFFSIZE_SIZE_MASK	0xffff0000
63 
64 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
65 #define SECTION_OFFSET(_offsize)	((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2))
66 
67 /* SECTION_SIZE is calculating the size in bytes out of offsize */
68 #define SECTION_SIZE(_offsize)		(((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)
69 
70 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index within section */
71 #define SECTION_ADDR(_offsize, idx) 	(MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
72 
73 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use offsetof, since the OFFSETUP collide with the firmware definition */
74 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
75 /* PHY configuration */
76 struct eth_phy_cfg {
77 	u32 speed;      /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
78 #define ETH_SPEED_AUTONEG   0
79 #define ETH_SPEED_SMARTLINQ  0x8 /* deprecated - use link_modes field instead */
80 
81 	u32 pause;      /* bitmask */
82 #define ETH_PAUSE_NONE		0x0
83 #define ETH_PAUSE_AUTONEG	0x1
84 #define ETH_PAUSE_RX		0x2
85 #define ETH_PAUSE_TX		0x4
86 
87 	u32 adv_speed;      /* Default should be the speed_cap_mask */
88 	u32 loopback_mode;
89 #define ETH_LOOPBACK_NONE		 (0)
90 #define ETH_LOOPBACK_INT_PHY		 (1) /* Serdes loopback. In AH, it refers to Near End */
91 #define ETH_LOOPBACK_EXT_PHY		 (2) /* External PHY Loopback */
92 #define ETH_LOOPBACK_EXT		 (3) /* External Loopback (Require loopback plug) */
93 #define ETH_LOOPBACK_MAC		 (4) /* MAC Loopback - not supported */
94 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123	 (5) /* Port to itself */
95 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301	 (6) /* Port to Port */
96 #define ETH_LOOPBACK_PCS_AH_ONLY	 (7) /* PCS loopback (TX to RX) */
97 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) /* Loop RX packet from PCS to TX */
98 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) /* Remote Serdes Loopback (RX to TX) */
99 
100 	u32 eee_cfg;
101 #define EEE_CFG_EEE_ENABLED	(1<<0)	/* EEE is enabled (configuration). Refer to eee_status->active for negotiated status */
102 #define EEE_CFG_TX_LPI		(1<<1)
103 #define EEE_CFG_ADV_SPEED_1G	(1<<2)
104 #define EEE_CFG_ADV_SPEED_10G	(1<<3)
105 #define EEE_TX_TIMER_USEC_MASK	(0xfffffff0)
106 #define EEE_TX_TIMER_USEC_SHIFT	4
107 #define EEE_TX_TIMER_USEC_BALANCED_TIME		(0xa00)
108 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	(0x100)
109 #define EEE_TX_TIMER_USEC_LATENCY_TIME		(0x6000)
110 
111 	u32 link_modes; /* Additional link modes */
112 #define LINK_MODE_SMARTLINQ_ENABLE		0x1 /* XXX deprecated */
113 };
114 
115 struct port_mf_cfg {
116 
117 	u32 dynamic_cfg;    /* device control channel */
118 #define PORT_MF_CFG_OV_TAG_MASK              0x0000ffff
119 #define PORT_MF_CFG_OV_TAG_SHIFT             0
120 #define PORT_MF_CFG_OV_TAG_DEFAULT         PORT_MF_CFG_OV_TAG_MASK
121 
122 	u32 reserved[1];
123 };
124 
125 /* DO NOT add new fields in the middle
126  * MUST be synced with struct pmm_stats_map
127  */
128 struct eth_stats {
129 	u64 r64;        /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
130 	u64 r127;       /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
131 	u64 r255;       /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
132 	u64 r511;       /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
133 	u64 r1023;      /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
134 	u64 r1518;      /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
135 	union {
136 		struct { /* bb */
137 			u64 r1522;      /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */
138 			u64 r2047;      /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
139 			u64 r4095;      /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
140 			u64 r9216;      /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
141 			u64 r16383;     /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */
142 
143 		} bb0;
144 		struct { /* ah */
145 			u64 unused1;
146 			u64 r1519_to_max; /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/
147 			u64 unused2;
148 			u64 unused3;
149 			u64 unused4;
150 		} ah0;
151 	} u0;
152 	u64 rfcs;       /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
153 	u64 rxcf;       /* 0x10 (Offset 0x60 ) RX control frame counter*/
154 	u64 rxpf;       /* 0x11 (Offset 0x68 ) RX pause frame counter*/
155 	u64 rxpp;       /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
156 	u64 raln;       /* 0x16 (Offset 0x78 ) RX alignment error counter*/
157 	u64 rfcr;       /* 0x19 (Offset 0x80 ) RX false carrier counter */
158 	u64 rovr;       /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
159 	u64 rjbr;       /* 0x1B (Offset 0x90 ) RX jabber frame counter */
160 	u64 rund;       /* 0x34 (Offset 0x98 ) RX undersized frame counter */
161 	u64 rfrg;       /* 0x35 (Offset 0xa0 ) RX fragment counter */
162 	u64 t64;        /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
163 	u64 t127;       /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
164 	u64 t255;       /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
165 	u64 t511;       /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
166 	u64 t1023;      /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
167 	u64 t1518;      /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
168 	union {
169 		struct { /* bb */
170 			u64 t2047;      /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
171 			u64 t4095;      /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
172 			u64 t9216;      /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
173 			u64 t16383;     /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */
174 		} bb1;
175 		struct { /* ah */
176 			u64 t1519_to_max; /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */
177 			u64 unused6;
178 			u64 unused7;
179 			u64 unused8;
180 		} ah1;
181 	} u1;
182 	u64 txpf;       /* 0x50 (Offset 0xf8 ) TX pause frame counter */
183 	u64 txpp;       /* 0x51 (Offset 0x100) TX PFC frame counter */
184 	union {
185 		struct { /* bb */
186 			u64 tlpiec;     /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
187 			u64 tncl;       /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
188 		} bb2;
189 		struct { /* ah */
190 			u64 unused9;
191 			u64 unused10;
192 		} ah2;
193 	} u2;
194 	u64 rbyte;      /* 0x3d (Offset 0x118) RX byte counter */
195 	u64 rxuca;      /* 0x0c (Offset 0x120) RX UC frame counter */
196 	u64 rxmca;      /* 0x0d (Offset 0x128) RX MC frame counter */
197 	u64 rxbca;      /* 0x0e (Offset 0x130) RX BC frame counter */
198 	u64 rxpok;      /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */
199 	u64 tbyte;      /* 0x6f (Offset 0x140) TX byte counter */
200 	u64 txuca;      /* 0x4d (Offset 0x148) TX UC frame counter */
201 	u64 txmca;      /* 0x4e (Offset 0x150) TX MC frame counter */
202 	u64 txbca;      /* 0x4f (Offset 0x158) TX BC frame counter */
203 	u64 txcf;       /* 0x54 (Offset 0x160) TX control frame counter */
204 	/* HSI - Cannot add more stats to this struct. If needed, then need to open new struct */
205 };
206 
207 struct brb_stats {
208 	u64 brb_truncate[8];
209 	u64 brb_discard[8];
210 };
211 
212 struct port_stats {
213 	struct brb_stats brb;
214 	struct eth_stats eth;
215 };
216 
217 /*-----+-----------------------------------------------------------------------------
218  * Chip | Number and       | Ports in| Ports in|2 PHY-s |# of ports|# of engines
219  *      | rate of physical | team #1 | team #2 |are used|per path  | (paths) enabled
220  *      | ports            |         |         |        |          |
221  *======+==================+=========+=========+========+==========+=================
222  * BB   | 1x100G           | This is special mode, where there are actually 2 HW func
223  * BB   | 2x10/20Gbps      | 0,1     | NA      |  No    | 1        | 1
224  * BB   | 2x40 Gbps        | 0,1     | NA      |  Yes   | 1        | 1
225  * BB   | 2x50Gbps         | 0,1     | NA      |  No    | 1        | 1
226  * BB   | 4x10Gbps         | 0,2     | 1,3     |  No    | 1/2      | 1,2 (2 is optional)
227  * BB   | 4x10Gbps         | 0,1     | 2,3     |  No    | 1/2      | 1,2 (2 is optional)
228  * BB   | 4x10Gbps         | 0,3     | 1,2     |  No    | 1/2      | 1,2 (2 is optional)
229  * BB   | 4x10Gbps         | 0,1,2,3 | NA      |  No    | 1        | 1
230  * AH   | 2x10/20Gbps      | 0,1     | NA      |  NA    | 1        | NA
231  * AH   | 4x10Gbps         | 0,1     | 2,3     |  NA    | 2        | NA
232  * AH   | 4x10Gbps         | 0,2     | 1,3     |  NA    | 2        | NA
233  * AH   | 4x10Gbps         | 0,3     | 1,2     |  NA    | 2        | NA
234  * AH   | 4x10Gbps         | 0,1,2,3 | NA      |  NA    | 1        | NA
235  *======+==================+=========+=========+========+==========+===================
236  */
237 
238 #define CMT_TEAM0 0
239 #define CMT_TEAM1 1
240 #define CMT_TEAM_MAX 2
241 
242 struct couple_mode_teaming {
243 	u8 port_cmt[MCP_GLOB_PORT_MAX];
244 #define PORT_CMT_IN_TEAM            (1<<0)
245 
246 #define PORT_CMT_PORT_ROLE          (1<<1)
247 #define PORT_CMT_PORT_INACTIVE      (0<<1)
248 #define PORT_CMT_PORT_ACTIVE        (1<<1)
249 
250 #define PORT_CMT_TEAM_MASK          (1<<2)
251 #define PORT_CMT_TEAM0              (0<<2)
252 #define PORT_CMT_TEAM1              (1<<2)
253 };
254 
255 /**************************************
256  *     LLDP and DCBX HSI structures
257  **************************************/
258 #define LLDP_CHASSIS_ID_STAT_LEN 4
259 #define LLDP_PORT_ID_STAT_LEN 4
260 #define DCBX_MAX_APP_PROTOCOL		32
261 #define MAX_SYSTEM_LLDP_TLV_DATA    32
262 
263 typedef enum _lldp_agent_e {
264 	LLDP_NEAREST_BRIDGE = 0,
265 	LLDP_NEAREST_NON_TPMR_BRIDGE,
266 	LLDP_NEAREST_CUSTOMER_BRIDGE,
267 	LLDP_MAX_LLDP_AGENTS
268 } lldp_agent_e;
269 
270 struct lldp_config_params_s {
271 	u32 config;
272 #define LLDP_CONFIG_TX_INTERVAL_MASK        0x000000ff
273 #define LLDP_CONFIG_TX_INTERVAL_SHIFT       0
274 #define LLDP_CONFIG_HOLD_MASK               0x00000f00
275 #define LLDP_CONFIG_HOLD_SHIFT              8
276 #define LLDP_CONFIG_MAX_CREDIT_MASK         0x0000f000
277 #define LLDP_CONFIG_MAX_CREDIT_SHIFT        12
278 #define LLDP_CONFIG_ENABLE_RX_MASK          0x40000000
279 #define LLDP_CONFIG_ENABLE_RX_SHIFT         30
280 #define LLDP_CONFIG_ENABLE_TX_MASK          0x80000000
281 #define LLDP_CONFIG_ENABLE_TX_SHIFT         31
282 	/* Holds local Chassis ID TLV header, subtype and 9B of payload.
283 	   If firtst byte is 0, then we will use default chassis ID */
284 	u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
285 	/* Holds local Port ID TLV header, subtype and 9B of payload.
286 	   If firtst byte is 0, then we will use default port ID */
287 	u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
288 };
289 
290 struct lldp_status_params_s {
291 	u32 prefix_seq_num;
292 	u32 status; /* TBD */
293 	/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
294 	u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
295 	/* Holds remote Port ID TLV header, subtype and 9B of payload. */
296 	u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
297 	u32 suffix_seq_num;
298 };
299 
300 struct dcbx_ets_feature {
301 	u32 flags;
302 #define DCBX_ETS_ENABLED_MASK                   0x00000001
303 #define DCBX_ETS_ENABLED_SHIFT                  0
304 #define DCBX_ETS_WILLING_MASK                   0x00000002
305 #define DCBX_ETS_WILLING_SHIFT                  1
306 #define DCBX_ETS_ERROR_MASK                     0x00000004
307 #define DCBX_ETS_ERROR_SHIFT                    2
308 #define DCBX_ETS_CBS_MASK                       0x00000008
309 #define DCBX_ETS_CBS_SHIFT                      3
310 #define DCBX_ETS_MAX_TCS_MASK                   0x000000f0
311 #define DCBX_ETS_MAX_TCS_SHIFT                  4
312 #define DCBX_OOO_TC_MASK			0x00000f00
313 #define DCBX_OOO_TC_SHIFT                 	8
314 	/* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
315 	u32  pri_tc_tbl[1];
316 /* Fixed TCP OOO TC usage is deprecated and used only for driver backward compatibility */
317 #define DCBX_TCP_OOO_TC				(4)
318 #define DCBX_TCP_OOO_K2_4PORT_TC		(3)
319 
320 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET		(DCBX_TCP_OOO_TC + 1)
321 #define DCBX_CEE_STRICT_PRIORITY		0xf
322 	/* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
323 	u32  tc_bw_tbl[2];
324 	/* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
325 	u32  tc_tsa_tbl[2];
326 #define DCBX_ETS_TSA_STRICT			0
327 #define DCBX_ETS_TSA_CBS			1
328 #define DCBX_ETS_TSA_ETS			2
329 };
330 
331 struct dcbx_app_priority_entry {
332 	u32 entry;
333 #define DCBX_APP_PRI_MAP_MASK       0x000000ff
334 #define DCBX_APP_PRI_MAP_SHIFT      0
335 #define DCBX_APP_PRI_0              0x01
336 #define DCBX_APP_PRI_1              0x02
337 #define DCBX_APP_PRI_2              0x04
338 #define DCBX_APP_PRI_3              0x08
339 #define DCBX_APP_PRI_4              0x10
340 #define DCBX_APP_PRI_5              0x20
341 #define DCBX_APP_PRI_6              0x40
342 #define DCBX_APP_PRI_7              0x80
343 #define DCBX_APP_SF_MASK            0x00000300
344 #define DCBX_APP_SF_SHIFT           8
345 #define DCBX_APP_SF_ETHTYPE         0
346 #define DCBX_APP_SF_PORT            1
347 #define DCBX_APP_SF_IEEE_MASK       0x0000f000
348 #define DCBX_APP_SF_IEEE_SHIFT      12
349 #define DCBX_APP_SF_IEEE_RESERVED   0
350 #define DCBX_APP_SF_IEEE_ETHTYPE    1
351 #define DCBX_APP_SF_IEEE_TCP_PORT   2
352 #define DCBX_APP_SF_IEEE_UDP_PORT   3
353 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
354 
355 #define DCBX_APP_PROTOCOL_ID_MASK   0xffff0000
356 #define DCBX_APP_PROTOCOL_ID_SHIFT  16
357 };
358 
359 
360 /* FW structure in BE */
361 struct dcbx_app_priority_feature {
362 	u32 flags;
363 #define DCBX_APP_ENABLED_MASK           0x00000001
364 #define DCBX_APP_ENABLED_SHIFT          0
365 #define DCBX_APP_WILLING_MASK           0x00000002
366 #define DCBX_APP_WILLING_SHIFT          1
367 #define DCBX_APP_ERROR_MASK             0x00000004
368 #define DCBX_APP_ERROR_SHIFT            2
369 	/* Not in use
370 	#define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00
371 	#define DCBX_APP_DEFAULT_PRI_SHIFT      8
372 	*/
373 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
374 #define DCBX_APP_MAX_TCS_SHIFT          12
375 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
376 #define DCBX_APP_NUM_ENTRIES_SHIFT      16
377 	struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
378 };
379 
380 /* FW structure in BE */
381 struct dcbx_features {
382 	/* PG feature */
383 	struct dcbx_ets_feature ets;
384 	/* PFC feature */
385 	u32 pfc;
386 #define DCBX_PFC_PRI_EN_BITMAP_MASK             0x000000ff
387 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT            0
388 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0            0x01
389 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1            0x02
390 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2            0x04
391 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3            0x08
392 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4            0x10
393 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5            0x20
394 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6            0x40
395 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7            0x80
396 
397 #define DCBX_PFC_FLAGS_MASK                     0x0000ff00
398 #define DCBX_PFC_FLAGS_SHIFT                    8
399 #define DCBX_PFC_CAPS_MASK                      0x00000f00
400 #define DCBX_PFC_CAPS_SHIFT                     8
401 #define DCBX_PFC_MBC_MASK                       0x00004000
402 #define DCBX_PFC_MBC_SHIFT                      14
403 #define DCBX_PFC_WILLING_MASK                   0x00008000
404 #define DCBX_PFC_WILLING_SHIFT                  15
405 #define DCBX_PFC_ENABLED_MASK                   0x00010000
406 #define DCBX_PFC_ENABLED_SHIFT                  16
407 #define DCBX_PFC_ERROR_MASK                     0x00020000
408 #define DCBX_PFC_ERROR_SHIFT                    17
409 
410 	/* APP feature */
411 	struct dcbx_app_priority_feature app;
412 };
413 
414 struct dcbx_local_params {
415 	u32 config;
416 #define DCBX_CONFIG_VERSION_MASK            0x00000007
417 #define DCBX_CONFIG_VERSION_SHIFT           0
418 #define DCBX_CONFIG_VERSION_DISABLED        0
419 #define DCBX_CONFIG_VERSION_IEEE            1
420 #define DCBX_CONFIG_VERSION_CEE             2
421 #define DCBX_CONFIG_VERSION_STATIC          4
422 
423 	u32 flags;
424 	struct dcbx_features features;
425 };
426 
427 struct dcbx_mib {
428 	u32 prefix_seq_num;
429 	u32 flags;
430 	/*
431 	#define DCBX_CONFIG_VERSION_MASK            0x00000007
432 	#define DCBX_CONFIG_VERSION_SHIFT           0
433 	#define DCBX_CONFIG_VERSION_DISABLED        0
434 	#define DCBX_CONFIG_VERSION_IEEE            1
435 	#define DCBX_CONFIG_VERSION_CEE             2
436 	#define DCBX_CONFIG_VERSION_STATIC          4
437 	*/
438 	struct dcbx_features features;
439 	u32 suffix_seq_num;
440 };
441 
442 struct lldp_system_tlvs_buffer_s {
443 	u16 valid;
444 	u16 length;
445 	u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
446 };
447 
448 struct dcb_dscp_map {
449 	u32 flags;
450 #define DCB_DSCP_ENABLE_MASK			0x1
451 #define DCB_DSCP_ENABLE_SHIFT			0
452 #define DCB_DSCP_ENABLE				1
453 	u32 dscp_pri_map[8];
454 	/* the map structure is the following:
455 	   each u32 is split into 4 bits chunks, each chunk holds priority for respective dscp
456 	   Lowest dscp is at lsb
457 			    31          28          24          20          16          12          8           4           0
458 	   dscp_pri_map[0]: | dscp7 pri | dscp6 pri | dscp5 pri | dscp4 pri | dscp3 pri | dscp2 pri | dscp1 pri | dscp0 pri |
459 	   dscp_pri_map[1]: | dscp15 pri| dscp14 pri| dscp13 pri| dscp12 pri| dscp11 pri| dscp10 pri| dscp9 pri | dscp8 pri |
460 	   etc.*/
461 };
462 
463 /**************************************/
464 /*                                    */
465 /*     P U B L I C      G L O B A L   */
466 /*                                    */
467 /**************************************/
468 struct public_global {
469 	u32 max_path;       /* 32bit is wasty, but this will be used often */
470 	u32 max_ports;      /* (Global) 32bit is wasty, but this will be used often */
471 #define MODE_1P	1		/* TBD - NEED TO THINK OF A BETTER NAME */
472 #define MODE_2P	2
473 #define MODE_3P	3
474 #define MODE_4P	4
475 	u32 debug_mb_offset;
476 	u32 phymod_dbg_mb_offset;
477 	struct couple_mode_teaming cmt;
478 	s32 internal_temperature; /* Temperature in Celcius (-255C / +255C), measured every second. */
479 	u32 mfw_ver;
480 	u32 running_bundle_id;
481 	s32 external_temperature;
482 	u32 mdump_reason;
483 #define MDUMP_REASON_INTERNAL_ERROR	(1 << 0)
484 #define MDUMP_REASON_EXTERNAL_TRIGGER	(1 << 1)
485 #define MDUMP_REASON_DUMP_AGED		(1 << 2)
486 	u32 ext_phy_upgrade_fw;
487 #define EXT_PHY_FW_UPGRADE_STATUS_MASK		(0x0000ffff)
488 #define EXT_PHY_FW_UPGRADE_STATUS_SHIFT		(0)
489 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS	(1)
490 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED	(2)
491 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS	(3)
492 #define EXT_PHY_FW_UPGRADE_TYPE_MASK		(0xffff0000)
493 #define EXT_PHY_FW_UPGRADE_TYPE_SHIFT		(16)
494 
495 	u8 runtime_port_swap_map[MODE_4P];
496 	u32 data_ptr;
497 	u32 data_size;
498 };
499 
500 /**************************************/
501 /*                                    */
502 /*     P U B L I C      P A T H       */
503 /*                                    */
504 /**************************************/
505 
506 /****************************************************************************
507  * Shared Memory 2 Region                                                   *
508  ****************************************************************************/
509 /* The fw_flr_ack is actually built in the following way:                   */
510 /* 8 bit:  PF ack                                                           */
511 /* 128 bit: VF ack                                                           */
512 /* 8 bit:  ios_dis_ack                                                      */
513 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
514 /* u32. The fw must have the VF right after the PF since this is how it     */
515 /* access arrays(it expects always the VF to reside after the PF, and that  */
516 /* makes the calculation much easier for it. )                              */
517 /* In order to answer both limitations, and keep the struct small, the code */
518 /* will abuse the structure defined here to achieve the actual partition    */
519 /* above                                                                    */
520 /****************************************************************************/
521 struct fw_flr_mb {
522 	u32 aggint;
523 	u32 opgen_addr;
524 	u32 accum_ack;      /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
525 #define ACCUM_ACK_PF_BASE	0
526 #define ACCUM_ACK_PF_SHIFT	0
527 
528 #define ACCUM_ACK_VF_BASE	8
529 #define ACCUM_ACK_VF_SHIFT	3
530 
531 #define ACCUM_ACK_IOV_DIS_BASE	256
532 #define ACCUM_ACK_IOV_DIS_SHIFT	8
533 
534 };
535 
536 struct public_path {
537 	struct fw_flr_mb flr_mb;
538 	/*
539 	 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
540 	 * which were disabled/flred
541 	 */
542 	u32 mcp_vf_disabled[VF_MAX_STATIC / 32];    /* 0x003c */
543 
544 	u32 process_kill; /* Reset on mcp reset, and incremented for eveny process kill event. */
545 #define PROCESS_KILL_COUNTER_MASK		0x0000ffff
546 #define PROCESS_KILL_COUNTER_SHIFT		0
547 #define PROCESS_KILL_GLOB_AEU_BIT_MASK		0xffff0000
548 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT		16
549 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id*32 + aeu_bit)
550 };
551 
552 /**************************************/
553 /*                                    */
554 /*     P U B L I C      P O R T       */
555 /*                                    */
556 /**************************************/
557 #define FC_NPIV_WWPN_SIZE 8
558 #define FC_NPIV_WWNN_SIZE 8
559 struct dci_npiv_settings {
560 	u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
561 	u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
562 };
563 
564 struct dci_fc_npiv_cfg {
565 	/* hdr used internally by the MFW */
566 	u32 hdr;
567 	u32 num_of_npiv;
568 };
569 
570 #define MAX_NUMBER_NPIV 64
571 struct dci_fc_npiv_tbl {
572 	struct dci_fc_npiv_cfg fc_npiv_cfg;
573 	struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
574 };
575 
576 /****************************************************************************
577  * Driver <-> FW Mailbox                                                    *
578  ****************************************************************************/
579 
580 struct public_port {
581 	u32 validity_map;   /* 0x0 (4*2 = 0x8) */
582 
583 	/* validity bits */
584 #define MCP_VALIDITY_PCI_CFG                    0x00100000
585 #define MCP_VALIDITY_MB                         0x00200000
586 #define MCP_VALIDITY_DEV_INFO                   0x00400000
587 #define MCP_VALIDITY_RESERVED                   0x00000007
588 
589 	/* One licensing bit should be set */
590 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038	/* yaniv - tbd ? license */
591 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
592 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
593 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
594 
595 	/* Active MFW */
596 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
597 #define MCP_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
598 #define MCP_VALIDITY_ACTIVE_MFW_NCSI            0x00000040
599 #define MCP_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
600 
601 	u32 link_status;
602 #define LINK_STATUS_LINK_UP				0x00000001
603 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001e
604 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD		(1<<1)
605 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(2<<1)
606 #define LINK_STATUS_SPEED_AND_DUPLEX_10G		(3<<1)
607 #define LINK_STATUS_SPEED_AND_DUPLEX_20G		(4<<1)
608 #define LINK_STATUS_SPEED_AND_DUPLEX_40G		(5<<1)
609 #define LINK_STATUS_SPEED_AND_DUPLEX_50G		(6<<1)
610 #define LINK_STATUS_SPEED_AND_DUPLEX_100G		(7<<1)
611 #define LINK_STATUS_SPEED_AND_DUPLEX_25G		(8<<1)
612 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
613 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
614 #define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
615 #define LINK_STATUS_PFC_ENABLED				0x00000100
616 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
617 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
618 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE		0x00000800
619 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE		0x00001000
620 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE		0x00002000
621 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE		0x00004000
622 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE		0x00008000
623 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE		0x00010000
624 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
625 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0<<18)
626 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1<<18)
627 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2<<18)
628 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3<<18)
629 #define LINK_STATUS_SFP_TX_FAULT			0x00100000
630 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00200000
631 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00400000
632 #define LINK_STATUS_RX_SIGNAL_PRESENT			0x00800000
633 #define LINK_STATUS_MAC_LOCAL_FAULT			0x01000000
634 #define LINK_STATUS_MAC_REMOTE_FAULT			0x02000000
635 #define LINK_STATUS_UNSUPPORTED_SPD_REQ			0x04000000
636 #define LINK_STATUS_FEC_MODE_MASK			0x38000000
637 #define LINK_STATUS_FEC_MODE_NONE			(0<<27)
638 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74		(1<<27)
639 #define LINK_STATUS_FEC_MODE_RS_CL91			(2<<27)
640 #define LINK_STATUS_EXT_PHY_LINK_UP			0x40000000
641 
642 	u32 link_status1;
643 	u32 ext_phy_fw_version;
644 	u32 drv_phy_cfg_addr;   /* Points to struct eth_phy_cfg (For READ-ONLY) */
645 
646 	u32 port_stx;
647 
648 	u32 stat_nig_timer;
649 
650 	struct port_mf_cfg port_mf_config;
651 	struct port_stats stats;
652 
653 	u32 media_type;
654 #define	MEDIA_UNSPECIFIED		0x0
655 #define	MEDIA_SFPP_10G_FIBER	0x1	/* Use MEDIA_MODULE_FIBER instead */
656 #define	MEDIA_XFP_FIBER			0x2	/* Use MEDIA_MODULE_FIBER instead */
657 #define	MEDIA_DA_TWINAX			0x3
658 #define	MEDIA_BASE_T			0x4
659 #define MEDIA_SFP_1G_FIBER		0x5	/* Use MEDIA_MODULE_FIBER instead */
660 #define MEDIA_MODULE_FIBER		0x6
661 #define	MEDIA_KR				0xf0
662 #define	MEDIA_NOT_PRESENT		0xff
663 
664 	u32 lfa_status;
665 #define LFA_LINK_FLAP_REASON_OFFSET		0
666 #define LFA_LINK_FLAP_REASON_MASK		0x000000ff
667 #define LFA_NO_REASON					(0<<0)
668 #define LFA_LINK_DOWN					(1<<0)
669 #define LFA_FORCE_INIT					(1<<1)
670 #define LFA_LOOPBACK_MISMATCH				(1<<2)
671 #define LFA_SPEED_MISMATCH				(1<<3)
672 #define LFA_FLOW_CTRL_MISMATCH				(1<<4)
673 #define LFA_ADV_SPEED_MISMATCH				(1<<5)
674 #define LFA_EEE_MISMATCH				(1<<6)
675 #define LFA_LINK_MODES_MISMATCH			(1<<7)
676 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET	8
677 #define LINK_FLAP_AVOIDANCE_COUNT_MASK		0x0000ff00
678 #define LINK_FLAP_COUNT_OFFSET			16
679 #define LINK_FLAP_COUNT_MASK			0x00ff0000
680 
681 	u32 link_change_count;
682 
683 	/* LLDP params */
684 	struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];  // offset: 536 bytes?
685 	struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
686 	struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
687 
688 	/* DCBX related MIB */
689 	struct dcbx_local_params local_admin_dcbx_mib;
690 	struct dcbx_mib remote_dcbx_mib;
691 	struct dcbx_mib operational_dcbx_mib;
692 
693 	/* FC_NPIV table offset & size in NVRAM value of 0 means not present */
694 	u32 fc_npiv_nvram_tbl_addr;
695 #define NPIV_TBL_INVALID_ADDR			0xFFFFFFFF
696 
697 	u32 fc_npiv_nvram_tbl_size;
698 	u32 transceiver_data;
699 #define ETH_TRANSCEIVER_STATE_MASK	      	0x000000FF
700 #define ETH_TRANSCEIVER_STATE_SHIFT	      	0x0
701 #define ETH_TRANSCEIVER_STATE_UNPLUGGED			0x00
702 #define ETH_TRANSCEIVER_STATE_PRESENT			0x01
703 #define ETH_TRANSCEIVER_STATE_VALID			0x03
704 #define ETH_TRANSCEIVER_STATE_UPDATING			0x08
705 #define ETH_TRANSCEIVER_TYPE_MASK		0x0000FF00
706 #define ETH_TRANSCEIVER_TYPE_SHIFT		0x8
707 #define ETH_TRANSCEIVER_TYPE_NONE			0x00
708 #define ETH_TRANSCEIVER_TYPE_UNKNOWN			0xFF
709 #define ETH_TRANSCEIVER_TYPE_1G_PCC			0x01 /* 1G Passive copper cable */
710 #define ETH_TRANSCEIVER_TYPE_1G_ACC			0x02 /* 1G Active copper cable  */
711 #define ETH_TRANSCEIVER_TYPE_1G_LX			0x03
712 #define ETH_TRANSCEIVER_TYPE_1G_SX			0x04
713 #define ETH_TRANSCEIVER_TYPE_10G_SR			0x05
714 #define ETH_TRANSCEIVER_TYPE_10G_LR			0x06
715 #define ETH_TRANSCEIVER_TYPE_10G_LRM			0x07
716 #define ETH_TRANSCEIVER_TYPE_10G_ER			0x08
717 #define ETH_TRANSCEIVER_TYPE_10G_PCC			0x09 /* 10G Passive copper cable */
718 #define ETH_TRANSCEIVER_TYPE_10G_ACC			0x0a /* 10G Active copper cable  */
719 #define ETH_TRANSCEIVER_TYPE_XLPPI			0x0b
720 #define ETH_TRANSCEIVER_TYPE_40G_LR4			0x0c
721 #define ETH_TRANSCEIVER_TYPE_40G_SR4			0x0d
722 #define ETH_TRANSCEIVER_TYPE_40G_CR4			0x0e
723 #define ETH_TRANSCEIVER_TYPE_100G_AOC			0x0f /* Active optical cable */
724 #define ETH_TRANSCEIVER_TYPE_100G_SR4			0x10
725 #define ETH_TRANSCEIVER_TYPE_100G_LR4			0x11
726 #define ETH_TRANSCEIVER_TYPE_100G_ER4			0x12
727 #define ETH_TRANSCEIVER_TYPE_100G_ACC			0x13 /* Active copper cable */
728 #define ETH_TRANSCEIVER_TYPE_100G_CR4			0x14
729 #define ETH_TRANSCEIVER_TYPE_4x10G_SR			0x15
730 #define ETH_TRANSCEIVER_TYPE_25G_CA_N			0x16 /* 25G Passive copper cable - short */
731 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S			0x17 /* 25G Active copper cable  - short */
732 #define ETH_TRANSCEIVER_TYPE_25G_CA_S			0x18 /* 25G Passive copper cable - medium */
733 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M			0x19 /* 25G Active copper cable  - medium */
734 #define ETH_TRANSCEIVER_TYPE_25G_CA_L			0x1a /* 25G Passive copper cable - long */
735 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L			0x1b /* 25G Active copper cable  - long */
736 #define ETH_TRANSCEIVER_TYPE_25G_SR			0x1c
737 #define ETH_TRANSCEIVER_TYPE_25G_LR			0x1d
738 #define ETH_TRANSCEIVER_TYPE_25G_AOC			0x1e
739 #define ETH_TRANSCEIVER_TYPE_4x10G			0x1f
740 #define ETH_TRANSCEIVER_TYPE_4x25G_CR			0x20
741 #define ETH_TRANSCEIVER_TYPE_1000BASET			0x21
742 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR	0x30
743 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR	0x31
744 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR	0x32
745 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR	0x33
746 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR	0x34
747 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR	0x35
748 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC	0x36
749 	u32 wol_info;
750 	u32 wol_pkt_len;
751 	u32 wol_pkt_details;
752 	struct dcb_dscp_map dcb_dscp_map;
753 
754 	u32 eee_status;
755 #define EEE_ACTIVE_BIT		(1<<0)		/* Set when EEE negotiation is complete. */
756 
757 #define EEE_LD_ADV_STATUS_MASK	0x000000f0	/* Shows the Local Device EEE capabilities */
758 #define EEE_LD_ADV_STATUS_SHIFT	4
759 	#define EEE_1G_ADV	(1<<1)
760 	#define EEE_10G_ADV	(1<<2)
761 #define	EEE_LP_ADV_STATUS_MASK	0x00000f00      /* Same values as in EEE_LD_ADV, but for Link Parter */
762 #define EEE_LP_ADV_STATUS_SHIFT	8
763 
764 	u32 eee_remote;	/* Used for EEE in LLDP */
765 #define EEE_REMOTE_TW_TX_MASK	0x0000ffff
766 #define EEE_REMOTE_TW_TX_SHIFT	0
767 #define EEE_REMOTE_TW_RX_MASK	0xffff0000
768 #define EEE_REMOTE_TW_RX_SHIFT	16
769 
770 	u32 module_info;
771 #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK		0x000000FF
772 #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET		0
773 #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED		(1 << 2)
774 #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE		(1 << 3)
775 #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED		(1 << 4)
776 #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED		(1 << 5)
777 #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC			(1 << 6)
778 #define ETH_TRANSCEIVER_IDENT_MASK			0x0000ff00
779 #define ETH_TRANSCEIVER_IDENT_OFFSET			8
780 };
781 
782 /**************************************/
783 /*                                    */
784 /*     P U B L I C      F U N C       */
785 /*                                    */
786 /**************************************/
787 
788 struct public_func {
789 
790 	u32 iscsi_boot_signature;
791 	u32 iscsi_boot_block_offset;
792 
793 	/* MTU size per funciton is needed for the OV feature */
794 	u32 mtu_size;
795 	/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
796 	/* For PCP values 0-3 use the map lower */
797 	/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
798 	 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
799 	 */
800 	u32 c2s_pcp_map_lower;
801 	/* For PCP values 4-7 use the map upper */
802 	/* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
803 	 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
804 	*/
805 	u32 c2s_pcp_map_upper;
806 
807 	/* For PCP default value get the MSB byte of the map default */
808 	u32 c2s_pcp_map_default;
809 
810 	u32 reserved[4];
811 
812 	// replace old mf_cfg
813 	u32 config;
814 	/* E/R/I/D */
815 	/* function 0 of each port cannot be hidden */
816 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
817 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
818 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001
819 
820 
821 #define FUNC_MF_CFG_PROTOCOL_MASK               0x000000f0
822 #define FUNC_MF_CFG_PROTOCOL_SHIFT              4
823 #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000000
824 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
825 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
826 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
827 #define FUNC_MF_CFG_PROTOCOL_MAX                0x00000030
828 
829 	/* MINBW, MAXBW */
830 	/* value range - 0..100, increments in 1 %  */
831 #define FUNC_MF_CFG_MIN_BW_MASK                 0x0000ff00
832 #define FUNC_MF_CFG_MIN_BW_SHIFT                8
833 #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
834 #define FUNC_MF_CFG_MAX_BW_MASK                 0x00ff0000
835 #define FUNC_MF_CFG_MAX_BW_SHIFT                16
836 #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x00640000
837 
838 	/*RDMA PROTOCL*/
839 #define FUNC_MF_CFG_RDMA_PROTOCOL_MASK          0x03000000
840 #define FUNC_MF_CFG_RDMA_PROTOCOL_SHIFT         24
841 #define FUNC_MF_CFG_RDMA_PROTOCOL_NONE         	0x00000000
842 #define FUNC_MF_CFG_RDMA_PROTOCOL_ROCE          0x01000000
843 #define FUNC_MF_CFG_RDMA_PROTOCOL_IWARP         0x02000000
844 	/*for future support*/
845 #define FUNC_MF_CFG_RDMA_PROTOCOL_BOTH          0x03000000
846 
847 #define FUNC_MF_CFG_BOOT_MODE_MASK		0x0C000000
848 #define FUNC_MF_CFG_BOOT_MODE_SHIFT		26
849 #define FUNC_MF_CFG_BOOT_MODE_BIOS_CTRL		0x00000000
850 #define FUNC_MF_CFG_BOOT_MODE_DISABLED		0x04000000
851 #define FUNC_MF_CFG_BOOT_MODE_ENABLED		0x08000000
852 
853 	u32 status;
854 #define FUNC_STATUS_VLINK_DOWN  		0x00000001
855 
856 	u32 mac_upper;      /* MAC */
857 #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
858 #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
859 #define FUNC_MF_CFG_UPPERMAC_DEFAULT            FUNC_MF_CFG_UPPERMAC_MASK
860 	u32 mac_lower;
861 #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
862 
863 	u32 fcoe_wwn_port_name_upper;
864 	u32 fcoe_wwn_port_name_lower;
865 
866 	u32 fcoe_wwn_node_name_upper;
867 	u32 fcoe_wwn_node_name_lower;
868 
869 	u32 ovlan_stag;     /* tags */
870 #define FUNC_MF_CFG_OV_STAG_MASK              0x0000ffff
871 #define FUNC_MF_CFG_OV_STAG_SHIFT             0
872 #define FUNC_MF_CFG_OV_STAG_DEFAULT           FUNC_MF_CFG_OV_STAG_MASK
873 
874 	u32 pf_allocation; /* vf per pf */
875 
876 	u32 preserve_data; /* Will be used bt CCM */
877 
878 	u32 driver_last_activity_ts;
879 
880 	/*
881 	 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
882 	 * VFs
883 	 */
884 	u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];    /* 0x0044 */
885 
886 	u32 drv_id;
887 #define DRV_ID_PDA_COMP_VER_MASK	0x0000ffff
888 #define DRV_ID_PDA_COMP_VER_SHIFT	0
889 
890 #define LOAD_REQ_HSI_VERSION		2
891 #define DRV_ID_MCP_HSI_VER_MASK		0x00ff0000
892 #define DRV_ID_MCP_HSI_VER_SHIFT	16
893 #define DRV_ID_MCP_HSI_VER_CURRENT	(LOAD_REQ_HSI_VERSION << DRV_ID_MCP_HSI_VER_SHIFT)
894 
895 #define DRV_ID_DRV_TYPE_MASK		0x7f000000
896 #define DRV_ID_DRV_TYPE_SHIFT		24
897 #define DRV_ID_DRV_TYPE_UNKNOWN		(0 << DRV_ID_DRV_TYPE_SHIFT)
898 #define DRV_ID_DRV_TYPE_LINUX		(1 << DRV_ID_DRV_TYPE_SHIFT)
899 #define DRV_ID_DRV_TYPE_WINDOWS		(2 << DRV_ID_DRV_TYPE_SHIFT)
900 #define DRV_ID_DRV_TYPE_DIAG		(3 << DRV_ID_DRV_TYPE_SHIFT)
901 #define DRV_ID_DRV_TYPE_PREBOOT		(4 << DRV_ID_DRV_TYPE_SHIFT)
902 #define DRV_ID_DRV_TYPE_SOLARIS		(5 << DRV_ID_DRV_TYPE_SHIFT)
903 #define DRV_ID_DRV_TYPE_VMWARE		(6 << DRV_ID_DRV_TYPE_SHIFT)
904 #define DRV_ID_DRV_TYPE_FREEBSD		(7 << DRV_ID_DRV_TYPE_SHIFT)
905 #define DRV_ID_DRV_TYPE_AIX		(8 << DRV_ID_DRV_TYPE_SHIFT)
906 
907 #define DRV_ID_DRV_TYPE_OS 			(DRV_ID_DRV_TYPE_LINUX | DRV_ID_DRV_TYPE_WINDOWS | \
908 									 DRV_ID_DRV_TYPE_SOLARIS | DRV_ID_DRV_TYPE_VMWARE | \
909 									 DRV_ID_DRV_TYPE_FREEBSD | DRV_ID_DRV_TYPE_AIX)
910 
911 #define DRV_ID_DRV_INIT_HW_MASK		0x80000000
912 #define DRV_ID_DRV_INIT_HW_SHIFT	31
913 #define DRV_ID_DRV_INIT_HW_FLAG		(1 << DRV_ID_DRV_INIT_HW_SHIFT)
914 };
915 
916 /**************************************/
917 /*                                    */
918 /*     P U B L I C       M B          */
919 /*                                    */
920 /**************************************/
921 /* This is the only section that the driver can write to, and each */
922 /* Basically each driver request to set feature parameters,
923  * will be done using a different command, which will be linked
924  * to a specific data structure from the union below.
925  * For huge strucuture, the common blank structure should be used.
926  */
927 
928 struct mcp_mac {
929 	u32 mac_upper;      /* Upper 16 bits are always zeroes */
930 	u32 mac_lower;
931 };
932 
933 struct mcp_val64 {
934 	u32 lo;
935 	u32 hi;
936 };
937 
938 struct mcp_file_att {
939 	u32 nvm_start_addr;
940 	u32 len;
941 };
942 
943 struct bist_nvm_image_att {
944 	u32 return_code;
945 	u32 image_type;		/* Image type */
946 	u32 nvm_start_addr;	/* NVM address of the image */
947 	u32 len;		/* Include CRC */
948 };
949 
950 #define MCP_DRV_VER_STR_SIZE 16
951 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
952 #define MCP_DRV_NVM_BUF_LEN 32
953 struct drv_version_stc {
954 	u32 version;
955 	u8 name[MCP_DRV_VER_STR_SIZE - 4];
956 };
957 
958 /* statistics for ncsi */
959 struct lan_stats_stc {
960 	u64 ucast_rx_pkts;
961 	u64 ucast_tx_pkts;
962 	u32 fcs_err;
963 	u32 rserved;
964 };
965 
966 struct fcoe_stats_stc {
967 	u64 rx_pkts;
968 	u64 tx_pkts;
969 	u32 fcs_err;
970 	u32 login_failure;
971 };
972 
973 struct iscsi_stats_stc {
974 	u64 rx_pdus;
975 	u64 tx_pdus;
976 	u64 rx_bytes;
977 	u64 tx_bytes;
978 };
979 
980 struct rdma_stats_stc {
981 	u64 rx_pkts;
982 	u64 tx_pkts;
983 	u64 rx_bytes;
984 	u64 tx_bytes;
985 };
986 
987 struct ocbb_data_stc {
988 	u32 ocbb_host_addr;
989 	u32 ocsd_host_addr;
990 	u32 ocsd_req_update_interval;
991 };
992 
993 #define MAX_NUM_OF_SENSORS			7
994 #define MFW_SENSOR_LOCATION_INTERNAL		1
995 #define MFW_SENSOR_LOCATION_EXTERNAL		2
996 #define MFW_SENSOR_LOCATION_SFP			3
997 
998 #define SENSOR_LOCATION_SHIFT			0
999 #define SENSOR_LOCATION_MASK			0x000000ff
1000 #define THRESHOLD_HIGH_SHIFT			8
1001 #define THRESHOLD_HIGH_MASK			0x0000ff00
1002 #define CRITICAL_TEMPERATURE_SHIFT		16
1003 #define CRITICAL_TEMPERATURE_MASK		0x00ff0000
1004 #define CURRENT_TEMP_SHIFT			24
1005 #define CURRENT_TEMP_MASK			0xff000000
1006 struct temperature_status_stc {
1007 	u32 num_of_sensors;
1008 	u32 sensor[MAX_NUM_OF_SENSORS];
1009 };
1010 
1011 /* crash dump configuration header */
1012 struct mdump_config_stc {
1013 	u32 version;
1014 	u32 config;
1015 	u32 epoc;
1016 	u32 num_of_logs;
1017 	u32 valid_logs;
1018 };
1019 
1020 enum resource_id_enum {
1021 	RESOURCE_NUM_SB_E		=	0,
1022 	RESOURCE_NUM_L2_QUEUE_E		=	1,
1023 	RESOURCE_NUM_VPORT_E		=	2,
1024 	RESOURCE_NUM_VMQ_E		=	3,
1025 	RESOURCE_FACTOR_NUM_RSS_PF_E	=	4,  /* Not a real resource!! it's a factor used to calculate others */
1026 	RESOURCE_FACTOR_RSS_PER_VF_E	=	5,  /* Not a real resource!! it's a factor used to calculate others */
1027 	RESOURCE_NUM_RL_E		=	6,
1028 	RESOURCE_NUM_PQ_E		=	7,
1029 	RESOURCE_NUM_VF_E		=	8,
1030 	RESOURCE_VFC_FILTER_E		=	9,
1031 	RESOURCE_ILT_E			=	10,
1032 	RESOURCE_CQS_E			=	11,
1033 	RESOURCE_GFT_PROFILES_E		=	12,
1034 	RESOURCE_NUM_TC_E		=	13,
1035 	RESOURCE_NUM_RSS_ENGINES_E	=	14,
1036 	RESOURCE_LL2_QUEUE_E		=	15,
1037 	RESOURCE_RDMA_STATS_QUEUE_E	=	16,
1038 	RESOURCE_BDQ_E			=	17,
1039 	RESOURCE_MAX_NUM,
1040 	RESOURCE_NUM_INVALID		=	0xFFFFFFFF
1041 };
1042 
1043 /* Resource ID is to be filled by the driver in the MB request
1044  * Size, offset & flags to be filled by the MFW in the MB response
1045  */
1046 struct resource_info {
1047 	enum resource_id_enum res_id;
1048 	u32 size; /* number of allocated resources */
1049 	u32 offset; /* Offset of the 1st resource */
1050 	u32 vf_size;
1051 	u32 vf_offset;
1052 	u32 flags;
1053 #define RESOURCE_ELEMENT_STRICT (1 << 0)
1054 };
1055 
1056 struct mcp_wwn {
1057 	u32 wwn_upper;
1058 	u32 wwn_lower;
1059 };
1060 
1061 #define DRV_ROLE_NONE		0
1062 #define DRV_ROLE_PREBOOT	1
1063 #define DRV_ROLE_OS		2
1064 #define DRV_ROLE_KDUMP		3
1065 
1066 struct load_req_stc {
1067 	u32 drv_ver_0;
1068 	u32 drv_ver_1;
1069 	u32 fw_ver;
1070 	u32 misc0;
1071 #define LOAD_REQ_ROLE_MASK		0x000000FF
1072 #define LOAD_REQ_ROLE_SHIFT		0
1073 #define LOAD_REQ_LOCK_TO_MASK		0x0000FF00
1074 #define LOAD_REQ_LOCK_TO_SHIFT		8
1075 #define LOAD_REQ_LOCK_TO_DEFAULT	0
1076 #define LOAD_REQ_LOCK_TO_NONE		255
1077 #define LOAD_REQ_FORCE_MASK		0x000F0000
1078 #define LOAD_REQ_FORCE_SHIFT		16
1079 #define LOAD_REQ_FORCE_NONE		0
1080 #define LOAD_REQ_FORCE_PF		1
1081 #define LOAD_REQ_FORCE_ALL		2
1082 #define LOAD_REQ_FLAGS0_MASK		0x00F00000
1083 #define LOAD_REQ_FLAGS0_SHIFT		20
1084 #define LOAD_REQ_FLAGS0_AVOID_RESET	(0x1 << 0)
1085 };
1086 
1087 struct load_rsp_stc {
1088 	u32 drv_ver_0;
1089 	u32 drv_ver_1;
1090 	u32 fw_ver;
1091 	u32 misc0;
1092 #define LOAD_RSP_ROLE_MASK		0x000000FF
1093 #define LOAD_RSP_ROLE_SHIFT		0
1094 #define LOAD_RSP_HSI_MASK		0x0000FF00
1095 #define LOAD_RSP_HSI_SHIFT		8
1096 #define LOAD_RSP_FLAGS0_MASK		0x000F0000
1097 #define LOAD_RSP_FLAGS0_SHIFT		16
1098 #define LOAD_RSP_FLAGS0_DRV_EXISTS	(0x1 << 0)
1099 };
1100 
1101 struct mdump_retain_data_stc {
1102 	u32 valid;
1103 	u32 epoch;
1104 	u32 pf;
1105 	u32 status;
1106 };
1107 
1108 union drv_union_data {
1109 	struct mcp_mac wol_mac; /* UNLOAD_DONE */
1110 
1111 	/* This configuration should be set by the driver for the LINK_SET command. */
1112 	struct eth_phy_cfg drv_phy_cfg;
1113 
1114 	struct mcp_val64 val64; /* For PHY / AVS commands */
1115 
1116 	u8 raw_data[MCP_DRV_NVM_BUF_LEN];
1117 
1118 	struct mcp_file_att file_att;
1119 
1120 	u32 ack_vf_disabled[VF_MAX_STATIC / 32];
1121 
1122 	struct drv_version_stc drv_version;
1123 
1124 	struct lan_stats_stc lan_stats;
1125 	struct fcoe_stats_stc fcoe_stats;
1126 	struct iscsi_stats_stc iscsi_stats;
1127 	struct rdma_stats_stc rdma_stats;
1128 	struct ocbb_data_stc ocbb_info;
1129 	struct temperature_status_stc temp_info;
1130 	struct resource_info resource;
1131 	struct bist_nvm_image_att nvm_image_att;
1132 	struct mdump_config_stc mdump_config;
1133 	struct mcp_mac lldp_mac;
1134 	struct mcp_wwn fcoe_fabric_name;
1135 	u32 dword;
1136 
1137 	struct load_req_stc load_req;
1138 	struct load_rsp_stc load_rsp;
1139 	struct mdump_retain_data_stc mdump_retain;
1140 	/* ... */
1141 };
1142 
1143 struct public_drv_mb {
1144 
1145 	u32 drv_mb_header;
1146 #define DRV_MSG_CODE_MASK                       0xffff0000
1147 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1148 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1149 #define DRV_MSG_CODE_INIT_HW                    0x12000000
1150 #define DRV_MSG_CODE_CANCEL_LOAD_REQ            0x13000000
1151 #define DRV_MSG_CODE_UNLOAD_REQ		        0x20000000
1152 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1153 #define DRV_MSG_CODE_INIT_PHY			0x22000000
1154 	/* Params - FORCE - Reinitialize the link regardless of LFA */
1155 	/*        - DONT_CARE - Don't flap the link if up */
1156 #define DRV_MSG_CODE_LINK_RESET			0x23000000
1157 
1158 	// Vitaly: LLDP commands
1159 #define DRV_MSG_CODE_SET_LLDP                   0x24000000
1160 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
1161 	/* OneView feature driver HSI*/
1162 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG		0x26000000
1163 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM		0x27000000
1164 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS	0x28000000
1165 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER	0x29000000
1166 #define DRV_MSG_CODE_NIG_DRAIN			0x30000000
1167 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE	0x31000000
1168 #define DRV_MSG_CODE_BW_UPDATE_ACK		0x32000000
1169 #define DRV_MSG_CODE_OV_UPDATE_MTU		0x33000000
1170 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG		0x34000000 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, data: struct resource_info */
1171 #define DRV_MSG_SET_RESOURCE_VALUE_MSG		0x35000000
1172 #define DRV_MSG_CODE_OV_UPDATE_WOL		0x38000000
1173 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE	0x39000000
1174 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK		0x3b000000
1175 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID	0x3c000000
1176 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME	0x3d000000
1177 #define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG	0x3e000000
1178 #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT	0x3f000000
1179 #define DRV_MSG_CODE_OV_GET_CURR_CFG		0x40000000
1180 
1181 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED    0x02000000 /*deprecated don't use*/
1182 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
1183 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1184 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
1185 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX            0xc0020000
1186 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN		0x00010000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */
1187 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA		0x00020000 /* Param should be set to the transaction size (up to 64 bytes) */
1188 #define DRV_MSG_CODE_NVM_GET_FILE_ATT		0x00030000 /* MFW will place the file offset and len in file_att struct */
1189 #define DRV_MSG_CODE_NVM_READ_NVRAM		0x00050000 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes*/
1190 #define DRV_MSG_CODE_NVM_WRITE_NVRAM		0x00060000 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes. In case this address is in the range of secured file in secured mode, the operation will fail */
1191 #define DRV_MSG_CODE_NVM_DEL_FILE		0x00080000 /* Delete a file from nvram. Param is image_type. */
1192 #define DRV_MSG_CODE_MCP_RESET			0x00090000 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. In case operation succeed, MCP will not ack back. */
1193 #define DRV_MSG_CODE_SET_SECURE_MODE		0x000a0000 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1 (Secure) / 2 (Full-Secure) */
1194 #define DRV_MSG_CODE_PHY_RAW_READ		0x000b0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port*/
1195 #define DRV_MSG_CODE_PHY_RAW_WRITE		0x000c0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port */
1196 #define DRV_MSG_CODE_PHY_CORE_READ		0x000d0000 /* Param: [0:15] - Address, [30:31] - port */
1197 #define DRV_MSG_CODE_PHY_CORE_WRITE		0x000e0000 /* Param: [0:15] - Address, [30:31] - port */
1198 #define DRV_MSG_CODE_SET_VERSION		0x000f0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */
1199 #define DRV_MSG_CODE_MCP_HALT			0x00100000 /* Halts the MCP. To resume MCP, user will need to use MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */
1200 #define DRV_MSG_CODE_SET_VMAC                   0x00110000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */
1201 #define DRV_MSG_CODE_GET_VMAC                   0x00120000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */
1202 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT		4
1203 #define DRV_MSG_CODE_VMAC_TYPE_MASK		0x30
1204 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
1205 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
1206 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3
1207 
1208 #define DRV_MSG_CODE_GET_STATS                  0x00130000 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */
1209 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
1210 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
1211 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
1212 #define DRV_MSG_CODE_STATS_TYPE_RDMA  		4
1213 #define DRV_MSG_CODE_PMD_DIAG_DUMP 		0x00140000 /* Host shall provide buffer and size for MFW  */
1214 #define DRV_MSG_CODE_PMD_DIAG_EYE  		0x00150000 /* Host shall provide buffer and size for MFW  */
1215 #define DRV_MSG_CODE_TRANSCEIVER_READ		0x00160000 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, [16:31] - offset */
1216 #define DRV_MSG_CODE_TRANSCEIVER_WRITE		0x00170000 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, [16:31] - offset */
1217 #define DRV_MSG_CODE_OCBB_DATA			0x00180000 /* indicate OCBB related information */
1218 #define DRV_MSG_CODE_SET_BW			0x00190000 /* Set function BW, params[15:8] - min, params[7:0] - max */
1219 #define BW_MAX_MASK				0x000000ff
1220 #define BW_MAX_SHIFT				0
1221 #define BW_MIN_MASK				0x0000ff00
1222 #define BW_MIN_SHIFT				8
1223 
1224 #define DRV_MSG_CODE_MASK_PARITIES		0x001a0000 /* When param is set to 1, all parities will be masked(disabled). When params are set to 0, parities will be unmasked again. */
1225 #define DRV_MSG_CODE_INDUCE_FAILURE		0x001b0000 /* param[0] - Simulate fan failure,  param[1] - simulate over temp. */
1226 #define DRV_MSG_FAN_FAILURE_TYPE		(1 << 0)
1227 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE	(1 << 1)
1228 #define DRV_MSG_CODE_GPIO_READ			0x001c0000 /* Param: [0:15] - gpio number */
1229 #define DRV_MSG_CODE_GPIO_WRITE			0x001d0000 /* Param: [0:15] - gpio number, [16:31] - gpio value */
1230 #define DRV_MSG_CODE_BIST_TEST			0x001e0000      /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */
1231 #define DRV_MSG_CODE_GET_TEMPERATURE            0x001f0000
1232 #define DRV_MSG_CODE_SET_LED_MODE		0x00200000 /* Set LED mode  params :0 operational, 1 LED turn ON, 2 LED turn OFF */
1233 #define DRV_MSG_CODE_TIMESTAMP                  0x00210000 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - driver version (MAJ MIN BUILD SUB) */
1234 #define DRV_MSG_CODE_EMPTY_MB			0x00220000 /* This is an empty mailbox just return OK*/
1235 
1236 #define DRV_MSG_CODE_RESOURCE_CMD		0x00230000 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, param[15:8] - age */
1237 
1238 #define RESOURCE_CMD_REQ_RESC_MASK		0x0000001F
1239 #define RESOURCE_CMD_REQ_RESC_SHIFT		0
1240 #define RESOURCE_CMD_REQ_OPCODE_MASK		0x000000E0
1241 #define RESOURCE_CMD_REQ_OPCODE_SHIFT		5
1242 #define RESOURCE_OPCODE_REQ			1 /* request resource ownership with default aging */
1243 #define RESOURCE_OPCODE_REQ_WO_AGING        	2 /* request resource ownership without aging */
1244 #define RESOURCE_OPCODE_REQ_W_AGING        	3 /* request resource ownership with specific aging timer (in seconds) */
1245 #define RESOURCE_OPCODE_RELEASE			4 /* release resource */
1246 #define RESOURCE_OPCODE_FORCE_RELEASE		5 /* force resource release */
1247 #define RESOURCE_CMD_REQ_AGE_MASK		0x0000FF00
1248 #define RESOURCE_CMD_REQ_AGE_SHIFT		8
1249 
1250 #define RESOURCE_CMD_RSP_OWNER_MASK		0x000000FF
1251 #define RESOURCE_CMD_RSP_OWNER_SHIFT		0
1252 #define RESOURCE_CMD_RSP_OPCODE_MASK		0x00000700
1253 #define RESOURCE_CMD_RSP_OPCODE_SHIFT		8
1254 #define RESOURCE_OPCODE_GNT			1 /* resource is free and granted to requester */
1255 #define RESOURCE_OPCODE_BUSY			2 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 16 = MFW, 17 = diag over serial */
1256 #define RESOURCE_OPCODE_RELEASED		3 /* indicate release request was acknowledged */
1257 #define RESOURCE_OPCODE_RELEASED_PREVIOUS	4 /* indicate release request was previously received by other owner */
1258 #define RESOURCE_OPCODE_WRONG_OWNER		5 /* indicate wrong owner during release */
1259 #define RESOURCE_OPCODE_UNKNOWN_CMD		255
1260 
1261 #define RESOURCE_DUMP				0 /* dedicate resource 0 for dump */
1262 
1263 #define DRV_MSG_CODE_GET_MBA_VERSION		0x00240000 /* Get MBA version */
1264 #define DRV_MSG_CODE_MDUMP_CMD			0x00250000 /* Send crash dump commands with param[3:0] - opcode */
1265 #define MDUMP_DRV_PARAM_OPCODE_MASK		0x0000000f
1266 #define DRV_MSG_CODE_MDUMP_ACK			0x01 /* acknowledge reception of error indication */
1267 #define DRV_MSG_CODE_MDUMP_SET_VALUES		0x02 /* set epoc and personality as follow: drv_data[3:0] - epoch, drv_data[7:4] - personality */
1268 #define DRV_MSG_CODE_MDUMP_TRIGGER		0x03 /* trigger crash dump procedure */
1269 #define DRV_MSG_CODE_MDUMP_GET_CONFIG		0x04 /* Request valid logs and config words */
1270 #define DRV_MSG_CODE_MDUMP_SET_ENABLE		0x05 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger enabled */
1271 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS		0x06 /* Clear all logs */
1272 #define DRV_MSG_CODE_MDUMP_GET_RETAIN		0x07 /* Get retained data */
1273 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN		0x08 /* Clear retain data */
1274 #define DRV_MSG_CODE_MEM_ECC_EVENTS		0x00260000 /* Param: None */
1275 #define DRV_MSG_CODE_GPIO_INFO			0x00270000 /* Param: [0:15] - gpio number */
1276 #define DRV_MSG_CODE_EXT_PHY_READ		0x00280000 /* Value will be placed in union */
1277 #define DRV_MSG_CODE_EXT_PHY_WRITE		0x00290000 /* Value shoud be placed in union */
1278 #define DRV_MB_PARAM_ADDR_SHIFT			0
1279 #define DRV_MB_PARAM_ADDR_MASK			0x0000FFFF
1280 #define DRV_MB_PARAM_DEVAD_SHIFT		16
1281 #define DRV_MB_PARAM_DEVAD_MASK			0x001F0000
1282 #define DRV_MB_PARAM_PORT_SHIFT			21
1283 #define DRV_MB_PARAM_PORT_MASK			0x00600000
1284 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE		0x002a0000
1285 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL	0x002b0000
1286 #define DRV_MSG_CODE_SET_LLDP_MAC			0x002c0000
1287 #define DRV_MSG_CODE_GET_LLDP_MAC			0x002d0000
1288 #define DRV_MSG_CODE_OS_WOL					0x002e0000
1289 
1290 #define DRV_MSG_CODE_GET_TLV_DONE  	        0x002f0000 /* Param: None */
1291 #define DRV_MSG_CODE_FEATURE_SUPPORT 		0x00300000 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */
1292 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT	0x00310000 /* return FW_MB_PARAM_FEATURE_SUPPORT_*  */
1293 
1294 #define DRV_MSG_CODE_READ_WOL_REG			0X00320000
1295 #define DRV_MSG_CODE_WRITE_WOL_REG			0X00330000
1296 #define DRV_MSG_CODE_GET_WOL_BUFFER			0X00340000
1297 
1298 #define DRV_MSG_SEQ_NUMBER_MASK				0x0000ffff
1299 
1300 	u32 drv_mb_param;
1301 	/* UNLOAD_REQ params */
1302 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
1303 #define DRV_MB_PARAM_UNLOAD_WOL_MCP		0x00000001
1304 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
1305 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
1306 
1307 	/* UNLOAD_DONE_params */
1308 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER        0x00000001
1309 
1310 	/* INIT_PHY params */
1311 #define DRV_MB_PARAM_INIT_PHY_FORCE		0x00000001
1312 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE		0x00000002
1313 
1314 	/* LLDP / DCBX params*/
1315 #define DRV_MB_PARAM_LLDP_SEND_MASK		0x00000001
1316 #define DRV_MB_PARAM_LLDP_SEND_SHIFT		0
1317 #define DRV_MB_PARAM_LLDP_AGENT_MASK		0x00000006
1318 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT       	1
1319 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK		0x00000008
1320 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT		3
1321 
1322 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK	0x000000FF
1323 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT	0
1324 
1325 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW	0x1
1326 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE	0x2
1327 
1328 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT		0
1329 #define DRV_MB_PARAM_NVM_OFFSET_MASK		0x00FFFFFF
1330 #define DRV_MB_PARAM_NVM_LEN_SHIFT		24
1331 #define DRV_MB_PARAM_NVM_LEN_MASK		0xFF000000
1332 
1333 #define DRV_MB_PARAM_PHY_ADDR_SHIFT		0
1334 #define DRV_MB_PARAM_PHY_ADDR_MASK		0x1FF0FFFF
1335 #define DRV_MB_PARAM_PHY_LANE_SHIFT		16
1336 #define DRV_MB_PARAM_PHY_LANE_MASK		0x000F0000
1337 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT	29
1338 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK	0x20000000
1339 #define DRV_MB_PARAM_PHY_PORT_SHIFT		30
1340 #define DRV_MB_PARAM_PHY_PORT_MASK		0xc0000000
1341 
1342 #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT		0
1343 #define DRV_MB_PARAM_PHYMOD_LANE_MASK		0x000000FF
1344 #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT		8
1345 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK		0x000FFF00
1346 	/* configure vf MSIX params BB */
1347 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT	0
1348 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK		0x000000FF
1349 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT	8
1350 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK	0x0000FF00
1351 	/* configure vf MSIX for PF params AH*/
1352 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_SHIFT	0
1353 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK	0x000000FF
1354 
1355 	/* OneView configuration parametres */
1356 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT		0
1357 #define DRV_MB_PARAM_OV_CURR_CFG_MASK		0x0000000F
1358 #define DRV_MB_PARAM_OV_CURR_CFG_NONE		0
1359 #define DRV_MB_PARAM_OV_CURR_CFG_OS			1
1360 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC	2
1361 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER		3
1362 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP		4
1363 #define DRV_MB_PARAM_OV_CURR_CFG_CNU		5
1364 #define DRV_MB_PARAM_OV_CURR_CFG_DCI		6
1365 #define DRV_MB_PARAM_OV_CURR_CFG_HII		7
1366 
1367 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT					0
1368 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK					0x000000FF
1369 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE					(1 << 0)
1370 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED		(1 << 1)
1371 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS	(1 << 1)
1372 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND			(1 << 2)
1373 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS		(1 << 3)
1374 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND			(1 << 3)
1375 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT 		(1 << 4)
1376 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED			(1 << 5)
1377 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF				(1 << 6)
1378 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 					0
1379 
1380 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT    	0
1381 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK		0x000000FF
1382 
1383 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT    		0
1384 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK			0xFFFFFFFF
1385 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK		0xFF000000
1386 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK		0x00FF0000
1387 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK		0x0000FF00
1388 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK		0x000000FF
1389 
1390 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT		0
1391 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK		0xF
1392 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN		0x1
1393 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED	0x2 /* Not Installed*/
1394 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING		0x3
1395 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED	0x4 /* installed but disabled by user/admin/OS */
1396 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE		0x5 /* installed and active */
1397 
1398 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT    	0
1399 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK		0xFFFFFFFF
1400 
1401 #define DRV_MB_PARAM_WOL_MASK		(DRV_MB_PARAM_WOL_DEFAULT | 	\
1402 					 DRV_MB_PARAM_WOL_DISABLED |	\
1403 					 DRV_MB_PARAM_WOL_ENABLED)
1404 #define DRV_MB_PARAM_WOL_DEFAULT	DRV_MB_PARAM_UNLOAD_WOL_MCP
1405 #define DRV_MB_PARAM_WOL_DISABLED	DRV_MB_PARAM_UNLOAD_WOL_DISABLED
1406 #define DRV_MB_PARAM_WOL_ENABLED	DRV_MB_PARAM_UNLOAD_WOL_ENABLED
1407 
1408 #define DRV_MB_PARAM_ESWITCH_MODE_MASK	(DRV_MB_PARAM_ESWITCH_MODE_NONE | \
1409 					 DRV_MB_PARAM_ESWITCH_MODE_VEB |   \
1410 					 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
1411 #define DRV_MB_PARAM_ESWITCH_MODE_NONE	0x0
1412 #define DRV_MB_PARAM_ESWITCH_MODE_VEB	0x1
1413 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA	0x2
1414 
1415 #define DRV_MB_PARAM_FCOE_CVID_MASK	0xFFF
1416 #define DRV_MB_PARAM_FCOE_CVID_SHIFT	0
1417 
1418 #define DRV_MB_PARAM_SET_LED_MODE_OPER		0x0
1419 #define DRV_MB_PARAM_SET_LED_MODE_ON		0x1
1420 #define DRV_MB_PARAM_SET_LED_MODE_OFF		0x2
1421 
1422 #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT		0
1423 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK		0x00000003
1424 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT		2
1425 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK		0x000000FC
1426 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT	8
1427 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK	0x0000FF00
1428 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT		16
1429 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK		0xFFFF0000
1430 
1431 #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT		0
1432 #define DRV_MB_PARAM_GPIO_NUMBER_MASK		0x0000FFFF
1433 #define DRV_MB_PARAM_GPIO_VALUE_SHIFT		16
1434 #define DRV_MB_PARAM_GPIO_VALUE_MASK		0xFFFF0000
1435 #define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT	16
1436 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK	0x00FF0000
1437 #define DRV_MB_PARAM_GPIO_CTRL_SHIFT		24
1438 #define DRV_MB_PARAM_GPIO_CTRL_MASK		0xFF000000
1439 
1440 	/* Resource Allocation params - Driver version support*/
1441 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000
1442 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT		16
1443 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF
1444 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0
1445 
1446 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST		0
1447 #define DRV_MB_PARAM_BIST_REGISTER_TEST		1
1448 #define DRV_MB_PARAM_BIST_CLOCK_TEST		2
1449 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES		3
1450 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX	4
1451 
1452 #define DRV_MB_PARAM_BIST_RC_UNKNOWN		0
1453 #define DRV_MB_PARAM_BIST_RC_PASSED		1
1454 #define DRV_MB_PARAM_BIST_RC_FAILED		2
1455 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER		3
1456 
1457 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT      0
1458 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK       0x000000FF
1459 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT      8
1460 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK       0x0000FF00
1461 
1462 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK      0x0000FFFF
1463 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SHIFT     0
1464 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 /* driver supports SmartLinQ parameter */
1465 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE       0x00000002 /* driver supports EEE parameter */
1466 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK      0xFFFF0000
1467 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_SHIFT     16
1468 
1469 	u32 fw_mb_header;
1470 #define FW_MSG_CODE_MASK                        0xffff0000
1471 #define FW_MSG_CODE_UNSUPPORTED			0x00000000
1472 #define FW_MSG_CODE_DRV_LOAD_ENGINE		0x10100000
1473 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1474 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1475 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
1476 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1      0x10210000
1477 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
1478 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10230000
1479 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
1480 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT     0x10310000
1481 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1482 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
1483 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
1484 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
1485 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1486 #define FW_MSG_CODE_INIT_PHY_DONE		0x21200000
1487 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS	0x21300000
1488 #define FW_MSG_CODE_LINK_RESET_DONE		0x23000000
1489 #define FW_MSG_CODE_SET_LLDP_DONE               0x24000000
1490 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT  0x24010000
1491 #define FW_MSG_CODE_SET_DCBX_DONE               0x25000000
1492 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE        0x26000000
1493 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE         0x27000000
1494 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE   0x28000000
1495 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE    0x29000000
1496 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE    0x31000000
1497 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
1498 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE  0x33000000
1499 #define FW_MSG_CODE_RESOURCE_ALLOC_OK           0x34000000
1500 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
1501 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
1502 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR      0x37000000
1503 #define FW_MSG_CODE_UPDATE_WOL_DONE		0x38000000
1504 #define FW_MSG_CODE_UPDATE_ESWITCH_MODE_DONE	0x39000000
1505 #define FW_MSG_CODE_UPDATE_ERR			0x3a010000
1506 #define FW_MSG_CODE_UPDATE_PARAM_ERR		0x3a020000
1507 #define FW_MSG_CODE_UPDATE_NOT_ALLOWED		0x3a030000
1508 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE	0x3b000000
1509 #define FW_MSG_CODE_UPDATE_FCOE_CVID_DONE	0x3c000000
1510 #define FW_MSG_CODE_UPDATE_FCOE_FABRIC_NAME_DONE	0x3d000000
1511 #define FW_MSG_CODE_UPDATE_BOOT_CFG_DONE	0x3e000000
1512 #define FW_MSG_CODE_RESET_TO_DEFAULT_ACK	0x3f000000
1513 #define FW_MSG_CODE_OV_GET_CURR_CFG_DONE	0x40000000
1514 
1515 #define FW_MSG_CODE_NIG_DRAIN_DONE              0x30000000
1516 #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1517 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
1518 #define FW_MSG_CODE_FLR_ACK                     0x02000000
1519 #define FW_MSG_CODE_FLR_NACK                    0x02100000
1520 #define FW_MSG_CODE_SET_DRIVER_DONE		0x02200000
1521 #define FW_MSG_CODE_SET_VMAC_SUCCESS            0x02300000
1522 #define FW_MSG_CODE_SET_VMAC_FAIL               0x02400000
1523 
1524 #define FW_MSG_CODE_NVM_OK			0x00010000
1525 #define FW_MSG_CODE_NVM_INVALID_MODE		0x00020000
1526 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED	0x00030000
1527 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE	0x00040000
1528 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND	0x00050000
1529 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND		0x00060000
1530 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
1531 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
1532 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC  	0x00090000
1533 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 	0x000a0000
1534 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 	0x000b0000
1535 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 		0x000c0000
1536 #define FW_MSG_CODE_NVM_OPERATION_FAILED 	0x000d0000
1537 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 	0x000e0000
1538 #define FW_MSG_CODE_NVM_BAD_OFFSET	 	0x000f0000
1539 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 		0x00100000
1540 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 		0x00200000
1541 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 		0x00300000
1542 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK	0x00400000
1543 #define FW_MSG_CODE_MCP_RESET_REJECT		0x00600000 /* MFW reject "mcp reset" command if one of the drivers is up */
1544 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH	0x00310000
1545 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING	0x00320000
1546 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY	0x00330000
1547 
1548 #define FW_MSG_CODE_PHY_OK			0x00110000
1549 #define FW_MSG_CODE_PHY_ERROR			0x00120000
1550 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR	0x00130000
1551 #define FW_MSG_CODE_SET_SECURE_MODE_OK		0x00140000
1552 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR		0x00150000
1553 #define FW_MSG_CODE_OK				0x00160000
1554 #define FW_MSG_CODE_LED_MODE_INVALID		0x00170000
1555 #define FW_MSG_CODE_PHY_DIAG_OK			0x00160000
1556 #define FW_MSG_CODE_PHY_DIAG_ERROR		0x00170000
1557 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE	0x00040000
1558 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE    0x00170000
1559 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
1560 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE	0x000c0000
1561 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH	0x00100000
1562 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK		0x00160000
1563 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR	0x00170000
1564 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT	0x00020000
1565 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE	0x000f0000
1566 #define FW_MSG_CODE_GPIO_OK			0x00160000
1567 #define FW_MSG_CODE_GPIO_DIRECTION_ERR		0x00170000
1568 #define FW_MSG_CODE_GPIO_CTRL_ERR		0x00020000
1569 #define FW_MSG_CODE_GPIO_INVALID	 	0x000f0000
1570 #define FW_MSG_CODE_GPIO_INVALID_VALUE		0x00050000
1571 #define FW_MSG_CODE_BIST_TEST_INVALID	 	0x000f0000
1572 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER	0x00700000
1573 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE	0x00710000
1574 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED	0x00720000
1575 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED	0x00730000
1576 #define FW_MSG_CODE_RECOVERY_MODE		0x00740000
1577 
1578 	/* mdump related response codes */
1579 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND	0x00010000
1580 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED		0x00020000
1581 #define FW_MSG_CODE_MDUMP_INVALID_CMD		0x00030000
1582 #define FW_MSG_CODE_MDUMP_IN_PROGRESS		0x00040000
1583 #define FW_MSG_CODE_MDUMP_WRITE_FAILED		0x00050000
1584 
1585 #define FW_MSG_CODE_OS_WOL_SUPPORTED		0x00800000
1586 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED	0x00810000
1587 
1588 #define FW_MSG_CODE_WOL_READ_WRITE_OK		0x00820000
1589 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL	0x00830000
1590 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR	0x00840000
1591 #define FW_MSG_CODE_WOL_READ_BUFFER_OK		0x00850000
1592 #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL	0x00860000
1593 
1594 
1595 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE   	 0x00870000
1596 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000
1597 
1598 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1599 
1600 
1601 	u32 fw_mb_param;
1602 /* Resource Allocation params - MFW version support */
1603 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000
1604 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT		16
1605 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF
1606 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0
1607 
1608 /* get pf rdma protocol command response */
1609 #define FW_MB_PARAM_GET_PF_RDMA_NONE		0x0
1610 #define FW_MB_PARAM_GET_PF_RDMA_ROCE		0x1
1611 #define FW_MB_PARAM_GET_PF_RDMA_IWARP		0x2
1612 #define FW_MB_PARAM_GET_PF_RDMA_BOTH		0x3
1613 
1614 /* get MFW feature support response */
1615 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001 /* MFW supports SmartLinQ */
1616 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002 /* MFW supports EEE */
1617 
1618 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR	(1<<0)
1619 
1620 	u32 drv_pulse_mb;
1621 #define DRV_PULSE_SEQ_MASK                      0x00007fff
1622 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1623 	/*
1624 	 * The system time is in the format of
1625 	 * (year-2001)*12*32 + month*32 + day.
1626 	 */
1627 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1628 	/*
1629 	 * Indicate to the firmware not to go into the
1630 	 * OS-absent when it is not getting driver pulse.
1631 	 * This is used for debugging as well for PXE(MBA).
1632 	 */
1633 
1634 	u32 mcp_pulse_mb;
1635 #define MCP_PULSE_SEQ_MASK                      0x00007fff
1636 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1637 	/* Indicates to the driver not to assert due to lack
1638 	 * of MCP response */
1639 #define MCP_EVENT_MASK                          0xffff0000
1640 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1641 
1642 	/* The union data is used by the driver to pass parameters to the scratchpad. */
1643 	union drv_union_data union_data;
1644 
1645 };
1646 
1647 /* MFW - DRV MB */
1648 /**********************************************************************
1649  * Description
1650  *   Incremental Aggregative
1651  *   8-bit MFW counter per message
1652  *   8-bit ack-counter per message
1653  * Capabilities
1654  *   Provides up to 256 aggregative message per type
1655  *   Provides 4 message types in dword
1656  *   Message type pointers to byte offset
1657  *   Backward Compatibility by using sizeof for the counters.
1658  *   No lock requires for 32bit messages
1659  * Limitations:
1660  * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
1661  * is required to prevent data corruption.
1662  **********************************************************************/
1663 enum MFW_DRV_MSG_TYPE {
1664 	MFW_DRV_MSG_LINK_CHANGE,
1665 	MFW_DRV_MSG_FLR_FW_ACK_FAILED,
1666 	MFW_DRV_MSG_VF_DISABLED,
1667 	MFW_DRV_MSG_LLDP_DATA_UPDATED,
1668 	MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
1669 	MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
1670 	MFW_DRV_MSG_ERROR_RECOVERY,
1671 	MFW_DRV_MSG_BW_UPDATE,
1672 	MFW_DRV_MSG_S_TAG_UPDATE,
1673 	MFW_DRV_MSG_GET_LAN_STATS,
1674 	MFW_DRV_MSG_GET_FCOE_STATS,
1675 	MFW_DRV_MSG_GET_ISCSI_STATS,
1676 	MFW_DRV_MSG_GET_RDMA_STATS,
1677 	MFW_DRV_MSG_FAILURE_DETECTED,
1678 	MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1679 	MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
1680 	MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE,
1681 	MFW_DRV_MSG_GET_TLV_REQ,
1682 	MFW_DRV_MSG_MAX
1683 };
1684 
1685 #define MFW_DRV_MSG_MAX_DWORDS(msgs)	(((msgs - 1) >> 2) + 1)
1686 #define MFW_DRV_MSG_DWORD(msg_id)	(msg_id >> 2)
1687 #define MFW_DRV_MSG_OFFSET(msg_id)	((msg_id & 0x3) << 3)
1688 #define MFW_DRV_MSG_MASK(msg_id)	(0xff << MFW_DRV_MSG_OFFSET(msg_id))
1689 
1690 #ifdef BIG_ENDIAN		/* Like MFW */
1691 #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[msg_id]++;
1692 #else
1693 #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;
1694 #endif
1695 
1696 #define MFW_DRV_UPDATE(shmem_func, msg_id)	(u8)((u8*)(MFW_MB_P(shmem_func)->msg))[msg_id]++;
1697 
1698 struct public_mfw_mb {
1699 	u32 sup_msgs;       /* Assigend with MFW_DRV_MSG_MAX */
1700 	u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];   /* Incremented by the MFW */
1701 	u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];   /* Incremented by the driver */
1702 };
1703 
1704 /**************************************/
1705 /*                                    */
1706 /*     P U B L I C       D A T A      */
1707 /*                                    */
1708 /**************************************/
1709 enum public_sections {
1710 	PUBLIC_DRV_MB,      /* Points to the first drv_mb of path0 */
1711 	PUBLIC_MFW_MB,      /* Points to the first mfw_mb of path0 */
1712 	PUBLIC_GLOBAL,
1713 	PUBLIC_PATH,
1714 	PUBLIC_PORT,
1715 	PUBLIC_FUNC,
1716 	PUBLIC_MAX_SECTIONS
1717 };
1718 
1719 struct drv_ver_info_stc {
1720 	u32 ver;
1721 	u8 name[32];
1722 };
1723 
1724 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
1725  * Please make sure data does not exceed this size.
1726  */
1727 #define NUM_RUNTIME_DWORDS 16
1728 struct drv_init_hw_stc {
1729 	u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
1730 	u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
1731 };
1732 
1733 struct mcp_public_data {
1734 	/* The sections fields is an array */
1735 	u32 num_sections;
1736 	offsize_t sections[PUBLIC_MAX_SECTIONS];
1737 	struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
1738 	struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
1739 	struct public_global global;
1740 	struct public_path path[MCP_GLOB_PATH_MAX];
1741 	struct public_port port[MCP_GLOB_PORT_MAX];
1742 	struct public_func func[MCP_GLOB_FUNC_MAX];
1743 };
1744 
1745 #define I2C_TRANSCEIVER_ADDR	0xa0
1746 #define MAX_I2C_TRANSACTION_SIZE	16
1747 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE	256
1748 
1749 /* OCBB definitions */
1750 enum tlvs {
1751 	/* Category 1: Device Properties */
1752 	DRV_TLV_CLP_STR,
1753 	DRV_TLV_CLP_STR_CTD,
1754 	/* Category 6: Device Configuration */
1755 	DRV_TLV_SCSI_TO,
1756 	DRV_TLV_R_T_TOV,
1757 	DRV_TLV_R_A_TOV,
1758 	DRV_TLV_E_D_TOV,
1759 	DRV_TLV_CR_TOV,
1760 	DRV_TLV_BOOT_TYPE,
1761 	/* Category 8: Port Configuration */
1762 	DRV_TLV_NPIV_ENABLED,
1763 	/* Category 10: Function Configuration */
1764 	DRV_TLV_FEATURE_FLAGS,
1765 	DRV_TLV_LOCAL_ADMIN_ADDR,
1766 	DRV_TLV_ADDITIONAL_MAC_ADDR_1,
1767 	DRV_TLV_ADDITIONAL_MAC_ADDR_2,
1768 	DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
1769 	DRV_TLV_LSO_MIN_SEGMENT_COUNT,
1770 	DRV_TLV_PROMISCUOUS_MODE,
1771 	DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
1772 	DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
1773 	DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
1774 	DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
1775 	DRV_TLV_OS_DRIVER_STATES,
1776 	DRV_TLV_PXE_BOOT_PROGRESS,
1777 	/* Category 12: FC/FCoE Configuration */
1778 	DRV_TLV_NPIV_STATE,
1779 	DRV_TLV_NUM_OF_NPIV_IDS,
1780 	DRV_TLV_SWITCH_NAME,
1781 	DRV_TLV_SWITCH_PORT_NUM,
1782 	DRV_TLV_SWITCH_PORT_ID,
1783 	DRV_TLV_VENDOR_NAME,
1784 	DRV_TLV_SWITCH_MODEL,
1785 	DRV_TLV_SWITCH_FW_VER,
1786 	DRV_TLV_QOS_PRIORITY_PER_802_1P,
1787 	DRV_TLV_PORT_ALIAS,
1788 	DRV_TLV_PORT_STATE,
1789 	DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
1790 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
1791 	DRV_TLV_LINK_FAILURE_COUNT,
1792 	DRV_TLV_FCOE_BOOT_PROGRESS,
1793 	/* Category 13: iSCSI Configuration */
1794 	DRV_TLV_TARGET_LLMNR_ENABLED,
1795 	DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
1796 	DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
1797 	DRV_TLV_AUTHENTICATION_METHOD,
1798 	DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
1799 	DRV_TLV_MAX_FRAME_SIZE,
1800 	DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
1801 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
1802 	DRV_TLV_ISCSI_BOOT_PROGRESS,
1803 	/* Category 20: Device Data */
1804 	DRV_TLV_PCIE_BUS_RX_UTILIZATION,
1805 	DRV_TLV_PCIE_BUS_TX_UTILIZATION,
1806 	DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
1807 	DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
1808 	DRV_TLV_NCSI_RX_BYTES_RECEIVED,
1809 	DRV_TLV_NCSI_TX_BYTES_SENT,
1810 	/* Category 22: Base Port Data */
1811 	DRV_TLV_RX_DISCARDS,
1812 	DRV_TLV_RX_ERRORS,
1813 	DRV_TLV_TX_ERRORS,
1814 	DRV_TLV_TX_DISCARDS,
1815 	DRV_TLV_RX_FRAMES_RECEIVED,
1816 	DRV_TLV_TX_FRAMES_SENT,
1817 	/* Category 23: FC/FCoE Port Data */
1818 	DRV_TLV_RX_BROADCAST_PACKETS,
1819 	DRV_TLV_TX_BROADCAST_PACKETS,
1820 	/* Category 28: Base Function Data */
1821 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
1822 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
1823 	DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1824 	DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1825 	DRV_TLV_PF_RX_FRAMES_RECEIVED,
1826 	DRV_TLV_RX_BYTES_RECEIVED,
1827 	DRV_TLV_PF_TX_FRAMES_SENT,
1828 	DRV_TLV_TX_BYTES_SENT,
1829 	DRV_TLV_IOV_OFFLOAD,
1830 	DRV_TLV_PCI_ERRORS_CAP_ID,
1831 	DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
1832 	DRV_TLV_UNCORRECTABLE_ERROR_MASK,
1833 	DRV_TLV_CORRECTABLE_ERROR_STATUS,
1834 	DRV_TLV_CORRECTABLE_ERROR_MASK,
1835 	DRV_TLV_PCI_ERRORS_AECC_REGISTER,
1836 	DRV_TLV_TX_QUEUES_EMPTY,
1837 	DRV_TLV_RX_QUEUES_EMPTY,
1838 	DRV_TLV_TX_QUEUES_FULL,
1839 	DRV_TLV_RX_QUEUES_FULL,
1840 	/* Category 29: FC/FCoE Function Data */
1841 	DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1842 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1843 	DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
1844 	DRV_TLV_FCOE_RX_BYTES_RECEIVED,
1845 	DRV_TLV_FCOE_TX_FRAMES_SENT,
1846 	DRV_TLV_FCOE_TX_BYTES_SENT,
1847 	DRV_TLV_CRC_ERROR_COUNT,
1848 	DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
1849 	DRV_TLV_CRC_ERROR_1_TIMESTAMP,
1850 	DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
1851 	DRV_TLV_CRC_ERROR_2_TIMESTAMP,
1852 	DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
1853 	DRV_TLV_CRC_ERROR_3_TIMESTAMP,
1854 	DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
1855 	DRV_TLV_CRC_ERROR_4_TIMESTAMP,
1856 	DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
1857 	DRV_TLV_CRC_ERROR_5_TIMESTAMP,
1858 	DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
1859 	DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
1860 	DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
1861 	DRV_TLV_DISPARITY_ERROR_COUNT,
1862 	DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
1863 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
1864 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
1865 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
1866 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
1867 	DRV_TLV_LAST_FLOGI_TIMESTAMP,
1868 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
1869 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
1870 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
1871 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
1872 	DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
1873 	DRV_TLV_LAST_FLOGI_RJT,
1874 	DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
1875 	DRV_TLV_FDISCS_SENT_COUNT,
1876 	DRV_TLV_FDISC_ACCS_RECEIVED,
1877 	DRV_TLV_FDISC_RJTS_RECEIVED,
1878 	DRV_TLV_PLOGI_SENT_COUNT,
1879 	DRV_TLV_PLOGI_ACCS_RECEIVED,
1880 	DRV_TLV_PLOGI_RJTS_RECEIVED,
1881 	DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
1882 	DRV_TLV_PLOGI_1_TIMESTAMP,
1883 	DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
1884 	DRV_TLV_PLOGI_2_TIMESTAMP,
1885 	DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
1886 	DRV_TLV_PLOGI_3_TIMESTAMP,
1887 	DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
1888 	DRV_TLV_PLOGI_4_TIMESTAMP,
1889 	DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
1890 	DRV_TLV_PLOGI_5_TIMESTAMP,
1891 	DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
1892 	DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
1893 	DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
1894 	DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
1895 	DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
1896 	DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
1897 	DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
1898 	DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
1899 	DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
1900 	DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
1901 	DRV_TLV_LOGOS_ISSUED,
1902 	DRV_TLV_LOGO_ACCS_RECEIVED,
1903 	DRV_TLV_LOGO_RJTS_RECEIVED,
1904 	DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
1905 	DRV_TLV_LOGO_1_TIMESTAMP,
1906 	DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
1907 	DRV_TLV_LOGO_2_TIMESTAMP,
1908 	DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
1909 	DRV_TLV_LOGO_3_TIMESTAMP,
1910 	DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
1911 	DRV_TLV_LOGO_4_TIMESTAMP,
1912 	DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
1913 	DRV_TLV_LOGO_5_TIMESTAMP,
1914 	DRV_TLV_LOGOS_RECEIVED,
1915 	DRV_TLV_ACCS_ISSUED,
1916 	DRV_TLV_PRLIS_ISSUED,
1917 	DRV_TLV_ACCS_RECEIVED,
1918 	DRV_TLV_ABTS_SENT_COUNT,
1919 	DRV_TLV_ABTS_ACCS_RECEIVED,
1920 	DRV_TLV_ABTS_RJTS_RECEIVED,
1921 	DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
1922 	DRV_TLV_ABTS_1_TIMESTAMP,
1923 	DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
1924 	DRV_TLV_ABTS_2_TIMESTAMP,
1925 	DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
1926 	DRV_TLV_ABTS_3_TIMESTAMP,
1927 	DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
1928 	DRV_TLV_ABTS_4_TIMESTAMP,
1929 	DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
1930 	DRV_TLV_ABTS_5_TIMESTAMP,
1931 	DRV_TLV_RSCNS_RECEIVED,
1932 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
1933 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
1934 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
1935 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
1936 	DRV_TLV_LUN_RESETS_ISSUED,
1937 	DRV_TLV_ABORT_TASK_SETS_ISSUED,
1938 	DRV_TLV_TPRLOS_SENT,
1939 	DRV_TLV_NOS_SENT_COUNT,
1940 	DRV_TLV_NOS_RECEIVED_COUNT,
1941 	DRV_TLV_OLS_COUNT,
1942 	DRV_TLV_LR_COUNT,
1943 	DRV_TLV_LRR_COUNT,
1944 	DRV_TLV_LIP_SENT_COUNT,
1945 	DRV_TLV_LIP_RECEIVED_COUNT,
1946 	DRV_TLV_EOFA_COUNT,
1947 	DRV_TLV_EOFNI_COUNT,
1948 	DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
1949 	DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
1950 	DRV_TLV_SCSI_STATUS_BUSY_COUNT,
1951 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
1952 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
1953 	DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
1954 	DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
1955 	DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
1956 	DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
1957 	DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
1958 	DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
1959 	DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
1960 	DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
1961 	DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
1962 	DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
1963 	DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
1964 	DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
1965 	DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
1966 	DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
1967 	/* Category 30: iSCSI Function Data */
1968 	DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1969 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1970 	DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
1971 	DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
1972 	DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
1973 	DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
1974 };
1975 
1976 #endif				/* MCP_PUBLIC_H */
1977