1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni 37*14b24e2bSVaishali Kulkarni #ifndef MISC_BITS_H 38*14b24e2bSVaishali Kulkarni #define MISC_BITS_H 39*14b24e2bSVaishali Kulkarni 40*14b24e2bSVaishali Kulkarni /*reset_config*/ 41*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_NCSI (0x1<<0) 42*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_UMAC (0x1<<1) 43*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_MSTAT (0x1<<2) 44*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_CPMU (0x1<<3) 45*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_PXPV_AUTO_MODE (0x1<<4) 46*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_NWM_MAC_CORE (0x1<<5) 47*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RSRV6 (0x1<<6) 48*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_REG_HARD_CORE_AUTO_MODE (0x1<<7) 49*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_HARD_CORE_RST_B_AUTO_MODE (0x1<<8) 50*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CPU_AUTO_MODE (0x1<<9) 51*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CORE_AUTO_MODE (0x1<<10) 52*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RSRV11 (0x1<<11) 53*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RSRV12 (0x1<<12) 54*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RSRV13 (0x1<<13) 55*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MISC_CORE_AUTO_MODE (0x1<<14) 56*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_DBUE_AUTO_MODE (0x1<<15) 57*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_GRC_RESET_ASSERT_ON_CORE_RST (0x1<<16) 58*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CPU_ASSERT_ON_CORE_RST (0x1<<17) 59*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CORE_ASSERT_ON_CORE_RST (0x1<<18) 60*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_RBCN_ASSERT_ON_CORE_RST (0x1<<19) 61*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_NWM_CORE (0x1<<20) 62*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_MISC_CORE_ASSERT_ON_CORE_RST (0x1<<21) 63*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_DBUE_ASSERT_ON_CORE_RST (0x1<<22) 64*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_WRAPPERS_IDDQ_AND_RST_SIGNALS_ASSERT_ON_CORE_RST (0x1<<23) 65*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RBCW (0x1<<24) 66*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_PGLC_AUTO_MODE (0x1<<25) 67*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_BMB_ON_CORE_RST (0x1<<26) 68*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_RST_OPTE_ON_CORE_RST (0x1<<27) 69*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_OPCS (0x1<<28) 70*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_NWS (0x1<<29) 71*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_MS (0x1<<30) 72*14b24e2bSVaishali Kulkarni #define MISCS_REGISTERS_RESET_CONFIG_LED (0x1<<31) 73*14b24e2bSVaishali Kulkarni 74*14b24e2bSVaishali Kulkarni /* MISCS_REG_RESET_PL_UA */ 75*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_SET (MISCS_REG_RESET_PL_UA + 4) 76*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_CLEAR (MISCS_REG_RESET_PL_UA + 8) 77*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_GRC (0x1<<0) 78*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<1) 79*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_MCP_N_HARD_CORE_RST_B (0x1<<2) 80*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_MCP_N_RESET_CMN_CPU (0x1<<3) 81*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_MCP_N_RESET_CMN_CORE (0x1<<4) 82*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_MISC_CORE (0x1<<5) 83*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_DBUE_UART (0x1<<6) 84*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_BMB (0x1<<7) 85*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_IPC (0x1<<8) 86*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_RST_CRBCN (0x1<<9) 87*14b24e2bSVaishali Kulkarni 88*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_UA_PROCESS_KILL (0x0) 89*14b24e2bSVaishali Kulkarni 90*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_SET (MISCS_REG_RESET_PL_HV + 4) 91*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_CLEAR (MISCS_REG_RESET_PL_HV + 8) 92*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_CNIG (0x1<<0) 93*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_PGLC (0x1<<1) 94*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_PXPV (0x1<<2) 95*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_CRBCH (0x1<<3) 96*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_OPTE (0x1<<4) 97*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_NCSI (0x1<<5) 98*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_UMAC (0x1<<6) 99*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_MSTAT (0x1<<7) 100*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_CPMU (0x1<<8) 101*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_RSRV (0x1<<9) 102*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_RBCW (0x1<<10) 103*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_OPCS (0x1<<11) 104*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_NWS (0x1<<12) 105*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_MS (0x1<<13) 106*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_RST_LED (0x1<<14) 107*14b24e2bSVaishali Kulkarni 108*14b24e2bSVaishali Kulkarni 109*14b24e2bSVaishali Kulkarni 110*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_PROCESS_KILL (0x0) 111*14b24e2bSVaishali Kulkarni 112*14b24e2bSVaishali Kulkarni /* MISC_REG_RESET_PL_UA */ 113*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_UA_SET (MISC_REG_RESET_PL_UA + 4) 114*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_UA_CLEAR (MISC_REG_RESET_PL_UA + 8) 115*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_UA_RST_MISC_CORE (0x1<<0) 116*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_UA_RST_GRC (0x1<<1) 117*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_UA_RST_RBCN (0x1<<2) 118*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_UA_RST_RBCZ (0x1<<3) 119*14b24e2bSVaishali Kulkarni 120*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_UA_PROCESS_KILL (0x0) 121*14b24e2bSVaishali Kulkarni 122*14b24e2bSVaishali Kulkarni /* MISC_REG_RESET_PL_HV */ 123*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_SET (MISC_REG_RESET_PL_HV + 4) 124*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_CLEAR (MISC_REG_RESET_PL_HV + 8) 125*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_RST_PSWHST (0x1<<0) 126*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_RST_PSWRQ (0x1<<1) 127*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_RST_PSWRD (0x1<<2) 128*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_RST_PSWWR (0x1<<3) 129*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_RST_ATC (0x1<<4) 130*14b24e2bSVaishali Kulkarni 131*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_HV_PROCESS_KILL \ 132*14b24e2bSVaishali Kulkarni (MISC_REG_RESET_PL_HV_RST_PSWRQ | \ 133*14b24e2bSVaishali Kulkarni MISC_REG_RESET_PL_HV_RST_PSWRD | \ 134*14b24e2bSVaishali Kulkarni MISC_REG_RESET_PL_HV_RST_PSWWR | \ 135*14b24e2bSVaishali Kulkarni MISC_REG_RESET_PL_HV_RST_ATC) 136*14b24e2bSVaishali Kulkarni 137*14b24e2bSVaishali Kulkarni /* PL_HV_2 - for K2 only */ 138*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_SET (MISCS_REG_RESET_PL_HV_2 + 4) 139*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_CLEAR (MISCS_REG_RESET_PL_HV_2 + 8) 140*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM (1<<0) 141*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC0 (1<<1) 142*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC1 (1<<2) 143*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC2 (1<<3) 144*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC3 (1<<4) 145*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS0 (1<<5) 146*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS1 (1<<6) 147*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS2 (1<<7) 148*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS3 (1<<8) 149*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS0 (1<<9) 150*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS1 (1<<10) 151*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS2 (1<<11) 152*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS3 (1<<12) 153*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS4 (1<<13) 154*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS5 (1<<14) 155*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS6 (1<<15) 156*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS7 (1<<16) 157*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE0 (1<<17) 158*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE1 (1<<18) 159*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE2 (1<<19) 160*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE3 (1<<20) 161*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE0 (1<<21) 162*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE1 (1<<22) 163*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE2 (1<<23) 164*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE3 (1<<24) 165*14b24e2bSVaishali Kulkarni #define MISCS_REG_RESET_PL_HV_2_RST_NWM_SDGB (1<<25) 166*14b24e2bSVaishali Kulkarni 167*14b24e2bSVaishali Kulkarni 168*14b24e2bSVaishali Kulkarni /* MISC_REG_RESET_PL_PDA_VMAIN_1 */ 169*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_SET (MISC_REG_RESET_PL_PDA_VMAIN_1 + 4) 170*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_CLEAR (MISC_REG_RESET_PL_PDA_VMAIN_1 + 8) 171*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_BRB (0x1<<0) 172*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PRS (0x1<<1) 173*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_SRC (0x1<<2) 174*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TSDM (0x1<<3) 175*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TSEM (0x1<<4) 176*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TCM (0x1<<5) 177*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCR (0x1<<6) 178*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_USDM (0x1<<7) 179*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_UCM (0x1<<8) 180*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_USEM (0x1<<9) 181*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_BTB (0x1<<10) 182*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PBF_PB1 (0x1<<11) 183*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PBF_PB2 (0x1<<12) 184*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RPB (0x1<<13) 185*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCU (0x1<<14) 186*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PBF (0x1<<15) 187*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_QM (0x1<<16) 188*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TM (0x1<<17) 189*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_DORQ (0x1<<18) 190*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_XCM (0x1<<19) 191*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_XSDM (0x1<<20) 192*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_XSEM (0x1<<21) 193*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCT (0x1<<22) 194*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_CDU (0x1<<23) 195*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_CCFC (0x1<<24) 196*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TCFC (0x1<<25) 197*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCP (0x1<<26) 198*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_IGU (0x1<<27) 199*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_DMAE (0x1<<28) 200*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_SEMI_RTC (0x1<<29) 201*14b24e2bSVaishali Kulkarni 202*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_1_PROCESS_KILL (~MISC_REG_RESET_PL_PDA_VMAIN_1_RST_IGU) 203*14b24e2bSVaishali Kulkarni 204*14b24e2bSVaishali Kulkarni /* MISC_REG_RESET_PL_PDA_VMAIN_2 */ 205*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_SET (MISC_REG_RESET_PL_PDA_VMAIN_2 + 4) 206*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_CLEAR (MISC_REG_RESET_PL_PDA_VMAIN_2 + 8) 207*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCF (0x1<<0) 208*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCX (0x1<<1) 209*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCS (0x1<<2) 210*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MCM (0x1<<3) 211*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PCM (0x1<<4) 212*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YCM (0x1<<5) 213*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MSDM (0x1<<6) 214*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YSDM (0x1<<7) 215*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PSDM (0x1<<8) 216*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MSEM (0x1<<9) 217*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YSEM (0x1<<10) 218*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PSEM (0x1<<11) 219*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_XYLD (0x1<<12) 220*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_TMLD (0x1<<13) 221*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MULD (0x1<<14) 222*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YULD (0x1<<15) 223*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RDIF (0x1<<16) 224*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_TDIF (0x1<<17) 225*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RSS (0x1<<18) 226*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_CAU (0x1<<19) 227*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PTU (0x1<<20) 228*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PRM (0x1<<21) 229*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCY (0x1<<22) 230*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCQ (0x1<<23) 231*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCM (0x1<<24) 232*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCB (0x1<<25) 233*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCV (0x1<<26) 234*14b24e2bSVaishali Kulkarni 235*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VMAIN_2_PROCESS_KILL (0x3FFFFF) 236*14b24e2bSVaishali Kulkarni 237*14b24e2bSVaishali Kulkarni /* MISC_REG_RESET_PL_PDA_VAUX */ 238*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_SET (MISC_REG_RESET_PL_PDA_VAUX + 4) 239*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_CLEAR (MISC_REG_RESET_PL_PDA_VAUX + 8) 240*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_NIG (0x1<<0) 241*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_RBCH (0x1<<1) 242*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_NIG_HARD (0x1<<2) 243*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_DBG (0x1<<3) 244*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_XMAC (0x1<<4) 245*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_XMAC_SOFT (0x1<<5) 246*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_MSTAT_NW (0x1<<6) 247*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_WOL (0x1<<7) 248*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_RST_WOL_HARD (0x1<<8) 249*14b24e2bSVaishali Kulkarni 250*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_PL_PDA_VAUX_PROCESS_KILL \ 251*14b24e2bSVaishali Kulkarni (MISC_REG_RESET_PL_PDA_VAUX_RST_NIG | \ 252*14b24e2bSVaishali Kulkarni MISC_REG_RESET_PL_PDA_VAUX_RST_NIG_HARD ) 253*14b24e2bSVaishali Kulkarni 254*14b24e2bSVaishali Kulkarni #define MISC_REG_RESET_BLOCKS(path, _reg_, _bits_) \ 255*14b24e2bSVaishali Kulkarni do { \ 256*14b24e2bSVaishali Kulkarni REG_WRITE(path, _reg_ ## _CLEAR, _bits_); \ 257*14b24e2bSVaishali Kulkarni REG_WRITE(path, _reg_ ## _SET, _bits_); \ 258*14b24e2bSVaishali Kulkarni } while (0) 259*14b24e2bSVaishali Kulkarni /* MISCS_REG_VAUX_EN_DIS */ 260*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_VALUE (0x3L<<0) 261*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_VALUE_POS 0 262*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_SET (0x3L<<2) 263*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_SET_POS 2 264*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_CLR (0x3L<<4) 265*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_CLR_POS 4 266*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_FLOAT (0x3L<<6) 267*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_FLOAT_POS 6 268*14b24e2bSVaishali Kulkarni 269*14b24e2bSVaishali Kulkarni /* VAUX_EN_DIS pin assignment */ 270*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_EN_L 0x1 /* Bit 0 */ 271*14b24e2bSVaishali Kulkarni #define MISCS_VAUX_DIS_L 0x2 /* Bit 1 */ 272*14b24e2bSVaishali Kulkarni 273*14b24e2bSVaishali Kulkarni #define MISCS_MAIN_SEQ_BYP_SEL_VAUX_B (1<<4) 274*14b24e2bSVaishali Kulkarni ///////////////////////// 275*14b24e2bSVaishali Kulkarni // HW Lock Definitions // 276*14b24e2bSVaishali Kulkarni ///////////////////////// 277*14b24e2bSVaishali Kulkarni 278*14b24e2bSVaishali Kulkarni // Masters 279*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_0 0 280*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_1 1 281*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_2 2 282*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_3 3 283*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_4 4 284*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_5 5 285*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_6 6 286*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_FUNC_7 7 287*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_RESERVED_8 8 288*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_RESERVED_9 9 289*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_RESERVED_10 10 290*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_RESERVED_11 11 291*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_RESERVED_12 12 292*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_HOST_SCRIPTS 13 293*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_MCP_RESET 14 294*14b24e2bSVaishali Kulkarni #define HW_LOCK_MASTER_MCP 15 295*14b24e2bSVaishali Kulkarni 296*14b24e2bSVaishali Kulkarni // Resources 297*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_0 (1 << 0) 298*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_1 (1 << 1) 299*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_2 (1 << 2) 300*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_3 (1 << 3) 301*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_4 (1 << 4) 302*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_5 (1 << 5) 303*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_6 (1 << 6) 304*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_7 (1 << 7) 305*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_8 (1 << 8) 306*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_9 (1 << 9) 307*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_10 (1 << 10) 308*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_11 (1 << 11) 309*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_12 (1 << 12) 310*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_13 (1 << 13) 311*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_14 (1 << 14) 312*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_15 (1 << 15) 313*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_16 (1 << 16) 314*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_17 (1 << 17) 315*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_18 (1 << 18) 316*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_19 (1 << 19) 317*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_20 (1 << 20) 318*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_21 (1 << 21) 319*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_22 (1 << 22) 320*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_23 (1 << 23) 321*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_24 (1 << 24) 322*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_25 (1 << 25) 323*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_RESERVED_26 (1 << 26) 324*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_OEM_0 (1 << 27) 325*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_OEM_1 (1 << 28) 326*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_OEM_2 (1 << 29) 327*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_OEM_3 (1 << 30) 328*14b24e2bSVaishali Kulkarni #define HW_LOCK_RESOURCE_OEM_4 (1 << 31) 329*14b24e2bSVaishali Kulkarni #define HW_LOCK_MAX_RESOURCE_VALUE (31) 330*14b24e2bSVaishali Kulkarni 331*14b24e2bSVaishali Kulkarni 332*14b24e2bSVaishali Kulkarni ///////////////////////// 333*14b24e2bSVaishali Kulkarni // CHIP DEF Definitions // 334*14b24e2bSVaishali Kulkarni ///////////////////////// 335*14b24e2bSVaishali Kulkarni #define MISCS_REG_CHIP_NUM_K2_DRVSIM 0x1628 336*14b24e2bSVaishali Kulkarni #define MISCS_REG_CHIP_NUM_BB_DRVSIM 0x1629 337*14b24e2bSVaishali Kulkarni 338*14b24e2bSVaishali Kulkarni #define MISCS_REG_CHIP_NUM_K2 0x1630 339*14b24e2bSVaishali Kulkarni #define MISCS_REG_CHIP_NUM_BB 0x1634 340*14b24e2bSVaishali Kulkarni #define MISCS_REG_CHIP_NUM_BB_T 0x1635 341*14b24e2bSVaishali Kulkarni 342*14b24e2bSVaishali Kulkarni 343*14b24e2bSVaishali Kulkarni #define CHIP_IS_BB(chip_num) ((chip_num == MISCS_REG_CHIP_NUM_BB_DRVSIM) || (chip_num == MISCS_REG_CHIP_NUM_BB) || (chip_num == MISCS_REG_CHIP_NUM_BB_T)) 344*14b24e2bSVaishali Kulkarni #define CHIP_IS_K2(chip_num) ((chip_num == MISCS_REG_CHIP_NUM_K2_DRVSIM) || (chip_num == MISCS_REG_CHIP_NUM_K2)) 345*14b24e2bSVaishali Kulkarni 346*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_CODE_MASK 0x000003ff 347*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_CODE_SHIFT 0 348*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_OVERRIDE_MASK 0x00000400 349*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_OVERRIDE_SHIFT 10 350*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_CODE_MASK 0x001ff800 351*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_CODE_SHIFT 11 352*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_OVERRIDE_MASK 0x00200000 353*14b24e2bSVaishali Kulkarni #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_OVERRIDE_SHIFT 21 354*14b24e2bSVaishali Kulkarni /* 355*14b24e2bSVaishali Kulkarni * Secured Mode Definitions 356*14b24e2bSVaishali Kulkarni */ 357*14b24e2bSVaishali Kulkarni enum secure_modes { 358*14b24e2bSVaishali Kulkarni SECURITY_MODE_NON_SECURED_MODE = 0, 359*14b24e2bSVaishali Kulkarni SECURITY_MODE_SECURED_MODE = 1, 360*14b24e2bSVaishali Kulkarni SECURITY_MODE_FULLY_SECURED_MODE = 2 361*14b24e2bSVaishali Kulkarni }; 362*14b24e2bSVaishali Kulkarni 363*14b24e2bSVaishali Kulkarni #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_MASK (0x1) 364*14b24e2bSVaishali Kulkarni #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_SHIFT (0) 365*14b24e2bSVaishali Kulkarni #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_EXT_PIN (0) 366*14b24e2bSVaishali Kulkarni #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_OVERRIDE (1) 367*14b24e2bSVaishali Kulkarni 368*14b24e2bSVaishali Kulkarni #define MISCS_REG_MFW_SECURITY_MODE_OVERRIDE_VAL_MASK (0x6) 369*14b24e2bSVaishali Kulkarni #define MISCS_REG_MFW_SECURITY_MODE_OVERRIDE_VAL_SHIFT (0x1) 370*14b24e2bSVaishali Kulkarni /* Values are SECURITY_MODE_XXX */ 371*14b24e2bSVaishali Kulkarni 372*14b24e2bSVaishali Kulkarni /* MISCS_REG_GENERIC_POR_0 definition */ 373*14b24e2bSVaishali Kulkarni #define MISCS_POR_RESET_VAL_SHIFT 0 374*14b24e2bSVaishali Kulkarni #define MISCS_POR_RESET_VAL_MASK 0x00000001 375*14b24e2bSVaishali Kulkarni 376*14b24e2bSVaishali Kulkarni #define MISCS_POR_CNT_SHIFT 1 377*14b24e2bSVaishali Kulkarni #define MISCS_POR_CNT_MASK 0x00000002 378*14b24e2bSVaishali Kulkarni 379*14b24e2bSVaishali Kulkarni #define MISCS_CORE_CNT_SHIFT 2 380*14b24e2bSVaishali Kulkarni #define MISCS_CORE_CNT_MASK 0x000ffffc 381*14b24e2bSVaishali Kulkarni 382*14b24e2bSVaishali Kulkarni #define MISCS_MCP_RESET_CNT_SHIFT 20 383*14b24e2bSVaishali Kulkarni #define MISCS_MCP_RESET_CNT_MASK 0xfff00000 384*14b24e2bSVaishali Kulkarni 385*14b24e2bSVaishali Kulkarni 386*14b24e2bSVaishali Kulkarni #define MISC_REG_BLOCK_256B_EN_K2_BRB (1<<0) 387*14b24e2bSVaishali Kulkarni #define MISC_REG_BLOCK_256B_EN_K2_BTB (1<<1) 388*14b24e2bSVaishali Kulkarni #endif // MISC_BITS_H 389