1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_TOOLS__ 37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_TOOLS__ 38*14b24e2bSVaishali Kulkarni 39*14b24e2bSVaishali Kulkarni /**********************************/ 40*14b24e2bSVaishali Kulkarni /* Tools HSI constants and macros */ 41*14b24e2bSVaishali Kulkarni /**********************************/ 42*14b24e2bSVaishali Kulkarni 43*14b24e2bSVaishali Kulkarni /* Width of GRC address in bits (addresses are specified in dwords) */ 44*14b24e2bSVaishali Kulkarni #define GRC_ADDR_BITS 23 45*14b24e2bSVaishali Kulkarni #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 46*14b24e2bSVaishali Kulkarni 47*14b24e2bSVaishali Kulkarni /* indicates an init that should be applied to any phase ID */ 48*14b24e2bSVaishali Kulkarni #define ANY_PHASE_ID 0xffff 49*14b24e2bSVaishali Kulkarni 50*14b24e2bSVaishali Kulkarni /* init pattern size in bytes */ 51*14b24e2bSVaishali Kulkarni #define INIT_PATTERN_SIZE_BITS 4 52*14b24e2bSVaishali Kulkarni #define MAX_INIT_PATTERN_SIZE (1 << INIT_PATTERN_SIZE_BITS) 53*14b24e2bSVaishali Kulkarni 54*14b24e2bSVaishali Kulkarni /* Max size in dwords of a zipped array */ 55*14b24e2bSVaishali Kulkarni #define MAX_ZIPPED_SIZE 8192 56*14b24e2bSVaishali Kulkarni 57*14b24e2bSVaishali Kulkarni /* Global PXP window */ 58*14b24e2bSVaishali Kulkarni #define NUM_OF_PXP_WIN 19 59*14b24e2bSVaishali Kulkarni #define PXP_WIN_DWORD_SIZE_BITS 10 60*14b24e2bSVaishali Kulkarni #define PXP_WIN_DWORD_SIZE (1 << PXP_WIN_DWORD_SIZE_BITS) 61*14b24e2bSVaishali Kulkarni #define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2) 62*14b24e2bSVaishali Kulkarni #define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4) 63*14b24e2bSVaishali Kulkarni 64*14b24e2bSVaishali Kulkarni 65*14b24e2bSVaishali Kulkarni /* 66*14b24e2bSVaishali Kulkarni * Binary buffer header 67*14b24e2bSVaishali Kulkarni */ 68*14b24e2bSVaishali Kulkarni struct bin_buffer_hdr 69*14b24e2bSVaishali Kulkarni { 70*14b24e2bSVaishali Kulkarni __le32 offset /* buffer offset in bytes from the beginning of the binary file */; 71*14b24e2bSVaishali Kulkarni __le32 length /* buffer length in bytes */; 72*14b24e2bSVaishali Kulkarni }; 73*14b24e2bSVaishali Kulkarni 74*14b24e2bSVaishali Kulkarni 75*14b24e2bSVaishali Kulkarni /* 76*14b24e2bSVaishali Kulkarni * binary buffer types 77*14b24e2bSVaishali Kulkarni */ 78*14b24e2bSVaishali Kulkarni enum bin_buffer_type 79*14b24e2bSVaishali Kulkarni { 80*14b24e2bSVaishali Kulkarni BIN_BUF_FW_VER_INFO /* fw_ver_info struct */, 81*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_CMD /* init commands */, 82*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_VAL /* init data */, 83*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_MODE_TREE /* init modes tree */, 84*14b24e2bSVaishali Kulkarni BIN_BUF_IRO /* internal RAM offsets array */, 85*14b24e2bSVaishali Kulkarni MAX_BIN_BUFFER_TYPE 86*14b24e2bSVaishali Kulkarni }; 87*14b24e2bSVaishali Kulkarni 88*14b24e2bSVaishali Kulkarni 89*14b24e2bSVaishali Kulkarni /* 90*14b24e2bSVaishali Kulkarni * init array header: raw 91*14b24e2bSVaishali Kulkarni */ 92*14b24e2bSVaishali Kulkarni struct init_array_raw_hdr 93*14b24e2bSVaishali Kulkarni { 94*14b24e2bSVaishali Kulkarni __le32 data; 95*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 96*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 97*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 98*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 99*14b24e2bSVaishali Kulkarni }; 100*14b24e2bSVaishali Kulkarni 101*14b24e2bSVaishali Kulkarni 102*14b24e2bSVaishali Kulkarni /* 103*14b24e2bSVaishali Kulkarni * init array header: standard 104*14b24e2bSVaishali Kulkarni */ 105*14b24e2bSVaishali Kulkarni struct init_array_standard_hdr 106*14b24e2bSVaishali Kulkarni { 107*14b24e2bSVaishali Kulkarni __le32 data; 108*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 109*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 110*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 111*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 112*14b24e2bSVaishali Kulkarni }; 113*14b24e2bSVaishali Kulkarni 114*14b24e2bSVaishali Kulkarni 115*14b24e2bSVaishali Kulkarni /* 116*14b24e2bSVaishali Kulkarni * init array header: zipped 117*14b24e2bSVaishali Kulkarni */ 118*14b24e2bSVaishali Kulkarni struct init_array_zipped_hdr 119*14b24e2bSVaishali Kulkarni { 120*14b24e2bSVaishali Kulkarni __le32 data; 121*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 122*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 123*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 124*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 125*14b24e2bSVaishali Kulkarni }; 126*14b24e2bSVaishali Kulkarni 127*14b24e2bSVaishali Kulkarni 128*14b24e2bSVaishali Kulkarni /* 129*14b24e2bSVaishali Kulkarni * init array header: pattern 130*14b24e2bSVaishali Kulkarni */ 131*14b24e2bSVaishali Kulkarni struct init_array_pattern_hdr 132*14b24e2bSVaishali Kulkarni { 133*14b24e2bSVaishali Kulkarni __le32 data; 134*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 135*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 136*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 137*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 138*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 139*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 140*14b24e2bSVaishali Kulkarni }; 141*14b24e2bSVaishali Kulkarni 142*14b24e2bSVaishali Kulkarni 143*14b24e2bSVaishali Kulkarni /* 144*14b24e2bSVaishali Kulkarni * init array header union 145*14b24e2bSVaishali Kulkarni */ 146*14b24e2bSVaishali Kulkarni union init_array_hdr 147*14b24e2bSVaishali Kulkarni { 148*14b24e2bSVaishali Kulkarni struct init_array_raw_hdr raw /* raw init array header */; 149*14b24e2bSVaishali Kulkarni struct init_array_standard_hdr standard /* standard init array header */; 150*14b24e2bSVaishali Kulkarni struct init_array_zipped_hdr zipped /* zipped init array header */; 151*14b24e2bSVaishali Kulkarni struct init_array_pattern_hdr pattern /* pattern init array header */; 152*14b24e2bSVaishali Kulkarni }; 153*14b24e2bSVaishali Kulkarni 154*14b24e2bSVaishali Kulkarni 155*14b24e2bSVaishali Kulkarni /* 156*14b24e2bSVaishali Kulkarni * init array types 157*14b24e2bSVaishali Kulkarni */ 158*14b24e2bSVaishali Kulkarni enum init_array_types 159*14b24e2bSVaishali Kulkarni { 160*14b24e2bSVaishali Kulkarni INIT_ARR_STANDARD /* standard init array */, 161*14b24e2bSVaishali Kulkarni INIT_ARR_ZIPPED /* zipped init array */, 162*14b24e2bSVaishali Kulkarni INIT_ARR_PATTERN /* a repeated pattern */, 163*14b24e2bSVaishali Kulkarni MAX_INIT_ARRAY_TYPES 164*14b24e2bSVaishali Kulkarni }; 165*14b24e2bSVaishali Kulkarni 166*14b24e2bSVaishali Kulkarni 167*14b24e2bSVaishali Kulkarni /* 168*14b24e2bSVaishali Kulkarni * init operation: callback 169*14b24e2bSVaishali Kulkarni */ 170*14b24e2bSVaishali Kulkarni struct init_callback_op 171*14b24e2bSVaishali Kulkarni { 172*14b24e2bSVaishali Kulkarni __le32 op_data; 173*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 174*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_OP_SHIFT 0 175*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 176*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 177*14b24e2bSVaishali Kulkarni __le16 callback_id /* Callback ID */; 178*14b24e2bSVaishali Kulkarni __le16 block_id /* Blocks ID */; 179*14b24e2bSVaishali Kulkarni }; 180*14b24e2bSVaishali Kulkarni 181*14b24e2bSVaishali Kulkarni 182*14b24e2bSVaishali Kulkarni /* 183*14b24e2bSVaishali Kulkarni * init operation: delay 184*14b24e2bSVaishali Kulkarni */ 185*14b24e2bSVaishali Kulkarni struct init_delay_op 186*14b24e2bSVaishali Kulkarni { 187*14b24e2bSVaishali Kulkarni __le32 op_data; 188*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 189*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_OP_SHIFT 0 190*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 191*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_RESERVED_SHIFT 4 192*14b24e2bSVaishali Kulkarni __le32 delay /* delay in us */; 193*14b24e2bSVaishali Kulkarni }; 194*14b24e2bSVaishali Kulkarni 195*14b24e2bSVaishali Kulkarni 196*14b24e2bSVaishali Kulkarni /* 197*14b24e2bSVaishali Kulkarni * init operation: if_mode 198*14b24e2bSVaishali Kulkarni */ 199*14b24e2bSVaishali Kulkarni struct init_if_mode_op 200*14b24e2bSVaishali Kulkarni { 201*14b24e2bSVaishali Kulkarni __le32 op_data; 202*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 203*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_OP_SHIFT 0 204*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 205*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 206*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 207*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 208*14b24e2bSVaishali Kulkarni __le16 reserved2; 209*14b24e2bSVaishali Kulkarni __le16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 210*14b24e2bSVaishali Kulkarni }; 211*14b24e2bSVaishali Kulkarni 212*14b24e2bSVaishali Kulkarni 213*14b24e2bSVaishali Kulkarni /* 214*14b24e2bSVaishali Kulkarni * init operation: if_phase 215*14b24e2bSVaishali Kulkarni */ 216*14b24e2bSVaishali Kulkarni struct init_if_phase_op 217*14b24e2bSVaishali Kulkarni { 218*14b24e2bSVaishali Kulkarni __le32 op_data; 219*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 220*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_OP_SHIFT 0 221*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 222*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 223*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 224*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 225*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 226*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 227*14b24e2bSVaishali Kulkarni __le32 phase_data; 228*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 229*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 230*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 231*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 232*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 233*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 234*14b24e2bSVaishali Kulkarni }; 235*14b24e2bSVaishali Kulkarni 236*14b24e2bSVaishali Kulkarni 237*14b24e2bSVaishali Kulkarni /* 238*14b24e2bSVaishali Kulkarni * init mode operators 239*14b24e2bSVaishali Kulkarni */ 240*14b24e2bSVaishali Kulkarni enum init_mode_ops 241*14b24e2bSVaishali Kulkarni { 242*14b24e2bSVaishali Kulkarni INIT_MODE_OP_NOT /* init mode not operator */, 243*14b24e2bSVaishali Kulkarni INIT_MODE_OP_OR /* init mode or operator */, 244*14b24e2bSVaishali Kulkarni INIT_MODE_OP_AND /* init mode and operator */, 245*14b24e2bSVaishali Kulkarni MAX_INIT_MODE_OPS 246*14b24e2bSVaishali Kulkarni }; 247*14b24e2bSVaishali Kulkarni 248*14b24e2bSVaishali Kulkarni 249*14b24e2bSVaishali Kulkarni /* 250*14b24e2bSVaishali Kulkarni * init operation: raw 251*14b24e2bSVaishali Kulkarni */ 252*14b24e2bSVaishali Kulkarni struct init_raw_op 253*14b24e2bSVaishali Kulkarni { 254*14b24e2bSVaishali Kulkarni __le32 op_data; 255*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 256*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_OP_SHIFT 0 257*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 258*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_PARAM1_SHIFT 4 259*14b24e2bSVaishali Kulkarni __le32 param2 /* Init param 2 */; 260*14b24e2bSVaishali Kulkarni }; 261*14b24e2bSVaishali Kulkarni 262*14b24e2bSVaishali Kulkarni 263*14b24e2bSVaishali Kulkarni /* 264*14b24e2bSVaishali Kulkarni * init array params 265*14b24e2bSVaishali Kulkarni */ 266*14b24e2bSVaishali Kulkarni struct init_op_array_params 267*14b24e2bSVaishali Kulkarni { 268*14b24e2bSVaishali Kulkarni __le16 size /* array size in dwords */; 269*14b24e2bSVaishali Kulkarni __le16 offset /* array start offset in dwords */; 270*14b24e2bSVaishali Kulkarni }; 271*14b24e2bSVaishali Kulkarni 272*14b24e2bSVaishali Kulkarni 273*14b24e2bSVaishali Kulkarni /* 274*14b24e2bSVaishali Kulkarni * Write init operation arguments 275*14b24e2bSVaishali Kulkarni */ 276*14b24e2bSVaishali Kulkarni union init_write_args 277*14b24e2bSVaishali Kulkarni { 278*14b24e2bSVaishali Kulkarni __le32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 279*14b24e2bSVaishali Kulkarni __le32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 280*14b24e2bSVaishali Kulkarni __le32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 281*14b24e2bSVaishali Kulkarni struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 282*14b24e2bSVaishali Kulkarni }; 283*14b24e2bSVaishali Kulkarni 284*14b24e2bSVaishali Kulkarni 285*14b24e2bSVaishali Kulkarni /* 286*14b24e2bSVaishali Kulkarni * init operation: write 287*14b24e2bSVaishali Kulkarni */ 288*14b24e2bSVaishali Kulkarni struct init_write_op 289*14b24e2bSVaishali Kulkarni { 290*14b24e2bSVaishali Kulkarni __le32 data; 291*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 292*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_OP_SHIFT 0 293*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 294*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_SOURCE_SHIFT 4 295*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_RESERVED_MASK 0x1 296*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_RESERVED_SHIFT 7 297*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 298*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 299*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 300*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_ADDRESS_SHIFT 9 301*14b24e2bSVaishali Kulkarni union init_write_args args /* Write init operation arguments */; 302*14b24e2bSVaishali Kulkarni }; 303*14b24e2bSVaishali Kulkarni 304*14b24e2bSVaishali Kulkarni 305*14b24e2bSVaishali Kulkarni /* 306*14b24e2bSVaishali Kulkarni * init operation: read 307*14b24e2bSVaishali Kulkarni */ 308*14b24e2bSVaishali Kulkarni struct init_read_op 309*14b24e2bSVaishali Kulkarni { 310*14b24e2bSVaishali Kulkarni __le32 op_data; 311*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 312*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_OP_SHIFT 0 313*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 314*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_POLL_TYPE_SHIFT 4 315*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_RESERVED_MASK 0x1 316*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_RESERVED_SHIFT 8 317*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 318*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_ADDRESS_SHIFT 9 319*14b24e2bSVaishali Kulkarni __le32 expected_val /* expected polling value, used only when polling is done */; 320*14b24e2bSVaishali Kulkarni }; 321*14b24e2bSVaishali Kulkarni 322*14b24e2bSVaishali Kulkarni 323*14b24e2bSVaishali Kulkarni /* 324*14b24e2bSVaishali Kulkarni * Init operations union 325*14b24e2bSVaishali Kulkarni */ 326*14b24e2bSVaishali Kulkarni union init_op 327*14b24e2bSVaishali Kulkarni { 328*14b24e2bSVaishali Kulkarni struct init_raw_op raw /* raw init operation */; 329*14b24e2bSVaishali Kulkarni struct init_write_op write /* write init operation */; 330*14b24e2bSVaishali Kulkarni struct init_read_op read /* read init operation */; 331*14b24e2bSVaishali Kulkarni struct init_if_mode_op if_mode /* if_mode init operation */; 332*14b24e2bSVaishali Kulkarni struct init_if_phase_op if_phase /* if_phase init operation */; 333*14b24e2bSVaishali Kulkarni struct init_callback_op callback /* callback init operation */; 334*14b24e2bSVaishali Kulkarni struct init_delay_op delay /* delay init operation */; 335*14b24e2bSVaishali Kulkarni }; 336*14b24e2bSVaishali Kulkarni 337*14b24e2bSVaishali Kulkarni 338*14b24e2bSVaishali Kulkarni /* 339*14b24e2bSVaishali Kulkarni * Init command operation types 340*14b24e2bSVaishali Kulkarni */ 341*14b24e2bSVaishali Kulkarni enum init_op_types 342*14b24e2bSVaishali Kulkarni { 343*14b24e2bSVaishali Kulkarni INIT_OP_READ /* GRC read init command */, 344*14b24e2bSVaishali Kulkarni INIT_OP_WRITE /* GRC write init command */, 345*14b24e2bSVaishali Kulkarni INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 346*14b24e2bSVaishali Kulkarni INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 347*14b24e2bSVaishali Kulkarni INIT_OP_DELAY /* delay init command */, 348*14b24e2bSVaishali Kulkarni INIT_OP_CALLBACK /* callback init command */, 349*14b24e2bSVaishali Kulkarni MAX_INIT_OP_TYPES 350*14b24e2bSVaishali Kulkarni }; 351*14b24e2bSVaishali Kulkarni 352*14b24e2bSVaishali Kulkarni 353*14b24e2bSVaishali Kulkarni /* 354*14b24e2bSVaishali Kulkarni * init polling types 355*14b24e2bSVaishali Kulkarni */ 356*14b24e2bSVaishali Kulkarni enum init_poll_types 357*14b24e2bSVaishali Kulkarni { 358*14b24e2bSVaishali Kulkarni INIT_POLL_NONE /* No polling */, 359*14b24e2bSVaishali Kulkarni INIT_POLL_EQ /* init value is included in the init command */, 360*14b24e2bSVaishali Kulkarni INIT_POLL_OR /* init value is all zeros */, 361*14b24e2bSVaishali Kulkarni INIT_POLL_AND /* init value is an array of values */, 362*14b24e2bSVaishali Kulkarni MAX_INIT_POLL_TYPES 363*14b24e2bSVaishali Kulkarni }; 364*14b24e2bSVaishali Kulkarni 365*14b24e2bSVaishali Kulkarni 366*14b24e2bSVaishali Kulkarni /* 367*14b24e2bSVaishali Kulkarni * init source types 368*14b24e2bSVaishali Kulkarni */ 369*14b24e2bSVaishali Kulkarni enum init_source_types 370*14b24e2bSVaishali Kulkarni { 371*14b24e2bSVaishali Kulkarni INIT_SRC_INLINE /* init value is included in the init command */, 372*14b24e2bSVaishali Kulkarni INIT_SRC_ZEROS /* init value is all zeros */, 373*14b24e2bSVaishali Kulkarni INIT_SRC_ARRAY /* init value is an array of values */, 374*14b24e2bSVaishali Kulkarni INIT_SRC_RUNTIME /* init value is provided during runtime */, 375*14b24e2bSVaishali Kulkarni MAX_INIT_SOURCE_TYPES 376*14b24e2bSVaishali Kulkarni }; 377*14b24e2bSVaishali Kulkarni 378*14b24e2bSVaishali Kulkarni 379*14b24e2bSVaishali Kulkarni struct fw_ver_num 380*14b24e2bSVaishali Kulkarni { 381*14b24e2bSVaishali Kulkarni u8 major /* Firmware major version number */; 382*14b24e2bSVaishali Kulkarni u8 minor /* Firmware minor version number */; 383*14b24e2bSVaishali Kulkarni u8 rev /* Firmware revision version number */; 384*14b24e2bSVaishali Kulkarni u8 eng /* Firmware engineering version number (for bootleg verisons) */; 385*14b24e2bSVaishali Kulkarni }; 386*14b24e2bSVaishali Kulkarni 387*14b24e2bSVaishali Kulkarni 388*14b24e2bSVaishali Kulkarni struct fw_ver_params 389*14b24e2bSVaishali Kulkarni { 390*14b24e2bSVaishali Kulkarni u8 image_id /* Firmware image ID */; 391*14b24e2bSVaishali Kulkarni u8 storm_id /* Storm ID */; 392*14b24e2bSVaishali Kulkarni u8 chip_ver /* Chip version number */; 393*14b24e2bSVaishali Kulkarni u8 reserved; 394*14b24e2bSVaishali Kulkarni }; 395*14b24e2bSVaishali Kulkarni 396*14b24e2bSVaishali Kulkarni 397*14b24e2bSVaishali Kulkarni struct fw_ver_info 398*14b24e2bSVaishali Kulkarni { 399*14b24e2bSVaishali Kulkarni __le16 tools_ver /* Tools version number */; 400*14b24e2bSVaishali Kulkarni __le16 reserved; 401*14b24e2bSVaishali Kulkarni struct fw_ver_num num; 402*14b24e2bSVaishali Kulkarni struct fw_ver_params params; 403*14b24e2bSVaishali Kulkarni __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; 404*14b24e2bSVaishali Kulkarni }; 405*14b24e2bSVaishali Kulkarni 406*14b24e2bSVaishali Kulkarni 407*14b24e2bSVaishali Kulkarni enum init_modes 408*14b24e2bSVaishali Kulkarni { 409*14b24e2bSVaishali Kulkarni MODE_BB_A0, 410*14b24e2bSVaishali Kulkarni MODE_BB_B0, 411*14b24e2bSVaishali Kulkarni MODE_K2, 412*14b24e2bSVaishali Kulkarni MODE_ASIC, 413*14b24e2bSVaishali Kulkarni MODE_EMUL_REDUCED, 414*14b24e2bSVaishali Kulkarni MODE_EMUL_FULL, 415*14b24e2bSVaishali Kulkarni MODE_FPGA, 416*14b24e2bSVaishali Kulkarni MODE_CHIPSIM, 417*14b24e2bSVaishali Kulkarni MODE_SF, 418*14b24e2bSVaishali Kulkarni MODE_MF_SD, 419*14b24e2bSVaishali Kulkarni MODE_MF_SI, 420*14b24e2bSVaishali Kulkarni MODE_PORTS_PER_ENG_1, 421*14b24e2bSVaishali Kulkarni MODE_PORTS_PER_ENG_2, 422*14b24e2bSVaishali Kulkarni MODE_PORTS_PER_ENG_4, 423*14b24e2bSVaishali Kulkarni MODE_100G, 424*14b24e2bSVaishali Kulkarni MODE_EAGLE_ENG1_WORKAROUND, 425*14b24e2bSVaishali Kulkarni MAX_INIT_MODES 426*14b24e2bSVaishali Kulkarni }; 427*14b24e2bSVaishali Kulkarni 428*14b24e2bSVaishali Kulkarni 429*14b24e2bSVaishali Kulkarni enum init_phases 430*14b24e2bSVaishali Kulkarni { 431*14b24e2bSVaishali Kulkarni PHASE_ENGINE, 432*14b24e2bSVaishali Kulkarni PHASE_PORT, 433*14b24e2bSVaishali Kulkarni PHASE_PF, 434*14b24e2bSVaishali Kulkarni PHASE_VF, 435*14b24e2bSVaishali Kulkarni PHASE_QM_PF, 436*14b24e2bSVaishali Kulkarni MAX_INIT_PHASES 437*14b24e2bSVaishali Kulkarni }; 438*14b24e2bSVaishali Kulkarni 439*14b24e2bSVaishali Kulkarni 440*14b24e2bSVaishali Kulkarni #endif /* __ECORE_HSI_TOOLS__ */ 441