xref: /illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/aeu_inputs.h (revision 14b24e2b79293068c8e016a69ef1d872fb5e2fd5)
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 /****************************************************************************
37  * Name:        aeu_inputs.h
38  *
39  * Description: This file contains the AEU inputs bits definitions which
40  *              should be used to configure the MISC_REGISTERS_AEU_ENABLE
41  *              registers.
42  *              The file was based upon the AEU specification.
43  *
44  * Created:     5/17/2015 yrosner
45  *
46  ****************************************************************************/
47 #ifndef AEU_INPUTS_H
48 #define AEU_INPUTS_H
49 
50 /* AEU INPUT REGISTER 1 */
51 #define AEU_INPUT1_BITS_GPIO0				(1<<0)
52 #define AEU_INPUT1_BITS_GPIO1				(1<<1)
53 #define AEU_INPUT1_BITS_GPIO2				(1<<2)
54 #define AEU_INPUT1_BITS_GPIO3				(1<<3)
55 #define AEU_INPUT1_BITS_GPIO4				(1<<4)
56 #define AEU_INPUT1_BITS_GPIO5				(1<<5)
57 #define AEU_INPUT1_BITS_GPIO6				(1<<6)
58 #define AEU_INPUT1_BITS_GPIO7				(1<<7)
59 #define AEU_INPUT1_BITS_GPIO8				(1<<8)
60 #define AEU_INPUT1_BITS_GPIO9				(1<<9)
61 #define AEU_INPUT1_BITS_GPIO10				(1<<10)
62 #define AEU_INPUT1_BITS_GPIO11				(1<<11)
63 #define AEU_INPUT1_BITS_GPIO12				(1<<12)
64 #define AEU_INPUT1_BITS_GPIO13				(1<<13)
65 #define AEU_INPUT1_BITS_GPIO14				(1<<14)
66 #define AEU_INPUT1_BITS_GPIO15				(1<<15)
67 #define AEU_INPUT1_BITS_GPIO16				(1<<16)
68 #define AEU_INPUT1_BITS_GPIO17				(1<<17)
69 #define AEU_INPUT1_BITS_GPIO18				(1<<18)
70 #define AEU_INPUT1_BITS_GPIO19				(1<<19)
71 #define AEU_INPUT1_BITS_GPIO20				(1<<20)
72 #define AEU_INPUT1_BITS_GPIO21				(1<<21)
73 #define AEU_INPUT1_BITS_GPIO22				(1<<22)
74 #define AEU_INPUT1_BITS_GPIO23				(1<<23)
75 #define AEU_INPUT1_BITS_GPIO24				(1<<24)
76 #define AEU_INPUT1_BITS_GPIO25				(1<<25)
77 #define AEU_INPUT1_BITS_GPIO26				(1<<26)
78 #define AEU_INPUT1_BITS_GPIO27				(1<<27)
79 #define AEU_INPUT1_BITS_GPIO28				(1<<28)
80 #define AEU_INPUT1_BITS_GPIO29				(1<<29)
81 #define AEU_INPUT1_BITS_GPIO30				(1<<30)
82 #define AEU_INPUT1_BITS_GPIO31				(1<<31)
83 
84 #define AEU_INPUT1_BITS_PARITY_ERROR (0)
85 #define AEU_INPUT1_BITS_PARITY_COMMON_BLOCKS (0)
86 
87 /* AEU INPUT REGISTER 2 */
88 #define AEU_INPUT2_BITS_PGLUE_CONFIG_SPACE		(1<<0)
89 #define AEU_INPUT2_BITS_PGLUE_MISC_FLR			(1<<1)
90 #define AEU_INPUT2_BITS_PGLUE_B_RBC_PARITY_ERROR	(1<<2)
91 #define AEU_INPUT2_BITS_PGLUE_B_RBC_HW_INTERRUPT	(1<<3)
92 #define AEU_INPUT2_BITS_PGLUE_MISC_MCTP_ATTN		(1<<4)
93 #define AEU_INPUT2_BITS_FLASH_EVENT			(1<<5)
94 #define AEU_INPUT2_BITS_SMB_EVENT			(1<<6)
95 #define AEU_INPUT2_BITS_MAIN_POWER_INTERRUPT		(1<<7)
96 #define AEU_INPUT2_BITS_SW_TIMERS_1			(1<<8)
97 #define AEU_INPUT2_BITS_SW_TIMERS_2			(1<<9)
98 #define AEU_INPUT2_BITS_SW_TIMERS_3			(1<<10)
99 #define AEU_INPUT2_BITS_SW_TIMERS_4			(1<<11)
100 #define AEU_INPUT2_BITS_SW_TIMERS_5			(1<<12)
101 #define AEU_INPUT2_BITS_SW_TIMERS_6			(1<<13)
102 #define AEU_INPUT2_BITS_SW_TIMERS_7			(1<<14)
103 #define AEU_INPUT2_BITS_SW_TIMERS_8			(1<<15)
104 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_0	(1<<16)
105 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_1	(1<<17)
106 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_2	(1<<18)
107 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_3	(1<<19)
108 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_4	(1<<20)
109 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_5	(1<<21)
110 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_6	(1<<22)
111 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_7	(1<<23)
112 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_8	(1<<24)
113 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_9	(1<<25)
114 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_10	(1<<26)
115 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_11	(1<<27)
116 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_12	(1<<28)
117 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_13	(1<<29)
118 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_14	(1<<30)
119 #define AEU_INPUT2_BITS_PCIE_GLUE_OR_PXP_VPD_EVENT_15	(1<<31)
120 
121 #define AEU_INPUT2_BITS_GENERATE_SYSTEM_KILL \
122 	(AEU_INPUT2_BITS_PGLUE_B_RBC_PARITY_ERROR)
123 
124 #define AEU_INPUT2_BITS_PARITY_ERROR \
125 	(AEU_INPUT2_BITS_PGLUE_B_RBC_PARITY_ERROR)
126 
127 #define AEU_INPUT2_BITS_PARITY_COMMON_BLOCKS \
128 	(AEU_INPUT2_BITS_PGLUE_B_RBC_PARITY_ERROR)
129 
130 /* AEU INPUT REGISTER 3 */
131 #define AEU_INPUT3_BITS_GENERAL_ATTN0			(1<<0)
132 #define AEU_INPUT3_BITS_GENERAL_ATTN1			(1<<1)
133 #define AEU_INPUT3_BITS_GENERAL_ATTN2			(1<<2)
134 #define AEU_INPUT3_BITS_GENERAL_ATTN3			(1<<3)
135 #define AEU_INPUT3_BITS_GENERAL_ATTN4			(1<<4)
136 #define AEU_INPUT3_BITS_GENERAL_ATTN5			(1<<5)
137 #define AEU_INPUT3_BITS_GENERAL_ATTN6			(1<<6)
138 #define AEU_INPUT3_BITS_GENERAL_ATTN7			(1<<7)
139 #define AEU_INPUT3_BITS_GENERAL_ATTN8			(1<<8)
140 #define AEU_INPUT3_BITS_GENERAL_ATTN9			(1<<9)
141 #define AEU_INPUT3_BITS_GENERAL_ATTN10			(1<<10)
142 #define AEU_INPUT3_BITS_GENERAL_ATTN11			(1<<11)
143 #define AEU_INPUT3_BITS_GENERAL_ATTN12			(1<<12)
144 #define AEU_INPUT3_BITS_GENERAL_ATTN13			(1<<13)
145 #define AEU_INPUT3_BITS_GENERAL_ATTN14			(1<<14)
146 #define AEU_INPUT3_BITS_GENERAL_ATTN15			(1<<15)
147 #define AEU_INPUT3_BITS_GENERAL_ATTN16			(1<<16)
148 #define AEU_INPUT3_BITS_GENERAL_ATTN17			(1<<17)
149 #define AEU_INPUT3_BITS_GENERAL_ATTN18			(1<<18)
150 #define AEU_INPUT3_BITS_GENERAL_ATTN19			(1<<19)
151 #define AEU_INPUT3_BITS_GENERAL_ATTN20			(1<<20)
152 #define AEU_INPUT3_BITS_GENERAL_ATTN21			(1<<21)
153 #define AEU_INPUT3_BITS_GENERAL_ATTN22			(1<<22)
154 #define AEU_INPUT3_BITS_GENERAL_ATTN23			(1<<23)
155 #define AEU_INPUT3_BITS_GENERAL_ATTN24			(1<<24)
156 #define AEU_INPUT3_BITS_GENERAL_ATTN25			(1<<25)
157 #define AEU_INPUT3_BITS_GENERAL_ATTN26			(1<<26)
158 #define AEU_INPUT3_BITS_GENERAL_ATTN27			(1<<27)
159 #define AEU_INPUT3_BITS_GENERAL_ATTN28			(1<<28)
160 #define AEU_INPUT3_BITS_GENERAL_ATTN29			(1<<29)
161 #define AEU_INPUT3_BITS_GENERAL_ATTN30			(1<<30)
162 #define AEU_INPUT3_BITS_GENERAL_ATTN31			(1<<31)
163 
164 #define AEU_INPUT3_BITS_PARITY_ERROR (0)
165 #define AEU_INPUT3_BITS_PARITY_COMMON_BLOCKS (0)
166 
167 /* AEU INPUT REGISTER 4 */
168 #define AEU_INPUT4_BITS_GENERAL_ATTN32			(1<<0)
169 #define AEU_INPUT4_BITS_GENERAL_ATTN33			(1<<1)
170 #define AEU_INPUT4_BITS_GENERAL_ATTN34			(1<<2)
171 #define AEU_INPUT4_BITS_GENERAL_ATTN35			(1<<3) /* Driver initiate recovery flow */
172 #define AEU_INPUT4_BITS_CNIG_ATTN_PORT_0		(1<<4)
173 #define AEU_INPUT4_BITS_CNIG_ATTN_PORT_1		(1<<5)
174 #define AEU_INPUT4_BITS_CNIG_ATTN_PORT_2		(1<<6)
175 #define AEU_INPUT4_BITS_CNIG_ATTN_PORT_3		(1<<7)
176 #define AEU_INPUT4_BITS_MCP_CPU_EVENT			(1<<8)
177 #define AEU_INPUT4_BITS_MCP_WATCHDOG_TIMER		(1<<9)
178 #define AEU_INPUT4_BITS_MCP_M2P_ATTN			(1<<10)
179 #define AEU_INPUT4_BITS_AVS_STOP_STATUS_READY		(1<<11)
180 #define AEU_INPUT4_BITS_MSTAT_PARITY_ERROR		(1<<12)
181 #define AEU_INPUT4_BITS_MSTAT_HW_INTERRUPT		(1<<13)
182 #define AEU_INPUT4_BITS_MSTAT_PER_PATH_PARITY_ERROR	(1<<14)
183 #define AEU_INPUT4_BITS_MSTAT_PER_PATH_HW_INTERRUPT	(1<<15)
184 #define AEU_INPUT4_BITS_OPTE_PARITY_ERROR		(1<<16)
185 #define AEU_INPUT4_BITS_MCP_PARITY_ERROR		(1<<17)
186 #define AEU_INPUT4_BITS_RSRV18				(1<<18)
187 #define AEU_INPUT4_BITS_RSRV19				(1<<19)
188 #define AEU_INPUT4_BITS_RSRV20				(1<<20)
189 #define AEU_INPUT4_BITS_BMBN_HW_INTERRUPT		(1<<21)
190 #define AEU_INPUT4_BITS_NIG_PARITY_ERROR		(1<<22)
191 #define AEU_INPUT4_BITS_NIG_HW_INTERRUPT		(1<<23)
192 #define AEU_INPUT4_BITS_BMB_PARITY_ERROR		(1<<24)
193 #define AEU_INPUT4_BITS_BMB_HW_INTERRUPT		(1<<25)
194 #define AEU_INPUT4_BITS_BTB_PARITY_ERROR		(1<<26)
195 #define AEU_INPUT4_BITS_BTB_HW_INTERRUPT		(1<<27)
196 #define AEU_INPUT4_BITS_BRB_PARITY_ERROR		(1<<28)
197 #define AEU_INPUT4_BITS_BRB_HW_INTERRUPT		(1<<29)
198 #define AEU_INPUT4_BITS_PRS_PARITY_ERROR		(1<<30)
199 #define AEU_INPUT4_BITS_PRS_HW_INTERRUPT		(1<<31)
200 
201 #define AEU_INPUT4_BITS_GENERATE_SYSTEM_KILL \
202 	(AEU_INPUT4_BITS_OPTE_PARITY_ERROR | \
203 	 AEU_INPUT4_BITS_MSTAT_PARITY_ERROR | \
204 	 AEU_INPUT4_BITS_MSTAT_PER_PATH_PARITY_ERROR | \
205 	 AEU_INPUT4_BITS_MCP_PARITY_ERROR | \
206 	 AEU_INPUT4_BITS_NIG_PARITY_ERROR | \
207 	 AEU_INPUT4_BITS_BMB_PARITY_ERROR)
208 
209 #define AEU_INPUT4_BITS_GENERATE_PROCESS_KILL \
210 	(AEU_INPUT4_BITS_GENERAL_ATTN35 | \
211 	 AEU_INPUT4_BITS_BTB_PARITY_ERROR | \
212 	 AEU_INPUT4_BITS_BRB_PARITY_ERROR | \
213 	 AEU_INPUT4_BITS_PRS_PARITY_ERROR)
214 
215 /* General ATTN35 is for the driver to trigger recovery flow */
216 #define AEU_INPUT4_BITS_PARITY_ERROR \
217 	(AEU_INPUT4_BITS_GENERATE_SYSTEM_KILL | \
218 	 AEU_INPUT4_BITS_GENERATE_PROCESS_KILL)
219 
220 #define AEU_INPUT4_BITS_PARITY_COMMON_BLOCKS \
221 	 (AEU_INPUT4_BITS_OPTE_PARITY_ERROR | \
222 	  AEU_INPUT4_BITS_MSTAT_PARITY_ERROR | \
223 	  AEU_INPUT4_BITS_MSTAT_PER_PATH_PARITY_ERROR | \
224 	  AEU_INPUT4_BITS_MCP_PARITY_ERROR)
225 
226 /* AEU INPUT REGISTER 5 */
227 #define AEU_INPUT5_BITS_SRC_PARITY_ERROR		(1<<0)
228 #define AEU_INPUT5_BITS_SRC_HW_INTERRUPT		(1<<1)
229 #define AEU_INPUT5_BITS_PB_CLIENT1_PARITY_ERROR		(1<<2)
230 #define AEU_INPUT5_BITS_PB_CLIENT1_HW_INTERRUPT		(1<<3)
231 #define AEU_INPUT5_BITS_PB_CLIENT2_PARITY_ERROR		(1<<4)
232 #define AEU_INPUT5_BITS_PB_CLIENT2_HW_INTERRUPT		(1<<5)
233 #define AEU_INPUT5_BITS_RPB_PARITY_ERROR		(1<<6)
234 #define AEU_INPUT5_BITS_RPB_HW_INTERRUPT		(1<<7)
235 #define AEU_INPUT5_BITS_PBF_PARITY_ERROR		(1<<8)
236 #define AEU_INPUT5_BITS_PBF_HW_INTERRUPT		(1<<9)
237 #define AEU_INPUT5_BITS_QM_PARITY_ERROR			(1<<10)
238 #define AEU_INPUT5_BITS_QM_HW_INTERRUPT			(1<<11)
239 #define AEU_INPUT5_BITS_TM_PARITY_ERROR			(1<<12)
240 #define AEU_INPUT5_BITS_TM_HW_INTERRUPT			(1<<13)
241 #define AEU_INPUT5_BITS_MCM_PARITY_ERROR		(1<<14)
242 #define AEU_INPUT5_BITS_MCM_HW_INTERRUPT		(1<<15)
243 #define AEU_INPUT5_BITS_MSDM_PARITY_ERROR		(1<<16)
244 #define AEU_INPUT5_BITS_MSDM_HW_INTERRUPT		(1<<17)
245 #define AEU_INPUT5_BITS_MSEM_PARITY_ERROR		(1<<18)
246 #define AEU_INPUT5_BITS_MSEM_HW_INTERRUPT		(1<<19)
247 #define AEU_INPUT5_BITS_PCM_PARITY_ERROR		(1<<20)
248 #define AEU_INPUT5_BITS_PCM_HW_INTERRUPT		(1<<21)
249 #define AEU_INPUT5_BITS_PSDM_PARITY_ERROR		(1<<22)
250 #define AEU_INPUT5_BITS_PSDM_HW_INTERRUPT		(1<<23)
251 #define AEU_INPUT5_BITS_PSEM_PARITY_ERROR		(1<<24)
252 #define AEU_INPUT5_BITS_PSEM_HW_INTERRUPT		(1<<25)
253 #define AEU_INPUT5_BITS_TCM_PARITY_ERROR		(1<<26)
254 #define AEU_INPUT5_BITS_TCM_HW_INTERRUPT		(1<<27)
255 #define AEU_INPUT5_BITS_TSDM_PARITY_ERROR		(1<<28)
256 #define AEU_INPUT5_BITS_TSDM_HW_INTERRUPT		(1<<29)
257 #define AEU_INPUT5_BITS_TSEM_PARITY_ERROR		(1<<30)
258 #define AEU_INPUT5_BITS_TSEM_HW_INTERRUPT		(1<<31)
259 
260 #define AEU_INPUT5_BITS_GENERATE_SYSTEM_KILL (0x0)
261 
262 #define AEU_INPUT5_BITS_GENERATE_PROCESS_KILL \
263 	(AEU_INPUT5_BITS_SRC_PARITY_ERROR | \
264 	 AEU_INPUT5_BITS_PB_CLIENT1_PARITY_ERROR | \
265 	 AEU_INPUT5_BITS_PB_CLIENT2_PARITY_ERROR | \
266 	 AEU_INPUT5_BITS_RPB_PARITY_ERROR | \
267 	 AEU_INPUT5_BITS_PBF_PARITY_ERROR | \
268 	 AEU_INPUT5_BITS_QM_PARITY_ERROR | \
269 	 AEU_INPUT5_BITS_TM_PARITY_ERROR | \
270 	 AEU_INPUT5_BITS_MCM_PARITY_ERROR | \
271 	 AEU_INPUT5_BITS_MSDM_PARITY_ERROR | \
272 	 AEU_INPUT5_BITS_MSEM_PARITY_ERROR | \
273 	 AEU_INPUT5_BITS_PCM_PARITY_ERROR | \
274 	 AEU_INPUT5_BITS_PSDM_PARITY_ERROR | \
275 	 AEU_INPUT5_BITS_PSEM_PARITY_ERROR | \
276 	 AEU_INPUT5_BITS_TCM_PARITY_ERROR | \
277 	 AEU_INPUT5_BITS_TSDM_PARITY_ERROR | \
278 	 AEU_INPUT5_BITS_TSEM_PARITY_ERROR)
279 
280 #define AEU_INPUT5_BITS_PARITY_ERROR \
281 	(AEU_INPUT5_BITS_GENERATE_SYSTEM_KILL | \
282 	 AEU_INPUT5_BITS_GENERATE_PROCESS_KILL)
283 
284 #define AEU_INPUT5_BITS_PARITY_COMMON_BLOCKS (0)
285 
286 /* AEU INPUT REGISTER 6 */
287 #define AEU_INPUT6_BITS_UCM_PARITY_ERROR		(1<<0)
288 #define AEU_INPUT6_BITS_UCM_HW_INTERRUPT		(1<<1)
289 #define AEU_INPUT6_BITS_USDM_PARITY_ERROR		(1<<2)
290 #define AEU_INPUT6_BITS_USDM_HW_INTERRUPT		(1<<3)
291 #define AEU_INPUT6_BITS_USEM_PARITY_ERROR		(1<<4)
292 #define AEU_INPUT6_BITS_USEM_HW_INTERRUPT		(1<<5)
293 #define AEU_INPUT6_BITS_XCM_PARITY_ERROR		(1<<6)
294 #define AEU_INPUT6_BITS_XCM_HW_INTERRUPT		(1<<7)
295 #define AEU_INPUT6_BITS_XSDM_PARITY_ERROR		(1<<8)
296 #define AEU_INPUT6_BITS_XSDM_HW_INTERRUPT		(1<<9)
297 #define AEU_INPUT6_BITS_XSEM_PARITY_ERROR		(1<<10)
298 #define AEU_INPUT6_BITS_XSEM_HW_INTERRUPT		(1<<11)
299 #define AEU_INPUT6_BITS_YCM_PARITY_ERROR		(1<<12)
300 #define AEU_INPUT6_BITS_YCM_HW_INTERRUPT		(1<<13)
301 #define AEU_INPUT6_BITS_YSDM_PARITY_ERROR		(1<<14)
302 #define AEU_INPUT6_BITS_YSDM_HW_INTERRUPT		(1<<15)
303 #define AEU_INPUT6_BITS_YSEM_PARITY_ERROR		(1<<16)
304 #define AEU_INPUT6_BITS_YSEM_HW_INTERRUPT		(1<<17)
305 #define AEU_INPUT6_BITS_XYLD_PARITY_ERROR		(1<<18)
306 #define AEU_INPUT6_BITS_XYLD_HW_INTERRUPT		(1<<19)
307 #define AEU_INPUT6_BITS_TMLD_PARITY_ERROR		(1<<20)
308 #define AEU_INPUT6_BITS_TMLD_HW_INTERRUPT		(1<<21)
309 #define AEU_INPUT6_BITS_MULD_PARITY_ERROR		(1<<22)
310 #define AEU_INPUT6_BITS_MULD_HW_INTERRUPT		(1<<23)
311 #define AEU_INPUT6_BITS_YULD_PARITY_ERROR		(1<<24)
312 #define AEU_INPUT6_BITS_YULD_HW_INTERRUPT		(1<<25)
313 #define AEU_INPUT6_BITS_DORQ_PARITY_ERROR		(1<<26)
314 #define AEU_INPUT6_BITS_DORQ_HW_INTERRUPT		(1<<27)
315 #define AEU_INPUT6_BITS_DBG_PARITY_ERROR		(1<<28)
316 #define AEU_INPUT6_BITS_DBG_HW_INTERRUPT		(1<<29)
317 #define AEU_INPUT6_BITS_IPC_PARITY_ERROR		(1<<30)
318 #define AEU_INPUT6_BITS_IPC_HW_INTERRUPT		(1<<31)
319 
320 #define AEU_INPUT6_BITS_GENERATE_SYSTEM_KILL \
321 	(AEU_INPUT6_BITS_IPC_PARITY_ERROR)
322 
323 #define AEU_INPUT6_BITS_GENERATE_PROCESS_KILL \
324 	(AEU_INPUT6_BITS_UCM_PARITY_ERROR | \
325 	 AEU_INPUT6_BITS_USDM_PARITY_ERROR | \
326 	 AEU_INPUT6_BITS_USEM_PARITY_ERROR | \
327 	 AEU_INPUT6_BITS_XCM_PARITY_ERROR | \
328 	 AEU_INPUT6_BITS_XSDM_PARITY_ERROR | \
329 	 AEU_INPUT6_BITS_XSEM_PARITY_ERROR | \
330 	 AEU_INPUT6_BITS_YCM_PARITY_ERROR | \
331 	 AEU_INPUT6_BITS_YSDM_PARITY_ERROR | \
332 	 AEU_INPUT6_BITS_YSEM_PARITY_ERROR | \
333 	 AEU_INPUT6_BITS_XYLD_PARITY_ERROR | \
334 	 AEU_INPUT6_BITS_TMLD_PARITY_ERROR | \
335 	 AEU_INPUT6_BITS_MULD_PARITY_ERROR | \
336 	 AEU_INPUT6_BITS_YULD_PARITY_ERROR | \
337 	 AEU_INPUT6_BITS_DORQ_PARITY_ERROR)
338 
339 #define AEU_INPUT6_BITS_PARITY_ERROR \
340 	(AEU_INPUT6_BITS_GENERATE_SYSTEM_KILL | \
341 	 AEU_INPUT6_BITS_GENERATE_PROCESS_KILL)
342 
343 #define AEU_INPUT6_BITS_PARITY_COMMON_BLOCKS \
344 	(AEU_INPUT6_BITS_IPC_PARITY_ERROR)
345 
346 /* AEU INPUT REGISTER 7 */
347 #define AEU_INPUT7_BITS_CCFC_PARITY_ERROR		(1<<0)
348 #define AEU_INPUT7_BITS_CCFC_HW_INTERRUPT		(1<<1)
349 #define AEU_INPUT7_BITS_CDU_PARITY_ERROR		(1<<2)
350 #define AEU_INPUT7_BITS_CDU_HW_INTERRUPT		(1<<3)
351 #define AEU_INPUT7_BITS_DMAE_PARITY_ERROR		(1<<4)
352 #define AEU_INPUT7_BITS_DMAE_HW_INTERRUPT		(1<<5)
353 #define AEU_INPUT7_BITS_IGU_PARITY_ERROR		(1<<6)
354 #define AEU_INPUT7_BITS_IGU_HW_INTERRUPT		(1<<7)
355 #define AEU_INPUT7_BITS_ATC_PARITY_ERROR		(1<<8)
356 #define AEU_INPUT7_BITS_ATC_HW_INTERRUPT		(1<<9)
357 #define AEU_INPUT7_BITS_CAU_PARITY_ERROR		(1<<10)
358 #define AEU_INPUT7_BITS_CAU_HW_INTERRUPT		(1<<11)
359 #define AEU_INPUT7_BITS_PTU_PARITY_ERROR		(1<<12)
360 #define AEU_INPUT7_BITS_PTU_HW_INTERRUPT		(1<<13)
361 #define AEU_INPUT7_BITS_PRM_PARITY_ERROR		(1<<14)
362 #define AEU_INPUT7_BITS_PRM_HW_INTERRUPT		(1<<15)
363 #define AEU_INPUT7_BITS_TCFC_PARITY_ERROR		(1<<16)
364 #define AEU_INPUT7_BITS_TCFC_HW_INTERRUPT		(1<<17)
365 #define AEU_INPUT7_BITS_RDIF_PARITY_ERROR		(1<<18)
366 #define AEU_INPUT7_BITS_RDIF_HW_INTERRUPT		(1<<19)
367 #define AEU_INPUT7_BITS_TDIF_PARITY_ERROR		(1<<20)
368 #define AEU_INPUT7_BITS_TDIF_HW_INTERRUPT		(1<<21)
369 #define AEU_INPUT7_BITS_RSS_PARITY_ERROR		(1<<22)
370 #define AEU_INPUT7_BITS_RSS_HW_INTERRUPT		(1<<23)
371 #define AEU_INPUT7_BITS_MISC_PARITY_ERROR		(1<<24)
372 #define AEU_INPUT7_BITS_MISC_HW_INTERRUPT		(1<<25)
373 #define AEU_INPUT7_BITS_MISCS_PARITY_ERROR		(1<<26)
374 #define AEU_INPUT7_BITS_MISCS_HW_INTERRUPT		(1<<27)
375 #define AEU_INPUT7_BITS_VAUX_PCI_CORE_OR_PGLUE_PARITY_ERROR	(1<<28)
376 #define AEU_INPUT7_BITS_VAUX_PCI_CORE_HW_INTERRUPT	(1<<29)
377 #define AEU_INPUT7_BITS_PSWRQ_PARITY_ERROR		(1<<30)
378 #define AEU_INPUT7_BITS_PSWRQ_HW_INTERRUPT		(1<<31)
379 
380 #define AEU_INPUT7_BITS_GENERATE_SYSTEM_KILL \
381 	 (AEU_INPUT7_BITS_IGU_PARITY_ERROR | \
382 	  AEU_INPUT7_BITS_ATC_PARITY_ERROR | \
383 	  AEU_INPUT7_BITS_CAU_PARITY_ERROR | \
384 	  AEU_INPUT7_BITS_MISC_PARITY_ERROR | \
385 	  AEU_INPUT7_BITS_MISCS_PARITY_ERROR | \
386 	  AEU_INPUT7_BITS_VAUX_PCI_CORE_OR_PGLUE_PARITY_ERROR | \
387 	  AEU_INPUT7_BITS_PSWRQ_PARITY_ERROR)
388 
389 #define AEU_INPUT7_BITS_GENERATE_PROCESS_KILL \
390 	(AEU_INPUT7_BITS_CCFC_PARITY_ERROR | \
391 	 AEU_INPUT7_BITS_CDU_PARITY_ERROR | \
392 	 AEU_INPUT7_BITS_DMAE_PARITY_ERROR | \
393 	 AEU_INPUT7_BITS_PTU_PARITY_ERROR | \
394 	 AEU_INPUT7_BITS_PRM_PARITY_ERROR | \
395 	 AEU_INPUT7_BITS_TCFC_PARITY_ERROR | \
396 	 AEU_INPUT7_BITS_RDIF_PARITY_ERROR | \
397 	 AEU_INPUT7_BITS_TDIF_PARITY_ERROR | \
398 	 AEU_INPUT7_BITS_RSS_PARITY_ERROR)
399 
400 #define AEU_INPUT7_BITS_PARITY_ERROR \
401 	(AEU_INPUT7_BITS_GENERATE_SYSTEM_KILL | \
402 	 AEU_INPUT7_BITS_GENERATE_PROCESS_KILL)
403 
404 #define AEU_INPUT7_BITS_PARITY_COMMON_BLOCKS \
405 	 (AEU_INPUT7_BITS_MISCS_PARITY_ERROR | \
406 	  AEU_INPUT7_BITS_VAUX_PCI_CORE_OR_PGLUE_PARITY_ERROR)
407 
408 /* AEU INPUT REGISTER 8 */
409 #define AEU_INPUT8_BITS_PSWRQ_PCI_CLK_PARITY_ERROR	(1<<0)
410 #define AEU_INPUT8_BITS_PSWRQ_PCI_CLK_HW_INTERRUPT	(1<<1)
411 #define AEU_INPUT8_BITS_PSWWR_PARITY_ERROR		(1<<2)
412 #define AEU_INPUT8_BITS_PSWWR_HW_INTERRUPT		(1<<3)
413 #define AEU_INPUT8_BITS_PSWWR_PCI_CLK_PARITY_ERROR	(1<<4)
414 #define AEU_INPUT8_BITS_PSWWR_PCI_CLK_HW_INTERRUPT	(1<<5)
415 #define AEU_INPUT8_BITS_PSWRD_PARITY_ERROR		(1<<6)
416 #define AEU_INPUT8_BITS_PSWRD_HW_INTERRUPT		(1<<7)
417 #define AEU_INPUT8_BITS_PSWRD_PCI_CLK_PARITY_ERROR	(1<<8)
418 #define AEU_INPUT8_BITS_PSWRD_PCI_CLK_HW_INTERRUPT	(1<<9)
419 #define AEU_INPUT8_BITS_PSWHST_PARITY_ERROR		(1<<10)
420 #define AEU_INPUT8_BITS_PSWHST_HW_INTERRUPT		(1<<11)
421 #define AEU_INPUT8_BITS_PSWHST_PCI_CLK_PARITY_ERROR	(1<<12)
422 #define AEU_INPUT8_BITS_PSWHST_PCI_CLK_HW_INTERRUPT	(1<<13)
423 #define AEU_INPUT8_BITS_GRC_PARITY_ERROR		(1<<14)
424 #define AEU_INPUT8_BITS_GRC_HW_INTERRUPT		(1<<15)
425 #define AEU_INPUT8_BITS_CPMU_PARITY_ERROR		(1<<16)
426 #define AEU_INPUT8_BITS_CPMU_HW_INTERRUPT		(1<<17)
427 #define AEU_INPUT8_BITS_NCSI_PARITY_ERROR		(1<<18)
428 #define AEU_INPUT8_BITS_NCSI_HW_INTERRUPT		(1<<19)
429 #define AEU_INPUT8_BITS_YSEM_PRAM_PARITY_ERROR		(1<<20)
430 #define AEU_INPUT8_BITS_XSEM_PRAM_PARITY_ERROR		(1<<21)
431 #define AEU_INPUT8_BITS_USEM_PRAM_PARITY_ERROR		(1<<22)
432 #define AEU_INPUT8_BITS_TSEM_PRAM_PARITY_ERROR		(1<<23)
433 #define AEU_INPUT8_BITS_PSEM_PRAM_PARITY_ERROR		(1<<24)
434 #define AEU_INPUT8_BITS_MSEM_PRAM_PARITY_ERROR		(1<<25)
435 #define AEU_INPUT8_BITS_PXP_MISC_MPS_ATTN		(1<<26)
436 #define AEU_INPUT8_BITS_PCIE_GLUE_OR_PXP_EXPANSION_ROM_EVENT	(1<<27)
437 #define AEU_INPUT8_BITS_PERST_B_ASSERTION		(1<<28)
438 #define AEU_INPUT8_BITS_PERST_B_DE_ASSERTION		(1<<29)
439 #define AEU_INPUT8_BITS_WOL_PARITY_ERROR		(1<<30) /* Relevant only for AH */
440 #define AEU_INPUT8_BITS_WOL_HW_INTERRUPT		(1<<31) /* Relevant only for AH */
441 
442 #define AEU_INPUT8_BITS_GENERATE_SYSTEM_KILL_K2 \
443 	(AEU_INPUT8_BITS_PSWRQ_PCI_CLK_PARITY_ERROR | \
444 	 AEU_INPUT8_BITS_PSWWR_PARITY_ERROR | \
445 	 AEU_INPUT8_BITS_PSWWR_PCI_CLK_PARITY_ERROR | \
446 	 AEU_INPUT8_BITS_PSWRD_PARITY_ERROR | \
447 	 AEU_INPUT8_BITS_PSWRD_PCI_CLK_PARITY_ERROR | \
448 	 AEU_INPUT8_BITS_PSWHST_PARITY_ERROR | \
449 	 AEU_INPUT8_BITS_PSWHST_PCI_CLK_PARITY_ERROR | \
450 	 AEU_INPUT8_BITS_CPMU_PARITY_ERROR | \
451 	 AEU_INPUT8_BITS_NCSI_PARITY_ERROR | \
452 	 AEU_INPUT8_BITS_WOL_PARITY_ERROR)
453 
454 #define AEU_INPUT8_BITS_GENERATE_SYSTEM_KILL_BB \
455 	(AEU_INPUT8_BITS_PSWRQ_PCI_CLK_PARITY_ERROR | \
456 	 AEU_INPUT8_BITS_PSWWR_PARITY_ERROR | \
457 	 AEU_INPUT8_BITS_PSWWR_PCI_CLK_PARITY_ERROR | \
458 	 AEU_INPUT8_BITS_PSWRD_PARITY_ERROR | \
459 	 AEU_INPUT8_BITS_PSWRD_PCI_CLK_PARITY_ERROR | \
460 	 AEU_INPUT8_BITS_PSWHST_PARITY_ERROR | \
461 	 AEU_INPUT8_BITS_PSWHST_PCI_CLK_PARITY_ERROR | \
462 	 AEU_INPUT8_BITS_CPMU_PARITY_ERROR | \
463 	 AEU_INPUT8_BITS_NCSI_PARITY_ERROR)
464 
465 #define AEU_INPUT8_BITS_GENERATE_PROCESS_KILL \
466 	(AEU_INPUT8_BITS_GRC_PARITY_ERROR | \
467 	 AEU_INPUT8_BITS_XSEM_PRAM_PARITY_ERROR | \
468 	 AEU_INPUT8_BITS_USEM_PRAM_PARITY_ERROR | \
469 	 AEU_INPUT8_BITS_TSEM_PRAM_PARITY_ERROR | \
470 	 AEU_INPUT8_BITS_PSEM_PRAM_PARITY_ERROR | \
471 	 AEU_INPUT8_BITS_MSEM_PRAM_PARITY_ERROR)
472 
473 #define AEU_INPUT8_BITS_PARITY_ERROR_BB \
474 	(AEU_INPUT8_BITS_GENERATE_SYSTEM_KILL_BB | \
475 	 AEU_INPUT8_BITS_GENERATE_PROCESS_KILL)
476 
477 #define AEU_INPUT8_BITS_PARITY_ERROR_K2 \
478 	(AEU_INPUT8_BITS_GENERATE_SYSTEM_KILL_K2 | \
479 	 AEU_INPUT8_BITS_GENERATE_PROCESS_KILL)
480 
481 #define AEU_INPUT8_BITS_PARITY_COMMON_BLOCKS_K2 \
482 	(AEU_INPUT8_BITS_NCSI_PARITY_ERROR | \
483 	 AEU_INPUT8_BITS_GRC_PARITY_ERROR | \
484 	 AEU_INPUT8_BITS_WOL_PARITY_ERROR)
485 
486 #define AEU_INPUT8_BITS_PARITY_COMMON_BLOCKS_BB \
487 	(AEU_INPUT8_BITS_NCSI_PARITY_ERROR | \
488 	 AEU_INPUT8_BITS_GRC_PARITY_ERROR)
489 
490 /* AEU INPUT REGISTER 9 */
491 #define AEU_INPUT9_BITS_MCP_LATCHED_MEMORY_PARITY	(1<<0)
492 #define AEU_INPUT9_BITS_MCP_LATCHED_SCRATCHPAD_CACHE	(1<<1)
493 #define AEU_INPUT9_BITS_AVS_PARITY			(1<<2)
494 #define AEU_INPUT9_BITS_AVS_HW_ATTN			(1<<3)
495 #define AEU_INPUT9_BITS_PCIE_CORE_HW_INTERRUPT		(1<<4)
496 #define AEU_INPUT9_BITS_PCIE_LINK_UP			(1<<5)
497 #define AEU_INPUT9_BITS_PCIE_HOT_RESET			(1<<6)
498 #define AEU_INPUT9_BITS_RSRV_7				(1<<7)
499 #define AEU_INPUT9_BITS_RSRV_8				(1<<8)
500 #define AEU_INPUT9_BITS_RSRV_9				(1<<9)
501 #define AEU_INPUT9_BITS_RSRV_10				(1<<10)
502 #define AEU_INPUT9_BITS_RSRV_11				(1<<11)
503 #define AEU_INPUT9_BITS_RSRV_12				(1<<12)
504 #define AEU_INPUT9_BITS_RSRV_13				(1<<13)
505 #define AEU_INPUT9_BITS_RSRV_14				(1<<14)
506 #define AEU_INPUT9_BITS_RSRV_15				(1<<15)
507 #define AEU_INPUT9_BITS_RSRV_16				(1<<16)
508 #define AEU_INPUT9_BITS_RSRV_17				(1<<17)
509 #define AEU_INPUT9_BITS_RSRV_18				(1<<18)
510 #define AEU_INPUT9_BITS_RSRV_19				(1<<19)
511 #define AEU_INPUT9_BITS_RSRV_20				(1<<20)
512 #define AEU_INPUT9_BITS_RSRV_21				(1<<21)
513 #define AEU_INPUT9_BITS_RSRV_22				(1<<22)
514 #define AEU_INPUT9_BITS_RSRV_23				(1<<23)
515 #define AEU_INPUT9_BITS_RSRV_24				(1<<24)
516 #define AEU_INPUT9_BITS_RSRV_25				(1<<25)
517 #define AEU_INPUT9_BITS_RSRV_26				(1<<26)
518 #define AEU_INPUT9_BITS_RSRV_27				(1<<27)
519 #define AEU_INPUT9_BITS_RSRV_28				(1<<28)
520 #define AEU_INPUT9_BITS_RSRV_29				(1<<29)
521 #define AEU_INPUT9_BITS_RSRV_30				(1<<30)
522 #define AEU_INPUT9_BITS_RSRV_31				(1<<31)
523 
524 #define AEU_INPUT9_BITS_GENERATE_SYSTEM_KILL \
525 	(AEU_INPUT9_BITS_MCP_LATCHED_MEMORY_PARITY | \
526 	 AEU_INPUT9_BITS_AVS_PARITY)
527 
528 #define AEU_INPUT9_BITS_GENERATE_PROCESS_KILL (0)
529 
530 #define AEU_INPUT9_BITS_PARITY_ERROR \
531 	(AEU_INPUT9_BITS_GENERATE_SYSTEM_KILL | \
532 	 AEU_INPUT9_BITS_GENERATE_PROCESS_KILL)
533 
534 #define AEU_INPUT9_BITS_PARITY_COMMON_BLOCKS \
535 	(AEU_INPUT9_BITS_MCP_LATCHED_MEMORY_PARITY | \
536 	 AEU_INPUT9_BITS_AVS_PARITY)
537 #endif /* AEU_INPUTS_H */
538