1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_RDMA_API_H__
37*14b24e2bSVaishali Kulkarni #define __ECORE_RDMA_API_H__
38*14b24e2bSVaishali Kulkarni 
39*14b24e2bSVaishali Kulkarni #ifndef LINUX_REMOVE
40*14b24e2bSVaishali Kulkarni #define ETH_ALEN 6
41*14b24e2bSVaishali Kulkarni #endif
42*14b24e2bSVaishali Kulkarni 
43*14b24e2bSVaishali Kulkarni #ifndef __EXTRACT__LINUX__
44*14b24e2bSVaishali Kulkarni 
45*14b24e2bSVaishali Kulkarni enum ecore_roce_ll2_tx_dest
46*14b24e2bSVaishali Kulkarni {
47*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_LL2_TX_DEST_NW /* Light L2 TX Destination to the Network */,
48*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_LL2_TX_DEST_LB /* Light L2 TX Destination to the Loopback */,
49*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_LL2_TX_DEST_MAX
50*14b24e2bSVaishali Kulkarni };
51*14b24e2bSVaishali Kulkarni 
52*14b24e2bSVaishali Kulkarni /* HW/FW RoCE Limitations (external. For internal see ecore_roce.h) */
53*14b24e2bSVaishali Kulkarni /* CNQ size Limitation
54*14b24e2bSVaishali Kulkarni  * The CNQ size should be set as twice the amount of CQs, since for each CQ one
55*14b24e2bSVaishali Kulkarni  * element may be inserted into the CNQ and another element is used per CQ to
56*14b24e2bSVaishali Kulkarni  * accommodate for a possible race in the arm mechanism.
57*14b24e2bSVaishali Kulkarni  * The FW supports a CNQ of 64k-1 and this apparently causes an issue - notice
58*14b24e2bSVaishali Kulkarni  * that the number of QPs can reach 32k giving 64k CQs and 128k CNQ elements.
59*14b24e2bSVaishali Kulkarni  * Luckily the FW can buffer CNQ elements avoiding an overflow, on the expense
60*14b24e2bSVaishali Kulkarni  * of performance.
61*14b24e2bSVaishali Kulkarni  */
62*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_CNQ_SIZE               (0xFFFF) /* 2^16 - 1 */
63*14b24e2bSVaishali Kulkarni 
64*14b24e2bSVaishali Kulkarni /* rdma interface */
65*14b24e2bSVaishali Kulkarni enum ecore_rdma_tid_type
66*14b24e2bSVaishali Kulkarni {
67*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_TID_REGISTERED_MR,
68*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_TID_FMR,
69*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_TID_MW_TYPE1,
70*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_TID_MW_TYPE2A
71*14b24e2bSVaishali Kulkarni };
72*14b24e2bSVaishali Kulkarni 
73*14b24e2bSVaishali Kulkarni enum ecore_roce_qp_state {
74*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_QP_STATE_RESET, /* Reset */
75*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_QP_STATE_INIT,  /* Initialized */
76*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_QP_STATE_RTR,   /* Ready to Receive */
77*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_QP_STATE_RTS,   /* Ready to Send */
78*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_QP_STATE_SQD,   /* Send Queue Draining */
79*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_QP_STATE_ERR,   /* Error */
80*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_QP_STATE_SQE    /* Send Queue Error */
81*14b24e2bSVaishali Kulkarni };
82*14b24e2bSVaishali Kulkarni 
83*14b24e2bSVaishali Kulkarni typedef
84*14b24e2bSVaishali Kulkarni void (*affiliated_event_t)(void	*context,
85*14b24e2bSVaishali Kulkarni 			   u8	fw_event_code,
86*14b24e2bSVaishali Kulkarni 			   void	*fw_handle);
87*14b24e2bSVaishali Kulkarni 
88*14b24e2bSVaishali Kulkarni typedef
89*14b24e2bSVaishali Kulkarni void (*unaffiliated_event_t)(void *context,
90*14b24e2bSVaishali Kulkarni 			     u8   event_code);
91*14b24e2bSVaishali Kulkarni 
92*14b24e2bSVaishali Kulkarni struct ecore_rdma_events {
93*14b24e2bSVaishali Kulkarni 	void			*context;
94*14b24e2bSVaishali Kulkarni 	affiliated_event_t	affiliated_event;
95*14b24e2bSVaishali Kulkarni 	unaffiliated_event_t	unaffiliated_event;
96*14b24e2bSVaishali Kulkarni };
97*14b24e2bSVaishali Kulkarni 
98*14b24e2bSVaishali Kulkarni struct ecore_rdma_device {
99*14b24e2bSVaishali Kulkarni     /* Vendor specific information */
100*14b24e2bSVaishali Kulkarni 	u32	vendor_id;
101*14b24e2bSVaishali Kulkarni 	u32	vendor_part_id;
102*14b24e2bSVaishali Kulkarni 	u32	hw_ver;
103*14b24e2bSVaishali Kulkarni 	u64	fw_ver;
104*14b24e2bSVaishali Kulkarni 
105*14b24e2bSVaishali Kulkarni 	u64	node_guid; /* node GUID */
106*14b24e2bSVaishali Kulkarni 	u64	sys_image_guid; /* System image GUID */
107*14b24e2bSVaishali Kulkarni 
108*14b24e2bSVaishali Kulkarni 	u8	max_cnq;
109*14b24e2bSVaishali Kulkarni 	u8	max_sge; /* The maximum number of scatter/gather entries
110*14b24e2bSVaishali Kulkarni 			  * per Work Request supported
111*14b24e2bSVaishali Kulkarni 			  */
112*14b24e2bSVaishali Kulkarni 	u8	max_srq_sge; /* The maximum number of scatter/gather entries
113*14b24e2bSVaishali Kulkarni 			      * per Work Request supported for SRQ
114*14b24e2bSVaishali Kulkarni 			      */
115*14b24e2bSVaishali Kulkarni 	u16	max_inline;
116*14b24e2bSVaishali Kulkarni 	u32	max_wqe; /* The maximum number of outstanding work
117*14b24e2bSVaishali Kulkarni 			  * requests on any Work Queue supported
118*14b24e2bSVaishali Kulkarni 			  */
119*14b24e2bSVaishali Kulkarni 	u32	max_srq_wqe; /* The maximum number of outstanding work
120*14b24e2bSVaishali Kulkarni 			      * requests on any Work Queue supported for SRQ
121*14b24e2bSVaishali Kulkarni 			      */
122*14b24e2bSVaishali Kulkarni 	u8	max_qp_resp_rd_atomic_resc; /* The maximum number of RDMA Reads
123*14b24e2bSVaishali Kulkarni 					     * & atomic operation that can be
124*14b24e2bSVaishali Kulkarni 					     * outstanding per QP
125*14b24e2bSVaishali Kulkarni 					     */
126*14b24e2bSVaishali Kulkarni 
127*14b24e2bSVaishali Kulkarni 	u8	max_qp_req_rd_atomic_resc; /* The maximum depth per QP for
128*14b24e2bSVaishali Kulkarni 					    * initiation of RDMA Read
129*14b24e2bSVaishali Kulkarni 					    * & atomic operations
130*14b24e2bSVaishali Kulkarni 					    */
131*14b24e2bSVaishali Kulkarni 	u64	max_dev_resp_rd_atomic_resc;
132*14b24e2bSVaishali Kulkarni 	u32	max_cq;
133*14b24e2bSVaishali Kulkarni 	u32	max_qp;
134*14b24e2bSVaishali Kulkarni 	u32	max_srq; /* Maximum number of SRQs */
135*14b24e2bSVaishali Kulkarni 	u32	max_mr; /* Maximum number of MRs supported by this device */
136*14b24e2bSVaishali Kulkarni 	u64	max_mr_size; /* Size (in bytes) of the largest contiguous memory
137*14b24e2bSVaishali Kulkarni 			      * block that can be registered by this device
138*14b24e2bSVaishali Kulkarni 			      */
139*14b24e2bSVaishali Kulkarni 	u32	max_cqe;
140*14b24e2bSVaishali Kulkarni 	u32	max_mw; /* The maximum number of memory windows supported */
141*14b24e2bSVaishali Kulkarni 	u32	max_fmr;
142*14b24e2bSVaishali Kulkarni 	u32	max_mr_mw_fmr_pbl;
143*14b24e2bSVaishali Kulkarni 	u64	max_mr_mw_fmr_size;
144*14b24e2bSVaishali Kulkarni 	u32	max_pd; /* The maximum number of protection domains supported */
145*14b24e2bSVaishali Kulkarni 	u32	max_ah;
146*14b24e2bSVaishali Kulkarni 	u8	max_pkey;
147*14b24e2bSVaishali Kulkarni 	u16	max_srq_wr; /* Maximum number of WRs per SRQ */
148*14b24e2bSVaishali Kulkarni 	u8	max_stats_queues; /* Maximum number of statistics queues */
149*14b24e2bSVaishali Kulkarni 	u32	dev_caps;
150*14b24e2bSVaishali Kulkarni 
151*14b24e2bSVaishali Kulkarni 	/* Abilty to support RNR-NAK generation */
152*14b24e2bSVaishali Kulkarni 
153*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_RNR_NAK_MASK				0x1
154*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_RNR_NAK_SHIFT			0
155*14b24e2bSVaishali Kulkarni 	/* Abilty to support shutdown port */
156*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK			0x1
157*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT			1
158*14b24e2bSVaishali Kulkarni 	/* Abilty to support port active event */
159*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK		0x1
160*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT		2
161*14b24e2bSVaishali Kulkarni 	/* Abilty to support port change event */
162*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK		0x1
163*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT		3
164*14b24e2bSVaishali Kulkarni 	/* Abilty to support system image GUID */
165*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_SYS_IMAGE_MASK			0x1
166*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_SYS_IMAGE_SHIFT			4
167*14b24e2bSVaishali Kulkarni 	/* Abilty to support bad P_Key counter support */
168*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK			0x1
169*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT			5
170*14b24e2bSVaishali Kulkarni 	/* Abilty to support atomic operations */
171*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_ATOMIC_OP_MASK			0x1
172*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_ATOMIC_OP_SHIFT			6
173*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_RESIZE_CQ_MASK			0x1
174*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_RESIZE_CQ_SHIFT			7
175*14b24e2bSVaishali Kulkarni 	/* Abilty to support modifying the maximum number of
176*14b24e2bSVaishali Kulkarni 	 * outstanding work requests per QP
177*14b24e2bSVaishali Kulkarni 	 */
178*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK			0x1
179*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT			8
180*14b24e2bSVaishali Kulkarni 	/* Abilty to support automatic path migration */
181*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK			0x1
182*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT			9
183*14b24e2bSVaishali Kulkarni 	/* Abilty to support the base memory management extensions */
184*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK			0x1
185*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT		10
186*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK			0x1
187*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT			11
188*14b24e2bSVaishali Kulkarni 	/* Abilty to support multipile page sizes per memory region */
189*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK		0x1
190*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT		12
191*14b24e2bSVaishali Kulkarni 	/* Abilty to support block list physical buffer list */
192*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BLOCK_MODE_MASK			0x1
193*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_BLOCK_MODE_SHIFT			13
194*14b24e2bSVaishali Kulkarni 	/* Abilty to support zero based virtual addresses */
195*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_ZBVA_MASK				0x1
196*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_ZBVA_SHIFT				14
197*14b24e2bSVaishali Kulkarni 	/* Abilty to support local invalidate fencing */
198*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK			0x1
199*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT		15
200*14b24e2bSVaishali Kulkarni 	/* Abilty to support Loopback on QP */
201*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_LB_INDICATOR_MASK			0x1
202*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_DEV_CAP_LB_INDICATOR_SHIFT			16
203*14b24e2bSVaishali Kulkarni 	u64	page_size_caps;
204*14b24e2bSVaishali Kulkarni 	u8	dev_ack_delay;
205*14b24e2bSVaishali Kulkarni 	u32	reserved_lkey; /* Value of reserved L_key */
206*14b24e2bSVaishali Kulkarni 	u32	bad_pkey_counter; /* Bad P_key counter support indicator */
207*14b24e2bSVaishali Kulkarni 	struct ecore_rdma_events events;
208*14b24e2bSVaishali Kulkarni };
209*14b24e2bSVaishali Kulkarni 
210*14b24e2bSVaishali Kulkarni enum ecore_port_state {
211*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_PORT_UP,
212*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_PORT_DOWN,
213*14b24e2bSVaishali Kulkarni };
214*14b24e2bSVaishali Kulkarni 
215*14b24e2bSVaishali Kulkarni enum ecore_roce_capability {
216*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_V1	= 1 << 0,
217*14b24e2bSVaishali Kulkarni 	ECORE_ROCE_V2	= 1 << 1,
218*14b24e2bSVaishali Kulkarni };
219*14b24e2bSVaishali Kulkarni 
220*14b24e2bSVaishali Kulkarni struct ecore_rdma_port {
221*14b24e2bSVaishali Kulkarni 	enum ecore_port_state port_state;
222*14b24e2bSVaishali Kulkarni 	int	link_speed;
223*14b24e2bSVaishali Kulkarni 	u64	max_msg_size;
224*14b24e2bSVaishali Kulkarni 	u8	source_gid_table_len;
225*14b24e2bSVaishali Kulkarni 	void	*source_gid_table_ptr;
226*14b24e2bSVaishali Kulkarni 	u8	pkey_table_len;
227*14b24e2bSVaishali Kulkarni 	void	*pkey_table_ptr;
228*14b24e2bSVaishali Kulkarni 	u32	pkey_bad_counter;
229*14b24e2bSVaishali Kulkarni 	enum ecore_roce_capability capability;
230*14b24e2bSVaishali Kulkarni };
231*14b24e2bSVaishali Kulkarni 
232*14b24e2bSVaishali Kulkarni struct ecore_rdma_cnq_params
233*14b24e2bSVaishali Kulkarni {
234*14b24e2bSVaishali Kulkarni 	u8  num_pbl_pages; /* Number of pages in the PBL allocated
235*14b24e2bSVaishali Kulkarni 				   * for this queue
236*14b24e2bSVaishali Kulkarni 				   */
237*14b24e2bSVaishali Kulkarni 	u64 pbl_ptr; /* Address to the first entry of the queue PBL */
238*14b24e2bSVaishali Kulkarni };
239*14b24e2bSVaishali Kulkarni 
240*14b24e2bSVaishali Kulkarni /* The CQ Mode affects the CQ doorbell transaction size.
241*14b24e2bSVaishali Kulkarni  * 64/32 bit machines should configure to 32/16 bits respectively.
242*14b24e2bSVaishali Kulkarni  */
243*14b24e2bSVaishali Kulkarni enum ecore_rdma_cq_mode {
244*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_CQ_MODE_16_BITS,
245*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_CQ_MODE_32_BITS,
246*14b24e2bSVaishali Kulkarni };
247*14b24e2bSVaishali Kulkarni 
248*14b24e2bSVaishali Kulkarni struct ecore_roce_dcqcn_params {
249*14b24e2bSVaishali Kulkarni 	u8	notification_point;
250*14b24e2bSVaishali Kulkarni 	u8	reaction_point;
251*14b24e2bSVaishali Kulkarni 
252*14b24e2bSVaishali Kulkarni 	/* fields for notification point */
253*14b24e2bSVaishali Kulkarni 	u32	cnp_send_timeout;
254*14b24e2bSVaishali Kulkarni 
255*14b24e2bSVaishali Kulkarni 	/* fields for reaction point */
256*14b24e2bSVaishali Kulkarni 	u32	rl_bc_rate;  /* Byte Counter Limit. */
257*14b24e2bSVaishali Kulkarni 	u16	rl_max_rate; /* Maximum rate in 1.6 Mbps resolution */
258*14b24e2bSVaishali Kulkarni 	u16	rl_r_ai;     /* Active increase rate */
259*14b24e2bSVaishali Kulkarni 	u16	rl_r_hai;    /* Hyper active increase rate */
260*14b24e2bSVaishali Kulkarni 	u16	dcqcn_g;     /* Alpha update gain in 1/64K resolution */
261*14b24e2bSVaishali Kulkarni 	u32	dcqcn_k_us;  /* Alpha update interval */
262*14b24e2bSVaishali Kulkarni 	u32	dcqcn_timeout_us;
263*14b24e2bSVaishali Kulkarni };
264*14b24e2bSVaishali Kulkarni 
265*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
266*14b24e2bSVaishali Kulkarni 
267*14b24e2bSVaishali Kulkarni #define ECORE_MPA_RTR_TYPE_NONE		0 /* No RTR type */
268*14b24e2bSVaishali Kulkarni #define ECORE_MPA_RTR_TYPE_ZERO_SEND	(1 << 0)
269*14b24e2bSVaishali Kulkarni #define ECORE_MPA_RTR_TYPE_ZERO_WRITE	(1 << 1)
270*14b24e2bSVaishali Kulkarni #define ECORE_MPA_RTR_TYPE_ZERO_READ	(1 << 2)
271*14b24e2bSVaishali Kulkarni 
272*14b24e2bSVaishali Kulkarni enum ecore_mpa_rev {
273*14b24e2bSVaishali Kulkarni 	ECORE_MPA_REV1,
274*14b24e2bSVaishali Kulkarni 	ECORE_MPA_REV2,
275*14b24e2bSVaishali Kulkarni };
276*14b24e2bSVaishali Kulkarni 
277*14b24e2bSVaishali Kulkarni struct ecore_iwarp_params {
278*14b24e2bSVaishali Kulkarni 	u32				rcv_wnd_size;
279*14b24e2bSVaishali Kulkarni 	u16				ooo_num_rx_bufs;
280*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_TS_EN (1 << 0)
281*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_DA_EN (1 << 1)
282*14b24e2bSVaishali Kulkarni 	u8				flags;
283*14b24e2bSVaishali Kulkarni 	u8				crc_needed;
284*14b24e2bSVaishali Kulkarni 	enum ecore_mpa_rev		mpa_rev;
285*14b24e2bSVaishali Kulkarni 	u8				mpa_rtr;
286*14b24e2bSVaishali Kulkarni 	u8				mpa_peer2peer;
287*14b24e2bSVaishali Kulkarni };
288*14b24e2bSVaishali Kulkarni 
289*14b24e2bSVaishali Kulkarni #endif
290*14b24e2bSVaishali Kulkarni 
291*14b24e2bSVaishali Kulkarni struct ecore_roce_params {
292*14b24e2bSVaishali Kulkarni 	enum ecore_rdma_cq_mode		cq_mode;
293*14b24e2bSVaishali Kulkarni 	struct ecore_roce_dcqcn_params	dcqcn_params;
294*14b24e2bSVaishali Kulkarni 	u8				ll2_handle; /* required for UD QPs */
295*14b24e2bSVaishali Kulkarni };
296*14b24e2bSVaishali Kulkarni 
297*14b24e2bSVaishali Kulkarni struct ecore_rdma_start_in_params {
298*14b24e2bSVaishali Kulkarni 	struct ecore_rdma_events	*events;
299*14b24e2bSVaishali Kulkarni 	struct ecore_rdma_cnq_params	cnq_pbl_list[128];
300*14b24e2bSVaishali Kulkarni 	u8				desired_cnq;
301*14b24e2bSVaishali Kulkarni 	u16				max_mtu;
302*14b24e2bSVaishali Kulkarni 	u8				mac_addr[ETH_ALEN];
303*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
304*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_params	iwarp;
305*14b24e2bSVaishali Kulkarni #endif
306*14b24e2bSVaishali Kulkarni 	struct ecore_roce_params	roce;
307*14b24e2bSVaishali Kulkarni };
308*14b24e2bSVaishali Kulkarni 
309*14b24e2bSVaishali Kulkarni struct ecore_rdma_add_user_out_params {
310*14b24e2bSVaishali Kulkarni 	/* output variables (given to miniport) */
311*14b24e2bSVaishali Kulkarni 	u16	dpi;
312*14b24e2bSVaishali Kulkarni 	u64	dpi_addr;
313*14b24e2bSVaishali Kulkarni 	u64	dpi_phys_addr;
314*14b24e2bSVaishali Kulkarni 	u32	dpi_size;
315*14b24e2bSVaishali Kulkarni 	u16	wid_count;
316*14b24e2bSVaishali Kulkarni };
317*14b24e2bSVaishali Kulkarni 
318*14b24e2bSVaishali Kulkarni /*Returns the CQ CID or zero in case of failure */
319*14b24e2bSVaishali Kulkarni struct ecore_rdma_create_cq_in_params {
320*14b24e2bSVaishali Kulkarni 	/* input variables (given by miniport) */
321*14b24e2bSVaishali Kulkarni 	u32	cq_handle_lo; /* CQ handle to be written in CNQ */
322*14b24e2bSVaishali Kulkarni 	u32	cq_handle_hi;
323*14b24e2bSVaishali Kulkarni 	u32	cq_size;
324*14b24e2bSVaishali Kulkarni 	u16	dpi;
325*14b24e2bSVaishali Kulkarni 	bool	pbl_two_level;
326*14b24e2bSVaishali Kulkarni 	u64	pbl_ptr;
327*14b24e2bSVaishali Kulkarni 	u16	pbl_num_pages;
328*14b24e2bSVaishali Kulkarni 	u8	pbl_page_size_log; /* for the pages that contain the
329*14b24e2bSVaishali Kulkarni 			   * pointers to the CQ pages
330*14b24e2bSVaishali Kulkarni 			   */
331*14b24e2bSVaishali Kulkarni 	u8	cnq_id;
332*14b24e2bSVaishali Kulkarni 	u16	int_timeout;
333*14b24e2bSVaishali Kulkarni };
334*14b24e2bSVaishali Kulkarni 
335*14b24e2bSVaishali Kulkarni #endif
336*14b24e2bSVaishali Kulkarni 
337*14b24e2bSVaishali Kulkarni struct ecore_rdma_resize_cq_in_params {
338*14b24e2bSVaishali Kulkarni 	/* input variables (given by miniport) */
339*14b24e2bSVaishali Kulkarni 
340*14b24e2bSVaishali Kulkarni 	u16	icid;
341*14b24e2bSVaishali Kulkarni 	u32	cq_size;
342*14b24e2bSVaishali Kulkarni 	bool	pbl_two_level;
343*14b24e2bSVaishali Kulkarni 	u64	pbl_ptr;
344*14b24e2bSVaishali Kulkarni 	u16	pbl_num_pages;
345*14b24e2bSVaishali Kulkarni 	u8	pbl_page_size_log; /* for the pages that contain the
346*14b24e2bSVaishali Kulkarni 		       * pointers to the CQ pages
347*14b24e2bSVaishali Kulkarni 		       */
348*14b24e2bSVaishali Kulkarni };
349*14b24e2bSVaishali Kulkarni 
350*14b24e2bSVaishali Kulkarni #ifndef __EXTRACT__LINUX__
351*14b24e2bSVaishali Kulkarni 
352*14b24e2bSVaishali Kulkarni enum roce_mode
353*14b24e2bSVaishali Kulkarni {
354*14b24e2bSVaishali Kulkarni 	ROCE_V1,
355*14b24e2bSVaishali Kulkarni 	ROCE_V2_IPV4,
356*14b24e2bSVaishali Kulkarni 	ROCE_V2_IPV6,
357*14b24e2bSVaishali Kulkarni 	MAX_ROCE_MODE
358*14b24e2bSVaishali Kulkarni };
359*14b24e2bSVaishali Kulkarni 
360*14b24e2bSVaishali Kulkarni struct ecore_rdma_create_qp_in_params {
361*14b24e2bSVaishali Kulkarni 	/* input variables (given by miniport) */
362*14b24e2bSVaishali Kulkarni 	u32	qp_handle_lo; /* QP handle to be written in CQE */
363*14b24e2bSVaishali Kulkarni 	u32	qp_handle_hi;
364*14b24e2bSVaishali Kulkarni 	u32	qp_handle_async_lo; /* QP handle to be written in async event */
365*14b24e2bSVaishali Kulkarni 	u32	qp_handle_async_hi;
366*14b24e2bSVaishali Kulkarni 	bool	use_srq;
367*14b24e2bSVaishali Kulkarni 	bool	signal_all;
368*14b24e2bSVaishali Kulkarni 	bool	fmr_and_reserved_lkey;
369*14b24e2bSVaishali Kulkarni 	u16	pd;
370*14b24e2bSVaishali Kulkarni 	u16	dpi;
371*14b24e2bSVaishali Kulkarni 	u16	sq_cq_id;
372*14b24e2bSVaishali Kulkarni 	u16	sq_num_pages;
373*14b24e2bSVaishali Kulkarni 	u64	sq_pbl_ptr;	/* Not relevant for iWARP */
374*14b24e2bSVaishali Kulkarni 	u8	max_sq_sges;
375*14b24e2bSVaishali Kulkarni 	u16	rq_cq_id;
376*14b24e2bSVaishali Kulkarni 	u16	rq_num_pages;
377*14b24e2bSVaishali Kulkarni 	u64	rq_pbl_ptr;	/* Not relevant for iWARP */
378*14b24e2bSVaishali Kulkarni 	u16	srq_id;
379*14b24e2bSVaishali Kulkarni 	u8	stats_queue;
380*14b24e2bSVaishali Kulkarni };
381*14b24e2bSVaishali Kulkarni 
382*14b24e2bSVaishali Kulkarni struct ecore_rdma_create_qp_out_params {
383*14b24e2bSVaishali Kulkarni 	/* output variables (given to miniport) */
384*14b24e2bSVaishali Kulkarni 	u32		qp_id;
385*14b24e2bSVaishali Kulkarni 	u16		icid;
386*14b24e2bSVaishali Kulkarni 	void		*rq_pbl_virt;
387*14b24e2bSVaishali Kulkarni 	dma_addr_t	rq_pbl_phys;
388*14b24e2bSVaishali Kulkarni 	void		*sq_pbl_virt;
389*14b24e2bSVaishali Kulkarni 	dma_addr_t	sq_pbl_phys;
390*14b24e2bSVaishali Kulkarni };
391*14b24e2bSVaishali Kulkarni 
392*14b24e2bSVaishali Kulkarni struct ecore_rdma_destroy_cq_in_params {
393*14b24e2bSVaishali Kulkarni 	/* input variables (given by miniport) */
394*14b24e2bSVaishali Kulkarni 	u16 icid;
395*14b24e2bSVaishali Kulkarni };
396*14b24e2bSVaishali Kulkarni 
397*14b24e2bSVaishali Kulkarni struct ecore_rdma_destroy_cq_out_params {
398*14b24e2bSVaishali Kulkarni 	/* output variables, provided to the upper layer */
399*14b24e2bSVaishali Kulkarni 
400*14b24e2bSVaishali Kulkarni 	/* Sequence number of completion notification sent for the CQ on
401*14b24e2bSVaishali Kulkarni 	 * the associated CNQ
402*14b24e2bSVaishali Kulkarni 	 */
403*14b24e2bSVaishali Kulkarni 	u16	num_cq_notif;
404*14b24e2bSVaishali Kulkarni };
405*14b24e2bSVaishali Kulkarni 
406*14b24e2bSVaishali Kulkarni /* ECORE GID can be used as IPv4/6 address in RoCE v2 */
407*14b24e2bSVaishali Kulkarni union ecore_gid {
408*14b24e2bSVaishali Kulkarni 	u8 bytes[16];
409*14b24e2bSVaishali Kulkarni 	u16 words[8];
410*14b24e2bSVaishali Kulkarni 	u32 dwords[4];
411*14b24e2bSVaishali Kulkarni 	u64 qwords[2];
412*14b24e2bSVaishali Kulkarni 	u32 ipv4_addr;
413*14b24e2bSVaishali Kulkarni };
414*14b24e2bSVaishali Kulkarni 
415*14b24e2bSVaishali Kulkarni struct ecore_rdma_modify_qp_in_params {
416*14b24e2bSVaishali Kulkarni 	/* input variables (given by miniport) */
417*14b24e2bSVaishali Kulkarni 	u32		modify_flags;
418*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK               0x1
419*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT              0
420*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_PKEY_MASK                    0x1
421*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_PKEY_SHIFT                   1
422*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK             0x1
423*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT            2
424*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_DEST_QP_MASK                 0x1
425*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT                3
426*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK          0x1
427*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT         4
428*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK                  0x1
429*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT                 5
430*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK                  0x1
431*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT                 6
432*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK       0x1
433*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT      7
434*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK      0x1
435*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT     8
436*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK             0x1
437*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT            9
438*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK               0x1
439*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT              10
440*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK           0x1
441*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT          11
442*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK       0x1
443*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT      12
444*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK     0x1
445*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT    13
446*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK               0x1
447*14b24e2bSVaishali Kulkarni #define ECORE_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT              14
448*14b24e2bSVaishali Kulkarni 
449*14b24e2bSVaishali Kulkarni 	enum ecore_roce_qp_state	new_state;
450*14b24e2bSVaishali Kulkarni 	u16		pkey;
451*14b24e2bSVaishali Kulkarni 	bool		incoming_rdma_read_en;
452*14b24e2bSVaishali Kulkarni 	bool		incoming_rdma_write_en;
453*14b24e2bSVaishali Kulkarni 	bool		incoming_atomic_en;
454*14b24e2bSVaishali Kulkarni 	bool		e2e_flow_control_en;
455*14b24e2bSVaishali Kulkarni 	u32		dest_qp;
456*14b24e2bSVaishali Kulkarni 	u16		mtu;
457*14b24e2bSVaishali Kulkarni 	u8		traffic_class_tos; /* IPv6/GRH tc; IPv4 TOS */
458*14b24e2bSVaishali Kulkarni 	u8		hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
459*14b24e2bSVaishali Kulkarni 	u32		flow_label; /* ignored in IPv4 */
460*14b24e2bSVaishali Kulkarni 	union ecore_gid	sgid; /* GRH SGID; IPv4/6 Source IP */
461*14b24e2bSVaishali Kulkarni 	union ecore_gid	dgid; /* GRH DGID; IPv4/6 Destination IP */
462*14b24e2bSVaishali Kulkarni 	u16		udp_src_port; /* RoCEv2 only */
463*14b24e2bSVaishali Kulkarni 
464*14b24e2bSVaishali Kulkarni 	u16		vlan_id;
465*14b24e2bSVaishali Kulkarni 
466*14b24e2bSVaishali Kulkarni 	u32		rq_psn;
467*14b24e2bSVaishali Kulkarni 	u32		sq_psn;
468*14b24e2bSVaishali Kulkarni 	u8		max_rd_atomic_resp;
469*14b24e2bSVaishali Kulkarni 	u8		max_rd_atomic_req;
470*14b24e2bSVaishali Kulkarni 	u32		ack_timeout;
471*14b24e2bSVaishali Kulkarni 	u8		retry_cnt;
472*14b24e2bSVaishali Kulkarni 	u8		rnr_retry_cnt;
473*14b24e2bSVaishali Kulkarni 	u8		min_rnr_nak_timer;
474*14b24e2bSVaishali Kulkarni 	bool		sqd_async;
475*14b24e2bSVaishali Kulkarni 	u8		remote_mac_addr[6];
476*14b24e2bSVaishali Kulkarni 	u8		local_mac_addr[6];
477*14b24e2bSVaishali Kulkarni 	bool		use_local_mac;
478*14b24e2bSVaishali Kulkarni 	enum roce_mode	roce_mode;
479*14b24e2bSVaishali Kulkarni };
480*14b24e2bSVaishali Kulkarni 
481*14b24e2bSVaishali Kulkarni struct ecore_rdma_query_qp_out_params {
482*14b24e2bSVaishali Kulkarni 	/* output variables (given to miniport) */
483*14b24e2bSVaishali Kulkarni 	enum ecore_roce_qp_state	state;
484*14b24e2bSVaishali Kulkarni 	u32		rq_psn; /* responder */
485*14b24e2bSVaishali Kulkarni 	u32		sq_psn; /* requester */
486*14b24e2bSVaishali Kulkarni 	bool		draining; /* send queue is draining */
487*14b24e2bSVaishali Kulkarni 	u16		mtu;
488*14b24e2bSVaishali Kulkarni 	u32		dest_qp;
489*14b24e2bSVaishali Kulkarni 	bool		incoming_rdma_read_en;
490*14b24e2bSVaishali Kulkarni 	bool		incoming_rdma_write_en;
491*14b24e2bSVaishali Kulkarni 	bool		incoming_atomic_en;
492*14b24e2bSVaishali Kulkarni 	bool		e2e_flow_control_en;
493*14b24e2bSVaishali Kulkarni 	union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
494*14b24e2bSVaishali Kulkarni 	union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
495*14b24e2bSVaishali Kulkarni 	u32		flow_label; /* ignored in IPv4 */
496*14b24e2bSVaishali Kulkarni 	u8		hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
497*14b24e2bSVaishali Kulkarni 	u8		traffic_class_tos; /* IPv6/GRH tc; IPv4 TOS */
498*14b24e2bSVaishali Kulkarni 	u32		timeout;
499*14b24e2bSVaishali Kulkarni 	u8		rnr_retry;
500*14b24e2bSVaishali Kulkarni 	u8		retry_cnt;
501*14b24e2bSVaishali Kulkarni 	u8		min_rnr_nak_timer;
502*14b24e2bSVaishali Kulkarni 	u16		pkey_index;
503*14b24e2bSVaishali Kulkarni 	u8		max_rd_atomic;
504*14b24e2bSVaishali Kulkarni 	u8		max_dest_rd_atomic;
505*14b24e2bSVaishali Kulkarni 	bool		sqd_async;
506*14b24e2bSVaishali Kulkarni };
507*14b24e2bSVaishali Kulkarni 
508*14b24e2bSVaishali Kulkarni struct ecore_rdma_register_tid_in_params {
509*14b24e2bSVaishali Kulkarni 	/* input variables (given by miniport) */
510*14b24e2bSVaishali Kulkarni 	u32	itid; /* index only, 18 bit long, lkey = itid << 8 | key */
511*14b24e2bSVaishali Kulkarni 	enum ecore_rdma_tid_type tid_type;
512*14b24e2bSVaishali Kulkarni 	u8	key;
513*14b24e2bSVaishali Kulkarni 	u16	pd;
514*14b24e2bSVaishali Kulkarni 	bool	local_read;
515*14b24e2bSVaishali Kulkarni 	bool	local_write;
516*14b24e2bSVaishali Kulkarni 	bool	remote_read;
517*14b24e2bSVaishali Kulkarni 	bool	remote_write;
518*14b24e2bSVaishali Kulkarni 	bool	remote_atomic;
519*14b24e2bSVaishali Kulkarni 	bool	mw_bind;
520*14b24e2bSVaishali Kulkarni 	u64	pbl_ptr;
521*14b24e2bSVaishali Kulkarni 	bool	pbl_two_level;
522*14b24e2bSVaishali Kulkarni 	u8	pbl_page_size_log; /* for the pages that contain the pointers
523*14b24e2bSVaishali Kulkarni 		       * to the MR pages
524*14b24e2bSVaishali Kulkarni 		       */
525*14b24e2bSVaishali Kulkarni 	u8	page_size_log; /* for the MR pages */
526*14b24e2bSVaishali Kulkarni 	u32	fbo;
527*14b24e2bSVaishali Kulkarni 	u64	length; /* only lower 40 bits are valid */
528*14b24e2bSVaishali Kulkarni 	u64	vaddr;
529*14b24e2bSVaishali Kulkarni 	bool	zbva;
530*14b24e2bSVaishali Kulkarni 	bool	phy_mr;
531*14b24e2bSVaishali Kulkarni 	bool	dma_mr;
532*14b24e2bSVaishali Kulkarni 
533*14b24e2bSVaishali Kulkarni 	/* DIF related fields */
534*14b24e2bSVaishali Kulkarni 	bool	dif_enabled;
535*14b24e2bSVaishali Kulkarni 	u64	dif_error_addr;
536*14b24e2bSVaishali Kulkarni 	u64	dif_runt_addr;
537*14b24e2bSVaishali Kulkarni };
538*14b24e2bSVaishali Kulkarni 
539*14b24e2bSVaishali Kulkarni struct ecore_rdma_create_srq_in_params	{
540*14b24e2bSVaishali Kulkarni 	u64 pbl_base_addr;
541*14b24e2bSVaishali Kulkarni 	u64 prod_pair_addr;
542*14b24e2bSVaishali Kulkarni 	u16 num_pages;
543*14b24e2bSVaishali Kulkarni 	u16 pd_id;
544*14b24e2bSVaishali Kulkarni 	u16 page_size;
545*14b24e2bSVaishali Kulkarni };
546*14b24e2bSVaishali Kulkarni 
547*14b24e2bSVaishali Kulkarni struct ecore_rdma_create_srq_out_params {
548*14b24e2bSVaishali Kulkarni 	u16 srq_id;
549*14b24e2bSVaishali Kulkarni };
550*14b24e2bSVaishali Kulkarni 
551*14b24e2bSVaishali Kulkarni struct ecore_rdma_destroy_srq_in_params {
552*14b24e2bSVaishali Kulkarni 	u16 srq_id;
553*14b24e2bSVaishali Kulkarni };
554*14b24e2bSVaishali Kulkarni 
555*14b24e2bSVaishali Kulkarni struct ecore_rdma_modify_srq_in_params {
556*14b24e2bSVaishali Kulkarni 	u32 wqe_limit;
557*14b24e2bSVaishali Kulkarni 	u16 srq_id;
558*14b24e2bSVaishali Kulkarni };
559*14b24e2bSVaishali Kulkarni #endif
560*14b24e2bSVaishali Kulkarni 
561*14b24e2bSVaishali Kulkarni struct ecore_rdma_resize_cq_out_params {
562*14b24e2bSVaishali Kulkarni 	/* output variables, provided to the upper layer */
563*14b24e2bSVaishali Kulkarni 	u32 prod; /* CQ producer value on old PBL */
564*14b24e2bSVaishali Kulkarni 	u32 cons; /* CQ consumer value on old PBL */
565*14b24e2bSVaishali Kulkarni };
566*14b24e2bSVaishali Kulkarni 
567*14b24e2bSVaishali Kulkarni struct ecore_rdma_resize_cnq_in_params {
568*14b24e2bSVaishali Kulkarni 	/* input variables (given by miniport) */
569*14b24e2bSVaishali Kulkarni 	u32	cnq_id;
570*14b24e2bSVaishali Kulkarni 	u32	pbl_page_size_log; /* for the pages that contain the
571*14b24e2bSVaishali Kulkarni 			* pointers to the cnq pages
572*14b24e2bSVaishali Kulkarni 			*/
573*14b24e2bSVaishali Kulkarni 	u64	pbl_ptr;
574*14b24e2bSVaishali Kulkarni };
575*14b24e2bSVaishali Kulkarni 
576*14b24e2bSVaishali Kulkarni #ifndef __EXTRACT__LINUX__
577*14b24e2bSVaishali Kulkarni struct ecore_rdma_stats_out_params {
578*14b24e2bSVaishali Kulkarni 	u64	sent_bytes;
579*14b24e2bSVaishali Kulkarni 	u64	sent_pkts;
580*14b24e2bSVaishali Kulkarni 	u64	rcv_bytes;
581*14b24e2bSVaishali Kulkarni 	u64	rcv_pkts;
582*14b24e2bSVaishali Kulkarni 
583*14b24e2bSVaishali Kulkarni 	/* RoCE only */
584*14b24e2bSVaishali Kulkarni 	u64	icrc_errors;		/* wraps at 32 bits */
585*14b24e2bSVaishali Kulkarni 	u64	retransmit_events;	/* wraps at 32 bits */
586*14b24e2bSVaishali Kulkarni 	u64	silent_drops;		/* wraps at 16 bits */
587*14b24e2bSVaishali Kulkarni 	u64	rnr_nacks_sent;		/* wraps at 16 bits */
588*14b24e2bSVaishali Kulkarni 
589*14b24e2bSVaishali Kulkarni 	/* iWARP only */
590*14b24e2bSVaishali Kulkarni 	u64	iwarp_tx_fast_rxmit_cnt;
591*14b24e2bSVaishali Kulkarni 	u64	iwarp_tx_slow_start_cnt;
592*14b24e2bSVaishali Kulkarni 	u64	unalign_rx_comp;
593*14b24e2bSVaishali Kulkarni };
594*14b24e2bSVaishali Kulkarni 
595*14b24e2bSVaishali Kulkarni struct ecore_rdma_counters_out_params {
596*14b24e2bSVaishali Kulkarni 	u64	pd_count;
597*14b24e2bSVaishali Kulkarni 	u64	max_pd;
598*14b24e2bSVaishali Kulkarni 	u64	dpi_count;
599*14b24e2bSVaishali Kulkarni 	u64	max_dpi;
600*14b24e2bSVaishali Kulkarni 	u64	cq_count;
601*14b24e2bSVaishali Kulkarni 	u64	max_cq;
602*14b24e2bSVaishali Kulkarni 	u64	qp_count;
603*14b24e2bSVaishali Kulkarni 	u64	max_qp;
604*14b24e2bSVaishali Kulkarni 	u64	tid_count;
605*14b24e2bSVaishali Kulkarni 	u64	max_tid;
606*14b24e2bSVaishali Kulkarni };
607*14b24e2bSVaishali Kulkarni #endif
608*14b24e2bSVaishali Kulkarni 
609*14b24e2bSVaishali Kulkarni enum _ecore_status_t
610*14b24e2bSVaishali Kulkarni ecore_rdma_add_user(void *rdma_cxt,
611*14b24e2bSVaishali Kulkarni 		    struct ecore_rdma_add_user_out_params *out_params);
612*14b24e2bSVaishali Kulkarni 
613*14b24e2bSVaishali Kulkarni enum _ecore_status_t
614*14b24e2bSVaishali Kulkarni ecore_rdma_alloc_pd(void *rdma_cxt,
615*14b24e2bSVaishali Kulkarni 		    u16	*pd);
616*14b24e2bSVaishali Kulkarni 
617*14b24e2bSVaishali Kulkarni enum _ecore_status_t
618*14b24e2bSVaishali Kulkarni ecore_rdma_alloc_tid(void *rdma_cxt,
619*14b24e2bSVaishali Kulkarni 		     u32 *tid);
620*14b24e2bSVaishali Kulkarni 
621*14b24e2bSVaishali Kulkarni enum _ecore_status_t
622*14b24e2bSVaishali Kulkarni ecore_rdma_create_cq(void *rdma_cxt,
623*14b24e2bSVaishali Kulkarni 		     struct ecore_rdma_create_cq_in_params *params,
624*14b24e2bSVaishali Kulkarni 		     u16 *icid);
625*14b24e2bSVaishali Kulkarni 
626*14b24e2bSVaishali Kulkarni /* Returns a pointer to the responders' CID, which is also a pointer to the
627*14b24e2bSVaishali Kulkarni  * ecore_qp_params struct. Returns NULL in case of failure.
628*14b24e2bSVaishali Kulkarni  */
629*14b24e2bSVaishali Kulkarni struct ecore_rdma_qp*
630*14b24e2bSVaishali Kulkarni ecore_rdma_create_qp(void *rdma_cxt,
631*14b24e2bSVaishali Kulkarni 		     struct ecore_rdma_create_qp_in_params  *in_params,
632*14b24e2bSVaishali Kulkarni 		     struct ecore_rdma_create_qp_out_params *out_params);
633*14b24e2bSVaishali Kulkarni 
634*14b24e2bSVaishali Kulkarni enum _ecore_status_t
635*14b24e2bSVaishali Kulkarni ecore_roce_create_ud_qp(void *rdma_cxt,
636*14b24e2bSVaishali Kulkarni 			struct ecore_rdma_create_qp_out_params *out_params);
637*14b24e2bSVaishali Kulkarni 
638*14b24e2bSVaishali Kulkarni enum _ecore_status_t
639*14b24e2bSVaishali Kulkarni ecore_rdma_deregister_tid(void *rdma_cxt,
640*14b24e2bSVaishali Kulkarni 			  u32		tid);
641*14b24e2bSVaishali Kulkarni 
642*14b24e2bSVaishali Kulkarni enum _ecore_status_t
643*14b24e2bSVaishali Kulkarni ecore_rdma_destroy_cq(void *rdma_cxt,
644*14b24e2bSVaishali Kulkarni 		      struct ecore_rdma_destroy_cq_in_params  *in_params,
645*14b24e2bSVaishali Kulkarni 		      struct ecore_rdma_destroy_cq_out_params *out_params);
646*14b24e2bSVaishali Kulkarni 
647*14b24e2bSVaishali Kulkarni enum _ecore_status_t
648*14b24e2bSVaishali Kulkarni ecore_rdma_destroy_qp(void *rdma_cxt,
649*14b24e2bSVaishali Kulkarni 		      struct ecore_rdma_qp *qp);
650*14b24e2bSVaishali Kulkarni 
651*14b24e2bSVaishali Kulkarni enum _ecore_status_t
652*14b24e2bSVaishali Kulkarni ecore_roce_destroy_ud_qp(void *rdma_cxt, u16 cid);
653*14b24e2bSVaishali Kulkarni 
654*14b24e2bSVaishali Kulkarni void
655*14b24e2bSVaishali Kulkarni ecore_rdma_free_pd(void *rdma_cxt,
656*14b24e2bSVaishali Kulkarni 		   u16	pd);
657*14b24e2bSVaishali Kulkarni 
658*14b24e2bSVaishali Kulkarni void
659*14b24e2bSVaishali Kulkarni ecore_rdma_free_tid(void *rdma_cxt,
660*14b24e2bSVaishali Kulkarni 		    u32	tid);
661*14b24e2bSVaishali Kulkarni 
662*14b24e2bSVaishali Kulkarni enum _ecore_status_t
663*14b24e2bSVaishali Kulkarni ecore_rdma_modify_qp(void *rdma_cxt,
664*14b24e2bSVaishali Kulkarni 		     struct ecore_rdma_qp *qp,
665*14b24e2bSVaishali Kulkarni 		     struct ecore_rdma_modify_qp_in_params *params);
666*14b24e2bSVaishali Kulkarni 
667*14b24e2bSVaishali Kulkarni struct ecore_rdma_device*
668*14b24e2bSVaishali Kulkarni ecore_rdma_query_device(void *rdma_cxt);
669*14b24e2bSVaishali Kulkarni 
670*14b24e2bSVaishali Kulkarni struct ecore_rdma_port*
671*14b24e2bSVaishali Kulkarni ecore_rdma_query_port(void *rdma_cxt);
672*14b24e2bSVaishali Kulkarni 
673*14b24e2bSVaishali Kulkarni enum _ecore_status_t
674*14b24e2bSVaishali Kulkarni ecore_rdma_query_qp(void *rdma_cxt,
675*14b24e2bSVaishali Kulkarni 		    struct ecore_rdma_qp		  *qp,
676*14b24e2bSVaishali Kulkarni 		    struct ecore_rdma_query_qp_out_params *out_params);
677*14b24e2bSVaishali Kulkarni 
678*14b24e2bSVaishali Kulkarni enum _ecore_status_t
679*14b24e2bSVaishali Kulkarni ecore_rdma_register_tid(void *rdma_cxt,
680*14b24e2bSVaishali Kulkarni 			struct ecore_rdma_register_tid_in_params *params);
681*14b24e2bSVaishali Kulkarni 
682*14b24e2bSVaishali Kulkarni void ecore_rdma_remove_user(void *rdma_cxt,
683*14b24e2bSVaishali Kulkarni 			    u16		dpi);
684*14b24e2bSVaishali Kulkarni 
685*14b24e2bSVaishali Kulkarni enum _ecore_status_t
686*14b24e2bSVaishali Kulkarni ecore_rdma_resize_cnq(void *rdma_cxt,
687*14b24e2bSVaishali Kulkarni 		      struct ecore_rdma_resize_cnq_in_params *in_params);
688*14b24e2bSVaishali Kulkarni 
689*14b24e2bSVaishali Kulkarni /*Returns the CQ CID or zero in case of failure */
690*14b24e2bSVaishali Kulkarni enum _ecore_status_t
691*14b24e2bSVaishali Kulkarni ecore_rdma_resize_cq(void *rdma_cxt,
692*14b24e2bSVaishali Kulkarni 		     struct ecore_rdma_resize_cq_in_params  *in_params,
693*14b24e2bSVaishali Kulkarni 		     struct ecore_rdma_resize_cq_out_params *out_params);
694*14b24e2bSVaishali Kulkarni 
695*14b24e2bSVaishali Kulkarni /* Before calling rdma_start upper layer (VBD/qed) should fill the
696*14b24e2bSVaishali Kulkarni  * page-size and mtu in hwfn context
697*14b24e2bSVaishali Kulkarni  */
698*14b24e2bSVaishali Kulkarni enum _ecore_status_t
699*14b24e2bSVaishali Kulkarni ecore_rdma_start(void *p_hwfn,
700*14b24e2bSVaishali Kulkarni 		 struct ecore_rdma_start_in_params *params);
701*14b24e2bSVaishali Kulkarni 
702*14b24e2bSVaishali Kulkarni enum _ecore_status_t
703*14b24e2bSVaishali Kulkarni ecore_rdma_stop(void *rdma_cxt);
704*14b24e2bSVaishali Kulkarni 
705*14b24e2bSVaishali Kulkarni enum _ecore_status_t
706*14b24e2bSVaishali Kulkarni ecore_rdma_query_stats(void *rdma_cxt, u8 stats_queue,
707*14b24e2bSVaishali Kulkarni 		       struct ecore_rdma_stats_out_params *out_parms);
708*14b24e2bSVaishali Kulkarni 
709*14b24e2bSVaishali Kulkarni enum _ecore_status_t
710*14b24e2bSVaishali Kulkarni ecore_rdma_query_counters(void *rdma_cxt,
711*14b24e2bSVaishali Kulkarni 			  struct ecore_rdma_counters_out_params *out_parms);
712*14b24e2bSVaishali Kulkarni 
713*14b24e2bSVaishali Kulkarni u32 ecore_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id);
714*14b24e2bSVaishali Kulkarni 
715*14b24e2bSVaishali Kulkarni u32 ecore_rdma_query_cau_timer_res(void *p_hwfn);
716*14b24e2bSVaishali Kulkarni 
717*14b24e2bSVaishali Kulkarni void ecore_rdma_cnq_prod_update(void *rdma_cxt, u8 cnq_index, u16 prod);
718*14b24e2bSVaishali Kulkarni 
719*14b24e2bSVaishali Kulkarni void ecore_rdma_resc_free(struct ecore_hwfn *p_hwfn);
720*14b24e2bSVaishali Kulkarni 
721*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
722*14b24e2bSVaishali Kulkarni 
723*14b24e2bSVaishali Kulkarni /* iWARP API */
724*14b24e2bSVaishali Kulkarni 
725*14b24e2bSVaishali Kulkarni #ifndef __EXTRACT__LINUX__
726*14b24e2bSVaishali Kulkarni 
727*14b24e2bSVaishali Kulkarni enum ecore_iwarp_event_type {
728*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_MPA_REQUEST, /* Passive side request received */
729*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_PASSIVE_COMPLETE, /* Passive side established
730*14b24e2bSVaishali Kulkarni 					     * ( ack on mpa response )
731*14b24e2bSVaishali Kulkarni 					     */
732*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_ACTIVE_COMPLETE, /* Active side reply received */
733*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_DISCONNECT,
734*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_CLOSE,
735*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_IRQ_FULL,
736*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_RQ_EMPTY,
737*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_LLP_TIMEOUT,
738*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_REMOTE_PROTECTION_ERROR,
739*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_CQ_OVERFLOW,
740*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_QP_CATASTROPHIC,
741*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_ACTIVE_MPA_REPLY,
742*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_LOCAL_ACCESS_ERROR,
743*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_REMOTE_OPERATION_ERROR,
744*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EVENT_TERMINATE_RECEIVED
745*14b24e2bSVaishali Kulkarni };
746*14b24e2bSVaishali Kulkarni 
747*14b24e2bSVaishali Kulkarni enum ecore_tcp_ip_version
748*14b24e2bSVaishali Kulkarni {
749*14b24e2bSVaishali Kulkarni 	ECORE_TCP_IPV4,
750*14b24e2bSVaishali Kulkarni 	ECORE_TCP_IPV6,
751*14b24e2bSVaishali Kulkarni };
752*14b24e2bSVaishali Kulkarni 
753*14b24e2bSVaishali Kulkarni struct ecore_iwarp_cm_info {
754*14b24e2bSVaishali Kulkarni 	enum ecore_tcp_ip_version ip_version;
755*14b24e2bSVaishali Kulkarni 	u32 remote_ip[4];
756*14b24e2bSVaishali Kulkarni 	u32 local_ip[4];
757*14b24e2bSVaishali Kulkarni 	u16 remote_port;
758*14b24e2bSVaishali Kulkarni 	u16 local_port;
759*14b24e2bSVaishali Kulkarni 	u16 vlan;
760*14b24e2bSVaishali Kulkarni 	const void *private_data;
761*14b24e2bSVaishali Kulkarni 	u16 private_data_len;
762*14b24e2bSVaishali Kulkarni 	u8 ord;
763*14b24e2bSVaishali Kulkarni 	u8 ird;
764*14b24e2bSVaishali Kulkarni };
765*14b24e2bSVaishali Kulkarni 
766*14b24e2bSVaishali Kulkarni struct ecore_iwarp_cm_event_params {
767*14b24e2bSVaishali Kulkarni 	enum ecore_iwarp_event_type event;
768*14b24e2bSVaishali Kulkarni 	const struct ecore_iwarp_cm_info *cm_info;
769*14b24e2bSVaishali Kulkarni 	void *ep_context; /* To be passed to accept call */
770*14b24e2bSVaishali Kulkarni 	int status;
771