1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_RDMA_H__
37*14b24e2bSVaishali Kulkarni #define __ECORE_RDMA_H__
38*14b24e2bSVaishali Kulkarni 
39*14b24e2bSVaishali Kulkarni #include "ecore_status.h"
40*14b24e2bSVaishali Kulkarni #include "ecore.h"
41*14b24e2bSVaishali Kulkarni #include "ecore_hsi_common.h"
42*14b24e2bSVaishali Kulkarni #include "ecore_proto_if.h"
43*14b24e2bSVaishali Kulkarni #include "ecore_roce_api.h"
44*14b24e2bSVaishali Kulkarni #include "ecore_dev_api.h"
45*14b24e2bSVaishali Kulkarni 
46*14b24e2bSVaishali Kulkarni /* Constants */
47*14b24e2bSVaishali Kulkarni 
48*14b24e2bSVaishali Kulkarni /* HW/FW RoCE Limitations (internal. For external see ecore_rdma_api.h) */
49*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_FMR                    (RDMA_MAX_TIDS) /* 2^17 - 1 */
50*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_P_KEY                  (1)
51*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_WQE                    (0x7FFF) /* 2^15 -1 */
52*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_SRQ_WQE_ELEM           (0x7FFF) /* 2^15 -1 */
53*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_PAGE_SIZE_CAPS             (0xFFFFF000) /* TODO: > 4k?! */
54*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_ACK_DELAY                  (15) /* 131 milliseconds */
55*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_MR_SIZE                (0x10000000000ULL) /* 2^40 */
56*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_CQS                    (RDMA_MAX_CQS) /* 64k */
57*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_MRS                    (RDMA_MAX_TIDS) /* 2^17 - 1 */
58*14b24e2bSVaishali Kulkarni /* Add 1 for header element */
59*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_SRQ_ELEM_PER_WQE	      (RDMA_MAX_SGE_PER_RQ_WQE + 1)
60*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_SGE_PER_SRQ_WQE	      (RDMA_MAX_SGE_PER_RQ_WQE)
61*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_SRQ_WQE_ELEM_SIZE          (16)
62*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_SRQS		      (32 * 1024) /* 32k */
63*14b24e2bSVaishali Kulkarni 
64*14b24e2bSVaishali Kulkarni /* Configurable */
65*14b24e2bSVaishali Kulkarni /* Max CQE is derived from u16/32 size, halved and decremented by 1 to handle
66*14b24e2bSVaishali Kulkarni  * wrap properly and then decremented by 1 again. The latter decrement comes
67*14b24e2bSVaishali Kulkarni  * from a requirement to create a chain that is bigger than what the user
68*14b24e2bSVaishali Kulkarni  * requested by one:
69*14b24e2bSVaishali Kulkarni  * The CQE size is 32 bytes but the FW writes in chunks of 64
70*14b24e2bSVaishali Kulkarni  * bytes, for performance purposes. Allocating an extra entry and telling the
71*14b24e2bSVaishali Kulkarni  * FW we have less prevents overwriting the first entry in case of a wrap i.e.
72*14b24e2bSVaishali Kulkarni  * when the FW writes the last entry and the application hasn't read the first
73*14b24e2bSVaishali Kulkarni  * one.
74*14b24e2bSVaishali Kulkarni  */
75*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_CQE_32_BIT             (0x7FFFFFFF - 1)
76*14b24e2bSVaishali Kulkarni #define ECORE_RDMA_MAX_CQE_16_BIT             (0x7FFF - 1)
77*14b24e2bSVaishali Kulkarni 
78*14b24e2bSVaishali Kulkarni enum ecore_rdma_toggle_bit {
79*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_TOGGLE_BIT_CLEAR = 0,
80*14b24e2bSVaishali Kulkarni 	ECORE_RDMA_TOGGLE_BIT_SET   = 1
81*14b24e2bSVaishali Kulkarni };
82*14b24e2bSVaishali Kulkarni 
83*14b24e2bSVaishali Kulkarni /* @@@TBD Currently we support only affilited events
84*14b24e2bSVaishali Kulkarni    * enum ecore_rdma_unaffiliated_event_code {
85*14b24e2bSVaishali Kulkarni    * ECORE_RDMA_PORT_ACTIVE, // Link Up
86*14b24e2bSVaishali Kulkarni    * ECORE_RDMA_PORT_CHANGED, // SGID table has changed
87*14b24e2bSVaishali Kulkarni    * ECORE_RDMA_LOCAL_CATASTROPHIC_ERR, // Fatal device error
88*14b24e2bSVaishali Kulkarni    * ECORE_RDMA_PORT_ERR, // Link down
89*14b24e2bSVaishali Kulkarni    * };
90*14b24e2bSVaishali Kulkarni    */
91*14b24e2bSVaishali Kulkarni 
92*14b24e2bSVaishali Kulkarni #define QEDR_MAX_BMAP_NAME	(10)
93*14b24e2bSVaishali Kulkarni struct ecore_bmap {
94*14b24e2bSVaishali Kulkarni 	u32           max_count;
95*14b24e2bSVaishali Kulkarni 	unsigned long *bitmap;
96*14b24e2bSVaishali Kulkarni 	char name[QEDR_MAX_BMAP_NAME];
97*14b24e2bSVaishali Kulkarni };
98*14b24e2bSVaishali Kulkarni 
99*14b24e2bSVaishali Kulkarni /* functions for enabling/disabling edpm in rdma PFs according to existence of
100*14b24e2bSVaishali Kulkarni  * qps during DCBx update or bar size
101*14b24e2bSVaishali Kulkarni  */
102*14b24e2bSVaishali Kulkarni void ecore_roce_dpm_dcbx(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
103*14b24e2bSVaishali Kulkarni void ecore_rdma_dpm_bar(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
104*14b24e2bSVaishali Kulkarni 
105*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
106*14b24e2bSVaishali Kulkarni 
107*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_PREALLOC_CNT	(256)
108*14b24e2bSVaishali Kulkarni 
109*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_LL2_SYN_TX_SIZE	(128)
110*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_LL2_SYN_RX_SIZE	(256)
111*14b24e2bSVaishali Kulkarni 
112*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_LL2_OOO_DEF_TX_SIZE	(256)
113*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_LL2_OOO_DEF_RX_SIZE	(4096)
114*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_LL2_OOO_MAX_RX_SIZE	(16384)
115*14b24e2bSVaishali Kulkarni 
116*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_MAX_SYN_PKT_SIZE	(128)
117*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_HANDLE_INVAL	(0xff)
118*14b24e2bSVaishali Kulkarni 
119*14b24e2bSVaishali Kulkarni struct ecore_iwarp_ll2_buff {
120*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_ll2_buff	*piggy_buf;
121*14b24e2bSVaishali Kulkarni 	void 				*data;
122*14b24e2bSVaishali Kulkarni 	dma_addr_t			data_phys_addr;
123*14b24e2bSVaishali Kulkarni 	u32				buff_size;
124*14b24e2bSVaishali Kulkarni };
125*14b24e2bSVaishali Kulkarni 
126*14b24e2bSVaishali Kulkarni struct ecore_iwarp_ll2_mpa_buf {
127*14b24e2bSVaishali Kulkarni 	osal_list_entry_t		list_entry;
128*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_ll2_buff	*ll2_buf;
129*14b24e2bSVaishali Kulkarni 	struct unaligned_opaque_data	data;
130*14b24e2bSVaishali Kulkarni 	u16				tcp_payload_len;
131*14b24e2bSVaishali Kulkarni 	u8				placement_offset;
132*14b24e2bSVaishali Kulkarni };
133*14b24e2bSVaishali Kulkarni 
134*14b24e2bSVaishali Kulkarni /* In some cases a fpdu will arrive with only one byte of the header, in this
135*14b24e2bSVaishali Kulkarni  * case the fpdu_length will be partial ( contain only higher byte and
136*14b24e2bSVaishali Kulkarni  * incomplete bytes will contain the invalid value */
137*14b24e2bSVaishali Kulkarni #define ECORE_IWARP_INVALID_INCOMPLETE_BYTES 0xffff
138*14b24e2bSVaishali Kulkarni 
139*14b24e2bSVaishali Kulkarni struct ecore_iwarp_fpdu {
140*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_ll2_buff 	*mpa_buf;
141*14b24e2bSVaishali Kulkarni 	dma_addr_t			pkt_hdr;
142*14b24e2bSVaishali Kulkarni 	u8				pkt_hdr_size;
143*14b24e2bSVaishali Kulkarni 	dma_addr_t			mpa_frag;
144*14b24e2bSVaishali Kulkarni 	void				*mpa_frag_virt;
145*14b24e2bSVaishali Kulkarni 	u16				mpa_frag_len;
146*14b24e2bSVaishali Kulkarni 	u16				fpdu_length;
147*14b24e2bSVaishali Kulkarni 	u16				incomplete_bytes;
148*14b24e2bSVaishali Kulkarni };
149*14b24e2bSVaishali Kulkarni 
150*14b24e2bSVaishali Kulkarni struct ecore_iwarp_info {
151*14b24e2bSVaishali Kulkarni 	osal_list_t			listen_list; /* ecore_iwarp_listener */
152*14b24e2bSVaishali Kulkarni 	osal_list_t			ep_list;     /* ecore_iwarp_ep */
153*14b24e2bSVaishali Kulkarni 	osal_list_t			ep_free_list;/* pre-allocated ep's */
154*14b24e2bSVaishali Kulkarni 	osal_list_t			mpa_buf_list;/* list of mpa_bufs */
155*14b24e2bSVaishali Kulkarni 	osal_list_t			mpa_buf_pending_list;
156*14b24e2bSVaishali Kulkarni 	osal_spinlock_t			iw_lock;
157*14b24e2bSVaishali Kulkarni 	osal_spinlock_t			qp_lock; /* for teardown races */
158*14b24e2bSVaishali Kulkarni 	struct iwarp_rxmit_stats_drv	stats;
159*14b24e2bSVaishali Kulkarni 	u32				rcv_wnd_scale;
160*14b24e2bSVaishali Kulkarni 	u16				max_mtu;
161*14b24e2bSVaishali Kulkarni 	u16				num_ooo_rx_bufs;
162*14b24e2bSVaishali Kulkarni 	u8				mac_addr[ETH_ALEN];
163*14b24e2bSVaishali Kulkarni 	u8				crc_needed;
164*14b24e2bSVaishali Kulkarni 	u8				tcp_flags;
165*14b24e2bSVaishali Kulkarni 	u8				ll2_syn_handle;
166*14b24e2bSVaishali Kulkarni 	u8				ll2_ooo_handle;
167*14b24e2bSVaishali Kulkarni 	u8				ll2_mpa_handle;
168*14b24e2bSVaishali Kulkarni 	u8				peer2peer;
169*14b24e2bSVaishali Kulkarni 	u8				_pad;
170*14b24e2bSVaishali Kulkarni 	enum mpa_negotiation_mode	mpa_rev;
171*14b24e2bSVaishali Kulkarni 	enum mpa_rtr_type		rtr_type;
172*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_fpdu		*partial_fpdus;
173*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_ll2_mpa_buf  *mpa_bufs;
174*14b24e2bSVaishali Kulkarni 	u8				*mpa_intermediate_buf;
175*14b24e2bSVaishali Kulkarni 	u16				max_num_partial_fpdus;
176*14b24e2bSVaishali Kulkarni 
177*14b24e2bSVaishali Kulkarni 	/* MPA statistics */
178*14b24e2bSVaishali Kulkarni 	u64				unalign_rx_comp;
179*14b24e2bSVaishali Kulkarni };
180*14b24e2bSVaishali Kulkarni #endif
181*14b24e2bSVaishali Kulkarni 
182*14b24e2bSVaishali Kulkarni #define IS_ECORE_DCQCN(p_hwfn)	\
183*14b24e2bSVaishali Kulkarni 	(!!(p_hwfn->pf_params.rdma_pf_params.enable_dcqcn))
184*14b24e2bSVaishali Kulkarni 
185*14b24e2bSVaishali Kulkarni struct ecore_roce_info {
186*14b24e2bSVaishali Kulkarni 	struct roce_events_stats	event_stats;
187*14b24e2bSVaishali Kulkarni 
188*14b24e2bSVaishali Kulkarni 	u8				dcqcn_enabled;
189*14b24e2bSVaishali Kulkarni 	u8				dcqcn_reaction_point;
190*14b24e2bSVaishali Kulkarni };
191*14b24e2bSVaishali Kulkarni 
192*14b24e2bSVaishali Kulkarni struct ecore_rdma_info {
193*14b24e2bSVaishali Kulkarni 	osal_spinlock_t			lock;
194*14b24e2bSVaishali Kulkarni 
195*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		cq_map;
196*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		pd_map;
197*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		tid_map;
198*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		srq_map;
199*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		cid_map;
200*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		tcp_cid_map;
201*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		real_cid_map;
202*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		dpi_map;
203*14b24e2bSVaishali Kulkarni 	struct ecore_bmap		toggle_bits;
204*14b24e2bSVaishali Kulkarni 	struct ecore_rdma_events	events;
205*14b24e2bSVaishali Kulkarni 	struct ecore_rdma_device	*dev;
206*14b24e2bSVaishali Kulkarni 	struct ecore_rdma_port		*port;
207*14b24e2bSVaishali Kulkarni 	u32				last_tid;
208*14b24e2bSVaishali Kulkarni 	u8				num_cnqs;
209*14b24e2bSVaishali Kulkarni 	struct rdma_sent_stats          rdma_sent_pstats;
210*14b24e2bSVaishali Kulkarni 	struct rdma_rcv_stats           rdma_rcv_tstats;
211*14b24e2bSVaishali Kulkarni 	u32				num_qps;
212*14b24e2bSVaishali Kulkarni 	u32				num_mrs;
213*14b24e2bSVaishali Kulkarni 	u32				num_srqs;
214*14b24e2bSVaishali Kulkarni 	u16				queue_zone_base;
215*14b24e2bSVaishali Kulkarni 	u16				max_queue_zones;
216*14b24e2bSVaishali Kulkarni 	enum protocol_type		proto;
217*14b24e2bSVaishali Kulkarni 	struct ecore_roce_info		roce;
218*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
219*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_info		iwarp;
220*14b24e2bSVaishali Kulkarni #endif
221*14b24e2bSVaishali Kulkarni 	bool				active;
222*14b24e2bSVaishali Kulkarni 	int				ref_cnt;
223*14b24e2bSVaishali Kulkarni };
224*14b24e2bSVaishali Kulkarni 
225*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
226*14b24e2bSVaishali Kulkarni enum ecore_iwarp_qp_state {
227*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_QP_STATE_IDLE,
228*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_QP_STATE_RTS,
229*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_QP_STATE_TERMINATE,
230*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_QP_STATE_CLOSING,
231*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_QP_STATE_ERROR,
232*14b24e2bSVaishali Kulkarni };
233*14b24e2bSVaishali Kulkarni #endif
234*14b24e2bSVaishali Kulkarni 
235*14b24e2bSVaishali Kulkarni struct ecore_rdma_qp {
236*14b24e2bSVaishali Kulkarni 	struct regpair qp_handle;
237*14b24e2bSVaishali Kulkarni 	struct regpair qp_handle_async;
238*14b24e2bSVaishali Kulkarni 	u32	qpid; /* iwarp: may differ from icid */
239*14b24e2bSVaishali Kulkarni 	u16	icid;
240*14b24e2bSVaishali Kulkarni 	enum ecore_roce_qp_state cur_state;
241*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
242*14b24e2bSVaishali Kulkarni 	enum ecore_iwarp_qp_state iwarp_state;
243*14b24e2bSVaishali Kulkarni #endif
244*14b24e2bSVaishali Kulkarni 	bool	use_srq;
245*14b24e2bSVaishali Kulkarni 	bool	signal_all;
246*14b24e2bSVaishali Kulkarni 	bool	fmr_and_reserved_lkey;
247*14b24e2bSVaishali Kulkarni 
248*14b24e2bSVaishali Kulkarni 	bool	incoming_rdma_read_en;
249*14b24e2bSVaishali Kulkarni 	bool	incoming_rdma_write_en;
250*14b24e2bSVaishali Kulkarni 	bool	incoming_atomic_en;
251*14b24e2bSVaishali Kulkarni 	bool	e2e_flow_control_en;
252*14b24e2bSVaishali Kulkarni 
253*14b24e2bSVaishali Kulkarni 	u16	pd;			/* Protection domain */
254*14b24e2bSVaishali Kulkarni 	u16	pkey;			/* Primary P_key index */
255*14b24e2bSVaishali Kulkarni 	u32	dest_qp;
256*14b24e2bSVaishali Kulkarni 	u16	mtu;
257*14b24e2bSVaishali Kulkarni 	u16	srq_id;
258*14b24e2bSVaishali Kulkarni 	u8	traffic_class_tos;	/* IPv6/GRH traffic class; IPv4 TOS */
259*14b24e2bSVaishali Kulkarni 	u8	hop_limit_ttl;		/* IPv6/GRH hop limit; IPv4 TTL */
260*14b24e2bSVaishali Kulkarni 	u16	dpi;
261*14b24e2bSVaishali Kulkarni 	u32	flow_label;		/* ignored in IPv4 */
262*14b24e2bSVaishali Kulkarni 	u16	vlan_id;
263*14b24e2bSVaishali Kulkarni 	u32	ack_timeout;
264*14b24e2bSVaishali Kulkarni 	u8	retry_cnt;
265*14b24e2bSVaishali Kulkarni 	u8	rnr_retry_cnt;
266*14b24e2bSVaishali Kulkarni 	u8	min_rnr_nak_timer;
267*14b24e2bSVaishali Kulkarni 	bool	sqd_async;
268*14b24e2bSVaishali Kulkarni 	union ecore_gid	sgid;		/* GRH SGID; IPv4/6 Source IP */
269*14b24e2bSVaishali Kulkarni 	union ecore_gid	dgid;		/* GRH DGID; IPv4/6 Destination IP */
270*14b24e2bSVaishali Kulkarni 	enum roce_mode roce_mode;
271*14b24e2bSVaishali Kulkarni 	u16	udp_src_port;		/* RoCEv2 only */
272*14b24e2bSVaishali Kulkarni 	u8	stats_queue;
273*14b24e2bSVaishali Kulkarni 
274*14b24e2bSVaishali Kulkarni 	/* requeseter */
275*14b24e2bSVaishali Kulkarni 	u8	max_rd_atomic_req;
276*14b24e2bSVaishali Kulkarni 	u32     sq_psn;
277*14b24e2bSVaishali Kulkarni 	u16	sq_cq_id; /* The cq to be associated with the send queue*/
278*14b24e2bSVaishali Kulkarni 	u16	sq_num_pages;
279*14b24e2bSVaishali Kulkarni 	dma_addr_t sq_pbl_ptr;
280*14b24e2bSVaishali Kulkarni 	void	*orq;
281*14b24e2bSVaishali Kulkarni 	dma_addr_t orq_phys_addr;
282*14b24e2bSVaishali Kulkarni 	u8	orq_num_pages;
283*14b24e2bSVaishali Kulkarni 	bool	req_offloaded;
284*14b24e2bSVaishali Kulkarni 
285*14b24e2bSVaishali Kulkarni 	/* responder */
286*14b24e2bSVaishali Kulkarni 	u8	max_rd_atomic_resp;
287*14b24e2bSVaishali Kulkarni 	u32     rq_psn;
288*14b24e2bSVaishali Kulkarni 	u16	rq_cq_id; /* The cq to be associated with the receive queue */
289*14b24e2bSVaishali Kulkarni 	u16	rq_num_pages;
290*14b24e2bSVaishali Kulkarni 	dma_addr_t rq_pbl_ptr;
291*14b24e2bSVaishali Kulkarni 	void	*irq;
292*14b24e2bSVaishali Kulkarni 	dma_addr_t irq_phys_addr;
293*14b24e2bSVaishali Kulkarni 	u8	irq_num_pages;
294*14b24e2bSVaishali Kulkarni 	bool	resp_offloaded;
295*14b24e2bSVaishali Kulkarni 	u32	cq_prod;
296*14b24e2bSVaishali Kulkarni 
297*14b24e2bSVaishali Kulkarni 	u8	remote_mac_addr[6];
298*14b24e2bSVaishali Kulkarni 	u8	local_mac_addr[6];
299*14b24e2bSVaishali Kulkarni 
300*14b24e2bSVaishali Kulkarni 	void	*shared_queue;
301*14b24e2bSVaishali Kulkarni 	dma_addr_t shared_queue_phys_addr;
302*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
303*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_ep *ep;
304*14b24e2bSVaishali Kulkarni #endif
305*14b24e2bSVaishali Kulkarni };
306*14b24e2bSVaishali Kulkarni 
307*14b24e2bSVaishali Kulkarni #ifdef CONFIG_ECORE_IWARP
308*14b24e2bSVaishali Kulkarni 
309*14b24e2bSVaishali Kulkarni enum ecore_iwarp_ep_state {
310*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EP_INIT,
311*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EP_MPA_REQ_RCVD,
312*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EP_MPA_OFFLOADED,
313*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EP_ESTABLISHED,
314*14b24e2bSVaishali Kulkarni 	ECORE_IWARP_EP_CLOSED
315*14b24e2bSVaishali Kulkarni };
316*14b24e2bSVaishali Kulkarni 
317*14b24e2bSVaishali Kulkarni union async_output {
318*14b24e2bSVaishali Kulkarni 	struct iwarp_eqe_data_mpa_async_completion mpa_response;
319*14b24e2bSVaishali Kulkarni 	struct iwarp_eqe_data_tcp_async_completion mpa_request;
320*14b24e2bSVaishali Kulkarni };
321*14b24e2bSVaishali Kulkarni 
322*14b24e2bSVaishali Kulkarni /* Endpoint structure represents a TCP connection. This connection can be
323*14b24e2bSVaishali Kulkarni  * associated with a QP or not (in which case QP==NULL)
324*14b24e2bSVaishali Kulkarni  */
325*14b24e2bSVaishali Kulkarni struct ecore_iwarp_ep {
326*14b24e2bSVaishali Kulkarni 	osal_list_entry_t		list_entry;
327*14b24e2bSVaishali Kulkarni 	int				sig;
328*14b24e2bSVaishali Kulkarni 	struct ecore_rdma_qp		*qp;
329*14b24e2bSVaishali Kulkarni 	enum ecore_iwarp_ep_state	state;
330*14b24e2bSVaishali Kulkarni 
331*14b24e2bSVaishali Kulkarni 	/* This contains entire buffer required for ep memories. This is the
332*14b24e2bSVaishali Kulkarni 	 * only one actually allocated and freed. The rest are pointers into
333*14b24e2bSVaishali Kulkarni 	 * this buffer
334*14b24e2bSVaishali Kulkarni 	 */
335*14b24e2bSVaishali Kulkarni 	void				*ep_buffer_virt;
336*14b24e2bSVaishali Kulkarni 	dma_addr_t			ep_buffer_phys;
337*14b24e2bSVaishali Kulkarni 
338*14b24e2bSVaishali Kulkarni 	/* Asynce EQE events contain only the ep pointer on the completion. The
339*14b24e2bSVaishali Kulkarni 	 * rest of the data is written to an output buffer pre-allocated by
340*14b24e2bSVaishali Kulkarni 	 * the driver. This buffer points to a location in the ep_buffer.
341*14b24e2bSVaishali Kulkarni 	 */
342*14b24e2bSVaishali Kulkarni 	union async_output		*async_output_virt;
343*14b24e2bSVaishali Kulkarni 	dma_addr_t			async_output_phys;
344*14b24e2bSVaishali Kulkarni 
345*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_cm_info	cm_info;
346*14b24e2bSVaishali Kulkarni 	enum tcp_connect_mode		connect_mode;
347*14b24e2bSVaishali Kulkarni 	enum mpa_rtr_type		rtr_type;
348*14b24e2bSVaishali Kulkarni 	enum mpa_negotiation_mode	mpa_rev;
349*14b24e2bSVaishali Kulkarni 	u32				tcp_cid;
350*14b24e2bSVaishali Kulkarni 	u32				cid;
351*14b24e2bSVaishali Kulkarni 	u8				remote_mac_addr[6];
352*14b24e2bSVaishali Kulkarni 	u8				local_mac_addr[6];
353*14b24e2bSVaishali Kulkarni 	u16				mss;
354*14b24e2bSVaishali Kulkarni 	bool				mpa_reply_processed;
355*14b24e2bSVaishali Kulkarni 
356*14b24e2bSVaishali Kulkarni 	/* The event_cb function is called for asynchrounous events associated
357*14b24e2bSVaishali Kulkarni 	 * with the ep. It is initialized at different entry points depending
358*14b24e2bSVaishali Kulkarni 	 * on whether the ep is the tcp connection active side or passive side
359*14b24e2bSVaishali Kulkarni 	 * The cb_context is passed to the event_cb function.
360*14b24e2bSVaishali Kulkarni 	 */
361*14b24e2bSVaishali Kulkarni 	iwarp_event_handler		event_cb;
362*14b24e2bSVaishali Kulkarni 	void				*cb_context;
363*14b24e2bSVaishali Kulkarni 
364*14b24e2bSVaishali Kulkarni 	/* For Passive side - syn packet related data */
365*14b24e2bSVaishali Kulkarni 	struct ecore_iwarp_ll2_buff	*syn;
366*14b24e2bSVaishali Kulkarni 	u16				syn_ip_payload_length;
367*14b24e2bSVaishali Kulkarni 	dma_addr_t			syn_phy_addr;
368*14b24e2bSVaishali Kulkarni };
369*14b24e2bSVaishali Kulkarni 
370*14b24e2bSVaishali Kulkarni struct ecore_iwarp_listener {
371*14b24e2bSVaishali Kulkarni 	osal_list_entry_t	list_entry;
372*14b24e2bSVaishali Kulkarni 
373*14b24e2bSVaishali Kulkarni 	/* The event_cb function is called for connection requests.
374*14b24e2bSVaishali Kulkarni 	 * The cb_context is passed to the event_cb function.
375*14b24e2bSVaishali Kulkarni 	 */
376*14b24e2bSVaishali Kulkarni 	iwarp_event_handler	event_cb;
377*14b24e2bSVaishali Kulkarni 	void			*cb_context;
378*14b24e2bSVaishali Kulkarni 	u32			max_backlog;
379*14b24e2bSVaishali Kulkarni 	u8			ip_version;
380*14b24e2bSVaishali Kulkarni 	u32			ip_addr[4];
381*14b24e2bSVaishali Kulkarni 	u16			port;
382*14b24e2bSVaishali Kulkarni 	u16			vlan;
383*14b24e2bSVaishali Kulkarni };
384*14b24e2bSVaishali Kulkarni 
385*14b24e2bSVaishali Kulkarni void ecore_iwarp_async_event(struct ecore_hwfn *p_hwfn,
386*14b24e2bSVaishali Kulkarni 			     u8 fw_event_code,
387*14b24e2bSVaishali Kulkarni 			     struct regpair *fw_handle,
388*14b24e2bSVaishali Kulkarni 			     u8 fw_return_code);
389*14b24e2bSVaishali Kulkarni 
390*14b24e2bSVaishali Kulkarni #endif /* CONFIG_ECORE_IWARP */
391*14b24e2bSVaishali Kulkarni 
392*14b24e2bSVaishali Kulkarni void ecore_roce_async_event(struct ecore_hwfn *p_hwfn,
393*14b24e2bSVaishali Kulkarni 			    u8 fw_event_code,
394*14b24e2bSVaishali Kulkarni 			    union rdma_eqe_data *rdma_data);
395*14b24e2bSVaishali Kulkarni 
396*14b24e2bSVaishali Kulkarni enum _ecore_status_t ecore_rdma_info_alloc(struct ecore_hwfn *p_hwfn);
397*14b24e2bSVaishali Kulkarni void ecore_rdma_info_free(struct ecore_hwfn *p_hwfn);
398*14b24e2bSVaishali Kulkarni 
399*14b24e2bSVaishali Kulkarni #endif /*__ECORE_RDMA_H__*/