114b24e2bSVaishali Kulkarni /*
214b24e2bSVaishali Kulkarni * CDDL HEADER START
314b24e2bSVaishali Kulkarni *
414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
514b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
614b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
714b24e2bSVaishali Kulkarni *
814b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
914b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
1014b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
1114b24e2bSVaishali Kulkarni * and limitations under the License.
1214b24e2bSVaishali Kulkarni *
1314b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
1414b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1514b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
1614b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
1714b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
1814b24e2bSVaishali Kulkarni *
1914b24e2bSVaishali Kulkarni * CDDL HEADER END
2014b24e2bSVaishali Kulkarni */
2114b24e2bSVaishali Kulkarni 
2214b24e2bSVaishali Kulkarni /*
2314b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
2414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
2514b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
2614b24e2bSVaishali Kulkarni 
2714b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
2814b24e2bSVaishali Kulkarni 
2914b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
3014b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
3114b24e2bSVaishali Kulkarni 
3214b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
3314b24e2bSVaishali Kulkarni * limitations under the License.
3414b24e2bSVaishali Kulkarni */
3514b24e2bSVaishali Kulkarni 
36b68ddc76SJohn Levon /*
37b68ddc76SJohn Levon  * Copyright 2018 Joyent, Inc.
38b68ddc76SJohn Levon  */
39b68ddc76SJohn Levon 
4014b24e2bSVaishali Kulkarni #include "bcm_osal.h"
4114b24e2bSVaishali Kulkarni #include "ecore.h"
4214b24e2bSVaishali Kulkarni #include "reg_addr.h"
4314b24e2bSVaishali Kulkarni #include "ecore_hw.h"
4414b24e2bSVaishali Kulkarni #include "ecore_hsi_common.h"
4514b24e2bSVaishali Kulkarni #include "ecore_mcp.h"
4614b24e2bSVaishali Kulkarni #include "nvm_cfg.h"
4714b24e2bSVaishali Kulkarni #include "ecore_phy_api.h"
4814b24e2bSVaishali Kulkarni 
4914b24e2bSVaishali Kulkarni #define SERDESID 0x900e
5014b24e2bSVaishali Kulkarni 
5114b24e2bSVaishali Kulkarni 
ecore_phy_read(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 lane,u32 addr,u32 cmd,u8 * buf)5214b24e2bSVaishali Kulkarni enum _ecore_status_t ecore_phy_read(struct ecore_hwfn *p_hwfn,
5314b24e2bSVaishali Kulkarni 				    struct ecore_ptt *p_ptt, u32 port, u32 lane,
5414b24e2bSVaishali Kulkarni 				    u32 addr, u32 cmd, u8 *buf)
5514b24e2bSVaishali Kulkarni {
5614b24e2bSVaishali Kulkarni 	return ecore_mcp_phy_read(p_hwfn->p_dev, cmd,
5714b24e2bSVaishali Kulkarni 			addr | (lane << 16) | (1<<29) | (port << 30), buf, 8);
5814b24e2bSVaishali Kulkarni }
5914b24e2bSVaishali Kulkarni 
ecore_phy_write(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 lane,u32 addr,u32 data_lo,u32 data_hi,u32 cmd)6014b24e2bSVaishali Kulkarni enum _ecore_status_t ecore_phy_write(struct ecore_hwfn *p_hwfn,
6114b24e2bSVaishali Kulkarni 				     struct ecore_ptt *p_ptt, u32 port,
6214b24e2bSVaishali Kulkarni 				     u32 lane, u32 addr, u32 data_lo,
6314b24e2bSVaishali Kulkarni 				     u32 data_hi, u32 cmd)
6414b24e2bSVaishali Kulkarni {
6514b24e2bSVaishali Kulkarni 	u8 buf64[8] = {0};
6614b24e2bSVaishali Kulkarni 
6714b24e2bSVaishali Kulkarni 	OSAL_MEMCPY(buf64, &data_lo, 4);
6814b24e2bSVaishali Kulkarni 	OSAL_MEMCPY(buf64 + 4, &data_hi, 4);
6914b24e2bSVaishali Kulkarni 
7014b24e2bSVaishali Kulkarni 	return ecore_mcp_phy_write(p_hwfn->p_dev, cmd,
7114b24e2bSVaishali Kulkarni 			addr | (lane << 16) | (1<<29) | (port << 30),
7214b24e2bSVaishali Kulkarni 				 buf64, 8);
7314b24e2bSVaishali Kulkarni }
7414b24e2bSVaishali Kulkarni 
7514b24e2bSVaishali Kulkarni /* phy core write */
ecore_phy_core_write(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 addr,u32 data_lo,u32 data_hi,char * p_phy_result_buf)7614b24e2bSVaishali Kulkarni int ecore_phy_core_write(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
7714b24e2bSVaishali Kulkarni 			  u32 port, u32 addr, u32 data_lo, u32 data_hi,
7814b24e2bSVaishali Kulkarni 			  char *p_phy_result_buf)
7914b24e2bSVaishali Kulkarni {
8014b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc = ECORE_INVAL;
8114b24e2bSVaishali Kulkarni 
8214b24e2bSVaishali Kulkarni 	if (port > 3) {
8314b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
8414b24e2bSVaishali Kulkarni 			     "ERROR! Port must be in range of 0..3\n");
8514b24e2bSVaishali Kulkarni 		return rc;
8614b24e2bSVaishali Kulkarni 	}
8714b24e2bSVaishali Kulkarni 
8814b24e2bSVaishali Kulkarni 	/* write to address */
8914b24e2bSVaishali Kulkarni 	rc = ecore_phy_write(p_hwfn, p_ptt, port, 0 /* lane */, addr, data_lo,
9014b24e2bSVaishali Kulkarni 			     data_hi, ECORE_PHY_CORE_WRITE);
9114b24e2bSVaishali Kulkarni 	if (rc == ECORE_SUCCESS)
9214b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf, "0\n");
9314b24e2bSVaishali Kulkarni 	else
9414b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
9514b24e2bSVaishali Kulkarni 			     "Failed placing phy_core command\n");
9614b24e2bSVaishali Kulkarni 
9714b24e2bSVaishali Kulkarni 	return rc;
9814b24e2bSVaishali Kulkarni }
9914b24e2bSVaishali Kulkarni 
10014b24e2bSVaishali Kulkarni /* phy core read */
ecore_phy_core_read(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 addr,char * p_phy_result_buf)10114b24e2bSVaishali Kulkarni int ecore_phy_core_read(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
10214b24e2bSVaishali Kulkarni 			 u32 port, u32 addr, char *p_phy_result_buf)
10314b24e2bSVaishali Kulkarni {
10414b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc = ECORE_INVAL;
10514b24e2bSVaishali Kulkarni 	u8 buf64[8] = {0};
10614b24e2bSVaishali Kulkarni 	u8 data_hi[4];
10714b24e2bSVaishali Kulkarni 	u8 data_lo[4];
10814b24e2bSVaishali Kulkarni 
10914b24e2bSVaishali Kulkarni 	if (port > 3) {
11014b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
11114b24e2bSVaishali Kulkarni 			     "ERROR! Port must be in range of 0..3\n");
11214b24e2bSVaishali Kulkarni 		return rc;
11314b24e2bSVaishali Kulkarni 	}
11414b24e2bSVaishali Kulkarni 
11514b24e2bSVaishali Kulkarni 	/* read from address */
11614b24e2bSVaishali Kulkarni 	rc = ecore_phy_read(p_hwfn, p_ptt, port, 0 /* lane */ , addr,
11714b24e2bSVaishali Kulkarni 			    ECORE_PHY_CORE_READ, buf64);
11814b24e2bSVaishali Kulkarni 	if (rc == ECORE_SUCCESS) {
11914b24e2bSVaishali Kulkarni 		OSAL_MEMCPY(data_lo, buf64, 4);
12014b24e2bSVaishali Kulkarni 		OSAL_MEMCPY(data_hi, (buf64 + 4), 4);
12114b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf, "0x%08x%08x\n",
12214b24e2bSVaishali Kulkarni 			     *(u32 *)data_hi, *(u32 *)data_lo);
12314b24e2bSVaishali Kulkarni 	}
12414b24e2bSVaishali Kulkarni 	else
12514b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf, "Failed placing phy_core command\n");
12614b24e2bSVaishali Kulkarni 
12714b24e2bSVaishali Kulkarni 	return rc;
12814b24e2bSVaishali Kulkarni }
12914b24e2bSVaishali Kulkarni 
13014b24e2bSVaishali Kulkarni /* phy raw write */
ecore_phy_raw_write(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 lane,u32 addr,u32 data_lo,u32 data_hi,char * p_phy_result_buf)13114b24e2bSVaishali Kulkarni int ecore_phy_raw_write(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
13214b24e2bSVaishali Kulkarni 			 u32 port, u32 lane, u32 addr, u32 data_lo,
13314b24e2bSVaishali Kulkarni 			 u32 data_hi, char *p_phy_result_buf)
13414b24e2bSVaishali Kulkarni {
13514b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc = ECORE_INVAL;
13614b24e2bSVaishali Kulkarni 
13714b24e2bSVaishali Kulkarni 	/* check if the enterd port is in the range */
13814b24e2bSVaishali Kulkarni 	if (port > 3) {
13914b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
14014b24e2bSVaishali Kulkarni 			     "Port must be in range of 0..3\n");
14114b24e2bSVaishali Kulkarni 		return rc;
14214b24e2bSVaishali Kulkarni 	}
14314b24e2bSVaishali Kulkarni 
14414b24e2bSVaishali Kulkarni 	/* check if the enterd lane is in the range */
14514b24e2bSVaishali Kulkarni 	if (lane > 6) {
14614b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
14714b24e2bSVaishali Kulkarni 			     "Lane must be in range of 0..6\n");
14814b24e2bSVaishali Kulkarni 		return rc;
14914b24e2bSVaishali Kulkarni 	}
15014b24e2bSVaishali Kulkarni 
15114b24e2bSVaishali Kulkarni 	/* write to address*/
15214b24e2bSVaishali Kulkarni 	rc = ecore_phy_write(p_hwfn,p_ptt, port, lane, addr, data_lo,
15314b24e2bSVaishali Kulkarni 			     data_hi, ECORE_PHY_RAW_WRITE);
15414b24e2bSVaishali Kulkarni 	if (rc == ECORE_SUCCESS)
15514b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf, "0\n");
15614b24e2bSVaishali Kulkarni 	else
15714b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
15814b24e2bSVaishali Kulkarni 			     "Failed placing phy_core command\n");
15914b24e2bSVaishali Kulkarni 
16014b24e2bSVaishali Kulkarni 	return rc;
16114b24e2bSVaishali Kulkarni }
16214b24e2bSVaishali Kulkarni 
16314b24e2bSVaishali Kulkarni /* phy raw read */
ecore_phy_raw_read(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 lane,u32 addr,char * p_phy_result_buf)16414b24e2bSVaishali Kulkarni int ecore_phy_raw_read(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
16514b24e2bSVaishali Kulkarni 			u32 port, u32 lane, u32 addr, char *p_phy_result_buf)
16614b24e2bSVaishali Kulkarni {
16714b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc = ECORE_INVAL;
16814b24e2bSVaishali Kulkarni 	u8 buf64[8] = {0};
16914b24e2bSVaishali Kulkarni 	u8 data_hi[4];
17014b24e2bSVaishali Kulkarni 	u8 data_lo[4];
17114b24e2bSVaishali Kulkarni 
17214b24e2bSVaishali Kulkarni 	/* check if the enterd port is in the range */
17314b24e2bSVaishali Kulkarni 	if (port > 3) {
17414b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
17514b24e2bSVaishali Kulkarni 			     "Port must be in range of 0..3\n");
17614b24e2bSVaishali Kulkarni 		return rc;
17714b24e2bSVaishali Kulkarni 	}
17814b24e2bSVaishali Kulkarni 
17914b24e2bSVaishali Kulkarni 	/* check if the enterd lane is in the range */
18014b24e2bSVaishali Kulkarni 	if (lane > 6) {
18114b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
18214b24e2bSVaishali Kulkarni 			     "Lane must be in range of 0..6\n");
18314b24e2bSVaishali Kulkarni 		return rc;
18414b24e2bSVaishali Kulkarni 	}
18514b24e2bSVaishali Kulkarni 
18614b24e2bSVaishali Kulkarni 	/* read from address */
18714b24e2bSVaishali Kulkarni 	rc = ecore_phy_read(p_hwfn,p_ptt, port, lane, addr, ECORE_PHY_RAW_READ,
18814b24e2bSVaishali Kulkarni 			    buf64);
18914b24e2bSVaishali Kulkarni 	if (rc == ECORE_SUCCESS) {
19014b24e2bSVaishali Kulkarni 		OSAL_MEMCPY(data_lo, buf64, 4);
19114b24e2bSVaishali Kulkarni 		OSAL_MEMCPY(data_hi, (buf64 + 4), 4);
19214b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf, "0x%08x%08x\n",
19314b24e2bSVaishali Kulkarni 			     *(u32 *)data_hi, *(u32 *)data_lo);
19414b24e2bSVaishali Kulkarni 	} else {
19514b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
19614b24e2bSVaishali Kulkarni 			     "Failed placing phy_core command\n");
19714b24e2bSVaishali Kulkarni 	}
19814b24e2bSVaishali Kulkarni 
19914b24e2bSVaishali Kulkarni 	return rc;
20014b24e2bSVaishali Kulkarni }
20114b24e2bSVaishali Kulkarni 
ecore_phy_get_nvm_cfg1_addr(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)20214b24e2bSVaishali Kulkarni static u32 ecore_phy_get_nvm_cfg1_addr(struct ecore_hwfn *p_hwfn,
20314b24e2bSVaishali Kulkarni 				       struct ecore_ptt *p_ptt)
20414b24e2bSVaishali Kulkarni {
20514b24e2bSVaishali Kulkarni 	u32 nvm_cfg_addr, nvm_cfg1_offset;
20614b24e2bSVaishali Kulkarni 
20714b24e2bSVaishali Kulkarni 	nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
20814b24e2bSVaishali Kulkarni 	nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr +
20914b24e2bSVaishali Kulkarni 				   offsetof(struct nvm_cfg,
21014b24e2bSVaishali Kulkarni 					    sections_offset[NVM_CFG_SECTION_NVM_CFG1]));
21114b24e2bSVaishali Kulkarni 	return MCP_REG_SCRATCH + nvm_cfg1_offset;
21214b24e2bSVaishali Kulkarni }
21314b24e2bSVaishali Kulkarni 
21414b24e2bSVaishali Kulkarni /* get phy info */
ecore_phy_info(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,char * p_phy_result_buf)21514b24e2bSVaishali Kulkarni int ecore_phy_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
21614b24e2bSVaishali Kulkarni 		    char *p_phy_result_buf)
21714b24e2bSVaishali Kulkarni {
21814b24e2bSVaishali Kulkarni 	u32 nvm_cfg1_addr = ecore_phy_get_nvm_cfg1_addr(p_hwfn, p_ptt);
21914b24e2bSVaishali Kulkarni 	u32 port_mode, port, max_ports, core_cfg, length = 0;
22014b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc = ECORE_INVAL;
22114b24e2bSVaishali Kulkarni 	u8 buf64[8] = {0};
22214b24e2bSVaishali Kulkarni 	u8 data_hi[4];
22314b24e2bSVaishali Kulkarni 	u8 data_lo[4];
22414b24e2bSVaishali Kulkarni 
22514b24e2bSVaishali Kulkarni 	u8 is_bb = ((ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM) & 0x8070)
22614b24e2bSVaishali Kulkarni 		    != 0x8070);
22714b24e2bSVaishali Kulkarni 
22814b24e2bSVaishali Kulkarni 	if (is_bb)
22914b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length],
23014b24e2bSVaishali Kulkarni 				       "Device: BB ");
23114b24e2bSVaishali Kulkarni 	else
23214b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length],
23314b24e2bSVaishali Kulkarni 				       "Device: AH ");
23414b24e2bSVaishali Kulkarni 
23514b24e2bSVaishali Kulkarni 	core_cfg = ecore_rd(p_hwfn, p_ptt, nvm_cfg1_addr +
23614b24e2bSVaishali Kulkarni 			    offsetof(struct nvm_cfg1, glob.core_cfg));
23714b24e2bSVaishali Kulkarni 	port_mode = (core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
23814b24e2bSVaishali Kulkarni 		NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET;
23914b24e2bSVaishali Kulkarni 	switch (port_mode) {
24014b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
24114b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "1x100G\n");
24214b24e2bSVaishali Kulkarni 		max_ports = 1;
24314b24e2bSVaishali Kulkarni 		break;
24414b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
24514b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "1x40G\n");
24614b24e2bSVaishali Kulkarni 		max_ports = 1;
24714b24e2bSVaishali Kulkarni 		break;
24814b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
24914b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "1x25G\n");
25014b24e2bSVaishali Kulkarni 		max_ports = 1;
25114b24e2bSVaishali Kulkarni 		break;
25214b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
25314b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "2x40G\n");
25414b24e2bSVaishali Kulkarni 		max_ports = 2;
25514b24e2bSVaishali Kulkarni 		break;
25614b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
25714b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "2x50G\n");
25814b24e2bSVaishali Kulkarni 		max_ports = 2;
25914b24e2bSVaishali Kulkarni 		break;
26014b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
26114b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "2x25G\n");
26214b24e2bSVaishali Kulkarni 		max_ports = 2;
26314b24e2bSVaishali Kulkarni 		break;
26414b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
26514b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "2x10G\n");
26614b24e2bSVaishali Kulkarni 		max_ports = 2;
26714b24e2bSVaishali Kulkarni 		break;
26814b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
26914b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "4x10G\n");
27014b24e2bSVaishali Kulkarni 		max_ports = 4;
27114b24e2bSVaishali Kulkarni 		break;
27214b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
27314b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "4x10G\n");
27414b24e2bSVaishali Kulkarni 		max_ports = 4;
27514b24e2bSVaishali Kulkarni 		break;
27614b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
27714b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "4x20G\n");
27814b24e2bSVaishali Kulkarni 		max_ports = 4;
27914b24e2bSVaishali Kulkarni 		break;
28014b24e2bSVaishali Kulkarni 	case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
28114b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length], "4x25G\n");
28214b24e2bSVaishali Kulkarni 		max_ports = 4;
28314b24e2bSVaishali Kulkarni 		break;
28414b24e2bSVaishali Kulkarni 	default:
28514b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length],
28614b24e2bSVaishali Kulkarni 				      "Wrong port mode\n");
28714b24e2bSVaishali Kulkarni 		return rc;
28814b24e2bSVaishali Kulkarni 	}
28914b24e2bSVaishali Kulkarni 
29014b24e2bSVaishali Kulkarni 	if (is_bb) {
29114b24e2bSVaishali Kulkarni 		for (port = 0; port < max_ports; port++) {
29214b24e2bSVaishali Kulkarni 			rc = ecore_phy_read(p_hwfn, p_ptt, port, 0, SERDESID,
29314b24e2bSVaishali Kulkarni 					    DRV_MSG_CODE_PHY_RAW_READ, buf64);
29414b24e2bSVaishali Kulkarni 			if (rc == ECORE_SUCCESS) {
29514b24e2bSVaishali Kulkarni 				length += OSAL_SPRINTF(
29614b24e2bSVaishali Kulkarni 					&p_phy_result_buf[length],
29714b24e2bSVaishali Kulkarni 					"Port %d is in ", port);
29814b24e2bSVaishali Kulkarni 				OSAL_MEMCPY(data_lo, buf64, 4);
29914b24e2bSVaishali Kulkarni 				OSAL_MEMCPY(data_hi, (buf64 + 4), 4);
30014b24e2bSVaishali Kulkarni 				if ((data_lo[0] & 0x3f) == 0x14)
30114b24e2bSVaishali Kulkarni 					length += OSAL_SPRINTF(
30214b24e2bSVaishali Kulkarni 						&p_phy_result_buf[length],
30314b24e2bSVaishali Kulkarni 						"Falcon\n");
30414b24e2bSVaishali Kulkarni 				else
30514b24e2bSVaishali Kulkarni 					length += OSAL_SPRINTF(
30614b24e2bSVaishali Kulkarni 						&p_phy_result_buf[length],
30714b24e2bSVaishali Kulkarni 						"Eagle\n");
30814b24e2bSVaishali Kulkarni 			}
30914b24e2bSVaishali Kulkarni 		}
31014b24e2bSVaishali Kulkarni 	} else {
31114b24e2bSVaishali Kulkarni 		/* @@@TMP until ecore_phy_read() on AH is supported */
31214b24e2bSVaishali Kulkarni 		for (port = 0; port < max_ports; port++)
31314b24e2bSVaishali Kulkarni 			length += OSAL_SPRINTF(&p_phy_result_buf[length],
31414b24e2bSVaishali Kulkarni 					       "Port %d is in MPS25\n", port);
31514b24e2bSVaishali Kulkarni 		rc = ECORE_SUCCESS;
31614b24e2bSVaishali Kulkarni 	}
31714b24e2bSVaishali Kulkarni 
31814b24e2bSVaishali Kulkarni 	return rc;
31914b24e2bSVaishali Kulkarni }
32014b24e2bSVaishali Kulkarni 
32114b24e2bSVaishali Kulkarni struct tsc_stat {
32214b24e2bSVaishali Kulkarni 	u32 reg;
32314b24e2bSVaishali Kulkarni 	char *name;
32414b24e2bSVaishali Kulkarni 	char *desc;
32514b24e2bSVaishali Kulkarni };
32614b24e2bSVaishali Kulkarni 
32714b24e2bSVaishali Kulkarni static struct tsc_stat ah_stat_regs[] = {
32814b24e2bSVaishali Kulkarni 	{0x000100, "ETHERSTATSOCTETS               ", "total, good and bad"},
32914b24e2bSVaishali Kulkarni /*	{0x000104, "ETHERSTATSOCTETS_H             ", "total, good and bad"},*/
33014b24e2bSVaishali Kulkarni 	{0x000108, "OCTETSOK                       ", "total, good"},
33114b24e2bSVaishali Kulkarni /*	{0x00010c, "OCTETSOK_H                     ", "total, good"}, */
33214b24e2bSVaishali Kulkarni 	{0x000110, "AALIGNMENTERRORS               ", "Wrong SFD detected"},
33314b24e2bSVaishali Kulkarni /*	{0x000114, "AALIGNMENTERRORS_H             ", "Wrong SFD detected"}, */
33414b24e2bSVaishali Kulkarni 	{0x000118, "APAUSEMACCTRLFRAMES            ", "Good Pause frames received"},
33514b24e2bSVaishali Kulkarni /*	{0x00011c, "APAUSEMACCTRLFRAMES_H          ", "Good Pause frames received"}, */
33614b24e2bSVaishali Kulkarni 	{0x000120, "FRAMESOK                       ", "Good frames received"},
33714b24e2bSVaishali Kulkarni /*	{0x000124, "FRAMESOK_H                     ", "Good frames received"}, */
33814b24e2bSVaishali Kulkarni 	{0x000128, "CRCERRORS                      ", "wrong CRC and good length received"},
33914b24e2bSVaishali Kulkarni /*	{0x00012c, "CRCERRORS_H                    ", "wrong CRC and good length received"}, */
34014b24e2bSVaishali Kulkarni 	{0x000130, "VLANOK                         ", "Good Frames with VLAN tag received"},
34114b24e2bSVaishali Kulkarni /*	{0x000134, "VLANOK_H                       ", "Good Frames with VLAN tag received"}, */
34214b24e2bSVaishali Kulkarni 	{0x000138, "IFINERRORS                     ", "Errored frames received"},
34314b24e2bSVaishali Kulkarni /*	{0x00013c, "IFINERRORS_H                   ", "Errored frames received"}, */
34414b24e2bSVaishali Kulkarni 	{0x000140, "IFINUCASTPKTS                  ", "Good Unicast received"},
34514b24e2bSVaishali Kulkarni /*	{0x000144, "IFINUCASTPKTS_H                ", "Good Unicast received"}, */
34614b24e2bSVaishali Kulkarni 	{0x000148, "IFINMCASTPKTS                  ", "Good Multicast received"},
34714b24e2bSVaishali Kulkarni /*	{0x00014c, "IFINMCASTPKTS_H                ", "Good Multicast received"}, */
34814b24e2bSVaishali Kulkarni 	{0x000150, "IFINBCASTPKTS                  ", "Good Broadcast received"},
34914b24e2bSVaishali Kulkarni /*	{0x000154, "IFINBCASTPKTS_H                ", "Good Broadcast received"}, */
35014b24e2bSVaishali Kulkarni 	{0x000158, "ETHERSTATSDROPEVENTS           ", "Dropped frames"},
35114b24e2bSVaishali Kulkarni /*	{0x00015c, "ETHERSTATSDROPEVENTS_H         ", "Dropped frames"}, */
35214b24e2bSVaishali Kulkarni 	{0x000160, "ETHERSTATSPKTS                 ", "Frames received, good and bad"},
35314b24e2bSVaishali Kulkarni /*	{0x000164, "ETHERSTATSPKTS_H               ", "Frames received, good and bad"}, */
35414b24e2bSVaishali Kulkarni 	{0x000168, "ETHERSTATSUNDERSIZEPKTS        ", "Frames received less 64 with good crc"},
35514b24e2bSVaishali Kulkarni /*	{0x00016c, "ETHERSTATSUNDERSIZEPKTS_H      ", "Frames received less 64 with good crc"}, */
35614b24e2bSVaishali Kulkarni 	{0x000170, "ETHERSTATSPKTS64               ", "Frames of 64 octets received"},
35714b24e2bSVaishali Kulkarni /*	{0x000174, "ETHERSTATSPKTS64_H             ", "Frames of 64 octets received"}, */
35814b24e2bSVaishali Kulkarni 	{0x000178, "ETHERSTATSPKTS65TO127          ", "Frames of 65 to 127 octets received"},
35914b24e2bSVaishali Kulkarni /*       {0x00017c, "ETHERSTATSPKTS65TO127_H        ", "Frames of 65 to 127 octets received"}, */
36014b24e2bSVaishali Kulkarni 	{0x000180, "ETHERSTATSPKTS128TO255         ", "Frames of 128 to 255 octets received"},
36114b24e2bSVaishali Kulkarni /*	{0x000184, "ETHERSTATSPKTS128TO255_H       ", "Frames of 128 to 255 octets received"}, */
36214b24e2bSVaishali Kulkarni 	{0x000188, "ETHERSTATSPKTS256TO511         ", "Frames of 256 to 511 octets received"},
36314b24e2bSVaishali Kulkarni /*	{0x00018c, "ETHERSTATSPKTS256TO511_H       ", "Frames of 256 to 511 octets received"},*/
36414b24e2bSVaishali Kulkarni 	{0x000190, "ETHERSTATSPKTS512TO1023        ", "Frames of 512 to 1023 octets received"},
36514b24e2bSVaishali Kulkarni /*	{0x000194, "ETHERSTATSPKTS512TO1023_H      ", "Frames of 512 to 1023 octets received"},*/
36614b24e2bSVaishali Kulkarni 	{0x000198, "ETHERSTATSPKTS1024TO1518       ", "Frames of 1024 to 1518 octets received"},
36714b24e2bSVaishali Kulkarni /*	{0x00019c, "ETHERSTATSPKTS1024TO1518_H     ", "Frames of 1024 to 1518 octets received"},*/
36814b24e2bSVaishali Kulkarni 	{0x0001a0, "ETHERSTATSPKTS1519TOMAX        ", "Frames of 1519 to FRM_LENGTH octets received"},
36914b24e2bSVaishali Kulkarni /*	{0x0001a4, "ETHERSTATSPKTS1519TOMAX_H      ", "Frames of 1519 to FRM_LENGTH octets received"},*/
37014b24e2bSVaishali Kulkarni 	{0x0001a8, "ETHERSTATSPKTSOVERSIZE         ", "Frames greater FRM_LENGTH and good CRC received"},
37114b24e2bSVaishali Kulkarni /*	{0x0001ac, "ETHERSTATSPKTSOVERSIZE_H       ", "Frames greater FRM_LENGTH and good CRC received"},*/
37214b24e2bSVaishali Kulkarni 	{0x0001b0, "ETHERSTATSJABBERS              ", "Frames greater FRM_LENGTH and bad CRC received"},
37314b24e2bSVaishali Kulkarni /*	{0x0001b4, "ETHERSTATSJABBERS_H            ", "Frames greater FRM_LENGTH and bad CRC received"},*/
37414b24e2bSVaishali Kulkarni 	{0x0001b8, "ETHERSTATSFRAGMENTS            ", "Frames less 64 and bad CRC received"},
37514b24e2bSVaishali Kulkarni /*	{0x0001bc, "ETHERSTATSFRAGMENTS_H          ", "Frames less 64 and bad CRC received"},*/
37614b24e2bSVaishali Kulkarni 	{0x0001c0, "AMACCONTROLFRAMES              ", "Good frames received of type 0x8808 but not Pause"},
37714b24e2bSVaishali Kulkarni /*	{0x0001c4, "AMACCONTROLFRAMES_H            ", "Good frames received of type 0x8808 but not Pause"},*/
37814b24e2bSVaishali Kulkarni 	{0x0001c8, "AFRAMETOOLONG                  ", "Good and bad frames exceeding FRM_LENGTH received"},
37914b24e2bSVaishali Kulkarni /*	{0x0001cc, "AFRAMETOOLONG_H                ", "Good and bad frames exceeding FRM_LENGTH received"},*/
38014b24e2bSVaishali Kulkarni 	{0x0001d0, "AINRANGELENGTHERROR            ", "Good frames with invalid length field (not supported)"},
38114b24e2bSVaishali Kulkarni /*	{0x0001d4, "AINRANGELENGTHERROR_H          ", "Good frames with invalid length field (not supported)"},*/
38214b24e2bSVaishali Kulkarni 	{0x000200, "TXETHERSTATSOCTETS             ", "total, good and bad"},
38314b24e2bSVaishali Kulkarni /*	{0x000204, "TXETHERSTATSOCTETS_H           ", "total, good and bad"},*/
38414b24e2bSVaishali Kulkarni 	{0x000208, "TXOCTETSOK                     ", "total, good"},
38514b24e2bSVaishali Kulkarni /*	{0x00020c, "TXOCTETSOK_H                   ", "total, good"},*/
38614b24e2bSVaishali Kulkarni 	{0x000218, "TXAPAUSEMACCTRLFRAMES          ", "Good Pause frames transmitted"},
38714b24e2bSVaishali Kulkarni /*	{0x00021c, "TXAPAUSEMACCTRLFRAMES_H        ", "Good Pause frames transmitted"},*/
38814b24e2bSVaishali Kulkarni 	{0x000220, "TXFRAMESOK                     ", "Good frames transmitted"},
38914b24e2bSVaishali Kulkarni /*	{0x000224, "TXFRAMESOK_H                   ", "Good frames transmitted"},*/
39014b24e2bSVaishali Kulkarni 	{0x000228, "TXCRCERRORS                    ", "wrong CRC transmitted"},
39114b24e2bSVaishali Kulkarni /*	{0x00022c, "TXCRCERRORS_H                  ", "wrong CRC transmitted"},*/
39214b24e2bSVaishali Kulkarni 	{0x000230, "TXVLANOK                       ", "Good Frames with VLAN tag transmitted"},
39314b24e2bSVaishali Kulkarni /*	{0x000234, "TXVLANOK_H                     ", "Good Frames with VLAN tag transmitted"},*/
39414b24e2bSVaishali Kulkarni 	{0x000238, "IFOUTERRORS                    ", "Errored frames transmitted"},
39514b24e2bSVaishali Kulkarni /*	{0x00023c, "IFOUTERRORS_H                  ", "Errored frames transmitted"},*/
39614b24e2bSVaishali Kulkarni 	{0x000240, "IFOUTUCASTPKTS                 ", "Good Unicast transmitted"},
39714b24e2bSVaishali Kulkarni /*	{0x000244, "IFOUTUCASTPKTS_H               ", "Good Unicast transmitted"},*/
39814b24e2bSVaishali Kulkarni 	{0x000248, "IFOUTMCASTPKTS                 ", "Good Multicast transmitted"},
39914b24e2bSVaishali Kulkarni /*	{0x00024c, "IFOUTMCASTPKTS_H               ", "Good Multicast transmitted"},*/
40014b24e2bSVaishali Kulkarni 	{0x000250, "IFOUTBCASTPKTS                 ", "Good Broadcast transmitted"},
40114b24e2bSVaishali Kulkarni /*	{0x000254, "IFOUTBCASTPKTS_H               ", "Good Broadcast transmitted"},*/
40214b24e2bSVaishali Kulkarni 	{0x000258, "TXETHERSTATSDROPEVENTS         ", "Dropped frames (unused, reserved)"},
40314b24e2bSVaishali Kulkarni /*	{0x00025c, "TXETHERSTATSDROPEVENTS_H       ", "Dropped frames (unused, reserved)"},*/
40414b24e2bSVaishali Kulkarni 	{0x000260, "TXETHERSTATSPKTS               ", "Frames transmitted, good and bad"},
40514b24e2bSVaishali Kulkarni /*	{0x000264, "TXETHERSTATSPKTS_H             ", "Frames transmitted, good and bad"},*/
40614b24e2bSVaishali Kulkarni 	{0x000268, "TXETHERSTATSUNDERSIZEPKTS      ", "Frames transmitted less 64"},
40714b24e2bSVaishali Kulkarni /*	{0x00026c, "TXETHERSTATSUNDERSIZEPKTS_H    ", "Frames transmitted less 64"},*/
40814b24e2bSVaishali Kulkarni 	{0x000270, "TXETHERSTATSPKTS64             ", "Frames of 64 octets transmitted"},
40914b24e2bSVaishali Kulkarni /*	{0x000274, "TXETHERSTATSPKTS64_H           ", "Frames of 64 octets transmitted"},*/
41014b24e2bSVaishali Kulkarni 	{0x000278, "TXETHERSTATSPKTS65TO127        ", "Frames of 65 to 127 octets transmitted"},
41114b24e2bSVaishali Kulkarni /*	{0x00027c, "TXETHERSTATSPKTS65TO127_H      ", "Frames of 65 to 127 octets transmitted"},*/
41214b24e2bSVaishali Kulkarni 	{0x000280, "TXETHERSTATSPKTS128TO255       ", "Frames of 128 to 255 octets transmitted"},
41314b24e2bSVaishali Kulkarni /*	{0x000284, "TXETHERSTATSPKTS128TO255_H     ", "Frames of 128 to 255 octets transmitted"},*/
41414b24e2bSVaishali Kulkarni 	{0x000288, "TXETHERSTATSPKTS256TO511       ", "Frames of 256 to 511 octets transmitted"},
41514b24e2bSVaishali Kulkarni /*	{0x00028c, "TXETHERSTATSPKTS256TO511_H     ", "Frames of 256 to 511 octets transmitted"},*/
41614b24e2bSVaishali Kulkarni 	{0x000290, "TXETHERSTATSPKTS512TO1023      ", "Frames of 512 to 1023 octets transmitted"},
41714b24e2bSVaishali Kulkarni /*	{0x000294, "TXETHERSTATSPKTS512TO1023_H    ", "Frames of 512 to 1023 octets transmitted"},*/
41814b24e2bSVaishali Kulkarni 	{0x000298, "TXETHERSTATSPKTS1024TO1518     ", "Frames of 1024 to 1518 octets transmitted"},
41914b24e2bSVaishali Kulkarni /*	{0x00029c, "TXETHERSTATSPKTS1024TO1518_H   ", "Frames of 1024 to 1518 octets transmitted"},*/
42014b24e2bSVaishali Kulkarni 	{0x0002a0, "TXETHERSTATSPKTS1519TOTX_MTU   ", "Frames of 1519 to FRM_LENGTH.TX_MTU octets transmitted"},
42114b24e2bSVaishali Kulkarni /*	{0x0002a4, "TXETHERSTATSPKTS1519TOTX_MTU_H ", "Frames of 1519 to FRM_LENGTH.TX_MTU octets transmitted"},*/
42214b24e2bSVaishali Kulkarni 	{0x0002c0, "TXAMACCONTROLFRAMES            ", "Good frames transmitted of type 0x8808 but not Pause"},
42314b24e2bSVaishali Kulkarni /*	{0x0002c4, "TXAMACCONTROLFRAMES_H          ", "Good frames transmitted of type 0x8808 but not Pause"},*/
42414b24e2bSVaishali Kulkarni 	{0x000380, "ACBFCPAUSEFRAMESRECEIVED_0     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
42514b24e2bSVaishali Kulkarni /*	{0x000384, "ACBFCPAUSEFRAMESRECEIVED_0_H   ", "Upper 32bit of 64bit counter."},*/
42614b24e2bSVaishali Kulkarni 	{0x000388, "ACBFCPAUSEFRAMESRECEIVED_1     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
42714b24e2bSVaishali Kulkarni /*	{0x00038c, "ACBFCPAUSEFRAMESRECEIVED_1_H   ", "Upper 32bit of 64bit counter."},*/
42814b24e2bSVaishali Kulkarni 	{0x000390, "ACBFCPAUSEFRAMESRECEIVED_2     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
42914b24e2bSVaishali Kulkarni /*	{0x000394, "ACBFCPAUSEFRAMESRECEIVED_2_H   ", "Upper 32bit of 64bit counter."},*/
43014b24e2bSVaishali Kulkarni 	{0x000398, "ACBFCPAUSEFRAMESRECEIVED_3     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
43114b24e2bSVaishali Kulkarni /*	{0x00039c, "ACBFCPAUSEFRAMESRECEIVED_3_H   ", "Upper 32bit of 64bit counter."},*/
43214b24e2bSVaishali Kulkarni 	{0x0003a0, "ACBFCPAUSEFRAMESRECEIVED_4     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
43314b24e2bSVaishali Kulkarni /*	{0x0003a4, "ACBFCPAUSEFRAMESRECEIVED_4_H   ", "Upper 32bit of 64bit counter."},*/
43414b24e2bSVaishali Kulkarni 	{0x0003a8, "ACBFCPAUSEFRAMESRECEIVED_5     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
43514b24e2bSVaishali Kulkarni /*	{0x0003ac, "ACBFCPAUSEFRAMESRECEIVED_5_H   ", "Upper 32bit of 64bit counter."},*/
43614b24e2bSVaishali Kulkarni 	{0x0003b0, "ACBFCPAUSEFRAMESRECEIVED_6     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
43714b24e2bSVaishali Kulkarni /*	{0x0003b4, "ACBFCPAUSEFRAMESRECEIVED_6_H   ", "Upper 32bit of 64bit counter."},*/
43814b24e2bSVaishali Kulkarni 	{0x0003b8, "ACBFCPAUSEFRAMESRECEIVED_7     ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class."},
43914b24e2bSVaishali Kulkarni /*	{0x0003bc, "ACBFCPAUSEFRAMESRECEIVED_7_H   ", "Upper 32bit of 64bit counter."},*/
44014b24e2bSVaishali Kulkarni 	{0x0003c0, "ACBFCPAUSEFRAMESTRANSMITTED_0  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
44114b24e2bSVaishali Kulkarni /*	{0x0003c4, "ACBFCPAUSEFRAMESTRANSMITTED_0_H", "Upper 32bit of 64bit counter."},*/
44214b24e2bSVaishali Kulkarni 	{0x0003c8, "ACBFCPAUSEFRAMESTRANSMITTED_1  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
44314b24e2bSVaishali Kulkarni /*	{0x0003cc, "ACBFCPAUSEFRAMESTRANSMITTED_1_H", "Upper 32bit of 64bit counter."},*/
44414b24e2bSVaishali Kulkarni 	{0x0003d0, "ACBFCPAUSEFRAMESTRANSMITTED_2  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
44514b24e2bSVaishali Kulkarni /*	{0x0003d4, "ACBFCPAUSEFRAMESTRANSMITTED_2_H", "Upper 32bit of 64bit counter."},*/
44614b24e2bSVaishali Kulkarni 	{0x0003d8, "ACBFCPAUSEFRAMESTRANSMITTED_3  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
44714b24e2bSVaishali Kulkarni /*	{0x0003dc, "ACBFCPAUSEFRAMESTRANSMITTED_3_H", "Upper 32bit of 64bit counter."},*/
44814b24e2bSVaishali Kulkarni 	{0x0003e0, "ACBFCPAUSEFRAMESTRANSMITTED_4  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
44914b24e2bSVaishali Kulkarni /*	{0x0003e4, "ACBFCPAUSEFRAMESTRANSMITTED_4_H", "Upper 32bit of 64bit counter."},*/
45014b24e2bSVaishali Kulkarni 	{0x0003e8, "ACBFCPAUSEFRAMESTRANSMITTED_5  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
45114b24e2bSVaishali Kulkarni /*	{0x0003ec, "ACBFCPAUSEFRAMESTRANSMITTED_5_H", "Upper 32bit of 64bit counter."},*/
45214b24e2bSVaishali Kulkarni 	{0x0003f0, "ACBFCPAUSEFRAMESTRANSMITTED_6  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
45314b24e2bSVaishali Kulkarni /*	{0x0003f4, "ACBFCPAUSEFRAMESTRANSMITTED_6_H", "Upper 32bit of 64bit counter."},*/
45414b24e2bSVaishali Kulkarni 	{0x0003f8, "ACBFCPAUSEFRAMESTRANSMITTED_7  ", "Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class."},
45514b24e2bSVaishali Kulkarni /*	{0x0003fc, "ACBFCPAUSEFRAMESTRANSMITTED_7_H", "Upper 32bit of 64bit counter."}*/
45614b24e2bSVaishali Kulkarni };
45714b24e2bSVaishali Kulkarni static struct tsc_stat bb_stat_regs[] = {
45814b24e2bSVaishali Kulkarni     {0x00000000, "GRX64","RX 64-byte frame counter" },
45914b24e2bSVaishali Kulkarni     {0x00000001, "GRX127","RX 65 to 127 byte frame counter" },
46014b24e2bSVaishali Kulkarni     {0x00000002, "GRX255","RX 128 to 255 byte frame counter" },
46114b24e2bSVaishali Kulkarni     {0x00000003, "GRX511","RX 256 to 511 byte frame counter" },
46214b24e2bSVaishali Kulkarni     {0x00000004, "GRX1023","RX 512 to 1023 byte frame counter" },
46314b24e2bSVaishali Kulkarni     {0x00000005, "GRX1518","RX 1024 to 1518 byte frame counter" },
46414b24e2bSVaishali Kulkarni     {0x00000006, "GRX1522","RX 1519 to 1522 byte VLAN-tagged frame counter" },
46514b24e2bSVaishali Kulkarni     {0x00000007, "GRX2047","RX 1519 to 2047 byte frame counter" },
46614b24e2bSVaishali Kulkarni     {0x00000008, "GRX4095","RX 2048 to 4095 byte frame counter" },
46714b24e2bSVaishali Kulkarni     {0x00000009, "GRX9216","RX 4096 to 9216 byte frame counter" },
46814b24e2bSVaishali Kulkarni     {0x0000000a, "GRX16383","RX 9217 to 16383 byte frame counter" },
46914b24e2bSVaishali Kulkarni     {0x0000000b, "GRXPKT","RX frame counter (all packets)" },
47014b24e2bSVaishali Kulkarni     {0x0000000c, "GRXUCA","RX UC frame counter" },
47114b24e2bSVaishali Kulkarni     {0x0000000d, "GRXMCA","RX MC frame counter" },
47214b24e2bSVaishali Kulkarni     {0x0000000e, "GRXBCA","RX BC frame counter" },
47314b24e2bSVaishali Kulkarni     {0x0000000f, "GRXFCS","RX FCS error frame counter" },
47414b24e2bSVaishali Kulkarni     {0x00000010, "GRXCF","RX control frame counter" },
47514b24e2bSVaishali Kulkarni     {0x00000011, "GRXPF","RX pause frame counter" },
47614b24e2bSVaishali Kulkarni     {0x00000012, "GRXPP","RX PFC frame counter" },
47714b24e2bSVaishali Kulkarni     {0x00000013, "GRXUO","RX unsupported opcode frame counter" },
47814b24e2bSVaishali Kulkarni     {0x00000014, "GRXUDA","RX unsupported DA for pause/PFC frame counter" },
47914b24e2bSVaishali Kulkarni     {0x00000015, "GRXWSA","RX incorrect SA counter" },
48014b24e2bSVaishali Kulkarni     {0x00000016, "GRXALN","RX alignment error counter" },
48114b24e2bSVaishali Kulkarni     {0x00000017, "GRXFLR","RX out-of-range length frame counter" },
48214b24e2bSVaishali Kulkarni     {0x00000018, "GRXFRERR","RX code error frame counter" },
48314b24e2bSVaishali Kulkarni     {0x00000019, "GRXFCR","RX false carrier counter" },
48414b24e2bSVaishali Kulkarni     {0x0000001a, "GRXOVR","RX oversized frame counter" },
48514b24e2bSVaishali Kulkarni     {0x0000001b, "GRXJBR","RX jabber frame counter" },
48614b24e2bSVaishali Kulkarni     {0x0000001c, "GRXMTUE","RX MTU check error frame counter" },
48714b24e2bSVaishali Kulkarni     {0x0000001d, "GRXMCRC",
48814b24e2bSVaishali Kulkarni 	    "RX packet with 4-Byte CRC matching MACSEC_PROG_TX_CRC." },
48914b24e2bSVaishali Kulkarni     {0x0000001e, "GRXPRM","RX promiscuous packet counter" },
49014b24e2bSVaishali Kulkarni     {0x0000001f, "GRXVLN","RX single and double VLAN tagged frame counter" },
49114b24e2bSVaishali Kulkarni     {0x00000020, "GRXDVLN","RX double VLANG tagged frame counter" },
49214b24e2bSVaishali Kulkarni     {0x00000021, "GRXTRFU","RX truncated frame (due to RX FIFO full) counter" },
49314b24e2bSVaishali Kulkarni     {0x00000022, "GRXPOK","RX good frame (good CRC, not oversized, no ERROR)" },
49414b24e2bSVaishali Kulkarni     {0x00000023, "GRXPFCOFF0",
49514b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority0" },
49614b24e2bSVaishali Kulkarni     {0x00000024, "GRXPFCOFF1",
49714b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority1" },
49814b24e2bSVaishali Kulkarni     {0x00000025, "GRXPFCOFF2",
49914b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority2" },
50014b24e2bSVaishali Kulkarni     {0x00000026, "GRXPFCOFF3",
50114b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority3" },
50214b24e2bSVaishali Kulkarni     {0x00000027, "GRXPFCOFF4",
50314b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority4" },
50414b24e2bSVaishali Kulkarni     {0x00000028, "GRXPFCOFF5",
50514b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority5" },
50614b24e2bSVaishali Kulkarni     {0x00000029, "GRXPFCOFF6",
50714b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority6" },
50814b24e2bSVaishali Kulkarni     {0x0000002a, "GRXPFCOFF7",
50914b24e2bSVaishali Kulkarni 	    "RX PFC frame transition XON to XOFF for Priority7" },
51014b24e2bSVaishali Kulkarni     {0x0000002b, "GRXPFCP0","RX PFC frame with enable bit set for Priority0" },
51114b24e2bSVaishali Kulkarni     {0x0000002c, "GRXPFCP1","RX PFC frame with enable bit set for Priority1" },
51214b24e2bSVaishali Kulkarni     {0x0000002d, "GRXPFCP2","RX PFC frame with enable bit set for Priority2" },
51314b24e2bSVaishali Kulkarni     {0x0000002e, "GRXPFCP3","RX PFC frame with enable bit set for Priority3" },
51414b24e2bSVaishali Kulkarni     {0x0000002f, "GRXPFCP4","RX PFC frame with enable bit set for Priority4" },
51514b24e2bSVaishali Kulkarni     {0x00000030, "GRXPFCP5","RX PFC frame with enable bit set for Priority5" },
51614b24e2bSVaishali Kulkarni     {0x00000031, "GRXPFCP6","RX PFC frame with enable bit set for Priority6" },
51714b24e2bSVaishali Kulkarni     {0x00000032, "GRXPFCP7","RX PFC frame with enable bit set for Priority7" },
51814b24e2bSVaishali Kulkarni     {0x00000033, "GRXSCHCRC","RX frame with SCH CRC error. For LH mode only" },
51914b24e2bSVaishali Kulkarni     {0x00000034, "GRXUND","RX undersized frame counter" },
52014b24e2bSVaishali Kulkarni     {0x00000035, "GRXFRG","RX fragment counter" },
52114b24e2bSVaishali Kulkarni     {0x00000036, "RXEEELPI", "RX EEE LPI counter"},
52214b24e2bSVaishali Kulkarni     {0x00000037, "RXEEELPIDU", "RX EEE LPI duration counter"},
52314b24e2bSVaishali Kulkarni     {0x00000038, "RXLLFCPHY", "RX LLFC PHY COUNTER"},
52414b24e2bSVaishali Kulkarni     {0x00000039, "RXLLFCLOG", "RX LLFC LOG COUNTER"},
52514b24e2bSVaishali Kulkarni     {0x0000003a, "RXLLFCCRC", "RX LLFC CRC COUNTER"},
52614b24e2bSVaishali Kulkarni     {0x0000003b, "RXHCFC", "RX HCFC COUNTER"},
52714b24e2bSVaishali Kulkarni     {0x0000003c, "RXHCFCCRC", "RX HCFC CRC COUNTER"},
52814b24e2bSVaishali Kulkarni     {0x0000003d, "GRXBYT", "RX byte counter"},
52914b24e2bSVaishali Kulkarni     {0x0000003e, "GRXRBYT", "RX runt byte counter"},
53014b24e2bSVaishali Kulkarni     {0x0000003f, "GRXRPKT", "RX packet counter"},
53114b24e2bSVaishali Kulkarni     {0x00000040, "GTX64", "TX 64-byte frame counter"},
53214b24e2bSVaishali Kulkarni     {0x00000041, "GTX127", "TX 65 to 127 byte frame counter"},
53314b24e2bSVaishali Kulkarni     {0x00000042, "GTX255", "TX 128 to 255 byte frame counter"},
53414b24e2bSVaishali Kulkarni     {0x00000043, "GTX511", "TX 256 to 511 byte frame counter"},
53514b24e2bSVaishali Kulkarni     {0x00000044, "GTX1023", "TX 512 to 1023 byte frame counter"},
53614b24e2bSVaishali Kulkarni     {0x00000045, "GTX1518", "TX 1024 to 1518 byte frame counter"},
53714b24e2bSVaishali Kulkarni     {0x00000046, "GTX1522", "TX 1519 to 1522 byte VLAN-tagged frame counter"},
53814b24e2bSVaishali Kulkarni     {0x00000047, "GTX2047", "TX 1519 to 2047 byte frame counter"},
53914b24e2bSVaishali Kulkarni     {0x00000048, "GTX4095", "TX 2048 to 4095 byte frame counte"},
54014b24e2bSVaishali Kulkarni     {0x00000049, "GTX9216", "TX 4096 to 9216 byte frame counter"},
54114b24e2bSVaishali Kulkarni     {0x0000004a, "GTX16383", "TX 9217 to 16383 byte frame counter"},
54214b24e2bSVaishali Kulkarni     {0x0000004b, "GTXPOK", "TX good frame counter"},
54314b24e2bSVaishali Kulkarni     {0x0000004c, "GTXPKT", "TX frame counter (all packets"},
54414b24e2bSVaishali Kulkarni     {0x0000004d, "GTXUCA", "TX UC frame counter"},
54514b24e2bSVaishali Kulkarni     {0x0000004e, "GTXMCA", "TX MC frame counter"},
54614b24e2bSVaishali Kulkarni     {0x0000004f, "GTXBCA", "TX BC frame counter"},
54714b24e2bSVaishali Kulkarni     {0x00000050, "GTXPF", "TX pause frame counter"},
54814b24e2bSVaishali Kulkarni     {0x00000051, "GTXPP", "TX PFC frame counter"},
54914b24e2bSVaishali Kulkarni     {0x00000052, "GTXJBR", "TX jabber counter"},
55014b24e2bSVaishali Kulkarni     {0x00000053, "GTXFCS", "TX FCS error counter"},
55114b24e2bSVaishali Kulkarni     {0x00000054, "GTXCF", "TX control frame counter"},
55214b24e2bSVaishali Kulkarni     {0x00000055, "GTXOVR", "TX oversize packet counter"},
55314b24e2bSVaishali Kulkarni     {0x00000056, "GTXDFR", "TX Single Deferral Frame Counter"},
55414b24e2bSVaishali Kulkarni     {0x00000057, "GTXEDF", "TX Multiple Deferral Frame Counter"},
55514b24e2bSVaishali Kulkarni     {0x00000058, "GTXSCL", "TX Single Collision Frame Counter"},
55614b24e2bSVaishali Kulkarni     {0x00000059, "GTXMCL", "TX Multiple Collision Frame Counter"},
55714b24e2bSVaishali Kulkarni     {0x0000005a, "GTXLCL", "TX Late Collision Frame Counter"},
55814b24e2bSVaishali Kulkarni     {0x0000005b, "GTXXCL", "TX Excessive Collision Frame Counter"},
55914b24e2bSVaishali Kulkarni     {0x0000005c, "GTXFRG", "TX fragment counter"},
56014b24e2bSVaishali Kulkarni     {0x0000005d, "GTXERR", "TX error (set by system) frame counter"},
56114b24e2bSVaishali Kulkarni     {0x0000005e, "GTXVLN", "TX VLAN Tag Frame Counter"},
56214b24e2bSVaishali Kulkarni     {0x0000005f, "GTXDVLN", "TX Double VLAN Tag Frame Counter"},
56314b24e2bSVaishali Kulkarni     {0x00000060, "GTXRPKT", "TX RUNT Frame Counter"},
56414b24e2bSVaishali Kulkarni     {0x00000061, "GTXUFL", "TX FIFO Underrun Counter"},
56514b24e2bSVaishali Kulkarni     {0x00000062, "GTXPFCP0", "TX PFC frame with enable bit set for Priority0"},
56614b24e2bSVaishali Kulkarni     {0x00000063, "GTXPFCP1", "TX PFC frame with enable bit set for Priority1"},
56714b24e2bSVaishali Kulkarni     {0x00000064, "GTXPFCP2", "TX PFC frame with enable bit set for Priority2"},
56814b24e2bSVaishali Kulkarni     {0x00000065, "GTXPFCP3", "TX PFC frame with enable bit set for Priority3"},
56914b24e2bSVaishali Kulkarni     {0x00000066, "GTXPFCP4", "TX PFC frame with enable bit set for Priority4"},
57014b24e2bSVaishali Kulkarni     {0x00000067, "GTXPFCP5", "TX PFC frame with enable bit set for Priority5"},
57114b24e2bSVaishali Kulkarni     {0x00000068, "GTXPFCP6", "TX PFC frame with enable bit set for Priority6"},
57214b24e2bSVaishali Kulkarni     {0x00000069, "GTXPFCP7", "TX PFC frame with enable bit set for Priority7"},
57314b24e2bSVaishali Kulkarni     {0x0000006a, "TXEEELPI", "TX EEE LPI Event Counter"},
57414b24e2bSVaishali Kulkarni     {0x0000006b, "TXEEELPIDU", "TX EEE LPI Duration Counter"},
57514b24e2bSVaishali Kulkarni     {0x0000006c, "TXLLFCLOG", "Transmit Logical Type LLFC message counter"},
57614b24e2bSVaishali Kulkarni     {0x0000006d, "TXHCFC", "Transmit Logical Type LLFC message counter"},
57714b24e2bSVaishali Kulkarni     {0x0000006e, "GTXNCL", "Transmit Total Collision Counter"},
57814b24e2bSVaishali Kulkarni     {0x0000006f, "GTXBYT", "TX byte counter"}
57914b24e2bSVaishali Kulkarni };
58014b24e2bSVaishali Kulkarni 
58114b24e2bSVaishali Kulkarni /* get mac status */
ecore_bb_phy_mac_stat(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,char * p_phy_result_buf)58214b24e2bSVaishali Kulkarni static int ecore_bb_phy_mac_stat(struct ecore_hwfn *p_hwfn,
58314b24e2bSVaishali Kulkarni 				 struct ecore_ptt *p_ptt,
58414b24e2bSVaishali Kulkarni 				 u32 port, char *p_phy_result_buf)
58514b24e2bSVaishali Kulkarni {
58614b24e2bSVaishali Kulkarni 	u8 buf64[8] = {0}, data_hi[4], data_lo[4];
58714b24e2bSVaishali Kulkarni 	bool b_false_alarm = false;
58814b24e2bSVaishali Kulkarni 	u32 length, reg_id, addr;
58914b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc = ECORE_INVAL;
59014b24e2bSVaishali Kulkarni 
59114b24e2bSVaishali Kulkarni 	length = OSAL_SPRINTF(p_phy_result_buf,
59214b24e2bSVaishali Kulkarni 			       "MAC stats for port %d (only non-zero)\n", port);
59314b24e2bSVaishali Kulkarni 
59414b24e2bSVaishali Kulkarni 	for (reg_id = 0; reg_id < OSAL_ARRAY_SIZE(bb_stat_regs); reg_id++) {
59514b24e2bSVaishali Kulkarni 		addr = bb_stat_regs[reg_id].reg;
59614b24e2bSVaishali Kulkarni 		rc = ecore_phy_read(p_hwfn, p_ptt, port, 0 /*lane*/, addr,
59714b24e2bSVaishali Kulkarni 				    ECORE_PHY_CORE_READ, buf64);
59814b24e2bSVaishali Kulkarni 
59914b24e2bSVaishali Kulkarni 		OSAL_MEMCPY(data_lo, buf64, 4);
60014b24e2bSVaishali Kulkarni 		OSAL_MEMCPY(data_hi, (buf64 + 4), 4);
60114b24e2bSVaishali Kulkarni 
60214b24e2bSVaishali Kulkarni 		if (rc == ECORE_SUCCESS) {
60314b24e2bSVaishali Kulkarni 			if (*(u32 *)data_lo != 0) {  /* Only non-zero */
60414b24e2bSVaishali Kulkarni 				length += OSAL_SPRINTF(&p_phy_result_buf[length],
60514b24e2bSVaishali Kulkarni 						       "%-10s: 0x%08x (%s)\n",
60614b24e2bSVaishali Kulkarni 						       bb_stat_regs[reg_id].name,
60714b24e2bSVaishali Kulkarni 						       *(u32 *)data_lo,
60814b24e2bSVaishali Kulkarni 						       bb_stat_regs[reg_id].desc);
60914b24e2bSVaishali Kulkarni 				if ((bb_stat_regs[reg_id].reg == 0x0000000f) ||
61014b24e2bSVaishali Kulkarni 				    (bb_stat_regs[reg_id].reg == 0x00000018) ||
61114b24e2bSVaishali Kulkarni 				    (bb_stat_regs[reg_id].reg == 0x00000035))
61214b24e2bSVaishali Kulkarni 					b_false_alarm = true;
61314b24e2bSVaishali Kulkarni 			}
61414b24e2bSVaishali Kulkarni 		} else {
61514b24e2bSVaishali Kulkarni 			OSAL_SPRINTF(p_phy_result_buf, "Failed reading stat 0x%x\n\n",
61614b24e2bSVaishali Kulkarni 				     addr);
61714b24e2bSVaishali Kulkarni 		}
61814b24e2bSVaishali Kulkarni 	}
61914b24e2bSVaishali Kulkarni 
62014b24e2bSVaishali Kulkarni 	if (b_false_alarm)
62114b24e2bSVaishali Kulkarni 		length += OSAL_SPRINTF(&p_phy_result_buf[length],
62214b24e2bSVaishali Kulkarni 				       "Note: GRXFCS/GRXFRERR/GRXFRG may "
62314b24e2bSVaishali Kulkarni 				       "increment when the port shuts down\n");
62414b24e2bSVaishali Kulkarni 
62514b24e2bSVaishali Kulkarni 	return rc;
62614b24e2bSVaishali Kulkarni }
62714b24e2bSVaishali Kulkarni 
62814b24e2bSVaishali Kulkarni /* get mac status */
ecore_ah_e5_phy_mac_stat(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,char * p_phy_result_buf)62914b24e2bSVaishali Kulkarni static int ecore_ah_e5_phy_mac_stat(struct ecore_hwfn *p_hwfn,
63014b24e2bSVaishali Kulkarni 				    struct ecore_ptt *p_ptt, u32 port,
63114b24e2bSVaishali Kulkarni 				    char *p_phy_result_buf)
63214b24e2bSVaishali Kulkarni {
633b68ddc76SJohn Levon 	u32 length, reg_id, addr, data_hi __unused, data_lo;
63414b24e2bSVaishali Kulkarni 
63514b24e2bSVaishali Kulkarni 	length = OSAL_SPRINTF(p_phy_result_buf,
63614b24e2bSVaishali Kulkarni 			       "MAC stats for port %d (only non-zero)\n", port);
63714b24e2bSVaishali Kulkarni 
63814b24e2bSVaishali Kulkarni 	for (reg_id = 0; reg_id < OSAL_ARRAY_SIZE(ah_stat_regs); reg_id++) {
63914b24e2bSVaishali Kulkarni 		addr = ah_stat_regs[reg_id].reg;
64014b24e2bSVaishali Kulkarni 		data_lo = ecore_rd(p_hwfn, p_ptt,
64114b24e2bSVaishali Kulkarni 				   NWM_REG_MAC0_K2_E5 +
64214b24e2bSVaishali Kulkarni 				   NWM_REG_MAC0_SIZE * 4 * port +
64314b24e2bSVaishali Kulkarni 				   addr);
64414b24e2bSVaishali Kulkarni 		data_hi = ecore_rd(p_hwfn, p_ptt,
64514b24e2bSVaishali Kulkarni 				   NWM_REG_MAC0_K2_E5 +
64614b24e2bSVaishali Kulkarni 				   NWM_REG_MAC0_SIZE * 4 * port +
64714b24e2bSVaishali Kulkarni 				   addr + 4);
64814b24e2bSVaishali Kulkarni 
64914b24e2bSVaishali Kulkarni 		if (data_lo) {  /* Only non-zero */
65014b24e2bSVaishali Kulkarni 			length += OSAL_SPRINTF(&p_phy_result_buf[length],
65114b24e2bSVaishali Kulkarni 					       "%-10s: 0x%08x (%s)\n",
65214b24e2bSVaishali Kulkarni 					       ah_stat_regs[reg_id].name,
65314b24e2bSVaishali Kulkarni 					       data_lo,
65414b24e2bSVaishali Kulkarni 					       ah_stat_regs[reg_id].desc);
65514b24e2bSVaishali Kulkarni 		}
65614b24e2bSVaishali Kulkarni 	}
65714b24e2bSVaishali Kulkarni 
65814b24e2bSVaishali Kulkarni 	return ECORE_SUCCESS;
65914b24e2bSVaishali Kulkarni }
66014b24e2bSVaishali Kulkarni 
ecore_phy_mac_stat(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,char * p_phy_result_buf)66114b24e2bSVaishali Kulkarni int ecore_phy_mac_stat(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
66214b24e2bSVaishali Kulkarni 			u32 port, char *p_phy_result_buf)
66314b24e2bSVaishali Kulkarni {
66414b24e2bSVaishali Kulkarni 	int num_ports = ecore_device_num_ports(p_hwfn->p_dev);
66514b24e2bSVaishali Kulkarni 
66614b24e2bSVaishali Kulkarni 	if (port >= (u32)num_ports) {
66714b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
66814b24e2bSVaishali Kulkarni 			     "Port must be in range of 0..%d\n", num_ports);
66914b24e2bSVaishali Kulkarni 		return ECORE_INVAL;
67014b24e2bSVaishali Kulkarni 	}
67114b24e2bSVaishali Kulkarni 
67214b24e2bSVaishali Kulkarni 	if (ECORE_IS_BB(p_hwfn->p_dev))
67314b24e2bSVaishali Kulkarni 		return ecore_bb_phy_mac_stat(p_hwfn, p_ptt, port,
67414b24e2bSVaishali Kulkarni 					     p_phy_result_buf);
67514b24e2bSVaishali Kulkarni 	else
67614b24e2bSVaishali Kulkarni 		return ecore_ah_e5_phy_mac_stat(p_hwfn, p_ptt, port,
67714b24e2bSVaishali Kulkarni 						p_phy_result_buf);
67814b24e2bSVaishali Kulkarni }
67914b24e2bSVaishali Kulkarni 
68014b24e2bSVaishali Kulkarni #define SFP_RX_LOS_OFFSET 110
68114b24e2bSVaishali Kulkarni #define SFP_TX_DISABLE_OFFSET 110
68214b24e2bSVaishali Kulkarni #define SFP_TX_FAULT_OFFSET 110
68314b24e2bSVaishali Kulkarni 
68414b24e2bSVaishali Kulkarni #define QSFP_RX_LOS_OFFSET 3
68514b24e2bSVaishali Kulkarni #define QSFP_TX_DISABLE_OFFSET 86
68614b24e2bSVaishali Kulkarni #define QSFP_TX_FAULT_OFFSET 4
68714b24e2bSVaishali Kulkarni 
68814b24e2bSVaishali Kulkarni /* Set SFP error string */
ecore_sfp_set_error(enum _ecore_status_t rc,u32 offset,char * p_phy_result_buf,char * p_err_str)68914b24e2bSVaishali Kulkarni static int ecore_sfp_set_error(enum _ecore_status_t rc, u32 offset,
69014b24e2bSVaishali Kulkarni 			       char *p_phy_result_buf, char *p_err_str)
69114b24e2bSVaishali Kulkarni {
69214b24e2bSVaishali Kulkarni 	if (rc != ECORE_SUCCESS) {
69314b24e2bSVaishali Kulkarni 		if (rc == ECORE_NODEV)
69414b24e2bSVaishali Kulkarni 			OSAL_SPRINTF((char *)&p_phy_result_buf[offset],
69514b24e2bSVaishali Kulkarni 				     "Transceiver is unplugged.\n");
69614b24e2bSVaishali Kulkarni 		else
69714b24e2bSVaishali Kulkarni 			OSAL_SPRINTF((char *)&p_phy_result_buf[offset], "%s",
69814b24e2bSVaishali Kulkarni 				     p_err_str);
69914b24e2bSVaishali Kulkarni 
70014b24e2bSVaishali Kulkarni 		return ECORE_UNKNOWN_ERROR;
70114b24e2bSVaishali Kulkarni 	}
70214b24e2bSVaishali Kulkarni 
70314b24e2bSVaishali Kulkarni 	return rc;
70414b24e2bSVaishali Kulkarni }
70514b24e2bSVaishali Kulkarni 
70614b24e2bSVaishali Kulkarni /* Validate SFP port */
ecore_validate_sfp_port(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,char * p_phy_result_buf)70714b24e2bSVaishali Kulkarni static int ecore_validate_sfp_port(struct ecore_hwfn *p_hwfn,
70814b24e2bSVaishali Kulkarni 				   struct ecore_ptt *p_ptt,
70914b24e2bSVaishali Kulkarni 				   u32 port, char *p_phy_result_buf)
71014b24e2bSVaishali Kulkarni {
71114b24e2bSVaishali Kulkarni 	/* Verify <port> field is between 0 and number of ports */
71214b24e2bSVaishali Kulkarni 	u32 num_ports = ecore_device_num_ports(p_hwfn->p_dev);
71314b24e2bSVaishali Kulkarni 
71414b24e2bSVaishali Kulkarni 	if (port >= num_ports) {
71514b24e2bSVaishali Kulkarni 		if (num_ports == 1)
71614b24e2bSVaishali Kulkarni 			OSAL_SPRINTF(p_phy_result_buf,
71714b24e2bSVaishali Kulkarni 				     "Bad port number, must be 0.\n");
71814b24e2bSVaishali Kulkarni 		else
71914b24e2bSVaishali Kulkarni 			OSAL_SPRINTF(p_phy_result_buf,
72014b24e2bSVaishali Kulkarni 				     "Bad port number, must be between 0 and %d.\n",
72114b24e2bSVaishali Kulkarni 				     num_ports-1);
72214b24e2bSVaishali Kulkarni 
72314b24e2bSVaishali Kulkarni 		return ECORE_INVAL;
72414b24e2bSVaishali Kulkarni 	}
72514b24e2bSVaishali Kulkarni 
72614b24e2bSVaishali Kulkarni 	return ECORE_SUCCESS;
72714b24e2bSVaishali Kulkarni }
72814b24e2bSVaishali Kulkarni 
72914b24e2bSVaishali Kulkarni /* Validate SFP parameters */
ecore_validate_sfp_parameters(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 addr,u32 offset,u32 size,char * p_phy_result_buf)73014b24e2bSVaishali Kulkarni static int ecore_validate_sfp_parameters(struct ecore_hwfn *p_hwfn,
73114b24e2bSVaishali Kulkarni 					 struct ecore_ptt *p_ptt,
73214b24e2bSVaishali Kulkarni 					 u32 port, u32 addr, u32 offset,
73314b24e2bSVaishali Kulkarni 					 u32 size, char *p_phy_result_buf)
73414b24e2bSVaishali Kulkarni {
73514b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc;
73614b24e2bSVaishali Kulkarni 
73714b24e2bSVaishali Kulkarni 	/* Verify <port> field is between 0 and number of ports */
73814b24e2bSVaishali Kulkarni 	rc = ecore_validate_sfp_port(p_hwfn, p_ptt, port, p_phy_result_buf);
73914b24e2bSVaishali Kulkarni 	if (rc != ECORE_SUCCESS)
74014b24e2bSVaishali Kulkarni 		return rc;
74114b24e2bSVaishali Kulkarni 
74214b24e2bSVaishali Kulkarni 	/* Verify <I2C> field is 0xA0 or 0xA2 */
74314b24e2bSVaishali Kulkarni 	if ((addr != 0xA0) && (addr != 0xA2)) {
74414b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
74514b24e2bSVaishali Kulkarni 			     "Bad I2C address, must be 0xA0 or 0xA2.\n");
74614b24e2bSVaishali Kulkarni 		return ECORE_INVAL;
74714b24e2bSVaishali Kulkarni 	}
74814b24e2bSVaishali Kulkarni 
74914b24e2bSVaishali Kulkarni 	/* Verify <size> field is 1 - MAX_I2C_TRANSCEIVER_PAGE_SIZE */
75014b24e2bSVaishali Kulkarni 	if ((size == 0) || (size > MAX_I2C_TRANSCEIVER_PAGE_SIZE)) {
75114b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
75214b24e2bSVaishali Kulkarni 			     "Bad size, must be between 1 and %d.\n",
75314b24e2bSVaishali Kulkarni 			     MAX_I2C_TRANSCEIVER_PAGE_SIZE);
75414b24e2bSVaishali Kulkarni 		return ECORE_INVAL;
75514b24e2bSVaishali Kulkarni 	}
75614b24e2bSVaishali Kulkarni 
75714b24e2bSVaishali Kulkarni 	/* Verify <offset> + <size> <= MAX_I2C_TRANSCEIVER_PAGE_SIZE */
75814b24e2bSVaishali Kulkarni 	if (offset + size > MAX_I2C_TRANSCEIVER_PAGE_SIZE) {
75914b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
76014b24e2bSVaishali Kulkarni 			     "Bad offset and size, must not exceed %d.\n",
76114b24e2bSVaishali Kulkarni 			     MAX_I2C_TRANSCEIVER_PAGE_SIZE);
76214b24e2bSVaishali Kulkarni 		return ECORE_INVAL;
76314b24e2bSVaishali Kulkarni 	}
76414b24e2bSVaishali Kulkarni 
76514b24e2bSVaishali Kulkarni 	return rc;
76614b24e2bSVaishali Kulkarni }
76714b24e2bSVaishali Kulkarni 
76814b24e2bSVaishali Kulkarni /* Write to SFP */
ecore_phy_sfp_write(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 port,u32 addr,u32 offset,u32 size,u32 val,char * p_phy_result_buf)76914b24e2bSVaishali Kulkarni int ecore_phy_sfp_write(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
77014b24e2bSVaishali Kulkarni 			u32 port, u32 addr, u32 offset, u32 size,
77114b24e2bSVaishali Kulkarni 			u32 val, char *p_phy_result_buf)
77214b24e2bSVaishali Kulkarni {
77314b24e2bSVaishali Kulkarni 	enum _ecore_status_t rc;
77414b24e2bSVaishali Kulkarni 
77514b24e2bSVaishali Kulkarni 	rc = ecore_validate_sfp_parameters(p_hwfn, p_ptt, port, addr,
77614b24e2bSVaishali Kulkarni 					   offset, size, p_phy_result_buf);
77714b24e2bSVaishali Kulkarni 	if (rc == ECORE_SUCCESS)
77814b24e2bSVaishali Kulkarni 	{
77914b24e2bSVaishali Kulkarni 		rc = ecore_mcp_phy_sfp_write(p_hwfn, p_ptt, port, addr,
78014b24e2bSVaishali Kulkarni 					     offset, size, (u8 *)&val);
78114b24e2bSVaishali Kulkarni 
78214b24e2bSVaishali Kulkarni 		if (rc != ECORE_SUCCESS)
78314b24e2bSVaishali Kulkarni 			return ecore_sfp_set_error(rc, 0, p_phy_result_buf,
78414b24e2bSVaishali Kulkarni 						   "Error writing to transceiver.\n");
78514b24e2bSVaishali Kulkarni 
78614b24e2bSVaishali Kulkarni 		OSAL_SPRINTF(p_phy_result_buf,
78714b24e2bSVaishali Kulkarni 			     "Written successfully to transceiver.\n");
78814b24e2bSVaishali Kulkarni 	}
78914b24e2bSVaishali Kulkarni 
79014b24e2b