1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #include "bcm_osal.h"
37*14b24e2bSVaishali Kulkarni #include "ecore.h"
38*14b24e2bSVaishali Kulkarni #include "ecore_spq.h"
39*14b24e2bSVaishali Kulkarni #include "reg_addr.h"
40*14b24e2bSVaishali Kulkarni #include "ecore_gtt_reg_addr.h"
41*14b24e2bSVaishali Kulkarni #include "ecore_init_ops.h"
42*14b24e2bSVaishali Kulkarni #include "ecore_rt_defs.h"
43*14b24e2bSVaishali Kulkarni #include "ecore_int.h"
44*14b24e2bSVaishali Kulkarni #include "reg_addr.h"
45*14b24e2bSVaishali Kulkarni #include "ecore_hw.h"
46*14b24e2bSVaishali Kulkarni #include "ecore_sriov.h"
47*14b24e2bSVaishali Kulkarni #include "ecore_vf.h"
48*14b24e2bSVaishali Kulkarni #include "ecore_hw_defs.h"
49*14b24e2bSVaishali Kulkarni #include "ecore_hsi_common.h"
50*14b24e2bSVaishali Kulkarni #include "ecore_mcp.h"
51*14b24e2bSVaishali Kulkarni #include "ecore_dbg_fw_funcs.h"
52*14b24e2bSVaishali Kulkarni 
53*14b24e2bSVaishali Kulkarni #ifdef DIAG
54*14b24e2bSVaishali Kulkarni /* This is nasty, but diag is using the drv_dbg_fw_funcs.c [non-ecore flavor],
55*14b24e2bSVaishali Kulkarni  * and so the functions are lacking ecore prefix.
56*14b24e2bSVaishali Kulkarni  * If there would be other clients needing this [or if the content that isn't
57*14b24e2bSVaishali Kulkarni  * really optional there would increase], we'll need to re-think this.
58*14b24e2bSVaishali Kulkarni  */
59*14b24e2bSVaishali Kulkarni enum dbg_status dbg_read_attn(struct ecore_hwfn *dev,
60*14b24e2bSVaishali Kulkarni 							  struct ecore_ptt *ptt,
61*14b24e2bSVaishali Kulkarni 							  enum block_id block,
62*14b24e2bSVaishali Kulkarni 							  enum dbg_attn_type attn_type,
63*14b24e2bSVaishali Kulkarni 							  bool clear_status,
64*14b24e2bSVaishali Kulkarni 							  struct dbg_attn_block_result *results);
65*14b24e2bSVaishali Kulkarni 
66*14b24e2bSVaishali Kulkarni enum dbg_status dbg_parse_attn(struct ecore_hwfn *dev,
67*14b24e2bSVaishali Kulkarni 							   struct dbg_attn_block_result *results);
68*14b24e2bSVaishali Kulkarni 
69*14b24e2bSVaishali Kulkarni const char* dbg_get_status_str(enum dbg_status status);
70*14b24e2bSVaishali Kulkarni 
71*14b24e2bSVaishali Kulkarni #define ecore_dbg_read_attn(hwfn, ptt, id, type, clear, results) \
72*14b24e2bSVaishali Kulkarni 	dbg_read_attn(hwfn, ptt, id, type, clear, results)
73*14b24e2bSVaishali Kulkarni #define ecore_dbg_parse_attn(hwfn, results) \
74*14b24e2bSVaishali Kulkarni 	dbg_parse_attn(hwfn, results)
75*14b24e2bSVaishali Kulkarni #define ecore_dbg_get_status_str(status) \
76*14b24e2bSVaishali Kulkarni 	dbg_get_status_str(status)
77*14b24e2bSVaishali Kulkarni #endif
78*14b24e2bSVaishali Kulkarni 
79*14b24e2bSVaishali Kulkarni struct ecore_pi_info {
80*14b24e2bSVaishali Kulkarni 	ecore_int_comp_cb_t comp_cb;
81*14b24e2bSVaishali Kulkarni 	void *cookie; /* Will be sent to the completion callback function */
82*14b24e2bSVaishali Kulkarni };
83*14b24e2bSVaishali Kulkarni 
84*14b24e2bSVaishali Kulkarni struct ecore_sb_sp_info {
85*14b24e2bSVaishali Kulkarni 	struct ecore_sb_info sb_info;
86*14b24e2bSVaishali Kulkarni 	/* per protocol index data */
87*14b24e2bSVaishali Kulkarni 	struct ecore_pi_info pi_info_arr[PIS_PER_SB];
88*14b24e2bSVaishali Kulkarni };
89*14b24e2bSVaishali Kulkarni 
90*14b24e2bSVaishali Kulkarni enum ecore_attention_type {
91*14b24e2bSVaishali Kulkarni 	ECORE_ATTN_TYPE_ATTN,
92*14b24e2bSVaishali Kulkarni 	ECORE_ATTN_TYPE_PARITY,
93*14b24e2bSVaishali Kulkarni };
94*14b24e2bSVaishali Kulkarni 
95*14b24e2bSVaishali Kulkarni #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
96*14b24e2bSVaishali Kulkarni 	ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
97*14b24e2bSVaishali Kulkarni 
98*14b24e2bSVaishali Kulkarni struct aeu_invert_reg_bit {
99*14b24e2bSVaishali Kulkarni 	char bit_name[30];
100*14b24e2bSVaishali Kulkarni 
101*14b24e2bSVaishali Kulkarni #define ATTENTION_PARITY		(1 << 0)
102*14b24e2bSVaishali Kulkarni 
103*14b24e2bSVaishali Kulkarni #define ATTENTION_LENGTH_MASK		(0x00000ff0)
104*14b24e2bSVaishali Kulkarni #define ATTENTION_LENGTH_SHIFT		(4)
105*14b24e2bSVaishali Kulkarni #define ATTENTION_LENGTH(flags)		(((flags) & ATTENTION_LENGTH_MASK) >> \
106*14b24e2bSVaishali Kulkarni 					 ATTENTION_LENGTH_SHIFT)
107*14b24e2bSVaishali Kulkarni #define ATTENTION_SINGLE		(1 << ATTENTION_LENGTH_SHIFT)
108*14b24e2bSVaishali Kulkarni #define ATTENTION_PAR			(ATTENTION_SINGLE | ATTENTION_PARITY)
109*14b24e2bSVaishali Kulkarni #define ATTENTION_PAR_INT		((2 << ATTENTION_LENGTH_SHIFT) | \
110*14b24e2bSVaishali Kulkarni 					 ATTENTION_PARITY)
111*14b24e2bSVaishali Kulkarni 
112*14b24e2bSVaishali Kulkarni /* Multiple bits start with this offset */
113*14b24e2bSVaishali Kulkarni #define ATTENTION_OFFSET_MASK		(0x000ff000)
114*14b24e2bSVaishali Kulkarni #define ATTENTION_OFFSET_SHIFT		(12)
115*14b24e2bSVaishali Kulkarni 
116*14b24e2bSVaishali Kulkarni #define ATTENTION_BB_MASK		(0x00700000)
117*14b24e2bSVaishali Kulkarni #define ATTENTION_BB_SHIFT		(20)
118*14b24e2bSVaishali Kulkarni #define ATTENTION_BB(value)		(value << ATTENTION_BB_SHIFT)
119*14b24e2bSVaishali Kulkarni #define ATTENTION_BB_DIFFERENT		(1 << 23)
120*14b24e2bSVaishali Kulkarni 
121*14b24e2bSVaishali Kulkarni #define	ATTENTION_CLEAR_ENABLE		(1 << 28)
122*14b24e2bSVaishali Kulkarni 	unsigned int flags;
123*14b24e2bSVaishali Kulkarni 
124*14b24e2bSVaishali Kulkarni 	/* Callback to call if attention will be triggered */
125*14b24e2bSVaishali Kulkarni 	enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
126*14b24e2bSVaishali Kulkarni 
127*14b24e2bSVaishali Kulkarni 	enum block_id block_index;
128*14b24e2bSVaishali Kulkarni };
129*14b24e2bSVaishali Kulkarni 
130*14b24e2bSVaishali Kulkarni struct aeu_invert_reg {
131*14b24e2bSVaishali Kulkarni 	struct aeu_invert_reg_bit bits[32];
132*14b24e2bSVaishali Kulkarni };
133*14b24e2bSVaishali Kulkarni 
134*14b24e2bSVaishali Kulkarni #define MAX_ATTN_GRPS		(8)
135*14b24e2bSVaishali Kulkarni #define NUM_ATTN_REGS		(9)
136*14b24e2bSVaishali Kulkarni 
ecore_mcp_attn_cb(struct ecore_hwfn * p_hwfn)137*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
138*14b24e2bSVaishali Kulkarni {
139*14b24e2bSVaishali Kulkarni 	u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
140*14b24e2bSVaishali Kulkarni 
141*14b24e2bSVaishali Kulkarni 	DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
142*14b24e2bSVaishali Kulkarni 		tmp);
143*14b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
144*14b24e2bSVaishali Kulkarni 		 0xffffffff);
145*14b24e2bSVaishali Kulkarni 
146*14b24e2bSVaishali Kulkarni 	return ECORE_SUCCESS;
147*14b24e2bSVaishali Kulkarni }
148*14b24e2bSVaishali Kulkarni 
149*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK		(0x3c000)
150*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT	(14)
151*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK		(0x03fc0)
152*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT	(6)
153*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK	(0x00020)
154*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT	(5)
155*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK	(0x0001e)
156*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT	(1)
157*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK	(0x1)
158*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT	(0)
159*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_VF_DISABLED		(0x1)
160*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS		(0x1)
161*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK 	(0x1)
162*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT	(0)
163*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK	(0x1e)
164*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT	(1)
165*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK	(0x20)
166*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT	(5)
167*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK	(0x3fc0)
168*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT	(6)
169*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK	(0x3c000)
170*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT	(14)
171*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK	(0x3fc0000)
172*14b24e2bSVaishali Kulkarni #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT	(18)
ecore_pswhst_attn_cb(struct ecore_hwfn * p_hwfn)173*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
174*14b24e2bSVaishali Kulkarni {
175*14b24e2bSVaishali Kulkarni 	u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, PSWHST_REG_VF_DISABLED_ERROR_VALID);
176*14b24e2bSVaishali Kulkarni 
177*14b24e2bSVaishali Kulkarni 	/* Disabled VF access */
178*14b24e2bSVaishali Kulkarni 	if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
179*14b24e2bSVaishali Kulkarni 		u32 addr, data;
180*14b24e2bSVaishali Kulkarni 
181*14b24e2bSVaishali Kulkarni 		addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
182*14b24e2bSVaishali Kulkarni 				PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
183*14b24e2bSVaishali Kulkarni 		data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
184*14b24e2bSVaishali Kulkarni 				PSWHST_REG_VF_DISABLED_ERROR_DATA);
185*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn->p_dev, "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x] Write [0x%02x] Addr [0x%08x]\n",
186*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK) >>
187*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
188*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK) >>
189*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
190*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
191*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
192*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
193*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
194*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
195*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
196*14b24e2bSVaishali Kulkarni 			addr);
197*14b24e2bSVaishali Kulkarni 	}
198*14b24e2bSVaishali Kulkarni 
199*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
200*14b24e2bSVaishali Kulkarni 		       PSWHST_REG_INCORRECT_ACCESS_VALID);
201*14b24e2bSVaishali Kulkarni 	if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
202*14b24e2bSVaishali Kulkarni 		u32 addr, data, length;
203*14b24e2bSVaishali Kulkarni 
204*14b24e2bSVaishali Kulkarni 		addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
205*14b24e2bSVaishali Kulkarni 				PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
206*14b24e2bSVaishali Kulkarni 		data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
207*14b24e2bSVaishali Kulkarni 				PSWHST_REG_INCORRECT_ACCESS_DATA);
208*14b24e2bSVaishali Kulkarni 		length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
209*14b24e2bSVaishali Kulkarni 				  PSWHST_REG_INCORRECT_ACCESS_LENGTH);
210*14b24e2bSVaishali Kulkarni 
211*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn->p_dev, "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
212*14b24e2bSVaishali Kulkarni 			addr, length,
213*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
214*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
215*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
216*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
217*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
218*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
219*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
220*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
221*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
222*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
223*14b24e2bSVaishali Kulkarni 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
224*14b24e2bSVaishali Kulkarni 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
225*14b24e2bSVaishali Kulkarni 			data);
226*14b24e2bSVaishali Kulkarni 	}
227*14b24e2bSVaishali Kulkarni 
228*14b24e2bSVaishali Kulkarni 	/* TODO - We know 'some' of these are legal due to virtualization,
229*14b24e2bSVaishali Kulkarni 	 * but is it true for all of them?
230*14b24e2bSVaishali Kulkarni 	 */
231*14b24e2bSVaishali Kulkarni 	return ECORE_SUCCESS;
232*14b24e2bSVaishali Kulkarni }
233*14b24e2bSVaishali Kulkarni 
234*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_VALID_BIT		(1 << 0)
235*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_ADDRESS_MASK	(0x7fffff << 0)
236*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_RDWR_BIT		(1 << 23)
237*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_MASTER_MASK		(0xf << 24)
238*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_MASTER_SHIFT	(24)
239*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_PF_MASK		(0xf)
240*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_VF_MASK		(0xff << 4)
241*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_VF_SHIFT		(4)
242*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_PRIV_MASK		(0x3 << 14)
243*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_PRIV_SHIFT		(14)
244*14b24e2bSVaishali Kulkarni #define ECORE_GRC_ATTENTION_PRIV_VF		(0)
grc_timeout_attn_master_to_str(u8 master)245*14b24e2bSVaishali Kulkarni static const char* grc_timeout_attn_master_to_str(u8 master)
246*14b24e2bSVaishali Kulkarni {
247*14b24e2bSVaishali Kulkarni 	switch(master) {
248*14b24e2bSVaishali Kulkarni 	case 1: return "PXP";
249*14b24e2bSVaishali Kulkarni 	case 2: return "MCP";
250*14b24e2bSVaishali Kulkarni 	case 3: return "MSDM";
251*14b24e2bSVaishali Kulkarni 	case 4: return "PSDM";
252*14b24e2bSVaishali Kulkarni 	case 5: return "YSDM";
253*14b24e2bSVaishali Kulkarni 	case 6: return "USDM";
254*14b24e2bSVaishali Kulkarni 	case 7: return "TSDM";
255*14b24e2bSVaishali Kulkarni 	case 8: return "XSDM";
256*14b24e2bSVaishali Kulkarni 	case 9: return "DBU";
257*14b24e2bSVaishali Kulkarni 	case 10: return "DMAE";
258*14b24e2bSVaishali Kulkarni 	default:
259*14b24e2bSVaishali Kulkarni 		return "Unkown";
260*14b24e2bSVaishali Kulkarni 	}
261*14b24e2bSVaishali Kulkarni }
262*14b24e2bSVaishali Kulkarni 
ecore_grc_attn_cb(struct ecore_hwfn * p_hwfn)263*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
264*14b24e2bSVaishali Kulkarni {
265*14b24e2bSVaishali Kulkarni 	u32 tmp, tmp2;
266*14b24e2bSVaishali Kulkarni 
267*14b24e2bSVaishali Kulkarni 	/* We've already cleared the timeout interrupt register, so we learn
268*14b24e2bSVaishali Kulkarni 	 * of interrupts via the validity register
269*14b24e2bSVaishali Kulkarni 	 */
270*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
271*14b24e2bSVaishali Kulkarni 		       GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
272*14b24e2bSVaishali Kulkarni 	if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
273*14b24e2bSVaishali Kulkarni 		goto out;
274*14b24e2bSVaishali Kulkarni 
275*14b24e2bSVaishali Kulkarni 	/* Read the GRC timeout information */
276*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
277*14b24e2bSVaishali Kulkarni 		       GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
278*14b24e2bSVaishali Kulkarni 	tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
279*14b24e2bSVaishali Kulkarni 			GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
280*14b24e2bSVaishali Kulkarni 
281*14b24e2bSVaishali Kulkarni 	DP_INFO(p_hwfn->p_dev,
282*14b24e2bSVaishali Kulkarni 		"GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
283*14b24e2bSVaishali Kulkarni 		tmp2, tmp,
284*14b24e2bSVaishali Kulkarni 		(tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
285*14b24e2bSVaishali Kulkarni 		(tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
286*14b24e2bSVaishali Kulkarni 		grc_timeout_attn_master_to_str((tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
287*14b24e2bSVaishali Kulkarni 					       ECORE_GRC_ATTENTION_MASTER_SHIFT),
288*14b24e2bSVaishali Kulkarni 		(tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
289*14b24e2bSVaishali Kulkarni 		(((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
290*14b24e2bSVaishali Kulkarni 		  ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
291*14b24e2bSVaishali Kulkarni 		 ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
292*14b24e2bSVaishali Kulkarni 		(tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
293*14b24e2bSVaishali Kulkarni 		ECORE_GRC_ATTENTION_VF_SHIFT);
294*14b24e2bSVaishali Kulkarni 
295*14b24e2bSVaishali Kulkarni out:
296*14b24e2bSVaishali Kulkarni 	/* Regardles of anything else, clean the validity bit */
297*14b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
298*14b24e2bSVaishali Kulkarni 		 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
299*14b24e2bSVaishali Kulkarni 	return ECORE_SUCCESS;
300*14b24e2bSVaishali Kulkarni }
301*14b24e2bSVaishali Kulkarni 
302*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
303*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
304*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
305*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
306*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
307*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
308*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
309*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
310*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS2_BME	(1 << 22)
311*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
312*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
313*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
314*14b24e2bSVaishali Kulkarni #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
ecore_pglub_rbc_attn_cb(struct ecore_hwfn * p_hwfn)315*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
316*14b24e2bSVaishali Kulkarni {
317*14b24e2bSVaishali Kulkarni 	u32 tmp;
318*14b24e2bSVaishali Kulkarni 
319*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
320*14b24e2bSVaishali Kulkarni 		       PGLUE_B_REG_TX_ERR_WR_DETAILS2);
321*14b24e2bSVaishali Kulkarni 	if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
322*14b24e2bSVaishali Kulkarni 		u32 addr_lo, addr_hi, details;
323*14b24e2bSVaishali Kulkarni 
324*14b24e2bSVaishali Kulkarni 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
325*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
326*14b24e2bSVaishali Kulkarni 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
327*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
328*14b24e2bSVaishali Kulkarni 		details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
329*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_TX_ERR_WR_DETAILS);
330*14b24e2bSVaishali Kulkarni 
331*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn, "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
332*14b24e2bSVaishali Kulkarni 			addr_hi, addr_lo, details,
333*14b24e2bSVaishali Kulkarni 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
334*14b24e2bSVaishali Kulkarni 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
335*14b24e2bSVaishali Kulkarni 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
336*14b24e2bSVaishali Kulkarni 			tmp,
337*14b24e2bSVaishali Kulkarni 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0),
338*14b24e2bSVaishali Kulkarni 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0),
339*14b24e2bSVaishali Kulkarni 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0));
340*14b24e2bSVaishali Kulkarni 	}
341*14b24e2bSVaishali Kulkarni 
342*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
343*14b24e2bSVaishali Kulkarni 		       PGLUE_B_REG_TX_ERR_RD_DETAILS2);
344*14b24e2bSVaishali Kulkarni 	if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
345*14b24e2bSVaishali Kulkarni 		u32 addr_lo, addr_hi, details;
346*14b24e2bSVaishali Kulkarni 
347*14b24e2bSVaishali Kulkarni 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
348*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
349*14b24e2bSVaishali Kulkarni 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
350*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
351*14b24e2bSVaishali Kulkarni 		details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
352*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_TX_ERR_RD_DETAILS);
353*14b24e2bSVaishali Kulkarni 
354*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn, "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
355*14b24e2bSVaishali Kulkarni 			addr_hi, addr_lo, details,
356*14b24e2bSVaishali Kulkarni 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
357*14b24e2bSVaishali Kulkarni 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
358*14b24e2bSVaishali Kulkarni 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
359*14b24e2bSVaishali Kulkarni 			tmp,
360*14b24e2bSVaishali Kulkarni 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0),
361*14b24e2bSVaishali Kulkarni 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0),
362*14b24e2bSVaishali Kulkarni 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0));
363*14b24e2bSVaishali Kulkarni 	}
364*14b24e2bSVaishali Kulkarni 
365*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
366*14b24e2bSVaishali Kulkarni 		       PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
367*14b24e2bSVaishali Kulkarni 	if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
368*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp);
369*14b24e2bSVaishali Kulkarni 
370*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
371*14b24e2bSVaishali Kulkarni 		       PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
372*14b24e2bSVaishali Kulkarni 	if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
373*14b24e2bSVaishali Kulkarni 		u32 addr_hi, addr_lo;
374*14b24e2bSVaishali Kulkarni 
375*14b24e2bSVaishali Kulkarni 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
376*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
377*14b24e2bSVaishali Kulkarni 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
378*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
379*14b24e2bSVaishali Kulkarni 
380*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn, "ICPL eror - %08x [Address %08x:%08x]\n",
381*14b24e2bSVaishali Kulkarni 			tmp, addr_hi, addr_lo);
382*14b24e2bSVaishali Kulkarni 	}
383*14b24e2bSVaishali Kulkarni 
384*14b24e2bSVaishali Kulkarni 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
385*14b24e2bSVaishali Kulkarni 		       PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
386*14b24e2bSVaishali Kulkarni 	if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
387*14b24e2bSVaishali Kulkarni 		u32 addr_hi, addr_lo, details;
388*14b24e2bSVaishali Kulkarni 
389*14b24e2bSVaishali Kulkarni 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
390*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
391*14b24e2bSVaishali Kulkarni 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
392*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
393*14b24e2bSVaishali Kulkarni 		details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
394*14b24e2bSVaishali Kulkarni 				   PGLUE_B_REG_VF_ILT_ERR_DETAILS);
395*14b24e2bSVaishali Kulkarni 
396*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn, "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
397*14b24e2bSVaishali Kulkarni 			details, tmp, addr_hi, addr_lo);
398*14b24e2bSVaishali Kulkarni 	}
399*14b24e2bSVaishali Kulkarni 
400*14b24e2bSVaishali Kulkarni 	/* Clear the indications */
401*14b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
402*14b24e2bSVaishali Kulkarni 		 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
403*14b24e2bSVaishali Kulkarni 
404*14b24e2bSVaishali Kulkarni 	return ECORE_SUCCESS;
405*14b24e2bSVaishali Kulkarni }
406*14b24e2bSVaishali Kulkarni 
ecore_fw_assertion(struct ecore_hwfn * p_hwfn)407*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
408*14b24e2bSVaishali Kulkarni {
409*14b24e2bSVaishali Kulkarni 	DP_NOTICE(p_hwfn, false, "FW assertion!\n");
410*14b24e2bSVaishali Kulkarni 
411*14b24e2bSVaishali Kulkarni 	ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
412*14b24e2bSVaishali Kulkarni 
413*14b24e2bSVaishali Kulkarni 	return ECORE_INVAL;
414*14b24e2bSVaishali Kulkarni }
415*14b24e2bSVaishali Kulkarni 
416*14b24e2bSVaishali Kulkarni static enum _ecore_status_t
ecore_general_attention_35(struct ecore_hwfn * p_hwfn)417*14b24e2bSVaishali Kulkarni ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
418*14b24e2bSVaishali Kulkarni {
419*14b24e2bSVaishali Kulkarni 	DP_INFO(p_hwfn, "General attention 35!\n");
420*14b24e2bSVaishali Kulkarni 
421*14b24e2bSVaishali Kulkarni 	return ECORE_SUCCESS;
422*14b24e2bSVaishali Kulkarni }
423*14b24e2bSVaishali Kulkarni 
424*14b24e2bSVaishali Kulkarni #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff)
425*14b24e2bSVaishali Kulkarni #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
426*14b24e2bSVaishali Kulkarni #define ECORE_DORQ_ATTENTION_SIZE_MASK	 (0x7f0000)
427*14b24e2bSVaishali Kulkarni #define ECORE_DORQ_ATTENTION_SIZE_SHIFT	 (16)
428*14b24e2bSVaishali Kulkarni 
ecore_dorq_attn_cb(struct ecore_hwfn * p_hwfn)429*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
430*14b24e2bSVaishali Kulkarni {
431*14b24e2bSVaishali Kulkarni 	u32 reason;
432*14b24e2bSVaishali Kulkarni 
433*14b24e2bSVaishali Kulkarni 	reason = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
434*14b24e2bSVaishali Kulkarni 		 ECORE_DORQ_ATTENTION_REASON_MASK;
435*14b24e2bSVaishali Kulkarni 	if (reason) {
436*14b24e2bSVaishali Kulkarni 		u32 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
437*14b24e2bSVaishali Kulkarni 				       DORQ_REG_DB_DROP_DETAILS);
438*14b24e2bSVaishali Kulkarni 
439*14b24e2bSVaishali Kulkarni 		DP_INFO(p_hwfn->p_dev,
440*14b24e2bSVaishali Kulkarni 			"DORQ db_drop: adress 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n",
441*14b24e2bSVaishali Kulkarni 			 ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
442*14b24e2bSVaishali Kulkarni 				  DORQ_REG_DB_DROP_DETAILS_ADDRESS),
443*14b24e2bSVaishali Kulkarni 			(u16)(details & ECORE_DORQ_ATTENTION_OPAQUE_MASK),
444*14b24e2bSVaishali Kulkarni 			((details & ECORE_DORQ_ATTENTION_SIZE_MASK) >>
445*14b24e2bSVaishali Kulkarni 			 ECORE_DORQ_ATTENTION_SIZE_SHIFT) * 4, reason);
446*14b24e2bSVaishali Kulkarni 	}
447*14b24e2bSVaishali Kulkarni 
448*14b24e2bSVaishali Kulkarni 	return ECORE_INVAL;
449*14b24e2bSVaishali Kulkarni }
450*14b24e2bSVaishali Kulkarni 
ecore_tm_attn_cb(struct ecore_hwfn * p_hwfn)451*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
452*14b24e2bSVaishali Kulkarni {
453*14b24e2bSVaishali Kulkarni #ifndef ASIC_ONLY
454*14b24e2bSVaishali Kulkarni 	if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
455*14b24e2bSVaishali Kulkarni 		u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
456*14b24e2bSVaishali Kulkarni 				   TM_REG_INT_STS_1);
457*14b24e2bSVaishali Kulkarni 
458*14b24e2bSVaishali Kulkarni 		if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
459*14b24e2bSVaishali Kulkarni 			    TM_REG_INT_STS_1_PEND_CONN_SCAN))
460*14b24e2bSVaishali Kulkarni 			return ECORE_INVAL;
461*14b24e2bSVaishali Kulkarni 
462*14b24e2bSVaishali Kulkarni 		if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
463*14b24e2bSVaishali Kulkarni 			   TM_REG_INT_STS_1_PEND_CONN_SCAN))
464*14b24e2bSVaishali Kulkarni 			DP_INFO(p_hwfn, "TM attention on emulation - most likely results of clock-ratios\n");
465*14b24e2bSVaishali Kulkarni 		val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
466*14b24e2bSVaishali Kulkarni 		val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
467*14b24e2bSVaishali Kulkarni 		       TM_REG_INT_MASK_1_PEND_TASK_SCAN;
468*14b24e2bSVaishali Kulkarni 		ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
469*14b24e2bSVaishali Kulkarni 
470*14b24e2bSVaishali Kulkarni 		return ECORE_SUCCESS;
471*14b24e2bSVaishali Kulkarni 	}
472*14b24e2bSVaishali Kulkarni #endif
473*14b24e2bSVaishali Kulkarni 
474*14b24e2bSVaishali Kulkarni 	return ECORE_INVAL;
475*14b24e2bSVaishali Kulkarni }
476*14b24e2bSVaishali Kulkarni 
477*14b24e2bSVaishali Kulkarni /* Instead of major changes to the data-structure, we have a some 'special'
478*14b24e2bSVaishali Kulkarni  * identifiers for sources that changed meaning between adapters.
479*14b24e2bSVaishali Kulkarni  */
480*14b24e2bSVaishali Kulkarni enum aeu_invert_reg_special_type {
481*14b24e2bSVaishali Kulkarni 	AEU_INVERT_REG_SPECIAL_CNIG_0,
482*14b24e2bSVaishali Kulkarni 	AEU_INVERT_REG_SPECIAL_CNIG_1,
483*14b24e2bSVaishali Kulkarni 	AEU_INVERT_REG_SPECIAL_CNIG_2,
484*14b24e2bSVaishali Kulkarni 	AEU_INVERT_REG_SPECIAL_CNIG_3,
485*14b24e2bSVaishali Kulkarni 	AEU_INVERT_REG_SPECIAL_MAX,
486*14b24e2bSVaishali Kulkarni };
487*14b24e2bSVaishali Kulkarni 
488*14b24e2bSVaishali Kulkarni static struct aeu_invert_reg_bit
489*14b24e2bSVaishali Kulkarni aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
490*14b24e2bSVaishali Kulkarni 	{"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
491*14b24e2bSVaishali Kulkarni 	{"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
492*14b24e2bSVaishali Kulkarni 	{"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
493*14b24e2bSVaishali Kulkarni 	{"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
494*14b24e2bSVaishali Kulkarni };
495*14b24e2bSVaishali Kulkarni 
496*14b24e2bSVaishali Kulkarni /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
497*14b24e2bSVaishali Kulkarni static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] =
498*14b24e2bSVaishali Kulkarni {
499*14b24e2bSVaishali Kulkarni 	{
500*14b24e2bSVaishali Kulkarni 		{	/* After Invert 1 */
501*14b24e2bSVaishali Kulkarni 			{"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
502*14b24e2bSVaishali Kulkarni 		}
503*14b24e2bSVaishali Kulkarni 	},
504*14b24e2bSVaishali Kulkarni 
505*14b24e2bSVaishali Kulkarni 	{
506*14b24e2bSVaishali Kulkarni 		{	/* After Invert 2 */
507*14b24e2bSVaishali Kulkarni 			{"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
508*14b24e2bSVaishali Kulkarni 			{"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
509*14b24e2bSVaishali Kulkarni 			{"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb, BLOCK_PGLUE_B},
510*14b24e2bSVaishali Kulkarni 			{"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
511*14b24e2bSVaishali Kulkarni 			{"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
512*14b24e2bSVaishali Kulkarni 			{"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
513*14b24e2bSVaishali Kulkarni 			{"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
514*14b24e2bSVaishali Kulkarni 			{"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
515*14b24e2bSVaishali Kulkarni 			{"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, BLOCK_PGLCS},
516*14b24e2bSVaishali Kulkarni 		}
517*14b24e2bSVaishali Kulkarni 	},
518*14b24e2bSVaishali Kulkarni 
519*14b24e2bSVaishali Kulkarni 	{
520*14b24e2bSVaishali Kulkarni 		{	/* After Invert 3 */
521*14b24e2bSVaishali Kulkarni 			{"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
522*14b24e2bSVaishali Kulkarni 		}
523*14b24e2bSVaishali Kulkarni 	},
524*14b24e2bSVaishali Kulkarni 
525*14b24e2bSVaishali Kulkarni 	{
526*14b24e2bSVaishali Kulkarni 		{	/* After Invert 4 */
527*14b24e2bSVaishali Kulkarni 			{"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_fw_assertion, MAX_BLOCK_ID},
528*14b24e2bSVaishali Kulkarni 			{"General Attention %d", (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
529*14b24e2bSVaishali Kulkarni 			{"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_general_attention_35, MAX_BLOCK_ID},
530*14b24e2bSVaishali Kulkarni 			{"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
531*14b24e2bSVaishali Kulkarni 				       ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0) , OSAL_NULL, BLOCK_NWS},
532*14b24e2bSVaishali Kulkarni 			{"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
533*14b24e2bSVaishali Kulkarni 					  ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), OSAL_NULL, BLOCK_NWS},
534*14b24e2bSVaishali Kulkarni 			{"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
535*14b24e2bSVaishali Kulkarni 				       ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), OSAL_NULL, BLOCK_NWM},
536*14b24e2bSVaishali Kulkarni 			{"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
537*14b24e2bSVaishali Kulkarni 					  ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), OSAL_NULL, BLOCK_NWM},
538*14b24e2bSVaishali Kulkarni 			{"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
539*14b24e2bSVaishali Kulkarni 			{"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
540*14b24e2bSVaishali Kulkarni 			{"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
541*14b24e2bSVaishali Kulkarni 			{"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
542*14b24e2bSVaishali Kulkarni 			{"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
543*14b24e2bSVaishali Kulkarni 			{"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
544*14b24e2bSVaishali Kulkarni 			{"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
545*14b24e2bSVaishali Kulkarni 			{"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
546*14b24e2bSVaishali Kulkarni 			{"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
547*14b24e2bSVaishali Kulkarni 			{"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
548*14b24e2bSVaishali Kulkarni 			{"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
549*14b24e2bSVaishali Kulkarni 			{"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
550*14b24e2bSVaishali Kulkarni 		}
551*14b24e2bSVaishali Kulkarni 	},
552*14b24e2bSVaishali Kulkarni 
553*14b24e2bSVaishali Kulkarni 	{
554*14b24e2bSVaishali Kulkarni 		{	/* After Invert 5 */
555*14b24e2bSVaishali Kulkarni 			{"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
556*14b24e2bSVaishali Kulkarni 			{"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
557*14b24e2bSVaishali Kulkarni 			{"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
558*14b24e2bSVaishali Kulkarni 			{"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
559*14b24e2bSVaishali Kulkarni 			{"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
560*14b24e2bSVaishali Kulkarni 			{"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
561*14b24e2bSVaishali Kulkarni 			{"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
562*14b24e2bSVaishali Kulkarni 			{"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
563*14b24e2bSVaishali Kulkarni 			{"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
564*14b24e2bSVaishali Kulkarni 			{"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
565*14b24e2bSVaishali Kulkarni 			{"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
566*14b24e2bSVaishali Kulkarni 			{"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
567*14b24e2bSVaishali Kulkarni 			{"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
568*14b24e2bSVaishali Kulkarni 			{"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
569*14b24e2bSVaishali Kulkarni 			{"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
570*14b24e2bSVaishali Kulkarni 			{"TSEM", ATTENTION_PAR_INT,  OSAL_NULL, BLOCK_TSEM},
571*14b24e2bSVaishali Kulkarni 		}
572*14b24e2bSVaishali Kulkarni 	},
573*14b24e2bSVaishali Kulkarni 
574*14b24e2bSVaishali Kulkarni 	{
575*14b24e2bSVaishali Kulkarni 		{	/* After Invert 6 */
576*14b24e2bSVaishali Kulkarni 			{"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
577*14b24e2bSVaishali Kulkarni 			{"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
578*14b24e2bSVaishali Kulkarni 			{"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
579*14b24e2bSVaishali Kulkarni 			{"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
580*14b24e2bSVaishali Kulkarni 			{"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
581*14b24e2bSVaishali Kulkarni 			{"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
582*14b24e2bSVaishali Kulkarni 			{"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
583*14b24e2bSVaishali Kulkarni 			{"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
584*14b24e2bSVaishali Kulkarni 			{"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
585*14b24e2bSVaishali Kulkarni 			{"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
586*14b24e2bSVaishali Kulkarni 			{"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
587*14b24e2bSVaishali Kulkarni 			{"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
588*14b24e2bSVaishali Kulkarni 			{"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
589*14b24e2bSVaishali Kulkarni 			{"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
590*14b24e2bSVaishali Kulkarni 			{"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
591*14b24e2bSVaishali Kulkarni 			{"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
592*14b24e2bSVaishali Kulkarni 		}
593*14b24e2bSVaishali Kulkarni 	},
594*14b24e2bSVaishali Kulkarni 
595*14b24e2bSVaishali Kulkarni 	{
596*14b24e2bSVaishali Kulkarni 		{	/* After Invert 7 */
597*14b24e2bSVaishali Kulkarni 			{"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
598*14b24e2bSVaishali Kulkarni 			{"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
599*14b24e2bSVaishali Kulkarni 			{"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
600*14b24e2bSVaishali Kulkarni 			{"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
601*14b24e2bSVaishali Kulkarni 			{"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
602*14b24e2bSVaishali Kulkarni 			{"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
603*14b24e2bSVaishali Kulkarni 			{"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
604*14b24e2bSVaishali Kulkarni 			{"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
605*14b24e2bSVaishali Kulkarni 			{"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
606*14b24e2bSVaishali Kulkarni 			{"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
607*14b24e2bSVaishali Kulkarni 			{"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
608*14b24e2bSVaishali Kulkarni 			{"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
609*14b24e2bSVaishali Kulkarni 			{"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
610*14b24e2bSVaishali Kulkarni 			{"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
611*14b24e2bSVaishali Kulkarni 			{"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
612*14b24e2bSVaishali Kulkarni 			{"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
613*14b24e2bSVaishali Kulkarni 			{"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
614*14b24e2bSVaishali Kulkarni 		}
615*14b24e2bSVaishali Kulkarni 	},
616*14b24e2bSVaishali Kulkarni 
617*14b24e2bSVaishali Kulkarni 	{
618*14b24e2bSVaishali Kulkarni 		{	/* After Invert 8 */
619*14b24e2bSVaishali Kulkarni 			{"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
620*14b24e2bSVaishali Kulkarni 			{"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
621*14b24e2bSVaishali Kulkarni 			{"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
622*14b24e2bSVaishali Kulkarni 			{"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
623*14b24e2bSVaishali Kulkarni 			{"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
624*14b24e2bSVaishali Kulkarni 			{"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
625*14b24e2bSVaishali Kulkarni 			{"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
626*14b24e2bSVaishali Kulkarni 			{"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
627*14b24e2bSVaishali Kulkarni 			{"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
628*14b24e2bSVaishali Kulkarni 			{"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
629*14b24e2bSVaishali Kulkarni 			{"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
630*14b24e2bSVaishali Kulkarni 			{"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
631*14b24e2bSVaishali Kulkarni 			{"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
632*14b24e2bSVaishali Kulkarni 			{"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
633*14b24e2bSVaishali Kulkarni 			{"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
634*14b24e2bSVaishali Kulkarni 			{"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
635*14b24e2bSVaishali Kulkarni 			{"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
636*14b24e2bSVaishali Kulkarni 			{"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
637*14b24e2bSVaishali Kulkarni 			{"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
638*14b24e2bSVaishali Kulkarni 			{"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
639*14b24e2bSVaishali Kulkarni 			{"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
640*14b24e2bSVaishali Kulkarni 		}
641*14b24e2bSVaishali Kulkarni 	},
642*14b24e2bSVaishali Kulkarni 
643*14b24e2bSVaishali Kulkarni 	{
644*14b24e2bSVaishali Kulkarni 		{	/* After Invert 9 */
645*14b24e2bSVaishali Kulkarni 			{"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
646*14b24e2bSVaishali Kulkarni 			{"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
647*14b24e2bSVaishali Kulkarni 			{"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
648*14b24e2bSVaishali Kulkarni 			{"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
649*14b24e2bSVaishali Kulkarni 			{"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
650*14b24e2bSVaishali Kulkarni 		}
651*14b24e2bSVaishali Kulkarni 	},
652*14b24e2bSVaishali Kulkarni 
653*14b24e2bSVaishali Kulkarni };
654*14b24e2bSVaishali Kulkarni 
655*14b24e2bSVaishali Kulkarni static struct aeu_invert_reg_bit *
ecore_int_aeu_translate(struct ecore_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_bit)656*14b24e2bSVaishali Kulkarni ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
657*14b24e2bSVaishali Kulkarni 			struct aeu_invert_reg_bit *p_bit)
658*14b24e2bSVaishali Kulkarni {
659*14b24e2bSVaishali Kulkarni 	if (!ECORE_IS_BB(p_hwfn->p_dev))
660*14b24e2bSVaishali Kulkarni 		return p_bit;
661*14b24e2bSVaishali Kulkarni 
662*14b24e2bSVaishali Kulkarni 	if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
663*14b24e2bSVaishali Kulkarni 		return p_bit;
664*14b24e2bSVaishali Kulkarni 
665*14b24e2bSVaishali Kulkarni 	return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
666*14b24e2bSVaishali Kulkarni 				  ATTENTION_BB_SHIFT];
667*14b24e2bSVaishali Kulkarni }
668*14b24e2bSVaishali Kulkarni 
ecore_int_is_parity_flag(struct ecore_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_bit)669*14b24e2bSVaishali Kulkarni static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
670*14b24e2bSVaishali Kulkarni 				     struct aeu_invert_reg_bit *p_bit)
671*14b24e2bSVaishali Kulkarni {
672*14b24e2bSVaishali Kulkarni 	return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
673*14b24e2bSVaishali Kulkarni 		  ATTENTION_PARITY);
674*14b24e2bSVaishali Kulkarni }
675*14b24e2bSVaishali Kulkarni 
676*14b24e2bSVaishali Kulkarni #define ATTN_STATE_BITS		(0xfff)
677*14b24e2bSVaishali Kulkarni #define ATTN_BITS_MASKABLE	(0x3ff)
678*14b24e2bSVaishali Kulkarni struct ecore_sb_attn_info {
679*14b24e2bSVaishali Kulkarni 	/* Virtual & Physical address of the SB */
680*14b24e2bSVaishali Kulkarni 	struct atten_status_block	*sb_attn;
681*14b24e2bSVaishali Kulkarni 	dma_addr_t			sb_phys;
682*14b24e2bSVaishali Kulkarni 
683*14b24e2bSVaishali Kulkarni 	/* Last seen running index */
684*14b24e2bSVaishali Kulkarni 	u16				index;
685*14b24e2bSVaishali Kulkarni 
686*14b24e2bSVaishali Kulkarni 	/* A mask of the AEU bits resulting in a parity error */
687*14b24e2bSVaishali Kulkarni 	u32				parity_mask[NUM_ATTN_REGS];
688*14b24e2bSVaishali Kulkarni 
689*14b24e2bSVaishali Kulkarni 	/* A pointer to the attention description structure */
690*14b24e2bSVaishali Kulkarni 	struct aeu_invert_reg		*p_aeu_desc;
691*14b24e2bSVaishali Kulkarni 
692*14b24e2bSVaishali Kulkarni 	/* Previously asserted attentions, which are still unasserted */
693*14b24e2bSVaishali Kulkarni 	u16				known_attn;
694*14b24e2bSVaishali Kulkarni 
695*14b24e2bSVaishali Kulkarni 	/* Cleanup address for the link's general hw attention */
696*14b24e2bSVaishali Kulkarni 	u32				mfw_attn_addr;
697*14b24e2bSVaishali Kulkarni };
698*14b24e2bSVaishali Kulkarni 
ecore_attn_update_idx(struct ecore_hwfn * p_hwfn,struct ecore_sb_attn_info * p_sb_desc)699*14b24e2bSVaishali Kulkarni static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
700*14b24e2bSVaishali Kulkarni 				 struct ecore_sb_attn_info *p_sb_desc)
701*14b24e2bSVaishali Kulkarni {
702*14b24e2bSVaishali Kulkarni 	u16 rc = 0, index;
703*14b24e2bSVaishali Kulkarni 
704*14b24e2bSVaishali Kulkarni 	OSAL_MMIOWB(p_hwfn->p_dev);
705*14b24e2bSVaishali Kulkarni 
706*14b24e2bSVaishali Kulkarni 	index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
707*14b24e2bSVaishali Kulkarni 	if (p_sb_desc->index != index) {
708*14b24e2bSVaishali Kulkarni 		p_sb_desc->index = index;
709*14b24e2bSVaishali Kulkarni 		rc = ECORE_SB_ATT_IDX;
710*14b24e2bSVaishali Kulkarni 	}
711*14b24e2bSVaishali Kulkarni 
712*14b24e2bSVaishali Kulkarni 	OSAL_MMIOWB(p_hwfn->p_dev);
713*14b24e2bSVaishali Kulkarni 
714*14b24e2bSVaishali Kulkarni 	return rc;
715*14b24e2bSVaishali Kulkarni }
716*14b24e2bSVaishali Kulkarni 
717*14b24e2bSVaishali Kulkarni /**
718*14b24e2bSVaishali Kulkarni  * @brief ecore_int_assertion - handles asserted attention bits
719*14b24e2bSVaishali Kulkarni  *
720*14b24e2bSVaishali Kulkarni  * @param p_hwfn
721*14b24e2bSVaishali Kulkarni  * @param asserted_bits newly asserted bits
722*14b24e2bSVaishali Kulkarni  * @return enum _ecore_status_t
723*14b24e2bSVaishali Kulkarni  */
ecore_int_assertion(struct ecore_hwfn * p_hwfn,u16 asserted_bits)724*14b24e2bSVaishali Kulkarni static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
725*14b24e2bSVaishali Kulkarni 						u16 asserted_bits)
726*14b24e2bSVaishali Kulkarni {
727*14b24e2bSVaishali Kulkarni 	struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
728*14b24e2bSVaishali Kulkarni 	u32 igu_mask;
729*14b24e2bSVaishali Kulkarni 
730*14b24e2bSVaishali Kulkarni 	/* Mask the source of the attention in the IGU */
731*14b24e2bSVaishali Kulkarni 	igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
732*14b24e2bSVaishali Kulkarni 			    IGU_REG_ATTENTION_ENABLE);
733*14b24e2bSVaishali Kulkarni 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
734*14b24e2bSVaishali Kulkarni 		   igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
735*14b24e2bSVaishali Kulkarni 	igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
736