114b24e2bSVaishali Kulkarni /*
214b24e2bSVaishali Kulkarni * CDDL HEADER START
314b24e2bSVaishali Kulkarni *
414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
514b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
614b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
714b24e2bSVaishali Kulkarni *
814b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
914b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
1014b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
1114b24e2bSVaishali Kulkarni * and limitations under the License.
1214b24e2bSVaishali Kulkarni *
1314b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
1414b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1514b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
1614b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
1714b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
1814b24e2bSVaishali Kulkarni *
1914b24e2bSVaishali Kulkarni * CDDL HEADER END
2014b24e2bSVaishali Kulkarni */
2114b24e2bSVaishali Kulkarni 
2214b24e2bSVaishali Kulkarni /*
2314b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
2414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
2514b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
2614b24e2bSVaishali Kulkarni 
2714b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
2814b24e2bSVaishali Kulkarni 
2914b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
3014b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
3114b24e2bSVaishali Kulkarni 
3214b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
3314b24e2bSVaishali Kulkarni * limitations under the License.
3414b24e2bSVaishali Kulkarni */
3514b24e2bSVaishali Kulkarni 
3614b24e2bSVaishali Kulkarni #include "bcm_osal.h"
3714b24e2bSVaishali Kulkarni #include "ecore_hw.h"
3814b24e2bSVaishali Kulkarni #include "ecore_init_ops.h"
3914b24e2bSVaishali Kulkarni #include "reg_addr.h"
4014b24e2bSVaishali Kulkarni #include "ecore_rt_defs.h"
4114b24e2bSVaishali Kulkarni #include "ecore_hsi_common.h"
4214b24e2bSVaishali Kulkarni #include "ecore_hsi_init_func.h"
4314b24e2bSVaishali Kulkarni #include "ecore_hsi_eth.h"
4414b24e2bSVaishali Kulkarni #include "ecore_hsi_init_tool.h"
4514b24e2bSVaishali Kulkarni #include "ecore_iro.h"
4614b24e2bSVaishali Kulkarni #include "ecore_init_fw_funcs.h"
4714b24e2bSVaishali Kulkarni 
4814b24e2bSVaishali Kulkarni #define CDU_VALIDATION_DEFAULT_CFG 61
4914b24e2bSVaishali Kulkarni 
5014b24e2bSVaishali Kulkarni static u16 con_region_offsets[3][E4_NUM_OF_CONNECTION_TYPES] = {
5114b24e2bSVaishali Kulkarni 	{ 400,  336,  352,  304,  304,  384,  416,  352}, /* region 3 offsets */
5214b24e2bSVaishali Kulkarni 	{ 528,  496,  416,  448,  448,  512,  544,  480}, /* region 4 offsets */
5314b24e2bSVaishali Kulkarni 	{ 608,  544,  496,  512,  576,  592,  624,  560}  /* region 5 offsets */
5414b24e2bSVaishali Kulkarni };
5514b24e2bSVaishali Kulkarni static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
5614b24e2bSVaishali Kulkarni 	{ 240,  240,  112,    0,    0,    0,    0,   96}  /* region 1 offsets */
5714b24e2bSVaishali Kulkarni };
5814b24e2bSVaishali Kulkarni 
5914b24e2bSVaishali Kulkarni /* General constants */
6014b24e2bSVaishali Kulkarni #define QM_PQ_MEM_4KB(pq_size)			(pq_size ? DIV_ROUND_UP((pq_size + 1) * QM_PQ_ELEMENT_SIZE, 0x1000) : 0)
6114b24e2bSVaishali Kulkarni #define QM_PQ_SIZE_256B(pq_size)		(pq_size ? DIV_ROUND_UP(pq_size, 0x100) - 1 : 0)
6214b24e2bSVaishali Kulkarni #define QM_INVALID_PQ_ID		0xffff
6314b24e2bSVaishali Kulkarni 
6414b24e2bSVaishali Kulkarni /* Feature enable */
6514b24e2bSVaishali Kulkarni #define QM_BYPASS_EN			1
6614b24e2bSVaishali Kulkarni #define QM_BYTE_CRD_EN			1
6714b24e2bSVaishali Kulkarni 
6814b24e2bSVaishali Kulkarni /* Other PQ constants */
6914b24e2bSVaishali Kulkarni #define QM_OTHER_PQS_PER_PF		4
7014b24e2bSVaishali Kulkarni 
7114b24e2bSVaishali Kulkarni /* WFQ constants: */
7214b24e2bSVaishali Kulkarni 
7314b24e2bSVaishali Kulkarni /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
7414b24e2bSVaishali Kulkarni #define QM_WFQ_UPPER_BOUND		62500000
7514b24e2bSVaishali Kulkarni 
7614b24e2bSVaishali Kulkarni /* Bit  of VOQ in WFQ VP PQ map */
7714b24e2bSVaishali Kulkarni #define QM_WFQ_VP_PQ_VOQ_SHIFT		0
7814b24e2bSVaishali Kulkarni 
7914b24e2bSVaishali Kulkarni /* Bit  of PF in WFQ VP PQ map */
8014b24e2bSVaishali Kulkarni #define QM_WFQ_VP_PQ_PF_SHIFT		5
8114b24e2bSVaishali Kulkarni 
8214b24e2bSVaishali Kulkarni /* 0x9000 = 4*9*1024 */
8314b24e2bSVaishali Kulkarni #define QM_WFQ_INC_VAL(weight)		((weight) * 0x9000)
8414b24e2bSVaishali Kulkarni 
8514b24e2bSVaishali Kulkarni /* 0.7 * upper bound (62500000) */
8614b24e2bSVaishali Kulkarni #define QM_WFQ_MAX_INC_VAL		43750000
8714b24e2bSVaishali Kulkarni 
8814b24e2bSVaishali Kulkarni /* RL constants: */
8914b24e2bSVaishali Kulkarni 
9014b24e2bSVaishali Kulkarni /* Upper bound is set to 10 * burst size of 1ms in 50Gbps */
9114b24e2bSVaishali Kulkarni #define QM_RL_UPPER_BOUND		62500000
9214b24e2bSVaishali Kulkarni 
9314b24e2bSVaishali Kulkarni /* Period in us */
9414b24e2bSVaishali Kulkarni #define QM_RL_PERIOD			5
9514b24e2bSVaishali Kulkarni 
9614b24e2bSVaishali Kulkarni /* Period in 25MHz cycles */
9714b24e2bSVaishali Kulkarni #define QM_RL_PERIOD_CLK_25M		(25 * QM_RL_PERIOD)
9814b24e2bSVaishali Kulkarni 
9914b24e2bSVaishali Kulkarni /* 0.7 * upper bound (62500000) */
10014b24e2bSVaishali Kulkarni #define QM_RL_MAX_INC_VAL		43750000
10114b24e2bSVaishali Kulkarni 
10214b24e2bSVaishali Kulkarni /* RL increment value - rate is specified in mbps. the factor of 1.01 was
10314b24e2bSVaishali Kulkarni  * added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC
10414b24e2bSVaishali Kulkarni  * 2544 test. In this scenario the PF RL was reducing the line rate to 99%
10514b24e2bSVaishali Kulkarni  * although the credit increment value was the correct one and FW calculated
10614b24e2bSVaishali Kulkarni  * correct packet sizes. The reason for the inaccuracy of the RL is unknown at
10714b24e2bSVaishali Kulkarni  * this point.
10814b24e2bSVaishali Kulkarni  */
10914b24e2bSVaishali Kulkarni #define QM_RL_INC_VAL(rate)			OSAL_MAX_T(u32, (u32)(((rate ? rate : 1000000) * QM_RL_PERIOD * 101) 	/ (8 * 100)), 1)
11014b24e2bSVaishali Kulkarni 
11114b24e2bSVaishali Kulkarni /* AFullOprtnstcCrdMask constants */
11214b24e2bSVaishali Kulkarni #define QM_OPPOR_LINE_VOQ_DEF		1
11314b24e2bSVaishali Kulkarni #define QM_OPPOR_FW_STOP_DEF		0
11414b24e2bSVaishali Kulkarni #define QM_OPPOR_PQ_EMPTY_DEF		1
11514b24e2bSVaishali Kulkarni 
11614b24e2bSVaishali Kulkarni /* Command Queue constants: */
11714b24e2bSVaishali Kulkarni 
11814b24e2bSVaishali Kulkarni /* Pure LB CmdQ lines (+spare) */
11914b24e2bSVaishali Kulkarni #define PBF_CMDQ_PURE_LB_LINES		150
12014b24e2bSVaishali Kulkarni 
12114b24e2bSVaishali Kulkarni #define PBF_CMDQ_LINES_RT_OFFSET(voq)		(PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq 	* (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 	- PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
12214b24e2bSVaishali Kulkarni 
12314b24e2bSVaishali Kulkarni #define PBF_BTB_GUARANTEED_RT_OFFSET(voq) 	(PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq 	* (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 	- PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
12414b24e2bSVaishali Kulkarni 
12514b24e2bSVaishali Kulkarni #define QM_VOQ_LINE_CRD(pbf_cmd_lines)		((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
12614b24e2bSVaishali Kulkarni 
12714b24e2bSVaishali Kulkarni /* BTB: blocks constants (block size = 256B) */
12814b24e2bSVaishali Kulkarni 
12914b24e2bSVaishali Kulkarni /* 256B blocks in 9700B packet */
13014b24e2bSVaishali Kulkarni #define BTB_JUMBO_PKT_BLOCKS		38
13114b24e2bSVaishali Kulkarni 
13214b24e2bSVaishali Kulkarni /* Headroom per-port */
13314b24e2bSVaishali Kulkarni #define BTB_HEADROOM_BLOCKS		BTB_JUMBO_PKT_BLOCKS
13414b24e2bSVaishali Kulkarni #define BTB_PURE_LB_FACTOR		10
13514b24e2bSVaishali Kulkarni 
13614b24e2bSVaishali Kulkarni /* Factored (hence really 0.7) */
13714b24e2bSVaishali Kulkarni #define BTB_PURE_LB_RATIO		7
13814b24e2bSVaishali Kulkarni 
13914b24e2bSVaishali Kulkarni /* QM stop command constants */
14014b24e2bSVaishali Kulkarni #define QM_STOP_PQ_MASK_WIDTH		32
14114b24e2bSVaishali Kulkarni #define QM_STOP_CMD_ADDR		2
14214b24e2bSVaishali Kulkarni #define QM_STOP_CMD_STRUCT_SIZE		2
14314b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PAUSE_MASK_OFFSET	0
14414b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PAUSE_MASK_SHIFT	0
145*7e3488dcSToomas Soome #define QM_STOP_CMD_PAUSE_MASK_MASK	UINT_MAX
14614b24e2bSVaishali Kulkarni #define QM_STOP_CMD_GROUP_ID_OFFSET	1
14714b24e2bSVaishali Kulkarni #define QM_STOP_CMD_GROUP_ID_SHIFT	16
14814b24e2bSVaishali Kulkarni #define QM_STOP_CMD_GROUP_ID_MASK	15
14914b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PQ_TYPE_OFFSET	1
15014b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PQ_TYPE_SHIFT	24
15114b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PQ_TYPE_MASK	1
15214b24e2bSVaishali Kulkarni #define QM_STOP_CMD_MAX_POLL_COUNT	100
15314b24e2bSVaishali Kulkarni #define QM_STOP_CMD_POLL_PERIOD_US	500
15414b24e2bSVaishali Kulkarni 
15514b24e2bSVaishali Kulkarni /* QM command macros */
15614b24e2bSVaishali Kulkarni #define QM_CMD_STRUCT_SIZE(cmd)		  cmd##_STRUCT_SIZE
15714b24e2bSVaishali Kulkarni #define QM_CMD_SET_FIELD(var, cmd, field, value)  	SET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value)
15814b24e2bSVaishali Kulkarni 
15914b24e2bSVaishali Kulkarni /* QM: VOQ macros */
16014b24e2bSVaishali Kulkarni #define PHYS_VOQ(port, tc, max_phys_tcs_per_port) 	((port) * (max_phys_tcs_per_port) + (tc))
16114b24e2bSVaishali Kulkarni #define LB_VOQ(port)				  	(MAX_PHYS_VOQS + (port))
16214b24e2bSVaishali Kulkarni #define VOQ(port, tc, max_phys_tcs_per_port)	  	((tc) < LB_TC ? PHYS_VOQ(port, tc, max_phys_tcs_per_port) 	: LB_VOQ(port))
16314b24e2bSVaishali Kulkarni 
16414b24e2bSVaishali Kulkarni 
16514b24e2bSVaishali Kulkarni /******************** INTERNAL IMPLEMENTATION *********************/
16614b24e2bSVaishali Kulkarni 
16714b24e2bSVaishali Kulkarni /* Prepare PF RL enable/disable runtime init values */
ecore_enable_pf_rl(struct ecore_hwfn * p_hwfn,bool pf_rl_en)16814b24e2bSVaishali Kulkarni static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn,
16914b24e2bSVaishali Kulkarni 							   bool pf_rl_en)
17014b24e2bSVaishali Kulkarni {
17114b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
17214b24e2bSVaishali Kulkarni 	if (pf_rl_en) {
17314b24e2bSVaishali Kulkarni 
17414b24e2bSVaishali Kulkarni 		/* Enable RLs for all VOQs */
17514b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET, (1 << MAX_NUM_VOQS) - 1);
17614b24e2bSVaishali Kulkarni 
17714b24e2bSVaishali Kulkarni 		/* Write RL period */
17814b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
17914b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIODTIMER_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
18014b24e2bSVaishali Kulkarni 
18114b24e2bSVaishali Kulkarni 		/* Set credit threshold for QM bypass flow */
18214b24e2bSVaishali Kulkarni 		if (QM_BYPASS_EN)
18314b24e2bSVaishali Kulkarni 			STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET, QM_RL_UPPER_BOUND);
18414b24e2bSVaishali Kulkarni 	}
18514b24e2bSVaishali Kulkarni }
18614b24e2bSVaishali Kulkarni 
18714b24e2bSVaishali Kulkarni /* Prepare PF WFQ enable/disable runtime init values */
ecore_enable_pf_wfq(struct ecore_hwfn * p_hwfn,bool pf_wfq_en)18814b24e2bSVaishali Kulkarni static void ecore_enable_pf_wfq(struct ecore_hwfn *p_hwfn,
18914b24e2bSVaishali Kulkarni 								bool pf_wfq_en)
19014b24e2bSVaishali Kulkarni {
19114b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
19214b24e2bSVaishali Kulkarni 
19314b24e2bSVaishali Kulkarni 	/* Set credit threshold for QM bypass flow */
19414b24e2bSVaishali Kulkarni 	if (pf_wfq_en && QM_BYPASS_EN)
19514b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET, QM_WFQ_UPPER_BOUND);
19614b24e2bSVaishali Kulkarni }
19714b24e2bSVaishali Kulkarni 
19814b24e2bSVaishali Kulkarni /* Prepare VPORT RL enable/disable runtime init values */
ecore_enable_vport_rl(struct ecore_hwfn * p_hwfn,bool vport_rl_en)19914b24e2bSVaishali Kulkarni static void ecore_enable_vport_rl(struct ecore_hwfn *p_hwfn,
20014b24e2bSVaishali Kulkarni 								  bool vport_rl_en)
20114b24e2bSVaishali Kulkarni {
20214b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET, vport_rl_en ? 1 : 0);
20314b24e2bSVaishali Kulkarni 	if (vport_rl_en) {
20414b24e2bSVaishali Kulkarni 
20514b24e2bSVaishali Kulkarni 		/* Write RL period (use timer 0 only) */
20614b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIOD_0_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
20714b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
20814b24e2bSVaishali Kulkarni 
20914b24e2bSVaishali Kulkarni 		/* Set credit threshold for QM bypass flow */
21014b24e2bSVaishali Kulkarni 		if (QM_BYPASS_EN)
21114b24e2bSVaishali Kulkarni 			STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET, QM_RL_UPPER_BOUND);
21214b24e2bSVaishali Kulkarni 	}
21314b24e2bSVaishali Kulkarni }
21414b24e2bSVaishali Kulkarni 
21514b24e2bSVaishali Kulkarni /* Prepare VPORT WFQ enable/disable runtime init values */
ecore_enable_vport_wfq(struct ecore_hwfn * p_hwfn,bool vport_wfq_en)21614b24e2bSVaishali Kulkarni static void ecore_enable_vport_wfq(struct ecore_hwfn *p_hwfn,
21714b24e2bSVaishali Kulkarni 								   bool vport_wfq_en)
21814b24e2bSVaishali Kulkarni {
21914b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET, vport_wfq_en ? 1 : 0);
22014b24e2bSVaishali Kulkarni 
22114b24e2bSVaishali Kulkarni 	/* Set credit threshold for QM bypass flow */
22214b24e2bSVaishali Kulkarni 	if (vport_wfq_en && QM_BYPASS_EN)
22314b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET, QM_WFQ_UPPER_BOUND);
22414b24e2bSVaishali Kulkarni }
22514b24e2bSVaishali Kulkarni 
22614b24e2bSVaishali Kulkarni /* Prepare runtime init values to allocate PBF command queue lines for
22714b24e2bSVaishali Kulkarni  * the specified VOQ.
22814b24e2bSVaishali Kulkarni  */
ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn * p_hwfn,u8 voq,u16 cmdq_lines)22914b24e2bSVaishali Kulkarni static void ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn *p_hwfn,
23014b24e2bSVaishali Kulkarni 										 u8 voq,
23114b24e2bSVaishali Kulkarni 										 u16 cmdq_lines)
23214b24e2bSVaishali Kulkarni {
23314b24e2bSVaishali Kulkarni 	u32 qm_line_crd;
23414b24e2bSVaishali Kulkarni 
23514b24e2bSVaishali Kulkarni 	qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
23614b24e2bSVaishali Kulkarni 
23714b24e2bSVaishali Kulkarni 	OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), (u32)cmdq_lines);
23814b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + voq, qm_line_crd);
23914b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + voq, qm_line_crd);
24014b24e2bSVaishali Kulkarni }
24114b24e2bSVaishali Kulkarni 
24214b24e2bSVaishali Kulkarni /* Prepare runtime init values to allocate PBF command queue lines. */
ecore_cmdq_lines_rt_init(struct ecore_hwfn * p_hwfn,u8 max_ports_per_engine,u8 max_phys_tcs_per_port,struct init_qm_port_params port_params[MAX_NUM_PORTS])24314b24e2bSVaishali Kulkarni static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
24414b24e2bSVaishali Kulkarni 									 u8 max_ports_per_engine,
24514b24e2bSVaishali Kulkarni 									 u8 max_phys_tcs_per_port,
24614b24e2bSVaishali Kulkarni 									 struct init_qm_port_params port_params[MAX_NUM_PORTS])
24714b24e2bSVaishali Kulkarni {
24814b24e2bSVaishali Kulkarni 	u8 tc, voq, port_id, num_tcs_in_port;
24914b24e2bSVaishali Kulkarni 
25014b24e2bSVaishali Kulkarni 	/* Clear PBF lines for all VOQs */
25114b24e2bSVaishali Kulkarni 	for (voq = 0; voq < MAX_NUM_VOQS; voq++)
25214b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
25314b24e2bSVaishali Kulkarni 
25414b24e2bSVaishali Kulkarni 	for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
25514b24e2bSVaishali Kulkarni 		u16 phys_lines, phys_lines_per_tc;
25614b24e2bSVaishali Kulkarni 
25714b24e2bSVaishali Kulkarni 		if (!port_params[port_id].active)
25814b24e2bSVaishali Kulkarni 			continue;
25914b24e2bSVaishali Kulkarni 
26014b24e2bSVaishali Kulkarni 		/* Find #lines to divide between the active physical TCs */
26114b24e2bSVaishali Kulkarni 		phys_lines = port_params[port_id].num_pbf_cmd_lines - PBF_CMDQ_PURE_LB_LINES;
26214b24e2bSVaishali Kulkarni 
26314b24e2bSVaishali Kulkarni 		/* Find #lines per active physical TC */
26414b24e2bSVaishali Kulkarni 		num_tcs_in_port = 0;
26514b24e2bSVaishali Kulkarni 		for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
26614b24e2bSVaishali Kulkarni 			if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1)
26714b24e2bSVaishali Kulkarni 				num_tcs_in_port++;
26814b24e2bSVaishali Kulkarni 		phys_lines_per_tc = phys_lines / num_tcs_in_port;
26914b24e2bSVaishali Kulkarni 
27014b24e2bSVaishali Kulkarni 		/* Init registers per active TC */
27114b24e2bSVaishali Kulkarni 		for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
27214b24e2bSVaishali Kulkarni 			if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1) {
27314b24e2bSVaishali Kulkarni 				voq = PHYS_VOQ(port_id, tc, max_phys_tcs_per_port);
27414b24e2bSVaishali Kulkarni 				ecore_cmdq_lines_voq_rt_init(p_hwfn, voq, phys_lines_per_tc);
27514b24e2bSVaishali Kulkarni 			}
27614b24e2bSVaishali Kulkarni 		}
27714b24e2bSVaishali Kulkarni 
27814b24e2bSVaishali Kulkarni 		/* Init registers for pure LB TC */
27914b24e2bSVaishali Kulkarni 		ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id), PBF_CMDQ_PURE_LB_LINES);
28014b24e2bSVaishali Kulkarni 	}
28114b24e2bSVaishali Kulkarni }
28214b24e2bSVaishali Kulkarni 
28314b24e2bSVaishali Kulkarni /* Prepare runtime init values to allocate guaranteed BTB blocks for the
28414b24e2bSVaishali Kulkarni  * specified port. The guaranteed BTB space is divided between the TCs as
28514b24e2bSVaishali Kulkarni  * follows (shared space Is currently not used):
28614b24e2bSVaishali Kulkarni  * 1. Parameters:
28714b24e2bSVaishali Kulkarni  *    B - BTB blocks for this port
28814b24e2bSVaishali Kulkarni  *    C - Number of physical TCs for this port
28914b24e2bSVaishali Kulkarni  * 2. Calculation:
29014b24e2bSVaishali Kulkarni  *    a. 38 blocks (9700B jumbo frame) are allocated for global per port
29114b24e2bSVaishali Kulkarni  *	 headroom.
29214b24e2bSVaishali Kulkarni  *    b. B = B - 38 (remainder after global headroom allocation).
29314b24e2bSVaishali Kulkarni  *    c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ.
29414b24e2bSVaishali Kulkarni  *    d. B = B � MAX(38, B/(C+0.7)) (remainder after pure LB allocation).
29514b24e2bSVaishali Kulkarni  *    e. B/C blocks are allocated for each physical TC.
29614b24e2bSVaishali Kulkarni  * Assumptions:
29714b24e2bSVaishali Kulkarni  * - MTU is up to 9700 bytes (38 blocks)
29814b24e2bSVaishali Kulkarni  * - All TCs are considered symmetrical (same rate and packet size)
29914b24e2bSVaishali Kulkarni  * - No optimization for lossy TC (all are considered lossless). Shared space
30014b24e2bSVaishali Kulkarni  *   is not enabled and allocated for each TC.
30114b24e2bSVaishali Kulkarni  */
ecore_btb_blocks_rt_init(struct ecore_hwfn * p_hwfn,u8 max_ports_per_engine,u8 max_phys_tcs_per_port,struct init_qm_port_params port_params[MAX_NUM_PORTS])30214b24e2bSVaishali Kulkarni static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
30314b24e2bSVaishali Kulkarni 									 u8 max_ports_per_engine,
30414b24e2bSVaishali Kulkarni 									 u8 max_phys_tcs_per_port,
30514b24e2bSVaishali Kulkarni 									 struct init_qm_port_params port_params[MAX_NUM_PORTS])
30614b24e2bSVaishali Kulkarni {
30714b24e2bSVaishali Kulkarni 	u32 usable_blocks, pure_lb_blocks, phys_blocks;
30814b24e2bSVaishali Kulkarni 	u8 tc, voq, port_id, num_tcs_in_port;
30914b24e2bSVaishali Kulkarni 
31014b24e2bSVaishali Kulkarni 	for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
31114b24e2bSVaishali Kulkarni 		if (!port_params[port_id].active)
31214b24e2bSVaishali Kulkarni 			continue;
31314b24e2bSVaishali Kulkarni 
31414b24e2bSVaishali Kulkarni 		/* Subtract headroom blocks */
31514b24e2bSVaishali Kulkarni 		usable_blocks = port_params[port_id].num_btb_blocks - BTB_HEADROOM_BLOCKS;
31614b24e2bSVaishali Kulkarni 
31714b24e2bSVaishali Kulkarni 		/* Find blocks per physical TC. use factor to avoid floating
31814b24e2bSVaishali Kulkarni 		 * arithmethic.
31914b24e2bSVaishali Kulkarni 		 */
32014b24e2bSVaishali Kulkarni 		num_tcs_in_port = 0;
32114b24e2bSVaishali Kulkarni 		for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
32214b24e2bSVaishali Kulkarni 			if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1)
32314b24e2bSVaishali Kulkarni 				num_tcs_in_port++;
32414b24e2bSVaishali Kulkarni 
32514b24e2bSVaishali Kulkarni 		pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) / (num_tcs_in_port * BTB_PURE_LB_FACTOR + BTB_PURE_LB_RATIO);
32614b24e2bSVaishali Kulkarni 		pure_lb_blocks = OSAL_MAX_T(u32, BTB_JUMBO_PKT_BLOCKS, pure_lb_blocks / BTB_PURE_LB_FACTOR);
32714b24e2bSVaishali Kulkarni 		phys_blocks = (usable_blocks - pure_lb_blocks) / num_tcs_in_port;
32814b24e2bSVaishali Kulkarni 
32914b24e2bSVaishali Kulkarni 		/* Init physical TCs */
33014b24e2bSVaishali Kulkarni 		for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
33114b24e2bSVaishali Kulkarni 			if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1) {
33214b24e2bSVaishali Kulkarni 				voq = PHYS_VOQ(port_id, tc, max_phys_tcs_per_port);
33314b24e2bSVaishali Kulkarni 				STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(voq), phys_blocks);
33414b24e2bSVaishali Kulkarni 			}
33514b24e2bSVaishali Kulkarni 		}
33614b24e2bSVaishali Kulkarni 
33714b24e2bSVaishali Kulkarni 		/* Init pure LB TC */
33814b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(LB_VOQ(port_id)), pure_lb_blocks);
33914b24e2bSVaishali Kulkarni 	}
34014b24e2bSVaishali Kulkarni }
34114b24e2bSVaishali Kulkarni 
34214b24e2bSVaishali Kulkarni /* Prepare Tx PQ mapping runtime init values for the specified PF */
ecore_tx_pq_map_rt_init(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 port_id,u8 pf_id,u8 max_phys_tcs_per_port,bool is_first_pf,u32 num_pf_cids,u32 num_vf_cids,u16 start_pq,u16 num_pf_pqs,u16 num_vf_pqs,u8 start_vport,u32 base_mem_addr_4kb,struct init_qm_pq_params * pq_params,struct init_qm_vport_params * vport_params)34314b24e2bSVaishali Kulkarni static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
34414b24e2bSVaishali Kulkarni 									struct ecore_ptt *p_ptt,
34514b24e2bSVaishali Kulkarni 									u8 port_id,
34614b24e2bSVaishali Kulkarni 									u8 pf_id,
34714b24e2bSVaishali Kulkarni 									u8 max_phys_tcs_per_port,
34814b24e2bSVaishali Kulkarni 									bool is_first_pf,
34914b24e2bSVaishali Kulkarni 									u32 num_pf_cids,
35014b24e2bSVaishali Kulkarni 									u32 num_vf_cids,
35114b24e2bSVaishali Kulkarni 									u16 start_pq,
35214b24e2bSVaishali Kulkarni 									u16 num_pf_pqs,
35314b24e2bSVaishali Kulkarni 									u16 num_vf_pqs,
35414b24e2bSVaishali Kulkarni 									u8 start_vport,
35514b24e2bSVaishali Kulkarni 									u32 base_mem_addr_4kb,
35614b24e2bSVaishali Kulkarni 									struct init_qm_pq_params *pq_params,
35714b24e2bSVaishali Kulkarni 									struct init_qm_vport_params *vport_params)
35814b24e2bSVaishali Kulkarni {
35914b24e2bSVaishali Kulkarni 	/* A bit per Tx PQ indicating if the PQ is associated with a VF */
36014b24e2bSVaishali Kulkarni 	u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
36114b24e2bSVaishali Kulkarni 	u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
36214b24e2bSVaishali Kulkarni 	u16 num_pqs, first_pq_group, last_pq_group, i, pq_id, pq_group;
36314b24e2bSVaishali Kulkarni 	u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
36414b24e2bSVaishali Kulkarni 
36514b24e2bSVaishali Kulkarni 	num_pqs = num_pf_pqs + num_vf_pqs;
36614b24e2bSVaishali Kulkarni 
36714b24e2bSVaishali Kulkarni 	first_pq_group = start_pq / QM_PF_QUEUE_GROUP_SIZE;
36814b24e2bSVaishali Kulkarni 	last_pq_group = (start_pq + num_pqs - 1) / QM_PF_QUEUE_GROUP_SIZE;
36914b24e2bSVaishali Kulkarni 
37014b24e2bSVaishali Kulkarni 	pq_mem_4kb = QM_PQ_MEM_4KB(num_pf_cids);
37114b24e2bSVaishali Kulkarni 	vport_pq_mem_4kb = QM_PQ_MEM_4KB(num_vf_cids);
37214b24e2bSVaishali Kulkarni 	mem_addr_4kb = base_mem_addr_4kb;
37314b24e2bSVaishali Kulkarni 
37414b24e2bSVaishali Kulkarni 	/* Set mapping from PQ group to PF */
37514b24e2bSVaishali Kulkarni 	for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
37614b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));
37714b24e2bSVaishali Kulkarni 
37814b24e2bSVaishali Kulkarni 	/* Set PQ sizes */
37914b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET, QM_PQ_SIZE_256B(num_pf_cids));
38014b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET, QM_PQ_SIZE_256B(num_vf_cids));
38114b24e2bSVaishali Kulkarni 
38214b24e2bSVaishali Kulkarni 	/* Go over all Tx PQs */
38314b24e2bSVaishali Kulkarni 	for (i = 0, pq_id = start_pq; i < num_pqs; i++, pq_id++) {
38414b24e2bSVaishali Kulkarni 		u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS;
38514b24e2bSVaishali Kulkarni 		struct qm_rf_pq_map tx_pq_map;
38614b24e2bSVaishali Kulkarni 		bool is_vf_pq, rl_valid;
38714b24e2bSVaishali Kulkarni 		u8 voq, vport_id_in_pf;
38814b24e2bSVaishali Kulkarni 		u16 first_tx_pq_id;
38914b24e2bSVaishali Kulkarni 
39014b24e2bSVaishali Kulkarni 		voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
39114b24e2bSVaishali Kulkarni 		is_vf_pq = (i >= num_pf_pqs);
39214b24e2bSVaishali Kulkarni 		rl_valid = pq_params[i].rl_valid && pq_params[i].vport_id < max_qm_global_rls;
39314b24e2bSVaishali Kulkarni 
39414b24e2bSVaishali Kulkarni 		/* Update first Tx PQ of VPORT/TC */
39514b24e2bSVaishali Kulkarni 		vport_id_in_pf = pq_params[i].vport_id - start_vport;
39614b24e2bSVaishali Kulkarni 		first_tx_pq_id = vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id];
39714b24e2bSVaishali Kulkarni 		if (first_tx_pq_id == QM_INVALID_PQ_ID) {
39814b24e2bSVaishali Kulkarni 
39914b24e2bSVaishali Kulkarni 			/* Create new VP PQ */
40014b24e2bSVaishali Kulkarni 			vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id] = pq_id;
40114b24e2bSVaishali Kulkarni 			first_tx_pq_id = pq_id;
40214b24e2bSVaishali Kulkarni 
40314b24e2bSVaishali Kulkarni 			/* Map VP PQ to VOQ and PF */
40414b24e2bSVaishali Kulkarni 			STORE_RT_REG(p_hwfn, QM_REG_WFQVPMAP_RT_OFFSET + first_tx_pq_id, (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | (pf_id << QM_WFQ_VP_PQ_PF_SHIFT));
40514b24e2bSVaishali Kulkarni 		}
40614b24e2bSVaishali Kulkarni 
40714b24e2bSVaishali Kulkarni 		/* Check RL ID */
40814b24e2bSVaishali Kulkarni 		if (pq_params[i].rl_valid && pq_params[i].vport_id >= max_qm_global_rls)
40914b24e2bSVaishali Kulkarni 			DP_NOTICE(p_hwfn, true, "Invalid VPORT ID for rate limiter configuration\n");
41014b24e2bSVaishali Kulkarni 
41114b24e2bSVaishali Kulkarni 		/* Fill PQ map entry */
41214b24e2bSVaishali Kulkarni 		OSAL_MEMSET(&tx_pq_map, 0, sizeof(tx_pq_map));
41314b24e2bSVaishali Kulkarni 		SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
41414b24e2bSVaishali Kulkarni 		SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0);
41514b24e2bSVaishali Kulkarni 		SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
41614b24e2bSVaishali Kulkarni 		SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID, rl_valid ? pq_params[i].vport_id : 0);
41714b24e2bSVaishali Kulkarni 		SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
41814b24e2bSVaishali Kulkarni 		SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, pq_params[i].wrr_group);
41914b24e2bSVaishali Kulkarni 
42014b24e2bSVaishali Kulkarni 		/* Write PQ map entry to CAM */
42114b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, *((u32*)&tx_pq_map));
42214b24e2bSVaishali Kulkarni 
42314b24e2bSVaishali Kulkarni 		/* Set base address */
42414b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id, mem_addr_4kb);
42514b24e2bSVaishali Kulkarni 
42614b24e2bSVaishali Kulkarni 		/* If VF PQ, add indication to PQ VF mask */
42714b24e2bSVaishali Kulkarni 		if (is_vf_pq) {
42814b24e2bSVaishali Kulkarni 			tx_pq_vf_mask[pq_id / QM_PF_QUEUE_GROUP_SIZE] |= (1 << (pq_id % QM_PF_QUEUE_GROUP_SIZE));
42914b24e2bSVaishali Kulkarni 			mem_addr_4kb += vport_pq_mem_4kb;
43014b24e2bSVaishali Kulkarni 		}
43114b24e2bSVaishali Kulkarni 		else {
43214b24e2bSVaishali Kulkarni 			mem_addr_4kb += pq_mem_4kb;
43314b24e2bSVaishali Kulkarni 		}
43414b24e2bSVaishali Kulkarni 	}
43514b24e2bSVaishali Kulkarni 
43614b24e2bSVaishali Kulkarni 	/* Store Tx PQ VF mask to size select register */
43714b24e2bSVaishali Kulkarni 	for (i = 0; i < num_tx_pq_vf_masks; i++)
43814b24e2bSVaishali Kulkarni 		if (tx_pq_vf_mask[i])
43914b24e2bSVaishali Kulkarni 			STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i, tx_pq_vf_mask[i]);
44014b24e2bSVaishali Kulkarni }
44114b24e2bSVaishali Kulkarni 
44214b24e2bSVaishali Kulkarni /* Prepare Other PQ mapping runtime init values for the specified PF */
ecore_other_pq_map_rt_init(struct ecore_hwfn * p_hwfn,u8 port_id,u8 pf_id,u32 num_pf_cids,u32 num_tids,u32 base_mem_addr_4kb)44314b24e2bSVaishali Kulkarni static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
44414b24e2bSVaishali Kulkarni 									   u8 port_id,
44514b24e2bSVaishali Kulkarni 									   u8 pf_id,
44614b24e2bSVaishali Kulkarni 									   u32 num_pf_cids,
44714b24e2bSVaishali Kulkarni 									   u32 num_tids,
44814b24e2bSVaishali Kulkarni 									   u32 base_mem_addr_4kb)
44914b24e2bSVaishali Kulkarni {
45014b24e2bSVaishali Kulkarni 	u32 pq_size, pq_mem_4kb, mem_addr_4kb;
45114b24e2bSVaishali Kulkarni 	u16 i, pq_id, pq_group;
45214b24e2bSVaishali Kulkarni 
45314b24e2bSVaishali Kulkarni 	/* A single other PQ group is used in each PF, where PQ group i is used
45414b24e2bSVaishali Kulkarni 	 * in PF i.
45514b24e2bSVaishali Kulkarni 	 */
45614b24e2bSVaishali Kulkarni 	pq_group = pf_id;
45714b24e2bSVaishali Kulkarni 	pq_size = num_pf_cids + num_tids;
45814b24e2bSVaishali Kulkarni 	pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
45914b24e2bSVaishali Kulkarni 	mem_addr_4kb = base_mem_addr_4kb;
46014b24e2bSVaishali Kulkarni 
46114b24e2bSVaishali Kulkarni 	/* Map PQ group to PF */
46214b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));
46314b24e2bSVaishali Kulkarni 
46414b24e2bSVaishali Kulkarni 	/* Set PQ sizes */
46514b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET, QM_PQ_SIZE_256B(pq_size));
46614b24e2bSVaishali Kulkarni 
46714b24e2bSVaishali Kulkarni 	/* Set base address */
46814b24e2bSVaishali Kulkarni 	for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE; i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
46914b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id, mem_addr_4kb);
47014b24e2bSVaishali Kulkarni 		mem_addr_4kb += pq_mem_4kb;
47114b24e2bSVaishali Kulkarni 	}
47214b24e2bSVaishali Kulkarni }
47314b24e2bSVaishali Kulkarni 
47414b24e2bSVaishali Kulkarni /* Prepare PF WFQ runtime init values for the specified PF.
47514b24e2bSVaishali Kulkarni  * Return -1 on error.
47614b24e2bSVaishali Kulkarni  */
ecore_pf_wfq_rt_init(struct ecore_hwfn * p_hwfn,u8 port_id,u8 pf_id,u16 pf_wfq,u8 max_phys_tcs_per_port,u16 num_tx_pqs,struct init_qm_pq_params * pq_params)47714b24e2bSVaishali Kulkarni static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
47814b24e2bSVaishali Kulkarni 								u8 port_id,
47914b24e2bSVaishali Kulkarni 								u8 pf_id,
48014b24e2bSVaishali Kulkarni 								u16 pf_wfq,
48114b24e2bSVaishali Kulkarni 								u8 max_phys_tcs_per_port,
48214b24e2bSVaishali Kulkarni 								u16 num_tx_pqs,
48314b24e2bSVaishali Kulkarni 								struct init_qm_pq_params *pq_params)
48414b24e2bSVaishali Kulkarni {
48514b24e2bSVaishali Kulkarni 	u32 inc_val, crd_reg_offset;
48614b24e2bSVaishali Kulkarni 	u8 voq;
48714b24e2bSVaishali Kulkarni 	u16 i;
48814b24e2bSVaishali Kulkarni 
48914b24e2bSVaishali Kulkarni 	crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? QM_REG_WFQPFCRD_RT_OFFSET : QM_REG_WFQPFCRD_MSB_RT_OFFSET) + (pf_id % MAX_NUM_PFS_BB);
49014b24e2bSVaishali Kulkarni 
49114b24e2bSVaishali Kulkarni 	inc_val = QM_WFQ_INC_VAL(pf_wfq);
49214b24e2bSVaishali Kulkarni 	if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
49314b24e2bSVaishali Kulkarni 		DP_NOTICE(p_hwfn, true, "Invalid PF WFQ weight configuration\n");
49414b24e2bSVaishali Kulkarni 		return -1;
49514b24e2bSVaishali Kulkarni 	}
49614b24e2bSVaishali Kulkarni 
49714b24e2bSVaishali Kulkarni 	for(i = 0; i < num_tx_pqs; i++) {
49814b24e2bSVaishali Kulkarni 		voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
49914b24e2bSVaishali Kulkarni 		OVERWRITE_RT_REG(p_hwfn, crd_reg_offset + voq * MAX_NUM_PFS_BB, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
50014b24e2bSVaishali Kulkarni 	}
50114b24e2bSVaishali Kulkarni 
50214b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id, QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
50314b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);
50414b24e2bSVaishali Kulkarni 
50514b24e2bSVaishali Kulkarni 	return 0;
50614b24e2bSVaishali Kulkarni }
50714b24e2bSVaishali Kulkarni 
50814b24e2bSVaishali Kulkarni /* Prepare PF RL runtime init values for the specified PF.
50914b24e2bSVaishali Kulkarni  * Return -1 on error.
51014b24e2bSVaishali Kulkarni  */
ecore_pf_rl_rt_init(struct ecore_hwfn * p_hwfn,u8 pf_id,u32 pf_rl)51114b24e2bSVaishali Kulkarni static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn,
51214b24e2bSVaishali Kulkarni 							  u8 pf_id,
51314b24e2bSVaishali Kulkarni 							  u32 pf_rl)
51414b24e2bSVaishali Kulkarni {
51514b24e2bSVaishali Kulkarni 	u32 inc_val;
51614b24e2bSVaishali Kulkarni 
51714b24e2bSVaishali Kulkarni 	inc_val = QM_RL_INC_VAL(pf_rl);
51814b24e2bSVaishali Kulkarni 	if (inc_val > QM_RL_MAX_INC_VAL) {
51914b24e2bSVaishali Kulkarni 		DP_NOTICE(p_hwfn, true, "Invalid PF rate limit configuration\n");
52014b24e2bSVaishali Kulkarni 		return -1;
52114b24e2bSVaishali Kulkarni 	}
52214b24e2bSVaishali Kulkarni 
52314b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id, (u32)QM_RL_CRD_REG_SIGN_BIT);
52414b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id, QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
52514b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
52614b24e2bSVaishali Kulkarni 
52714b24e2bSVaishali Kulkarni 	return 0;
52814b24e2bSVaishali Kulkarni }
52914b24e2bSVaishali Kulkarni 
53014b24e2bSVaishali Kulkarni /* Prepare VPORT WFQ runtime init values for the specified VPORTs.
53114b24e2bSVaishali Kulkarni  * Return -1 on error.
53214b24e2bSVaishali Kulkarni  */
ecore_vp_wfq_rt_init(struct ecore_hwfn * p_hwfn,u8 num_vports,struct init_qm_vport_params * vport_params)53314b24e2bSVaishali Kulkarni static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
53414b24e2bSVaishali Kulkarni 								u8 num_vports,
53514b24e2bSVaishali Kulkarni 								struct init_qm_vport_params *vport_params)
53614b24e2bSVaishali Kulkarni {
53714b24e2bSVaishali Kulkarni 	u16 vport_pq_id;
53814b24e2bSVaishali Kulkarni 	u32 inc_val;
53914b24e2bSVaishali Kulkarni 	u8 tc, i;
54014b24e2bSVaishali Kulkarni 
54114b24e2bSVaishali Kulkarni 	/* Go over all PF VPORTs */
54214b24e2bSVaishali Kulkarni 	for (i = 0; i < num_vports; i++) {
54314b24e2bSVaishali Kulkarni 		if (!vport_params[i].vport_wfq)
54414b24e2bSVaishali Kulkarni 			continue;
54514b24e2bSVaishali Kulkarni 
54614b24e2bSVaishali Kulkarni 		inc_val = QM_WFQ_INC_VAL(vport_params[i].vport_wfq);
54714b24e2bSVaishali Kulkarni 		if (inc_val > QM_WFQ_MAX_INC_VAL) {
54814b24e2bSVaishali Kulkarni 			DP_NOTICE(p_hwfn, true, "Invalid VPORT WFQ weight configuration\n");
54914b24e2bSVaishali Kulkarni 			return -1;
55014b24e2bSVaishali Kulkarni 		}
55114b24e2bSVaishali Kulkarni 
55214b24e2bSVaishali Kulkarni 		/* Each VPORT can have several VPORT PQ IDs for various TCs */
55314b24e2bSVaishali Kulkarni 		for (tc = 0; tc < NUM_OF_TCS; tc++) {
55414b24e2bSVaishali Kulkarni 			vport_pq_id = vport_params[i].first_tx_pq_id[tc];
55514b24e2bSVaishali Kulkarni 			if (vport_pq_id != QM_INVALID_PQ_ID) {
55614b24e2bSVaishali Kulkarni 				STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET + vport_pq_id, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
55714b24e2bSVaishali Kulkarni 				STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET + vport_pq_id, inc_val);
55814b24e2bSVaishali Kulkarni 			}
55914b24e2bSVaishali Kulkarni 		}
56014b24e2bSVaishali Kulkarni 	}
56114b24e2bSVaishali Kulkarni 
56214b24e2bSVaishali Kulkarni 	return 0;
56314b24e2bSVaishali Kulkarni }
56414b24e2bSVaishali Kulkarni 
56514b24e2bSVaishali Kulkarni /* Prepare VPORT RL runtime init values for the specified VPORTs.
56614b24e2bSVaishali Kulkarni  * Return -1 on error.
56714b24e2bSVaishali Kulkarni  */
ecore_vport_rl_rt_init(struct ecore_hwfn * p_hwfn,u8 start_vport,u8 num_vports,struct init_qm_vport_params * vport_params)56814b24e2bSVaishali Kulkarni static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
56914b24e2bSVaishali Kulkarni 								  u8 start_vport,
57014b24e2bSVaishali Kulkarni 								  u8 num_vports,
57114b24e2bSVaishali Kulkarni 								  struct init_qm_vport_params *vport_params)
57214b24e2bSVaishali Kulkarni {
57314b24e2bSVaishali Kulkarni 	u8 i, vport_id;
57414b24e2bSVaishali Kulkarni 	u32 inc_val;
57514b24e2bSVaishali Kulkarni 
57614b24e2bSVaishali Kulkarni 	if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) {
57714b24e2bSVaishali Kulkarni 		DP_NOTICE(p_hwfn, true, "Invalid VPORT ID for rate limiter configuration\n");
57814b24e2bSVaishali Kulkarni 		return -1;
57914b24e2bSVaishali Kulkarni 	}
58014b24e2bSVaishali Kulkarni 
58114b24e2bSVaishali Kulkarni 	/* Go over all PF VPORTs */
58214b24e2bSVaishali Kulkarni 	for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
58314b24e2bSVaishali Kulkarni 		inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl);
58414b24e2bSVaishali Kulkarni 		if (inc_val > QM_RL_MAX_INC_VAL) {
58514b24e2bSVaishali Kulkarni 			DP_NOTICE(p_hwfn, true, "Invalid VPORT rate-limit configuration\n");
58614b24e2bSVaishali Kulkarni 			return -1;
58714b24e2bSVaishali Kulkarni 		}
58814b24e2bSVaishali Kulkarni 
58914b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id, (u32)QM_RL_CRD_REG_SIGN_BIT);
59014b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id, QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
59114b24e2bSVaishali Kulkarni 		STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id, inc_val);
59214b24e2bSVaishali Kulkarni 	}
59314b24e2bSVaishali Kulkarni 
59414b24e2bSVaishali Kulkarni 	return 0;
59514b24e2bSVaishali Kulkarni }
59614b24e2bSVaishali Kulkarni 
ecore_poll_on_qm_cmd_ready(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)59714b24e2bSVaishali Kulkarni static bool ecore_poll_on_qm_cmd_ready(struct ecore_hwfn *p_hwfn,
59814b24e2bSVaishali Kulkarni 									   struct ecore_ptt *p_ptt)
59914b24e2bSVaishali Kulkarni {
60014b24e2bSVaishali Kulkarni 	u32 reg_val, i;
60114b24e2bSVaishali Kulkarni 
60214b24e2bSVaishali Kulkarni 	for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; i++) {
60314b24e2bSVaishali Kulkarni 		OSAL_UDELAY(QM_STOP_CMD_POLL_PERIOD_US);
60414b24e2bSVaishali Kulkarni 		reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
60514b24e2bSVaishali Kulkarni 	}
60614b24e2bSVaishali Kulkarni 
60714b24e2bSVaishali Kulkarni 	/* Check if timeout while waiting for SDM command ready */
60814b24e2bSVaishali Kulkarni 	if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
60914b24e2bSVaishali Kulkarni 		DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "Timeout when waiting for QM SDM command ready signal\n");
61014b24e2bSVaishali Kulkarni 		return false;
61114b24e2bSVaishali Kulkarni 	}
61214b24e2bSVaishali Kulkarni 
61314b24e2bSVaishali Kulkarni 	return true;
61414b24e2bSVaishali Kulkarni }
61514b24e2bSVaishali Kulkarni 
ecore_send_qm_cmd(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 cmd_addr,u32 cmd_data_lsb,u32 cmd_data_msb)61614b24e2bSVaishali Kulkarni static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn,
61714b24e2bSVaishali Kulkarni 							  struct ecore_ptt *p_ptt,
61814b24e2bSVaishali Kulkarni 					   u32 cmd_addr,
61914b24e2bSVaishali Kulkarni 					   u32 cmd_data_lsb,
62014b24e2bSVaishali Kulkarni 					   u32 cmd_data_msb)
62114b24e2bSVaishali Kulkarni {
62214b24e2bSVaishali Kulkarni 	if (!ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
62314b24e2bSVaishali Kulkarni 		return false;
62414b24e2bSVaishali Kulkarni 
62514b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr);
62614b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb);
62714b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb);
62814b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1);
62914b24e2bSVaishali Kulkarni 	ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0);
63014b24e2bSVaishali Kulkarni 
63114b24e2bSVaishali Kulkarni 	return ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt);
63214b24e2bSVaishali Kulkarni }
63314b24e2bSVaishali Kulkarni 
63414b24e2bSVaishali Kulkarni 
63514b24e2bSVaishali Kulkarni /******************** INTERFACE IMPLEMENTATION *********************/
63614b24e2bSVaishali Kulkarni 
ecore_qm_pf_mem_size(u8 pf_id,u32 num_pf_cids,u32 num_vf_cids,u32 num_tids,u16 num_pf_pqs,u16 num_vf_pqs)63714b24e2bSVaishali Kulkarni u32 ecore_qm_pf_mem_size(u8 pf_id,
63814b24e2bSVaishali Kulkarni 						 u32 num_pf_cids,
63914b24e2bSVaishali Kulkarni 						 u32 num_vf_cids,
64014b24e2bSVaishali Kulkarni 						 u32 num_tids,
64114b24e2bSVaishali Kulkarni 						 u16 num_pf_pqs,
64214b24e2bSVaishali Kulkarni 						 u16 num_vf_pqs)
64314b24e2bSVaishali Kulkarni {
64414b24e2bSVaishali Kulkarni 	return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
64514b24e2bSVaishali Kulkarni 		   QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
64614b24e2bSVaishali Kulkarni 		   QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
64714b24e2bSVaishali Kulkarni }
64814b24e2bSVaishali Kulkarni 
ecore_qm_common_rt_init(struct ecore_hwfn * p_hwfn,u8 max_ports_per_engine,u8 max_phys_tcs_per_port,bool pf_rl_en,bool pf_wfq_en,bool vport_rl_en,bool vport_wfq_en,struct init_qm_port_params port_params[MAX_NUM_PORTS])64914b24e2bSVaishali Kulkarni int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
65014b24e2bSVaishali Kulkarni 							u8 max_ports_per_engine,
65114b24e2bSVaishali Kulkarni 							u8 max_phys_tcs_per_port,
65214b24e2bSVaishali Kulkarni 							bool pf_rl_en,
65314b24e2bSVaishali Kulkarni 							bool pf_wfq_en,
65414b24e2bSVaishali Kulkarni 							bool vport_rl_en,
65514b24e2bSVaishali Kulkarni 							bool vport_wfq_en,
65614b24e2bSVaishali Kulkarni 							struct init_qm_port_params port_params[MAX_NUM_PORTS])
65714b24e2bSVaishali Kulkarni {
65814b24e2bSVaishali Kulkarni 	u32 mask;
65914b24e2bSVaishali Kulkarni 
66014b24e2bSVaishali Kulkarni 	/* Init AFullOprtnstcCrdMask */
66114b24e2bSVaishali Kulkarni 	mask = (QM_OPPOR_LINE_VOQ_DEF << QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT) |
66214b24e2bSVaishali Kulkarni 		(QM_BYTE_CRD_EN << QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT) |
66314b24e2bSVaishali Kulkarni 		(pf_wfq_en << QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT) |
66414b24e2bSVaishali Kulkarni 		(vport_wfq_en << QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT) |
66514b24e2bSVaishali Kulkarni 		(pf_rl_en << QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT) |
66614b24e2bSVaishali Kulkarni 		(vport_rl_en << QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT) |
66714b24e2bSVaishali Kulkarni 		(QM_OPPOR_FW_STOP_DEF << QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT) |
66814b24e2bSVaishali Kulkarni 		(QM_OPPOR_PQ_EMPTY_DEF << QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);
66914b24e2bSVaishali Kulkarni 	STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
67014b24e2bSVaishali Kulkarni 
67114b24e2bSVaishali Kulkarni 	/* Enable/disable PF RL */
67214b24e2bSVaishali Kulkarni 	ecore_enable_pf_rl(p_hwfn, pf_rl_en);
67314b24e2bSVaishali Kulkarni 
67414b24e2bSVaishali Kulkarni 	/* Enable/disable PF WFQ */
67514b24e2bSVaishali Kulkarni 	ecore_enable_pf_wfq(p_hwfn, pf_wfq_en);
67614b24e2bSVaishali Kulkarni 
67714b24e2bSVaishali Kulkarni 	/* Enable/disable VPORT RL */
67814b24e2bSVaishali Kulkarni 	ecore_enable_vport_rl(p_hwfn, vport_rl_en);
67914b24e2bSVaishali Kulkarni 
68014b24e2bSVaishali Kulkarni 	/* Enable/disable VPORT WFQ */
68114b24e2bSVaishali Kulkarni 	ecore_enable_vport_wfq(p_hwfn, vport_wfq_en);
68214b24e2bSVaishali Kulkarni 
68314b24e2bSVaishali Kulkarni 	/* Init PBF CMDQ line credit */
68414b24e2bSVaishali Kulkarni 	ecore_cmdq_lines_rt_init(p_hwfn, max_ports_per_engine, max_phys_tcs_per_port, port_params);
68514b24e2bSVaishali Kulkarni 
68614b24e2bSVaishali Kulkarni 	/* Init BTB blocks in PBF */
68714b24e2bSVaishali Kulkarni 	ecore_btb_blocks_rt_init(p_hwfn, max_ports_per_engine, max_phys_tcs_per_port, port_params);
68814b24e2bSVaishali Kulkarni 
68914b24e2bSVaishali Kulkarni 	return 0;
69014b24e2bSVaishali Kulkarni }
69114b24e2bSVaishali Kulkarni 
ecore_qm_pf_rt_init(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 port_id,u8 pf_id,u8 max_phys_tcs_per_port,bool is_first_pf,u32 num_pf_cids,u32 num_vf_cids,u32 num_tids,u16 start_pq,u16 num_pf_pqs,u16 num_vf_pqs,u8 start_vport,u8 num_vports,u16 pf_wfq,u32 pf_rl,struct init_qm_pq_params * pq_params,struct init_qm_vport_params * vport_params)69214b24e2bSVaishali Kulkarni int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
69314b24e2bSVaishali Kulkarni 						struct ecore_ptt *p_ptt,
69414b24e2bSVaishali Kulkarni 						u8 port_id,
69514b24e2bSVaishali Kulkarni 						u8 pf_id,
69614b24e2bSVaishali Kulkarni 						u8 max_phys_tcs_per_port,
69714b24e2bSVaishali Kulkarni 						bool is_first_pf,
69814b24e2bSVaishali Kulkarni 						u32 num_pf_cids,
69914b24e2bSVaishali Kulkarni 						u32 num_vf_cids,
70014b24e2bSVaishali Kulkarni 						u32 num_tids,
70114b24e2bSVaishali Kulkarni 						u16 start_pq,
70214b24e2bSVaishali Kulkarni 						u16 num_pf_pqs,
70314b24e2bSVaishali Kulkarni 						u16 num_vf_pqs,
70414b24e2bSVaishali Kulkarni 						u8 start_vport,
70514b24e2bSVaishali Kulkarni 						u8 num_vports,
70614b24e2bSVaishali Kulkarni 						u16 pf_wfq,
70714b24e2bSVaishali Kulkarni 						u32 pf_rl,
70814b24e2bSVaishali Kulkarni 						struct init_qm_pq_params *pq_params,
70914b24e2bSVaishali Kulkarni 						struct init_qm_vport_params *vport_params)
71014b24e2bSVaishali Kulkarni {
71114b24e2bSVaishali Kulkarni 	u32 other_mem_size_4kb;
71214b24e2bSVaishali Kulkarni 	u8 tc, i;
71314b24e2bSVaishali Kulkarni 
71414b24e2bSVaishali Kulkarni 	other_mem_size_4kb = QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
71514b24e2bSVaishali Kulkarni 
71614b24e2bSVaishali Kulkarni 	/* Clear first Tx PQ ID array for each VPORT */
71714b24e2bSVaishali Kulkarni 	for(i = 0; i < num_vports; i++)
71814b24e2bSVaishali Kulkarni 		for(tc = 0; tc < NUM_OF_TCS; tc++)
71914b24e2bSVaishali Kulkarni 			vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
72014b24e2bSVaishali Kulkarni 
72114b24e2bSVaishali Kulkarni 	/* Map Other PQs (if any) */
72214b24e2bSVaishali Kulkarni #if QM_OTHER_PQS_PER_PF > 0
72314b24e2bSVaishali Kulkarni 	ecore_other_pq_map_rt_init(p_hwfn, port_id, pf_id, num_pf_cids, num_tids, 0);
72414b24e2bSVaishali Kulkarni #endif
72514b24e2bSVaishali Kulkarni 
72614b24e2bSVaishali Kulkarni 	/* Map Tx PQs */
72714b24e2bSVaishali Kulkarni 	ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, port_id, pf_id, max_phys_tcs_per_port, is_first_pf, num_pf_cids, num_vf_cids,
72814b24e2bSVaishali Kulkarni 							start_pq, num_pf_pqs, num_vf_pqs, start_vport, other_mem_size_4kb, pq_params, vport_params);
72914b24e2bSVaishali Kulkarni 
73014b24e2bSVaishali Kulkarni 	/* Init PF WFQ */
73114b24e2bSVaishali Kulkarni 	if (pf_wfq)
73214b24e2bSVaishali Kulkarni 		if (ecore_pf_wfq_rt_init(p_hwfn, port_id, pf_id, pf_wfq, max_phys_tcs_per_port, num_pf_pqs + num_vf_pqs, pq_params))
73314b24e2bSVaishali Kulkarni 		return -1;
73414b24e2bSVaishali Kulkarni 
73514b24e2bSVaishali Kulkarni 	/* Init PF RL */
73614b24e2bSVaishali Kulkarni 	if (ecore_pf_rl_rt_init(p_hwfn, pf_id, pf_rl))
73714b24e2bSVaishali Kulkarni 		return -1;
73814b24e2bSVaishali Kulkarni 
73914b24e2bSVaishali Kulkarni 	/* Set VPORT WFQ */
74014b24e2bSVaishali Kulkarni 	if (ecore_vp_wfq_rt_init(p_hwfn, num_vports, vport_params))
74114b24e2bSVaishali Kulkarni 		return -1;
74214b24e2bSVaishali Kulkarni 
74314b24e2bSVaishali Kulkarni 	/* Set VPORT RL */
74414b24e2bSVaishali Kulkarni 	if (ecore_vport_rl_rt_init(p_hwfn, start_vport, num_vports, vport_params))
74514b24e2bSVaishali Kulkarni 		return -1;
74614b24e2bSVaishali Kulkarni 
74714b24e2bSVaishali Kulkarni 	return 0;
74814b24e2bSVaishali Kulkarni }
74914b24e2bSVaishali Kulkarni 
ecore_init_pf_wfq(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 pf_id,u16 pf_wfq)75014b24e2bSVaishali Kulkarni int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
75114b24e2bSVaishali Kulkarni 					  struct ecore_ptt *p_ptt,
75214b24e2bSVaishali Kulkarni 					  u8 pf_id,
75314b24e2bSVaishali Kulkarni 					  u16 pf_wfq)
75414b24e2bSVaishali Kulkarni {
75514b24e2bSVaishali Kulkarni 	u32 inc_val;
75614b24e2bSVaishali Kulkarni 
75714b24e2b