xref: /illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw_defs.h (revision 14b24e2b79293068c8e016a69ef1d872fb5e2fd5)
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 #ifndef _ECORE_IGU_DEF_H_
37 #define _ECORE_IGU_DEF_H_
38 
39 /* Fields of IGU PF CONFIGRATION REGISTER */
40 #define IGU_PF_CONF_FUNC_EN       (0x1<<0)  /* function enable        */
41 #define IGU_PF_CONF_MSI_MSIX_EN   (0x1<<1)  /* MSI/MSIX enable        */
42 #define IGU_PF_CONF_INT_LINE_EN   (0x1<<2)  /* INT enable             */
43 #define IGU_PF_CONF_ATTN_BIT_EN   (0x1<<3)  /* attention enable       */
44 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4)  /* single ISR mode enable */
45 #define IGU_PF_CONF_SIMD_MODE     (0x1<<5)  /* simd all ones mode     */
46 
47 /* Fields of IGU VF CONFIGRATION REGISTER */
48 #define IGU_VF_CONF_FUNC_EN        (0x1<<0)  /* function enable        */
49 #define IGU_VF_CONF_MSI_MSIX_EN    (0x1<<1)  /* MSI/MSIX enable        */
50 #define IGU_VF_CONF_SINGLE_ISR_EN  (0x1<<4)  /* single ISR mode enable */
51 #define IGU_VF_CONF_PARENT_MASK    (0xF)     /* Parent PF              */
52 #define IGU_VF_CONF_PARENT_SHIFT   5         /* Parent PF              */
53 
54 /* Igu control commands
55  */
56 enum igu_ctrl_cmd
57 {
58 	IGU_CTRL_CMD_TYPE_RD,
59 	IGU_CTRL_CMD_TYPE_WR,
60 	MAX_IGU_CTRL_CMD
61 };
62 
63 /* Control register for the IGU command register
64  */
65 struct igu_ctrl_reg
66 {
67 	u32 ctrl_data;
68 #define IGU_CTRL_REG_FID_MASK		0xFFFF /* Opaque_FID	 */
69 #define IGU_CTRL_REG_FID_SHIFT		0
70 #define IGU_CTRL_REG_PXP_ADDR_MASK	0xFFF /* Command address */
71 #define IGU_CTRL_REG_PXP_ADDR_SHIFT	16
72 #define IGU_CTRL_REG_RESERVED_MASK	0x1
73 #define IGU_CTRL_REG_RESERVED_SHIFT	28
74 #define IGU_CTRL_REG_TYPE_MASK		0x1 /* use enum igu_ctrl_cmd */
75 #define IGU_CTRL_REG_TYPE_SHIFT		31
76 };
77 
78 #endif
79