1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_TOE__
37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_TOE__
38*14b24e2bSVaishali Kulkarni /************************************************************************/
39*14b24e2bSVaishali Kulkarni /* Add include to common TCP target */
40*14b24e2bSVaishali Kulkarni /************************************************************************/
41*14b24e2bSVaishali Kulkarni #include "tcp_common.h"
42*14b24e2bSVaishali Kulkarni 
43*14b24e2bSVaishali Kulkarni /********************/
44*14b24e2bSVaishali Kulkarni /* TOE FW CONSTANTS */
45*14b24e2bSVaishali Kulkarni /********************/
46*14b24e2bSVaishali Kulkarni 
47*14b24e2bSVaishali Kulkarni #define TOE_MAX_RAMROD_PER_PF				8
48*14b24e2bSVaishali Kulkarni #define TOE_TX_PAGE_SIZE_BYTES				4096
49*14b24e2bSVaishali Kulkarni #define TOE_GRQ_PAGE_SIZE_BYTES				4096
50*14b24e2bSVaishali Kulkarni #define TOE_RX_CQ_PAGE_SIZE_BYTES			4096
51*14b24e2bSVaishali Kulkarni 
52*14b24e2bSVaishali Kulkarni #define TOE_RX_MAX_RSS_CHAINS				64
53*14b24e2bSVaishali Kulkarni #define TOE_TX_MAX_TSS_CHAINS				64
54*14b24e2bSVaishali Kulkarni #define TOE_RSS_INDIRECTION_TABLE_SIZE		128
55*14b24e2bSVaishali Kulkarni 
56*14b24e2bSVaishali Kulkarni 
57*14b24e2bSVaishali Kulkarni /*
58*14b24e2bSVaishali Kulkarni  * The toe storm context of Mstorm
59*14b24e2bSVaishali Kulkarni  */
60*14b24e2bSVaishali Kulkarni struct mstorm_toe_conn_st_ctx
61*14b24e2bSVaishali Kulkarni {
62*14b24e2bSVaishali Kulkarni 	__le32 reserved[24];
63*14b24e2bSVaishali Kulkarni };
64*14b24e2bSVaishali Kulkarni 
65*14b24e2bSVaishali Kulkarni 
66*14b24e2bSVaishali Kulkarni /*
67*14b24e2bSVaishali Kulkarni  * The toe storm context of Pstorm
68*14b24e2bSVaishali Kulkarni  */
69*14b24e2bSVaishali Kulkarni struct pstorm_toe_conn_st_ctx
70*14b24e2bSVaishali Kulkarni {
71*14b24e2bSVaishali Kulkarni 	__le32 reserved[36];
72*14b24e2bSVaishali Kulkarni };
73*14b24e2bSVaishali Kulkarni 
74*14b24e2bSVaishali Kulkarni 
75*14b24e2bSVaishali Kulkarni /*
76*14b24e2bSVaishali Kulkarni  * The toe storm context of Ystorm
77*14b24e2bSVaishali Kulkarni  */
78*14b24e2bSVaishali Kulkarni struct ystorm_toe_conn_st_ctx
79*14b24e2bSVaishali Kulkarni {
80*14b24e2bSVaishali Kulkarni 	__le32 reserved[8];
81*14b24e2bSVaishali Kulkarni };
82*14b24e2bSVaishali Kulkarni 
83*14b24e2bSVaishali Kulkarni /*
84*14b24e2bSVaishali Kulkarni  * The toe storm context of Xstorm
85*14b24e2bSVaishali Kulkarni  */
86*14b24e2bSVaishali Kulkarni struct xstorm_toe_conn_st_ctx
87*14b24e2bSVaishali Kulkarni {
88*14b24e2bSVaishali Kulkarni 	__le32 reserved[44];
89*14b24e2bSVaishali Kulkarni };
90*14b24e2bSVaishali Kulkarni 
91*14b24e2bSVaishali Kulkarni struct e4_ystorm_toe_conn_ag_ctx
92*14b24e2bSVaishali Kulkarni {
93*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
94*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
95*14b24e2bSVaishali Kulkarni 	u8 flags0;
96*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
97*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
98*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
99*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT                 1
100*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK          0x3 /* cf0 */
101*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT         2
102*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK     0x3 /* cf1 */
103*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_SHIFT    4
104*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_CF2_MASK                   0x3 /* cf2 */
105*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_CF2_SHIFT                  6
106*14b24e2bSVaishali Kulkarni 	u8 flags1;
107*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK       0x1 /* cf0en */
108*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT      0
109*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK  0x1 /* cf1en */
110*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_SHIFT 1
111*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
112*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT                2
113*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK            0x1 /* rule0en */
114*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_SHIFT           3
115*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
116*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT              4
117*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
118*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT              5
119*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
120*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT              6
121*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK          0x1 /* rule4en */
122*14b24e2bSVaishali Kulkarni #define E4_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_SHIFT         7
123*14b24e2bSVaishali Kulkarni 	u8 completion_opcode /* byte2 */;
124*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
125*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
126*14b24e2bSVaishali Kulkarni 	__le32 rel_seq /* reg0 */;
127*14b24e2bSVaishali Kulkarni 	__le32 rel_seq_threshold /* reg1 */;
128*14b24e2bSVaishali Kulkarni 	__le16 app_prod /* word1 */;
129*14b24e2bSVaishali Kulkarni 	__le16 app_cons /* word2 */;
130*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
131*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
132*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
133*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
134*14b24e2bSVaishali Kulkarni };
135*14b24e2bSVaishali Kulkarni 
136*14b24e2bSVaishali Kulkarni struct e4_xstorm_toe_conn_ag_ctx
137*14b24e2bSVaishali Kulkarni {
138*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
139*14b24e2bSVaishali Kulkarni 	u8 state /* state */;
140*14b24e2bSVaishali Kulkarni 	u8 flags0;
141*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
142*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
143*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK          0x1 /* exist_in_qm1 */
144*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_SHIFT         1
145*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK             0x1 /* exist_in_qm2 */
146*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED1_SHIFT            2
147*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK          0x1 /* exist_in_qm3 */
148*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT         3
149*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK       0x1 /* bit4 */
150*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_SHIFT      4
151*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK             0x1 /* cf_array_active */
152*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED2_SHIFT            5
153*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT6_MASK                  0x1 /* bit6 */
154*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT6_SHIFT                 6
155*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT7_MASK                  0x1 /* bit7 */
156*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT7_SHIFT                 7
157*14b24e2bSVaishali Kulkarni 	u8 flags1;
158*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT8_MASK                  0x1 /* bit8 */
159*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT                 0
160*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT9_MASK                  0x1 /* bit9 */
161*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT9_SHIFT                 1
162*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT10_MASK                 0x1 /* bit10 */
163*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT10_SHIFT                2
164*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT11_MASK                 0x1 /* bit11 */
165*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT11_SHIFT                3
166*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT12_MASK                 0x1 /* bit12 */
167*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT12_SHIFT                4
168*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT13_MASK                 0x1 /* bit13 */
169*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT13_SHIFT                5
170*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT14_MASK                 0x1 /* bit14 */
171*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT14_SHIFT                6
172*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT15_MASK                 0x1 /* bit15 */
173*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT15_SHIFT                7
174*14b24e2bSVaishali Kulkarni 	u8 flags2;
175*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF0_MASK                   0x3 /* timer0cf */
176*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT                  0
177*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF1_MASK                   0x3 /* timer1cf */
178*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF1_SHIFT                  2
179*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
180*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF2_SHIFT                  4
181*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK        0x3 /* timer_stop_all */
182*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT       6
183*14b24e2bSVaishali Kulkarni 	u8 flags3;
184*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF4_MASK                   0x3 /* cf4 */
185*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT                  0
186*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF5_MASK                   0x3 /* cf5 */
187*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF5_SHIFT                  2
188*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
189*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF6_SHIFT                  4
190*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
191*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF7_SHIFT                  6
192*14b24e2bSVaishali Kulkarni 	u8 flags4;
193*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
194*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT                  0
195*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
196*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF9_SHIFT                  2
197*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
198*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF10_SHIFT                 4
199*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF11_MASK                  0x3 /* cf11 */
200*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF11_SHIFT                 6
201*14b24e2bSVaishali Kulkarni 	u8 flags5;
202*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF12_MASK                  0x3 /* cf12 */
203*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT                 0
204*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF13_MASK                  0x3 /* cf13 */
205*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF13_SHIFT                 2
206*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF14_MASK                  0x3 /* cf14 */
207*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF14_SHIFT                 4
208*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF15_MASK                  0x3 /* cf15 */
209*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF15_SHIFT                 6
210*14b24e2bSVaishali Kulkarni 	u8 flags6;
211*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF16_MASK                  0x3 /* cf16 */
212*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT                 0
213*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF17_MASK                  0x3 /* cf_array_cf */
214*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF17_SHIFT                 2
215*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF18_MASK                  0x3 /* cf18 */
216*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF18_SHIFT                 4
217*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK              0x3 /* cf19 */
218*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_SHIFT             6
219*14b24e2bSVaishali Kulkarni 	u8 flags7;
220*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK              0x3 /* cf20 */
221*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT             0
222*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK              0x3 /* cf21 */
223*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_SHIFT             2
224*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK             0x3 /* cf22 */
225*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_SHIFT            4
226*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK                 0x1 /* cf0en */
227*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT                6
228*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK                 0x1 /* cf1en */
229*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT                7
230*14b24e2bSVaishali Kulkarni 	u8 flags8;
231*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
232*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT                0
233*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK     0x1 /* cf3en */
234*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT    1
235*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK                 0x1 /* cf4en */
236*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT                2
237*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK                 0x1 /* cf5en */
238*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT                3
239*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
240*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT                4
241*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
242*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT                5
243*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
244*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT                6
245*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
246*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF9EN_SHIFT                7
247*14b24e2bSVaishali Kulkarni 	u8 flags9;
248*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
249*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT               0
250*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK                0x1 /* cf11en */
251*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF11EN_SHIFT               1
252*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK                0x1 /* cf12en */
253*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF12EN_SHIFT               2
254*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK                0x1 /* cf13en */
255*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF13EN_SHIFT               3
256*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK                0x1 /* cf14en */
257*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF14EN_SHIFT               4
258*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK                0x1 /* cf15en */
259*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF15EN_SHIFT               5
260*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK                0x1 /* cf16en */
261*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF16EN_SHIFT               6
262*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK                0x1 /* cf_array_cf_en */
263*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF17EN_SHIFT               7
264*14b24e2bSVaishali Kulkarni 	u8 flags10;
265*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK                0x1 /* cf18en */
266*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT               0
267*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK           0x1 /* cf19en */
268*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT          1
269*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK           0x1 /* cf20en */
270*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT          2
271*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK           0x1 /* cf21en */
272*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT          3
273*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK          0x1 /* cf22en */
274*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT         4
275*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK                0x1 /* cf23en */
276*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF23EN_SHIFT               5
277*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
278*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT              6
279*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK  0x1 /* rule1en */
280*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
281*14b24e2bSVaishali Kulkarni 	u8 flags11;
282*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK         0x1 /* rule2en */
283*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT        0
284*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
285*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT              1
286*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK             0x1 /* rule4en */
287*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED3_SHIFT            2
288*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
289*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT              3
290*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
291*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT              4
292*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
293*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT              5
294*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK          0x1 /* rule8en */
295*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_SHIFT         6
296*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK               0x1 /* rule9en */
297*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE9EN_SHIFT              7
298*14b24e2bSVaishali Kulkarni 	u8 flags12;
299*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK              0x1 /* rule10en */
300*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT             0
301*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK              0x1 /* rule11en */
302*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE11EN_SHIFT             1
303*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK          0x1 /* rule12en */
304*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_SHIFT         2
305*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK          0x1 /* rule13en */
306*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_SHIFT         3
307*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK              0x1 /* rule14en */
308*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE14EN_SHIFT             4
309*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK              0x1 /* rule15en */
310*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE15EN_SHIFT             5
311*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK              0x1 /* rule16en */
312*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE16EN_SHIFT             6
313*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK              0x1 /* rule17en */
314*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE17EN_SHIFT             7
315*14b24e2bSVaishali Kulkarni 	u8 flags13;
316*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK              0x1 /* rule18en */
317*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT             0
318*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK              0x1 /* rule19en */
319*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_RULE19EN_SHIFT             1
320*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK          0x1 /* rule20en */
321*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_SHIFT         2
322*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK          0x1 /* rule21en */
323*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_SHIFT         3
324*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK          0x1 /* rule22en */
325*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_SHIFT         4
326*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK          0x1 /* rule23en */
327*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_SHIFT         5
328*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK          0x1 /* rule24en */
329*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_SHIFT         6
330*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK          0x1 /* rule25en */
331*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_SHIFT         7
332*14b24e2bSVaishali Kulkarni 	u8 flags14;
333*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT16_MASK                 0x1 /* bit16 */
334*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT                0
335*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT17_MASK                 0x1 /* bit17 */
336*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT17_SHIFT                1
337*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT18_MASK                 0x1 /* bit18 */
338*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT18_SHIFT                2
339*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT19_MASK                 0x1 /* bit19 */
340*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT19_SHIFT                3
341*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT20_MASK                 0x1 /* bit20 */
342*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT20_SHIFT                4
343*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT21_MASK                 0x1 /* bit21 */
344*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_BIT21_SHIFT                5
345*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF23_MASK                  0x3 /* cf23 */
346*14b24e2bSVaishali Kulkarni #define E4_XSTORM_TOE_CONN_AG_CTX_CF23_SHIFT                 6
347*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
348*14b24e2bSVaishali Kulkarni 	__le16 physical_q0 /* physical_q0 */;
349*14b24e2bSVaishali Kulkarni 	__le16 physical_q1 /* physical_q1 */;
350*14b24e2bSVaishali Kulkarni 	__le16 word2 /* physical_q2 */;
351*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
352*14b24e2bSVaishali Kulkarni 	__le16 bd_prod /* word4 */;
353*14b24e2bSVaishali Kulkarni 	__le16 word5 /* word5 */;
354*14b24e2bSVaishali Kulkarni 	__le16 word6 /* conn_dpi */;
355*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
356*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
357*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
358*14b24e2bSVaishali Kulkarni 	u8 byte6 /* byte6 */;
359*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
360*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
361*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
362*14b24e2bSVaishali Kulkarni 	__le32 more_to_send_seq /* reg3 */;
363*14b24e2bSVaishali Kulkarni 	__le32 local_adv_wnd_seq /* reg4 */;
364*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* cf_array0 */;
365*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* cf_array1 */;
366*14b24e2bSVaishali Kulkarni 	__le16 word7 /* word7 */;
367*14b24e2bSVaishali Kulkarni 	__le16 word8 /* word8 */;
368*14b24e2bSVaishali Kulkarni 	__le16 word9 /* word9 */;
369*14b24e2bSVaishali Kulkarni 	__le16 word10 /* word10 */;
370*14b24e2bSVaishali Kulkarni 	__le32 reg7 /* reg7 */;
371*14b24e2bSVaishali Kulkarni 	__le32 reg8 /* reg8 */;
372*14b24e2bSVaishali Kulkarni 	__le32 reg9 /* reg9 */;
373*14b24e2bSVaishali Kulkarni 	u8 byte7 /* byte7 */;
374*14b24e2bSVaishali Kulkarni 	u8 byte8 /* byte8 */;
375*14b24e2bSVaishali Kulkarni 	u8 byte9 /* byte9 */;
376*14b24e2bSVaishali Kulkarni 	u8 byte10 /* byte10 */;
377*14b24e2bSVaishali Kulkarni 	u8 byte11 /* byte11 */;
378*14b24e2bSVaishali Kulkarni 	u8 byte12 /* byte12 */;
379*14b24e2bSVaishali Kulkarni 	u8 byte13 /* byte13 */;
380*14b24e2bSVaishali Kulkarni 	u8 byte14 /* byte14 */;
381*14b24e2bSVaishali Kulkarni 	u8 byte15 /* byte15 */;
382*14b24e2bSVaishali Kulkarni 	u8 e5_reserved /* e5_reserved */;
383*14b24e2bSVaishali Kulkarni 	__le16 word11 /* word11 */;
384*14b24e2bSVaishali Kulkarni 	__le32 reg10 /* reg10 */;
385*14b24e2bSVaishali Kulkarni 	__le32 reg11 /* reg11 */;
386*14b24e2bSVaishali Kulkarni 	__le32 reg12 /* reg12 */;
387*14b24e2bSVaishali Kulkarni 	__le32 reg13 /* reg13 */;
388*14b24e2bSVaishali Kulkarni 	__le32 reg14 /* reg14 */;
389*14b24e2bSVaishali Kulkarni 	__le32 reg15 /* reg15 */;
390*14b24e2bSVaishali Kulkarni 	__le32 reg16 /* reg16 */;
391*14b24e2bSVaishali Kulkarni 	__le32 reg17 /* reg17 */;
392*14b24e2bSVaishali Kulkarni };
393*14b24e2bSVaishali Kulkarni 
394*14b24e2bSVaishali Kulkarni struct e4_tstorm_toe_conn_ag_ctx
395*14b24e2bSVaishali Kulkarni {
396*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
397*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
398*14b24e2bSVaishali Kulkarni 	u8 flags0;
399*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
400*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
401*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT1_MASK               0x1 /* exist_in_qm1 */
402*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT              1
403*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT2_MASK               0x1 /* bit2 */
404*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT2_SHIFT              2
405*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT3_MASK               0x1 /* bit3 */
406*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT3_SHIFT              3
407*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT4_MASK               0x1 /* bit4 */
408*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT4_SHIFT              4
409*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT5_MASK               0x1 /* bit5 */
410*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_BIT5_SHIFT              5
411*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK         0x3 /* timer0cf */
412*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_SHIFT        6
413*14b24e2bSVaishali Kulkarni 	u8 flags1;
414*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
415*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT               0
416*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF2_MASK                0x3 /* timer2cf */
417*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF2_SHIFT               2
418*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK     0x3 /* timer_stop_all */
419*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT    4
420*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF4_MASK                0x3 /* cf4 */
421*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF4_SHIFT               6
422*14b24e2bSVaishali Kulkarni 	u8 flags2;
423*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF5_MASK                0x3 /* cf5 */
424*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT               0
425*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
426*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF6_SHIFT               2
427*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF7_MASK                0x3 /* cf7 */
428*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF7_SHIFT               4
429*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF8_MASK                0x3 /* cf8 */
430*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF8_SHIFT               6
431*14b24e2bSVaishali Kulkarni 	u8 flags3;
432*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3 /* cf9 */
433*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
434*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF10_MASK               0x3 /* cf10 */
435*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF10_SHIFT              2
436*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK      0x1 /* cf0en */
437*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_SHIFT     4
438*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
439*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT             5
440*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
441*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT             6
442*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK  0x1 /* cf3en */
443*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
444*14b24e2bSVaishali Kulkarni 	u8 flags4;
445*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK              0x1 /* cf4en */
446*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT             0
447*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK              0x1 /* cf5en */
448*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT             1
449*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
450*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT             2
451*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK              0x1 /* cf7en */
452*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT             3
453*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK              0x1 /* cf8en */
454*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT             4
455*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1 /* cf9en */
456*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       5
457*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK             0x1 /* cf10en */
458*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT            6
459*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
460*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT           7
461*14b24e2bSVaishali Kulkarni 	u8 flags5;
462*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
463*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT           0
464*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
465*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT           1
466*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
467*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT           2
468*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
469*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT           3
470*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
471*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT           4
472*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
473*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT           5
474*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
475*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT           6
476*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK            0x1 /* rule8en */
477*14b24e2bSVaishali Kulkarni #define E4_TSTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT           7
478*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
479*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
480*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
481*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
482*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
483*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* reg5 */;
484*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* reg6 */;
485*14b24e2bSVaishali Kulkarni 	__le32 reg7 /* reg7 */;
486*14b24e2bSVaishali Kulkarni 	__le32 reg8 /* reg8 */;
487*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
488*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
489*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
490*14b24e2bSVaishali Kulkarni };
491*14b24e2bSVaishali Kulkarni 
492*14b24e2bSVaishali Kulkarni struct e4_ustorm_toe_conn_ag_ctx
493*14b24e2bSVaishali Kulkarni {
494*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
495*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
496*14b24e2bSVaishali Kulkarni 	u8 flags0;
497*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
498*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
499*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_BIT1_MASK               0x1 /* exist_in_qm1 */
500*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_BIT1_SHIFT              1
501*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF0_MASK                0x3 /* timer0cf */
502*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF0_SHIFT               2
503*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
504*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF1_SHIFT               4
505*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK      0x3 /* timer2cf */
506*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_SHIFT     6
507*14b24e2bSVaishali Kulkarni 	u8 flags1;
508*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK     0x3 /* timer_stop_all */
509*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT    0
510*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK       0x3 /* cf4 */
511*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT      2
512*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK              0x3 /* cf5 */
513*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_SHIFT             4
514*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
515*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF6_SHIFT               6
516*14b24e2bSVaishali Kulkarni 	u8 flags2;
517*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF0EN_MASK              0x1 /* cf0en */
518*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT             0
519*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
520*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT             1
521*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK   0x1 /* cf2en */
522*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_SHIFT  2
523*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK  0x1 /* cf3en */
524*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 3
525*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK    0x1 /* cf4en */
526*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT   4
527*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1 /* cf5en */
528*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_SHIFT          5
529*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
530*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT             6
531*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
532*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT           7
533*14b24e2bSVaishali Kulkarni 	u8 flags3;
534*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
535*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT           0
536*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
537*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT           1
538*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
539*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT           2
540*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
541*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT           3
542*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
543*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT           4
544*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
545*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT           5
546*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
547*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT           6
548*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK            0x1 /* rule8en */
549*14b24e2bSVaishali Kulkarni #define E4_USTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT           7
550*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
551*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
552*14b24e2bSVaishali Kulkarni 	__le16 word0 /* conn_dpi */;
553*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
554*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
555*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
556*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
557*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
558*14b24e2bSVaishali Kulkarni 	__le16 word2 /* word2 */;
559*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
560*14b24e2bSVaishali Kulkarni };
561*14b24e2bSVaishali Kulkarni 
562*14b24e2bSVaishali Kulkarni /*
563*14b24e2bSVaishali Kulkarni  * The toe storm context of Tstorm
564*14b24e2bSVaishali Kulkarni  */
565*14b24e2bSVaishali Kulkarni struct tstorm_toe_conn_st_ctx
566*14b24e2bSVaishali Kulkarni {
567*14b24e2bSVaishali Kulkarni 	__le32 reserved[16];
568*14b24e2bSVaishali Kulkarni };
569*14b24e2bSVaishali Kulkarni 
570*14b24e2bSVaishali Kulkarni /*
571*14b24e2bSVaishali Kulkarni  * The toe storm context of Ustorm
572*14b24e2bSVaishali Kulkarni  */
573*14b24e2bSVaishali Kulkarni struct ustorm_toe_conn_st_ctx
574*14b24e2bSVaishali Kulkarni {
575*14b24e2bSVaishali Kulkarni 	__le32 reserved[52];
576*14b24e2bSVaishali Kulkarni };
577*14b24e2bSVaishali Kulkarni 
578*14b24e2bSVaishali Kulkarni /*
579*14b24e2bSVaishali Kulkarni  * toe connection context
580*14b24e2bSVaishali Kulkarni  */
581*14b24e2bSVaishali Kulkarni struct toe_conn_context
582*14b24e2bSVaishali Kulkarni {
583*14b24e2bSVaishali Kulkarni 	struct ystorm_toe_conn_st_ctx ystorm_st_context /* ystorm storm context */;
584*14b24e2bSVaishali Kulkarni 	struct pstorm_toe_conn_st_ctx pstorm_st_context /* pstorm storm context */;
585*14b24e2bSVaishali Kulkarni 	struct regpair pstorm_st_padding[2] /* padding */;
586*14b24e2bSVaishali Kulkarni 	struct xstorm_toe_conn_st_ctx xstorm_st_context /* xstorm storm context */;
587*14b24e2bSVaishali Kulkarni 	struct regpair xstorm_st_padding[2] /* padding */;
588*14b24e2bSVaishali Kulkarni 	struct e4_ystorm_toe_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
589*14b24e2bSVaishali Kulkarni 	struct e4_xstorm_toe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */;
590*14b24e2bSVaishali Kulkarni 	struct e4_tstorm_toe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
591*14b24e2bSVaishali Kulkarni 	struct regpair tstorm_ag_padding[2] /* padding */;
592*14b24e2bSVaishali Kulkarni 	struct timers_context timer_context /* timer context */;
593*14b24e2bSVaishali Kulkarni 	struct e4_ustorm_toe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
594*14b24e2bSVaishali Kulkarni 	struct tstorm_toe_conn_st_ctx tstorm_st_context /* tstorm storm context */;
595*14b24e2bSVaishali Kulkarni 	struct mstorm_toe_conn_st_ctx mstorm_st_context /* mstorm storm context */;
596*14b24e2bSVaishali Kulkarni 	struct ustorm_toe_conn_st_ctx ustorm_st_context /* ustorm storm context */;
597*14b24e2bSVaishali Kulkarni };
598*14b24e2bSVaishali Kulkarni 
599*14b24e2bSVaishali Kulkarni 
600*14b24e2bSVaishali Kulkarni /*
601*14b24e2bSVaishali Kulkarni  * toe init ramrod header
602*14b24e2bSVaishali Kulkarni  */
603*14b24e2bSVaishali Kulkarni struct toe_init_ramrod_header
604*14b24e2bSVaishali Kulkarni {
605*14b24e2bSVaishali Kulkarni 	u8 first_rss /* First rss in PF */;
606*14b24e2bSVaishali Kulkarni 	u8 num_rss /* Num of rss ids in PF */;
607*14b24e2bSVaishali Kulkarni 	u8 reserved[6];
608*14b24e2bSVaishali Kulkarni };
609*14b24e2bSVaishali Kulkarni 
610*14b24e2bSVaishali Kulkarni /*
611*14b24e2bSVaishali Kulkarni  * toe pf init parameters
612*14b24e2bSVaishali Kulkarni  */
613*14b24e2bSVaishali Kulkarni struct toe_pf_init_params
614*14b24e2bSVaishali Kulkarni {
615*14b24e2bSVaishali Kulkarni 	__le32 push_timeout /* push timer timeout in miliseconds */;
616*14b24e2bSVaishali Kulkarni 	__le16 grq_buffer_size /* GRQ buffer size in bytes */;
617*14b24e2bSVaishali Kulkarni 	__le16 grq_sb_id /* GRQ status block id */;
618*14b24e2bSVaishali Kulkarni 	u8 grq_sb_index /* GRQ status block index */;
619*14b24e2bSVaishali Kulkarni 	u8 max_seg_retransmit /* Maximum number of retransmits for one segment */;
620*14b24e2bSVaishali Kulkarni 	u8 doubt_reachability /* Doubt reachability threshold */;
621*14b24e2bSVaishali Kulkarni 	u8 ll2_rx_queue_id /* Queue ID of the Light-L2 Rx Queue */;
622*14b24e2bSVaishali Kulkarni 	__le16 grq_fetch_threshold /* when passing this threshold, firmware will sync the driver with grq consumer */;
623*14b24e2bSVaishali Kulkarni 	u8 reserved1[2];
624*14b24e2bSVaishali Kulkarni 	struct regpair grq_page_addr /* Address of the first page in the grq ring */;
625*14b24e2bSVaishali Kulkarni };
626*14b24e2bSVaishali Kulkarni 
627*14b24e2bSVaishali Kulkarni /*
628*14b24e2bSVaishali Kulkarni  * toe tss parameters
629*14b24e2bSVaishali Kulkarni  */
630*14b24e2bSVaishali Kulkarni struct toe_tss_params
631*14b24e2bSVaishali Kulkarni {
632*14b24e2bSVaishali Kulkarni 	struct regpair curr_page_addr /* Address of the current page in the tx cq ring */;
633*14b24e2bSVaishali Kulkarni 	struct regpair next_page_addr /* Address of the next page in the tx cq ring */;
634*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* Status block id */;
635*14b24e2bSVaishali Kulkarni 	u8 status_block_index /* Status block index */;
636*14b24e2bSVaishali Kulkarni 	__le16 status_block_id /* Status block id */;
637*14b24e2bSVaishali Kulkarni 	__le16 reserved1[2];
638*14b24e2bSVaishali Kulkarni };
639*14b24e2bSVaishali Kulkarni 
640*14b24e2bSVaishali Kulkarni /*
641*14b24e2bSVaishali Kulkarni  * toe rss parameters
642*14b24e2bSVaishali Kulkarni  */
643*14b24e2bSVaishali Kulkarni struct toe_rss_params
644*14b24e2bSVaishali Kulkarni {
645*14b24e2bSVaishali Kulkarni 	struct regpair curr_page_addr /* Address of the current page in the rx cq ring */;
646*14b24e2bSVaishali Kulkarni 	struct regpair next_page_addr /* Address of the next page in the rx cq ring */;
647*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* Status block id */;
648*14b24e2bSVaishali Kulkarni 	u8 status_block_index /* Status block index */;
649*14b24e2bSVaishali Kulkarni 	__le16 status_block_id /* Status block id */;
650*14b24e2bSVaishali Kulkarni 	__le16 reserved1[2];
651*14b24e2bSVaishali Kulkarni };
652*14b24e2bSVaishali Kulkarni 
653*14b24e2bSVaishali Kulkarni /*
654*14b24e2bSVaishali Kulkarni  * toe init ramrod data
655*14b24e2bSVaishali Kulkarni  */
656*14b24e2bSVaishali Kulkarni struct toe_init_ramrod_data
657*14b24e2bSVaishali Kulkarni {
658*14b24e2bSVaishali Kulkarni 	struct toe_init_ramrod_header hdr;
659*14b24e2bSVaishali Kulkarni 	struct tcp_init_params tcp_params;
660*14b24e2bSVaishali Kulkarni 	struct toe_pf_init_params pf_params;
661*14b24e2bSVaishali Kulkarni 	struct toe_tss_params tss_params[TOE_TX_MAX_TSS_CHAINS];
662*14b24e2bSVaishali Kulkarni 	struct toe_rss_params rss_params[TOE_RX_MAX_RSS_CHAINS];
663*14b24e2bSVaishali Kulkarni };
664*14b24e2bSVaishali Kulkarni 
665*14b24e2bSVaishali Kulkarni 
666*14b24e2bSVaishali Kulkarni 
667*14b24e2bSVaishali Kulkarni /*
668*14b24e2bSVaishali Kulkarni  * toe offload parameters
669*14b24e2bSVaishali Kulkarni  */
670*14b24e2bSVaishali Kulkarni struct toe_offload_params
671*14b24e2bSVaishali Kulkarni {
672*14b24e2bSVaishali Kulkarni 	struct regpair tx_bd_page_addr /* Tx Bd page address */;
673*14b24e2bSVaishali Kulkarni 	struct regpair tx_app_page_addr /* Tx App page address */;
674*14b24e2bSVaishali Kulkarni 	struct regpair rx_bd_page_addr /* Rx Bd page address */;
675*14b24e2bSVaishali Kulkarni 	__le32 more_to_send_seq /* Last byte in bd prod (not including fin) */;
676*14b24e2bSVaishali Kulkarni 	__le16 tx_app_prod /* Producer of application buffer ring */;
677*14b24e2bSVaishali Kulkarni 	__le16 rcv_indication_size /* Recieve indication threshold */;
678*14b24e2bSVaishali Kulkarni 	__le16 reserved;
679*14b24e2bSVaishali Kulkarni 	u8 rss_tss_id /* RSS/TSS absolute id */;
680*14b24e2bSVaishali Kulkarni 	u8 ignore_grq_push;
681*14b24e2bSVaishali Kulkarni 	struct regpair rx_db_data_ptr;
682*14b24e2bSVaishali Kulkarni 	__le32 reserved1;
683*14b24e2bSVaishali Kulkarni };
684*14b24e2bSVaishali Kulkarni 
685*14b24e2bSVaishali Kulkarni 
686*14b24e2bSVaishali Kulkarni /*
687*14b24e2bSVaishali Kulkarni  * TOE offload ramrod data - DMAed by firmware
688*14b24e2bSVaishali Kulkarni  */
689*14b24e2bSVaishali Kulkarni struct toe_offload_ramrod_data
690*14b24e2bSVaishali Kulkarni {
691*14b24e2bSVaishali Kulkarni 	struct tcp_offload_params tcp_ofld_params;
692*14b24e2bSVaishali Kulkarni 	struct toe_offload_params toe_ofld_params;
693*14b24e2bSVaishali Kulkarni };
694*14b24e2bSVaishali Kulkarni 
695*14b24e2bSVaishali Kulkarni 
696*14b24e2bSVaishali Kulkarni 
697*14b24e2bSVaishali Kulkarni /*
698*14b24e2bSVaishali Kulkarni  * TOE ramrod command IDs
699*14b24e2bSVaishali Kulkarni  */
700*14b24e2bSVaishali Kulkarni enum toe_ramrod_cmd_id
701*14b24e2bSVaishali Kulkarni {
702*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_UNUSED,
703*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_FUNC_INIT,
704*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_INITATE_OFFLOAD,
705*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_FUNC_CLOSE,
706*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_SEARCHER_DELETE,
707*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_TERMINATE,
708*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_QUERY,
709*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_UPDATE,
710*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_EMPTY,
711*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_RESET_SEND,
712*14b24e2bSVaishali Kulkarni 	TOE_RAMROD_INVALIDATE,
713*14b24e2bSVaishali Kulkarni 	MAX_TOE_RAMROD_CMD_ID
714